From fbad6c24396b265d4e19cc78aef9b1c7e7e6de64 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 19 Feb 2017 14:19:02 +0100 Subject: spi: spi-fsl-dspi: Fix error handling According to error handling in this function, it is likely that going to 'out_master_put' was expected here. Signed-off-by: Christophe JAILLET Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 14c8e7ce1913..15201645bdc4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1002,7 +1002,8 @@ static int dspi_probe(struct platform_device *pdev) if (IS_ERR(dspi->regmap)) { dev_err(&pdev->dev, "failed to init regmap: %ld\n", PTR_ERR(dspi->regmap)); - return PTR_ERR(dspi->regmap); + ret = PTR_ERR(dspi->regmap); + goto out_master_put; } dspi_init(dspi); -- cgit v1.2.3-58-ga151 From a5b0443c9bf42173f0847889d880a45de67e0f8f Mon Sep 17 00:00:00 2001 From: kbuild test robot Date: Mon, 20 Feb 2017 01:33:10 +0800 Subject: spi: lantiq-ssc: fix platform_no_drv_owner.cocci warnings drivers/spi/spi-lantiq-ssc.c:973:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Fengguang Wu Acked-by: Hauke Mehrtens Signed-off-by: Mark Brown --- drivers/spi/spi-lantiq-ssc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c index 8a626f7fccea..fe3986fa2f23 100644 --- a/drivers/spi/spi-lantiq-ssc.c +++ b/drivers/spi/spi-lantiq-ssc.c @@ -970,7 +970,6 @@ static struct platform_driver lantiq_ssc_driver = { .remove = lantiq_ssc_remove, .driver = { .name = "spi-lantiq-ssc", - .owner = THIS_MODULE, .of_match_table = lantiq_ssc_match, }, }; -- cgit v1.2.3-58-ga151 From 0135c03df914f0481c61f097c78d37cece84f330 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Mon, 20 Feb 2017 11:50:09 +0100 Subject: spi/bcm63xx: make spi subsystem aware of message size limits The bcm63xx SPI controller does not allow manual control of the CS lines and will toggle it automatically before and after sending data, so we are limited to messages that fit in the FIFO buffer. Since the CS lines aren't available as GPIOs either, we will need to make slave drivers aware of this limitation so they can handle them accordingly. Signed-off-by: Jonas Gorski Signed-off-by: Mark Brown --- drivers/spi/spi-bcm63xx.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index fee747030ee6..caa733ec405c 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -428,6 +428,13 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } +static size_t bcm63xx_spi_max_length(struct spi_device *dev) +{ + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); + + return bs->fifo_size; +} + static const unsigned long bcm6348_spi_reg_offsets[] = { [SPI_CMD] = SPI_6348_CMD, [SPI_INT_STATUS] = SPI_6348_INT_STATUS, @@ -541,6 +548,8 @@ static int bcm63xx_spi_probe(struct platform_device *pdev) master->transfer_one_message = bcm63xx_spi_transfer_one; master->mode_bits = MODEBITS; master->bits_per_word_mask = SPI_BPW_MASK(8); + master->max_transfer_size = bcm63xx_spi_max_length; + master->max_message_size = bcm63xx_spi_max_length; master->auto_runtime_pm = true; bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; -- cgit v1.2.3-58-ga151 From c29f08890ae337e398becf5ba586114553e99771 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 21 Feb 2017 11:58:22 +0100 Subject: spi/bcm63xx: allow for probing through devicetree Add required binding support to probe through device tree. Use the compatible instead of the resource size for identifiying the block type, and allow reducing the number of cs lines through OF. Signed-off-by: Jonas Gorski Signed-off-by: Mark Brown --- drivers/spi/spi-bcm63xx.c | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index caa733ec405c..325131370941 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -26,6 +26,7 @@ #include #include #include +#include /* BCM 6338/6348 SPI core */ #define SPI_6348_RSET_SIZE 64 @@ -484,21 +485,48 @@ static const struct platform_device_id bcm63xx_spi_dev_match[] = { }, }; +static const struct of_device_id bcm63xx_spi_of_match[] = { + { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets }, + { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets }, + { }, +}; + static int bcm63xx_spi_probe(struct platform_device *pdev) { struct resource *r; const unsigned long *bcm63xx_spireg; struct device *dev = &pdev->dev; - int irq; + int irq, bus_num; struct spi_master *master; struct clk *clk; struct bcm63xx_spi *bs; int ret; + u32 num_cs = BCM63XX_SPI_MAX_CS; - if (!pdev->id_entry->driver_data) - return -EINVAL; + if (dev->of_node) { + const struct of_device_id *match; - bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data; + match = of_match_node(bcm63xx_spi_of_match, dev->of_node); + if (!match) + return -EINVAL; + bcm63xx_spireg = match->data; + + of_property_read_u32(dev->of_node, "num-cs", &num_cs); + if (num_cs > BCM63XX_SPI_MAX_CS) { + dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", + num_cs); + num_cs = BCM63XX_SPI_MAX_CS; + } + + bus_num = -1; + } else if (pdev->id_entry->driver_data) { + const struct platform_device_id *match = pdev->id_entry; + + bcm63xx_spireg = (const unsigned long *)match->driver_data; + bus_num = BCM63XX_SPI_BUS_NUM; + } else { + return -EINVAL; + } irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -543,8 +571,9 @@ static int bcm63xx_spi_probe(struct platform_device *pdev) goto out_err; } - master->bus_num = BCM63XX_SPI_BUS_NUM; - master->num_chipselect = BCM63XX_SPI_MAX_CS; + master->dev.of_node = dev->of_node; + master->bus_num = bus_num; + master->num_chipselect = num_cs; master->transfer_one_message = bcm63xx_spi_transfer_one; master->mode_bits = MODEBITS; master->bits_per_word_mask = SPI_BPW_MASK(8); @@ -633,6 +662,7 @@ static struct platform_driver bcm63xx_spi_driver = { .driver = { .name = "bcm63xx-spi", .pm = &bcm63xx_spi_pm_ops, + .of_match_table = bcm63xx_spi_of_match, }, .id_table = bcm63xx_spi_dev_match, .probe = bcm63xx_spi_probe, -- cgit v1.2.3-58-ga151 From ccd0657c33b2c3701c5b14725284b7e671d3fb93 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Wed, 22 Feb 2017 00:30:40 +0100 Subject: spi/bcm63xx: fix typo in bcm63xx_spi_max_length breaking compilation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix compilation by renaming argument dev to spi as expected by the code. Fixes the following error: drivers/spi/spi-bcm63xx.c: In function ‘bcm63xx_spi_max_length’: drivers/spi/spi-bcm63xx.c:434:50: error: ‘spi’ undeclared (first use in this function) struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); ^~~ Fixes: 0135c03df914 ("spi/bcm63xx: make spi subsystem aware of message size limits") Signed-off-by: Jonas Gorski Signed-off-by: Mark Brown --- drivers/spi/spi-bcm63xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index 325131370941..247f71b02235 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -429,7 +429,7 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static size_t bcm63xx_spi_max_length(struct spi_device *dev) +static size_t bcm63xx_spi_max_length(struct spi_device *spi) { struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); -- cgit v1.2.3-58-ga151 From 68c97b92c0a0dfdc134564f1f1c04b1c8ed27bba Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 22 Feb 2017 15:14:20 -0300 Subject: spi: sc18is602: Add OF device ID table The driver doesn't have a struct of_device_id table but supported devices are registered via Device Trees. This is working on the assumption that a I2C device registered via OF will always match a legacy I2C device ID and that the MODALIAS reported will always be of the form i2c:. But this could change in the future so the correct approach is to have an OF device ID table if the devices are registered via OF. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- drivers/spi/spi-sc18is602.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c index f63714ffb62f..52cf0e9189c2 100644 --- a/drivers/spi/spi-sc18is602.c +++ b/drivers/spi/spi-sc18is602.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -271,7 +272,10 @@ static int sc18is602_probe(struct i2c_client *client, hw->dev = dev; hw->ctrl = 0xff; - hw->id = id->driver_data; + if (client->dev.of_node) + hw->id = (enum chips)of_device_get_match_data(&client->dev); + else + hw->id = id->driver_data; switch (hw->id) { case sc18is602: @@ -323,9 +327,27 @@ static const struct i2c_device_id sc18is602_id[] = { }; MODULE_DEVICE_TABLE(i2c, sc18is602_id); +static const struct of_device_id sc18is602_of_match[] = { + { + .compatible = "nxp,sc18is602", + .data = (void *)sc18is602 + }, + { + .compatible = "nxp,sc18is602b", + .data = (void *)sc18is602b + }, + { + .compatible = "nxp,sc18is603", + .data = (void *)sc18is603 + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sc18is602_of_match); + static struct i2c_driver sc18is602_driver = { .driver = { .name = "sc18is602", + .of_match_table = of_match_ptr(sc18is602_of_match), }, .probe = sc18is602_probe, .id_table = sc18is602_id, -- cgit v1.2.3-58-ga151 From ad2fca0721d1376c1689d909fdfcf5d7e240dac7 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 27 Feb 2017 23:21:25 +0100 Subject: spi: lantiq-ssc: add LTQ_ prefix to defines The blackfin architecture has a SPI_STAT define which conflicts with the define from the spi-lantiq-ssc driver in compile test mode. Fix this by adding a prefix in front of every define. Reported-by: kbuild test robot Signed-off-by: Hauke Mehrtens Signed-off-by: Mark Brown --- drivers/spi/spi-lantiq-ssc.c | 437 ++++++++++++++++++++++--------------------- 1 file changed, 222 insertions(+), 215 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c index 8a626f7fccea..633c30b4d5a6 100644 --- a/drivers/spi/spi-lantiq-ssc.c +++ b/drivers/spi/spi-lantiq-ssc.c @@ -26,136 +26,140 @@ #include #endif -#define SPI_RX_IRQ_NAME "spi_rx" -#define SPI_TX_IRQ_NAME "spi_tx" -#define SPI_ERR_IRQ_NAME "spi_err" -#define SPI_FRM_IRQ_NAME "spi_frm" - -#define SPI_CLC 0x00 -#define SPI_PISEL 0x04 -#define SPI_ID 0x08 -#define SPI_CON 0x10 -#define SPI_STAT 0x14 -#define SPI_WHBSTATE 0x18 -#define SPI_TB 0x20 -#define SPI_RB 0x24 -#define SPI_RXFCON 0x30 -#define SPI_TXFCON 0x34 -#define SPI_FSTAT 0x38 -#define SPI_BRT 0x40 -#define SPI_BRSTAT 0x44 -#define SPI_SFCON 0x60 -#define SPI_SFSTAT 0x64 -#define SPI_GPOCON 0x70 -#define SPI_GPOSTAT 0x74 -#define SPI_FPGO 0x78 -#define SPI_RXREQ 0x80 -#define SPI_RXCNT 0x84 -#define SPI_DMACON 0xec -#define SPI_IRNEN 0xf4 -#define SPI_IRNICR 0xf8 -#define SPI_IRNCR 0xfc - -#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ -#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) -#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ -#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) -#define SPI_CLC_DISS BIT(1) /* Disable status bit */ -#define SPI_CLC_DISR BIT(0) /* Disable request bit */ - -#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ -#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) -#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ -#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) -#define SPI_ID_MOD_S 8 /* Module ID */ -#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) -#define SPI_ID_CFG_S 5 /* DMA interface support */ -#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) -#define SPI_ID_REV_M 0x1F /* Hardware revision number */ - -#define SPI_CON_BM_S 16 /* Data width selection */ -#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) -#define SPI_CON_EM BIT(24) /* Echo mode */ -#define SPI_CON_IDLE BIT(23) /* Idle bit value */ -#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ -#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ -#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ -#define SPI_CON_AEN BIT(10) /* Abort error enable */ -#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ -#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ -#define SPI_CON_LB BIT(7) /* Loopback control */ -#define SPI_CON_PO BIT(6) /* Clock polarity control */ -#define SPI_CON_PH BIT(5) /* Clock phase control */ -#define SPI_CON_HB BIT(4) /* Heading control */ -#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ -#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ - -#define SPI_STAT_RXBV_S 28 -#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) -#define SPI_STAT_BSY BIT(13) /* Busy flag */ -#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ -#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ -#define SPI_STAT_AE BIT(10) /* Abort error flag */ -#define SPI_STAT_RE BIT(9) /* Receive error flag */ -#define SPI_STAT_TE BIT(8) /* Transmit error flag */ -#define SPI_STAT_ME BIT(7) /* Mode error flag */ -#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ -#define SPI_STAT_EN BIT(0) /* Enable bit */ -#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ - SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) - -#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ -#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ -#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ -#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ -#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ -#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ -#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ -#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ -#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ -#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ -#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ -#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ -#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ -#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ -#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ -#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ -#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ - SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ - SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) - -#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ -#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) -#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ -#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ - -#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ -#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) -#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ -#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ - -#define SPI_FSTAT_RXFFL_S 0 -#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) -#define SPI_FSTAT_TXFFL_S 8 -#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) - -#define SPI_GPOCON_ISCSBN_S 8 -#define SPI_GPOCON_INVOUTN_S 0 - -#define SPI_FGPO_SETOUTN_S 8 -#define SPI_FGPO_CLROUTN_S 0 - -#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ -#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ - -#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ -#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ -#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ -#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ -#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ -#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ -#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ -#define SPI_IRNEN_ALL 0x1F +#define LTQ_SPI_RX_IRQ_NAME "spi_rx" +#define LTQ_SPI_TX_IRQ_NAME "spi_tx" +#define LTQ_SPI_ERR_IRQ_NAME "spi_err" +#define LTQ_SPI_FRM_IRQ_NAME "spi_frm" + +#define LTQ_SPI_CLC 0x00 +#define LTQ_SPI_PISEL 0x04 +#define LTQ_SPI_ID 0x08 +#define LTQ_SPI_CON 0x10 +#define LTQ_SPI_STAT 0x14 +#define LTQ_SPI_WHBSTATE 0x18 +#define LTQ_SPI_TB 0x20 +#define LTQ_SPI_RB 0x24 +#define LTQ_SPI_RXFCON 0x30 +#define LTQ_SPI_TXFCON 0x34 +#define LTQ_SPI_FSTAT 0x38 +#define LTQ_SPI_BRT 0x40 +#define LTQ_SPI_BRSTAT 0x44 +#define LTQ_SPI_SFCON 0x60 +#define LTQ_SPI_SFSTAT 0x64 +#define LTQ_SPI_GPOCON 0x70 +#define LTQ_SPI_GPOSTAT 0x74 +#define LTQ_SPI_FPGO 0x78 +#define LTQ_SPI_RXREQ 0x80 +#define LTQ_SPI_RXCNT 0x84 +#define LTQ_SPI_DMACON 0xec +#define LTQ_SPI_IRNEN 0xf4 +#define LTQ_SPI_IRNICR 0xf8 +#define LTQ_SPI_IRNCR 0xfc + +#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ +#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S) +#define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ +#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S) +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ + +#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ +#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S) +#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ +#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S) +#define LTQ_SPI_ID_MOD_S 8 /* Module ID */ +#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S) +#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */ +#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S) +#define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */ + +#define LTQ_SPI_CON_BM_S 16 /* Data width selection */ +#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S) +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ + +#define LTQ_SPI_STAT_RXBV_S 28 +#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S) +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ +#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ +#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \ + LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \ + LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE) + +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ +#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \ + LTQ_SPI_WHBSTATE_CLRME | \ + LTQ_SPI_WHBSTATE_CLRTE | \ + LTQ_SPI_WHBSTATE_CLRRE | \ + LTQ_SPI_WHBSTATE_CLRAE | \ + LTQ_SPI_WHBSTATE_CLRTUE) + +#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S) +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S) +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_FSTAT_RXFFL_S 0 +#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S) +#define LTQ_SPI_FSTAT_TXFFL_S 8 +#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S) + +#define LTQ_SPI_GPOCON_ISCSBN_S 8 +#define LTQ_SPI_GPOCON_INVOUTN_S 0 + +#define LTQ_SPI_FGPO_SETOUTN_S 8 +#define LTQ_SPI_FGPO_CLROUTN_S 0 + +#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ +#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ + +#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ +#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ +#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ +#define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ +#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ +#define LTQ_SPI_IRNEN_ALL 0x1F struct lantiq_ssc_hwcfg { unsigned int irnen_r; @@ -208,16 +212,16 @@ static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) { - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; + return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S; } static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) { - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - return fstat & SPI_FSTAT_RXFFL_M; + return fstat & LTQ_SPI_FSTAT_RXFFL_M; } static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) @@ -227,38 +231,38 @@ static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) { - u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; + u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; - val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; - lantiq_ssc_writel(spi, val, SPI_RXFCON); + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; + lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); } static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) { - u32 val = 1 << SPI_TXFCON_TXFITL_S; + u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; - val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; - lantiq_ssc_writel(spi, val, SPI_TXFCON); + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; + lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); } static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); } static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); } static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); } static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); } static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, @@ -287,7 +291,7 @@ static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", spi_clk, max_speed_hz, brt); - lantiq_ssc_writel(spi, brt, SPI_BRT); + lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); } static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, @@ -296,9 +300,9 @@ static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, u32 bm; /* CON.BM value = bits_per_word - 1 */ - bm = (bits_per_word - 1) << SPI_CON_BM_S; + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; - lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); + lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); } static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, @@ -315,28 +319,28 @@ static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, * 3 1 1 1 0 */ if (mode & SPI_CPHA) - con_clr |= SPI_CON_PH; + con_clr |= LTQ_SPI_CON_PH; else - con_set |= SPI_CON_PH; + con_set |= LTQ_SPI_CON_PH; if (mode & SPI_CPOL) - con_set |= SPI_CON_PO | SPI_CON_IDLE; + con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; else - con_clr |= SPI_CON_PO | SPI_CON_IDLE; + con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; /* Set heading control */ if (mode & SPI_LSB_FIRST) - con_clr |= SPI_CON_HB; + con_clr |= LTQ_SPI_CON_HB; else - con_set |= SPI_CON_HB; + con_set |= LTQ_SPI_CON_HB; /* Set loopback mode */ if (mode & SPI_LOOP) - con_set |= SPI_CON_LB; + con_set |= LTQ_SPI_CON_LB; else - con_clr |= SPI_CON_LB; + con_clr |= LTQ_SPI_CON_LB; - lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); + lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); } static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) @@ -347,37 +351,39 @@ static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) * Set clock divider for run mode to 1 to * run at same frequency as FPI bus */ - lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); + lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); /* Put controller into config mode */ hw_enter_config_mode(spi); /* Clear error flags */ - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); /* Enable error checking, disable TX/RX */ - lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | - SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | + LTQ_SPI_CON_RXOFF, LTQ_SPI_CON); /* Setup default SPI mode */ hw_setup_bits_per_word(spi, spi->bits_per_word); hw_setup_clock_mode(spi, SPI_MODE_0); /* Enable master mode and clear error flags */ - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, - SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | + LTQ_SPI_WHBSTATE_CLR_ERRORS, + LTQ_SPI_WHBSTATE); /* Reset GPIO/CS registers */ - lantiq_ssc_writel(spi, 0, SPI_GPOCON); - lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); + lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); + lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); /* Enable and flush FIFOs */ rx_fifo_reset(spi); tx_fifo_reset(spi); /* Enable interrupts */ - lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, - SPI_IRNEN); + lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | + LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); } static int lantiq_ssc_setup(struct spi_device *spidev) @@ -400,13 +406,13 @@ static int lantiq_ssc_setup(struct spi_device *spidev) } /* set GPO pin to CS mode */ - gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); + gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); /* invert GPO pin */ if (spidev->mode & SPI_CS_HIGH) gpocon |= 1 << (cs - spi->base_cs); - lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); + lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); return 0; } @@ -442,18 +448,18 @@ static void hw_setup_transfer(struct lantiq_ssc_spi *spi, } /* Configure transmitter and receiver */ - con = lantiq_ssc_readl(spi, SPI_CON); + con = lantiq_ssc_readl(spi, LTQ_SPI_CON); if (t->tx_buf) - con &= ~SPI_CON_TXOFF; + con &= ~LTQ_SPI_CON_TXOFF; else - con |= SPI_CON_TXOFF; + con |= LTQ_SPI_CON_TXOFF; if (t->rx_buf) - con &= ~SPI_CON_RXOFF; + con &= ~LTQ_SPI_CON_RXOFF; else - con |= SPI_CON_RXOFF; + con |= LTQ_SPI_CON_RXOFF; - lantiq_ssc_writel(spi, con, SPI_CON); + lantiq_ssc_writel(spi, con, LTQ_SPI_CON); } static int lantiq_ssc_unprepare_message(struct spi_master *master, @@ -464,7 +470,8 @@ static int lantiq_ssc_unprepare_message(struct spi_master *master, flush_workqueue(spi->wq); /* Disable transmitter and receiver while idle */ - lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, + LTQ_SPI_CON); return 0; } @@ -503,7 +510,7 @@ static void tx_fifo_write(struct lantiq_ssc_spi *spi) break; } - lantiq_ssc_writel(spi, data, SPI_TB); + lantiq_ssc_writel(spi, data, LTQ_SPI_TB); tx_free--; } } @@ -517,7 +524,7 @@ static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) unsigned int rx_fill = rx_fifo_level(spi); while (rx_fill) { - data = lantiq_ssc_readl(spi, SPI_RB); + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); switch (spi->bits_per_word) { case 2 ... 8: @@ -563,9 +570,9 @@ static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) */ while (rx_fill) { if (spi->rx_todo < 4) { - rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & - SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; - data = lantiq_ssc_readl(spi, SPI_RB); + rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & + LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S; + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); shift = (rxbv - 1) * 8; rx8 = spi->rx; @@ -578,7 +585,7 @@ static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) spi->rx++; } } else { - data = lantiq_ssc_readl(spi, SPI_RB); + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); rx32 = (u32 *) spi->rx; *rx32++ = data; @@ -603,7 +610,7 @@ static void rx_request(struct lantiq_ssc_spi *spi) if (rxreq > rxreq_max) rxreq = rxreq_max; - lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); + lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); } static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) @@ -642,26 +649,26 @@ completed: static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) { struct lantiq_ssc_spi *spi = data; - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - if (!(stat & SPI_STAT_ERRORS)) + if (!(stat & LTQ_SPI_STAT_ERRORS)) return IRQ_NONE; - if (stat & SPI_STAT_RUE) + if (stat & LTQ_SPI_STAT_RUE) dev_err(spi->dev, "receive underflow error\n"); - if (stat & SPI_STAT_TUE) + if (stat & LTQ_SPI_STAT_TUE) dev_err(spi->dev, "transmit underflow error\n"); - if (stat & SPI_STAT_AE) + if (stat & LTQ_SPI_STAT_AE) dev_err(spi->dev, "abort error\n"); - if (stat & SPI_STAT_RE) + if (stat & LTQ_SPI_STAT_RE) dev_err(spi->dev, "receive overflow error\n"); - if (stat & SPI_STAT_TE) + if (stat & LTQ_SPI_STAT_TE) dev_err(spi->dev, "transmit overflow error\n"); - if (stat & SPI_STAT_ME) + if (stat & LTQ_SPI_STAT_ME) dev_err(spi->dev, "mode error\n"); /* Clear error flags */ - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); /* set bad status so it can be retried */ if (spi->master->cur_msg) @@ -721,9 +728,9 @@ static void lantiq_ssc_bussy_work(struct work_struct *work) end = jiffies + msecs_to_jiffies(timeout); do { - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - if (!(stat & SPI_STAT_BSY)) { + if (!(stat & LTQ_SPI_STAT_BSY)) { spi_finalize_current_transfer(spi->master); return; } @@ -755,9 +762,9 @@ static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) if (!!(spidev->mode & SPI_CS_HIGH) == enable) fgpo = (1 << (cs - spi->base_cs)); else - fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); + fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); - lantiq_ssc_writel(spi, fgpo, SPI_FPGO); + lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); } static int lantiq_ssc_transfer_one(struct spi_master *master, @@ -772,13 +779,13 @@ static int lantiq_ssc_transfer_one(struct spi_master *master, } static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { - .irnen_r = SPI_IRNEN_R_XWAY, - .irnen_t = SPI_IRNEN_T_XWAY, + .irnen_r = LTQ_SPI_IRNEN_R_XWAY, + .irnen_t = LTQ_SPI_IRNEN_T_XWAY, }; static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { - .irnen_r = SPI_IRNEN_R_XRX, - .irnen_t = SPI_IRNEN_T_XRX, + .irnen_r = LTQ_SPI_IRNEN_R_XRX, + .irnen_t = LTQ_SPI_IRNEN_T_XRX, }; static const struct of_device_id lantiq_ssc_match[] = { @@ -814,21 +821,21 @@ static int lantiq_ssc_probe(struct platform_device *pdev) return -ENXIO; } - rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); + rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); if (rx_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME); return -ENXIO; } - tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); + tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); if (tx_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME); return -ENXIO; } - err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); + err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); if (err_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME); return -ENXIO; } @@ -849,17 +856,17 @@ static int lantiq_ssc_probe(struct platform_device *pdev) } err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, - 0, SPI_RX_IRQ_NAME, spi); + 0, LTQ_SPI_RX_IRQ_NAME, spi); if (err) goto err_master_put; err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, - 0, SPI_TX_IRQ_NAME, spi); + 0, LTQ_SPI_TX_IRQ_NAME, spi); if (err) goto err_master_put; err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, - 0, SPI_ERR_IRQ_NAME, spi); + 0, LTQ_SPI_ERR_IRQ_NAME, spi); if (err) goto err_master_put; @@ -916,11 +923,11 @@ static int lantiq_ssc_probe(struct platform_device *pdev) } INIT_WORK(&spi->work, lantiq_ssc_bussy_work); - id = lantiq_ssc_readl(spi, SPI_ID); - spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; - spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; - supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; - revision = id & SPI_ID_REV_M; + id = lantiq_ssc_readl(spi, LTQ_SPI_ID); + spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S; + spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S; + supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S; + revision = id & LTQ_SPI_ID_REV_M; lantiq_ssc_hw_init(spi); @@ -952,8 +959,8 @@ static int lantiq_ssc_remove(struct platform_device *pdev) { struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); - lantiq_ssc_writel(spi, 0, SPI_IRNEN); - lantiq_ssc_writel(spi, 0, SPI_CLC); + lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); + lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); rx_fifo_flush(spi); tx_fifo_flush(spi); hw_enter_config_mode(spi); -- cgit v1.2.3-58-ga151 From 826cf175ed705f70a49d04aca832c1cc9ff048d8 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 28 Feb 2017 14:25:18 -0800 Subject: spi: allow attaching device properties to SPI board info Generic device properties support statically defined property sets. For them to be usable, we need to attach these property sets before devices are registered and probed. Allowing to attach property list to spi_board_info structure will allow non-ACPI non-DT boards switch to using generic properties and get rid of custom platform data. Signed-off-by: Dmitry Torokhov Signed-off-by: Mark Brown --- drivers/spi/spi.c | 32 ++++++++++++++++++++++++++++---- include/linux/spi/spi.h | 4 ++++ 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 90b5b2efafbf..6cc86060d22f 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -600,13 +601,28 @@ struct spi_device *spi_new_device(struct spi_master *master, proxy->controller_data = chip->controller_data; proxy->controller_state = NULL; - status = spi_add_device(proxy); - if (status < 0) { - spi_dev_put(proxy); - return NULL; + if (chip->properties) { + status = device_add_properties(&proxy->dev, chip->properties); + if (status) { + dev_err(&master->dev, + "failed to add properties to '%s': %d\n", + chip->modalias, status); + goto err_dev_put; + } } + status = spi_add_device(proxy); + if (status < 0) + goto err_remove_props; + return proxy; + +err_remove_props: + if (chip->properties) + device_remove_properties(&proxy->dev); +err_dev_put: + spi_dev_put(proxy); + return NULL; } EXPORT_SYMBOL_GPL(spi_new_device); @@ -664,6 +680,7 @@ static void spi_match_master_to_boardinfo(struct spi_master *master, * * The board info passed can safely be __initdata ... but be careful of * any embedded pointers (platform_data, etc), they're copied as-is. + * Device properties are deep-copied though. * * Return: zero on success, else a negative error code. */ @@ -683,6 +700,13 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) struct spi_master *master; memcpy(&bi->board_info, info, sizeof(*info)); + if (info->properties) { + bi->board_info.properties = + property_entries_dup(info->properties); + if (IS_ERR(bi->board_info.properties)) + return PTR_ERR(bi->board_info.properties); + } + mutex_lock(&board_lock); list_add_tail(&bi->list, &board_list); list_for_each_entry(master, &spi_master_list, list) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 75c6bd0ac605..5a8c4b24f2dc 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,7 @@ #include struct dma_chan; +struct property_entry; struct spi_master; struct spi_transfer; struct spi_flash_read_message; @@ -1209,6 +1210,7 @@ int spi_flash_read(struct spi_device *spi, * @modalias: Initializes spi_device.modalias; identifies the driver. * @platform_data: Initializes spi_device.platform_data; the particular * data stored there is driver-specific. + * @properties: Additional device properties for the device. * @controller_data: Initializes spi_device.controller_data; some * controllers need hints about hardware setup, e.g. for DMA. * @irq: Initializes spi_device.irq; depends on how the board is wired. @@ -1241,10 +1243,12 @@ struct spi_board_info { * * platform_data goes to spi_device.dev.platform_data, * controller_data goes to spi_device.controller_data, + * device properties are copied and attached to spi_device, * irq is copied too */ char modalias[SPI_NAME_SIZE]; const void *platform_data; + const struct property_entry *properties; void *controller_data; int irq; -- cgit v1.2.3-58-ga151 From f974cf57b1b95839b224b01335c45347f746a365 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 28 Feb 2017 14:25:19 -0800 Subject: spi: allow registering empty spi_board_info lists Many boards form list of spi_board_info entries depending on config, and it is possible to end up with empty list. Do not report error in such cases. Signed-off-by: Dmitry Torokhov Signed-off-by: Mark Brown --- drivers/spi/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 6cc86060d22f..f699ea530b88 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -690,7 +690,7 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) int i; if (!n) - return -EINVAL; + return 0; bi = kcalloc(n, sizeof(*bi), GFP_KERNEL); if (!bi) -- cgit v1.2.3-58-ga151 From 913f536c6c18a2e19e32f06971101c1d0ae3739c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 6 Mar 2017 20:14:43 +0800 Subject: spi: sun6i: Allow transfers larger than FIFO size The spi-sun6i driver have the same problem that spi-sun4i used to have -- SPI transfers are limited to one FIFO depth. This commit fixes this problem in the same way it's fixed in spi-sun4i. See commit 196737912da5 ("spi: sun4i: Allow transfers larger than FIFO size") for more information. The sun6i SPI controllers features changeable interrupt trigger level, but I set it to 3/4 of fifo depth, as same as the the sun4i SPI controllers. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Mark Brown --- drivers/spi/spi-sun6i.c | 90 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index e3114832c485..6e9ca93db9bf 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -46,13 +46,19 @@ #define SUN6I_TFR_CTL_XCH BIT(31) #define SUN6I_INT_CTL_REG 0x10 +#define SUN6I_INT_CTL_RF_RDY BIT(0) +#define SUN6I_INT_CTL_TF_ERQ BIT(4) #define SUN6I_INT_CTL_RF_OVF BIT(8) #define SUN6I_INT_CTL_TC BIT(12) #define SUN6I_INT_STA_REG 0x14 #define SUN6I_FIFO_CTL_REG 0x18 +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 #define SUN6I_FIFO_CTL_RF_RST BIT(15) +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 #define SUN6I_FIFO_CTL_TF_RST BIT(31) #define SUN6I_FIFO_STA_REG 0x1c @@ -68,14 +74,16 @@ #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) #define SUN6I_CLK_CTL_DRS BIT(12) +#define SUN6I_MAX_XFER_SIZE 0xffffff + #define SUN6I_BURST_CNT_REG 0x30 -#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) +#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) #define SUN6I_XMIT_CNT_REG 0x34 -#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) +#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) #define SUN6I_BURST_CTL_CNT_REG 0x38 -#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) +#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) #define SUN6I_TXDATA_REG 0x200 #define SUN6I_RXDATA_REG 0x300 @@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) writel(value, sspi->base_addr + reg); } +static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) +{ + u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); + + reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; + + return reg & SUN6I_FIFO_STA_TF_CNT_MASK; +} + +static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) +{ + u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); + + reg |= mask; + sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); +} + +static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) +{ + u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); + + reg &= ~mask; + sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); +} + static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) { u32 reg, cnt; @@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) { + u32 cnt; u8 byte; - if (len > sspi->len) - len = sspi->len; + /* See how much data we can fit */ + cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); + + len = min3(len, (int)cnt, sspi->len); while (len--) { byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; @@ -170,12 +206,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master, struct sun6i_spi *sspi = spi_master_get_devdata(master); unsigned int mclk_rate, div, timeout; unsigned int start, end, tx_time; + unsigned int trig_level; unsigned int tx_len = 0; int ret = 0; u32 reg; - /* We don't support transfer larger than the FIFO */ - if (tfr->len > sspi->fifo_depth) + if (tfr->len > SUN6I_MAX_XFER_SIZE) return -EINVAL; reinit_completion(&sspi->done); @@ -190,6 +226,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); + /* + * Setup FIFO interrupt trigger level + * Here we choose 3/4 of the full fifo depth, as it's the hardcoded + * value used in old generation of Allwinner SPI controller. + * (See spi-sun4i.c) + */ + trig_level = sspi->fifo_depth / 4 * 3; + sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, + (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | + (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); + /* * Setup the transfer control register: Chip Select, * polarities, etc. @@ -274,6 +321,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, /* Enable the interrupts */ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); + sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC | + SUN6I_INT_CTL_RF_RDY); + if (tx_len > sspi->fifo_depth) + sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); /* Start the transfer */ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); @@ -293,8 +344,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master, goto out; } - sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); - out: sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); @@ -309,10 +358,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) /* Transfer complete */ if (status & SUN6I_INT_CTL_TC) { sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); + sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); complete(&sspi->done); return IRQ_HANDLED; } + /* Receive FIFO 3/4 full */ + if (status & SUN6I_INT_CTL_RF_RDY) { + sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); + /* Only clear the interrupt _after_ draining the FIFO */ + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); + return IRQ_HANDLED; + } + + /* Transmit FIFO 3/4 empty */ + if (status & SUN6I_INT_CTL_TF_ERQ) { + sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); + + if (!sspi->len) + /* nothing left to transmit */ + sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); + + /* Only clear the interrupt _after_ re-seeding the FIFO */ + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); + + return IRQ_HANDLED; + } + return IRQ_NONE; } -- cgit v1.2.3-58-ga151 From 8aedbf580d21121d2a032e4c8ea12d8d2d85e275 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 23 Feb 2017 19:01:56 +0100 Subject: spi: davinci: Use SPI framework to handle DMA mapping Uppers layers like MTD can pass vmalloc'd buffers to the SPI driver, and the current implementation will fail to map these kind of buffers. The SPI framework is able to detect the best way to handle and map buffers. This commit updates the davinci SPI driver in order to use the SPI framework to handle the DMA mapping of buffers coming from an upper layer. Signed-off-by: Fabien Parent Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 69 +++++++++++++---------------------------------- 1 file changed, 18 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 02fb96797ac8..164cc719be54 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -467,6 +467,19 @@ static void davinci_spi_cleanup(struct spi_device *spi) kfree(spicfg); } +static bool davinci_spi_can_dma(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + struct davinci_spi_config *spicfg = spi->controller_data; + bool can_dma = false; + + if (spicfg) + can_dma = spicfg->io_type == SPI_IO_TYPE_DMA; + + return can_dma; +} + static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) { struct device *sdev = dspi->bitbang.master->dev.parent; @@ -581,8 +594,6 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) struct davinci_spi_config *spicfg; struct davinci_spi_platform_data *pdata; unsigned uninitialized_var(rx_buf_count); - void *dummy_buf = NULL; - struct scatterlist sg_rx, sg_tx; dspi = spi_master_get_devdata(spi->master); pdata = &dspi->pdata; @@ -630,51 +641,18 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) }; struct dma_async_tx_descriptor *rxdesc; struct dma_async_tx_descriptor *txdesc; - void *buf; - - dummy_buf = kzalloc(t->len, GFP_KERNEL); - if (!dummy_buf) - goto err_alloc_dummy_buf; dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); - sg_init_table(&sg_rx, 1); - if (!t->rx_buf) - buf = dummy_buf; - else - buf = t->rx_buf; - t->rx_dma = dma_map_single(&spi->dev, buf, - t->len, DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, !t->rx_dma)) { - ret = -EFAULT; - goto err_rx_map; - } - sg_dma_address(&sg_rx) = t->rx_dma; - sg_dma_len(&sg_rx) = t->len; - - sg_init_table(&sg_tx, 1); - if (!t->tx_buf) - buf = dummy_buf; - else - buf = (void *)t->tx_buf; - t->tx_dma = dma_map_single(&spi->dev, buf, - t->len, DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - ret = -EFAULT; - goto err_tx_map; - } - sg_dma_address(&sg_tx) = t->tx_dma; - sg_dma_len(&sg_tx) = t->len; - rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, - &sg_rx, 1, DMA_DEV_TO_MEM, + t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!rxdesc) goto err_desc; txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, - &sg_tx, 1, DMA_MEM_TO_DEV, + t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!txdesc) goto err_desc; @@ -710,16 +688,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) } clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) { + if (spicfg->io_type == SPI_IO_TYPE_DMA) clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - dma_unmap_single(&spi->dev, t->rx_dma, - t->len, DMA_FROM_DEVICE); - dma_unmap_single(&spi->dev, t->tx_dma, - t->len, DMA_TO_DEVICE); - kfree(dummy_buf); - } - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); @@ -742,12 +713,6 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) return t->len; err_desc: - dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); -err_tx_map: - dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); -err_rx_map: - kfree(dummy_buf); -err_alloc_dummy_buf: return ret; } @@ -988,8 +953,10 @@ static int davinci_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->num_chipselect = pdata->num_chipselect; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); + master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); master->setup = davinci_spi_setup; master->cleanup = davinci_spi_cleanup; + master->can_dma = davinci_spi_can_dma; dspi->bitbang.chipselect = davinci_spi_chipselect; dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; -- cgit v1.2.3-58-ga151 From 3e2e1258443ea97e40dfb4a3cf15108d17939066 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 23 Feb 2017 19:01:57 +0100 Subject: spi: davinci: enable DMA when channels are defined in DT When booting with DT the SPI driver is always using the SPI_IO_TYPE_INTR mode to transfer data even if DMA channels are defined in the DT. This commit changes the behaviour to select the SPI_IO_TYPE_DMA mode if DMA channels are defined in the DT and will keep SPI_IO_TYPE_INTR if the channels are not defined in it. Signed-off-by: Fabien Parent Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 164cc719be54..1e24395a04f2 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -389,6 +389,7 @@ static int davinci_spi_of_setup(struct spi_device *spi) { struct davinci_spi_config *spicfg = spi->controller_data; struct device_node *np = spi->dev.of_node; + struct davinci_spi *dspi = spi_master_get_devdata(spi->master); u32 prop; if (spicfg == NULL && np) { @@ -400,6 +401,9 @@ static int davinci_spi_of_setup(struct spi_device *spi) if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) spicfg->wdelay = (u8)prop; spi->controller_data = spicfg; + + if (dspi->dma_rx && dspi->dma_tx) + spicfg->io_type = SPI_IO_TYPE_DMA; } return 0; -- cgit v1.2.3-58-ga151 From ff18e1ef04e2073889569b07a5ddd54a6527917f Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Wed, 1 Mar 2017 10:08:12 +0100 Subject: spi/bcm63xx-hsspi: allow providing clock rate through a second clock The HSSPI block actually has two clock inputs, one for gating the block, and one for the PLL rate. To allow these to be represented as two clocks, add support for retrieving the rate from a separate "pll" clock, if the "hsspi" clock does not provide one. Signed-off-by: Jonas Gorski Acked-by: Florian Fainelli Signed-off-by: Mark Brown --- drivers/spi/spi-bcm63xx-hsspi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 55789f7cda92..79096d17ebde 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -351,8 +351,16 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) return PTR_ERR(clk); rate = clk_get_rate(clk); - if (!rate) - return -EINVAL; + if (!rate) { + struct clk *pll_clk = devm_clk_get(dev, "pll"); + + if (IS_ERR(pll_clk)) + return PTR_ERR(pll_clk); + + rate = clk_get_rate(pll_clk); + if (!rate) + return -EINVAL; + } ret = clk_prepare_enable(clk); if (ret) -- cgit v1.2.3-58-ga151 From 7ab2463550e2a3a5b97dfa82e5bf8038b986f007 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Wed, 1 Mar 2017 10:08:14 +0100 Subject: spi/bcm63xx-hsspi: allow for probing through devicetree Add required binding support to probe through device tree. Signed-off-by: Jonas Gorski Acked-by: Florian Fainelli Signed-off-by: Mark Brown --- drivers/spi/spi-bcm63xx-hsspi.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 79096d17ebde..5514cd02e93a 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -19,6 +19,7 @@ #include #include #include +#include #define HSSPI_GLOBAL_CTRL_REG 0x0 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 @@ -91,6 +92,7 @@ #define HSSPI_MAX_SYNC_CLOCK 30000000 +#define HSSPI_SPI_MAX_CS 8 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ struct bcm63xx_hsspi { @@ -332,7 +334,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct clk *clk; int irq, ret; - u32 reg, rate; + u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -382,8 +384,17 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) mutex_init(&bs->bus_mutex); init_completion(&bs->done); - master->bus_num = HSSPI_BUS_NUM; - master->num_chipselect = 8; + master->dev.of_node = dev->of_node; + if (!dev->of_node) + master->bus_num = HSSPI_BUS_NUM; + + of_property_read_u32(dev->of_node, "num-cs", &num_cs); + if (num_cs > 8) { + dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", + num_cs); + num_cs = HSSPI_SPI_MAX_CS; + } + master->num_chipselect = num_cs; master->setup = bcm63xx_hsspi_setup; master->transfer_one_message = bcm63xx_hsspi_transfer_one; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | @@ -469,10 +480,16 @@ static int bcm63xx_hsspi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend, bcm63xx_hsspi_resume); +static const struct of_device_id bcm63xx_hsspi_of_match[] = { + { .compatible = "brcm,bcm6328-hsspi", }, + { }, +}; + static struct platform_driver bcm63xx_hsspi_driver = { .driver = { .name = "bcm63xx-hsspi", .pm = &bcm63xx_hsspi_pm_ops, + .of_match_table = bcm63xx_hsspi_of_match, }, .probe = bcm63xx_hsspi_probe, .remove = bcm63xx_hsspi_remove, -- cgit v1.2.3-58-ga151 From 500a32abaf818b3f4afe5b7f0ba9ca9b7a3aa65e Mon Sep 17 00:00:00 2001 From: Liu Xiang Date: Thu, 9 Mar 2017 22:40:01 +0800 Subject: spi: fsl: Call irq_dispose_mapping in err path Irq_dispose_mapping should be called in err path to release the resources that irq_of_parse_and_map requested. Signed-off-by: Liu Xiang Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 8b290d9d7935..592034320a41 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -813,7 +813,7 @@ static int of_fsl_spi_probe(struct platform_device *ofdev) struct device_node *np = ofdev->dev.of_node; struct spi_master *master; struct resource mem; - int irq, type; + int irq = 0, type; int ret = -ENOMEM; ret = of_mpc8xxx_spi_probe(ofdev); @@ -846,6 +846,7 @@ static int of_fsl_spi_probe(struct platform_device *ofdev) return 0; err: + irq_dispose_mapping(irq); if (type == TYPE_FSL) of_fsl_spi_free_chipselects(dev); return ret; -- cgit v1.2.3-58-ga151 From 251831bd4f4903415da7f0ce04dc0de26bc43f1d Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sun, 12 Mar 2017 11:11:43 +0000 Subject: spi: xlp: update for ARCH_VULCAN2 ARCH_VULCAN arm64 platform (for Broadcom Vulcan ARM64 processors) has been discontinued. Cavium's ThunderX2 CN99XX (ARCH_THUNDER2) will be the next revision of the platform. Update compile dependencies and ACPI ID to reflect this change. There is not need to retain ARCH_VULCAN since the Vulcan processor was never in production and ARCH_VULCAN will be deleted soon. Signed-off-by: Jayachandran C Signed-off-by: Mark Brown --- drivers/acpi/acpi_apd.c | 1 + drivers/spi/Kconfig | 2 +- drivers/spi/spi-xlp.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c index 7dd70927991e..89e74d0a6c33 100644 --- a/drivers/acpi/acpi_apd.c +++ b/drivers/acpi/acpi_apd.c @@ -164,6 +164,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = { #ifdef CONFIG_ARM64 { "APMC0D0F", APD_ADDR(xgene_i2c_desc) }, { "BRCM900D", APD_ADDR(vulcan_spi_desc) }, + { "CAV900D", APD_ADDR(vulcan_spi_desc) }, #endif { } }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec4aa252d6e8..8c40b5216ad6 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -705,7 +705,7 @@ config SPI_XILINX config SPI_XLP tristate "Netlogic XLP SPI controller driver" - depends on CPU_XLP || ARCH_VULCAN || COMPILE_TEST + depends on CPU_XLP || ARCH_THUNDER2 || COMPILE_TEST help Enable support for the SPI controller on the Netlogic XLP SoCs. Currently supported XLP variants are XLP8XX, XLP3XX, XLP2XX, XLP9XX diff --git a/drivers/spi/spi-xlp.c b/drivers/spi/spi-xlp.c index bea7a93a6046..80cb4d6af892 100644 --- a/drivers/spi/spi-xlp.c +++ b/drivers/spi/spi-xlp.c @@ -442,6 +442,7 @@ static int xlp_spi_probe(struct platform_device *pdev) #ifdef CONFIG_ACPI static const struct acpi_device_id xlp_spi_acpi_match[] = { { "BRCM900D", 0 }, + { "CAV900D", 0 }, { }, }; MODULE_DEVICE_TABLE(acpi, xlp_spi_acpi_match); -- cgit v1.2.3-58-ga151 From 6b3a631e7f8eca75a987ed760898d28fb3628143 Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Thu, 23 Feb 2017 19:01:58 +0100 Subject: spi: davinci: use rx buffer as dummy tx buffer When doing rx-only transfer, the transfer will fail if the number of SG entries exceeds 20. This happens because the eDMA DMA engine is limited to 20 SG entries in one transaction, and when the DMA transcation is resumed (which takes > 150us), rx errors occurs because the slave is still transmitting. Fix this by using the rx buffer as the dummy tx buffer, so that resuming the rx transcation happens at the same time as resuming the tx transcation. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 1e24395a04f2..ca122165a3c6 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -655,6 +655,12 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) if (!rxdesc) goto err_desc; + if (!t->tx_buf) { + /* use rx buffer as dummy tx buffer */ + t->tx_sg.sgl = t->rx_sg.sgl; + t->tx_sg.nents = t->rx_sg.nents; + } + txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -957,7 +963,7 @@ static int davinci_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->num_chipselect = pdata->num_chipselect; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); - master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); + master->flags = SPI_MASTER_MUST_RX; master->setup = davinci_spi_setup; master->cleanup = davinci_spi_cleanup; master->can_dma = davinci_spi_can_dma; -- cgit v1.2.3-58-ga151 From 0718b764880434ac7a5b7c0f5cb2c805c589a807 Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Thu, 23 Feb 2017 19:01:59 +0100 Subject: spi: davinci: do not use DMA if transfer length is less than 16 Higher bitrate and lower CPU load if using PIO in this case. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index ca122165a3c6..75c658e4e487 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -109,6 +109,8 @@ #define SPIDEF 0x4c #define SPIFMT0 0x50 +#define DMA_MIN_BYTES 16 + /* SPI Controller driver's private data. */ struct davinci_spi { struct spi_bitbang bitbang; @@ -479,7 +481,8 @@ static bool davinci_spi_can_dma(struct spi_master *master, bool can_dma = false; if (spicfg) - can_dma = spicfg->io_type == SPI_IO_TYPE_DMA; + can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && + (xfer->len >= DMA_MIN_BYTES); return can_dma; } @@ -620,10 +623,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) reinit_completion(&dspi->done); - if (spicfg->io_type == SPI_IO_TYPE_INTR) - set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - - if (spicfg->io_type != SPI_IO_TYPE_DMA) { + if (!davinci_spi_can_dma(spi->master, spi, t)) { + if (spicfg->io_type != SPI_IO_TYPE_POLL) + set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); /* start the transfer */ dspi->wcount--; tx_data = dspi->get_tx(dspi); @@ -698,7 +700,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) } clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) + if (davinci_spi_can_dma(spi->master, spi, t)) clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); -- cgit v1.2.3-58-ga151 From 4dd9becbce4f10009322c3e2297f9db3ace94a10 Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Thu, 23 Feb 2017 19:02:00 +0100 Subject: spi: davinci: do not use DMA for vmalloc'ed buffers Using vmalloc'ed buffers will fail since daVinci has VIVT cache and only the kernel lowmem virtual address is invalidated/flushed when performing DMA. The virtual address returned from vmalloc() is not invalidated/flushed and may contain stale data when returning from spi_sync(). Fixes errors when running UBIFS over SPI NOR. Revert this when all upper layer users of vmalloc'ed buffers sent to SPI handles cache flushing/invalidating. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 75c658e4e487..f37bbdd18d61 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -482,7 +482,9 @@ static bool davinci_spi_can_dma(struct spi_master *master, if (spicfg) can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && - (xfer->len >= DMA_MIN_BYTES); + (xfer->len >= DMA_MIN_BYTES) && + !is_vmalloc_addr(xfer->rx_buf) && + !is_vmalloc_addr(xfer->tx_buf); return can_dma; } -- cgit v1.2.3-58-ga151 From 576333a1fb940767e8638fafea908214682e8acd Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Thu, 23 Feb 2017 19:02:01 +0100 Subject: spi: loopback-test: add option to use vmalloc'ed buffers Using vmalloc'ed buffers will use one SG entry for each page, that may provoke DMA errors for large transfers. Also vmalloc'ed buffers may cause errors on CPU's with VIVT cache. Add this option to catch these errors when testing. Note that to catch VIVT cache errors, checking the rx range has to be disabled, so this option has been added as well. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 50e620f4e8fe..35960515382e 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -55,6 +55,18 @@ module_param(run_only_test, int, 0); MODULE_PARM_DESC(run_only_test, "only run the test with this number (0-based !)"); +/* use vmalloc'ed buffers */ +int use_vmalloc; +module_param(use_vmalloc, int, 0644); +MODULE_PARM_DESC(use_vmalloc, + "use vmalloc'ed buffers instead of kmalloc'ed"); + +/* check rx ranges */ +int check_ranges = 1; +module_param(check_ranges, int, 0644); +MODULE_PARM_DESC(check_ranges, + "checks rx_buffer pattern are valid"); + /* the actual tests to execute */ static struct spi_test spi_tests[] = { { @@ -492,9 +504,11 @@ static int spi_test_check_loopback_result(struct spi_device *spi, int ret; /* checks rx_buffer pattern are valid with loopback or without */ - ret = spi_check_rx_ranges(spi, msg, rx); - if (ret) - return ret; + if (check_ranges) { + ret = spi_check_rx_ranges(spi, msg, rx); + if (ret) + return ret; + } /* if we run without loopback, then return now */ if (!loopback) @@ -965,13 +979,19 @@ int spi_test_run_tests(struct spi_device *spi, /* allocate rx/tx buffers of 128kB size without devm * in the hope that is on a page boundary */ - rx = kzalloc(SPI_TEST_MAX_SIZE_PLUS, GFP_KERNEL); + if (use_vmalloc) + rx = vmalloc(SPI_TEST_MAX_SIZE_PLUS); + else + rx = kzalloc(SPI_TEST_MAX_SIZE_PLUS, GFP_KERNEL); if (!rx) { ret = -ENOMEM; goto out; } - tx = kzalloc(SPI_TEST_MAX_SIZE_PLUS, GFP_KERNEL); + if (use_vmalloc) + tx = vmalloc(SPI_TEST_MAX_SIZE_PLUS); + else + tx = kzalloc(SPI_TEST_MAX_SIZE_PLUS, GFP_KERNEL); if (!tx) { ret = -ENOMEM; goto out; @@ -999,8 +1019,8 @@ int spi_test_run_tests(struct spi_device *spi, } out: - kfree(rx); - kfree(tx); + kvfree(rx); + kvfree(tx); return ret; } EXPORT_SYMBOL_GPL(spi_test_run_tests); -- cgit v1.2.3-58-ga151 From 91b4634632e0138b655a63fdb1704edbbcd6cdda Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Thu, 16 Mar 2017 11:00:30 +0000 Subject: spi: spidev: Add sx1301 to device tree compatibility list Add entry for the semtech sx1301 baseband processor implementing a LoRa concentrator IP. At this time this chip requires an spidev userspace driver. Signed-off-by: Ben Whitten Signed-off-by: Steve deRosier Signed-off-by: Mark Brown --- drivers/spi/spidev.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 9e2e099baf8c..9a2a79a871ba 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -697,6 +697,7 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "rohm,dh2228fv" }, { .compatible = "lineartechnology,ltc2488" }, { .compatible = "ge,achc" }, + { .compatible = "semtech,sx1301" }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); -- cgit v1.2.3-58-ga151 From e542f7e63cb17242fcfc1be5edd69532cf434697 Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Fri, 17 Mar 2017 12:07:58 +0100 Subject: spi: loopback-test: fix compile error on x86 Fix compile error caused by missing vmalloc() definition on x86 (and maybe other platforms) by including vmalloc.h. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 35960515382e..4e7843ec8aac 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include "spi-test.h" -- cgit v1.2.3-58-ga151 From c4e121aeb754f1ac5f2bcc791aa4177dcfb3b401 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:26 +0900 Subject: spi: loopback-test: correct mismatched test description and configuration The test "two tx-transfers - alter first" actually alters the second not the first transfer. Similarly the test "two tx-transfers - alter second" actually alters the first not the second transfer. The mismatches for the two symmetrical tests cancel each other's mistakes. But it's better to fix the mismatches to avoid confusion. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 50e620f4e8fe..99422f3a15e0 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -132,7 +132,7 @@ static struct spi_test spi_tests[] = { .fill_option = FILL_COUNT_8, .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, - .iterate_transfer_mask = BIT(1), + .iterate_transfer_mask = BIT(0), .transfers = { { .len = 1, @@ -149,7 +149,7 @@ static struct spi_test spi_tests[] = { .fill_option = FILL_COUNT_8, .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, - .iterate_transfer_mask = BIT(0), + .iterate_transfer_mask = BIT(1), .transfers = { { .len = 16, -- cgit v1.2.3-58-ga151 From 8494801db1fc21867f587dae465236100bf228cc Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:27 +0900 Subject: spi: loopback-test: don't skip comparing the first byte of rx_buf When the loopback parameter is set, rx_buf are compared with tx_buf after the spi_message is executed. But the first byte of buffer is not checked. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 99422f3a15e0..85c0c4e391d9 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -507,7 +507,7 @@ static int spi_test_check_loopback_result(struct spi_device *spi, continue; /* so depending on tx_buf we need to handle things */ if (xfer->tx_buf) { - for (i = 1; i < xfer->len; i++) { + for (i = 0; i < xfer->len; i++) { txb = ((u8 *)xfer->tx_buf)[i]; rxb = ((u8 *)xfer->rx_buf)[i]; if (txb != rxb) -- cgit v1.2.3-58-ga151 From 8916671e93a38c509e2ffb02c2ce3f37efe8af40 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:28 +0900 Subject: spi: loopback-test: add ability to test zero-length transfer The spi-loopback-test module currently cannot test the spi_message including a zero-length transfer. Because the zero-length transfer is treated as a special value in several meanings. 1. The number of spi_transfer to execute in one test case is described by spi_test.transfer_count. It is normally computed by counting number of transfers with len > 0 in spi_test.transfers array. This change stops the detection for the number of spi_transfer. Each spi_test.transfer_count needs to be filled by hand now. 2. The spi_test.iterate_len is a list of transfer length to iterate on. This list is terminated by zero, so zero-length transfer cannot be included. This changes the terminal value from 0 to -1. 3. The length for the spi_transfer masked by spi_test.iterate_transfer_mask is iterated. Before starting the iteration, the default value which is statically initialized is applied. In order to specify the default value, zero-length is reserved. Currently, the default values are always '1'. So this removes this trick and add '1' to iterate_len list. By applying all these changes, the spi-loopback-test can execute spi messages with zero-length transfer. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 55 +++++++++++++---------------------------- drivers/spi/spi-test.h | 19 +++++++------- 2 files changed, 26 insertions(+), 48 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 85c0c4e391d9..6df6dddc2890 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -63,9 +63,9 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_rx_align = ITERATE_ALIGN, + .transfer_count = 1, .transfers = { { - .len = 1, .tx_buf = TX(0), .rx_buf = RX(0), }, @@ -77,9 +77,9 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_rx_align = ITERATE_ALIGN, + .transfer_count = 1, .transfers = { { - .len = 1, .tx_buf = TX(PAGE_SIZE - 4), .rx_buf = RX(PAGE_SIZE - 4), }, @@ -90,9 +90,9 @@ static struct spi_test spi_tests[] = { .fill_option = FILL_COUNT_8, .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, + .transfer_count = 1, .transfers = { { - .len = 1, .tx_buf = TX(0), }, }, @@ -102,9 +102,9 @@ static struct spi_test spi_tests[] = { .fill_option = FILL_COUNT_8, .iterate_len = { ITERATE_MAX_LEN }, .iterate_rx_align = ITERATE_ALIGN, + .transfer_count = 1, .transfers = { { - .len = 1, .rx_buf = RX(0), }, }, @@ -115,13 +115,12 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0) | BIT(1), + .transfer_count = 2, .transfers = { { - .len = 1, .tx_buf = TX(0), }, { - .len = 1, /* this is why we cant use ITERATE_MAX_LEN */ .tx_buf = TX(SPI_TEST_MAX_SIZE_HALF), }, @@ -133,9 +132,9 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0), + .transfer_count = 2, .transfers = { { - .len = 1, .tx_buf = TX(64), }, { @@ -150,13 +149,13 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(1), + .transfer_count = 2, .transfers = { { .len = 16, .tx_buf = TX(0), }, { - .len = 1, .tx_buf = TX(64), }, }, @@ -167,13 +166,12 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0) | BIT(1), + .transfer_count = 2, .transfers = { { - .len = 1, .tx_buf = TX(0), }, { - .len = 1, .rx_buf = RX(0), }, }, @@ -184,9 +182,9 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0), + .transfer_count = 2, .transfers = { { - .len = 1, .tx_buf = TX(0), }, { @@ -201,13 +199,13 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(1), + .transfer_count = 2, .transfers = { { .len = 1, .tx_buf = TX(0), }, { - .len = 1, .rx_buf = RX(0), }, }, @@ -218,14 +216,13 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0) | BIT(1), + .transfer_count = 2, .transfers = { { - .len = 1, .tx_buf = TX(0), .rx_buf = RX(0), }, { - .len = 1, /* making sure we align without overwrite * the reason we can not use ITERATE_MAX_LEN */ @@ -240,9 +237,9 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(0), + .transfer_count = 2, .transfers = { { - .len = 1, /* making sure we align without overwrite */ .tx_buf = TX(1024), .rx_buf = RX(1024), @@ -261,6 +258,7 @@ static struct spi_test spi_tests[] = { .iterate_len = { ITERATE_MAX_LEN }, .iterate_tx_align = ITERATE_ALIGN, .iterate_transfer_mask = BIT(1), + .transfer_count = 2, .transfers = { { .len = 1, @@ -268,7 +266,6 @@ static struct spi_test spi_tests[] = { .rx_buf = RX(0), }, { - .len = 1, /* making sure we align without overwrite */ .tx_buf = TX(1024), .rx_buf = RX(1024), @@ -503,7 +500,7 @@ static int spi_test_check_loopback_result(struct spi_device *spi, /* if applicable to transfer check that rx_buf is equal to tx_buf */ list_for_each_entry(xfer, &msg->transfers, transfer_list) { /* if there is no rx, then no check is needed */ - if (!xfer->rx_buf) + if (!xfer->len || !xfer->rx_buf) continue; /* so depending on tx_buf we need to handle things */ if (xfer->tx_buf) { @@ -745,15 +742,6 @@ static int spi_test_run_iter(struct spi_device *spi, /* copy the test template to test */ memcpy(&test, testtemplate, sizeof(test)); - /* set up test->transfers to the correct count */ - if (!test.transfer_count) { - for (i = 0; - (i < SPI_TEST_MAX_TRANSFERS) && test.transfers[i].len; - i++) { - test.transfer_count++; - } - } - /* if iterate_transfer_mask is not set, * then set it to first transfer only */ @@ -799,8 +787,7 @@ static int spi_test_run_iter(struct spi_device *spi, /* only when bit in transfer mask is set */ if (!(test.iterate_transfer_mask & BIT(i))) continue; - if (len) - test.transfers[i].len = len; + test.transfers[i].len = len; if (test.transfers[i].tx_buf) test.transfers[i].tx_buf += tx_off; if (test.transfers[i].tx_buf) @@ -910,15 +897,6 @@ int spi_test_run_test(struct spi_device *spi, const struct spi_test *test, /* iterate over all the iterable values using macros * (to make it a bit more readable... */ -#define FOR_EACH_ITERATE(var, defaultvalue) \ - for (idx_##var = -1, var = defaultvalue; \ - ((idx_##var < 0) || \ - ( \ - (idx_##var < SPI_TEST_MAX_ITERATE) && \ - (var = test->iterate_##var[idx_##var]) \ - ) \ - ); \ - idx_##var++) #define FOR_EACH_ALIGNMENT(var) \ for (var = 0; \ var < (test->iterate_##var ? \ @@ -928,7 +906,8 @@ int spi_test_run_test(struct spi_device *spi, const struct spi_test *test, 1); \ var++) - FOR_EACH_ITERATE(len, 0) { + for (idx_len = 0; idx_len < SPI_TEST_MAX_ITERATE && + (len = test->iterate_len[idx_len]) != -1; idx_len++) { FOR_EACH_ALIGNMENT(tx_align) { FOR_EACH_ALIGNMENT(rx_align) { /* and run the iteration */ diff --git a/drivers/spi/spi-test.h b/drivers/spi/spi-test.h index 922c52833239..2dd569138880 100644 --- a/drivers/spi/spi-test.h +++ b/drivers/spi/spi-test.h @@ -48,9 +48,8 @@ * * @msg: a template @spi_message usedfor the default settings * @transfers: array of @spi_transfers that are part of the - * resulting spi_message. The first transfer with len == 0 - * signifies the end of the list - * @transfer_count: normally computed number of transfers with len > 0 + * resulting spi_message. + * @transfer_count: number of transfers * * @run_test: run a specific spi_test - this allows to override * the default implementation of @spi_test_run_transfer @@ -62,8 +61,7 @@ * @expected_return: the expected return code - in some cases we want to * test also for error conditions * - * @iterate_len: list of length to iterate on (in addition to the - * explicitly set @spi_transfer.len) + * @iterate_len: list of length to iterate on * @iterate_tx_align: change the alignment of @spi_transfer.tx_buf * for all values in the below range if set. * the ranges are: @@ -89,7 +87,7 @@ struct spi_test { int (*execute_msg)(struct spi_device *spi, struct spi_test *test, void *tx, void *rx); int expected_return; - /* iterate over all the non-zero values */ + /* iterate over all values, terminated by a -1 */ int iterate_len[SPI_TEST_MAX_ITERATE]; int iterate_tx_align; int iterate_rx_align; @@ -126,11 +124,12 @@ int spi_test_execute_msg(struct spi_device *spi, int spi_test_run_tests(struct spi_device *spi, struct spi_test *tests); -/* some of the default @spi_transfer.len to test */ -#define ITERATE_LEN 2, 3, 7, 11, 16, 31, 32, 64, 97, 128, 251, 256, \ +#define ITERATE_LEN_LIST 1, 2, 3, 7, 11, 16, 31, 32, 64, 97, 128, 251, 256, \ 1021, 1024, 1031, 4093, PAGE_SIZE, 4099, 65536, 65537 - -#define ITERATE_MAX_LEN ITERATE_LEN, SPI_TEST_MAX_SIZE - 1, SPI_TEST_MAX_SIZE +/* some of the default @spi_transfer.len to test, terminated by a -1 */ +#define ITERATE_LEN ITERATE_LEN_LIST, -1 +#define ITERATE_MAX_LEN ITERATE_LEN_LIST, (SPI_TEST_MAX_SIZE - 1), \ + SPI_TEST_MAX_SIZE, -1 /* the default alignment to test */ #define ITERATE_ALIGN sizeof(int) -- cgit v1.2.3-58-ga151 From 0bd7fda56b94002d9985040c02bb701956fa657e Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:29 +0900 Subject: spi: loopback-test: test zero-length transfer In order to test various spi_messages including zero-length transfer, this adds zero length into the iterate_len list. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-test.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-test.h b/drivers/spi/spi-test.h index 2dd569138880..82fff4a0fd94 100644 --- a/drivers/spi/spi-test.h +++ b/drivers/spi/spi-test.h @@ -124,7 +124,7 @@ int spi_test_execute_msg(struct spi_device *spi, int spi_test_run_tests(struct spi_device *spi, struct spi_test *tests); -#define ITERATE_LEN_LIST 1, 2, 3, 7, 11, 16, 31, 32, 64, 97, 128, 251, 256, \ +#define ITERATE_LEN_LIST 0, 1, 2, 3, 7, 11, 16, 31, 32, 64, 97, 128, 251, 256, \ 1021, 1024, 1031, 4093, PAGE_SIZE, 4099, 65536, 65537 /* some of the default @spi_transfer.len to test, terminated by a -1 */ #define ITERATE_LEN ITERATE_LEN_LIST, -1 -- cgit v1.2.3-58-ga151 From ea9936f32435699907807aaac87f993482208578 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:30 +0900 Subject: spi: loopback-test: add elapsed time check This adds checks whether the elapsed time is longer than the minimam estimated time. The estimated time is calculated with the total transfer length per clock rate and optional spi_transfer.delay_usecs. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 38 ++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-test.h | 2 ++ 2 files changed, 40 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 6df6dddc2890..66e8cfd04395 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -479,6 +480,35 @@ static int spi_check_rx_ranges(struct spi_device *spi, return ret; } +static int spi_test_check_elapsed_time(struct spi_device *spi, + struct spi_test *test) +{ + int i; + unsigned long long estimated_time = 0; + unsigned long long delay_usecs = 0; + + for (i = 0; i < test->transfer_count; i++) { + struct spi_transfer *xfer = test->transfers + i; + unsigned long long nbits = BITS_PER_BYTE * xfer->len; + + delay_usecs += xfer->delay_usecs; + if (!xfer->speed_hz) + continue; + estimated_time += div_u64(nbits * NSEC_PER_SEC, xfer->speed_hz); + } + + estimated_time += delay_usecs * NSEC_PER_USEC; + if (test->elapsed_time < estimated_time) { + dev_err(&spi->dev, + "elapsed time %lld ns is shorter than minimam estimated time %lld ns\n", + test->elapsed_time, estimated_time); + + return -EINVAL; + } + + return 0; +} + static int spi_test_check_loopback_result(struct spi_device *spi, struct spi_message *msg, void *tx, void *rx) @@ -817,12 +847,16 @@ int spi_test_execute_msg(struct spi_device *spi, struct spi_test *test, /* only if we do not simulate */ if (!simulate_only) { + ktime_t start; + /* dump the complete message before and after the transfer */ if (dump_messages == 3) spi_test_dump_message(spi, msg, true); + start = ktime_get(); /* run spi message */ ret = spi_sync(spi, msg); + test->elapsed_time = ktime_to_ns(ktime_sub(ktime_get(), start)); if (ret == -ETIMEDOUT) { dev_info(&spi->dev, "spi-message timed out - reruning...\n"); @@ -848,6 +882,10 @@ int spi_test_execute_msg(struct spi_device *spi, struct spi_test *test, /* run rx-buffer tests */ ret = spi_test_check_loopback_result(spi, msg, tx, rx); + if (ret) + goto exit; + + ret = spi_test_check_elapsed_time(spi, test); } /* if requested or on error dump message (including data) */ diff --git a/drivers/spi/spi-test.h b/drivers/spi/spi-test.h index 82fff4a0fd94..6ed7b899da8a 100644 --- a/drivers/spi/spi-test.h +++ b/drivers/spi/spi-test.h @@ -75,6 +75,7 @@ * @fill_option: define the way how tx_buf is filled * @fill_pattern: fill pattern to apply to the tx_buf * (used in some of the @fill_options) + * @elapsed_time: elapsed time in nanoseconds */ struct spi_test { @@ -108,6 +109,7 @@ struct spi_test { #define FILL_TRANSFER_BYTE_32 11 /* fill with the transfer byte - 32 bit */ #define FILL_TRANSFER_NUM 16 /* fill with the transfer number */ u32 fill_pattern; + unsigned long long elapsed_time; }; /* default implementation for @spi_test.run_test */ -- cgit v1.2.3-58-ga151 From 8687113e1515f4c9104a6eaedc384ec762c6550f Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sat, 18 Mar 2017 03:17:31 +0900 Subject: spi: loopback-test: add test spi_message with delay after transfers This adds a new test to check whether the spi_transfer.delay_usecs setting has properly taken effect. Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 66e8cfd04395..fcae3377ec26 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -273,6 +273,25 @@ static struct spi_test spi_tests[] = { }, }, }, + { + .description = "two tx+rx transfers - delay after transfer", + .fill_option = FILL_COUNT_8, + .iterate_len = { ITERATE_MAX_LEN }, + .iterate_transfer_mask = BIT(0) | BIT(1), + .transfer_count = 2, + .transfers = { + { + .tx_buf = TX(0), + .rx_buf = RX(0), + .delay_usecs = 1000, + }, + { + .tx_buf = TX(0), + .rx_buf = RX(0), + .delay_usecs = 1000, + }, + }, + }, { /* end of tests sequence */ } }; -- cgit v1.2.3-58-ga151 From 1234e8398fe03267bf2e353e36825dbd0abc2fc6 Mon Sep 17 00:00:00 2001 From: Frode Isaksen Date: Fri, 17 Mar 2017 16:41:10 +0100 Subject: spi: davinci: add comment about dummy tx buffer usage Add explanation about using the the rx buffer as the dummy tx buffer. Signed-off-by: Frode Isaksen Signed-off-by: Mark Brown --- drivers/spi/spi-davinci.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index f37bbdd18d61..595acdcfc7d0 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -660,7 +660,11 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) goto err_desc; if (!t->tx_buf) { - /* use rx buffer as dummy tx buffer */ + /* To avoid errors when doing rx-only transfers with + * many SG entries (> 20), use the rx buffer as the + * dummy tx buffer so that dma reloads are done at the + * same time for rx and tx. + */ t->tx_sg.sgl = t->rx_sg.sgl; t->tx_sg.nents = t->rx_sg.nents; } -- cgit v1.2.3-58-ga151 From 3288d5cb40c09213e86d67b5cab09de1deb65a5c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 20 Mar 2017 22:38:49 +0800 Subject: spi: sun6i: update max transfer size reported The spi-sun6i driver have already got the ability to do large transfers. However, the max transfer size reported is still fifo depth - 1. Update the max transfer size reported to the max value possible. Reported-by: Martin Ayotte Signed-off-by: Icenowy Zheng Signed-off-by: Mark Brown --- drivers/spi/spi-sun6i.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 6e9ca93db9bf..03a773a9531a 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -194,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) { - struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); - - return sspi->fifo_depth - 1; + return SUN6I_MAX_XFER_SIZE - 1; } static int sun6i_spi_transfer_one(struct spi_master *master, -- cgit v1.2.3-58-ga151 From d2c14c64d678713fced6f2261ce7d398b4351de5 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 20 Mar 2017 13:58:05 +0000 Subject: spi: loopback-test: fix potential integer overflow on multiple A multiplication of 8U * xfer-len with the type of a 32 bit unsigned int is evaluated using 32 bit arithmetic and then used in a context that expects an expression of type unsigned long long (64 bits). Avoid any potential overflow by casting BITS_PER_BYTE to unsigned long long. Detected by CoverityScan, CID#1419691 ("Unintentional integer overflow") Fixes: ea9936f324356 ("spi: loopback-test: add elapsed time check") Signed-off-by: Colin Ian King Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index fcae3377ec26..6888d5c34ac4 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -508,7 +508,8 @@ static int spi_test_check_elapsed_time(struct spi_device *spi, for (i = 0; i < test->transfer_count; i++) { struct spi_transfer *xfer = test->transfers + i; - unsigned long long nbits = BITS_PER_BYTE * xfer->len; + unsigned long long nbits = (unsigned long long)BITS_PER_BYTE * + xfer->len; delay_usecs += xfer->delay_usecs; if (!xfer->speed_hz) -- cgit v1.2.3-58-ga151 From 1351aaeb50b2ae5eb5469b3d3d0a84073a127a39 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Fri, 24 Mar 2017 12:12:15 +0530 Subject: spi: spi-ti-qspi: Use dma_engine wrapper for dma memcpy call Instead of calling device_prep_dma_memcpy() directly with dma_device pointer, use the newly introduced dmaengine_prep_dma_memcpy() wrapper API. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- drivers/spi/spi-ti-qspi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index ec6fb09e2e17..bd19a20a122e 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -401,8 +401,7 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, struct dma_async_tx_descriptor *tx; int ret; - tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, - len, flags); + tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags); if (!tx) { dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); return -EIO; -- cgit v1.2.3-58-ga151 From 812613591cb652344186c4cd912304ed02138566 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Wed, 22 Mar 2017 09:18:26 +0900 Subject: spi: omap2-mcspi: poll OMAP2_MCSPI_CHSTAT_RXS for PIO transfer When running the spi-loopback-test with slower clock rate like 10 KHz, the test for 251 bytes transfer was failed. This failure triggered an spi-omap2-mcspi's error message "DMA RX last word empty". This message means that PIO for reading the remaining bytes due to the DMA transfer length reduction is failed. This problem can be fixed by polling OMAP2_MCSPI_CHSTAT_RXS bit in channel status register to wait until the receive buffer register is filled. Cc: Mark Brown Signed-off-by: Akinobu Mita Signed-off-by: Mark Brown --- drivers/spi/spi-omap2-mcspi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index 79800e991ccd..7275223dbcd4 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -454,6 +454,8 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, int elements = 0; int word_len, element_count; struct omap2_mcspi_cs *cs = spi->controller_state; + void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; + mcspi = spi_master_get_devdata(spi->master); mcspi_dma = &mcspi->dma_channels[spi->chip_select]; count = xfer->len; @@ -549,8 +551,8 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, if (l & OMAP2_MCSPI_CHCONF_TURBO) { elements--; - if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) - & OMAP2_MCSPI_CHSTAT_RXS)) { + if (!mcspi_wait_for_reg_bit(chstat_reg, + OMAP2_MCSPI_CHSTAT_RXS)) { u32 w; w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); @@ -568,8 +570,7 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, return count; } } - if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) - & OMAP2_MCSPI_CHSTAT_RXS)) { + if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) { u32 w; w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); -- cgit v1.2.3-58-ga151 From cb3c8e5ade3f01839ce0a9388ddc9729de4e2d6d Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Mon, 27 Mar 2017 10:59:28 +0530 Subject: spi: spi-ti-qspi: Remove unused dma_dev variable commit 1351aaeb50b2 ("spi: spi-ti-qspi: Use dma_engine wrapper for dma memcpy call") introduced this warning: drivers/spi/spi-ti-qspi.c: In function 'ti_qspi_dma_xfer': drivers/spi/spi-ti-qspi.c:398:21: warning: unused variable 'dma_dev' [-Wunused-variable] struct dma_device *dma_dev = chan->device; Fix it by removing the unused variable. Signed-off-by: Vignesh R Reported-by: Stephen Rothwell Signed-off-by: Mark Brown --- drivers/spi/spi-ti-qspi.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index bd19a20a122e..804914ebfd9d 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -395,7 +395,6 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len) { struct dma_chan *chan = qspi->rx_chan; - struct dma_device *dma_dev = chan->device; dma_cookie_t cookie; enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; struct dma_async_tx_descriptor *tx; -- cgit v1.2.3-58-ga151 From 905e0b5ef9690c5433b642f46f1d756bb374da17 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 30 Mar 2017 11:01:25 +0100 Subject: spi: loopback-test: fix spelling mistake: "minimam" -> "minimum" trivial fix to spelling mistake in dev_err error message Signed-off-by: Colin Ian King Signed-off-by: Mark Brown --- drivers/spi/spi-loopback-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 6888d5c34ac4..e6041539afed 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -520,7 +520,7 @@ static int spi_test_check_elapsed_time(struct spi_device *spi, estimated_time += delay_usecs * NSEC_PER_USEC; if (test->elapsed_time < estimated_time) { dev_err(&spi->dev, - "elapsed time %lld ns is shorter than minimam estimated time %lld ns\n", + "elapsed time %lld ns is shorter than minimum estimated time %lld ns\n", test->elapsed_time, estimated_time); return -EINVAL; -- cgit v1.2.3-58-ga151 From 849794c50b24b93676b939028c811d6e116ef335 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Thu, 6 Apr 2017 10:16:23 +0200 Subject: spi: pl022: don't use uninitialized variable The num-cs property is a required property according to the binding documentation. However, if it is not present, the driver currently simply uses random junk from the stack for the num-cs since the variable whose pointer is passed to of_property_read_u32() is not initialized. Signed-off-by: Rabin Vincent Signed-off-by: Mark Brown --- drivers/spi/spi-pl022.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index f7f7ba17b40e..2f76e022cc59 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -2074,7 +2074,7 @@ pl022_platform_data_dt_get(struct device *dev) { struct device_node *np = dev->of_node; struct pl022_ssp_controller *pd; - u32 tmp; + u32 tmp = 0; if (!np) { dev_err(dev, "no dt node defined\n"); -- cgit v1.2.3-58-ga151 From 1017f424015933a12e5068dc7f59ddf6b8645218 Mon Sep 17 00:00:00 2001 From: Bastian Stender Date: Fri, 7 Apr 2017 15:52:33 +0200 Subject: spi: orion: add LSB support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The orion spi driver currently only supports the normal (i.e. MSB) mode. This patch adds LSB first mode. Also correct the comment about supported SPI modes that was left over by b15d5d7004e2 ("spi/orion: Add SPI_CHPA and SPI_CPOL support to kirkwood driver."). Signed-off-by: Bastian Stender Acked-by: Uwe Kleine-König Signed-off-by: Mark Brown --- drivers/spi/spi-orion.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index 6b001c4a5640..be2e87ee8b31 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -39,6 +39,8 @@ #define ORION_SPI_IF_CTRL_REG 0x00 #define ORION_SPI_IF_CONFIG_REG 0x04 +#define ORION_SPI_IF_RXLSBF BIT(14) +#define ORION_SPI_IF_TXLSBF BIT(13) #define ORION_SPI_DATA_OUT_REG 0x08 #define ORION_SPI_DATA_IN_REG 0x0c #define ORION_SPI_INT_CAUSE_REG 0x10 @@ -234,6 +236,11 @@ orion_spi_mode_set(struct spi_device *spi) reg |= ORION_SPI_MODE_CPOL; if (spi->mode & SPI_CPHA) reg |= ORION_SPI_MODE_CPHA; + if (spi->mode & SPI_LSB_FIRST) + reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; + else + reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); + writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); } @@ -591,8 +598,8 @@ static int orion_spi_probe(struct platform_device *pdev) master->bus_num = cell_index; } - /* we support only mode 0, and no options */ - master->mode_bits = SPI_CPHA | SPI_CPOL; + /* we support all 4 SPI modes and LSB first option */ + master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; master->set_cs = orion_spi_set_cs; master->transfer_one = orion_spi_transfer_one; master->num_chipselect = ORION_NUM_CHIPSELECTS; -- cgit v1.2.3-58-ga151 From 05514c86965f98f9b0e57f73700771fa267050a7 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 12 Apr 2017 09:05:19 +0200 Subject: spi: atmel: factorize reusable code for SPI controller init The SPI controller configuration during the init can be reused, for the resume function for example. Let's move this configuration to a separate function. Signed-off-by: Quentin Schulz Acked-by: Nicolas Ferre Signed-off-by: Mark Brown --- drivers/spi/spi-atmel.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 0e7712bac3b6..247d920a512f 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1464,6 +1464,25 @@ static int atmel_spi_gpio_cs(struct platform_device *pdev) return 0; } +static void atmel_spi_init(struct atmel_spi *as) +{ + spi_writel(as, CR, SPI_BIT(SWRST)); + spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ + if (as->caps.has_wdrbt) { + spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); + } else { + spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); + } + + if (as->use_pdc) + spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); + spi_writel(as, CR, SPI_BIT(SPIEN)); + + if (as->fifo_size) + spi_writel(as, CR, SPI_BIT(FIFOEN)); +} + static int atmel_spi_probe(struct platform_device *pdev) { struct resource *regs; @@ -1572,26 +1591,14 @@ static int atmel_spi_probe(struct platform_device *pdev) as->spi_clk = clk_get_rate(clk); - spi_writel(as, CR, SPI_BIT(SWRST)); - spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ - if (as->caps.has_wdrbt) { - spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); - } else { - spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); - } - - if (as->use_pdc) - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); - spi_writel(as, CR, SPI_BIT(SPIEN)); - as->fifo_size = 0; if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", &as->fifo_size)) { dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); - spi_writel(as, CR, SPI_BIT(FIFOEN)); } + atmel_spi_init(as); + pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_active(&pdev->dev); -- cgit v1.2.3-58-ga151 From e53800787a251d67e532fadf72886be0661aba12 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 14 Apr 2017 10:22:43 +0200 Subject: spi: atmel: add deepest PM support to SAMA5D2 This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2 SoC's SPI controller. When resuming from deepest state, it is required to restore MR register as the registers are lost since VDD core has been shut down when entering deepest state on the SAMA5D2. Signed-off-by: Quentin Schulz Acked-by: Alexandre Belloni Acked-by: Nicolas Ferre Signed-off-by: Mark Brown --- drivers/spi/spi-atmel.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 247d920a512f..1eb83c9613d5 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1702,8 +1702,17 @@ static int atmel_spi_suspend(struct device *dev) static int atmel_spi_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); + struct atmel_spi *as = spi_master_get_devdata(master); int ret; + ret = clk_prepare_enable(as->clk); + if (ret) + return ret; + + atmel_spi_init(as); + + clk_disable_unprepare(as->clk); + if (!pm_runtime_suspended(dev)) { ret = atmel_spi_runtime_resume(dev); if (ret) -- cgit v1.2.3-58-ga151 From 833bfade96561216aa2129516a5926a0326860a2 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Mon, 17 Apr 2017 01:38:05 +0200 Subject: spi: double time out tolerance The generic SPI code calculates how long the issued transfer would take and adds 100ms in addition to the timeout as tolerance. On my 500 MHz Lantiq Mips SoC I am getting timeouts from the SPI like this when the system boots up: m25p80 spi32766.4: SPI transfer timed out blk_update_request: I/O error, dev mtdblock3, sector 2 SQUASHFS error: squashfs_read_data failed to read block 0x6e After increasing the tolerance for the timeout to 200ms I haven't seen these SPI transfer time outs any more. The Lantiq SPI driver in use here has an extra work queue in between, which gets triggered when the controller send the last word and the hardware FIFOs used for reading and writing are only 8 words long. Signed-off-by: Hauke Mehrtens Signed-off-by: Mark Brown --- drivers/spi/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 656dd3e3220c..0af62c6f93a8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1012,7 +1012,7 @@ static int spi_transfer_one_message(struct spi_master *master, ret = 0; ms = 8LL * 1000LL * xfer->len; do_div(ms, xfer->speed_hz); - ms += ms + 100; /* some tolerance */ + ms += ms + 200; /* some tolerance */ if (ms > UINT_MAX) ms = UINT_MAX; -- cgit v1.2.3-58-ga151 From 400c18e3dc86e04ef5afec9b86a8586ca629b9e9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Apr 2017 20:09:06 +0200 Subject: spi: dw: Disable clock after unregistering the host The dw_mmio driver disables the block clock before unregistering the host. The code unregistering the host may access the SPI block registers. If register access happens with block clock disabled, this may lead to a bus hang. Disable the clock after unregistering the host to prevent such situation. This bug was observed on Altera Cyclone V SoC. Signed-off-by: Marek Vasut Cc: Andy Shevchenko Cc: Mark Brown Signed-off-by: Mark Brown --- drivers/spi/spi-dw-mmio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 447497e9124c..d25cc4037e23 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -115,8 +115,8 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) { struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); - clk_disable_unprepare(dwsmmio->clk); dw_spi_remove_host(&dwsmmio->dws); + clk_disable_unprepare(dwsmmio->clk); return 0; } -- cgit v1.2.3-58-ga151 From 2bca34455b257d75080d87e800ae14afe49001bf Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 11 Apr 2017 17:22:24 +0530 Subject: spi: Add can_dma like interface for spi_flash_read Add an interface analogous to ->can_dma() for spi_flash_read() interface. This will enable SPI controller drivers to inform SPI core when not to do DMA mappings. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- drivers/spi/spi.c | 2 +- include/linux/spi/spi.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 656dd3e3220c..5e1bb43b8a8f 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2811,7 +2811,7 @@ int spi_flash_read(struct spi_device *spi, mutex_lock(&master->bus_lock_mutex); mutex_lock(&master->io_mutex); - if (master->dma_rx) { + if (master->dma_rx && master->spi_flash_can_dma(spi, msg)) { rx_dev = master->dma_rx->device->dev; ret = spi_map_buf(master, rx_dev, &msg->rx_sg, msg->buf, msg->len, diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 75c6bd0ac605..cd8ae65568e3 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -375,6 +375,8 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv) * @unprepare_message: undo any work done by prepare_message(). * @spi_flash_read: to support spi-controller hardwares that provide * accelerated interface to read from flash devices. + * @spi_flash_can_dma: analogous to can_dma() interface, but for + * controllers implementing spi_flash_read. * @flash_read_supported: spi device supports flash read * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS * number. Any individual value may be -ENOENT for CS lines that @@ -538,6 +540,8 @@ struct spi_master { struct spi_message *message); int (*spi_flash_read)(struct spi_device *spi, struct spi_flash_read_message *msg); + bool (*spi_flash_can_dma)(struct spi_device *spi, + struct spi_flash_read_message *msg); bool (*flash_read_supported)(struct spi_device *spi); /* -- cgit v1.2.3-58-ga151 From c687c46e9e4527c4b4d82bc3cca58c1b08bcfb83 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 11 Apr 2017 17:22:25 +0530 Subject: spi: spi-ti-qspi: Use bounce buffer if read buffer is not DMA'ble Flash filesystems like JFFS2, UBIFS and MTD block layer can provide vmalloc'd or kmap'd buffers that cannot be mapped using dma_map_sg() and can potentially be in memory region above 32bit addressable region(ie buffers belonging to memory region backed by LPAE) of DMA, implement spi_flash_can_dma() interface to inform SPI core not to map such buffers. When buffers are not mapped for DMA, then use a pre allocated bounce buffer(64K = typical flash erase sector size) to read from flash and then do a copy to actual destination buffer. This is approach is much faster than using memcpy using CPU and also reduces CPU load. With this patch, UBIFS read speed is ~18MB/s and CPU utilization <20% on DRA74 Rev H EVM. Performance degradation is negligible when compared with non bounce buffer case while using UBIFS. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- drivers/spi/spi-ti-qspi.c | 66 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 59 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 804914ebfd9d..23a06148b8ae 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -57,6 +58,8 @@ struct ti_qspi { struct ti_qspi_regs ctx_reg; dma_addr_t mmap_phys_base; + dma_addr_t rx_bb_dma_addr; + void *rx_bb_addr; struct dma_chan *rx_chan; u32 spi_max_frequency; @@ -126,6 +129,8 @@ struct ti_qspi { #define QSPI_SETUP_ADDR_SHIFT 8 #define QSPI_SETUP_DUMMY_SHIFT 10 +#define QSPI_DMA_BUFFER_SIZE SZ_64K + static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, unsigned long reg) { @@ -429,6 +434,35 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, return 0; } +static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, + struct spi_flash_read_message *msg) +{ + size_t readsize = msg->len; + void *to = msg->buf; + dma_addr_t dma_src = qspi->mmap_phys_base + msg->from; + int ret = 0; + + /* + * Use bounce buffer as FS like jffs2, ubifs may pass + * buffers that does not belong to kernel lowmem region. + */ + while (readsize != 0) { + size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE, + readsize); + + ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, + dma_src, xfer_len); + if (ret != 0) + return ret; + memcpy(to, qspi->rx_bb_addr, xfer_len); + readsize -= xfer_len; + dma_src += xfer_len; + to += xfer_len; + } + + return ret; +} + static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, loff_t from) { @@ -496,6 +530,12 @@ static void ti_qspi_setup_mmap_read(struct spi_device *spi, QSPI_SPI_SETUP_REG(spi->chip_select)); } +static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi, + struct spi_flash_read_message *msg) +{ + return virt_addr_valid(msg->buf); +} + static int ti_qspi_spi_flash_read(struct spi_device *spi, struct spi_flash_read_message *msg) { @@ -509,15 +549,12 @@ static int ti_qspi_spi_flash_read(struct spi_device *spi, ti_qspi_setup_mmap_read(spi, msg); if (qspi->rx_chan) { - if (msg->cur_msg_mapped) { + if (msg->cur_msg_mapped) ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from); - if (ret) - goto err_unlock; - } else { - dev_err(qspi->dev, "Invalid address for DMA\n"); - ret = -EIO; + else + ret = ti_qspi_dma_bounce_buffer(qspi, msg); + if (ret) goto err_unlock; - } } else { memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len); } @@ -718,6 +755,17 @@ static int ti_qspi_probe(struct platform_device *pdev) ret = 0; goto no_dma; } + qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, + QSPI_DMA_BUFFER_SIZE, + &qspi->rx_bb_dma_addr, + GFP_KERNEL | GFP_DMA); + if (!qspi->rx_bb_addr) { + dev_err(qspi->dev, + "dma_alloc_coherent failed, using PIO mode\n"); + dma_release_channel(qspi->rx_chan); + goto no_dma; + } + master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma; master->dma_rx = qspi->rx_chan; init_completion(&qspi->transfer_complete); if (res_mmap) @@ -757,6 +805,10 @@ static int ti_qspi_remove(struct platform_device *pdev) pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + if (qspi->rx_bb_addr) + dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, + qspi->rx_bb_addr, + qspi->rx_bb_dma_addr); if (qspi->rx_chan) dma_release_channel(qspi->rx_chan); -- cgit v1.2.3-58-ga151 From bfca76185d9bd5b3de562bf5023e5d3dddaa9dce Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sun, 23 Apr 2017 18:14:36 +0100 Subject: spi: tegra: fix spelling mistake: "trasfer" -> "transfer" trivial fix to spelling mistake in dbg_err messages Signed-off-by: Colin Ian King Signed-off-by: Mark Brown --- drivers/spi/spi-tegra114.c | 2 +- drivers/spi/spi-tegra20-sflash.c | 2 +- drivers/spi/spi-tegra20-slink.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 73779cecc3bb..08012ae5aa66 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -837,7 +837,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, SPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tspi->dev, - "spi trasfer timeout, err %d\n", ret); + "spi transfer timeout, err %d\n", ret); ret = -EIO; goto complete_xfer; } diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index b6558bb6f9df..2c797ee2664d 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c @@ -341,7 +341,7 @@ static int tegra_sflash_transfer_one_message(struct spi_master *master, SPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tsd->dev, - "spi trasfer timeout, err %d\n", ret); + "spi transfer timeout, err %d\n", ret); ret = -EIO; goto exit; } diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index 85c91f58b42f..0c06ce424210 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -824,7 +824,7 @@ static int tegra_slink_transfer_one(struct spi_master *master, SLINK_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tspi->dev, - "spi trasfer timeout, err %d\n", ret); + "spi transfer timeout, err %d\n", ret); return -EIO; } -- cgit v1.2.3-58-ga151 From f72efa7e690ab5c4068ccba31c4da032bc45c29c Mon Sep 17 00:00:00 2001 From: Leif Middelschulte Date: Sun, 23 Apr 2017 21:19:58 +0200 Subject: spi-imx: Implements handling of the SPI_READY mode flag. This patch implements consideration of the SPI_READY mode flag as defined in spi.h. It extends the device tree bindings to support the values defined by the reference manual for the DRCTL field. Thus supporting edge-triggered and level-triggered bursts. Signed-off-by: Leif Middelschulte Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/fsl-imx-cspi.txt | 7 +++++++ drivers/spi/spi-imx.c | 20 ++++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 8bc95e2fc47f..31b5b21598ff 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -23,6 +23,12 @@ See the clock consumer binding, Obsolete properties: - fsl,spi-num-chipselects : Contains the number of the chipselect +Optional properties: +- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register +controlling the SPI_READY handling. Note that to enable the DRCTL consideration, +the SPI_READY mode-flag needs to be set too. +Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). + Example: ecspi@70010000 { @@ -35,4 +41,5 @@ ecspi@70010000 { <&gpio3 25 0>; /* GPIO3_25 */ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; + fsl,spi-rdy-drctl = <1>; }; diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 9a7c62f471dc..b402530a7a9a 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -95,6 +95,7 @@ struct spi_imx_data { unsigned int spi_bus_clk; unsigned int bytes_per_word; + unsigned int spi_drctl; unsigned int count; void (*tx)(struct spi_imx_data *); @@ -246,6 +247,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, #define MX51_ECSPI_CTRL_XCH (1 << 2) #define MX51_ECSPI_CTRL_SMC (1 << 3) #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) +#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) @@ -355,6 +357,12 @@ static int mx51_ecspi_config(struct spi_device *spi, */ ctrl |= MX51_ECSPI_CTRL_MODE_MASK; + /* + * Enable SPI_RDY handling (falling edge/level triggered). + */ + if (spi->mode & SPI_READY) + ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); + /* set clock speed */ ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); spi_imx->spi_bus_clk = clk; @@ -1173,7 +1181,7 @@ static int spi_imx_probe(struct platform_device *pdev) struct spi_master *master; struct spi_imx_data *spi_imx; struct resource *res; - int i, ret, irq; + int i, ret, irq, spi_drctl; if (!np && !mxc_platform_info) { dev_err(&pdev->dev, "can't get the platform data\n"); @@ -1181,6 +1189,12 @@ static int spi_imx_probe(struct platform_device *pdev) } master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); + ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); + if ((ret < 0) || (spi_drctl >= 0x3)) { + /* '11' is reserved */ + spi_drctl = 0; + } + if (!master) return -ENOMEM; @@ -1216,7 +1230,9 @@ static int spi_imx_probe(struct platform_device *pdev) spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) - spi_imx->bitbang.master->mode_bits |= SPI_LOOP; + spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; + + spi_imx->spi_drctl = spi_drctl; init_completion(&spi_imx->xfer_done); -- cgit v1.2.3-58-ga151 From b42a33bd93fe0b2438511b1c7c00cfd47e17841b Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Tue, 25 Apr 2017 11:30:14 -0700 Subject: spi: cadence: Allow for GPIO pins to be used as chipselects This adds support for using GPIOs for chipselects as described by the default dt-bindings. Signed-off-by: Moritz Fischer Signed-off-by: Mark Brown --- drivers/spi/spi-cadence.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 1c57ce64abba..f0b5c7b91f37 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -127,6 +128,10 @@ struct cdns_spi { u32 is_decoded_cs; }; +struct cdns_spi_device_data { + bool gpio_requested; +}; + /* Macros for the SPI controller read/write */ static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) { @@ -456,6 +461,64 @@ static int cdns_unprepare_transfer_hardware(struct spi_master *master) return 0; } +static int cdns_spi_setup(struct spi_device *spi) +{ + + int ret = -EINVAL; + struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi); + + /* this is a pin managed by the controller, leave it alone */ + if (spi->cs_gpio == -ENOENT) + return 0; + + /* this seems to be the first time we're here */ + if (!cdns_spi_data) { + cdns_spi_data = kzalloc(sizeof(*cdns_spi_data), GFP_KERNEL); + if (!cdns_spi_data) + return -ENOMEM; + cdns_spi_data->gpio_requested = false; + spi_set_ctldata(spi, cdns_spi_data); + } + + /* if we haven't done so, grab the gpio */ + if (!cdns_spi_data->gpio_requested && gpio_is_valid(spi->cs_gpio)) { + ret = gpio_request_one(spi->cs_gpio, + (spi->mode & SPI_CS_HIGH) ? + GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH, + dev_name(&spi->dev)); + if (ret) + dev_err(&spi->dev, "can't request chipselect gpio %d\n", + spi->cs_gpio); + else + cdns_spi_data->gpio_requested = true; + } else { + if (gpio_is_valid(spi->cs_gpio)) { + int mode = ((spi->mode & SPI_CS_HIGH) ? + GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH); + + ret = gpio_direction_output(spi->cs_gpio, mode); + if (ret) + dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n", + spi->cs_gpio, ret); + } + } + + return ret; +} + +static void cdns_spi_cleanup(struct spi_device *spi) +{ + struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi); + + if (cdns_spi_data) { + if (cdns_spi_data->gpio_requested) + gpio_free(spi->cs_gpio); + kfree(cdns_spi_data); + spi_set_ctldata(spi, NULL); + } + +} + /** * cdns_spi_probe - Probe method for the SPI driver * @pdev: Pointer to the platform_device structure @@ -555,6 +618,8 @@ static int cdns_spi_probe(struct platform_device *pdev) master->transfer_one = cdns_transfer_one; master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; master->set_cs = cdns_spi_chipselect; + master->setup = cdns_spi_setup; + master->cleanup = cdns_spi_cleanup; master->auto_runtime_pm = true; master->mode_bits = SPI_CPOL | SPI_CPHA; -- cgit v1.2.3-58-ga151