From 83edd73a9cfd03dad9052abec31d9fb16a28543d Mon Sep 17 00:00:00 2001 From: Darren Etheridge Date: Fri, 23 Aug 2013 16:52:51 -0500 Subject: video: da8xx-fb: fixing timing off by one errors The LCD controller represents some of the timing fields with a 0 in the register representing 1. This was not taken into account when these registers were being set. Interestingly enough not all of the LCDC controller timing registers implement this representation so carefully went through the technical reference manual to only "fix" the correct timings. Signed-off-by: Darren Etheridge Signed-off-by: Tomi Valkeinen --- drivers/video/da8xx-fb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 0a0983f88075..7dfa7a70fcfe 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -407,9 +407,9 @@ static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, u32 reg; reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; - reg |= ((back_porch & 0xff) << 24) - | ((front_porch & 0xff) << 16) - | ((pulse_width & 0x3f) << 10); + reg |= (((back_porch-1) & 0xff) << 24) + | (((front_porch-1) & 0xff) << 16) + | (((pulse_width-1) & 0x3f) << 10); lcdc_write(reg, LCD_RASTER_TIMING_0_REG); } @@ -421,7 +421,7 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; reg |= ((back_porch & 0xff) << 24) | ((front_porch & 0xff) << 16) - | ((pulse_width & 0x3f) << 10); + | (((pulse_width-1) & 0x3f) << 10); lcdc_write(reg, LCD_RASTER_TIMING_1_REG); } -- cgit v1.2.3-58-ga151