From aeb8f8cb1537450e99f7d8f1a1d84d55b0fc6b26 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Fri, 5 Aug 2016 09:36:03 -0400 Subject: spi: rspi: Increase accuracy of bit rate for RZ When you leave the clock divider at 0, 130kHz is the lowest you can go. Also, by adjusting the clock divider you can get more accurate resolutions for clock speeds lower than 16MHz. This patch uses the clock divider as part of the bit rate setup. Signed-off-by: Chris Brandt Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers/spi/spi-rspi.c') diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 818843336932..a816f07e168e 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -295,14 +295,24 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) { int spbr; + int div = 0; + unsigned long clksrc; /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); + clksrc = clk_get_rate(rspi->clk); + while (div < 3) { + if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ + break; + div++; + clksrc /= 2; + } + /* Sets transfer bit rate */ - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), - 2 * rspi->max_speed_hz) - 1; + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); + rspi->spcmd |= div << 2; /* Disable dummy transmission, set byte access */ rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); -- cgit v1.2.3-58-ga151