From 970f6cf2e91465c53dbbf9d80d755a7e8139fedb Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 21:17:16 +0100 Subject: ARM: exynos: Simplify code in Exynos3250 CPU core restart path exynos_core_restart() is called by secondary CPU boot procedure, used by CPU hotplug and coupled CPU idle. Replace of_machine_is_compatible() call with a simple SoC revision check. of_machine_is_compatible() function performs a dozen of string comparisons during the full device tree walk, while soc_is_exynos3250() is a simple integer check on SoC revision variable. This change also fixes the following warning: ============================= WARNING: suspicious RCU usage 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Not tainted ----------------------------- ./include/trace/events/lock.h:37 suspicious rcu_dereference_check() usage! other info that might help us debug this: rcu_scheduler_active = 2, debug_locks = 1 RCU used illegally from extended quiescent state! no locks held by swapper/0/0. stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Hardware name: Samsung Exynos (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0xb4/0xd4) [] (dump_stack) from [] (lock_acquire+0x418/0x584) [] (lock_acquire) from [] (_raw_spin_lock_irqsave+0x4c/0x60) [] (_raw_spin_lock_irqsave) from [] (of_device_is_compatible+0x1c/0x4c) [] (of_device_is_compatible) from [] (exynos_core_restart+0x14/0xb0) [] (exynos_core_restart) from [] (exynos_cpu0_enter_aftr+0x1d0/0x1dc) [] (exynos_cpu0_enter_aftr) from [] (exynos_enter_coupled_lowpower+0x44/0x74) [] (exynos_enter_coupled_lowpower) from [] (cpuidle_enter_state+0x178/0x660) [] (cpuidle_enter_state) from [] (cpuidle_enter_state_coupled+0x35c/0x378) [] (cpuidle_enter_state_coupled) from [] (cpuidle_enter+0x50/0x54) [] (cpuidle_enter) from [] (do_idle+0x224/0x2a4) [] (do_idle) from [] (cpu_startup_entry+0x18/0x1c) [] (cpu_startup_entry) from [] (start_kernel+0x640/0x67c) [] (start_kernel) from [<00000000>] (0x0) Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027201716.15745-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index d7fedbb2eefe..ea0be59f469a 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -215,7 +215,7 @@ void exynos_core_restart(u32 core_id) unsigned int timeout = 16; u32 val; - if (!of_machine_is_compatible("samsung,exynos3250")) + if (!soc_is_exynos3250()) return; while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) { -- cgit v1.2.3-58-ga151 From 2f4ac2d79eb4c09ee6dbda1d2fc2616f281094f9 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 27 Sep 2020 15:03:13 +0800 Subject: ARM: imx: Add revision support for i.MX7ULP revision 2.2 On i.MX7ULP revision 2.2, the value is 3, so add support for this revision, otherwise, it will use default revision of 1.0 which is incorrect. Signed-off-by: Anson Huang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 445256e6a4a0..f6032ea7de8b 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -45,6 +45,9 @@ static void __init imx7ulp_set_revision(void) case 2: imx_set_soc_revision(IMX_CHIP_REVISION_2_1); break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; default: imx_set_soc_revision(IMX_CHIP_REVISION_1_0); break; -- cgit v1.2.3-58-ga151 From 5a76c474e8b940dc324eed4e10d486405c4110d7 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Mon, 10 Aug 2020 13:22:08 +0100 Subject: ARM: exynos: clear prefetch bits in default l2c_aux_val Clear the L310_AUX_CTRL_DATA_PREFETCH and L310_AUX_CTRL_INSTR_PREFETCH bits in the l2c_aux_val defaults for Exynos since they can now be set using the standard l2c2x0 devicetree bindings. Signed-off-by: Guillaume Tucker Link: https://lore.kernel.org/r/e44b5226f3ad1551459830c678ed183762d8e458.1597061474.git.guillaume.tucker@collabora.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 700763e07083..a99d8eba4bb3 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -206,8 +206,8 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x38400000, - .l2c_aux_mask = 0xc60fffff, + .l2c_aux_val = 0x08400000, + .l2c_aux_mask = 0xf60fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init, -- cgit v1.2.3-58-ga151 From ba66a25536dd24b73d36e380c68593e95e4e06a8 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 20 Oct 2020 09:50:34 +0200 Subject: arm64: meson: ship only the necessary clock controllers There now the menu entries for the amlogic clock controllers. Do not select these when ARM64 is enabled so it possible to ship only the required. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201020075034.172825-1-jbrunet@baylibre.com --- arch/arm64/Kconfig.platforms | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6f2494dd6d60..329e22c09cad 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -153,9 +153,6 @@ config ARCH_MESON bool "Amlogic Platforms" select PINCTRL select PINCTRL_MESON - select COMMON_CLK_GXBB - select COMMON_CLK_AXG - select COMMON_CLK_G12A select MESON_IRQ_GPIO help This enables support for the arm64 based Amlogic SoCs -- cgit v1.2.3-58-ga151 From 7544bfc0866f56326e47f8ec8b3f68c6db496125 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Nov 2020 19:04:54 -0300 Subject: ARM: imx: imx7ulp: Add a comment explaining the B2 silicon version To help the users to understand the meaning of bits 31-28 of the JTAG_ID_REG register, add a comment explaining the value that is expected from a i.MX7ULP rev B2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index f6032ea7de8b..a3c8dadec1c5 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -37,6 +37,7 @@ static void __init imx7ulp_set_revision(void) * bit[31:28] of JTAG_ID register defines revision as below from B0: * 0001 B0 * 0010 B1 + * 0011 B2 */ switch (revision >> 28) { case 1: -- cgit v1.2.3-58-ga151 From 53cc6bc69e536efe6c1cef98edfb7b3f0a14fabe Mon Sep 17 00:00:00 2001 From: Sven Van Asbroeck Date: Wed, 4 Nov 2020 11:54:18 -0500 Subject: ARM: imx: mach-imx6q: correctly identify i.MX6QP SoCs The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux: the log (incorrectly) shows "i.MX6Q rev 2.1". Correct this by assuming that every SoC that identifies as i.MX6Q with rev >= 2.0 is really an i.MX6QP. Signed-off-by: Sven Van Asbroeck Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6q.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..703998ebb52e 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -245,8 +245,13 @@ static void __init imx6q_axi_init(void) static void __init imx6q_init_machine(void) { - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) - imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + /* + * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. + * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), + * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. + */ + imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); -- cgit v1.2.3-58-ga151 From f9135aaf2767500dee419c03640f7a3784b56559 Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 13 Nov 2020 22:25:26 +0100 Subject: ARM: exynos: extend cpuidle support to P4 Note boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The P4 Note family supports cpuidle, so allow it to make use of this feature. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-6-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index a99d8eba4bb3..25b01da4771b 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -177,7 +177,8 @@ static void __init exynos_dt_machine_init(void) if (of_machine_is_compatible("samsung,exynos4210") || (of_machine_is_compatible("samsung,exynos4412") && (of_machine_is_compatible("samsung,trats2") || - of_machine_is_compatible("samsung,midas"))) || + of_machine_is_compatible("samsung,midas") || + of_machine_is_compatible("samsung,p4note"))) || of_machine_is_compatible("samsung,exynos3250") || of_machine_is_compatible("samsung,exynos5250")) platform_device_register(&exynos_cpuidle); -- cgit v1.2.3-58-ga151 From 3c5902d270edb6ccc3049acfe5d3e96653c87dcd Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:06:58 +0800 Subject: ARM: OMAP2+: Fix memleak in omap2xxx_clkt_vps_init If the clk_register fails, we should free hw before function returns to prevent memleak. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 2a3e72286d3a..70892b3da28d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -244,6 +244,12 @@ void omap2xxx_clkt_vps_init(void) hw->hw.init = &init; clk = clk_register(NULL, &hw->hw); + if (IS_ERR(clk)) { + printk(KERN_ERR "Failed to register clock\n"); + kfree(hw); + return; + } + clkdev_create(clk, "cpufreq_ck", NULL); return; cleanup: -- cgit v1.2.3-58-ga151 From c3f244d5776ecd236657fc1c4b7c5d1d4d01ca7e Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:07:20 +0800 Subject: ARM: OMAP2+: Fix kfree NULL pointer in omap2xxx_clkt_vps_init The returns pointer is NULL when kzalloc fails to apply for space, so fix kfree NULL pointer. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 70892b3da28d..edf046b470ba 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -235,7 +235,7 @@ void omap2xxx_clkt_vps_init(void) hw = kzalloc(sizeof(*hw), GFP_KERNEL); if (!hw) - goto cleanup; + return; init.name = "virt_prcm_set"; init.ops = &virt_prcm_set_ops; init.parent_names = &parent_name; @@ -251,8 +251,5 @@ void omap2xxx_clkt_vps_init(void) } clkdev_create(clk, "cpufreq_ck", NULL); - return; -cleanup: - kfree(hw); } #endif -- cgit v1.2.3-58-ga151 From 6d9be9376b0e29211b6e6c1775ba6f81fb6c4ea5 Mon Sep 17 00:00:00 2001 From: Jing Xiangfeng Date: Sat, 19 Sep 2020 11:43:31 +0800 Subject: ARM: OMAP2+: Remove redundant assignment to variable ret The variable ret has been initialized with '-ENOMEM'. The assignment in the if branch is redundant. So remove it. Signed-off-by: Jing Xiangfeng Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fc7bb2ca1672..f3191704cab9 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -334,10 +334,9 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **hwmods; od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); - if (!od) { - ret = -ENOMEM; + if (!od) goto oda_exit1; - } + od->hwmods_cnt = oh_cnt; hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL); -- cgit v1.2.3-58-ga151 From e106698cbb901d9b74dea4c9a3b5a7e6598ae481 Mon Sep 17 00:00:00 2001 From: Xu Wang Date: Wed, 4 Nov 2020 06:45:05 +0000 Subject: ARM: OMAP2+: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/display.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 2000fca6bd4e..6daaa645ae5d 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -385,8 +385,7 @@ int omap_dss_reset(struct omap_hwmod *oh) } for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -412,8 +411,7 @@ int omap_dss_reset(struct omap_hwmod *oh) pr_debug("dss_core: softreset done\n"); for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; -- cgit v1.2.3-58-ga151 From 2e023b938048c9857af09b96ce672e9a31dbfb38 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Thu, 10 Sep 2020 19:06:40 +0800 Subject: ARM: OMAP1: clock: Use IS_ERR_OR_NULL() to clean code Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by: Zhang Shengju Signed-off-by: Tang Bin Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index bd5be82101f3..9d4a0ab50a46 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -612,7 +612,7 @@ int clk_enable(struct clk *clk) unsigned long flags; int ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); @@ -627,7 +627,7 @@ void clk_disable(struct clk *clk) { unsigned long flags; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; spin_lock_irqsave(&clockfw_lock, flags); @@ -650,7 +650,7 @@ unsigned long clk_get_rate(struct clk *clk) unsigned long flags; unsigned long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -670,7 +670,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) unsigned long flags; long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -686,7 +686,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) unsigned long flags; int ret = -EINVAL; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return ret; spin_lock_irqsave(&clockfw_lock, flags); @@ -791,7 +791,7 @@ void clk_preinit(struct clk *clk) int clk_register(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; /* @@ -817,7 +817,7 @@ EXPORT_SYMBOL(clk_register); void clk_unregister(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; mutex_lock(&clocks_mutex); -- cgit v1.2.3-58-ga151 From ae04aad75b3718b84df559bb0352f27695045fe0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:16 +0100 Subject: ARM: shmobile: r8a7778: Introduce HPBREG_BASE Replace the hardcoded address of the HPB Register block by a macro. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-2-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7778.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 2bc93f391bcf..819dbda47298 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -14,6 +14,8 @@ #include "common.h" +#define HPBREG_BASE 0xfe700000 + #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ @@ -22,7 +24,7 @@ static void __init r8a7778_init_irq_dt(void) { - void __iomem *base = ioremap(0xfe700000, 0x00100000); + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); BUG_ON(!base); -- cgit v1.2.3-58-ga151 From caf67a935740d7a4e9a7b0a3176237ad22a677e8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:17 +0100 Subject: ARM: shmobile: r8a7779: Use ioremap() to map INTC2 registers Replace using the legacy IOMEM() macro to map various registers related to INTC2 configuration by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-3-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 86406e3f9b22..07c1bc96d4d9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -38,30 +38,36 @@ static void __init r8a7779_map_io(void) iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); } +#define HPBREG_BASE 0xfe700000 + /* IRQ */ -#define INT2SMSKCR0 IOMEM(0xfe7822a0) -#define INT2SMSKCR1 IOMEM(0xfe7822a4) -#define INT2SMSKCR2 IOMEM(0xfe7822a8) -#define INT2SMSKCR3 IOMEM(0xfe7822ac) -#define INT2SMSKCR4 IOMEM(0xfe7822b0) +#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */ +#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */ +#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */ +#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */ +#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */ -#define INT2NTSR0 IOMEM(0xfe700060) -#define INT2NTSR1 IOMEM(0xfe700064) +#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */ +#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */ static void __init r8a7779_init_irq_dt(void) { + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); + irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, INT2NTSR0); - __raw_writel(0x3fffffff, INT2NTSR1); + __raw_writel(0xffffffff, base + INT2NTSR0); + __raw_writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, INT2SMSKCR0); - __raw_writel(0xfff7ffff, INT2SMSKCR1); - __raw_writel(0xfffbffdf, INT2SMSKCR2); - __raw_writel(0xbffffffc, INT2SMSKCR3); - __raw_writel(0x003fee3f, INT2SMSKCR4); + __raw_writel(0xfffffff0, base + INT2SMSKCR0); + __raw_writel(0xfff7ffff, base + INT2SMSKCR1); + __raw_writel(0xfffbffdf, base + INT2SMSKCR2); + __raw_writel(0xbffffffc, base + INT2SMSKCR3); + __raw_writel(0x003fee3f, base + INT2SMSKCR4); + + iounmap(base); } static const char *const r8a7779_compat_dt[] __initconst = { -- cgit v1.2.3-58-ga151 From 617ff9e657c4c4a6ffca325740e36d0d5e1f636e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:18 +0100 Subject: ARM: shmobile: r8a7779: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map the ARM Reset Vector Address Register (AVECR) by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-4-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-r8a7779.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 0ed73b650c14..f6713886ee16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -20,8 +20,10 @@ #include "common.h" #include "r8a7779.h" -#define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE 0xf0000000 +#define HPBREG_BASE 0xfe700000 +#define AVECR 0x0040 /* ARM Reset Vector Address Register */ + +#define R8A7779_SCU_BASE 0xf0000000 static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -36,11 +38,15 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *base = ioremap(HPBREG_BASE, 0x1000); + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), AVECR); + __raw_writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); + + iounmap(base); } #ifdef CONFIG_HOTPLUG_CPU -- cgit v1.2.3-58-ga151 From 5b0480f53dbfe58b6aa291f462a708f178c4bd40 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:19 +0100 Subject: ARM: shmobile: r8a7779: Remove obsolete static mappings There are no more users of the statically mapped IOMEM regions on R-Car H1. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-5-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 07c1bc96d4d9..446d40b50b7b 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -15,29 +15,6 @@ #include "common.h" #include "r8a7779.h" -static struct map_desc r8a7779_io_desc[] __initdata = { - /* 2M identity mapping for 0xf0000000 (MPCORE) */ - { - .virtual = 0xf0000000, - .pfn = __phys_to_pfn(0xf0000000), - .length = SZ_2M, - .type = MT_DEVICE_NONSHARED - }, - /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ - { - .virtual = 0xfe000000, - .pfn = __phys_to_pfn(0xfe000000), - .length = SZ_16M, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init r8a7779_map_io(void) -{ - debug_ll_io_init(); - iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); -} - #define HPBREG_BASE 0xfe700000 /* IRQ */ @@ -77,7 +54,6 @@ static const char *const r8a7779_compat_dt[] __initconst = { DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .smp = smp_ops(r8a7779_smp_ops), - .map_io = r8a7779_map_io, .init_irq = r8a7779_init_irq_dt, .init_late = shmobile_init_late, .dt_compat = r8a7779_compat_dt, -- cgit v1.2.3-58-ga151 From cc85e21d6d18ffea52eef061f987978153c2aa0a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:20 +0100 Subject: ARM: shmobile: sh73a0: Use ioremap() to map L2C registers Replace using the legacy IOMEM() macro to map the L2C registers by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-6-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index eb4a62fa4289..e2fcfe1e4f24 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -44,7 +44,7 @@ static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); + l2x0_init(ioremap(0xf0100000, PAGE_SIZE), 0x00400000, 0xc20f0fff); #endif } -- cgit v1.2.3-58-ga151 From a0a6624dbec851ab5c136efbecd87a49617a5cc9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:21 +0100 Subject: ARM: shmobile: sh73a0: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map various registers related to secondary CPU bringup by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-7-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-sh73a0.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0403aa8629dd..6d892d11d81c 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -16,31 +16,42 @@ #include "common.h" #include "sh73a0.h" -#define WUPCR IOMEM(0xe6151010) -#define SRESCR IOMEM(0xe6151018) -#define PSTR IOMEM(0xe6151040) -#define SBAR IOMEM(0xe6180020) -#define APARMBAREA IOMEM(0xe6f10020) +#define CPG_BASE2 0xe6151000 +#define WUPCR 0x10 /* System-CPU Wake Up Control Register */ +#define SRESCR 0x18 /* System-CPU Software Reset Control Register */ +#define PSTR 0x40 /* System-CPU Power Status Register */ + +#define SYSC_BASE 0xe6180000 +#define SBAR 0x20 /* SYS Boot Address Register */ + +#define AP_BASE 0xe6f10000 +#define APARMBAREA 0x20 /* Address Translation Area Register */ #define SH73A0_SCU_BASE 0xf0000000 static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int lcpu = cpu_logical_map(cpu); + void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, WUPCR); /* wake up */ + if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, SRESCR); /* reset */ - + __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + iounmap(cpg2); return 0; } static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE); + void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); + /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), SBAR); + __raw_writel(0, ap + APARMBAREA); /* 4k */ + __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + iounmap(sysc); + iounmap(ap); /* setup sh73a0 specific SCU bits */ shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus); -- cgit v1.2.3-58-ga151 From 5705747c0c8f90aee5a433a94f58c9ffad8a5a37 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:22 +0100 Subject: ARM: shmobile: sh73a0: Remove obsolete static mapping There are no more users of the statically mapped IOMEM region on SH-Mobile AG5. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-8-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index e2fcfe1e4f24..890bf537b7de 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,24 +22,6 @@ #include "common.h" #include "sh73a0.h" -static struct map_desc sh73a0_io_desc[] __initdata = { - /* create a 1:1 identity mapping for 0xe6xxxxxx - * used by CPGA, INTC and PFC. - */ - { - .virtual = 0xe6000000, - .pfn = __phys_to_pfn(0xe6000000), - .length = 256 << 20, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init sh73a0_map_io(void) -{ - debug_ll_io_init(); - iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); -} - static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 @@ -55,7 +37,6 @@ static const char *const sh73a0_boards_compat_dt[] __initconst = { DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), - .map_io = sh73a0_map_io, .init_machine = sh73a0_generic_init, .init_late = shmobile_init_late, .dt_compat = sh73a0_boards_compat_dt, -- cgit v1.2.3-58-ga151 From d4a617c9bbef94e4a776901cf12c95eafd54504a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 15:24:47 +0100 Subject: ARM: shmobile: Stop using __raw_*() I/O accessors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM platform code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201117142447.2205664-1-geert+renesas@glider.be --- arch/arm/mach-shmobile/platsmp-scu.c | 2 +- arch/arm/mach-shmobile/setup-r8a7778.c | 8 ++++---- arch/arm/mach-shmobile/setup-r8a7779.c | 14 +++++++------- arch/arm/mach-shmobile/smp-r8a7779.c | 2 +- arch/arm/mach-shmobile/smp-sh73a0.c | 10 +++++----- 5 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index fcfcef1d1ae4..3849f71e6e12 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c @@ -64,7 +64,7 @@ static int shmobile_smp_scu_psr_core_disabled(int cpu) { unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + if ((readl(shmobile_scu_base + 8) & mask) == mask) return 1; return 0; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 819dbda47298..02cda9cada4c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -31,12 +31,12 @@ static void __init r8a7778_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0x73ffffff, base + INT2NTSR0); - __raw_writel(0xffffffff, base + INT2NTSR1); + writel(0x73ffffff, base + INT2NTSR0); + writel(0xffffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0x08330773, base + INT2SMSKCR0); - __raw_writel(0x00311110, base + INT2SMSKCR1); + writel(0x08330773, base + INT2SMSKCR0); + writel(0x00311110, base + INT2SMSKCR1); iounmap(base); } diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 446d40b50b7b..b6e282116d66 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -34,15 +34,15 @@ static void __init r8a7779_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, base + INT2NTSR0); - __raw_writel(0x3fffffff, base + INT2NTSR1); + writel(0xffffffff, base + INT2NTSR0); + writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, base + INT2SMSKCR0); - __raw_writel(0xfff7ffff, base + INT2SMSKCR1); - __raw_writel(0xfffbffdf, base + INT2SMSKCR2); - __raw_writel(0xbffffffc, base + INT2SMSKCR3); - __raw_writel(0x003fee3f, base + INT2SMSKCR4); + writel(0xfffffff0, base + INT2SMSKCR0); + writel(0xfff7ffff, base + INT2SMSKCR1); + writel(0xfffbffdf, base + INT2SMSKCR2); + writel(0xbffffffc, base + INT2SMSKCR3); + writel(0x003fee3f, base + INT2SMSKCR4); iounmap(base); } diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index f6713886ee16..1bc609986c16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -41,7 +41,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) void __iomem *base = ioremap(HPBREG_BASE, 0x1000); /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), base + AVECR); + writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 6d892d11d81c..453d48865029 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -34,10 +34,10 @@ static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) unsigned int lcpu = cpu_logical_map(cpu); void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ + if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + writel(1 << lcpu, cpg2 + SRESCR); /* reset */ iounmap(cpg2); return 0; } @@ -48,8 +48,8 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, ap + APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + writel(0, ap + APARMBAREA); /* 4k */ + writel(__pa(shmobile_boot_vector), sysc + SBAR); iounmap(sysc); iounmap(ap); -- cgit v1.2.3-58-ga151 From 4ba79e25d7f1a7394021ba4c215a7ecdcc270fb6 Mon Sep 17 00:00:00 2001 From: Ivan Zaentsev Date: Mon, 16 Nov 2020 19:58:26 +0300 Subject: ARM: mxs: Add serial number support for i.MX23, i.MX28 SoCs i.MX23 and i.MX28 SoCs unique identifiers are factory-programmed in On-Chip OTP memory. i.MX28's 64-bit unique id is in HW_OCOTP_OPS2:HW_OCOTP_OPS3 (see MCIMX28 Ref. Man., sec. 20.4.22-23). i.MX23 provides 32-bit long unique id in HW_OCOTP_OPS3. Though not clearly documented, there is a clue in sec. 35.9.3. The unique id is reported in /sys/devices/soc0/serial_number and in /proc/cpuinfo Signed-off-by: Ivan Zaentsev Suggested-by: Evgeny Boger Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/mach-mxs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index c109f47e9cbc..25c9d184fa4c 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "pm.h" @@ -51,6 +52,9 @@ #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +#define HW_OCOTP_OPS2 19 /* offset 0x150 */ +#define HW_OCOTP_OPS3 20 /* offset 0x160 */ + static u32 chipid; static u32 socid; @@ -379,6 +383,8 @@ static void __init mxs_machine_init(void) struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; + u64 soc_uid = 0; + const u32 *ocotp = mxs_get_ocotp(); int ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -394,8 +400,21 @@ static void __init mxs_machine_init(void) soc_dev_attr->soc_id = mxs_get_soc_id(); soc_dev_attr->revision = mxs_get_revision(); + if (socid == HW_DIGCTL_CHIPID_MX23) { + soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3]; + } else if (socid == HW_DIGCTL_CHIPID_MX28) { + soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2]; + soc_uid <<= 32; + system_serial_low = ocotp[HW_OCOTP_OPS3]; + soc_uid |= system_serial_low; + } + + if (soc_uid) + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->serial_number); kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return; -- cgit v1.2.3-58-ga151 From dcb11100cd5d3f5a191b7fba75422e3df792f3ff Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 7 Dec 2020 15:01:56 -0800 Subject: arm64: Kconfig: meson: drop pinctrl Don't automatically select pinctrl drivers, leave it up to defaults in drivers/pinctrl/meson, which default to built-in, but are also now optionally configurable as modules as of commit 9c65441ec823 ("pinctrl/meson: enable building as modules") Signed-off-by: Kevin Hilman Reviewed-by: Jerome Brunet Link: https://lore.kernel.org/r/20201207230156.10198-1-khilman@baylibre.com' Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a75513b4ce6b..d8a4c4a9292c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -152,8 +152,6 @@ config ARCH_MEDIATEK config ARCH_MESON bool "Amlogic Platforms" - select PINCTRL - select PINCTRL_MESON select MESON_IRQ_GPIO help This enables support for the arm64 based Amlogic SoCs -- cgit v1.2.3-58-ga151