From 39d9b77b8debb4746e189aa5b61ae6e81ec5eab8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2015 12:16:47 +0300 Subject: x86/pci/intel_mid_pci: Work around for IRQ0 assignment On Intel Tangier the MMC host controller is wired up to irq 0. But several other devices have irq 0 associated as well due to a bogus PCI configuration. The first initialized driver will acquire irq 0 and make it unavailable for other devices. If the sdhci driver is not the first one it will fail to acquire the interrupt and therefor be non functional. Add a quirk to the pci irq enable function which denies irq 0 to anything else than the MMC host controller driver on Tangier platforms. Fixes: 90b9aacf912a (serial: 8250_pci: add Intel Tangier support) Signed-off-by: Andy Shevchenko Cc: Bjorn Helgaas Link: http://lkml.kernel.org/r/1438161409-4671-2-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/pci/intel_mid_pci.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'arch/x86/pci/intel_mid_pci.c') diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 27062303c881..7553921c146c 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -35,6 +35,9 @@ #define PCIE_CAP_OFFSET 0x100 +/* Quirks for the listed devices */ +#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190 + /* Fixed BAR fields */ #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */ #define PCI_FIXED_BAR_0_SIZE 0x04 @@ -214,10 +217,27 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) if (dev->irq_managed && dev->irq > 0) return 0; - if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) + switch (intel_mid_identify_cpu()) { + case INTEL_MID_CPU_CHIP_TANGIER: polarity = 0; /* active high */ - else + + /* Special treatment for IRQ0 */ + if (dev->irq == 0) { + /* + * TNG has IRQ0 assigned to eMMC controller. But there + * are also other devices with bogus PCI configuration + * that have IRQ0 assigned. This check ensures that + * eMMC gets it. + */ + if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC) + return -EBUSY; + } + break; + default: polarity = 1; /* active low */ + break; + } + ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity); /* -- cgit v1.2.3-58-ga151 From 2a61c8eaf1879db99286c3f5fe5e78086c7edb85 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2015 12:16:48 +0300 Subject: x86/pci/intel_mid_pci: Propagate actual return code mp_map_gsi_to_irq() returns different codes if it fails. intel_mid_pci_irq_enable() hides this under -EBUSY. Return the actual failure code. Signed-off-by: Andy Shevchenko Cc: Bjorn Helgaas Link: http://lkml.kernel.org/r/1438161409-4671-3-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/pci/intel_mid_pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/x86/pci/intel_mid_pci.c') diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 7553921c146c..3361f0aab61c 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -213,6 +213,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) { struct irq_alloc_info info; int polarity; + int ret; if (dev->irq_managed && dev->irq > 0) return 0; @@ -244,8 +245,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to * IOAPIC RTE entries, so we just enable RTE for the device. */ - if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0) - return -EBUSY; + ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info); + if (ret < 0) + return ret; dev->irq_managed = 1; -- cgit v1.2.3-58-ga151 From 0abbdea1e9592fba120521ce22c6c26301e72761 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2015 12:16:49 +0300 Subject: x86/pci/intel_mid_pci: Make intel_mid_pci_ops static This fixes the following sparse warning. arch/x86/pci/intel_mid_pci.c:265:16: warning: symbol 'intel_mid_pci_ops' was not declared. Should it be static? Signed-off-by: Andy Shevchenko Cc: Bjorn Helgaas Link: http://lkml.kernel.org/r/1438161409-4671-4-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/pci/intel_mid_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/x86/pci/intel_mid_pci.c') diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 3361f0aab61c..b096da523794 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -263,7 +263,7 @@ static void intel_mid_pci_irq_disable(struct pci_dev *dev) } } -struct pci_ops intel_mid_pci_ops = { +static struct pci_ops intel_mid_pci_ops = { .read = pci_read, .write = pci_write, }; -- cgit v1.2.3-58-ga151 From 5054e1e63946abff39bc7b154fac049110d9d3bb Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 29 Jul 2015 21:16:19 +0200 Subject: x86/pci/intel_mid_pci: Use proper constants for irq polarity polarity = 0 means active high. Not really intuitive, so people add comments to it instead of just using a self explaining constant. Use the IOAPIC_POL_ constants and get rid of those horrible to read tail comments. Signed-off-by: Thomas Gleixner Cc: Andy Shevchenko Cc: Bjorn Helgaas --- arch/x86/pci/intel_mid_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/x86/pci/intel_mid_pci.c') diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index b096da523794..8b93e634af84 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -220,7 +220,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) switch (intel_mid_identify_cpu()) { case INTEL_MID_CPU_CHIP_TANGIER: - polarity = 0; /* active high */ + polarity = IOAPIC_POL_HIGH; /* Special treatment for IRQ0 */ if (dev->irq == 0) { @@ -235,7 +235,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) } break; default: - polarity = 1; /* active low */ + polarity = IOAPIC_POL_LOW; break; } -- cgit v1.2.3-58-ga151