From 5e7705df28720c424c11bdedf0d568177351c55a Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Mon, 12 Aug 2013 15:25:22 -0400 Subject: tile PCI RC: add comment about "PCI hole" problem Explain the rationale of not overlapping the 64-bit DMA window with the PA range. Signed-off-by: Chris Metcalf --- arch/tile/include/asm/pci.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/tile') diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h index c99ad44233f4..dfedd7ac7298 100644 --- a/arch/tile/include/asm/pci.h +++ b/arch/tile/include/asm/pci.h @@ -122,6 +122,11 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit * devices, we create a separate map region that handles the low * 4GB. + * + * This design lets us avoid the "PCI hole" problem where the host bridge + * won't pass DMA traffic with target addresses that happen to fall within the + * BAR space. This enables us to use all the physical memory for DMA, instead + * of wasting the same amount of physical memory as the BAR window size. */ #define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) -- cgit v1.2.3-58-ga151