From db5489f4be000cbb7e7ce9cc1a264c5d3d25b56f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 9 Dec 2022 23:04:36 +0800 Subject: riscv: Implement semihost.h for earlycon semihost driver Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by: Bin Meng Tested-by: Sergey Matyukevich Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20221209150437.795918-3-bmeng@tinylab.org Signed-off-by: Greg Kroah-Hartman --- arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/riscv/include/asm/semihost.h (limited to 'arch/riscv') diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h new file mode 100644 index 000000000000..557a34938193 --- /dev/null +++ b/arch/riscv/include/asm/semihost.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng + */ + +#ifndef _RISCV_SEMIHOST_H_ +#define _RISCV_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +} + +#endif /* _RISCV_SEMIHOST_H_ */ -- cgit v1.2.3-58-ga151