From c12603e76ef666ce5c51a9d6faf155c9e3de7601 Mon Sep 17 00:00:00 2001 From: Xiao Wang Date: Thu, 16 May 2024 17:04:30 +0800 Subject: riscv, bpf: Optimize zextw insn with Zba extension The Zba extension provides add.uw insn which can be used to implement zext.w with rs2 set as ZERO. Signed-off-by: Xiao Wang Signed-off-by: Daniel Borkmann Tested-by: Pu Lehui Reviewed-by: Andrew Jones Reviewed-by: Pu Lehui Link: https://lore.kernel.org/bpf/20240516090430.493122-1-xiao.w.wang@intel.com --- arch/riscv/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/riscv/Kconfig') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9e87287942dc..6b8f1059594d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -595,6 +595,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) depends on AS_HAS_OPTION_ARCH +config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" + default y + help + Add support for enabling optimisations in the kernel when the Zba + extension is detected at boot. + + The Zba extension provides instructions to accelerate the generation + of addresses that index into arrays of basic data types. + + If you don't know what to do here, say Y. + config RISCV_ISA_ZBB bool "Zbb extension support for bit manipulation instructions" depends on TOOLCHAIN_HAS_ZBB -- cgit v1.2.3-58-ga151