From 175671e75c54cf4b17c71d9c99151dd5635964b1 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Mon, 21 Jun 2010 10:19:50 +0000 Subject: Blackfin: ptrace: enable access to L1 stacks If an app is placing its stack in L1 scratchpad SRAM, make sure ptrace is granted access to it so that gdb can do its thing. Signed-off-by: Barry Song Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/ptrace.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 6ec77685df52..d890c1e35ec6 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -27,6 +27,7 @@ #include #include #include +#include /* * does not yet catch signals sent when the child dies. @@ -135,6 +136,13 @@ static inline int is_user_addr_valid(struct task_struct *child, if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END) return 0; +#ifdef CONFIG_APP_STACK_L1 + if (child->mm->context.l1_stack_save) + if (start >= (unsigned long)l1_stack_base && + start + len < (unsigned long)l1_stack_base + l1_stack_len) + return 0; +#endif + return -EIO; } -- cgit v1.2.3-58-ga151 From 41c3e3346ab8e5caf9e76395bd812fac884ad371 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Tue, 29 Jun 2010 08:43:38 +0000 Subject: Blackfin: access_ok: permit L1 stack When apps run with their stack in L1, some system calls might be made where a buffer is in the stack as an argument. So make sure the core Blackfin access code does not reject this memory location. Signed-off-by: Barry Song Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/process.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index c86a3ed5f48f..cd0c090ebc54 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -493,6 +493,11 @@ int _access_ok(unsigned long addr, unsigned long size) return 1; #endif +#ifndef CONFIG_EXCEPTION_L1_SCRATCH + if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len)) + return 1; +#endif + aret = in_async(addr, size); if (aret < 2) return aret; -- cgit v1.2.3-58-ga151 From 99a5b2878b56d24919eb7e646f2d8e02f63a6efc Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 6 Sep 2010 10:16:04 +0000 Subject: Blackfin: add new cacheflush syscall Flushing caches sometimes requires anomaly workarounds which require supervisor-only insns. Normally we don't need to flush caches from userspace so this isn't a problem, but when gcc generates trampolines on the stack, we do. So add a new syscall for gcc to use modeled after the mips version. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/Kbuild | 1 + arch/blackfin/include/asm/cachectl.h | 20 ++++++++++++++++++++ arch/blackfin/include/asm/ptrace.h | 3 +++ arch/blackfin/include/asm/unistd.h | 3 ++- arch/blackfin/kernel/ptrace.c | 4 ++-- arch/blackfin/kernel/sys_bfin.c | 15 +++++++++++++++ arch/blackfin/mach-common/entry.S | 1 + 7 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 arch/blackfin/include/asm/cachectl.h (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index d9eb29e2555c..9e7c5379d3ff 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -1,4 +1,5 @@ include include/asm-generic/Kbuild.asm header-y += bfin_sport.h +header-y += cachectl.h header-y += fixed_code.h diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h new file mode 100644 index 000000000000..03255df6c1ea --- /dev/null +++ b/arch/blackfin/include/asm/cachectl.h @@ -0,0 +1,20 @@ +/* + * based on the mips/cachectl.h + * + * Copyright 2010 Analog Devices Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h index aaa1c6c2bc19..832d7c009a2c 100644 --- a/arch/blackfin/include/asm/ptrace.h +++ b/arch/blackfin/include/asm/ptrace.h @@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child); /* common code demands this function */ #define ptrace_disable(child) user_disable_single_step(child) +extern int is_user_addr_valid(struct task_struct *child, + unsigned long start, unsigned long len); + /* * Get the address of the live pt_regs for the specified task. * These are saved onto the top kernel stack when the process diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 14fcd254b185..928ae975b87e 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -392,8 +392,9 @@ #define __NR_fanotify_init 371 #define __NR_fanotify_mark 372 #define __NR_prlimit64 373 +#define __NR_cacheflush 374 -#define __NR_syscall 374 +#define __NR_syscall 375 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index d890c1e35ec6..b35839354130 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -114,8 +114,8 @@ put_reg(struct task_struct *task, long regno, unsigned long data) /* * check that an address falls within the bounds of the target process's memory mappings */ -static inline int is_user_addr_valid(struct task_struct *child, - unsigned long start, unsigned long len) +int +is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len) { struct vm_area_struct *vma; struct sram_list_struct *sraml; diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index bdc1e2f0da32..89448ed7065d 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c @@ -21,6 +21,8 @@ #include #include +#include +#include asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) { @@ -70,3 +72,16 @@ asmlinkage int sys_bfin_spinlock(int *p) return ret; } + +SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op) +{ + if (is_user_addr_valid(current, addr, len) != 0) + return -EINVAL; + + if (op & DCACHE) + blackfin_dcache_flush_range(addr, addr + len); + if (op & ICACHE) + blackfin_icache_flush_range(addr, addr + len); + + return 0; +} diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 16ea779c3a6f..2ca915ee181f 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1737,6 +1737,7 @@ ENTRY(_sys_call_table) .long _sys_fanotify_init .long _sys_fanotify_mark .long _sys_prlimit64 + .long _sys_cacheflush .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall -- cgit v1.2.3-58-ga151 From 05bbec38dbafa60583be8347dea88919d48cc733 Mon Sep 17 00:00:00 2001 From: steven miao Date: Fri, 17 Sep 2010 03:03:17 +0000 Subject: Blackfin: gpio: add peripheral group check Many Blackfin parts group sets of pins into a single functional unit. This means you cannot use different pins within a group for different peripherals. Our resource conflict checking thus far has been limited to individual pins, so if someone tried to grab a different pin from the same group, it would be allowed while silently changing the other pins in the same group. One common example is the pin set PG12 - PG15 on BF51x parts. They may either be used with SPI0 (1st function), or they may be used with PTP/PWM/AMS3 (3rd function). Ideally, we'd like to use PG12 - PG14 for SPI0 while using PG15 with AMS3, but the hardware does not permit this. In the past, the software would allow the pins to be requested this way, but ultimately things like the Blackfin SPI driver would stop working when the hardware rerouted to a different peripheral. Signed-off-by: steven miao Signed-off-by: Mike Frysinger --- arch/blackfin/kernel/bfin_gpio.c | 185 +++++++++++++++++++++++++-------------- 1 file changed, 118 insertions(+), 67 deletions(-) (limited to 'arch/blackfin/kernel') diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index ca1c1f9debd6..170cf90735ba 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -1,7 +1,7 @@ /* * GPIO Abstraction Layer * - * Copyright 2006-2009 Analog Devices Inc. + * Copyright 2006-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ @@ -215,82 +215,91 @@ static void port_setup(unsigned gpio, unsigned short usage) } #ifdef BF537_FAMILY -static struct { - unsigned short res; - unsigned short offset; -} port_mux_lut[] = { - {.res = P_PPI0_D13, .offset = 11}, - {.res = P_PPI0_D14, .offset = 11}, - {.res = P_PPI0_D15, .offset = 11}, - {.res = P_SPORT1_TFS, .offset = 11}, - {.res = P_SPORT1_TSCLK, .offset = 11}, - {.res = P_SPORT1_DTPRI, .offset = 11}, - {.res = P_PPI0_D10, .offset = 10}, - {.res = P_PPI0_D11, .offset = 10}, - {.res = P_PPI0_D12, .offset = 10}, - {.res = P_SPORT1_RSCLK, .offset = 10}, - {.res = P_SPORT1_RFS, .offset = 10}, - {.res = P_SPORT1_DRPRI, .offset = 10}, - {.res = P_PPI0_D8, .offset = 9}, - {.res = P_PPI0_D9, .offset = 9}, - {.res = P_SPORT1_DRSEC, .offset = 9}, - {.res = P_SPORT1_DTSEC, .offset = 9}, - {.res = P_TMR2, .offset = 8}, - {.res = P_PPI0_FS3, .offset = 8}, - {.res = P_TMR3, .offset = 7}, - {.res = P_SPI0_SSEL4, .offset = 7}, - {.res = P_TMR4, .offset = 6}, - {.res = P_SPI0_SSEL5, .offset = 6}, - {.res = P_TMR5, .offset = 5}, - {.res = P_SPI0_SSEL6, .offset = 5}, - {.res = P_UART1_RX, .offset = 4}, - {.res = P_UART1_TX, .offset = 4}, - {.res = P_TMR6, .offset = 4}, - {.res = P_TMR7, .offset = 4}, - {.res = P_UART0_RX, .offset = 3}, - {.res = P_UART0_TX, .offset = 3}, - {.res = P_DMAR0, .offset = 3}, - {.res = P_DMAR1, .offset = 3}, - {.res = P_SPORT0_DTSEC, .offset = 1}, - {.res = P_SPORT0_DRSEC, .offset = 1}, - {.res = P_CAN0_RX, .offset = 1}, - {.res = P_CAN0_TX, .offset = 1}, - {.res = P_SPI0_SSEL7, .offset = 1}, - {.res = P_SPORT0_TFS, .offset = 0}, - {.res = P_SPORT0_DTPRI, .offset = 0}, - {.res = P_SPI0_SSEL2, .offset = 0}, - {.res = P_SPI0_SSEL3, .offset = 0}, +static const s8 port_mux[] = { + [GPIO_PF0] = 3, + [GPIO_PF1] = 3, + [GPIO_PF2] = 4, + [GPIO_PF3] = 4, + [GPIO_PF4] = 5, + [GPIO_PF5] = 6, + [GPIO_PF6] = 7, + [GPIO_PF7] = 8, + [GPIO_PF8 ... GPIO_PF15] = -1, + [GPIO_PG0 ... GPIO_PG7] = -1, + [GPIO_PG8] = 9, + [GPIO_PG9] = 9, + [GPIO_PG10] = 10, + [GPIO_PG11] = 10, + [GPIO_PG12] = 10, + [GPIO_PG13] = 11, + [GPIO_PG14] = 11, + [GPIO_PG15] = 11, + [GPIO_PH0 ... GPIO_PH15] = -1, + [PORT_PJ0 ... PORT_PJ3] = -1, + [PORT_PJ4] = 1, + [PORT_PJ5] = 1, + [PORT_PJ6 ... PORT_PJ9] = -1, + [PORT_PJ10] = 0, + [PORT_PJ11] = 0, }; -static void portmux_setup(unsigned short per) +static int portmux_group_check(unsigned short per) { - u16 y, offset, muxreg; + u16 ident = P_IDENT(per); u16 function = P_FUNCT2MUX(per); + s8 offset = port_mux[ident]; + u16 m, pmux, pfunc; - for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { - if (port_mux_lut[y].res == per) { - - /* SET PORTMUX REG */ - - offset = port_mux_lut[y].offset; - muxreg = bfin_read_PORT_MUX(); + if (offset < 0) + return 0; - if (offset != 1) - muxreg &= ~(1 << offset); - else - muxreg &= ~(3 << 1); + pmux = bfin_read_PORT_MUX(); + for (m = 0; m < ARRAY_SIZE(port_mux); ++m) { + if (m == ident) + continue; + if (port_mux[m] != offset) + continue; + if (!is_reserved(peri, m, 1)) + continue; - muxreg |= (function << offset); - bfin_write_PORT_MUX(muxreg); + if (offset == 1) + pfunc = (pmux >> offset) & 3; + else + pfunc = (pmux >> offset) & 1; + if (pfunc != function) { + pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", + ident, function, m, pfunc); + return -EINVAL; } } + + return 0; +} + +static void portmux_setup(unsigned short per) +{ + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + s8 offset = port_mux[ident]; + u16 pmux; + + if (offset == -1) + return; + + pmux = bfin_read_PORT_MUX(); + if (offset != 1) + pmux &= ~(1 << offset); + else + pmux &= ~(3 << 1); + pmux |= (function << offset); + bfin_write_PORT_MUX(pmux); } #elif defined(CONFIG_BF54x) inline void portmux_setup(unsigned short per) { - u32 pmux; u16 ident = P_IDENT(per); u16 function = P_FUNCT2MUX(per); + u32 pmux; pmux = gpio_array[gpio_bank(ident)]->port_mux; @@ -302,20 +311,54 @@ inline void portmux_setup(unsigned short per) inline u16 get_portmux(unsigned short per) { - u32 pmux; u16 ident = P_IDENT(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - + u32 pmux = gpio_array[gpio_bank(ident)]->port_mux; return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); } +static int portmux_group_check(unsigned short per) +{ + return 0; +} #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) +static int portmux_group_check(unsigned short per) +{ + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + u16 pin, gpiopin, pfunc; + + for (pin = 0; pin < GPIO_BANKSIZE; ++pin) { + if (offset != pmux_offset[gpio_bank(ident)][pin]) + continue; + + gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin; + if (gpiopin == ident) + continue; + if (!is_reserved(peri, gpiopin, 1)) + continue; + + pfunc = *port_mux[gpio_bank(ident)]; + pfunc = (pfunc >> offset) & 3; + if (pfunc != function) { + pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", + ident, function, gpiopin, pfunc); + return -EINVAL; + } + } + + return 0; +} + inline void portmux_setup(unsigned short per) { - u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + u16 pmux; pmux = *port_mux[gpio_bank(ident)]; + if (((pmux >> offset) & 3) == function) + return; pmux &= ~(3 << offset); pmux |= (function & 3) << offset; *port_mux[gpio_bank(ident)] = pmux; @@ -323,6 +366,10 @@ inline void portmux_setup(unsigned short per) } #else # define portmux_setup(...) do { } while (0) +static int portmux_group_check(unsigned short per) +{ + return 0; +} #endif #ifndef CONFIG_BF54x @@ -735,6 +782,10 @@ int peripheral_request(unsigned short per, const char *label) } } + if (unlikely(portmux_group_check(per))) { + hard_local_irq_restore(flags); + return -EBUSY; + } anyway: reserve(peri, ident); -- cgit v1.2.3-58-ga151