From a2449091522990e9746a3f1420b9041d9669590c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 18 Dec 2008 11:51:57 +0100 Subject: [ARM] MXC: do not include mach/hardware.h from mach/memory.h Instead of including other header files, define PHYS_OFFSET directly Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock.c | 1 + arch/arm/plat-mxc/include/mach/entry-macro.S | 2 ++ arch/arm/plat-mxc/include/mach/io.h | 4 ++-- arch/arm/plat-mxc/include/mach/memory.h | 8 +++++++- arch/arm/plat-mxc/include/mach/mx1.h | 2 -- arch/arm/plat-mxc/include/mach/mx27.h | 3 --- arch/arm/plat-mxc/include/mach/mx31.h | 3 --- arch/arm/plat-mxc/irq.c | 1 + 8 files changed, 13 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index 9f14a871ee7c..b1746aae1f89 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "crm_regs.h" diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 11632028f7d1..5f01d60da845 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -9,6 +9,8 @@ * published by the Free Software Foundation. */ +#include + #define AVIC_NIMASK 0x04 @ this macro disables fast irq (not implemented) diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index c0cb267e7403..b4f2de769466 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -25,8 +25,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) /* Access all peripherals below 0x80000000 as nonshared device * but leave l2cc alone. */ - if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) || - (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE))) + if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || + (phys_addr >= 0x30000000 + SZ_1M))) mtype = MT_DEVICE_NONSHARED; } diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 203688e6164e..0b808399097f 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,6 +11,12 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#include +#if defined CONFIG_ARCH_MX1 +#define PHYS_OFFSET UL(0x08000000) +#elif defined CONFIG_ARCH_MX2 +#define PHYS_OFFSET UL(0xA0000000) +#elif defined CONFIG_ARCH_MX3 +#define PHYS_OFFSET UL(0x80000000) +#endif #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 8476a15dbfc0..b92e02324d8e 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -18,8 +18,6 @@ #include -#define PHYS_OFFSET UL(0x08000000) - /* * Memory map */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index ae8637471ae8..0313be720552 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -289,7 +289,4 @@ extern int mx27_revision(void); /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ #define ARCH_NR_GPIOS (192 + 16) -/* Start of RAM */ -#define PHYS_OFFSET SDRAM_BASE_ADDR - #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 2f6d9fc0ab23..de026654b00e 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -239,9 +239,6 @@ #define PCMCIA_IO_ADDRESS(x) \ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) -/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */ -#define PHYS_OFFSET CSD0_BASE_ADDR - /* * Interrupt numbers */ diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 06862654a89a..6e7578a3514b 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -22,6 +22,7 @@ #include #include #include +#include #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ -- cgit v1.2.3-58-ga151