From 1f88d1e5f9e5d965c2208edc2c757eaff8960bca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Aug 2022 13:15:25 +0300 Subject: MAINTAINERS: pwm-fan: Drop Bartlomiej Zolnierkiewicz Bartlomiej's Samsung email address is not working since around last year and there was no follow up patch take over of the drivers, so drop the email from maintainers. Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220808101526.46556-2-krzysztof.kozlowski@linaro.org --- MAINTAINERS | 8 -------- 1 file changed, 8 deletions(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..0bd4089579d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16533,14 +16533,6 @@ T: git git://linuxtv.org/media_tree.git F: drivers/media/usb/pwc/* F: include/trace/events/pwc.h -PWM FAN DRIVER -M: Bartlomiej Zolnierkiewicz -L: linux-hwmon@vger.kernel.org -S: Supported -F: Documentation/devicetree/bindings/hwmon/pwm-fan.txt -F: Documentation/hwmon/pwm-fan.rst -F: drivers/hwmon/pwm-fan.c - PWM IR Transmitter M: Sean Young L: linux-media@vger.kernel.org -- cgit v1.2.3-58-ga151 From 6212d2d9bbde60171d0c534e5f43932f84a06d5e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Aug 2022 13:15:24 +0300 Subject: MAINTAINERS: Drop Bartlomiej Zolnierkiewicz Bartlomiej's Samsung email address is not working since around last year and there was no follow up patch take over of the drivers, so drop the email from maintainers. Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220808101526.46556-1-krzysztof.kozlowski@linaro.org --- MAINTAINERS | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 0bd4089579d1..bb22702c967c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5370,8 +5370,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git F: drivers/cpuidle/cpuidle-big_little.c CPUIDLE DRIVER - ARM EXYNOS -M: Bartlomiej Zolnierkiewicz M: Daniel Lezcano +R: Krzysztof Kozlowski M: Kukjin Kim L: linux-pm@vger.kernel.org L: linux-samsung-soc@vger.kernel.org @@ -12405,7 +12405,6 @@ F: drivers/power/supply/max77976_charger.c MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS M: Krzysztof Kozlowski -M: Bartlomiej Zolnierkiewicz L: linux-pm@vger.kernel.org S: Supported B: mailto:linux-samsung-soc@vger.kernel.org @@ -12417,7 +12416,6 @@ F: drivers/power/supply/max77693_charger.c MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS M: Chanwoo Choi M: Krzysztof Kozlowski -M: Bartlomiej Zolnierkiewicz L: linux-kernel@vger.kernel.org S: Supported B: mailto:linux-samsung-soc@vger.kernel.org @@ -17949,7 +17947,6 @@ F: drivers/platform/x86/samsung-laptop.c SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS M: Krzysztof Kozlowski -M: Bartlomiej Zolnierkiewicz L: linux-kernel@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Supported -- cgit v1.2.3-58-ga151 From 845081313632b6a27dff576cf102b4aecb4654cf Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Sat, 10 Sep 2022 22:42:32 +0300 Subject: dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC: the CSRs layout is absolutely different and it doesn't support IRQs unlike DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there is no any reason to have these controllers described in the same bindings. Let's split the DT-schema up. Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW uMCTL2 DDR controller only, we need to accordingly fix the device descriptions. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220910194237.10142-15-Sergey.Semin@baikalelectronics.ru --- .../memory-controllers/synopsys,ddrc-ecc.yaml | 63 +++++++--------------- .../memory-controllers/xlnx,zynq-ddrc-a05.yaml | 38 +++++++++++++ MAINTAINERS | 1 + 3 files changed, 59 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml index f46e95704f53..0be8ecc73d1a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Synopsys IntelliDDR Multi Protocol memory controller +title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski @@ -12,21 +12,22 @@ maintainers: - Michal Simek description: | - The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and - 32-bit bus width configurations. + Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of + working with the memory devices supporting up to (LP)DDR4 protocol. It can + be equipped with SEC/DEC ECC feature if DRAM data bus width is either + 16-bits or 32-bits or 64-bits wide. - The Zynq DDR ECC controller has an optional ECC support in half-bus width - (16-bit) configuration. - - These both ECC controllers correct single bit ECC errors and detect double bit - ECC errors. + For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a + controller. It has an optional SEC/DEC ECC support in 64- and 32-bits + bus width configurations. properties: compatible: - enum: - - snps,ddrc-3.80a - - xlnx,zynq-ddrc-a05 - - xlnx,zynqmp-ddrc-2.40a + oneOf: + - description: Synopsys DW uMCTL2 DDR controller v3.80a + const: snps,ddrc-3.80a + - description: Xilinx ZynqMP DDR controller v2.40a + const: xlnx,zynqmp-ddrc-2.40a interrupts: maxItems: 1 @@ -37,40 +38,16 @@ properties: required: - compatible - reg - -allOf: - - if: - properties: - compatible: - contains: - enum: - - snps,ddrc-3.80a - - xlnx,zynqmp-ddrc-2.40a - then: - required: - - interrupts - else: - properties: - interrupts: false + - interrupts additionalProperties: false examples: - | - memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; - - - | - axi { - #address-cells = <2>; - #size-cells = <2>; - - memory-controller@fd070000 { - compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x0 0x30000>; - interrupt-parent = <&gic>; - interrupts = <0 112 4>; - }; + memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; }; +... diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml new file mode 100644 index 000000000000..8f72e2f8588a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq A05 DDR Memory Controller + +maintainers: + - Krzysztof Kozlowski + - Manish Narani + - Michal Simek + +description: + The Zynq DDR ECC controller has an optional ECC support in half-bus width + (16-bit) configuration. It is cappable of correcting single bit ECC errors + and detecting double bit ECC errors. + +properties: + compatible: + const: xlnx,zynq-ddrc-a05 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..1d51bdb5143e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3087,6 +3087,7 @@ W: http://wiki.xilinx.com T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ F: drivers/clocksource/timer-cadence-ttc.c -- cgit v1.2.3-58-ga151 From 9f60675a0f2e72f7967cc534f1c97f6da3b47392 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Sat, 10 Sep 2022 22:42:33 +0300 Subject: dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name The DT-schema name and the corresponding generic compatible string look inappropriate in the current DW uMCTL2 DDRC DT-bindings: 1. DT-schema name contains undefined vendor-prefix. It's supposed to be "snps", not "synopsys". 2. DT-schema name has "ecc" suffix. That is a device property, and has nothing to do with the controller actual name. 3. The controller name is different. It's DW uMCTL2 DDRC. Just DDRC doesn't identify the IP-core in subject. 4. There is no much point in using the IP-core version in the device name since it can be retrieved from the corresponding device CSR. Moreover the DW uMCTL2 DDRC driver doesn't differentiate the IP-core version at the current state. In order to fix all the inconsistencies described above we suggest to rename the DT-schema to "snps,dw-umctl2-ddrc.yaml", deprecate the compatible string "snps,ddrc-3.80a" and define a new generic device name as "snps,dw-umctl2-ddrc". Signed-off-by: Serge Semin Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220910194237.10142-16-Sergey.Semin@baikalelectronics.ru --- .../memory-controllers/snps,dw-umctl2-ddrc.yaml | 56 ++++++++++++++++++++++ .../memory-controllers/synopsys,ddrc-ecc.yaml | 53 -------------------- MAINTAINERS | 1 + 3 files changed, 57 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml new file mode 100644 index 000000000000..9212dfe6e956 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare Universal Multi-Protocol Memory Controller + +maintainers: + - Krzysztof Kozlowski + - Manish Narani + - Michal Simek + +description: | + Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of + working with the memory devices supporting up to (LP)DDR4 protocol. It can + be equipped with SEC/DEC ECC feature if DRAM data bus width is either + 16-bits or 32-bits or 64-bits wide. + + For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a + controller. It has an optional SEC/DEC ECC support in 64- and 32-bits + bus width configurations. + +properties: + compatible: + oneOf: + - deprecated: true + description: Synopsys DW uMCTL2 DDR controller v3.80a + const: snps,ddrc-3.80a + - description: Synopsys DW uMCTL2 DDR controller + const: snps,dw-umctl2-ddrc + - description: Xilinx ZynqMP DDR controller v2.40a + const: xlnx,zynqmp-ddrc-2.40a + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; +... diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml deleted file mode 100644 index 0be8ecc73d1a..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml +++ /dev/null @@ -1,53 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Synopsys DesignWare Universal Multi-Protocol Memory Controller - -maintainers: - - Krzysztof Kozlowski - - Manish Narani - - Michal Simek - -description: | - Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of - working with the memory devices supporting up to (LP)DDR4 protocol. It can - be equipped with SEC/DEC ECC feature if DRAM data bus width is either - 16-bits or 32-bits or 64-bits wide. - - For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a - controller. It has an optional SEC/DEC ECC support in 64- and 32-bits - bus width configurations. - -properties: - compatible: - oneOf: - - description: Synopsys DW uMCTL2 DDR controller v3.80a - const: snps,ddrc-3.80a - - description: Xilinx ZynqMP DDR controller v2.40a - const: xlnx,zynqmp-ddrc-2.40a - - interrupts: - maxItems: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - | - memory-controller@fd070000 { - compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0xfd070000 0x30000>; - interrupt-parent = <&gic>; - interrupts = <0 112 4>; - }; -... diff --git a/MAINTAINERS b/MAINTAINERS index 1d51bdb5143e..7b2714898198 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3087,6 +3087,7 @@ W: http://wiki.xilinx.com T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ -- cgit v1.2.3-58-ga151