From a55361454c210ae4fd840cde3913f320663c405a Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Thu, 23 May 2024 18:45:28 +0530 Subject: arm64: dts: qcom: qcs6490-rb3gen2: Enable PMK8350 RTC module Enable PMK8350 RTC module that is found on qcs6490-rb3gen2. Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20240523131528.3454431-1-quic_uchheda@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a085ff5b5fb2..5cc259c5b262 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -602,6 +602,10 @@ status = "okay"; }; +&pmk8350_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 6314184be3910c956def78c6899f58c70100372b Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 25 May 2024 11:07:05 -0700 Subject: arm64: dts: qcom: sc8180x: Drop ipa-virt interconnect The IPA BCM is already exposed by clk-rpmh, remove the interconnect node for the same. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240525-sc8180x-drop-ipa-icc-v1-1-84ac4cf08fe3@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 067712310560..2be1a5ab0e60 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2250,13 +2250,6 @@ status = "disabled"; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc8180x-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- cgit v1.2.3-58-ga151 From 8ed45f79142caeefa42e98eb243df35746123c09 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 25 May 2024 10:54:07 -0700 Subject: arm64: dts: qcom: sc8180x: Fix aoss_qmp node The #power-domains property is no longer accepted according to the AOSS QMP binding, drop it from the node. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240525-sc8180x-aop-validation-fix-v1-1-66cfa3c9ccf6@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 2be1a5ab0e60..788ebb20651d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3361,7 +3361,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; }; sram@c3f0000 { -- cgit v1.2.3-58-ga151 From dc402e084a9e0cc714ffd6008dce3c63281b8142 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 25 May 2024 10:56:20 -0700 Subject: arm64: dts: qcom: sc8180x: Correct PCIe slave ports The interconnects property was clearly copy-pasted between the 4 PCIe controllers, giving all four the cpu-pcie path destination of SLAVE_0. The four ports are all associated with CN0, but update the property for correctness sake. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240525-sc8180x-pcie-interconnect-port-fix-v1-1-f86affa02392@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 788ebb20651d..1e2766a0e21d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1890,7 +1890,7 @@ power-domains = <&gcc PCIE_3_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie3_phy>; @@ -2012,7 +2012,7 @@ power-domains = <&gcc PCIE_1_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie1_phy>; @@ -2134,7 +2134,7 @@ power-domains = <&gcc PCIE_2_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie2_phy>; -- cgit v1.2.3-58-ga151 From b3f8cdef8a5c0bc89ceb1095856f64ba7445c6b9 Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Sat, 25 May 2024 16:08:57 +0200 Subject: arm64: dts: qcom: msm8996: add reset for display subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add reset for display subsystem, make sure it gets properly reset. Signed-off-by: Barnabás Czémán Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240525-mdss-reset-v1-1-c0489e8be0d0@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8d2cb6f41095..5348feac026e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -982,6 +982,8 @@ <&mmcc MDSS_MDP_CLK>; clock-names = "iface", "core"; + resets = <&mmcc MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; ranges; -- cgit v1.2.3-58-ga151 From 4b699d2d569483760a18eeec1d80f691d635550e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:38 +0300 Subject: arm64: dts: qcom: sm8150: move USB graph to the SoC dtsi Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-1-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 13 ------------- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 6cb6f503fdac..69ce0baf2423 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -470,7 +470,6 @@ &mdss_dp_out { data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss_dsi0 { @@ -676,18 +675,10 @@ orientation-switch; }; -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp_out>; -}; - &usb_1_qmpphy_out { remote-endpoint = <&pm8150b_typec_mux_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &usb_2_qmpphy { status = "okay"; vdda-phy-supply = <&vreg_l3c_1p2>; @@ -711,10 +702,6 @@ remote-endpoint = <&pm8150b_role_switch_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; -}; - &usb_2_dwc3 { dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index ff22e4346660..cb878b7305c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3507,6 +3507,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3514,6 +3515,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -3672,6 +3674,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; @@ -3894,6 +3897,7 @@ reg = <1>; mdss_dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; }; -- cgit v1.2.3-58-ga151 From 18eac39beb32cec920aaa29aaa15084cde6e366b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:39 +0300 Subject: arm64: dts: qcom: sm8350: move USB graph to the SoC dtsi Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-2-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 25 +++---------------------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 11 +++++++++++ 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 4c25ab2f5670..81e5577cccb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -486,17 +486,10 @@ &mdss_dp { status = "okay"; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp0_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; - }; - }; - }; +&mdss_dp_out { + data-lanes = <0 1>; }; &mpss { @@ -864,10 +857,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { status = "okay"; @@ -885,18 +874,10 @@ orientation-switch; }; -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f7c4700f00c3..24c42f285163 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2273,6 +2273,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -2280,6 +2281,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -2405,6 +2407,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; @@ -2626,6 +2629,14 @@ remote-endpoint = <&dpu_intf0_out>; }; }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; }; dp_opp_table: opp-table { -- cgit v1.2.3-58-ga151 From a84f3627f9d9765853b244f0cf50d3cafd1f0957 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:40 +0300 Subject: arm64: dts: qcom: sm8450: move USB graph to the SoC dtsi Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-3-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 25 +++---------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 11 +++++++++++ 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 3be46b56c723..9926294e4f84 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -674,17 +674,10 @@ &mdss_dp0 { status = "okay"; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp0_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; - }; - }; - }; +&mdss_dp0_out { + data-lanes = <0 1>; }; &pcie0 { @@ -1114,10 +1107,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { status = "okay"; @@ -1135,18 +1124,10 @@ orientation-switch; }; -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 616461fcbab9..d138b90bb280 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2321,6 +2321,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -2328,6 +2329,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3119,6 +3121,14 @@ remote-endpoint = <&dpu_intf0_out>; }; }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; }; dp_opp_table: opp-table { @@ -4584,6 +4594,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; -- cgit v1.2.3-58-ga151 From 2f212acedbbfe7119219935c8c670c3323f07186 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:41 +0300 Subject: arm64: dts: qcom: sm8550: move USB graph to the SoC dtsi Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-4-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 13 ------------- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 13 ------------- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 13 ------------- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 5 files changed, 4 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 12d60a0ee095..f786d9114936 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -940,7 +940,6 @@ }; &mdss_dp0_out { - remote-endpoint = <&usb_dp_qmpphy_dp_in>; data-lanes = <0 1>; }; @@ -1267,10 +1266,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -1289,18 +1284,10 @@ status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 3d4ad5aac70f..56800ab903a1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -736,7 +736,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; &pcie_1_phy_aux_clk { @@ -960,10 +959,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -982,18 +977,10 @@ status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 92f015017418..d0b373da39d4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -807,7 +807,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; &pcie_1_phy_aux_clk { @@ -1144,10 +1143,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -1166,18 +1161,10 @@ status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 85e0d3d66e16..7a8d5c34e9e6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -746,10 +746,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&pm8550vs_2_l1>; vdda12-supply = <&pm8550vs_2_l3>; @@ -770,10 +766,6 @@ remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index bc5aeb05ffc3..3ada5a30ecb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2910,6 +2910,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3186,6 +3187,7 @@ reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3193,6 +3195,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3280,6 +3283,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; -- cgit v1.2.3-58-ga151 From 65931e59e0399129d845452c945b8017ad0570df Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:42 +0300 Subject: arm64: dts: qcom: sm8650: move USB graph to the SoC dtsi Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-5-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 13 ------------- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 4e94f7fe4d2d..65ee00db5622 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -832,7 +832,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; &pcie_1_phy_aux_clk { @@ -1211,10 +1210,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1i_0p88>; vdda12-supply = <&vreg_l3i_1p2>; @@ -1233,18 +1228,10 @@ status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62a6e77730bc..bc5d73019361 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3675,6 +3675,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3767,6 +3768,7 @@ reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3774,6 +3776,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3864,6 +3867,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; -- cgit v1.2.3-58-ga151 From 4f35b0fe2673655148d528982386d9ba5113d537 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:43 +0300 Subject: arm64: dts: qcom: sm8350: move PHY's orientation-switch to SoC dtsi The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-6-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 2 -- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..70036a95cace 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1373,7 +1373,6 @@ vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p92>; - orientation-switch; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8ccade628f1f..46d2567e9a3f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3936,6 +3936,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 81e5577cccb7..895adce59e75 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -870,8 +870,6 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p88>; - - orientation-switch; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 24c42f285163..d67c19a59d5a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2256,6 +2256,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From 1a1322c8a698c8ccafed5379ae8c97dbf8480698 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:44 +0300 Subject: arm64: dts: qcom: sm8450: move PHY's orientation-switch to SoC dtsi The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-7-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 -- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 9926294e4f84..71dc06db7736 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1120,8 +1120,6 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; - - orientation-switch; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d138b90bb280..3494d5076368 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2304,6 +2304,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From d02c0027ea20f67a8dcf023786eb993abee2179e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:45 +0300 Subject: arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsi The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-8-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 -- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 -- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 -- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 - arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 5 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index f786d9114936..98934e4a81b2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1279,8 +1279,6 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; - orientation-switch; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 56800ab903a1..d3fd00176233 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -972,8 +972,6 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p91>; - orientation-switch; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index d0b373da39d4..1d487c42a39b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1156,8 +1156,6 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; - orientation-switch; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 7a8d5c34e9e6..92a88fb05609 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -757,7 +757,6 @@ &usb_dp_qmpphy { vdda-phy-supply = <&pm8550vs_2_l3>; vdda-pll-supply = <&pm8550ve_l3>; - orientation-switch; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3ada5a30ecb7..9980504f66db 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3170,6 +3170,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From fbb22a182267c8de4056bd531caae1d5a32bb40c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:46 +0300 Subject: arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsi The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-9-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 -- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 65ee00db5622..f93de21a26ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1223,8 +1223,6 @@ vdda-phy-supply = <&vreg_l3i_1p2>; vdda-pll-supply = <&vreg_l3g_0p91>; - orientation-switch; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bc5d73019361..dacfade2ceaf 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3751,6 +3751,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From c2f1d0c08fc11ad45d5980ffb1ba3a0a78cc8318 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:47 +0300 Subject: arm64: dts: qcom: sm8650-mtp: connect USB-C SS port to QMP PHY The lanes from the USB-C SS port are connected to the combo USB+DP QMP PHY rather than the SS port of the USB controller. Move the connection endpoint to the QMP PHY out port. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-10-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index d04ceaa73c2b..819f6eadba07 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -59,7 +59,7 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_dp_qmpphy_out>; }; }; }; @@ -853,10 +853,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1i_0p88>; vdda12-supply = <&vreg_l3i_1p2>; @@ -873,6 +869,10 @@ status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + &xo_board { clock-frequency = <76800000>; }; -- cgit v1.2.3-58-ga151 From dad66630a083263b513448426523a3b52a959c79 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:48 +0300 Subject: arm64: dts: qcom: delete wrong usb-role-switch properties The usb-role-switch property doesn't make sense for the USB hosts which are fixed to either host or peripheral USB data mode. Delete usb-role-switch property being present in SoC dtsi. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-11-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts | 1 + arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts | 1 + arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts | 1 + arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts | 1 + arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts | 1 + arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 1 + arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts | 1 + arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts | 1 + arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 1 + arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 1 + arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 1 + 11 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts index 711d84dad9d7..2edf804eb7c9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts @@ -301,5 +301,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index a5957e79b818..336b916729e4 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -321,5 +321,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts index 6b9245cd8b0c..bdf1bfc79c56 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts @@ -326,5 +326,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts index 9ac4f507e321..fccb9c4360ca 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -322,5 +322,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index b0588f30f8f1..d46325e79917 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -357,5 +357,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 47ca2d000341..27de7cf31c83 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -667,6 +667,7 @@ }; &usb_1_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts index e27f3c5d5bba..a288d52fb6d7 100644 --- a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts +++ b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts @@ -248,5 +248,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts index c82d6e628d2c..2f55db0c8ce3 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -287,5 +287,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index 2c7a12983dae..9153a5a55ed9 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -240,6 +240,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 98eb072fa912..4a30024aa48f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -234,6 +234,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 54da053a8042..9d78bb3f7190 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -359,6 +359,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; -- cgit v1.2.3-58-ga151 From 7c0922fc894ffff393ba57c4c20fc034e3a4917f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Apr 2024 15:43:49 +0300 Subject: arm64: dts: qcom: x1e80100: drop wrong usb-role-switch properties The usb-role-switch property doesn't make sense for the USB hosts which are fixed to the host USB data mode. Delete usb-role-switch property from these hosts. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-12-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 3 --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 --- 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index c5c2895b37c7..7e4a13969d25 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -849,7 +849,6 @@ &usb_1_ss0_dwc3 { dr_mode = "host"; - usb-role-switch; }; &usb_1_ss1_hsphy { @@ -871,7 +870,6 @@ &usb_1_ss1_dwc3 { dr_mode = "host"; - usb-role-switch; }; &usb_1_ss2_hsphy { @@ -893,5 +891,4 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; - usb-role-switch; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 2061fbe7b75a..1aebfa5f958d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -545,7 +545,6 @@ &usb_1_ss0_dwc3 { dr_mode = "host"; - usb-role-switch; }; &usb_1_ss1_hsphy { @@ -567,7 +566,6 @@ &usb_1_ss1_dwc3 { dr_mode = "host"; - usb-role-switch; }; &usb_1_ss2_hsphy { @@ -589,5 +587,4 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; - usb-role-switch; }; -- cgit v1.2.3-58-ga151 From e7686284066073e3f39b02df0f71db96d7538f48 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 2 May 2024 10:00:36 +0200 Subject: arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-1-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3494d5076368..ee0f092c02a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2000,8 +2000,8 @@ "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells = <1>; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From 0cc97d9e3fdf9a7b71b4edfd020a44c54c40df52 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 2 May 2024 10:00:37 +0200 Subject: arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 ------------------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++--------- 4 files changed, 4 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 98934e4a81b2..31f52df6b67e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -978,10 +978,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index d3fd00176233..42d4d558b7aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -738,10 +738,6 @@ data-lanes = <0 1>; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 1d487c42a39b..2ed1715000c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -720,17 +720,6 @@ status = "okay"; }; -&gcc { - clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <&pcie0_phy>, - <&pcie1_phy>, - <0>, - <&ufs_mem_phy 0>, - <&ufs_mem_phy 1>, - <&ufs_mem_phy 2>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; -}; - &gpi_dma1 { status = "okay"; }; @@ -809,10 +798,6 @@ data-lanes = <0 1>; }; -&pcie_1_phy_aux_clk { - status = "disabled"; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -906,10 +891,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9980504f66db..79311a6bd1ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -58,11 +58,6 @@ clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -776,8 +771,8 @@ #power-domain-cells = <1>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1928,8 +1923,8 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; - clock-output-names = "pcie1_pipe_clk"; + #clock-cells = <1>; + clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From d00b42f170dfa4d5ffbd616aec36de8159168bba Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 2 May 2024 10:00:38 +0200 Subject: arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-3-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 819f6eadba07..fa6c3b397f2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -641,10 +641,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index f93de21a26ad..98f6a272ce5a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -834,10 +834,6 @@ data-lanes = <0 1>; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index dacfade2ceaf..518fa4c4f303 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -60,11 +60,6 @@ clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -758,8 +753,8 @@ <&bi_tcxo_ao_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2467,8 +2462,8 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; - clock-output-names = "pcie1_pipe_clk"; + #clock-cells = <1>; + clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From 2f2120a15251097f9afcab5b4db7894ce03b2933 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:41 +0530 Subject: arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct node name for the controller instances. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-21-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 518fa4c4f303..d7c432552233 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2203,7 +2203,7 @@ reg = <0 0x010c3000 0 0x1000>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c00000 0 0x3000>, @@ -2331,7 +2331,7 @@ status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c08000 0 0x3000>, -- cgit v1.2.3-58-ga151 From 329dce8aad3efba47ad968c1cedf2d028c5643f6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Apr 2024 10:48:12 +0200 Subject: dt-bindings: arm: qcom: Document the HDK8650 board Document the Qualcomm SM8650 based HDK (Hardware Development Kit) embedded development platform designed by Qualcomm and sold by Lantronix [1]. [1] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240422-topic-sm8650-upstream-hdk-v4-1-b33993eaa2e8@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae885414b181..29f187e8536b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1009,6 +1009,7 @@ properties: - items: - enum: + - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd - const: qcom,sm8650 -- cgit v1.2.3-58-ga151 From 01061441029e7fdedcd5d573ae6bd7c4e025018a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Apr 2024 10:48:13 +0200 Subject: arm64: dts: qcom: sm8650: add support for the SM8650-HDK board The SM8650-HDK is an embedded development platforms for the Snapdragon 8 Gen 3 SoC aka SM8650, with the following features: - Qualcomm SM8650 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Product Page: [3] [1] https://www.96boards.org/specifications/ [2] https://git.codelinaro.org/linaro/qcomlt/debugboard [3] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/ Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240422-topic-sm8650-upstream-hdk-v4-2-b33993eaa2e8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 1251 +++++++++++++++++++++++++++++++ 2 files changed, 1252 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8650-hdk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f63abb43e9fe..74e6796eb5eb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -242,6 +242,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts new file mode 100644 index 000000000000..3791c36579be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -0,0 +1,1251 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8650 HDK"; + compatible = "qcom,sm8650-hdk", "qcom,sm8650"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart15; + serial1 = &uart14; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + led-2 { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pm8550b_gpios 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_bob_3v3>; + gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-HDK"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT3", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_bob_3v3: regulator-vreg-bob-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_BOB_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm8650/ipa_fws.mbn"; + status = "okay"; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3e_0p9>; + vdda-pll-supply = <&vreg_l3i_1p2>; + vdda-qref-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source = <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +/* The RGB signals are routed to 3 separate LEDs on the HDK8650 */ +&pm8550_pwm { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + default-state = "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pmk8550_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8650/adsp.mbn", + "qcom/sm8650/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/cdsp.mbn", + "qcom/sm8650/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8650/modem.mbn", + "qcom/sm8650/modem_dtb.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 8>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio85"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio28"; + function = "gpio"; + output-high; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddio-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_l15b_1p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa0p8-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p9-supply = <&vreg_s6c_1p8>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> USB-C + */ + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- cgit v1.2.3-58-ga151 From fbc7a70b2c1b03eab1ba4a0d611867a2de23d142 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 24 Apr 2024 11:16:02 +0530 Subject: arm64: dts: qcom: qcm6490-rb3: Enable gpi-dma and qup node Enable gpi-dma0, gpi-dma1 and qupv3_id_1 nodes for buses usecase on RB3gen2. Signed-off-by: Viken Dadhaniya Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240424054602.5731-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5cc259c5b262..fe1fa0d12e60 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -530,6 +530,14 @@ ; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -610,6 +618,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs6490/adsp.mbn"; status = "okay"; -- cgit v1.2.3-58-ga151 From 2b96407b8f10f1d71b58cb35704eb91b8ea78db1 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 24 Apr 2024 13:28:53 +0530 Subject: arm64: dts: qcom: sc7280: Remove CTS/RTS configuration For IDP variant, GPIO 20/21 is used by camera use case and camera driver is not able acquire these GPIOs as it is acquired by UART5 driver as RTS/CTS pin. UART5 is designed for debug UART for all the board variants of the sc7280 chipset and RTS/CTS configuration is not required for debug uart usecase. Remove CTS/RTS configuration for UART5 instance and change compatible string to debug UART. Remove overwriting compatible property from individual target specific file as it is not required. Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20240424075853.11445-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 1 - arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 1 - arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ 6 files changed, 2 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index f3432701945f..8cd2fe80dbb2 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -864,7 +864,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 27de7cf31c83..a0668f767e4b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -658,7 +658,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index fe1fa0d12e60..c4cde4328e3d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -648,7 +648,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index a0059527d9e4..7370aa0dbf0e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -495,7 +495,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index f9b96bd2477e..7d1d5bbbbbd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -427,7 +427,6 @@ }; uart_dbg: &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index fc9ec367e3a5..246fb7919d27 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1440,12 +1440,12 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-uart"; + compatible = "qcom,geni-debug-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; @@ -5407,16 +5407,6 @@ function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts-state { - pins = "gpio20"; - function = "qup05"; - }; - - qup_uart5_rts: qup-uart5-rts-state { - pins = "gpio21"; - function = "qup05"; - }; - qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05"; -- cgit v1.2.3-58-ga151 From 15476ccd3dc6cea04048d159115c86a3d5042501 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Wed, 24 Apr 2024 18:15:02 +0800 Subject: arm64: dts: qcom: sm4450: Add cpufreq support Add a description of a SM4450 cpufreq-epss controller,add references to it from CPU nodes and make EPSS a supplyer of clocks for the CPUs. Signed-off-by: Tengfei Fan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240424101503.635364-3-quic_tengfan@quicinc.com Link: https://lore.kernel.org/r/20240424101503.635364-4-quic_tengfan@quicinc.com [bjorn: Squashed the two changes, and updated commit message] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 603c962661cc..8d75c4f9731c 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -29,6 +29,14 @@ clock-frequency = <32000>; #clock-cells = <0>; }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; }; cpus { @@ -39,10 +47,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { @@ -63,10 +73,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { @@ -81,10 +93,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { @@ -99,10 +113,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { @@ -117,10 +133,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_400: l2-cache { @@ -135,10 +153,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_500: l2-cache { @@ -153,10 +173,12 @@ device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { @@ -171,10 +193,12 @@ device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_700: l2-cache { @@ -526,6 +550,19 @@ }; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; timer { -- cgit v1.2.3-58-ga151 From 6986a75d06a370b57811c79d269f1c014cbc7199 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Wed, 24 Apr 2024 14:32:10 +0000 Subject: arm64: dts: qcom: msm8916/39-samsung-a2015: Add PMIC and charger The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy A3/A5/A7 2015 - Samsung Galaxy E5/E7 - Samsung Galaxy Grand Max Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240424143158.24358-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 53 +++++++++++++++++++- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 6 +++ .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 6 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts | 6 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts | 7 +++ .../boot/dts/qcom/msm8916-samsung-grandmax.dts | 6 +++ arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 56 +++++++++++++++++++++- 7 files changed, 138 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 4bbbee80b5e4..e6355e5e2177 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -28,6 +28,12 @@ }; }; + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + clk_pwm: pwm { compatible = "clk-pwm"; #pwm-cells = <2>; @@ -245,7 +251,7 @@ &blsp_i2c4 { status = "okay"; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; interrupt-parent = <&tlmm>; @@ -253,6 +259,44 @@ pinctrl-names = "default"; pinctrl-0 = <&fg_alert_default>; + + power-supplies = <&charger>; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; }; }; @@ -476,6 +520,13 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 3b934f5eba47..906d31f1ea21 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -55,6 +55,12 @@ "0", "0", "1"; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 391befa22bb4..fe39be7a742b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -29,6 +29,12 @@ "0", "0", "1"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts index fad2535255f7..800cb1038da0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts @@ -23,6 +23,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts index b412b61ca258..ec1debd2e245 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts @@ -23,6 +23,13 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + + &pm8916_l17 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index 5882b3a593b8..135df1739dbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -41,6 +41,12 @@ }; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4400000>; +}; + ®_motor_vdd { gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index 0c599e71a464..91acdb160227 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -33,6 +33,15 @@ }; }; + battery: battery { + compatible = "simple-battery"; + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4300000>; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + gpio-hall-sensor { compatible = "gpio-keys"; @@ -82,7 +91,7 @@ #address-cells = <1>; #size-cells = <0>; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; @@ -91,6 +100,8 @@ pinctrl-0 = <&fg_alert_default>; pinctrl-names = "default"; + + power-supplies = <&charger>; }; }; @@ -325,6 +336,42 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -510,6 +557,13 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + reg_tsp_en_default: reg-tsp-en-default-state { pins = "gpio73"; function = "gpio"; -- cgit v1.2.3-58-ga151 From d81348c71028c6049e536799244f2518658b63c0 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Wed, 24 Apr 2024 14:49:32 +0000 Subject: arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add connector for MUIC Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424144922.28189-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 5e933fb8b363..62864cca0cbb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -114,6 +114,12 @@ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index b438fa81886c..08485dcc20de 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -15,6 +15,12 @@ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; -- cgit v1.2.3-58-ga151 From 81a0a21b6159c6a9ed1e39c23e755cd05a102ce3 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Wed, 24 Apr 2024 18:42:06 +0100 Subject: ARM: dts: qcom: msm8226-microsoft-common: Enable smbb explicitly Enable the smbb node explicitly for MSM8x26 Lumia devices. These devices rely on the smbb driver in order to detect USB state. It seems that this was accidentally missed in the commit that this fixes. Fixes: c9c8179d0ccd ("ARM: dts: qcom: Disable pm8941 & pm8226 smbb charger by default") Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424174206.4220-1-rayyan@ansari.sh Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi index 525d8c608b06..8839b23fc693 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi @@ -287,6 +287,10 @@ status = "okay"; }; +&smbb { + status = "okay"; +}; + &usb { extcon = <&smbb>; dr_mode = "peripheral"; -- cgit v1.2.3-58-ga151 From 404a89438abc0b89ec9adaf35c26743c17e448ce Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 25 Apr 2024 10:07:16 +0200 Subject: arm64: dts: qcom: sm8650-hdk: enable GPU Add path of the GPU firmware for the SM8650-HDK board Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240425-topic-sm8650-upstream-hdk-gpu-v1-1-465a11af7441@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 3791c36579be..7f2dbada63b5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -836,6 +836,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21"; -- cgit v1.2.3-58-ga151 From 220be0f04eb1c753fdfe8ff95942fbcdc5ed650a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 26 Apr 2024 11:23:24 +0530 Subject: arm64: dts: qcom: sdx75: Add IPCC node Add IPCC devicetree node to Qcom's SDX75 platform. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/20240426055326.3141727-5-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index da1704061d58..15bb987f6554 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -441,6 +441,15 @@ #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,sdx75-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x2000>; -- cgit v1.2.3-58-ga151 From 85ab1969865b78dc14af930d0819d52ab9cd6dee Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 26 Apr 2024 11:23:25 +0530 Subject: arm64: dts: qcom: sdx75: Add TCSR register space Add TCSR register space devicetree node for accessing different status registers. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/20240426055326.3141727-6-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 15bb987f6554..8f71efa9f938 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -547,6 +547,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sdx75-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + }; + usb: usb@a6f8800 { compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; -- cgit v1.2.3-58-ga151 From 91f767eb693881c0424e05866fde3c033c86c2d3 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 26 Apr 2024 11:23:26 +0530 Subject: arm64: dts: qcom: sdx75: Add AOSS node Add AOSS channel devicetree node for Qcom's SDX75 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/20240426055326.3141727-7-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 8f71efa9f938..d433ed196db6 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -641,6 +642,17 @@ interrupt-controller; }; + aoss_qmp: power-controller@c310000 { + compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c310000 0 0x1000>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c400000 0x0 0x3000>, -- cgit v1.2.3-58-ga151 From 355e5d72a4e52c6b7e56913036cb0daa36317b29 Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Fri, 26 Apr 2024 16:58:37 +0530 Subject: arm64: dts: qcom: sdx75: Add modem SMP2P node Add SMP2P node for the SDX75 platform to communicate with the modem. Signed-off-by: Kaushal Kumar Link: https://lore.kernel.org/r/20240426112837.17478-1-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index d433ed196db6..a16b61e7a8f5 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -406,6 +406,41 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; -- cgit v1.2.3-58-ga151 From bfb751d9221361185bd2331dbf6e751e351a6c5d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 26 Apr 2024 14:31:01 +0200 Subject: arm64: dts: qocm: sdx75: align smem node name with coding style Node names should not have vendor prefixes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240426123101.500676-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index a16b61e7a8f5..2939492cfd50 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -441,7 +441,7 @@ }; }; - smem: qcom,smem { + smem: smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; -- cgit v1.2.3-58-ga151 From 1924f55182243a762c6926962054e338dbbef40d Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Tue, 30 Apr 2024 21:25:39 +0530 Subject: arm64: dts: qcom: sa8775p: Add ep pcie0 controller node Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1714492540-15419-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 31de73594839..4084e77ed5bb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3689,6 +3689,52 @@ }; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; -- cgit v1.2.3-58-ga151 From c5f5de8434ec35d8ccd5b3a746df3afb37bfefeb Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Tue, 30 Apr 2024 21:51:27 +0530 Subject: arm64: dts: qcom: sa8775p: Add ep pcie1 controller node Add ep pcie dtsi node for pcie1 controller found on sa8775p platform. It supports gen4 and x4 link width. Limiting the speed to Gen3 due to stability issue with Gen4. Signed-off-by: Mrinmay Sarkar Link: https://lore.kernel.org/r/1714494089-7917-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 4084e77ed5bb..90656455aa7d 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3845,6 +3845,53 @@ }; }; + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <4>; + + status = "disabled"; + }; + pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; -- cgit v1.2.3-58-ga151 From 48299f604d27dad1168cc90b89f33853162c6e33 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:30 +0300 Subject: arm64: dts: qcom: sc7180: drop extra UFS PHY compat The DT schema doesn't have a fallback compatible for qcom,sc7180-qmp-ufs-phy. Drop it from the dtsi too. Fixes: 858536d9dc94 ("arm64: dts: qcom: sc7180: Add UFS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-4-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4774a859bd7e..52d074a4fbf3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1582,8 +1582,7 @@ }; ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sc7180-qmp-ufs-phy", - "qcom,sm7150-qmp-ufs-phy"; + compatible = "qcom,sc7180-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, -- cgit v1.2.3-58-ga151 From 9a80ecce60bd4919019a3cdb64604c9b183a8518 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:31 +0300 Subject: arm64: dts: qcom: sc8180x: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-5-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 1e2766a0e21d..a2bd808bb330 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2245,6 +2245,8 @@ resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; + power-domains = <&gcc UFS_PHY_GDSC>; + #phy-cells = <0>; status = "disabled"; -- cgit v1.2.3-58-ga151 From fd39ae8b9bc10419b1e4b849cdbc6755a967ade1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:32 +0300 Subject: arm64: dts: qcom: sdm845: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: cc16687fbd74 ("arm64: dts: qcom: sdm845: add UFS controller") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-6-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 10de2bd46ffc..26b1638c76f9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2666,6 +2666,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; -- cgit v1.2.3-58-ga151 From a9eb454873a813ddc4578e5c3b37778de6fda472 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:33 +0300 Subject: arm64: dts: qcom: sm6115: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-7-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index aca0a87092e4..5896868d9e6b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1230,6 +1230,8 @@ "ref_aux", "qref"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; -- cgit v1.2.3-58-ga151 From 18c2727282c5264ff5502daac26c43000e8eb202 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:34 +0300 Subject: arm64: dts: qcom: sm6350: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-8-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 84ff20a96c83..acf0b0f73af9 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1197,6 +1197,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; -- cgit v1.2.3-58-ga151 From 154ed5ea328d8a97a4ef5d1447e6f06d11fe2bbe Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:35 +0300 Subject: arm64: dts: qcom: sm8250: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-9-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 46d2567e9a3f..759e0822b3ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2580,6 +2580,8 @@ resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; + power-domains = <&gcc UFS_PHY_GDSC>; + #phy-cells = <0>; status = "disabled"; -- cgit v1.2.3-58-ga151 From 634acc8cea1584b507801315831a330443f819b4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:36 +0300 Subject: arm64: dts: qcom: sm8350: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-10-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d67c19a59d5a..708107da0ab0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1779,6 +1779,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; -- cgit v1.2.3-58-ga151 From 27d3f57cf5a71484ea38770d4bfd10f6ef035cf4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:37 +0300 Subject: arm64: dts: qcom: sm8450: add power-domain to UFS PHY The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-11-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index ee0f092c02a6..ddbf97b84764 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4441,6 +4441,8 @@ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_0_CLKREF_EN>; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; -- cgit v1.2.3-58-ga151 From 4edbcf264fe2c0167e0b0b0af060bc767e01f9f3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:38 +0300 Subject: arm64: dts: qcom: sda660-ifc6560: document missing USB PHY supplies On the IFC6560 one of the USB PHY supplies is the L10A power supply. However this regulator also supplies VDDA_APC1_CS, VDD_PLL2 and VDD_P11 consumers. Touching the supply causes the board to be reset. Document the supply as a fixed always-on regulator. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-12-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 702ab49bbc59..60412281ab27 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -96,6 +96,18 @@ vin-supply = <&vph_pwr>; }; + + /* + * this is also used for APC1 CPU power, touching it resets the board + */ + vreg_l10a_1p8: vreg-l10a-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-always-on; + regulator-boot-on; + }; }; &adsp_pil { @@ -220,6 +232,7 @@ status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; @@ -227,6 +240,7 @@ status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; @@ -464,5 +478,6 @@ &usb3_qmpphy { vdda-phy-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From c1aefeae8cb7b71c1bb6d33b1bda7fc322094e16 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 1 May 2024 19:19:39 +0300 Subject: arm64: dts: qcom: msm8996-xiaomi-common: drop excton from the USB PHY The USB PHYs don't use extcon connectors, drop the extcon property from the hsusb_phy1 node. Fixes: 46680fe9ba61 ("arm64: dts: qcom: msm8996: Add support for the Xiaomi MSM8996 platform") Cc: Yassine Oudjana Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-13-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 5ab583be9e0a..0386636a29f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -405,7 +405,6 @@ &hsusb_phy1 { status = "okay"; - extcon = <&typec>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -- cgit v1.2.3-58-ga151 From dd1bd5bf7420497aace9521d314f6c7e22f22118 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 2 May 2024 14:33:24 +0530 Subject: arm64: dts: qcom: qdu1000: Add USB3 and PHY support Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on QDU1000/QRU1000 SoCs. Also add required pins for USB, so that the interface can work reliably. Co-developed-by: Amrit Anand Signed-off-by: Amrit Anand Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20240502090326.21489-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 120 ++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f2a5e2e40461..7a77f7a55498 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -913,6 +915,124 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,qdu1000-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0x0 0x088e3000 0x0 0x120>; + #phy-cells = <0>; + + clocks =<&gcc GCC_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@88e5000 { + compatible = "qcom,qdu1000-qmp-usb3-uni-phy"; + reg = <0x0 0x088e5000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB2_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,qdu1000-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "usb-ddr", + "apps-usb"; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + + iommus = <&apps_smmu 0xc0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, + <&usb_1_qmpphy>; + phy-names = "usb2-phy", + "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qdu1000-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; -- cgit v1.2.3-58-ga151 From 00ea07cd1c884efe4b02a5a61794673054547488 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 2 May 2024 14:33:25 +0530 Subject: arm64: dts: qcom: qdu1000-idp: enable USB nodes Enable both USB controllers and associated hsphy and qmp phy nodes on QDU1000 IDP. Co-developed-by: Amrit Anand Signed-off-by: Amrit Anand Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20240502090326.21489-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 5a25cdec969e..e65305f8136c 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -500,3 +500,26 @@ &uart7 { status = "okay"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l8a_0p91>; + vdda18-supply = <&vreg_l14a_1p8>; + vdda33-supply = <&vreg_l2a_2p3>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l8a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; + + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 4d3fadbcd63372e9a1cd15701f882ece252437f4 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 2 May 2024 14:33:26 +0530 Subject: arm64: dts: qcom: qru1000-idp: enable USB nodes Enable both USB controllers and associated hsphy and qmp phy nodes on QRU1000 IDP. Co-developed-by: Amrit Anand Signed-off-by: Amrit Anand Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20240502090326.21489-4-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 2a862c83309e..1c781d9e24cf 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -467,3 +467,26 @@ &uart7 { status = "okay"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l8a_0p91>; + vdda18-supply = <&vreg_l14a_1p8>; + vdda33-supply = <&vreg_l2a_2p3>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l8a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; + + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 49e950487b3e55cbc8bf9f7062e7094f052d11bf Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 17 May 2024 01:05:33 +0530 Subject: arm64: dts: qcom: sm8650: Enable download mode register write Enable download mode setting for sm8650 which can help collect ramdump for this SoC. Signed-off-by: Mukesh Ojha Reviewed-by: Elliot Berman Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1715888133-2810-1-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d7c432552233..1774be6c53e5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -366,6 +366,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8650", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; -- cgit v1.2.3-58-ga151 From e31de4ed955566c5e6bd7ec3d1d4c9d22e723e8a Mon Sep 17 00:00:00 2001 From: Tanmay Shah Date: Fri, 12 Apr 2024 11:37:07 -0700 Subject: dts: zynqmp: add properties for TCM in remoteproc Add properties as per new bindings in zynqmp remoteproc node to represent TCM address and size. This patch also adds alternative remoteproc node to represent remoteproc cluster in split mode. By default lockstep mode is enabled and users should disable it before using split mode dts. Both device-tree nodes can't be used simultaneously one of them must be disabled. For zcu102-1.0 and zcu102-1.1 board remoteproc split mode dts node is enabled and lockstep mode dts is disabled. Signed-off-by: Tanmay Shah Reviewed-by: Mathieu Poirier Link: https://lore.kernel.org/r/20240412183708.4036007-4-tanmay.shah@amd.com Signed-off-by: Michal Simek --- .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 8 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 67 ++++++++++++++++++++-- 2 files changed, 70 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts index c8f71a1aec89..495ca94b45db 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -14,6 +14,14 @@ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; +&rproc_split { + status = "okay"; +}; + +&rproc_lockstep { + status = "disabled"; +}; + &eeprom { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index d99830c9b85f..0b730f6eeef1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -260,19 +260,76 @@ ranges; }; - remoteproc { + rproc_lockstep: remoteproc@ffe00000 { compatible = "xlnx,zynqmp-r5fss"; xlnx,cluster-mode = <1>; + xlnx,tcm-mode = <1>; - r5f-0 { + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>; + }; + }; + + rproc_split: remoteproc-split@ffe00000 { + status = "disabled"; + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + xlnx,tcm-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_0>; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; memory-region = <&rproc_0_fw_image>; }; - r5f-1 { + r5f@1 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_1>; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_1_fw_image>; }; }; -- cgit v1.2.3-58-ga151 From 709407de64d971e7f1e6c26b8b845df5c98b56be Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:30 +0800 Subject: dt-bindings: riscv: Add T-HEAD C908 compatible The thead,c908 is a RISC-V CPU core from T-HEAD Semiconductor which used in Canaan Kendryte K230 SoC. Signed-off-by: Yangyu Chen Acked-by: Conor Dooley Reviewed-by: Guo Ren Link: https://lore.kernel.org/linux-riscv/tencent_22BA0425B4DF1CA1713B62E4423C1BFBF809@qq.com/ Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..d067f2a468ee 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74 - sifive,u74-mc - thead,c906 + - thead,c908 - thead,c910 - thead,c920 - const: riscv -- cgit v1.2.3-58-ga151 From 947bde9069c8241afe401433a6eff276595bb073 Mon Sep 17 00:00:00 2001 From: Dmitry Rokosov Date: Thu, 28 Mar 2024 22:26:35 +0300 Subject: arm64: dts: amlogic: a1: add cooling-cells for DVFS feature It's used for CPU with DVFS feature to specify minimum and maximum cooling state used in the reference. Without these values DVFS will not work and dtbs_check will raise the error. Signed-off-by: Dmitry Rokosov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240328192645.20914-2-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index c03e207ea6c5..edd751243277 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -28,6 +28,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -36,6 +37,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache0 { -- cgit v1.2.3-58-ga151 From 049d141161903e656d9475950bb976240802c01c Mon Sep 17 00:00:00 2001 From: Dmitry Rokosov Date: Thu, 28 Mar 2024 22:26:36 +0300 Subject: arm64: dts: amlogic: a1: introduce cpu temperature sensor The A1 SoC family has only one thermal sensor for CPU temperature measurement. It is required to set the TS clock rate to 500kHz to make it workable. Signed-off-by: Dmitry Rokosov Link: https://lore.kernel.org/r/20240328192645.20914-3-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index edd751243277..a3ff266fb17d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -400,6 +400,17 @@ power-domains = <&pwrc PWRC_USB_ID>; }; + cpu_temp: temperature-sensor@4c00 { + compatible = "amlogic,a1-cpu-thermal"; + reg = <0x0 0x4c00 0x0 0x50>; + interrupts = ; + clocks = <&clkc_periphs CLKID_TS>; + assigned-clocks = <&clkc_periphs CLKID_TS>; + assigned-clock-rates = <500000>; + #thermal-sensor-cells = <0>; + amlogic,ao-secure = <&sec_AO>; + }; + hwrng: rng@5118 { compatible = "amlogic,meson-rng"; reg = <0x0 0x5118 0x0 0x4>; -- cgit v1.2.3-58-ga151 From 593ab951232be4779e77f5b1bee0bef4e6fc1022 Mon Sep 17 00:00:00 2001 From: Dmitry Rokosov Date: Thu, 28 Mar 2024 22:26:37 +0300 Subject: arm64: dts: amlogic: ad402: setup thermal-zones There is one thermal zone with 3 trip points: soc_passive, soc_hot, and soc_critical, as well as two cooling maps. Signed-off-by: Dmitry Rokosov Link: https://lore.kernel.org/r/20240328192645.20914-4-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts index 4bc30af05848..c8579b6e67cf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "meson-a1.dtsi" +#include / { compatible = "amlogic,ad402", "amlogic,a1"; @@ -114,6 +115,50 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; }; + + thermal-zones { + soc_thermal: soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <130>; + + thermal-sensors = <&cpu_temp>; + + trips { + soc_passive: soc-passive { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_hot: soc-hot { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + + soc_critical: soc-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + soc_cooling_maps: cooling-maps { + map0 { + trip = <&soc_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&soc_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; &usb2_phy1 { -- cgit v1.2.3-58-ga151 From cae4c862d8b2d7debb07e6d831e079520163ac4f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 27 May 2024 07:00:22 +0300 Subject: arm64: dts: qcom: sdm850-lenovo-yoga-c630: fix IPA firmware path Specify firmware path for the IPA network controller on the Lenovo Yoga C630 laptop. Without this property IPA tries to load firmware from the default location, which likely will fail. Fixes: 2e01e0c21459 ("arm64: dts: qcom: sdm850-yoga: Enable IPA") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240527-yoga-ipa-fw-v1-1-99ac1f5db283@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 47dc42f6e936..8e30f8cc0916 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -494,6 +494,7 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm850/LENOVO/81JL/ipa_fws.elf"; status = "okay"; }; -- cgit v1.2.3-58-ga151 From ceb39b051b779339749ef0ce30b8d79165e733aa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 27 May 2024 07:01:11 +0300 Subject: arm64: dts: qcom: sdm850-lenovo-yoga-c630: add WiFi calibration variant Add calibration variant that is used by the board data for the laptop: bus=snoc,qmi-board-id=ff,qmi-chip-id=30214,variant=Lenovo_C630 Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240527-yoga-wifi-calib-v1-1-af9dc33880e8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 8e30f8cc0916..8402ea2d93a7 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -835,6 +835,7 @@ vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "Lenovo_C630"; }; &crypto { -- cgit v1.2.3-58-ga151 From 265d9989df5012adc5bec8e894dff0572c195a0c Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 23 May 2024 21:20:27 -0400 Subject: arm64: dts: qcom: sdm670: add smem region The shared memory region is used for information about the SoC and communication with remote processors. Add the smem region for SDM670. Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20240524012023.318965-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 80e81c4233b3..187c6698835d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -509,6 +509,18 @@ no-map; }; + smem@86000000 { + compatible = "qcom,smem"; + reg = <0 0x86000000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_mem: tz@86200000 { + reg = <0 0x86200000 0 0x2d00000>; + no-map; + }; + camera_mem: camera-mem@8ab00000 { reg = <0 0x8ab00000 0 0x500000>; no-map; @@ -1139,6 +1151,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm670-tlmm"; reg = <0 0x03400000 0 0xc00000>; -- cgit v1.2.3-58-ga151 From 37f5169f5c83c5de469d666aea7b9eca4c30e6b9 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 23 May 2024 17:33:36 +0530 Subject: arm64: dts: qcom: sdx75: Add SDHCI node Add sdhc node for SDX75 SoC to support SD card. Also add pins required for SDHCI. Signed-off-by: Naina Mehta Link: https://lore.kernel.org/r/20240523120337.9530-3-quic_nainmeht@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 89 +++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 2939492cfd50..9fe0a300e42f 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -588,6 +589,54 @@ reg = <0x0 0x01fc0000 0x0 0x30000>; }; + sdhc: mmc@8804000 { + compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + iommus = <&apps_smmu 0x00a0 0x0>; + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb: usb@a6f8800 { compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; @@ -744,6 +793,46 @@ drive-strength = <2>; bias-pull-down; }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3-58-ga151 From a1b05c448e74a092c59a84b16e9d4a673c764f1f Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 23 May 2024 17:33:37 +0530 Subject: arm64: dts: qcom: sdx75-idp: add SDHCI for SD Card Enable SDHCI on sdx75-idp to support SD card. Also add the required regulators. Signed-off-by: Naina Mehta Link: https://lore.kernel.org/r/20240523120337.9530-4-quic_nainmeht@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 45 ++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index f76e72fb2072..fde16308c7e2 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -41,6 +41,29 @@ vin-supply = <&vph_ext>; }; + + reg_2v952_vcc: regulator-2v952-vcc { + compatible = "regulator-gpio"; + regulator-name = "2v952_vcc"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3600000>; + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + states = <1650000 0>, <3600000 1>; + startup-delay-us = <5000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_ext>; + }; + + reg_2v95_vdd: regulator-2v95-vdd { + compatible = "regulator-fixed"; + regulator-name = "2v95_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + vin-supply = <®_2v952_vcc>; + }; }; &apps_rsc { @@ -259,8 +282,30 @@ status = "okay"; }; +&sdhc { + cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_2v95_vdd>; + vqmmc-supply = <®_2v952_vcc>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc1_default &sd_cd>; + pinctrl-1 = <&sdc1_sleep &sd_cd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <110 6>; + + sd_cd: sd-cd-state { + pins = "gpio103"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart1 { -- cgit v1.2.3-58-ga151 From 7ddab80e115086c0f2f37fa5a95466d0885d66d2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 23 May 2024 09:59:35 +0200 Subject: arm64: dts: qcom: sdm450: add Lenovo Smart Tab M10 DTS This add initial support for the Lenovo Smart Tab M10 (WiFi) (model tbx605f) which is a 10.1" tablet by Lenovo based on the SDM450 SoC. It has a 10.1" LCP touch panel, SDCard slot, Volume+Power buttons, USB-C port amd front-facing camera (not supported). The proper LCP Panel support will be added later, for now using the simeple-framebuffer with the bootloader-initialized video memory. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240523-topic-sdm450-upstream-tbx605f-v1-3-e52b89133226@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts | 276 +++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 74e6796eb5eb..0cf3d5f764f8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -175,6 +175,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts b/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts new file mode 100644 index 000000000000..175befc02b22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Neil Armstrong + */ +/dts-v1/; + +#include "sdm450.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/ { + model = "Lenovo Smart Tab M10"; + compatible = "lenovo,tbx605f", "qcom,sdm450"; + chassis-type = "tablet"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1200 * 1920 * 3)>; + + width = <1200>; + height = <1920>; + stride = <(1200 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + reserved-memory { + other_ext_region@0 { + no-map; + reg = <0x00 0x84500000 0x00 0x2300000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&pm8953_l10>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1200>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <0x08>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; + +&wcnss { + vddpx-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; + + vddxo-supply = <&pm8953_l7>; + vddrfa-supply = <&pm8953_l19>; + vddpa-supply = <&pm8953_l9>; + vdddig-supply = <&pm8953_l5>; +}; -- cgit v1.2.3-58-ga151 From 6596118ccdcdb3ec5e417293e43bf6b122363a37 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 21 May 2024 09:19:46 +0800 Subject: arm64: dts: qcom: Add coresight nodes for SA8775p Add following coresight components on SA8775p, TMC/ETF, TPDM, dynamic Funnel, TPDA and ETM. Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20240521011946.3148712-2-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 926 ++++++++++++++++++++++++++++++++++ 1 file changed, 926 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 90656455aa7d..dcb2d8435d47 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -205,6 +205,19 @@ }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = + <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; @@ -1644,6 +1657,919 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + stm: stm@4002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x4002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + tpdm@4003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm0_out: endpoint { + remote-endpoint = + <&qdss_tpda_in0>; + }; + }; + }; + }; + + tpda@4004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = + <&funnel0_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_tpda_in0: endpoint { + remote-endpoint = + <&qdss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_tpda_in1: endpoint { + remote-endpoint = + <&qdss_tpdm1_out>; + }; + }; + }; + }; + + tpdm@400f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x400f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm1_out: endpoint { + remote-endpoint = + <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@4041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&qdss_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel0_in6: endpoint { + remote-endpoint = + <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + }; + + funnel@4042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4042000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&qdss_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + }; + + funnel@4045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4045000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_funnel_out: endpoint { + remote-endpoint = + <&aoss_funnel_in7>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + funnel@4b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = + <&etf0_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + aoss_funnel_in6: endpoint { + remote-endpoint = + <&aoss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + aoss_funnel_in7: endpoint { + remote-endpoint = + <&qdss_funnel_out>; + }; + }; + }; + }; + + tmc_etf: tmc@4b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = + <&swao_rep_in>; + }; + }; + }; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = + <&aoss_funnel_out>; + }; + }; + }; + }; + + replicator@4b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + swao_rep_out1: endpoint { + remote-endpoint = + <&eud_in>; + }; + }; + }; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = + <&etf0_out>; + }; + }; + }; + }; + + tpda@4b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = + <&aoss_funnel_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aoss_tpda_in0: endpoint { + remote-endpoint = + <&aoss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + aoss_tpda_in1: endpoint { + remote-endpoint = + <&aoss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + aoss_tpda_in2: endpoint { + remote-endpoint = + <&aoss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + aoss_tpda_in3: endpoint { + remote-endpoint = + <&aoss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + aoss_tpda_in4: endpoint { + remote-endpoint = + <&aoss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@4b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm0_out: endpoint { + remote-endpoint = + <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@4b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm1_out: endpoint { + remote-endpoint = + <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@4b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm2_out: endpoint { + remote-endpoint = + <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@4b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm3_out: endpoint { + remote-endpoint = + <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@4b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm4_out: endpoint { + remote-endpoint = + <&aoss_tpda_in4>; + }; + }; + }; + }; + + aoss_cti: cti@4b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x4b13000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm@6040000 { + compatible = "arm,primecell"; + reg = <0x0 0x6040000 0x0 0x1000>; + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + etm@6140000 { + compatible = "arm,primecell"; + reg = <0x0 0x6140000 0x0 0x1000>; + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + etm@6240000 { + compatible = "arm,primecell"; + reg = <0x0 0x6240000 0x0 0x1000>; + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel0_in2>; + }; + }; + }; + }; + + etm@6340000 { + compatible = "arm,primecell"; + reg = <0x0 0x6340000 0x0 0x1000>; + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel0_in3>; + }; + }; + }; + }; + + etm@6440000 { + compatible = "arm,primecell"; + reg = <0x0 0x6440000 0x0 0x1000>; + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel0_in4>; + }; + }; + }; + }; + + etm@6540000 { + compatible = "arm,primecell"; + reg = <0x0 0x6540000 0x0 0x1000>; + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel0_in5>; + }; + }; + }; + }; + + etm@6640000 { + compatible = "arm,primecell"; + reg = <0x0 0x6640000 0x0 0x1000>; + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel0_in6>; + }; + }; + }; + }; + + etm@6740000 { + compatible = "arm,primecell"; + reg = <0x0 0x6740000 0x0 0x1000>; + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel0_in7>; + }; + }; + }; + }; + + funnel@6800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel0_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel0_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel0_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel0_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel0_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel0_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@6810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6810000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&funnel1_in4>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel1_in3: endpoint { + remote-endpoint = + <&apss_tpda_out>; + }; + }; + }; + }; + + tpdm@6860000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6860000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm3_out: endpoint { + remote-endpoint = + <&apss_tpda_in3>; + }; + }; + }; + }; + + tpdm@6861000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6861000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm4_out: endpoint { + remote-endpoint = + <&apss_tpda_in4>; + }; + }; + }; + }; + + tpda@6863000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x6863000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_tpda_out: endpoint { + remote-endpoint = + <&apss_funnel1_in3>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_tpda_in0: endpoint { + remote-endpoint = + <&apss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_tpda_in1: endpoint { + remote-endpoint = + <&apss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_tpda_in2: endpoint { + remote-endpoint = + <&apss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_tpda_in3: endpoint { + remote-endpoint = + <&apss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_tpda_in4: endpoint { + remote-endpoint = + <&apss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@68a0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm0_out: endpoint { + remote-endpoint = + <&apss_tpda_in0>; + }; + }; + }; + }; + + tpdm@68b0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm1_out: endpoint { + remote-endpoint = + <&apss_tpda_in1>; + }; + }; + }; + }; + + tpdm@68c0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm2_out: endpoint { + remote-endpoint = + <&apss_tpda_in2>; + }; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; -- cgit v1.2.3-58-ga151 From e07c4a702eb0abbb200c07593cfc429338ec42bf Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 17 May 2024 15:34:23 +0530 Subject: arm64: dts: qcom: sdx75: Support for I2C and SPI Add devicetree node for I2C and SPI busses in SDX75. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/20240517100423.2006022-3-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 431 ++++++++++++++++++++++++++++++++++++ 1 file changed, 431 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 9fe0a300e42f..9b93f6501d55 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -487,6 +488,28 @@ #mbox-cells = <2>; }; + gpi_dma: dma-controller@900000 { + compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00900000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7f>; + iommus = <&apps_smmu 0xf6 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x2000>; @@ -503,6 +526,52 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>, + <&gpi_dma 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>, + <&gpi_dma 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + uart1: serial@984000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00984000 0x0 0x4000>; @@ -521,6 +590,229 @@ "sleep"; status = "disabled"; }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>, + <&gpi_dma 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>, + <&gpi_dma 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>, + <&gpi_dma 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>, + <&gpi_dma 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>, + <&gpi_dma 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>, + <&gpi_dma 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>, + <&gpi_dma 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0099c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>, + <&gpi_dma 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0099c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>, + <&gpi_dma 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; usb_hsphy: phy@ff4000 { @@ -771,6 +1063,145 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio110", "gpio111"; + function = "qup_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio112", "gpio113"; + function = "qup_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio116", "gpio117"; + function = "qup_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio11"; + function = "qup_se0"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup_se0"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio17"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio16"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio55"; + function = "qup_se3"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup_se3"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio115"; + function = "qup_se6"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio112", "gpio113", "gpio114"; + function = "qup_se6"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio119"; + function = "qup_se7"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio116", "gpio117", "gpio118"; + function = "qup_se7"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_uart4_cts_rts: qup-uart4-cts-rts-state { + /* CTS, RTS */ + pins = "gpio52", "gpio53"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart4_default: qup-uart4-default-state { + /* TX, RX */ + pins = "gpio54", "gpio55"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-up; + }; + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { tx-pins { pins = "gpio12"; -- cgit v1.2.3-58-ga151 From 98a0c4f2278b4d6c1c7722735c20b2247de6293f Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Wed, 15 May 2024 16:27:44 +0200 Subject: arm64: dts: qcom: msm8998: enable adreno_smmu by default 15 qcom platform DTSI files define an adreno_smmu node. msm8998 is the only one with adreno_smmu disabled by default. There's no reason why this SMMU should be disabled by default, it doesn't need any further configuration. Bring msm8998 in line with the 14 other platforms. This fixes GPU init failing with ENODEV: msm_dpu c901000.display-controller: failed to load adreno gpu msm_dpu c901000.display-controller: failed to bind 5000000.gpu (ops a3xx_ops): -19 Fixes: 87cd46d68aeac8 ("Configure Adreno GPU and related IOMMU") Signed-off-by: Marc Gonzalez Reviewed-by: Bryan O'Donoghue Reviewed-by: Marijn Suijten Reviewed-by: Jeffrey Hugo Link: https://lore.kernel.org/r/be51d1a4-e8fc-48d1-9afb-a42b1d6ca478@freebox.fr Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d795b2bbe133..254c12d7373c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1590,7 +1590,6 @@ * SoC VDDMX RPM Power Domain in the Adreno driver. */ power-domains = <&gpucc GPU_GX_GDSC>; - status = "disabled"; }; gpucc: clock-controller@5065000 { -- cgit v1.2.3-58-ga151 From 17944fd55b8d03457ffaf4fd37ed7bef679bc4a4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:08 +0300 Subject: arm64: dts: qcom: sc8180x: correct dispcc clocks Correct the clocks being used by the display clock controller on the SC8180X platform (to match the schema): - Drop the sleep clock - Add DSI clocks - Reorder eDP / DP clocks This changes the order of clocks, however it should be noted that the clock list was neither correct nor followed the schema beforehand. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-2-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index a2bd808bb330..6f17fb7975fe 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3303,21 +3303,27 @@ compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>; clock-names = "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; + "edp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; -- cgit v1.2.3-58-ga151 From db67e95835d0d79a1c1dd53a016c951706e0af10 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:09 +0300 Subject: arm64: dts: qcom: sm8250: describe HS signals properly The OF graph should describe physical signals. There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Rename endpoints to mention USB HS signal instead (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-3-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 70036a95cace..c52357214de5 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1356,8 +1356,8 @@ usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1464,8 +1464,8 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 41f117474872..3596dd328c31 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,8 +659,8 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; }; @@ -725,8 +725,8 @@ status = "okay"; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 759e0822b3ac..4ec9541ce104 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4230,7 +4230,7 @@ phy-names = "usb2-phy", "usb3-phy"; port { - usb_1_role_switch_out: endpoint {}; + usb_1_dwc3_hs_out: endpoint {}; }; }; }; -- cgit v1.2.3-58-ga151 From 88347987574b435b23fced20982dc15115ff81b8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:10 +0300 Subject: arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by: Luca Weiss Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-4-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4ec9541ce104..f3f9dea0550b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3951,6 +3951,10 @@ port@1 { reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; }; port@2 { @@ -4229,8 +4233,24 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_dwc3_hs_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 35e3a9c1afce0aa72a4f71f43cae9784f01825fc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:11 +0300 Subject: arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer bindings rather than old bindings which had PHYs as subdevices. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-5-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 122 ++++++++++++---------------------- 1 file changed, 41 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 6f17fb7975fe..4234c80932cd 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2506,28 +2507,25 @@ status = "disabled"; }; - usb_prim_qmpphy: phy@88e9000 { + usb_prim_qmpphy: phy@88e8000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>, - <0 0x088ea000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088e8000 0 0x3000>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2541,59 +2539,38 @@ usb_prim_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_prim_qmpphy_usb_ss_in: endpoint {}; + }; + port@2 { reg = <2>; usb_prim_qmpphy_dp_in: endpoint {}; }; }; - - usb_prim_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_prim_phy_pipe_clk_src"; - }; - - usb_prim_dpphy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; }; usb_sec_qmpphy: phy@88ee000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088ee000 0 0x18c>, - <0 0x088ed000 0 0x10>, - <0 0x088ef000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088ed000 0 0x3000>; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2607,37 +2584,18 @@ usb_sec_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_sec_qmpphy_usb_ss_in: endpoint {}; + }; + port@2 { reg = <2>; usb_sec_qmpphy_dp_in: endpoint {}; }; }; - - usb_sec_ssphy: usb3-phy@88e9200 { - reg = <0 0x088ee200 0 0x200>, - <0 0x088ee400 0 0x200>, - <0 0x088eec00 0 0x218>, - <0 0x088ee600 0 0x200>, - <0 0x088ee800 0 0x200>, - <0 0x088eea00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_sec_phy_pipe_clk_src"; - }; - - usb_sec_dpphy: dp-phy@88ef200 { - reg = <0 0x088ef200 0 0x200>, - <0 0x088ef400 0 0x200>, - <0 0x088efa00 0 0x200>, - <0 0x088ef600 0 0x200>, - <0 0x088ef800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - clock-output-names = "qmp_dptx1_phy_pll_link_clk", - "qmp_dptx1_phy_pll_vco_div_clk"; - }; }; system-cache-controller@9200000 { @@ -2706,7 +2664,7 @@ iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; port { @@ -2763,7 +2721,7 @@ iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; port { @@ -3081,9 +3039,10 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_prim_dpphy>; + phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3158,9 +3117,10 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; - assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_sec_dpphy>; + phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3307,12 +3267,12 @@ <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <&usb_prim_dpphy 0>, - <&usb_prim_dpphy 1>, + <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&edp_phy 0>, <&edp_phy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>; + <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", -- cgit v1.2.3-58-ga151 From 757688ad094cb520378e6665215a1b79aa46a8ff Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:12 +0300 Subject: arm64: dts: qcom: sc8180x: describe USB signals properly Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-6-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++---- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +++++----- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 46 +++++++++++++++++++--- 3 files changed, 58 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6af99116c715..5b226577f9d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -68,7 +68,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -103,7 +103,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -582,6 +582,10 @@ dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -590,8 +594,8 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; }; &usb_sec_hsphy { @@ -619,10 +623,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index bfee60c93ccc..65d923497a05 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -71,7 +71,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -106,7 +106,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -648,6 +648,10 @@ dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -656,10 +660,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -685,10 +685,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; @@ -697,6 +693,10 @@ dr_mode = "host"; }; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &wifi { memory-region = <&wlan_mem>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 4234c80932cd..140b38e35481 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2542,7 +2542,9 @@ port@1 { reg = <1>; - usb_prim_qmpphy_usb_ss_in: endpoint {}; + usb_prim_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_prim_dwc3_ss>; + }; }; port@2 { @@ -2587,7 +2589,9 @@ port@1 { reg = <1>; - usb_sec_qmpphy_usb_ss_in: endpoint {}; + usb_sec_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_sec_dwc3_ss>; + }; }; port@2 { @@ -2667,8 +2671,23 @@ phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_prim_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_prim_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_prim_dwc3_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; + }; }; }; }; @@ -2724,8 +2743,23 @@ phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_sec_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_sec_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_sec_dwc3_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 93830ef7bbcdfd440fd6d93adfb59f20560950a5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:13 +0300 Subject: arm64: dts: qcom: sc8280xp: describe USB signals properly Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-7-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 ++++---- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 ++++---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++++++++++++++++-- 3 files changed, 70 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 41215567b3ae..a2627ab4db9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,7 +56,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -91,7 +91,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -675,6 +675,10 @@ dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -700,10 +704,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -712,6 +712,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -737,10 +741,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index e937732abede..cd914fffcf06 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -117,7 +117,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -152,7 +152,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -1131,6 +1131,10 @@ dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -1156,10 +1160,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -1168,6 +1168,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -1193,10 +1197,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0549ba1fbeea..e87196b2ace0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3222,6 +3222,14 @@ usb_0_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3275,6 +3283,14 @@ usb_1_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3560,8 +3576,23 @@ phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3622,8 +3653,23 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; }; }; }; -- cgit v1.2.3-58-ga151 From b73ed308f9f69499fde654d63ed6c1fd44870793 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:14 +0300 Subject: arm64: dts: qcom: x1e80100: describe USB signals properly Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-8-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++-- 1 file changed, 141 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..cf8d8d5b1870 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2543,6 +2543,33 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2610,33 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2677,33 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint { + }; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -3445,8 +3526,23 @@ dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3514,8 +3610,15 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; - port { - usb_2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; }; }; }; @@ -3590,8 +3693,23 @@ dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3673,8 +3791,23 @@ dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 42214cbd945871b48d1ca1a6bd17f02e1a5f823e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:15 +0300 Subject: arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints Follow other Qualcomm platforms and rename pm8150b_role_switch_in to pm8150_hs_in. Corresponding port is described as HS port rather than role switching. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-9-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 69ce0baf2423..bac08f00b303 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -555,7 +555,7 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { + pm8150b_hs_in: endpoint { remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -699,7 +699,7 @@ }; &usb_1_dwc3_hs { - remote-endpoint = <&pm8150b_role_switch_in>; + remote-endpoint = <&pm8150b_hs_in>; }; &usb_2_dwc3 { -- cgit v1.2.3-58-ga151 From f44da5d8722de348ff2eb8b206c69b52809c1772 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 10 May 2024 14:27:08 +0200 Subject: arm64: dts: qcom: sc7280: Add APR nodes for sound Add the different services found on APR on some devices with SC7280 SoC. Additionally add an empty sound node in the root node as is seen on other SoC dtsi files so device dt's can easily use that. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240510-sc7280-apr-v1-1-e9eabda05f85@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 246fb7919d27..e3ff325576de 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -3762,6 +3763,75 @@ label = "lpass"; qcom,remote-pid = <2>; + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1801 0x0>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; @@ -5981,6 +6051,9 @@ }; }; + sound: sound { + }; + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; -- cgit v1.2.3-58-ga151 From 418c2ffd7df9bfc25c21172bd881b78d7569fb4d Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Wed, 8 May 2024 18:34:34 +0200 Subject: arm64: dts: qcom: msm8976: Add IOMMU nodes Add the nodes describing the apps and gpu iommu and its context banks that are found on msm8976 SoCs. Signed-off-by: Adam Skladowski Link: https://lore.kernel.org/r/20240508163455.8757-2-a39.skl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 81 +++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..8bdcc1438177 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -808,6 +808,87 @@ reg = <0x01937000 0x30000>; }; + apps_iommu: iommu@1ee0000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + reg = <0x01ee0000 0x3000>; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* VFE */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x15000 0x1000>; + qcom,ctx-asid = <20>; + interrupts = ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x16000 0x1000>; + qcom,ctx-asid = <21>; + interrupts = ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x17000 0x1000>; + qcom,ctx-asid = <22>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01f08000 0x8000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX3D_TCU_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_CX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0 0x1000>; + qcom,ctx-asid = <0>; + interrupts = ; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x1000 0x1000>; + qcom,ctx-asid = <2>; + interrupts = ; + }; + + /* gfx3d priv */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + qcom,ctx-asid = <1>; + interrupts = ; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x1000>, -- cgit v1.2.3-58-ga151 From b0516dbf8e218dede2fd2837ca82dccd9cdcdafc Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Wed, 8 May 2024 18:34:35 +0200 Subject: arm64: dts: qcom: msm8976: Add MDSS nodes Add MDSS nodes to support displays on MSM8976 SoC. Signed-off-by: Adam Skladowski Link: https://lore.kernel.org/r/20240508163455.8757-3-a39.skl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 280 +++++++++++++++++++++++++++++++++- 1 file changed, 276 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 8bdcc1438177..7536432aa1fc 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -785,10 +785,10 @@ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <0>, - <0>, - <0>, - <0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "xo_a", "dsi0pll", @@ -808,6 +808,278 @@ reg = <0x01937000 0x30000>; }; + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 22>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + mdss_mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177780000 { + opp-hz = /bits/ 64 <177780000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, + <&gcc GCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-161250000 { + opp-hz = /bits/ 64 <161250000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, + <&gcc GCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a96b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + apps_iommu: iommu@1ee0000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; reg = <0x01ee0000 0x3000>; -- cgit v1.2.3-58-ga151 From 00e67d8e80f06bb848a3dd516d06e2f040b7d8f2 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Wed, 8 May 2024 18:34:36 +0200 Subject: arm64: dts: qcom: msm8976: Add Adreno GPU Add Adreno GPU node. Signed-off-by: Adam Skladowski Link: https://lore.kernel.org/r/20240508163455.8757-4-a39.skl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 71 +++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 7536432aa1fc..a79d916b9fff 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1080,6 +1080,77 @@ }; }; + adreno_gpu: gpu@1c00000 { + compatible = "qcom,adreno-510.0", "qcom,adreno"; + + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GFX3D_OXILI_CLK>, + <&gcc GCC_GFX3D_OXILI_AHB_CLK>, + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, + <&gcc GCC_GFX3D_BIMC_CLK>, + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, + <&gcc GCC_GFX3D_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "rbbmtimer", + "alwayson"; + + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&gpu_iommu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0xff>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xff>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0xff>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + }; + }; + apps_iommu: iommu@1ee0000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; reg = <0x01ee0000 0x3000>; -- cgit v1.2.3-58-ga151 From 45878973229a93f0f42aa048ac8c6223af010082 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Wed, 8 May 2024 18:34:37 +0200 Subject: arm64: dts: qcom: msm8976: Add WCNSS node Add node describing wireless connectivity subsystem. Signed-off-by: Adam Skladowski Link: https://lore.kernel.org/r/20240508163455.8757-5-a39.skl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 105 ++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index a79d916b9fff..1b158608c49d 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -771,6 +771,36 @@ drive-strength = <2>; bias-disable; }; + + wcss_wlan_default: wcss-wlan-default-state { + wcss-wlan2-pins { + pins = "gpio40"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio41"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio42"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1458,6 +1488,81 @@ status = "disabled"; }; + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", + "dxe", + "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains = <&rpmpd MSM8976_VDDCX>, + <&rpmpd MSM8976_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-0 = <&wcss_wlan_default>; + pinctrl-names = "default"; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + mboxes = <&apcs 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; -- cgit v1.2.3-58-ga151 From e60ac570137b42ef61a01a6b26133a8e2d7e8d4b Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 6 May 2024 21:47:58 -0500 Subject: arm64: dts: qcom: ipq9574: add MDIO bus The IPQ95xx uses an IPQ4019 compatible MDIO controller that is already supported. Add a DT node to expose it. Signed-off-by: Alexandru Gagniuc Link: https://lore.kernel.org/r/20240507024758.2810514-2-mr.nuke.me@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..ded02bc39275 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -232,6 +232,16 @@ clock-names = "core"; }; + mdio: mdio@90000 { + compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x5a1>; -- cgit v1.2.3-58-ga151 From bfc10ebd76d56e3bf8899891e5730604eea46db4 Mon Sep 17 00:00:00 2001 From: Bryant Mairs Date: Mon, 19 Feb 2024 22:43:16 +0100 Subject: dt-bindings: arm: qcom: Document samsung,milletwifi device Add binding documentation for Samsung Galaxy Tab 4 8.0 Wi-Fi tablet which is based on Snapdragon 400 (apq8026) SoC. Acked-by: Linus Walleij Acked-by: Conor Dooley Signed-off-by: Bryant Mairs Link: https://lore.kernel.org/r/20240219214643.197116-2-bryant@mai.rs Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 29f187e8536b..b1b231aa4472 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -104,6 +104,7 @@ properties: - huawei,sturgeon - lg,lenok - samsung,matisse-wifi + - samsung,milletwifi - const: qcom,apq8026 - items: -- cgit v1.2.3-58-ga151 From 49b9981a0ecae2bbb298d8b0c2b8058220038691 Mon Sep 17 00:00:00 2001 From: Bryant Mairs Date: Mon, 19 Feb 2024 22:43:17 +0100 Subject: ARM: dts: qcom: Add support for Samsung Galaxy Tab 4 8.0 Wi-Fi Add support for this tablet based on the MSM8226 SoC, codenamed "milletwifi". Acked-by: Linus Walleij Reviewed-by: Luca Weiss Signed-off-by: Bryant Mairs Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240219214643.197116-3-bryant@mai.rs Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcom-apq8026-samsung-milletwifi.dts | 573 +++++++++++++++++++++ 2 files changed, 574 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index e2e922bdc9e9..1149a310ad43 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8026-huawei-sturgeon.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8026-samsung-matisse-wifi.dtb \ + qcom-apq8026-samsung-milletwifi.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts new file mode 100644 index 000000000000..7d519156d91d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki + * Copyright (c) 2023, Bryant Mairs + */ + +/dts-v1/; + +#include +#include +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + +/ { + model = "Samsung Galaxy Tab 4 8.0 Wi-Fi"; + compatible = "samsung,milletwifi", "qcom,apq8026"; + chassis-type = "tablet"; + + aliases { + display0 = &framebuffer0; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <800>; + height = <1280>; + stride = <(800 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Cover"; + gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-home { + label = "Home"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + enable-supply = <®_backlight_vddio>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + + /* + * Change transition duration: 200ms, Change + * transition strength: heavy, PWM hysteresis: + * 1-bit w/ 8-bit resolution + */ + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + + /* + * PWM phase configuration: 3-phase/3 drivers + * (0, 120deg, 240deg, -, -, -), + * PWM frequency: 9616Hz (10-bit) + */ + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x34>; + }; + + /* + * Enable LED drivers 2 & 3, Boot inductor + * current limit: 1.5A/2.6A + */ + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xfa>; + }; + }; + }; + + reg_backlight_vddio: regulator-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "backlight_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&backlight_vddio_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en1_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default_state>; + pinctrl-names = "default"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + mpss_region: mpss@8400000 { + reg = <0x08400000 0x1f00000>; + no-map; + }; + + mba_region: mba@a300000 { + reg = <0x0a300000 0x100000>; + no-map; + }; + + reserved@cb00000 { + reg = <0x0cb00000 0x700000>; + no-map; + }; + + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0x700000>; + no-map; + }; + + adsp_region: adsp@d900000 { + reg = <0x0d900000 0x1800000>; + no-map; + }; + + venus@f100000 { + reg = <0x0f100000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x260000>; + no-map; + }; + + rfsa@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-0 = <&accel_int_default_state>; + pinctrl-names = "default"; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + st,drdy-int-pin = <1>; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + charger@6a { + compatible = "summit,smb358"; + reg = <0x6a>; + + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&charger_int_default_state>; + pinctrl-names = "default"; + + summit,enable-usb-charging; + summit,enable-charge-control = ; + summit,fast-voltage-threshold-microvolt = <3000000>; + summit,chip-temperature-threshold-celsius = <130>; + summit,usb-current-limit-microamp = <1500000>; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + muic: usb-switch@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&muic_int_default_state>; + pinctrl-names = "default"; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms252", "melfas,mms114"; + reg = <0x48>; + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + avdd-supply = <®_tsp_3p3v>; + vdd-supply = <®_tsp_1p8v>; + linux,keycodes = ; + + pinctrl-0 = <&tsp_int_rst_default_state>; + pinctrl-names = "default"; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + regulator-always-on; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdhc2_default_state>, <&sdc2_cd_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + accel_int_default_state: accel-int-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_vddio_default_state: backlight-vddio-default-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + charger_int_default_state: charger-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + muic_int_default_state: muic-int-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default_state: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default_state: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en1_default_state: tsp-en1-default-state { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default_state: tsp-int-rst-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; -- cgit v1.2.3-58-ga151 From e23dfb4ee30a120a947abb94a718ccc1eb5f87ff Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 20 Feb 2024 00:11:22 +0100 Subject: ARM: dts: qcom: msm8974-hammerhead: Hook up backlight Connect the panel with the backlight nodes so that the backlight can be turned off when the display is blanked. Signed-off-by: Luca Weiss Reviewed-by: Daniel Thompson Link: https://lore.kernel.org/r/20240220-lm3630a-fixups-v1-4-9ca62f7e4a33@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 4aaae8537a3f..8eaa5b162815 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -182,7 +182,7 @@ status = "okay"; clock-frequency = <355000>; - led-controller@38 { + backlight: led-controller@38 { compatible = "ti,lm3630a"; status = "okay"; reg = <0x38>; @@ -272,6 +272,8 @@ reg = <0>; compatible = "lg,acx467akm-7"; + backlight = <&backlight>; + pinctrl-names = "default"; pinctrl-0 = <&panel_pin>; -- cgit v1.2.3-58-ga151 From 4b220c6fa9f379cb8803dbca73ae1f4128dfa5c8 Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Mon, 11 Mar 2024 19:41:37 +0530 Subject: arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent The PCIe EP controller on SA8775P supports cache coherency, hence add the "dma-coherent" property to mark it as such. Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1710166298-27144-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index dcb2d8435d47..5632fa896b93 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4649,6 +4649,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + dma-coherent; iommus = <&pcie_smmu 0x0000 0x7f>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "core"; -- cgit v1.2.3-58-ga151 From 16babb0567e4c1c1eea0c1e5c86d5e2904b569c9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 14 Mar 2024 20:00:14 +0100 Subject: dt-bindings: arm: qcom: Add Samsung Galaxy Note 3 Add the compatible for this Samsung smartphone ("phablet" as it was named in that era). Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240314-samsung-hlte-v2-1-84094b41c033@z3ntu.xyz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b1b231aa4472..2fa5512da007 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -176,6 +176,7 @@ properties: - items: - enum: - lge,hammerhead + - samsung,hlte - sony,xperia-amami - sony,xperia-honami - const: qcom,msm8974 -- cgit v1.2.3-58-ga151 From b4f6c63bf34d8da1b769483bb1f4a603c53896ce Mon Sep 17 00:00:00 2001 From: Adam Honse Date: Thu, 14 Mar 2024 20:00:15 +0100 Subject: ARM: dts: qcom: msm8974: Add Samsung Galaxy Note 3 Add the devicetree for this "phablet" using the Snapdragon 800 SoC. Signed-off-by: Adam Honse [luca@z3ntu.xyz: clean up, prepare for upstream] Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240314-samsung-hlte-v2-2-84094b41c033@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcom-msm8974-samsung-hlte.dts | 401 +++++++++++++++++++++ 2 files changed, 402 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 1149a310ad43..e6114a95428b 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8960-cdp.dtb \ qcom-msm8960-samsung-expressatt.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-samsung-hlte.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ qcom-msm8974pro-fairphone-fp2.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts new file mode 100644 index 000000000000..903bb4d12513 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy Note 3"; + compatible = "samsung,hlte", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_3; /* SDC3 SD card slot */ + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_pin_a>; + pinctrl-names = "default"; + + key-home { + label = "Home Key"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + touch_ldo: regulator-touch { + compatible = "regulator-fixed"; + regulator-name = "touch-ldo"; + + gpio = <&pm8941_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + + pinctrl-0 = <&touch_ldo_pin>; + pinctrl-names = "default"; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pm8941_gpios>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8941_l10>; + vio-supply = <&touch_ldo>; + + pinctrl-0 = <&touch_pin>; + pinctrl-names = "default"; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp2_i2c6 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pm8941_gpios>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fuelgauge_pin>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + bias-pull-up; + power-source = ; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio26"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + touch_pin: touchscreen-int-state { + pins = "gpio30"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + touch_ldo_pin: touchscreen-ldo-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = ; + qcom,drive-strength = ; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhc_3 { + max-frequency = <100000000>; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l21>; + + pinctrl-0 = <&sdhc3_pin_a>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + sdhc1_pin_a: sdhc1-pin-active-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdhc3_pin_a: sdhc3-pin-active-state { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 5c59666c443d730991ddbe46b098dc473cf56a55 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 26 Mar 2024 15:52:27 +0100 Subject: dt-bindings: arm: qcom: add TP-Link Archer AX55 v1 Document the TP-Link Archer AX55 v1 which is a dual-band WiFi router based on the IPQ5018 SoC. Signed-off-by: Gabor Juhos Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240326-archer-ax55-v1-v4-1-dc5b54a4bb00@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2fa5512da007..00f37a174ce8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -318,6 +318,7 @@ properties: - items: - enum: - qcom,ipq5018-rdp432-c2 + - tplink,archer-ax55-v1 - const: qcom,ipq5018 - items: -- cgit v1.2.3-58-ga151 From e6d33c8b2f8063e1f195cfc0e7f1c9e21066d13b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 26 Mar 2024 15:52:28 +0100 Subject: arm64: dts: qcom: add TP-Link Archer AX55 v1 Add device tree source for the TP-Link Archer AX55 v1 [1] which is a dual-band WiFi router based on the IPQ5018 SoC. At the moment, only the UART, the GPIO LEDs and buttons are usable, but it makes it possible to boot an initramfs image on the device. The device tree can be extended in the future, once support for other periherals will be available for the platform. 1. https://www.tp-link.com/en/home-networking/wifi-router/archer-ax55/v1/ Signed-off-by: Gabor Juhos Link: https://lore.kernel.org/r/20240326-archer-ax55-v1-v4-2-dc5b54a4bb00@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 128 +++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0cf3d5f764f8..e8c5b364a09b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts new file mode 100644 index 000000000000..5bb021cb29cd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + +/dts-v1/; + +#include +#include +#include + +#include "ipq5018.dtsi" + +/ { + model = "TP-Link Archer AX55 v1"; + compatible = "tplink,archer-ax55-v1", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led-0 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WAN_ONLINE; + gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_USB; + gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + }; + }; + + buttons { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + button-reset { + debounce-interval = <60>; + gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + + button-wps { + debounce-interval = <60>; + gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + label = "wps"; + linux,code = ; + }; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + button_pins: button-pins-state { + pins = "gpio25", "gpio31"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + led_pins: led-pins-state { + pins = "gpio10", "gpio11", "gpio13", "gpio18", "gpio22", + "gpio38", "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + uart_pins: uart-pins-state { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; -- cgit v1.2.3-58-ga151 From ad986e45ada999d67bb47ec8a0316fc931927c21 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 20:28:04 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa ZERO 3W/3E Add devicetree binding documentation for Radxa ZERO 3W/3E boards. The Radxa ZERO 3W/3E is an ultra-small, high-performance single board computer based on the Rockchip RK3566, with a compact form factor and rich interfaces. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240521202810.1225636-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e04c213a0dee..51cdaabaf0d9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -814,6 +814,13 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ZERO 3W/3E + items: + - enum: + - radxa,zero-3e + - radxa,zero-3w + - const: rockchip,rk3566 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 -- cgit v1.2.3-58-ga151 From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 20:28:05 +0000 Subject: arm64: dts: rockchip: Add Radxa ZERO 3W/3E The Radxa ZERO 3W/3E is an ultra-small, high-performance single board computer based on the Rockchip RK3566, with a compact form factor and rich interfaces. The ZERO 3W and ZERO 3E are basically the same size and model, but differ only in storage and network interfaces. - eMMC (3W) - SD-card (both) - Ethernet (3E) - WiFi/BT (3W) Add initial support for eMMC, SD-card, Ethernet, HDMI and USB. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 +++++++++++++++++++++ .../boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 51 +++ .../boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++ 4 files changed, 607 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f42fa62b4064..3e5e9c833767 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,6 +90,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi new file mode 100644 index 000000000000..623d5939d194 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3566.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + + led-green { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca_1v8: regulator-1v8-vcca { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca1v8_image: regulator-1v8-vcca-image { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk817-clkout1", "rk817-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8_p: LDO_REG7 { + regulator-name = "vcc_1v8_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-name = "vcc5v_midu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-name = "vbus"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pinctrl { + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts new file mode 100644 index 000000000000..e166d66990b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3E"; + compatible = "radxa,zero-3e", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + gmac1_rstn: gmac1-rstn { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts new file mode 100644 index 000000000000..9bf4f464915f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3W"; + compatible = "radxa,zero-3w", "rockchip,rk3566"; + + aliases { + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From fc0daeccc384233eadfa9d5ddbd00159653c6bdc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:07 +0000 Subject: arm64: dts: rockchip: Add sdmmc related properties on rk3308-rock-pi-s Add cap-mmc-highspeed to allow use of high speed MMC mode using an eMMC to uSD board. Use disable-wp to signal that no physical write-protect line is present. Also add vcc_io used for card and IO line power as vmmc-supply. Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index b47fe02c33fb..09177713e57a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -264,7 +264,10 @@ }; &sdmmc { + cap-mmc-highspeed; cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 7affb86ef62581e3475ce3e0a7640da1f2ee29f8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:08 +0000 Subject: arm64: dts: rockchip: Add pinctrl for UART0 to rk3308-rock-pi-s UAR0 CTS/RTS is not wired to any pin and is not used for the default serial console use of UART0 on ROCK Pi S. Override the SoC defined pinctrl props to limit configuration of the two xfer pins wired to one of the GPIO pin headers. Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index 09177713e57a..97438f539333 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -286,6 +286,8 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 4b64ed510ed946a4e4ca6d51d6512bf5361f6a04 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:10 +0000 Subject: arm64: dts: rockchip: Add mdio and ethernet-phy nodes to rk3308-rock-pi-s Be explicit about the Ethernet port and define mdio and ethernet-phy nodes in the device tree for ROCK Pi S. Fixes: bc3753aed81f ("arm64: dts: rockchip: rock-pi-s add more peripherals") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-8-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 26 ++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index 97438f539333..eb7718833e53 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -136,11 +136,25 @@ &gmac { clock_in_out = "output"; + phy-handle = <&rtl8201f>; phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -213,6 +227,12 @@ pinctrl-names = "default"; pinctrl-0 = <&rtc_32k>; + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { green_led_gio: green-led-gpio { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3-58-ga151 From 36d3bbc8cdbef2f83391f7708888265ac4c37a99 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:11 +0000 Subject: arm64: dts: rockchip: Add OTP device node for RK3308 The RK3308 SoC contains a controller for one-time-programmable memory, add a device node for it. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-9-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 962ea893999b..ca2a20893fd0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -556,6 +556,30 @@ status = "disabled"; }; + otp: efuse@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + }; + dmac0: dma-controller@ff2c0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff2c0000 0x0 0x4000>; -- cgit v1.2.3-58-ga151 From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:14 +0000 Subject: arm64: dts: rockchip: Add rk3308 IO voltage domains Add a disabled RK3308 IO voltage domains node to SoC DT. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index ca2a20893fd0..9996e022fef8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -173,6 +173,11 @@ compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; reg = <0x0 0xff000000 0x0 0x08000>; + io_domains: io-domains { + compatible = "rockchip,rk3308-io-voltage-domain"; + status = "disabled"; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x500>; -- cgit v1.2.3-58-ga151 From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:15 +0000 Subject: arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage. Add io-domains node with the VCCIO supplies connected on the board. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index eb7718833e53..f58c76601807 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -223,6 +223,16 @@ status = "okay"; }; +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&rtc_32k>; -- cgit v1.2.3-58-ga151 From 12c3ec878cbe3709782e85b88124abecc3bb8617 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:10:16 +0000 Subject: arm64: dts: rockchip: Update WIFi/BT related nodes on rk3308-rock-pi-s Update WiFi SDIO and BT UART related props to better reflect details about the optional onboard RTL8723DS WiFi/BT module. Also correct the compatible used for bluetooth to match the WiFi/BT module used on the board. Fixes: bc3753aed81f ("arm64: dts: rockchip: rock-pi-s add more peripherals") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521211029.1236094-14-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 40 ++++++++++++++++++++--- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index f58c76601807..0b973c1a5ef9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -15,6 +15,7 @@ ethernet0 = &gmac; mmc0 = &emmc; mmc1 = &sdmmc; + mmc2 = &sdio; }; chosen { @@ -237,6 +238,20 @@ pinctrl-names = "default"; pinctrl-0 = <&rtc_32k>; + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + gmac { mac_rst: mac-rst { rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -286,11 +301,24 @@ cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <1000000>; + max-frequency = <100000000>; mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; non-removable; - sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; status = "okay"; + + rtl8723ds: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; }; &sdmmc { @@ -322,12 +350,16 @@ }; &uart4 { + uart-has-rtscts; status = "okay"; bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; }; }; -- cgit v1.2.3-58-ga151 From 768dfd7b49a24b02f1422bf8e2270bcdccea16b9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:22:42 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa ROCK S0 Add devicetree binding for the Radxa ROCK S0 board. Radxa ROCK S0 is a single-board computer based on the Rockchip RK3308B SoC in an ultra-compact form factor. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240521212247.1240226-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 51cdaabaf0d9..77469270b271 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -814,6 +814,11 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ROCK S0 + items: + - const: radxa,rock-s0 + - const: rockchip,rk3308 + - description: Radxa ZERO 3W/3E items: - enum: -- cgit v1.2.3-58-ga151 From adeb5d2a4ba47910238b3c4f5fd960cc0c26a98b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 21 May 2024 21:22:43 +0000 Subject: arm64: dts: rockchip: Add Radxa ROCK S0 Radxa ROCK S0 is a single-board computer based on the Rockchip RK3308B SoC in an ultra-compact form factor. Add initial support for eMMC, SD-card, Ethernet, WiFi/BT and USB. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240521212247.1240226-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts | 293 ++++++++++++++++++++++++ 2 files changed, 294 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3e5e9c833767..d80809038e8a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-s0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351v.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts new file mode 100644 index 000000000000..bd6419a5c20a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include "rk3308.dtsi" + +/ { + model = "Radxa ROCK S0"; + compatible = "radxa,rock-s0", "rockchip,rk3308"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led>; + + led-green { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_log: regulator-1v04-vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1040000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v5-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_io: regulator-3v3-vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_core: regulator-vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_core"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-handle = <&rtl8201f>; + phy-supply = <&vcc_io>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; + + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + pwr_led: pwr-led { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + }; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart4 { + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + clocks = <&cru SCLK_RTC32K>; + clock-names = "lpo"; + interrupt-parent = <&gpio4>; + interrupts = ; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + vbat-supply = <&vcc_io>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 54bf0c27380b95a220b94ea835b5e8bf58baded9 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Sat, 13 Apr 2024 16:18:05 +0200 Subject: arm64: dts: renesas: r8a779g0: Use MDIO node for all AVB devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch from defining the PHY inside the AVB node itself and create a dedicated MDIO node for AVB0, the only AVB describing a PHY. This is needed as adding PHYs to AVB1 and AVB2 will require setting MDIO bus parameters and thus requires a dedicated node. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240413141806.300989-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 6 ------ .../boot/dts/renesas/white-hawk-cpu-common.dtsi | 23 +++++++++++++--------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 9bc542bc6169..2ee306305d83 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -815,8 +815,6 @@ phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -862,8 +860,6 @@ phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -909,8 +905,6 @@ phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index 8ac17370ff36..b671bfab049b 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -142,18 +142,23 @@ &avb0 { pinctrl-0 = <&avb0_pins>; pinctrl-names = "default"; - phy-handle = <&phy0>; + phy-handle = <&avb0_phy>; tx-internal-delay-ps = <2000>; status = "okay"; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; }; }; -- cgit v1.2.3-58-ga151 From b4944dc7b7935a022be7f777d5cf47e0c1becc96 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Sat, 13 Apr 2024 16:18:06 +0200 Subject: arm64: dts: renesas: white-hawk: ethernet: Describe AVB1 and AVB2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe the two Marvell 88Q2110/QFN40 PHYs available on the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) sub-board. The two PHYs are wired up on the board by default, there is no need to move any resistors which are needed to access other PHYs available on this sub-board. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240413141806.300989-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/white-hawk-ethernet.dtsi | 103 +++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi index a218fda337cf..595ec4ff4cdd 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi @@ -6,6 +6,57 @@ * Copyright (C) 2022 Glider bv */ +/ { + aliases { + ethernet1 = &avb1; + ethernet2 = &avb2; + }; +}; + +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + &i2c0 { eeprom@53 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -14,3 +65,55 @@ pagesize = <8>; }; }; + +&pfc { + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + }; +}; -- cgit v1.2.3-58-ga151 From f50e5ddc3ff66434d011b031af3cdbac3d80bd82 Mon Sep 17 00:00:00 2001 From: Clément Léger Date: Mon, 13 May 2024 09:25:18 +0200 Subject: ARM: dts: renesas: r9a06g032: Describe GMAC1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named GMAC1/2, that are based on Synopsys cores. GMAC1 is connected to a RGMII/RMII converter that is already described in this device tree. Signed-off-by: Clément Léger [rgantois: commit log] Reviewed-by: Geert Uytterhoeven Signed-off-by: Romain Gantois Link: https://lore.kernel.org/r/20240513-rzn1-gmac1-v7-7-6acf58b5440d@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 45f60eeeaaa1..466077a8f0ac 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -316,6 +316,24 @@ data-width = <8>; }; + gmac1: ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupts = , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + status = "disabled"; + }; + gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>; -- cgit v1.2.3-58-ga151 From 200cba84b6a9e6b16f5c2a61ef231b199222028b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 15 May 2024 11:18:51 +0200 Subject: arm64: dts: renesas: gray-hawk-single: Add aliases for I2C buses They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240515091925.24353-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index cfbe8c8680cd..2b9a19bb1c5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -17,6 +17,10 @@ compatible = "renesas,gray-hawk-single", "renesas,r8a779h0"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; serial0 = &hscif0; serial1 = &hscif2; ethernet0 = &avb0; -- cgit v1.2.3-58-ga151 From 4406d43d82cd2f29dbd581833fd4aa6d467b23aa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 23 May 2024 11:18:45 +0200 Subject: arm64: dts: renesas: condor-i: Add I2C EEPROM The I2C EEPROM U197 on Condor is also present on Condor-I, but it was moved to the other side of the bi-directional voltage-level translator on I2C bus zero, and relabeled to U230. Move it to condor-common.dtsi to make it available on Condor-I, too. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/33a1ec9ee8fff7708f699c668d7399fde2b46553.1716455483.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 6 ++++++ arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 -------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 7c34d14dcd7e..8b7c0c34eadc 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -227,6 +227,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 68d1f1d53b3a..1d326552e2fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -14,11 +14,3 @@ model = "Renesas Condor board based on r8a77980"; compatible = "renesas,condor", "renesas,r8a77980"; }; - -&i2c0 { - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; -- cgit v1.2.3-58-ga151 From e9e6ed5a220f59a298db39b861500a6aea66e528 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 23 May 2024 22:50:38 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Add aliases for I2C buses They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240523205041.7356-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index b671bfab049b..80496fb3d476 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -13,6 +13,12 @@ / { aliases { ethernet0 = &avb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &hscif0; }; -- cgit v1.2.3-58-ga151 From 15a11ba906bd0156ee1fe31a871b2204d8175d63 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 23 May 2024 22:50:39 +0200 Subject: arm64: dts: renesas: spider-cpu: Add aliases for I2C buses They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240523205041.7356-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 477f3114d2fd..4ed8d4c37906 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -15,6 +15,12 @@ compatible = "renesas,spider-cpu", "renesas,r8a779f0"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &hscif0; serial1 = &scif0; }; -- cgit v1.2.3-58-ga151 From fefa929e898cc472ca2b225552659cabfa90d4e2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 23 May 2024 22:50:40 +0200 Subject: arm64: dts: renesas: s4sk: Add aliases for I2C buses They are numbered like this in the schematics, so keep the names in Linux the same. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240523205041.7356-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index bc65a7b4d999..fa910b85859e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -14,6 +14,12 @@ compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &hscif0; serial1 = &hscif1; ethernet0 = &rswitch; -- cgit v1.2.3-58-ga151 From 56ae780a4387d71dd709895acd95112d01f37fb4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 18 Apr 2024 09:44:21 +0300 Subject: arm64: dts: qcom: msm8996: add glink-edge nodes MSM8996 provides limited glink support, so add corresponding device tree nodes. For example the following interfaces are provided on db820c: modem: 2080000.remoteproc:glink-edge.LOOPBACK_CTL_MPSS.-1.-1 2080000.remoteproc:glink-edge.glink_ssr.-1.-1 2080000.remoteproc:glink-edge.rpmsg_chrdev.0.0 adsp: 9300000.remoteproc:glink-edge.LOOPBACK_CTL_LPASS.-1.-1 9300000.remoteproc:glink-edge.glink_ssr.-1.-1 9300000.remoteproc:glink-edge.rpmsg_chrdev.0.0 Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240418-msm8996-remoteproc-v2-2-b9ae852bf6bc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 5348feac026e..2e0f0d4f509f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2485,6 +2485,13 @@ status = "disabled"; + glink-edge { + interrupts = ; + label = "dsps"; + qcom,remote-pid = <3>; + mboxes = <&apcs_glb 27>; + }; + smd-edge { interrupts = ; @@ -2554,6 +2561,13 @@ memory-region = <&mdata_mem>; }; + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 15>; + }; + smd-edge { interrupts = ; @@ -3499,6 +3513,14 @@ status = "disabled"; + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 9>; + }; + + smd-edge { interrupts = ; -- cgit v1.2.3-58-ga151 From 1b80b83f893dd69efe3c3bf84cd9f661218ccfc0 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 18 Apr 2024 09:44:22 +0300 Subject: arm64: dts: qcom: msm8996: add fastrpc nodes The ADSP provides fastrpc/compute capabilities. Enable support for the fastrpc on this DSP. Signed-off-by: Srinivas Kandagatla Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240418-msm8996-remoteproc-v2-3-b9ae852bf6bc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 57 +++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2e0f0d4f509f..c6bc3dbff75f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3577,6 +3577,63 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,smd-channels = "fastrpcsmd-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&lpass_q6_smmu 5>; + }; + + cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&lpass_q6_smmu 6>; + }; + + cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&lpass_q6_smmu 7>; + }; + + cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&lpass_q6_smmu 8>; + }; + + cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&lpass_q6_smmu 9>; + }; + + cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&lpass_q6_smmu 10>; + }; + + cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&lpass_q6_smmu 11>; + }; + + cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&lpass_q6_smmu 12>; + }; + }; }; }; -- cgit v1.2.3-58-ga151 From 02f838b7f8cdfb7a96b7f08e7f6716f230bdecba Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 8 Apr 2024 03:04:31 +0300 Subject: arm64: dts: qcom: msm8996: specify UFS core_clk frequencies Follow the example of other platforms and specify core_clk frequencies in the frequency table in addition to the core_clk_src frequencies. The driver should be setting the leaf frequency instead of some interim clock freq. Suggested-by: Nitin Rawat Fixes: 57fc67ef0d35 ("arm64: dts: qcom: msm8996: Add ufs related nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240408-msm8996-fix-ufs-v4-1-ee1a28bf8579@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c6bc3dbff75f..8cb2def4c419 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2104,7 +2104,7 @@ <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; freq-table-hz = <100000000 200000000>, - <0 0>, + <100000000 200000000>, <0 0>, <0 0>, <0 0>, -- cgit v1.2.3-58-ga151 From 7e35767cb7876a8109d155086bc38974467dbb67 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 8 Apr 2024 03:04:32 +0300 Subject: arm64: dts: qcom: msm8996: set GCC_UFS_ICE_CORE_CLK freq directly Instead of setting the frequency of the interim UFS_ICE_CORE_CLK_SRC clock, set the frequency of the leaf GCC_UFS_ICE_CORE_CLK clock directly. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240408-msm8996-fix-ufs-v4-2-ee1a28bf8579@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8cb2def4c419..e545cae6f59c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2108,9 +2108,9 @@ <0 0>, <0 0>, <0 0>, - <150000000 300000000>, - <75000000 150000000>, <0 0>, + <75000000 150000000>, + <150000000 300000000>, <0 0>, <0 0>, <0 0>; -- cgit v1.2.3-58-ga151 From d3d8b80845eb51266407aa39310dab0a42b7c6ad Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 8 Apr 2024 03:04:34 +0300 Subject: arm64: dts: qcom: msm8996: drop source clock entries from the UFS node There is no need to mention and/or to touch in any way the intermediate (source) clocks. Drop them from MSM8996 UFSHCD schema, making it follow the example lead by all other platforms. Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240408-msm8996-fix-ufs-v4-4-ee1a28bf8579@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e545cae6f59c..785ba327f08c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2079,24 +2079,20 @@ power-domains = <&gcc UFS_GDSC>; clock-names = - "core_clk_src", "core_clk", "bus_clk", "bus_aggr_clk", "iface_clk", - "core_clk_unipro_src", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; clocks = - <&gcc UFS_AXI_CLK_SRC>, <&gcc GCC_UFS_AXI_CLK>, <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, <&gcc GCC_AGGRE2_UFS_AXI_CLK>, <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, <&gcc GCC_UFS_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_ICE_CORE_CLK>, <&rpmcc RPM_SMD_LN_BB_CLK>, @@ -2104,8 +2100,6 @@ <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; freq-table-hz = <100000000 200000000>, - <100000000 200000000>, - <0 0>, <0 0>, <0 0>, <0 0>, -- cgit v1.2.3-58-ga151 From 1fabbb0888c3d74366133de848228a899477aa34 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 27 May 2024 11:08:24 +0530 Subject: dt-bindings: vendor-prefixes: Add Schneider Electric Add vendor prefix for Schneider Electric (https://www.se.com/). Acked-by: Krzysztof Kozlowski Signed-off-by: Sumit Garg Link: https://lore.kernel.org/r/20240527053826.294526-2-sumit.garg@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..a00ddcce5556 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1254,6 +1254,8 @@ patternProperties: description: Smart Battery System "^schindler,.*": description: Schindler + "^schneider,.*": + description: Schneider Electric "^seagate,.*": description: Seagate Technology PLC "^seeed,.*": -- cgit v1.2.3-58-ga151 From 6cf67a2b51edfcef998b545f8aec18b9e8cefc80 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 27 May 2024 11:08:25 +0530 Subject: dt-bindings: arm: qcom: Add Schneider Electric HMIBSC board Document the compatible for the Schneider Electric HMIBSC IIoT edge box core board based on the Qualcomm APQ8016E SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sumit Garg Link: https://lore.kernel.org/r/20240527053826.294526-3-sumit.garg@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 00f37a174ce8..655e39f4fe2d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -96,6 +96,7 @@ properties: - items: - enum: - qcom,apq8016-sbc + - schneider,apq8016-hmibsc - const: qcom,apq8016 - items: -- cgit v1.2.3-58-ga151 From cceb16d201bb129dc019bb7df6ec746bf12b398d Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 27 May 2024 11:08:26 +0530 Subject: arm64: dts: qcom: apq8016: Add Schneider HMIBSC board DTS Add Schneider Electric HMIBSC board DTS. The HMIBSC board is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 1GiB RAM - 8GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI - USB ethernet adaptors (soldered) Co-developed-by: Jagdish Gediya Signed-off-by: Jagdish Gediya Reviewed-by: Caleb Connolly Reviewed-by: Stephan Gerhold Signed-off-by: Sumit Garg Link: https://lore.kernel.org/r/20240527053826.294526-4-sumit.garg@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/apq8016-schneider-hmibsc.dts | 491 +++++++++++++++++++++ 2 files changed, 492 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e8c5b364a09b..640ca4ceb106 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,6 +5,7 @@ apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts new file mode 100644 index 000000000000..75c6137e5a11 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Schneider Electric HMIBSC Board"; + compatible = "schneider,apq8016-hmibsc", "qcom,apq8016"; + + aliases { + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + spi0 = &blsp_spi5; + usid0 = &pm8916_0; + }; + + chosen { + stdout-path = "serial0"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&msm_key_volp_n_default>; + pinctrl-names = "default"; + + button { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pm8916_mpps_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usb-hub { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + adv_bridge: bridge@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + pinctrl-names = "default","sleep"; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&blsp_spi5 { + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +&blsp_uart1 { + label = "UART0"; + status = "okay"; +}; + +&blsp_uart2 { + label = "UART1"; + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&pm8916_codec { + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM", + "NC", + "NC"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "NC", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "NC"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; +}; + +&pm8916_resin { + linux,code = ; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "HMIBSC"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + status = "okay"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&tlmm { + pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>; + pinctrl-names = "default"; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* + * UART1 being the debug console supports various modes of + * operation (RS-232/485/422) controlled via GPIOs configured + * mux as follows: + * + * gpio100 gpio99 UART mode + * 0 0 loopback + * 0 1 RS-232 + * 1 0 RS-485 + * 1 1 RS-422 + * + * The default mode configured here is RS-232 mode. + */ + uart1_mux0_rs232_high: uart1-mux0-rs232-state { + bootph-all; + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + uart1_mux1_rs232_low: uart1-mux1-rs232-state { + bootph-all; + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; + pinctrl-names = "default", "device"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + firmware-name = "qcom/apq8016/wcnss.mbn"; + status = "okay"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in msm8916.dtsi */ + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +&blsp_uart1_default { + bootph-all; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 5f2fd4aefac8ac376d1e4979d5237f5e7c53174d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 23 May 2024 09:59:33 +0200 Subject: dt-bindings: arm: qcom: Add Lenovo Smart Tab M10 (WiFi) This documents Lenovo Smart Tab M10 (WiFi) (model tbx605f) which is a 10.1" tablet by Lenovo based on the SDM450 SoC. Signed-off-by: Neil Armstrong Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240523-topic-sdm450-upstream-tbx605f-v1-1-e52b89133226@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 655e39f4fe2d..e99ccec4dbf4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -806,6 +806,7 @@ properties: - items: - enum: + - lenovo,tbx605f - motorola,ali - const: qcom,sdm450 -- cgit v1.2.3-58-ga151 From 14a1d1dc35d346a1523f38f6517c349dfa447a58 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 9 May 2024 16:06:48 +0200 Subject: dt-bindings: clock: rk3128: Add PCLK_MIPIPHY The DPHY's APB clock is required to be exposed in order to be able to enable it and access the phy's registers. Signed-off-by: Alex Bee Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240509140653.168591-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3128-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 6a47825dac5d..1be455ba4985 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -116,6 +116,7 @@ #define PCLK_GMAC 367 #define PCLK_PMU_PRE 368 #define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 /* hclk gates */ #define HCLK_SPDIF 440 -- cgit v1.2.3-58-ga151 From 1d3ac84d6a960baa50da4163160ae82f8dc74af6 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Fri, 17 May 2024 16:25:08 +0400 Subject: arm64: dts: rockchip: add rfkill node for M.2 Key E Bluetooth on Rock 5B By default the BT WAKE signal inside the M.2 key E connector on Radxa Rock 5B is driven low, which results in the Bluetooth function being disabled even if the inserted M.2 card supports it. Expose this signal as an RFKILL device so that it can be enabled by the userspace. Tested with an Intel AX210 card, which connects a Bluetooth device over the USB 2.0 bus. Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240517122509.4626-1-alchark@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index b8e15b76a8a6..4e2bf4eaef2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -65,6 +65,13 @@ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; }; + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { compatible = "regulator-fixed"; enable-active-high; -- cgit v1.2.3-58-ga151 From 62aad66b57466287925d17e7ed0f6f14fd6c5459 Mon Sep 17 00:00:00 2001 From: Gianluca Boiano Date: Tue, 2 Apr 2024 14:35:43 +0200 Subject: arm64: dts: qcom: pmi8950: add pwm node This node is actually found on some msm8953 devices (xiaomi-mido) and allows irled enablement Signed-off-by: Gianluca Boiano Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240402-pmi8950-pwm-support-v1-2-1a66899eeeb3@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 1029f3b1bb9a..b4822cb17a37 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -84,6 +84,14 @@ #address-cells = <1>; #size-cells = <0>; + pmi8950_pwm: pwm@b000 { + compatible = "qcom,pmi8950-pwm"; + reg = <0xb000 0x100>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8950_wled: leds@d800 { compatible = "qcom,pmi8950-wled"; reg = <0xd800>, <0xd900>; -- cgit v1.2.3-58-ga151 From 0ae1bf2e097354b4c85491d9cc165a0f8f972e7b Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 5 Apr 2024 19:06:10 +0500 Subject: dt-bindings: arm: qcom: Add msm8916 based Motorola devices Add compatible values for the msm8916 based Motorola smartphones. Signed-off-by: Nikita Travkin Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240405-msm8916-moto-init-v1-1-502b58176d34@trvn.ru Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index e99ccec4dbf4..10ac297b3c2e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -208,6 +208,9 @@ properties: - huawei,g7 - longcheer,l8910 - longcheer,l8150 + - motorola,harpia + - motorola,osprey + - motorola,surnia - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur -- cgit v1.2.3-58-ga151 From a204bf3fb7bd436787f715dddca2cb7c1c86c12f Mon Sep 17 00:00:00 2001 From: Joe Mason Date: Sat, 6 Apr 2024 11:14:28 +0000 Subject: arm64: dts: qcom: msm8916-samsung-fortuna: Add BMC150 accelerometer/magnetometer Some Grand Prime use a Bosch BMC150 accelerometer/magnetometer combo. The chip provides two separate I2C devices for the accelerometer and magnetometer that are already supported by the bmc150-accel and bmc150-magn driver. Signed-off-by: Joe Mason [Stephan: Move sensors to common dtsi, disabled by default] Signed-off-by: Stephan Gerhold [Raymond: Add it to grandprimelte. Use interrupts-extended] Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240406111348.14358-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 44 ++++++++++++++++++++++ .../boot/dts/qcom/msm8916-samsung-gprimeltecan.dts | 8 ++++ .../dts/qcom/msm8916-samsung-grandprimelte.dts | 8 ++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 62864cca0cbb..fa6bfce6d183 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -123,6 +123,43 @@ }; }; +&blsp_i2c2 { + /* Available sensors vary depending on model variant */ + status = "okay"; + + bosch_accel: accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + status = "disabled"; + }; + + bosch_magn: magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + status = "disabled"; + }; +}; + &blsp_i2c4 { status = "okay"; @@ -229,6 +266,13 @@ }; &tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + backlight_en_default: backlight-en-default-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 9d65fa58ba92..4dc74e8bf1d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -21,6 +21,14 @@ }; }; +&bosch_accel { + status = "okay"; +}; + +&bosch_magn { + status = "okay"; +}; + &mpss_mem { /* Firmware for gprimeltecan needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts index a66ce4b13547..cffad734c4df 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts @@ -10,6 +10,14 @@ chassis-type = "handset"; }; +&bosch_accel { + status = "okay"; +}; + +&bosch_magn { + status = "okay"; +}; + &mpss_mem { /* Firmware for grandprimelte needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; -- cgit v1.2.3-58-ga151 From 7f433e1e3c224b90d536109d7a37e116b98086fb Mon Sep 17 00:00:00 2001 From: Siddharth Manthan Date: Sat, 6 Apr 2024 11:14:45 +0000 Subject: arm64: dts: qcom: msm8916-samsung-fortuna: Add LSM303C accelerometer/magnetometer Some Grand Prime use a ST LSM303C accelerometer/magnetometer combo. Add support for it. Signed-off-by: Siddharth Manthan [Stephan: Move sensors to common dtsi (disabled by default)] Signed-off-by: Stephan Gerhold [Raymond: Use interrupts-extended] Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240406111348.14358-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8216-samsung-fortuna3g.dts | 8 ++++++ .../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 33 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts index 366914be7d53..e7f6df229f9a 100644 --- a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts +++ b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts @@ -9,3 +9,11 @@ compatible = "samsung,fortuna3g", "qcom,msm8916"; chassis-type = "handset"; }; + +&st_accel { + status = "okay"; +}; + +&st_magn { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index fa6bfce6d183..4f05cae68b37 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -158,6 +158,39 @@ status = "disabled"; }; + + st_accel: accelerometer@1d { + compatible = "st,lsm303c-accel"; + reg = <0x1d>; + interrupts-extended = <&tlmm 115 IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + st,drdy-int-pin = <1>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "-1"; + + status = "disabled"; + }; + + st_magn: magnetometer@1e { + compatible = "st,lsm303c-magn"; + reg = <0x1e>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "-1"; + + status = "disabled"; + }; }; &blsp_i2c4 { -- cgit v1.2.3-58-ga151 From e4558fcfbeb01c8bdb1163bc3c4f7c6227a22843 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sat, 6 Apr 2024 11:15:00 +0000 Subject: arm64: dts: qcom: msm8916-samsung-rossa: Add LIS2HH12 accelerometer Core Prime LTE uses ST LIS2HH12 accelerometer. Add support for it. [Stephen: Use common &st_accel definition from common dtsi] Signed-off-by: Stephan Gerhold Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240406111348.14358-4-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 08485dcc20de..13a848d97b9d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -32,3 +32,11 @@ &clk_pwm_backlight { status = "disabled"; }; + +&st_accel { + compatible = "st,lis2hh12"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 65321d09e38bfbebd0e66975e021b748844cf478 Mon Sep 17 00:00:00 2001 From: Ruby Iris Juric Date: Fri, 5 Apr 2024 19:06:11 +0500 Subject: arm64: dts: qcom: Add device tree for Motorola Moto G4 Play (harpia) Motorola Moto G4 Play is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound; - Accelerometer. msm8916 Moto devices share significant portion of the design so the common parts are separated into a common dtsi. Signed-off-by: Ruby Iris Juric Signed-off-by: Stephan Gerhold [Nikita: Split up to common dtsi] Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240405-msm8916-moto-init-v1-2-502b58176d34@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-motorola-common.dtsi | 161 +++++++++++++++++++++ .../boot/dts/qcom/msm8916-motorola-harpia.dts | 147 +++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 640ca4ceb106..d7b298d6ef8c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi new file mode 100644 index 000000000000..6a27d0ecd2ad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include +#include +#include + +/ { + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-1 = <&usb_id_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + touchscreen: touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + vio-supply = <&pm8916_l6>; + + syna,startup-delay-ms = <100>; + + rmi4-f01@1 { + reg = <1>; + syna,nosleep-mode = <1>; /* Allow sleeping */ + }; + + rmi4-f11@11 { + reg = <11>; + syna,sensor-type = <1>; /* Touchscreen */ + }; + }; +}; + +&blsp_uart1 { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5500000>; +}; + +&pm8916_resin { + linux,code = ; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* CTS/RTX are not used */ +&blsp_uart1_default { + pins = "gpio0", "gpio1"; +}; +&blsp_uart1_sleep { + pins = "gpio0", "gpio1"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + usb_id_sleep: usb-id-sleep-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts new file mode 100644 index 000000000000..8380451ebbf6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto G4 Play"; + compatible = "motorola,harpia", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&blsp_i2c1 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + }; + + /* charger@6b */ +}; + +&blsp_i2c4 { + status = "okay"; + + accelerometer@19 { + compatible = "bosch,bma253"; + reg = <0x19>; + + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>, + <&tlmm 119 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; + + /* proximity@49 */ +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,micbias1-ext-cap; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + pinctrl-0 = <&cdc_pdm_default &headset_switch_supply_en + &headset_switch_in>; + pinctrl-1 = <&cdc_pdm_sleep &headset_switch_supply_en + &headset_switch_in>; + pinctrl-names = "default", "sleep"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l16>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115", "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + battery_alert_default: battery-alert-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + headset_switch_in: headset-switch-in-state { + pins = "gpio112"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + headset_switch_supply_en: headset-switch-supply-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio118"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-58-ga151 From 24773481ae5e54f041a24b99037ba80775ec9fc5 Mon Sep 17 00:00:00 2001 From: Wiktor Strzębała Date: Fri, 5 Apr 2024 19:06:12 +0500 Subject: arm64: dts: qcom: Add Motorola Moto E 2015 LTE (surnia) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Motorola Moto E 2015 LTE is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound. Signed-off-by: Wiktor Strzębała [Valérie: Sound and modem] Co-developed-by: Valérie Roux Signed-off-by: Valérie Roux Signed-off-by: Stephan Gerhold [Nikita: Use common dtsi] Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240405-msm8916-moto-init-v1-3-502b58176d34@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-motorola-surnia.dts | 83 ++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d7b298d6ef8c..5bdf6ab9639b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts new file mode 100644 index 000000000000..eecf78ba45bb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto E 2015 LTE"; + compatible = "motorola,surnia", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&blsp_i2c4 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + + }; +}; + +&pm8916_codec { + qcom,micbias1-ext-cap; + qcom,micbias2-ext-cap; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC3", "MIC BIAS External1"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l16>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + battery_alert_default: battery-alert-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-58-ga151 From 83086701167434c444ecde8479f1b9d3e0804a65 Mon Sep 17 00:00:00 2001 From: Martijn Braam Date: Fri, 5 Apr 2024 19:06:13 +0500 Subject: arm64: dts: qcom: Add Motorola Moto G 2015 (osprey) Motorola Moto G 2015 is an msm8916 based smartphone. Supported features: - eMMC and SD; - Buttons; - Touchscreen; - USB; - Fuel Gauge; - Sound. Signed-off-by: Martijn Braam Signed-off-by: Stephan Gerhold [Nikita: Use common dtsi] Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240405-msm8916-moto-init-v1-4-502b58176d34@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-motorola-osprey.dts | 105 +++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5bdf6ab9639b..99d606a15449 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-osprey.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts new file mode 100644 index 000000000000..ec5589fc69bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto G 2015"; + compatible = "motorola,osprey", "qcom,msm8916"; + chassis-type = "handset"; + + reg_touch_vdda: regulator-touch-vdda { + compatible = "regulator-fixed"; + regulator-name = "touch_vdda"; + gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&touch_vdda_default>; + pinctrl-names = "default"; + startup-delay-us = <300>; + vin-supply = <&pm8916_l16>; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + + }; +}; + +&blsp_i2c6 { + /* magnetometer@c */ +}; + +&pm8916_codec { + qcom,micbias1-ext-cap; + qcom,micbias2-ext-cap; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC3", "MIC BIAS External1"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_touch_vdda>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + battery_alert_default: battery-alert-default-state { + pins = "gpio49"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touch_vdda_default: touch-vdda-default-state { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-58-ga151 From 92b9ce5b11d7ba281f5bf0029185d5c891b29344 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 9 Apr 2024 20:36:37 +0200 Subject: ARM: dts: qcom: msm8974-hammerhead: Update gpio hog node name Follow the gpio-hog bindings and use otg-hog as node name. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240409-qcom-pmic-gpio-hog-v2-2-5ff812d2baed@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 8eaa5b162815..fdb6e22986cf 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -330,7 +330,7 @@ power-source = ; }; - otg { + otg-hog { gpio-hog; gpios = <35 GPIO_ACTIVE_HIGH>; output-high; -- cgit v1.2.3-58-ga151 From 839936d9676bdc2e4dde63631131feb8870fa4d2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 18 Feb 2024 21:57:27 +0100 Subject: arm64: dts: qcom: qcs404: Use qcs404-hfpll compatible for hfpll Follow the updated bindings and use a QCS404-specific compatible for the HFPLL on this SoC. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240218-hfpll-yaml-v2-3-31543e0d6261@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ac451f378056..d591c83e4bac 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1324,7 +1324,7 @@ }; apcs_hfpll: clock-controller@b016000 { - compatible = "qcom,hfpll"; + compatible = "qcom,qcs404-hfpll"; reg = <0x0b016000 0x30>; #clock-cells = <0>; clock-output-names = "apcs_hfpll"; -- cgit v1.2.3-58-ga151 From c133cfc12cd717b72ce534477415446e1c33de47 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 8 Apr 2024 21:32:04 +0200 Subject: ARM: dts: qcom: msm8974: Use proper compatible for APCS syscon Use the apcs-kpss-global compatible for the APCS global mailbox block found on this SoC. This also resolves a dt-binding checker warning: arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dtb: syscon@f9011000: compatible: 'anyOf' conditional failed, one must be fixed: ['syscon'] is too short 'syscon' is not one of ['allwinner,sun8i-a83t-system-controller', 'allwinner,sun8i-h3-system-controller', 'allwinner,sun8i-v3s-system-controller', 'allwinner,sun50i-a64-system-controller', 'amd,pensando-elba-syscon', 'brcm,cru-clkset', 'freecom,fsg-cs2-system-controller', 'fsl,imx93-aonmix-ns-syscfg', 'fsl,imx93-wakeupmix-syscfg', 'hisilicon,dsa-subctrl', 'hisilicon,hi6220-sramctrl', 'hisilicon,pcie-sas-subctrl', 'hisilicon,peri-subctrl', 'hpe,gxp-sysreg', 'intel,lgm-syscon', 'loongson,ls1b-syscon', 'loongson,ls1c-syscon', 'marvell,armada-3700-usb2-host-misc', 'mediatek,mt8135-pctl-a-syscfg', 'mediatek,mt8135-pctl-b-syscfg', 'mediatek,mt8365-syscfg', 'microchip,lan966x-cpu-syscon', 'microchip,sparx5-cpu-syscon', 'mstar,msc313-pmsleep', 'nuvoton,ma35d1-sys', 'nuvoton,wpcm450-shm', 'rockchip,px30-qos', 'rockchip,rk3036-qos', 'rockchip,rk3066-qos', 'rockchip,rk3128-qos', 'rockchip,rk3228-qos', 'rockchip,rk3288-qos', 'rockchip,rk3368-qos', 'rockchip,rk3399-qos', 'rockchip,rk356 8-qos', 'rockchip,rk3588-qos', 'rockchip,rv1126-qos', 'starfive,jh7100-sysmain', 'ti,am62-usb-phy-ctrl', 'ti,am654-dss-oldi-io-ctrl', 'ti,am654-serdes-ctrl', 'ti,j784s4-pcie-ctrl'] from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml# Signed-off-by: Luca Weiss Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240408-msm8974-apcs-v1-2-90cb7368836e@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 5651bb31bd54..944098b5ad2b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -343,9 +343,11 @@ <0xf9002000 0x1000>; }; - apcs: syscon@f9011000 { - compatible = "syscon"; + apcs: mailbox@f9011000 { + compatible = "qcom,msm8974-apcs-kpss-global", + "qcom,msm8994-apcs-kpss-global", "syscon"; reg = <0xf9011000 0x1000>; + #mbox-cells = <1>; }; saw_l2: power-manager@f9012000 { -- cgit v1.2.3-58-ga151 From 574b9e8d078f16cc55967b16f10e610b5d374cff Mon Sep 17 00:00:00 2001 From: James McGregor Date: Fri, 26 Apr 2024 09:29:41 +0000 Subject: dt-bindings: input: sun4i-lradc-keys: Add H616 compatible The Allwinner H616 SoC has an LRADC which is compatible with the versions in existing SoCs. Add a compatible string for H616, with the R329 fallback. This is the same as the D1, so put them into an enum. Signed-off-by: James McGregor Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240426092924.15489-2-jamcgregor@protonmail.com Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index c384bf0bb25d..6bdb8040be65 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -22,7 +22,9 @@ properties: - const: allwinner,sun8i-a83t-r-lradc - const: allwinner,sun50i-r329-lradc - items: - - const: allwinner,sun20i-d1-lradc + - enum: + - allwinner,sun50i-h616-lradc + - allwinner,sun20i-d1-lradc - const: allwinner,sun50i-r329-lradc reg: -- cgit v1.2.3-58-ga151 From 048ed5efbc4eec85c114d915ee0739341499d4b9 Mon Sep 17 00:00:00 2001 From: James McGregor Date: Fri, 26 Apr 2024 09:29:48 +0000 Subject: ARM: dts: sun50i: Add LRADC node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a DT node for the Allwinner H616 LRADC describing the base address, interrupt, reset and clock gates. Signed-off-by: James McGregor Reviewed-by: Andre Przywara Reviewed-by: Jernej Škrabec Link: https://lore.kernel.org/r/20240426092924.15489-3-jamcgregor@protonmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 921d5f61d8d6..cd866d8667ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -602,6 +602,16 @@ #thermal-sensor-cells = <1>; }; + lradc: lradc@5070800 { + compatible = "allwinner,sun50i-h616-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x05070800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_KEYADC>; + resets = <&ccu RST_BUS_KEYADC>; + status = "disabled"; + }; + usbotg: usb@5100000 { compatible = "allwinner,sun50i-h616-musb", "allwinner,sun8i-h3-musb"; -- cgit v1.2.3-58-ga151 From 97babdce61f84f0344f91ca1b5bb702a375ccf03 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 28 Apr 2024 13:40:36 +0200 Subject: arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Add missing cache information to the Allwinner H6 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper H6 cache information. Adding the cache information to the H6 SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 The cache parameters for the H6 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner H6 V200 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 8a8591c4e7dd..2301c59b41b1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -29,6 +29,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -39,6 +46,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -49,6 +63,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -59,6 +80,22 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; -- cgit v1.2.3-58-ga151 From c452e215f8745912853a9d98ae23ddbdaa1f6104 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Mon, 27 May 2024 02:08:17 +0200 Subject: dt-bindings: arm: sunxi: Correct the descriptions for Pine64 boards Correct the descriptions of a few Pine64 boards and devices, according to their official names used in the Pine64 wiki and on the official Pine64 website. [1][2][3] This ensures consistency between the officially used names and the names in the source code. [1] https://wiki.pine64.org/wiki/PINE_A64 [2] https://wiki.pine64.org/wiki/PINE_H64 [3] https://pine64.org/devices/ Reviewed-by: Rob Herring (Arm) Cc: Marek Kraus Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/84cd1c70863704e950ca4cadffc7d5367434e06b.1716768092.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c6d0d8d81ed4..3196dbeb0cbb 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -708,12 +708,12 @@ properties: - const: olimex,a64-teres-i - const: allwinner,sun50i-a64 - - description: Pine64 + - description: Pine64 PINE A64 items: - const: pine64,pine64 - const: allwinner,sun50i-a64 - - description: Pine64+ + - description: Pine64 PINE A64+ items: - const: pine64,pine64-plus - const: allwinner,sun50i-a64 @@ -724,17 +724,17 @@ properties: - const: sochip,s3 - const: allwinner,sun8i-v3 - - description: Pine64 PineH64 model A + - description: Pine64 PINE H64 Model A items: - const: pine64,pine-h64 - const: allwinner,sun50i-h6 - - description: Pine64 PineH64 model B + - description: Pine64 PINE H64 Model B items: - const: pine64,pine-h64-model-b - const: allwinner,sun50i-h6 - - description: Pine64 LTS + - description: Pine64 PINE A64 LTS items: - const: pine64,pine64-lts - const: allwinner,sun50i-r18 @@ -763,17 +763,17 @@ properties: - const: pine64,pinephone - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Development Sample + - description: Pine64 PineTab Developer Sample items: - const: pine64,pinetab - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Early Adopter's batch (and maybe later ones) + - description: Pine64 PineTab Early Adopter items: - const: pine64,pinetab-early-adopter - const: allwinner,sun50i-a64 - - description: Pine64 SoPine Baseboard + - description: Pine64 SOPINE items: - const: pine64,sopine-baseboard - const: pine64,sopine -- cgit v1.2.3-58-ga151 From 523bfa3069eca7498e2ebb56206ac70c5ab6a74b Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Mon, 27 May 2024 02:08:18 +0200 Subject: arm64: dts: allwinner: Correct the model names for Pine64 boards Correct the model names of a few Pine64 boards and devices, according to their official names used in the Pine64 wiki and on the official Pine64 website. [1][2][3] This ensures consistency between the officially used names and the names in the source code. [1] https://wiki.pine64.org/wiki/PINE_A64 [2] https://wiki.pine64.org/wiki/PINE_H64 [3] https://pine64.org/devices/ Acked-by: Jernej Skrabec Cc: Marek Kraus Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/4a988518e0dba5de3ecfc172a0fa2b0653c00d8b.1716768092.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts index 596a25907432..709fe650a360 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts @@ -5,7 +5,7 @@ #include "sun50i-a64-sopine-baseboard.dts" / { - model = "Pine64 LTS"; + model = "Pine64 PINE A64 LTS"; compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", "allwinner,sun50i-a64"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index b54099b654c8..026d843cd7e0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -4,7 +4,7 @@ #include "sun50i-a64-pine64.dts" / { - model = "Pine64+"; + model = "Pine64 PINE A64+"; compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; /* TODO: Camera, touchscreen, etc. */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 2accb5ddf783..09e71fd60785 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -9,7 +9,7 @@ #include / { - model = "Pine64"; + model = "Pine64 PINE A64"; compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 6c65d5bc16ba..379c2c8466f5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -13,7 +13,7 @@ #include / { - model = "Pinebook"; + model = "Pine64 Pinebook"; compatible = "pine64,pinebook", "allwinner,sun50i-a64"; chassis-type = "laptop"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts index 6265360ce623..86cc85eb3d48 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts @@ -9,7 +9,7 @@ #include "sun50i-a64-pinetab.dts" / { - model = "PineTab, Early Adopter's version"; + model = "Pine64 PineTab Early Adopter"; compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index c6007df99938..f5fb1ee32dad 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -14,7 +14,7 @@ #include / { - model = "PineTab, Development Sample"; + model = "Pine64 PineTab Developer Sample"; compatible = "pine64,pinetab", "allwinner,sun50i-a64"; chassis-type = "tablet"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 5e66ce1a334f..be2347c8f267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -8,7 +8,7 @@ #include "sun50i-a64-sopine.dtsi" / { - model = "SoPine with baseboard"; + model = "Pine64 SOPINE on Baseboard carrier board"; compatible = "pine64,sopine-baseboard", "pine64,sopine", "allwinner,sun50i-a64"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index 66fe03910d5e..066fbeff8bfa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -8,7 +8,7 @@ /delete-node/ ®_gmac_3v3; / { - model = "Pine H64 model B"; + model = "Pine64 PINE H64 Model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; wifi_pwrseq: pwrseq { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 3910393be1f9..c8b275552872 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -9,7 +9,7 @@ #include / { - model = "Pine H64 model A"; + model = "Pine64 PINE H64 Model A"; compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { -- cgit v1.2.3-58-ga151 From 7360e752165496617e8fec4bbeb7aebf630ca775 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 28 Apr 2024 13:40:35 +0200 Subject: arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Add missing cache information to the Allwinner A64 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper A64 cache information. While there, use a more self-descriptive label for the L2 cache node, which also makes it more consistent with other SoC dtsi files. The cache parameters for the A64 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner A64 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 +++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index ce4aa44c3353..e868ca5ae753 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -51,10 +51,16 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -62,10 +68,16 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -73,10 +85,16 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -84,16 +102,25 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; - L2: l2-cache { + l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; -- cgit v1.2.3-58-ga151 From c8a346e408cb2e516472658ff191f13626d8571e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 17 Apr 2024 15:42:46 -0500 Subject: arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations. All the kryo CPUs are missing PMU compatibles, so they can't be fixed. Signed-off-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20240417204247.3216703-1-robh@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8976.dtsi | 12 +++++++++--- arch/arm64/boot/dts/qcom/sm4450.dtsi | 11 ++++++++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++++++++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 +++++++++++++++++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++-- 6 files changed, 60 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index 668e05185c21..fa36b62156bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -8,8 +8,8 @@ #include "msm8976.dtsi" -&pmu { - interrupts = ; +&pmu_a72 { + interrupts = ; }; &tsens { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 1b158608c49d..861c24cc2556 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -222,11 +222,17 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; }; + pmu_a72: pmu-a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 8d75c4f9731c..9c9919e78fbd 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -292,9 +292,14 @@ reg = <0x0 0xa0000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; }; psci { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 708107da0ab0..e01b4d4c07f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -301,8 +301,18 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + pmu-x1 { + compatible = "arm,cortex-x1-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 79311a6bd1ad..9564963fbabf 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -352,8 +352,23 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a510 { + compatible = "arm,cortex-a510-pmu"; + interrupts = ; + }; + + pmu-a710 { + compatible = "arm,cortex-a710-pmu"; + interrupts = ; + }; + + pmu-a715 { + compatible = "arm,cortex-a715-pmu"; + interrupts = ; + }; + + pmu-x3 { + compatible = "arm,cortex-x3-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1774be6c53e5..336c54242778 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -390,8 +390,18 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = ; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = ; + }; + + pmu-x4 { + compatible = "arm,cortex-x4-pmu"; interrupts = ; }; -- cgit v1.2.3-58-ga151 From bbb1dd6402f9c67ea00bc6bf0e2a01d71db4c7fd Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 18 Apr 2024 08:36:54 +0200 Subject: arm64: dts: qcom: pmi632: Add vibrator Add a node for the vibrator module found inside the PMI632. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240418-fp3-vibra-v1-1-b636b8b3ff32@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi632.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 94d53b1cf6c8..b4313728f3e7 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -200,5 +200,11 @@ status = "disabled"; }; + + pmi632_vib: vibrator@5700 { + compatible = "qcom,pmi632-vib"; + reg = <0x5700>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-58-ga151 From ffaa4b5d5d07aed600d82929d8862263ce341a71 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 18 Apr 2024 08:36:55 +0200 Subject: arm64: dts: qcom: sdm632-fairphone-fp3: Enable vibrator Enable the vibrator on the PMI632 which is used on this phone. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240418-fp3-vibra-v1-2-b636b8b3ff32@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index e2708c74e95a..2c1172aa97e4 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -143,6 +143,10 @@ status = "okay"; }; +&pmi632_vib { + status = "okay"; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; -- cgit v1.2.3-58-ga151 From 737abcabe97bb37e38be2504acd28ad779dbaf3d Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Mon, 29 Apr 2024 16:07:27 +0200 Subject: arm64: dts: qcom: msm8998: set qcom,no-msa-ready-indicator for wifi The ath10k driver waits for an "MSA_READY" indicator to complete initialization. If the indicator is not received, then the device remains unusable. cf. ath10k_qmi_driver_event_work() Several msm8998-based devices are affected by this issue. Oddly, it seems safe to NOT wait for the indicator, and proceed immediately when QMI_EVENT_SERVER_ARRIVE. Jeff Johnson wrote: The feedback I received was "it might be ok to change all ath10k qmi to skip waiting for msa_ready", and it was pointed out that ath11k (and ath12k) do not wait for it. However with so many deployed devices, "might be ok" isn't a strong argument for changing the default behavior. cf. also https://wiki.postmarketos.org/wiki/Qualcomm_Snapdragon_835_(MSM8998)#WLAN Signed-off-by: Marc Gonzalez Acked-by: Jeff Johnson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/0914f96e-fcfd-4088-924a-fc1991bce75f@freebox.fr Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 254c12d7373c..580b7cabf757 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3194,6 +3194,7 @@ iommus = <&anoc2_smmu 0x1900>, <&anoc2_smmu 0x1901>; qcom,snoc-host-cap-8bit-quirk; + qcom,no-msa-ready-indicator; }; }; }; -- cgit v1.2.3-58-ga151 From 49cc31f8ab44e60d8109da7e18c0983a917d4d74 Mon Sep 17 00:00:00 2001 From: Sagar Cheluvegowda Date: Tue, 14 May 2024 17:06:51 -0700 Subject: arm64: dts: qcom: sa8775p: mark ethernet devices as DMA-coherent Ethernet devices are cache coherent, mark it as such in the dtsi. Fixes: ff499a0fbb23 ("arm64: dts: qcom: sa8775p: add the first 1Gb ethernet interface") Fixes: e952348a7cc7 ("arm64: dts: qcom: sa8775p: add a node for EMAC1") Signed-off-by: Sagar Cheluvegowda Link: https://lore.kernel.org/r/20240514-mark_ethernet_devices_dma_coherent-v4-1-04e1198858c5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 5632fa896b93..b760f625ff09 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3430,6 +3430,7 @@ phy-names = "serdes"; iommus = <&apps_smmu 0x140 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; @@ -3464,6 +3465,7 @@ phy-names = "serdes"; iommus = <&apps_smmu 0x120 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; -- cgit v1.2.3-58-ga151 From 42870599f9441fc96f99050637d2dce6f8b52597 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Sat, 18 May 2024 19:01:42 +0530 Subject: arm64: dts: qcom: sm8450: Add interconnect path to PCIe node Add PCIe-MEM & CPU-PCIe interconnect path to the PCIe nodes. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru Link: https://lore.kernel.org/r/20240518-opp_support-v13-1-78c73edf50de@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index ddbf97b84764..db43b70c0660 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1803,6 +1803,12 @@ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1932,6 +1938,12 @@ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, -- cgit v1.2.3-58-ga151 From 628388982c1303283b220a47e69906f0924e4031 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Sat, 18 May 2024 19:01:45 +0530 Subject: arm64: dts: qcom: sm8450: Add OPP table support to PCIe PCIe host controller driver needs to choose the appropriate performance state of RPMh power domain and interconnect bandwidth based on the PCIe data rate. Hence, add the OPP table support to specify RPMh performance states and interconnect peak bandwidth. It should be noted that the different link configurations may share the same aggregate bandwidth, e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same bandwidth and share the same OPP entry. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru Link: https://lore.kernel.org/r/20240518-opp_support-v13-4-78c73edf50de@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index db43b70c0660..fe9cb0804285 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1851,8 +1851,35 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; @@ -1984,8 +2011,56 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; -- cgit v1.2.3-58-ga151 From 7bb38c20f2b64a65423e64e6765bd70a5eadee81 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 17 Apr 2024 06:37:29 -0700 Subject: arm64: dts: qcom: sdm845: Add DT nodes for the TBUs Add the device-tree nodes for the TBUs (translation buffer units) that are present on the sdm845 platforms. The TBUs can be used debug the kernel and provide additional information when a context faults occur. Describe the all registers, clocks, interconnects and power-domain resources that are needed for each of the TBUs. Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20240417133731.2055383-6-quic_c_gdjako@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 26b1638c76f9..493c99c8ce10 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -5107,6 +5108,78 @@ ; }; + anoc_1_tbu: tbu@150c5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c5000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@150c9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@150cd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150cd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@150d1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d1000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@150d5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_tbu: tbu@150d9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@150dd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150dd000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@150e1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; -- cgit v1.2.3-58-ga151 From d1f2b41e96f5d1c2241ef3740a5829d2f9979273 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 17 Apr 2024 06:37:31 -0700 Subject: arm64: dts: qcom: sc7280: Add DT nodes for the TBUs Add the device-tree nodes for the TBUs (translation buffer units) that are present on the sc7280 platforms. The TBUs can be used debug the kernel and provide additional information when a context faults occur. Describe all the registers, clocks, interconnects and power-domain resources that are needed for each of the TBUs. Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20240417133731.2055383-8-quic_c_gdjako@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e3ff325576de..c3aaa09b8187 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2990,6 +2990,18 @@ dma-coherent; }; + gfx_0_tbu: tbu@3dd9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x3dd9000 0x0 0x1000>; + qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; + }; + + gfx_1_tbu: tbu@3ddd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x3ddd000 0x0 0x1000>; + qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7280-mpss-pas"; reg = <0 0x04080000 0 0x10000>; @@ -5862,6 +5874,83 @@ ; }; + anoc_1_tbu: tbu@151dd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151dd000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@151e1000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e1000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@151e5000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@151e9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e9000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + compute_dsp_1_tbu: tbu@151ed000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151ed000 0x0 0x1000>; + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_0_tbu: tbu@151f1000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f1000 0x0 0x1000>; + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@151f5000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f5000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@151f9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f9000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@151fd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151fd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0 0x17a00000 0 0x10000>, /* GICD */ -- cgit v1.2.3-58-ga151 From d328da7f07563c1a4a21eae4b28b7b69d9ba3df9 Mon Sep 17 00:00:00 2001 From: Alexandru Marc Serdeliuc Date: Thu, 11 Apr 2024 18:51:30 +0200 Subject: dt-bindings: arm: qcom: Add Samsung Galaxy Z Fold5 This documents Samsung Galaxy Z Fold5 (samsung,q5q) which is a foldable phone by Samsung based on the sm8550 SoC. Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandru Marc Serdeliuc Link: https://lore.kernel.org/r/20240411-samsung-galaxy-zfold5-q5q-v6-1-8142297515aa@yahoo.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 10ac297b3c2e..c82c68f06e79 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1012,6 +1012,7 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - samsung,q5q - sony,pdx234 - const: qcom,sm8550 -- cgit v1.2.3-58-ga151 From ba2c082a401ff6ea0f3460cd80174b4c8273445d Mon Sep 17 00:00:00 2001 From: Alexandru Marc Serdeliuc Date: Thu, 11 Apr 2024 18:51:31 +0200 Subject: arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5 Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone based on sm8550 Currently working features: - Framebuffer - UFS - i2c - Buttons Signed-off-by: Alexandru Marc Serdeliuc Link: https://lore.kernel.org/r/20240411-samsung-galaxy-zfold5-q5q-v6-2-8142297515aa@yahoo.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 593 ++++++++++++++++++++++++ 2 files changed, 594 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 99d606a15449..ca0ab0412fee 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -247,6 +247,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts new file mode 100644 index 000000000000..4654ae1364ba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -0,0 +1,593 @@ +// SPDX-License-cdsp_memIdentifier: BSD-3-Clause +/* + * Copyright (c) 2024, Alexandru Marc Serdeliuc + * Copyright (c) 2024, David Wronek + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sm8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &adspslpi_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mpss_dsm_mem; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; + +/ { + model = "Samsung Galaxy Z Fold5"; + compatible = "samsung,q5q", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@b8000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xb8000000 0x0 0x2b00000>; + width = <2176>; + height = <1812>; + stride = <(2176 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + adspslpi_mem: adspslpi@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x59b4000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0 0x9c900000 0 0x2000000>; + no-map; + }; + + mpss_dsm_mem: mpss-dsm@d4d00000 { + reg = <0x0 0xd4d00000 0x0 0x3300000>; + no-map; + }; + + mpss_mem: mpss@8b400000 { + reg = <0x0 0x8b400000 0x0 0xfc00000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@d4a80000 { + reg = <0x0 0xd4a80000 0x0 0x280000>; + no-map; + }; + + /* + * The bootloader will only keep display hardware enabled + * if this memory region is named exactly 'splash_region' + */ + splash_region@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l3c_0p91: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e_0p9: smps4 { + regulator-name = "vreg_s4e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p1: smps5 { + regulator-name = "vreg_s5e_1p1"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name = "vreg_l3f_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vreg_s1g_1p2: smps1 { + regulator-name = "vreg_s1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p8: smps2 { + regulator-name = "vreg_s2g_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p7: smps3 { + regulator-name = "vreg_s3g_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p3: smps4 { + regulator-name = "vreg_s4g_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p8: smps5 { + regulator-name = "vreg_s5g_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p8: smps6 { + regulator-name = "vreg_s6g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name = "vreg_l1m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name = "vreg_l2n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name = "vreg_l3n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name = "vreg_l4n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name = "vreg_l5n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name = "vreg_l6n_3p3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name = "vreg_l7n_2p96"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + status = "disabled"; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mdt", + "qcom/sm8550/adsp_dtb.mdt"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mdt", + "qcom/sm8550/cdsp_dtb.mdt"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mdt", + "qcom/sm8550/modem_dtb.mdt"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, <50 2>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- cgit v1.2.3-58-ga151 From 2559e61e7ef4efe546f081d8bee917e410e8e6a9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 May 2024 13:17:18 +0200 Subject: arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs During the initial bringup, all of the peripherals on non-SMB PMICs were either not used, or were not necessary to accomplish certain goals. This however, left a hole in the hardware description. Add the missing ones. Note that the PM8010 errors out on reads on the CRD (works fine on the QCP) for reasons unknown, but that shall be ironed out in the future.. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240529-topic-x1e_pmic-v1-2-9de0506179eb@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 480 +++++++++++++++++++++++++++ 1 file changed, 480 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index 04301f772fbd..a5662d39fdff 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -3,10 +3,477 @@ * Copyright (c) 2024, Linaro Limited */ +#include +#include #include #include / { + thermal-zones { + pm8550-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-2-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_2_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-3-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_3_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-4-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_4_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-5-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_5_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-6-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_6_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-8-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_8_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-9-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_9_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8010-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + /* PMK8380 */ + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + /* Not yet sure what blocks access */ + status = "reserved"; + }; + + pmk8550_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + + pmk8550_gpios: gpio@8800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380C */ + pm8550: pmic@1 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8550_flash: led-controller@ee00 { + compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pm8550_pwm: pwm { + compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm"; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; + + /* PMC8380VE */ + pm8550ve_2: pmic@2 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_2_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_2_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380 is actually not a PM8550 series rebrand */ + pmc8380_3: pmic@3 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_3_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_3_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_4: pmic@4 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_4_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_4_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_4_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_5: pmic@5 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_5_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_5_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_5_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_6: pmic@6 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_6_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_6_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_6_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380VE */ + pm8550ve_8: pmic@8 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_8_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_8_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_8_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380VE */ + pm8550ve_9: pmic@9 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_9_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_9_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_9_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8010: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; }; &spmi_bus1 { @@ -48,4 +515,17 @@ #phy-cells = <0>; }; }; + + smb2360_3: pmic@c { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_3_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; }; -- cgit v1.2.3-58-ga151 From d4ec229eaeb8453ad7244fc1d919ac51ac5ba394 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Tue, 28 May 2024 18:45:16 +0200 Subject: arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Add missing cache information to the Allwinner H616 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper H616 cache information. Adding the cache information to the H616 SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 Rather conspicuously, almost no cache-related information is available in the publicly available Allwinner H616 datasheet (version 1.0) and H616 user manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were obtained and derived by hand from the cache size and layout specifications found in the following technical reference manual, and from the cache size and die revision hints available from the following community-provided data and memory subsystem benchmarks: - ARM Cortex-A53 revision r0p4 TRM, version J - Summary of the two available H616 die revisions and their differences in cache sizes observed from the CSSIDR_EL1 register readouts, provided by Andre Przywara [1][2] - Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC, provided by Thomas Kaiser [3] For future reference, here's a brief summary of the available documentation and the community-provided data and memory subsystem benchmarks: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The size of the L2 cache depends on the actual H616 die revision (there are two die revisions), so the entire SoC can have either 256 KB or 1 MB of unified L2 16-way, set-associative cache [1] Also for future reference, here's the relevant excerpt from the community- provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and 256 KB are the L1 data and L2 cache sizes, respectively: block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 4.3 ns / 7.3 ns 131072 : 6.6 ns / 10.5 ns 262144 : 9.8 ns / 15.2 ns 524288 : 91.8 ns / 142.9 ns 1048576 : 138.6 ns / 188.3 ns 2097152 : 163.0 ns / 204.8 ns 4194304 : 178.8 ns / 213.5 ns 8388608 : 187.1 ns / 217.9 ns 16777216 : 192.2 ns / 220.9 ns 33554432 : 196.5 ns / 224.0 ns 67108864 : 215.7 ns / 259.5 ns The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch will perform runtime adjustment of the device tree data, making the correct L2 cache size of 1 MB present in the device tree for the boards based on the revision of H616 that actually provides 1 MB of L2 cache. [1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/ [2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/ [3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt Suggested-by: Andre Przywara Helped-by: Andre Przywara Reviewed-by: Andre Przywara Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/e4b9cc3e3d366a571e552c31dafa5de847bc1c12.1716914537.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index cd866d8667ec..20564cc02267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -27,6 +27,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -36,6 +43,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -45,6 +59,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -54,6 +75,22 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; }; }; -- cgit v1.2.3-58-ga151 From f51df82d984838b960592ec83d9ec92de8d8c094 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 30 May 2024 01:39:16 +0200 Subject: dt-bindings: arm: qcom: Add QCM6490 SHIFTphone 8 The SHIFTphone 8 (codename otter) is a smartphone based on the QCM6490 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20240530-otter-bringup-v3-1-79e7a28c1b08@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c82c68f06e79..34d32f70a856 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -373,6 +373,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - shift,otter - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform -- cgit v1.2.3-58-ga151 From 249666e34c24aba3f12a201c79d19ab2a3ca3e17 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 30 May 2024 01:39:17 +0200 Subject: arm64: dts: qcom: add QCM6490 SHIFTphone 8 The SHIFTphone 8 is an upcoming QCM6490 smartphone, it has the following features: * 12GB of RAM, 512GB UFS storage * 1080p display. * Hardware kill switches for cameras and microphones * UART access via type-c SBU pins (enabled by an internal switch) Initial support includes: * Framebuffer display * UFS and sdcard storage * Battery monitoring and USB role switching via pmic glink * Bluetooth * Thermals * Wifi Signed-off-by: Caleb Connolly Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20240530-otter-bringup-v3-2-79e7a28c1b08@linaro.org [bjorn: Fixed indent of block comments] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 926 +++++++++++++++++++++++ 2 files changed, 927 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ca0ab0412fee..56992fc3fc59 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -98,6 +98,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts new file mode 100644 index 000000000000..e82938cab953 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -0,0 +1,926 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Luca Weiss + * Copyright (c) 2024, Caleb Connolly + */ + +/dts-v1/; + +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include "sc7280.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &rmtfs_mem; + +/ { + model = "SHIFT SHIFTphone 8"; + compatible = "shift,otter", "qcom,qcm6490"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + serial1 = &uart7; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@a000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_down_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + cont_splash_mem: cont-splash@e1000000 { + reg = <0x0 0xe1000000 0x0 0x2300000>; + no-map; + }; + + cdsp_mem: cdsp@88f00000 { + reg = <0x0 0x88f00000 0x0 0x1e00000>; + no-map; + }; + + rmtfs_mem: rmtfs@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = , ; + }; + }; + + thermal-zones { + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-cam-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b: smps8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vreg_l6b: ldo6 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + /* Constrained for UFS VCC, at least until UFS driver scales voltage */ + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + regulator-initial-mode = ; + }; + + vreg_s9c: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l3c: ldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l4c: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c: ldo6 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c: ldo9 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm6490/SHIFT/otter/a660_zap.mbn"; +}; + +&i2c1 { + status = "okay"; + + /* PM8008 PMIC @ 8 and 9 */ + /* rtc6226 FM receiver @ 64 */ + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /* tas2563 audio codec @ 4d */ +}; + +&i2c9 { + status = "okay"; + + /* TMS(?) NFC @ 28 */ + /* Ti drv2624 haptics @ 5a */ +}; + +&i2c13 { + status = "okay"; + + /* focaltech FT3658U @ 38 */ +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn"; + status = "okay"; +}; + +&pm7250b_adc { + channel@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "charger_skin_therm"; + }; + + channel@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + charger-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7325_gpios { + volume_down_default: volume-down-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + cam-flash-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wide-rfc-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@145 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_cam_flash_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; + + channel@147 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_wide_rfc_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/SHIFT/otter/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/SHIFT/otter/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/SHIFT/otter/modem.mbn"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcm6490/SHIFT/otter/wpss.mbn"; + status = "okay"; +}; + +&sdc2_clk { + drive-strength = <16>; + bias-disable; +}; + +&sdc2_cmd { + drive-strength = <10>; + bias-pull-up; +}; + +&sdc2_data { + drive-strength = <10>; + bias-pull-up; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l9c>; + vqmmc-supply = <&vreg_l6c>; + + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; + + status = "okay"; +}; + +&tlmm { + /* + * 48-52: protected by XPU, not sure why. + */ + gpio-reserved-ranges = <48 4>; + + bluetooth_enable_default: bluetooth-enable-default-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio86"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart7 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + pinctrl-0 = <&bluetooth_enable_default>, <&sw_ctrl_default>; + pinctrl-names = "default"; + + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_l19b>; + vddaon-supply = <&vreg_s7b>; + vddbtcxmx-supply = <&vreg_s7b>; + vddrfacmn-supply = <&vreg_s7b>; + vddrfa0p8-supply = <&vreg_s7b>; + vddrfa1p7-supply = <&vreg_s1b>; + vddrfa1p2-supply = <&vreg_s8b>; + vddrfa2p2-supply = <&vreg_s1c>; + vddasd-supply = <&vreg_l11c>; + + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b>; + vcc-max-microamp = <800000>; + /* + * Technically l9b enables an eLDO (supplied by s1b) which then powers + * VCCQ2 of the UFS. + */ + vccq-supply = <&vreg_l9b>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c>; + vdda-pll-supply = <&vreg_l6b>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l2b>; + + qcom,hs-crossover-voltage-microvolt = <28000>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + qcom,hs-rise-fall-time-bp = <5430>; + qcom,hs-disconnect-bp = <1743>; + qcom,hs-amplitude-bp = <2430>; + + qcom,pre-emphasis-amplitude-bp = <20000>; + qcom,pre-emphasis-duration-bp = <20000>; + + qcom,squelch-detector-bp = <(-2090)>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l1b>; + + status = "okay"; +}; + +&wifi { + qcom,ath11k-calibration-variant = "SHIFTphone_8"; + + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 809c20b1ffc80200bfcbbeceb0d946a3e0eed3a4 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Wed, 29 May 2024 18:15:34 +0800 Subject: arm64: dts: qcom: sa8775p: Add llcc support for the SA8775p platform Add llcc support for the SA8775p platform. Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240529101534.3166507-4-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b760f625ff09..eae0de9720b5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2885,6 +2885,25 @@ status = "disabled"; }; + llcc: system-cache-controller@9200000 { + compatible = "qcom,sa8775p-llcc"; + reg = <0x0 0x09200000 0x0 0x80000>, + <0x0 0x09300000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x80000>, + <0x0 0x09500000 0x0 0x80000>, + <0x0 0x09600000 0x0 0x80000>, + <0x0 0x09700000 0x0 0x80000>, + <0x0 0x09a00000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc_broadcast_base"; + interrupts = ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- cgit v1.2.3-58-ga151 From 718a2bb5fe7b2d67d887313f16f93cab5c43ab55 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:22 +0200 Subject: arm64: dts: stratix10: socdk: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: socfpga_stratix10_socdk.dts:182.10-211.4: Warning (avoid_unnecessary_addr_size): /soc@0/spi@ff8d2000/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 26173f0b0051..4eee777ef1a1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -180,8 +180,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; -- cgit v1.2.3-58-ga151 From 7f787253bca4fedfa97bfa087b8d3ae0105559de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:23 +0200 Subject: arm64: dts: stratix10: socdk_nand: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: socfpga_stratix10_socdk_nand.dts:171.10-200.4: Warning (avoid_unnecessary_addr_size): /soc@0/spi@ff8d2000/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 81d0e914a77c..7c53cb9621e5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -169,8 +169,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; -- cgit v1.2.3-58-ga151 From 41f7adb676f6c4aef439d78b15c7e1119216bc2b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:24 +0200 Subject: arm64: dts: agilex: socdk: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: socfpga_agilex_socdk.dts:108.10-137.4: Warning (avoid_unnecessary_addr_size): /soc@0/spi@ff8d2000/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index ad99aefeb185..b31cfa6b802d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -106,8 +106,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; -- cgit v1.2.3-58-ga151 From 32cdf4c75fdd135e66e11383aa84687873b77b89 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:25 +0200 Subject: arm64: dts: n5x: socdk: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: socfpga_n5x_socdk.dts:85.10-114.4: Warning (avoid_unnecessary_addr_size): /soc@0/spi@ff8d2000/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 2d70a92c2090..7952c7f47cc2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -83,8 +83,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; -- cgit v1.2.3-58-ga151 From 1536dc8edc653e0e4a333035a73ff146d0517749 Mon Sep 17 00:00:00 2001 From: Beniamin Sandu Date: Wed, 15 May 2024 19:12:49 +0100 Subject: arm64: dts: socfpga: stratix10: add L2 cache info This removes cacheinfo warnings at boot, e.g.: cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Beniamin Sandu Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index cbbc53c47921..0def0b0daaf7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -34,6 +34,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x0>; }; @@ -41,6 +42,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x1>; }; @@ -48,6 +50,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x2>; }; @@ -55,8 +58,15 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x3>; }; + + l2_shared: cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; }; firmware { -- cgit v1.2.3-58-ga151 From c566143137aaacfed1af09d8710edab1971c312d Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Fri, 31 May 2024 09:45:26 -0700 Subject: arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8450. Signed-off-by: Unnathi Chalicheemala Link: https://lore.kernel.org/r/bfc817da4188abdf5b543bedafb9cb0eb82806c2.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fe9cb0804285..216f4f703643 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4461,9 +4461,10 @@ compatible = "qcom,sm8450-llcc"; reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, - <0 0x19a00000 0 0x80000>; + <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; + "llcc3_base", "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = ; }; -- cgit v1.2.3-58-ga151 From 2a71a2eb1f5ec438f0ac1c7e294cd7ed32119af3 Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Fri, 31 May 2024 09:45:27 -0700 Subject: arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8550. Signed-off-by: Unnathi Chalicheemala Link: https://lore.kernel.org/r/9bb6e086adec4d3b2134462d504822fb79b009e7.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9564963fbabf..594813538863 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4311,12 +4311,14 @@ <0 0x25200000 0 0x200000>, <0 0x25400000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = ; }; -- cgit v1.2.3-58-ga151 From a7823576f7f7b1cb0a595332ab6b0b38e15f45a7 Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Fri, 31 May 2024 09:45:28 -0700 Subject: arm64: dts: qcom: sm8650: Add Broadcast_AND register in LLCC block Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8650. Signed-off-by: Unnathi Chalicheemala Link: https://lore.kernel.org/r/3a8804b35f44485637398faa9c0bda76813fe4d7.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 336c54242778..bb0b3c48ee4b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4994,12 +4994,14 @@ <0 0x25400000 0 0x200000>, <0 0x25200000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = ; }; -- cgit v1.2.3-58-ga151 From a5c84d2dde8089ece5e13f264359c6117ea3186b Mon Sep 17 00:00:00 2001 From: David Wronek Date: Fri, 31 May 2024 14:05:59 +0200 Subject: arm64: dts: qcom: sm8550-samsung-q5q: fix typo It looks like "cdsp_mem" was pasted in the license header by accident. Fix the typo by removing it. Signed-off-by: David Wronek Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240531-fix-typo-q5q-v1-1-95f10a8eff9b@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 4654ae1364ba..3d351e90bb39 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -1,4 +1,4 @@ -// SPDX-License-cdsp_memIdentifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2024, Alexandru Marc Serdeliuc * Copyright (c) 2024, David Wronek -- cgit v1.2.3-58-ga151 From 9ca6eaf1337693e4e626359b76016912921dc557 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Fri, 31 May 2024 17:35:30 +0800 Subject: dt-bindings: soc: qcom: add qcom,sa8775p-imem compatible Add qcom,sa8775p-imem compatible name support. Signed-off-by: Tengfei Fan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240531093531.238075-2-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 8025a852bc9c..faef3d6e0a94 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -22,6 +22,7 @@ properties: - qcom,msm8974-imem - qcom,qcs404-imem - qcom,qdu1000-imem + - qcom,sa8775p-imem - qcom,sc7180-imem - qcom,sc7280-imem - qcom,sdm630-imem -- cgit v1.2.3-58-ga151 From 93f340084d05e7c109c0de20cca429492a377c37 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Fri, 31 May 2024 17:35:31 +0800 Subject: arm64: dts: qcom: sa8775p: Add IMEM and PIL info region Add a simple-mfd representing IMEM on SA8775p and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Tengfei Fan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha Link: https://lore.kernel.org/r/20240531093531.238075-3-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index eae0de9720b5..89496728d840 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3044,6 +3044,20 @@ wakeup-parent = <&pdc>; }; + sram: sram@146d8000 { + compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; + reg = <0x0 0x146d8000 0x0 0x1000>; + ranges = <0x0 0x0 0x146d8000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; -- cgit v1.2.3-58-ga151 From 32a7b1d7c72bc846f417c457476efcfc4d283c6b Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Fri, 31 May 2024 17:04:21 +0800 Subject: arm64: dts: qcom: sm8550: Move usb-role-switch to SoC dtsi The usb-role-switch is SM8550 SoC property, so move it from board dts to SM8550 SoC dtsi. Signed-off-by: Tengfei Fan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240531090422.158813-2-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 - arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 - arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 31f52df6b67e..411de3451db8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1255,7 +1255,6 @@ &usb_1_dwc3 { dr_mode = "otg"; - usb-role-switch; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 42d4d558b7aa..84d16227ef80 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -948,7 +948,6 @@ &usb_1_dwc3 { dr_mode = "otg"; - usb-role-switch; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 2ed1715000c9..e20c6240f76d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1117,7 +1117,6 @@ &usb_1_dwc3 { dr_mode = "otg"; - usb-role-switch; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 92a88fb05609..6dd5232da9f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -739,7 +739,6 @@ &usb_1_dwc3 { dr_mode = "otg"; - usb-role-switch; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 594813538863..c55a818af935 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3279,6 +3279,7 @@ snps,has-lpm-erratum; tx-fifo-resize; dma-coherent; + usb-role-switch; ports { #address-cells = <1>; -- cgit v1.2.3-58-ga151 From 54bbf0a8ef45734531b12cc50528568e4220d1be Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Fri, 31 May 2024 17:04:22 +0800 Subject: arm64: dts: qcom: sm8550: Remove usb default dr_mode OTG is default usb dr_mode, so this property can be removed. Reviewed-by: Dmitry Baryshkov Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240531090422.158813-3-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 4 ---- 4 files changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 411de3451db8..e0dc03a97771 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1253,10 +1253,6 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 84d16227ef80..26dfca0c3e05 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -946,10 +946,6 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index e20c6240f76d..d27820fb5fc0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1115,10 +1115,6 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 6dd5232da9f9..85d487ef80a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -737,10 +737,6 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -- cgit v1.2.3-58-ga151 From ae5cee8e7349d7e5deff4cf90a08cbd738287155 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 30 May 2024 19:35:45 +0300 Subject: arm64: dts: qcom: x1e80100-crd: Fix USB PHYs regulators The 1.2v HS PHY shared regulator is actually LDO2 from PM8550ve id J. Also add the missing supplies to QMP PHYs. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-fix-usb-phy-supplies-v1-1-6eb72a546227@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 7e4a13969d25..722ed6181a0a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -832,7 +832,7 @@ &usb_1_ss0_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -840,6 +840,9 @@ }; &usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + status = "okay"; }; @@ -853,7 +856,7 @@ &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -861,6 +864,9 @@ }; &usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -874,7 +880,7 @@ &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; @@ -882,6 +888,9 @@ }; &usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; -- cgit v1.2.3-58-ga151 From 79abbcb13a9818bbc1701a1d2475a265a8275296 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:02 +0300 Subject: ARM: dts: qcom: apq8064: drop #power-domain-cells property of GCC On APQ8064 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-4-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 11e60b74c3c9..178a3b424670 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -684,7 +684,6 @@ compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&cxo_board>, <&pxo_board>, -- cgit v1.2.3-58-ga151 From 69eca4bd4c110eb748f68dc511b4dddec9fcd777 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:03 +0300 Subject: ARM: dts: qcom: msm8660: drop #power-domain-cells property of GCC On MSM8660 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-5-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index 455ba4bf1bf4..a66c474cd1aa 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -113,7 +113,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&pxo_board>, <&cxo_board>; -- cgit v1.2.3-58-ga151 From 660f6194693ede9c61cd9f01c36a7e56eff13dfd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:04 +0300 Subject: ARM: dts: qcom: msm8960: drop #power-domain-cells property of GCC On MSM8960 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-6-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 922f9e49468a..a9c6d2dbb460 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -129,7 +129,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, -- cgit v1.2.3-58-ga151 From c514f760b504fcb5bb34ea8daeb26f13c3561d95 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:05 +0300 Subject: ARM: dts: qcom: ipq4019: drop #power-domain-cells property of GCC On IPQ4019 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-7-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 0fb65f2bbcdf..56415ab34083 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -187,7 +187,6 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; clocks = <&xo>, <&sleep_clk>; -- cgit v1.2.3-58-ga151 From c39ce4b0a556408128fe11c25d22b7ba1d4a1c94 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:06 +0300 Subject: ARM: dts: qcom: ipq8064: drop #power-domain-cells property of GCC On IPQ8064 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-8-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index f128510d8445..12cf85441a0b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -519,7 +519,6 @@ reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; -- cgit v1.2.3-58-ga151 From 03df403dd7f495ce5e2324e4e6b4065b330acdc7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:07 +0300 Subject: ARM: dts: qcom: mdm9615: drop #power-domain-cells property of GCC On MDM9615 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-9-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 34c60994d026..573feb3218c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -102,7 +102,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-mdm9615"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, -- cgit v1.2.3-58-ga151 From 20676f7819d7364b7e8bd437b212106faa893b49 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 30 May 2024 19:35:46 +0300 Subject: arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulators The 1.2v HS PHY shared regulator is actually LDO2 from PM8550ve id J. Also add the missing supplies to QMP PHYs. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-fix-usb-phy-supplies-v1-2-6eb72a546227@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 1aebfa5f958d..d40dd2afda8a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -528,7 +528,7 @@ &usb_1_ss0_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -536,6 +536,9 @@ }; &usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + status = "okay"; }; @@ -549,7 +552,7 @@ &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -557,6 +560,9 @@ }; &usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -570,7 +576,7 @@ &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; @@ -578,6 +584,9 @@ }; &usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; -- cgit v1.2.3-58-ga151 From cf7d2157aa87dca6f078a2d4867fd0a9dbc357aa Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 30 May 2024 18:43:39 +0300 Subject: arm64: dts: qcom: x1e80100-crd: Fix the PHY regulator for PCIe 6a The actual PHY regulator is L1d instead of L3j, so fix it accordingly. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-1-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 722ed6181a0a..a1f901dda92f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -650,7 +650,7 @@ }; &pcie6a_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; -- cgit v1.2.3-58-ga151 From 87042003f6ea7d075784db98da6903738a38f3cf Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 30 May 2024 18:43:40 +0300 Subject: arm64: dts: qcom: x1e80100-qcp: Fix the PHY regulator for PCIe 6a The actual PHY regulator is L1d instead of L3j, so fix it accordingly. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Cc: stable@vger.kernel.org # 6.9 Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-2-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index d40dd2afda8a..2aec8ae2bf52 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -461,7 +461,7 @@ }; &pcie6a_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; -- cgit v1.2.3-58-ga151 From eb57cbe730d10ec8c6505492a9f3252b160e0f1e Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 30 May 2024 18:43:41 +0300 Subject: arm64: dts: qcom: x1e80100: Describe the PCIe 6a resources On both the CRD and QCP, on PCIe 6a sits the NVMe. Add the 3.3V gpio-controlled regulator and the clkreq, perst and wake gpios as resources for the PCIe 6a. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-3-ee17a9939ba5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 52 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 52 +++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index a1f901dda92f..4c327762f001 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -164,6 +164,20 @@ regulator-always-on; regulator-boot-on; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; }; &apps_rsc { @@ -646,6 +660,14 @@ }; &pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + status = "okay"; }; @@ -795,6 +817,36 @@ bias-disable; }; + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 2aec8ae2bf52..97c81667c6ca 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -50,6 +50,20 @@ regulator-always-on; regulator-boot-on; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; }; &apps_rsc { @@ -457,6 +471,14 @@ }; &pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + status = "okay"; }; @@ -519,6 +541,36 @@ drive-strength = <16>; bias-disable; }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; &uart21 { -- cgit v1.2.3-58-ga151 From 37ff5d0d75fece536cc493d0979e09f33edb75c4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 May 2024 17:05:47 +0200 Subject: arm64: dts: qcom: pm7250b: Add node for PMIC VBUS booster Add the required DTS node for the USB VBUS output regulator, which is available on PM7250B. This will provide the VBUS source to connected peripherals. Reviewed-by: Bryan O'Donoghue Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-1-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 3bf7cf5d1700..4faed25a787f 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -45,6 +45,12 @@ #address-cells = <1>; #size-cells = <0>; + pm7250b_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm7250b-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + pm7250b_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; -- cgit v1.2.3-58-ga151 From 6b5b15a1d785d5fb484d3a662b01776066d33137 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 May 2024 17:05:48 +0200 Subject: arm64: dts: qcom: pm7250b: Add a TCPM description Type-C port management functionality lives inside of the PMIC block on pm7250b. The Type-C port management logic controls orientation detection, vbus/vconn sense and to send/receive Type-C Power Domain messages. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-2-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 4faed25a787f..7dc7262f1537 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -51,6 +51,46 @@ status = "disabled"; }; + pm7250b_typec: typec@1500 { + compatible = "qcom,pm7250b-typec", "qcom,pm8150b-typec"; + reg = <0x1500>, + <0x1700>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + vdd-vbus-supply = <&pm7250b_vbus>; + status = "disabled"; + }; + pm7250b_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; -- cgit v1.2.3-58-ga151 From 6814d454c26b552f0009c803ffc0ce3434eaed7e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 May 2024 17:05:49 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB role switching Configure the Type-C and VBUS regulator on PM7250B and wire it up to the USB PHY, so that USB role and orientation switching works. For now USB Power Delivery properties are skipped / disabled, so that the (presumably) bootloader-configured charger doesn't get messed with and we can charge the phone with at least some amount of power. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240530-fp4-tcpm-v3-3-612d4bbd5e09@fairphone.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 1 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 50 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 58 +++++++++++++++++++++- 3 files changed, 108 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index dddd6e44d280..88ee04973a2f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -375,6 +375,7 @@ }; &usb_1_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "super-speed"; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index acf0b0f73af9..1ac626d963b8 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1715,10 +1715,39 @@ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; + orientation-switch; + #clock-cells = <1>; #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; dc_noc: interconnect@9160000 { @@ -1894,6 +1923,27 @@ snps,hird-threshold = /bits/ 8 <0x10>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index bc67e8c1fe4d..d2632f011353 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -19,6 +19,7 @@ #include #include #include +#include #include "sm7225.dtsi" #include "pm6150l.dtsi" #include "pm6350.dtsi" @@ -543,6 +544,53 @@ }; }; +&pm7250b_typec { + vdd-pdphy-supply = <&vreg_l3a>; + + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + /* + * Disable USB Power Delivery for now, seems to need extra work + * to support role switching while also letting the battery + * charge still - without charger driver + */ + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm7250b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; + }; + }; + + port@1 { + reg = <1>; + pm7250b_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; +}; + +&pm7250b_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1500000>; + status = "okay"; +}; + &pmk8350_rtc { status = "okay"; }; @@ -726,7 +774,11 @@ &usb_1_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + dr_mode = "otg"; +}; + +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm7250b_hs_in>; }; &usb_1_hsphy { @@ -744,6 +796,10 @@ status = "okay"; }; +&usb_1_qmpphy_out { + remote-endpoint = <&pm7250b_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&vreg_l4a>; vdd-1.8-xo-supply = <&vreg_l7a>; -- cgit v1.2.3-58-ga151 From cf2a08e149b28b4c8d9c63f84348f8d7fff0b5a7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 30 May 2024 11:31:56 +0300 Subject: arm64: dts: qcom: sm8650-hdk: remove redundant properties The commit 65931e59e039 ("arm64: dts: qcom: sm8650: move USB graph to the SoC dtsi") and commit fbb22a182267 ("arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsi") have moved some of the properties from the board DT files to the sm8650.dtsi. As the patch for sm8650 HDK predates those commits, it still had those properties inside. Drop these duplicate proerties from the sm8650-hdk.dts. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240530-sm8650-hdk-redundant-v1-1-c39c2ae65f3b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 7f2dbada63b5..182864a3b6bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -881,7 +881,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; &pcie0 { @@ -1220,10 +1219,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1i_0p88>; vdda12-supply = <&vreg_l3i_1p2>; @@ -1237,23 +1232,13 @@ vdda-phy-supply = <&vreg_l3i_1p2>; vdda-pll-supply = <&vreg_l3g_0p91>; - orientation-switch; - status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; -- cgit v1.2.3-58-ga151 From d1caecddf9f4bb17db10c8a46083a70688d0f46d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:08 +0300 Subject: arm64: dts: qcom: ipq5018: drop #power-domain-cells property of GCC On IPQ5018 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-10-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 32b178b639f0..7e6e2c121979 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -179,7 +179,6 @@ <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { -- cgit v1.2.3-58-ga151 From 2ad7dd5479c04026f8421f12baf7a2b482cf0bff Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:09 +0300 Subject: arm64: dts: qcom: ipq5332: drop #power-domain-cells property of GCC On IPQ5332 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-11-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 770d9c2fb456..573656587c0d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -208,7 +208,6 @@ reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, <0>, -- cgit v1.2.3-58-ga151 From ef3308cf52553522d619a858a72a68f82432865b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:10 +0300 Subject: arm64: dts: qcom: ipq9574: drop #power-domain-cells property of GCC On IPQ9574 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-12-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index ded02bc39275..d21937b09b4b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -315,7 +315,6 @@ <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { -- cgit v1.2.3-58-ga151 From 6c2e3ca212dd57678fbd38d66d63a0dcab45e81a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:11 +0300 Subject: arm64: dts: qcom: ipq6018: fix GCC node name Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-13-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 17ab6c475958..a84cf62d843c 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -396,7 +396,7 @@ }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq6018"; reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; -- cgit v1.2.3-58-ga151 From a884986eb2f79b71a4d50fa1b8e205f1f00d9514 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:12 +0300 Subject: arm64: dts: qcom: ipq8074: fix GCC node name Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-14-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d42de829e75..27cf8d50f254 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -363,7 +363,7 @@ }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; clocks = <&xo>, -- cgit v1.2.3-58-ga151 From 7fa676e166d8a70d74441929c88d50bd286fd366 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 4 Mar 2024 18:48:58 -0600 Subject: arm64: dts: imx8mp-beacon-kit: Enable HDMI bridge HPD The DSI to HDMI bridge supports hot-plut-detect, but the driver didn't previously support a shared IRQ GPIO. With the driver updated, the interrupt can be added to the bridge. Signed-off-by: Adam Ford Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index e5d3901f2913..da836172ae46 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -304,6 +304,8 @@ compatible = "adi,adv7535"; reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; reg-names = "main", "cec", "edid", "packet"; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; #sound-dai-cells = <0>; -- cgit v1.2.3-58-ga151 From ba9943f47dca126fb0abd3f735e55ebed5e1eeed Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 11:33:40 +0200 Subject: arm64: dts: mba93xxla: Add USB support This adds support for both USB host and USB Type-C ports. This includes the on-board USB hub. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-tqma9352-mba93xxla.dts | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index eb3f4cfb6986..da8f19a646a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -252,6 +252,32 @@ reg = <0x1c>; }; + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + eeprom2: eeprom@54 { compatible = "nxp,se97b", "atmel,24c02"; reg = <0x54>; @@ -433,6 +459,41 @@ pinctrl-0 = <&pinctrl_tpm5>; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; -- cgit v1.2.3-58-ga151 From ede231f3507219d09330aabf7fba965311be4fe6 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 11:33:41 +0200 Subject: arm64: dts: mba93xxca: Add USB support This adds support for both USB host and USB Type-C ports. This includes the on-board USB hub. Remove the gpio-hog for USB_RESET# as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-tqma9352-mba93xxca.dts | 73 ++++++++++++++++++---- 1 file changed, 61 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index af795ecf678b..852dd3d2eac7 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -303,6 +303,32 @@ reg = <0x1c>; }; + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + eeprom2: eeprom@54 { compatible = "nxp,se97b", "atmel,24c02"; reg = <0x54>; @@ -370,18 +396,6 @@ "WLAN_PD#", "WLAN_W_DISABLE#", "WLAN_PERST#", "12V_EN"; - /* - * Controls the on board USB Hub reset which is low - * active as reset signal. The output-low states, the - * signal is inactive, e.g. no reset - */ - usb-reset-hog { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "USB_RESET#"; - }; - /* * Controls the WiFi card PD pin which is low active * as power down signal. The output-high states, the signal @@ -492,6 +506,41 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; -- cgit v1.2.3-58-ga151 From 0cd7587c6ca012aa237c33c462582f942f6243e8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:46 +0200 Subject: arm64: dts: freescale: tqma9352: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Direct children cause warnings like: 425e0000.spi: ofpart partition /soc@0/bus@42000000/spi@425e0000/flash@0/ partition@600000 (/soc@0/bus@42000000/spi@425e0000/flash@0) #size-cells is wrongly set to <0>, assuming <1> for parsing partitions. This is due flexspi node having #size-cells = <0>. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi index 9d2328c185c9..edbd8cad35bc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi @@ -75,6 +75,12 @@ spi-max-frequency = <62000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 23929910e1383134c19ff0d845cb5ff2321515f3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:47 +0200 Subject: arm64: dts: freescale: tqma8mqml: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 8c0c6e715924..ca0205b9019e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -62,11 +62,15 @@ flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 7de82949255c02cd534e35477cc158e0ffcaa7e5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:48 +0200 Subject: arm64: dts: freescale: tqma8mqnl: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index fb24b9aa1b93..e68a3fd73e17 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -60,11 +60,15 @@ flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 618fc629f20417c30ba244dfc23884fa0bb25e94 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:49 +0200 Subject: arm64: dts: freescale: tqma8mpql: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi index ebc29a950ba9..336785a9fba8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -45,12 +45,16 @@ flash0: flash@0 { reg = <0>; - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 60153af6b517116b9d9a468dace522d09c0537ad Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:50 +0200 Subject: arm64: dts: freescale: tqma8mq: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 5ca6b2252546..01e5092e4c40 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -251,11 +251,15 @@ flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 9536dfd70e05ab7d622f19dcdd9fd35368e2ba2f Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 23 Apr 2024 13:31:51 +0200 Subject: arm64: dts: freescale: tqma8xx: Add partitions subnode to spi-nor The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xx.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi index d98469a7c47c..366912bf3d5e 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi @@ -61,12 +61,16 @@ flash0: flash@0 { reg = <0>; - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; spi-max-frequency = <66000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From 0bfafa074608490e032e7df30243d9b43a4a9a09 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 11:34:41 -0400 Subject: arm64: dts: imx8dxl-ss-adma: delete unused node Delete unused node in adma subsystem. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 5d012c95222f..f5dcdd940592 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -3,6 +3,20 @@ * Copyright 2019~2020, 2022 NXP */ +/delete-node/ &asrc1; +/delete-node/ &asrc1_lpcg; +/delete-node/ &adc1; +/delete-node/ &adc1_lpcg; +/delete-node/ &amix; +/delete-node/ &amix_lpcg; +/delete-node/ &edma1; +/delete-node/ &esai0; +/delete-node/ &esai0_lpcg; +/delete-node/ &sai4; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5; +/delete-node/ &sai5_lpcg; + &audio_ipg_clk { clock-frequency = <160000000>; }; -- cgit v1.2.3-58-ga151 From 3c9622455e253e096c12fc8475eb547a984a8ff4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 11:34:42 -0400 Subject: arm64: dts: imx8dxl-ss-adma: update audio node power domains and IRQ number The power domains of i.MX8DXL's acm is difference i.MX8QXP. IRQ number of sai[0..3] and spdif0 are also difference. Update power domains information for i.MX8DXL. Update sai[0..3] and spdif0's IRQ number for i.MX8DXL. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index f5dcdd940592..72434529f78e 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -17,6 +17,49 @@ /delete-node/ &sai5; /delete-node/ &sai5_lpcg; +&acm { + compatible = "fsl,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk"; +}; + &audio_ipg_clk { clock-frequency = <160000000>; }; @@ -191,3 +234,24 @@ &lpspi3 { interrupts = ; }; + +&sai0 { + interrupts = ; +}; + +&sai1 { + interrupts = ; +}; + +&sai2 { + interrupts = ; +}; + +&sai3 { + interrupts = ; +}; + +&spdif0 { + interrupts = , /* rx */ + ; /* tx */ +}; -- cgit v1.2.3-58-ga151 From b41c45eb990a9e35434c7f26466a9d10f5363d4f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 11:34:43 -0400 Subject: arm64: dts: imx8dxl-evk: add audio nodes Add audio nodes for imx8dxl-evk boards. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 229 ++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 2412ab145c06..4ac96a058629 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -137,6 +137,76 @@ enable-active-high; regulator-always-on; }; + + bt_sco_codec: audio-codec-bt { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-wm8960-1 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960_1>; + audio-asrc = <&asrc0>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-2 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio-2"; + audio-cpu = <&sai2>; + audio-codec = <&wm8960_2>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; + + sound-wm8960-3 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio-3"; + audio-cpu = <&sai3>; + audio-codec = <&wm8960_3>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; }; &adc0 { @@ -144,6 +214,11 @@ status = "okay"; }; +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -271,6 +346,78 @@ }; }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + wm8960_1: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, + <49152000>, + <12288000>, + <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + wm8960_2: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, + <49152000>, + <12288000>, + <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + wm8960_3: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, + <49152000>, + <12288000>, + <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; + }; + i2c@4 { #address-cells = <1>; #size-cells = <0>; @@ -390,6 +537,53 @@ status = "okay"; }; +&sai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai2 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai2_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai3_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + fsl,sai-asynchronous; + status = "okay"; +}; + &thermal_zones { pmic-thermal { polling-delay-passive = <250>; @@ -632,6 +826,41 @@ >; }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 + IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040 + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -- cgit v1.2.3-58-ga151 From 72674309f89600f886a0016d3e11690540c7254a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:37 -0400 Subject: arm64: dts: imx8-ss-audio: remove memory-region = <&dsp_reserved>; Different boards have different DDR memory sizes and layouts for reserved memory. This change reduces future dependencies to add 'imx8qm-ss-audio'. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 897cbb7b6742..ff5df0fed9e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -447,7 +447,6 @@ audio_subsys: bus@59000000 { <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 5ac99cb9ef17e08ee73805ca750932aa17573496 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:38 -0400 Subject: arm64: dts: imx8qm-ss-audio: add audio nodes Add i.MX8QM audio related nodes and update eDMA[0,1]'s information. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 473 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 86 ++++ 2 files changed, 559 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi new file mode 100644 index 000000000000..3036af49fc85 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0 { + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk"; +}; + +&asrc1 { + clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>, + <&asrc1_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk"; +}; + +&audio_subsys { + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59810000 0x10000>; + interrupts = ; + clocks = <&esai1_lpcg IMX_LPCG_CLK_0>, + <&esai1_lpcg IMX_LPCG_CLK_4>, + <&esai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai6_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai6_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai7_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai7_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; + + acm: acm@59e00000 { + compatible = "fsl,imx8qm-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_mlb_clk>, + <&clk_hdmi_rx_mclk>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_esai1_rx_clk>, + <&clk_esai1_rx_hf_clk>, + <&clk_esai1_tx_clk>, + <&clk_esai1_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>, + <&clk_sai5_rx_bclk>, + <&clk_sai6_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "mlb_clk", + "hdmi_rx_mclk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "esai1_rx_clk", + "esai1_rx_hf_clk", + "esai1_tx_clk", + "esai1_tx_hf_clk", + "spdif0_rx", + "spdif1_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk", + "sai5_tx_bclk", + "sai6_rx_bclk"; + }; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x591f0000 0x150000>; + dma-channels = <20>; + dma-channel-mask = <0>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* spdif1 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* sai4 */ + ; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x599f0000 0xc0000>; + dma-channels = <11>; + dma-channel-mask = <0xc0>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* no used */ + , /* no used */ + , /* sai6 */ + , + ; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; +}; + +&esai0 { + clocks = <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&esai0_lpcg { + clock-indices = , ; + clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk"; +}; + +&mqs0_lpcg { + clock-indices = , ; + clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk"; +}; + +&sai0 { + clocks = <&sai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai0_lpcg { + clock-indices = , ; + clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk"; +}; + +&sai1 { + clocks = <&sai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai1_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai1_lpcg { + clock-indices = , ; + clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk"; +}; + +&sai2 { + clocks = <&sai2_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai2_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai2_lpcg { + clock-indices = , ; + clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk"; +}; + +&sai3 { + clocks = <&sai3_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai3_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&sai3_lpcg { + clock-indices = , ; + clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk"; +}; + +&spdif0 { + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&spdif0_lpcg { + clock-indices = , ; + clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index b3d01677b70c..6092d70b10b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -461,7 +461,92 @@ }; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + clk_esai1_rx_clk: clock-esai1-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_rx_clk"; + }; + + clk_esai1_rx_hf_clk: clock-esai1-rx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_rx_hf_clk"; + }; + + clk_esai1_tx_clk: clock-esai1-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_tx_clk"; + }; + + clk_esai1_tx_hf_clk: clock-esai1-tx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_tx_hf_clk"; + }; + + clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "hdmi-rx-mclk"; + }; + + clk_mlb_clk: clock-mlb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mlb_clk"; + }; + + clk_sai5_rx_bclk: clock-sai5-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai5_rx_bclk"; + }; + + clk_sai5_tx_bclk: clock-sai5-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai5_tx_bclk"; + }; + + clk_sai6_rx_bclk: clock-sai6-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai6_rx_bclk"; + }; + + clk_sai6_tx_bclk: clock-sai6-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai6_tx_bclk"; + }; + + clk_spdif1_rx: clock-spdif1-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "spdif1_rx"; + }; + /* sorted in register address */ + #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" @@ -473,3 +558,4 @@ #include "imx8qm-ss-dma.dtsi" #include "imx8qm-ss-conn.dtsi" #include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-audio.dtsi" -- cgit v1.2.3-58-ga151 From d032d7fcc4f55c6b57daffde204d5e431ceaa5f7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:39 -0400 Subject: arm64: dts: imx8qm-mek: add sai and wm8960 support Add sai[0,1,6,7], wm8960 and asrc0 support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 139 +++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 5c6b39c6933f..6bdda248179f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -46,6 +46,46 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + bt_sco_codec: audio-codec-bt { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; }; &adc0 { @@ -55,6 +95,15 @@ status = "okay"; }; +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +114,21 @@ scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; status = "okay"; + + wm8960: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; }; &lpuart0 { @@ -160,7 +224,64 @@ status = "okay"; }; +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_4>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c @@ -256,6 +377,24 @@ >; }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -- cgit v1.2.3-58-ga151 From e3f79bdb53257977f97208413911df7113291179 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:40 -0400 Subject: arm64: dts: imx8x: add cm41 subsystem dtsi Add cm41 subsystem dtsi for iMX8X chips. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi | 68 +++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + 2 files changed, 69 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi new file mode 100644 index 000000000000..d715f2a6b037 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng + */ + +#include +#include + +cm41_ipg_clk: clock-cm41-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm41_ipg_clk"; +}; + +cm41_subsys: bus@38000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38000000 0x0 0x38000000 0x4000000>; + interrupt-parent = <&cm41_intmux>; + + cm41_i2c: i2c@3b230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x3b230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>, + <&cm41_i2c_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + status = "disabled"; + }; + + cm41_intmux: intmux@3b400000 { + compatible = "fsl,imx-intmux"; + reg = <0x3b400000 0x1000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cm41_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; + status = "disabled"; + }; + + cm41_i2c_lpcg: clock-controller@3b630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x3b630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, + <&cm41_ipg_clk>; + clock-indices = , ; + clock-output-names = "cm41_lpcg_i2c_clk", + "cm41_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 6092d70b10b9..8e94ffe1acb5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -546,6 +546,7 @@ }; /* sorted in register address */ + #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-img.dtsi" -- cgit v1.2.3-58-ga151 From 9918092cbb0e0cc33de6a85f43173f456612d391 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:41 -0400 Subject: arm64: dts: imx8qm-mek: add i2c0 and children devices Add i2c0 and all devices under it for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 6bdda248179f..dd9dd3cb7d47 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -104,6 +104,49 @@ status = "okay"; }; +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lsm303agr-accel"; + reg = <0x19>; + }; + + gyrometer@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + gyrometer@69 { + compatible = "st,l3g4200d-gyro"; + reg = <0x69>; + }; +}; + &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -282,6 +325,13 @@ >; }; + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c -- cgit v1.2.3-58-ga151 From 082784d652e4287a45e3eff003eabb0b00720395 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:42 -0400 Subject: arm64: dts: imx8qm-mek: add cm41_i2c and children devices Add cm41_i2c and devices under it for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index dd9dd3cb7d47..c5cb461c30c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -104,6 +104,26 @@ status = "okay"; }; +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm41_intmux { + status = "okay"; +}; + &i2c0 { #address-cells = <1>; #size-cells = <0>; @@ -352,6 +372,13 @@ >; }; + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -- cgit v1.2.3-58-ga151 From eb57eb2357b92bd4a1e3baa1395cc0bd9b2519fc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:43 -0400 Subject: arm64: dts: imx8qm-mek: add flexcan support Add flexcan[1,2,3] support for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 80 ++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index c5cb461c30c9..cb5cfd04b169 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -40,6 +40,44 @@ enable-active-high; }; + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; @@ -194,6 +232,27 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -433,6 +492,27 @@ >; }; + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 -- cgit v1.2.3-58-ga151 From bb96cd010673d923571385169a7a2bcdf9372a17 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:44 -0400 Subject: arm64: dts: imx8qm-mek: add lsio mu5 and mu6 Add lsio mu5 and mu6. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index cb5cfd04b169..3e57c760e40a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -286,6 +286,14 @@ }; }; +&lsio_mu5 { + status = "okay"; +}; + +&lsio_mu6 { + status = "okay"; +}; + &flexspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; -- cgit v1.2.3-58-ga151 From 6e7e34a2466486a5b6dd5caa2da55d5c25878be5 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:45 -0400 Subject: arm64: dts: imx8qm: add ocopt and fec_mac[0,1] add ocotp ad fec_mac[0,1] for imx8qm. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 8e94ffe1acb5..46a8046e9f50 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -333,6 +333,21 @@ compatible = "fsl,imx8qxp-sc-rtc"; }; + ocotp: ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + tsens: thermal-sensor { compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; #thermal-sensor-cells = <1>; -- cgit v1.2.3-58-ga151 From 0468df461ca787338051e8963cc196ba6858cde7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Apr 2024 16:24:46 -0400 Subject: arm64: dts: imx8qm-mek: add fec2 support Add fec2 support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 3e57c760e40a..c024be33fbcc 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -40,6 +40,15 @@ enable-active-high; }; + reg_fec2_supply: regulator-fec2-nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_can01_en: regulator-can01-gen { compatible = "regulator-fixed"; regulator-name = "can01-en"; @@ -334,6 +343,19 @@ }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + fsl,magic-packet; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -500,6 +522,24 @@ >; }; + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + pinctrl_flexcan1: flexcan0grp { fsl,pins = < IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 -- cgit v1.2.3-58-ga151 From 9f3d2c79d34bc729c7ae36be7dc9851fc8d891db Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Fri, 3 May 2024 23:22:48 +0200 Subject: arm64: dts: imx8qm: Add GPU nodes Add the DT node for the GPU core found on the i.MX8QM. etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6009 [drm] Initialized etnaviv 1.4.0 20151214 for etnaviv on minor 0 Signed-off-by: Christian Gmeiner Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 46a8046e9f50..61986e0639e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -564,6 +564,7 @@ #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" -- cgit v1.2.3-58-ga151 From 41f93a496af2696d970cbcb3814261a9b32dbaa2 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 8 May 2024 18:00:13 +0800 Subject: arm64: dts: imx8mp-evk: Add MX8-DLVDS-LCD1 display module support MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel and a touch IC. Add an overlay to support the LCD panel on i.MX8MP EVK. Specify 148.5MHz clock frequency in panel-timing node to accommodate 3.5-fold 519.75MHz media_ldb clock which is derived from 1.0395GHz video_pll1 clock. Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso | 77 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 19 ++++++ 3 files changed, 99 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bd443c2bc5a4..1b1e4db02071 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -191,6 +191,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb +imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb + imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso new file mode 100644 index 000000000000..1b71890d43d5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; +/plugin/; + +&{/} { + panel-lvds { + compatible = "koe,tx26d202vm0bwa"; + backlight = <&backlight_lvds>; + power-supply = <®_vext_3v3>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <130>; + hback-porch = <70>; + hsync-len = <30>; + vfront-porch = <5>; + vback-porch = <5>; + vsync-len = <5>; + de-active = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_odd: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_even: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + }; +}; + +&backlight_lvds { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_odd>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel_in_even>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 8be5b2a57f27..4a23c5373052 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -16,6 +16,16 @@ stdout-path = &uart2; }; + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + power-supply = <®_per_12v>; + status = "disabled"; + }; + hdmi-connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -96,6 +106,15 @@ enable-active-high; }; + reg_per_12v: regulator-per-12v { + compatible = "regulator-fixed"; + regulator-name = "PER_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; -- cgit v1.2.3-58-ga151 From a509981a2e985ac2b97c447546e463c3f96ac1c5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Apr 2024 22:30:04 +0100 Subject: arm64: dts: renesas: r9a09g011: Update fallback string for SDHI nodes Use 'renesas,rzg2l-sdhi' as a fallback string for SDHI nodes, where hs400_disabled and fixed_addr_mode quirks are applied. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240422213006.505576-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 50ed66d42a24..e008236c3d2d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -71,7 +71,7 @@ sdhi0: mmc@85000000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85000000 0 0x2000>; interrupts = , ; @@ -87,7 +87,7 @@ sdhi1: mmc@85010000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85010000 0 0x2000>; interrupts = , ; @@ -103,7 +103,7 @@ emmc: mmc@85020000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85020000 0 0x2000>; interrupts = , ; -- cgit v1.2.3-58-ga151 From 046084b5e1426efbf08913830bdb101dcbb06be5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Apr 2024 22:30:05 +0100 Subject: arm64: dts: renesas: rzg2l: Update fallback string for SDHI nodes Use 'renesas,rzg2l-sdhi' as a fallback string for SDHI nodes, where hs400_disabled and fixed_addr_mode quirks are applied. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240422213006.505576-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 6212ee550f33..2eccab9c8962 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -646,7 +646,7 @@ sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; interrupts = , ; @@ -662,7 +662,7 @@ sdhi1: mmc@11c10000 { compatible = "renesas,sdhi-r9a07g043", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; interrupts = , ; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 88634ae43287..c07ddd8124e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1050,7 +1050,7 @@ sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g044", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; interrupts = , ; @@ -1066,7 +1066,7 @@ sdhi1: mmc@11c10000 { compatible = "renesas,sdhi-r9a07g044", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; interrupts = , ; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e89bfe4085f5..8448afa8be54 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1058,7 +1058,7 @@ sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g054", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; interrupts = , ; @@ -1074,7 +1074,7 @@ sdhi1: mmc@11c10000 { compatible = "renesas,sdhi-r9a07g054", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; interrupts = , ; -- cgit v1.2.3-58-ga151 From f6e32aa9693e7f0748087e49484d97808f1bbc98 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Apr 2024 22:30:06 +0100 Subject: arm64: dts: renesas: r9a08g045: Update fallback string for SDHI nodes Use 'renesas,rzg2l-sdhi' as a fallback string for SDHI nodes, where hs400_disabled and fixed_addr_mode quirks are applied. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240422213006.505576-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..2162c247d6de 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -182,7 +182,7 @@ }; sdhi0: mmc@11c00000 { - compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; interrupts = , ; @@ -197,7 +197,7 @@ }; sdhi1: mmc@11c10000 { - compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; interrupts = , ; @@ -212,7 +212,7 @@ }; sdhi2: mmc@11c20000 { - compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; reg = <0x0 0x11c20000 0 0x10000>; interrupts = , ; -- cgit v1.2.3-58-ga151 From bba474656dd85b13e4c5d5bdb73ca08d9136df21 Mon Sep 17 00:00:00 2001 From: Pavel Löbl Date: Wed, 20 Mar 2024 07:10:19 +0100 Subject: ARM: dts: sunxi: remove duplicated entries in makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During introduction of DTS vendor subdirectories in 724ba6751532, sun8i section of the makefile got duplicated. Clean that up. Fixes: 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") Signed-off-by: Pavel Löbl Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240320061027.4078852-1-pavel@loebl.cz Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 62 ------------------------------------ 1 file changed, 62 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 4247f19b1adc..cd0d044882cf 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -261,68 +261,6 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a23-evb.dtb \ - sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-inet86dz.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ - sun8i-a23-polaroid-mid2407pxe03.dtb \ - sun8i-a23-polaroid-mid2809pxe04.dtb \ - sun8i-a23-q8-tablet.dtb \ - sun8i-a33-et-q8-v1.6.dtb \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-inet-d978-rev2.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-bananapi-m2-plus-v1.2.dtb \ - sun8i-h3-beelink-x2.dtb \ - sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-mapleboard-mp130.dtb \ - sun8i-h3-nanopi-duo2.dtb \ - sun8i-h3-nanopi-m1.dtb\ - \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ - sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ - sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-zeropi.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ - sun8i-r16-parrot.dtb \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-r40-oka40i-c.dtb \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-lichee-zero-plus.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-t113s-mangopi-mq-r-t113.dtb \ - sun8i-t3-cqa3t-bv3.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb \ - sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb -- cgit v1.2.3-58-ga151 From fbce12d2899c4f19632d85df06c6d9377a565534 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 3 May 2024 11:34:22 -0400 Subject: arm64: zynqmp: Add coresight cpu debug support Add coresight debug support to the device tree. This can be useful when panicking, especially when a core is hung in EL3. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20240503153422.1958812-1-sean.anderson@linux.dev Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 16 +++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 28 ++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index dd4569e7bd95..60d1b1acf9a0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -70,6 +70,22 @@ clocks = <&zynqmp_clk ACPU>; }; +&cpu0_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu1_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu2_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu3_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 0b730f6eeef1..95796d6b5515 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -387,6 +387,34 @@ }; }; + cpu0_debug: debug@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfec10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu1_debug: debug@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu2_debug: debug@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfee10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu3_debug: debug@fef10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfef10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; -- cgit v1.2.3-58-ga151 From fe7c551ea03e0df729966e33c58f9955f7408208 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 4 Jun 2024 13:49:48 +0200 Subject: arm64: dts: microchip: sparx5_pcb134: move non-MMIO nodes out of axi simple-bus nodes, so the "axi" node, should not have non-MMIO children as pointed out by simple-bus schema dtbs_check: sparx5_pcb134.dtb: axi@600000000: i2c-mux-0: {'compatible': ... should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 372 +++++++++++---------- 1 file changed, 194 insertions(+), 178 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 2c5574734c9e..e60acc74e822 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -13,6 +13,20 @@ priority = <200>; }; + i2c0_imux: i2c-mux-0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + + i2c0_emux: i2c-mux-1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + leds { compatible = "gpio-leds"; led-0 { @@ -248,6 +262,186 @@ default-state = "off"; }; }; + + sfp_eth12: sfp-eth12 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth13: sfp-eth13 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth14: sfp-eth14 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth15: sfp-eth15 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth48: sfp-eth48 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp5>; + tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth49: sfp-eth49 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp6>; + tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth50: sfp-eth50 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp7>; + tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth51: sfp-eth51 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp8>; + tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth52: sfp-eth52 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp9>; + tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth53: sfp-eth53 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp10>; + tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth54: sfp-eth54 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp11>; + tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth55: sfp-eth55 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp12>; + tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth56: sfp-eth56 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp13>; + tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth57: sfp-eth57 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp14>; + tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth58: sfp-eth58 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp15>; + tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth59: sfp-eth59 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp16>; + tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth60: sfp-eth60 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp17>; + tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth61: sfp-eth61 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp18>; + tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth62: sfp-eth62 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp19>; + tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth63: sfp-eth63 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp20>; + tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + }; }; &sgpio0 { @@ -385,21 +579,6 @@ }; }; -&axi { - i2c0_imux: i2c-mux-0 { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; - i2c0_emux: i2c-mux-1 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; -}; - &i2c0_imux { pinctrl-names = "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", @@ -535,169 +714,6 @@ }; }; -&axi { - sfp_eth12: sfp-eth12 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth13: sfp-eth13 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth14: sfp-eth14 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp3>; - tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth15: sfp-eth15 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp4>; - tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth48: sfp-eth48 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp5>; - tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth49: sfp-eth49 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp6>; - tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth50: sfp-eth50 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp7>; - tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth51: sfp-eth51 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp8>; - tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth52: sfp-eth52 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp9>; - tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth53: sfp-eth53 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp10>; - tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth54: sfp-eth54 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp11>; - tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth55: sfp-eth55 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp12>; - tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth56: sfp-eth56 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp13>; - tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth57: sfp-eth57 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp14>; - tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth58: sfp-eth58 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp15>; - tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth59: sfp-eth59 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp16>; - tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth60: sfp-eth60 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp17>; - tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth61: sfp-eth61 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp18>; - tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth62: sfp-eth62 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp19>; - tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; - }; - sfp_eth63: sfp-eth63 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp20>; - tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; - }; -}; - &switch { ethernet-ports { #address-cells = <1>; -- cgit v1.2.3-58-ga151 From 3a94fa4cb86e96103657ba3550ee68b424269613 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 4 Jun 2024 13:49:49 +0200 Subject: arm64: dts: microchip: sparx5_pcb135: move non-MMIO nodes out of axi simple-bus nodes, so the "axi" node, should not have non-MMIO children as pointed out by simple-bus schema dtbs_check: sparx5_pcb135_emmc.dtb: axi@600000000: sfp-eth60: {'compatible': ... should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 95 +++++++++++----------- 1 file changed, 47 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index af2f1831f07f..196868898f49 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -13,6 +13,13 @@ priority = <200>; }; + i2c0_imux: i2c-mux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + leds { compatible = "gpio-leds"; led-0 { @@ -56,6 +63,46 @@ default-state = "off"; }; }; + + sfp_eth60: sfp-eth60 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth61: sfp-eth61 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth62: sfp-eth62 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth63: sfp-eth63 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; + }; }; &gpio { @@ -119,15 +166,6 @@ microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; }; -&axi { - i2c0_imux: i2c-mux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; -}; - &i2c0_imux { pinctrl-names = "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", @@ -159,45 +197,6 @@ }; }; -&axi { - sfp_eth60: sfp-eth60 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth61: sfp-eth61 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth62: sfp-eth62 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp3>; - tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth63: sfp-eth63 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp4>; - tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; - }; -}; - &mdio0 { status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3-58-ga151 From d904c09b73fe9b0503e94f1c013d962e87a08123 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:23:55 +0200 Subject: ARM: dts: qcom: msm8974: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-2-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 944098b5ad2b..1bea3cef4ba7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -132,7 +132,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -219,7 +219,7 @@ interrupt-parent = <&intc>; interrupts = ; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -244,7 +244,7 @@ interrupt-parent = <&intc>; interrupts = ; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -269,7 +269,7 @@ interrupt-parent = <&intc>; interrupts = ; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -759,7 +759,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; wcnss { @@ -1578,7 +1578,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,smd-edge = <0>; label = "modem"; @@ -2215,7 +2215,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 8>; + mboxes = <&apcs 8>; qcom,smd-edge = <1>; label = "lpass"; }; -- cgit v1.2.3-58-ga151 From 3e971470619d80dd343e3abd80cb997bcb48f200 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:23:56 +0200 Subject: arm64: dts: qcom: msm8916: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-3-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index cedff4166bfb..46bb322ae133 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -308,7 +308,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -360,7 +360,7 @@ interrupts = ; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -385,7 +385,7 @@ interrupts = ; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -1978,7 +1978,7 @@ interrupts = ; qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,remote-pid = <1>; label = "hexagon"; @@ -2459,7 +2459,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; -- cgit v1.2.3-58-ga151 From 22e4e43484c4dd1f29a72cc62411072758e0681a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:23:57 +0200 Subject: arm64: dts: qcom: msm8939: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-4-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index dd45975682b2..95487de2ca6a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -248,7 +248,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs1_mbox 8 0>; + mboxes = <&apcs1_mbox 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -2067,7 +2067,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs1_mbox 8 17>; + mboxes = <&apcs1_mbox 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; -- cgit v1.2.3-58-ga151 From 11dff973ebe21950c7c5221919141fb0cb16354e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:23:58 +0200 Subject: arm64: dts: qcom: msm8953: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-5-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5d818fe057dd..c322d630dd09 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -195,7 +195,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -361,7 +361,7 @@ interrupts = ; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -386,7 +386,7 @@ interrupts = ; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -1267,7 +1267,7 @@ interrupts = ; qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,remote-pid = <1>; label = "modem"; @@ -1748,7 +1748,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; -- cgit v1.2.3-58-ga151 From a3d5570d8c8c6efc3d15d015b517f4e8bd11898f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:23:59 +0200 Subject: arm64: dts: qcom: msm8976: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-6-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 861c24cc2556..9b0f6d1f08be 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -243,7 +243,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -367,7 +367,7 @@ smp2p-hexagon { compatible = "qcom,smp2p"; interrupts = ; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -390,7 +390,7 @@ smp2p-modem { compatible = "qcom,smp2p"; interrupts = ; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -413,7 +413,7 @@ smp2p-wcnss { compatible = "qcom,smp2p"; interrupts = ; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; -- cgit v1.2.3-58-ga151 From ba5d9a91f8c3caf6867b3b87dce080d056222561 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 24 Apr 2024 18:24:00 +0200 Subject: arm64: dts: qcom: msm8994: Use mboxes properties for APCS Instead of passing the syscon to the various nodes, use the mbox interface using the mboxes property. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240424-apcs-mboxes-v1-7-6556c47cb501@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 695e541832ad..9949d2cd23d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -183,7 +183,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; qcom,remote-pid = <6>; @@ -300,7 +300,7 @@ interrupts = ; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -325,7 +325,7 @@ interrupt-parent = <&intc>; interrupts = ; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; -- cgit v1.2.3-58-ga151 From 4fbf92d51cbc8c5d2d4ea1fcfad4cd8365047f4d Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Tue, 21 May 2024 10:01:31 +0200 Subject: arm64: dts: st: OP-TEE async notif on PPI 15 for stm32mp25 Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous notification. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +++- arch/arm64/boot/dts/st/stm32mp253.dtsi | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index dcd0656d67a8..22a5379ea1c9 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -51,9 +51,11 @@ }; firmware { - optee { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; + interrupt-parent = <&intc>; + interrupts = ; }; scmi { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 029f88981961..69001f924d17 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -28,3 +28,7 @@ ; }; }; + +&optee { + interrupts = ; +}; -- cgit v1.2.3-58-ga151 From 6e043ff6350267bb39de01499a8ad0035c729393 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 29 May 2024 15:13:10 +0200 Subject: arm64: dts: st: enable STM32 access controller for RCC Use an STM32 access controller to filter the registration of clocks. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 22a5379ea1c9..7454e615350c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -443,6 +443,7 @@ <&scmi_clk CK_SCMI_TIMG2>, <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; }; exti1: interrupt-controller@44220000 { -- cgit v1.2.3-58-ga151 From c3aa0dccf0ccbdd2c2ad556382bbae95344e4992 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:22 +0200 Subject: arm64: dts: st: add usart nodes on stm32mp25 Update device-tree stm32mp251.dtsi to add some USART features. Add u(s)art 1, 3, 4, 5, 6, 7, 8, 9 nodes and compatible, interrupts, clocks, access-controllers properties. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 72 ++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 7454e615350c..2013f391f4b9 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -150,6 +150,33 @@ status = "disabled"; }; + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART3>; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART4>; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART5>; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + i2c1: i2c@40120000 { compatible = "st,stm32mp25-i2c"; reg = <0x40120000 0x400>; @@ -241,6 +268,15 @@ status = "disabled"; }; + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART6>; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + spi1: spi@40230000 { #address-cells = <1>; #size-cells = <0>; @@ -277,6 +313,24 @@ status = "disabled"; }; + uart9: serial@402c0000 { + compatible = "st,stm32h7-uart"; + reg = <0x402c0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART9>; + access-controllers = <&rifsc 39>; + status = "disabled"; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART1>; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + spi6: spi@40350000 { #address-cells = <1>; #size-cells = <0>; @@ -301,6 +355,24 @@ status = "disabled"; }; + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART7>; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + uart8: serial@40380000 { + compatible = "st,stm32h7-uart"; + reg = <0x40380000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART8>; + access-controllers = <&rifsc 38>; + status = "disabled"; + }; + spi8: spi@46020000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-58-ga151 From 066cfdcd75a6844c6a09751637261c9f1d5baad7 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:23 +0200 Subject: arm64: dts: st: add usart6 pinctrl used on stm32mp257f-ev1 board Add pins for USART6 on GPIO connector on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 7a82896dcbf6..4e677e64c406 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -128,6 +128,47 @@ ; /* USART2_RX */ }; }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART6_RX */ + ; /* USART6_CTS_NSS */ + bias-pull-up; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = , /* USART6_TX */ + , /* USART6_RTS */ + , /* USART6_CTS_NSS */ + ; /* USART6_RX */ + }; + }; }; &pinctrl_z { -- cgit v1.2.3-58-ga151 From 624aa659afbc902cd279ae719a2f58a22dca88c0 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:24 +0200 Subject: arm64: dts: st: add usart6 on stm32mp257f-ev1 board Add node for USART6 on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 27b7360e5dba..18c6266532b2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -18,6 +18,7 @@ aliases { serial0 = &usart2; + serial1 = &usart6; }; chosen { @@ -109,3 +110,12 @@ pinctrl-2 = <&usart2_sleep_pins_a>; status = "okay"; }; + +&usart6 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_idle_pins_a>; + pinctrl-2 = <&usart6_sleep_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; -- cgit v1.2.3-58-ga151 From 9c8d852dabbd49f4894d5d998ede8b98eb091921 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 25 Apr 2024 17:45:55 +0200 Subject: arm64: dts: st: add power domain on stm32mp25 Add power domains on STM32MP25x SoC for supported low power modes: - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when the Cortex A35 cluster and each device assigned to CPU1=CA35 are deactivated - RET_PD: D1 domain retention (VDDCore is reduced) to support the LPLV-Stop1 mode Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 9 +++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 2013f391f4b9..96d6de29c14c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -20,6 +20,8 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; }; @@ -90,6 +92,20 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&RET_PD>; + }; + + RET_PD: power-domain-retention { + #power-domain-cells = <0>; + }; }; timer { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 69001f924d17..652e41facb35 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -12,6 +12,8 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; }; @@ -21,6 +23,13 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + psci { + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + }; + timer { interrupts = , , -- cgit v1.2.3-58-ga151 From 0948424cd5e77c1f16ec64837dc1d51f71db7dd5 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 26 Apr 2024 17:05:24 +0200 Subject: ARM: dts: stm32: add DCMIPP pinctrl on STM32MP13x SoC family Adds DCMIPP pinctrl support and assigns dedicated GPIO pins. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 32c5d8a1e06a..b423d182aefd 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,39 @@ }; }; + dcmipp_pins_a: dcmi-0 { + pins1 { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmipp_sleep_pins_a: dcmi-sleep-0 { + pins1 { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ -- cgit v1.2.3-58-ga151 From 26c7b370eba6127431c82d1cbf5081f6b5674db6 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 26 Apr 2024 17:05:25 +0200 Subject: ARM: dts: stm32: enable camera support on stm32mp135f-dk board On STM32MP135F-DK board the camera support is made of the CSI based GC2145 sensor, connected to the ST-MIPID02 CSI to parallel bridge, connected to the DCMIPP parallel input. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 87 +++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 567e53ad285f..e43bb9b74b87 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -29,6 +29,20 @@ stdout-path = "serial0:115200n8"; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_mco1: clk-mco1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -141,6 +155,23 @@ status = "okay"; }; +&dcmipp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmipp_pins_a>; + pinctrl-1 = <&dcmipp_sleep_pins_a>; + status = "okay"; + + port { + dcmipp_0: endpoint { + remote-endpoint = <&mipid02_2>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -201,6 +232,62 @@ /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; + + stmipi: csi2rx@14 { + compatible = "st,st-mipid02"; + reg = <0x14>; + clocks = <&clk_mco1>; + clock-names = "xclk"; + VDDE-supply = <&scmi_v1v8_periph>; + VDDIN-supply = <&scmi_v1v8_periph>; + reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + mipid02_0: endpoint { + data-lanes = <1 2>; + lane-polarities = <0 0 0>; + remote-endpoint = <&gc2145_ep>; + }; + }; + port@2 { + reg = <2>; + + mipid02_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmipp_0>; + }; + }; + }; + }; + + gc2145: camera@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + iovdd-supply = <&scmi_v3v3_sw>; + avdd-supply = <&scmi_v3v3_sw>; + dvdd-supply = <&scmi_v3v3_sw>; + powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + port { + gc2145_ep: endpoint { + remote-endpoint = <&mipid02_0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <120000000 192000000 240000000>; + }; + }; + }; }; &iwdg2 { -- cgit v1.2.3-58-ga151 From 3d058df954ebdb592fd421e0005f6d0c25da21ed Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Mon, 6 May 2024 16:49:45 +0200 Subject: ARM: dts: stm32: add goodix touchscreen on stm32mp135f-dk Touchscreen reset needs to be configured via the pinctrl not the driver (a pull-down resistor has been soldered onto the reset line which forces the touchscreen to reset state). Interrupt line must have a pull-down resistor in order to freeze the i2c address at 0x5D. Signed-off-by: Yannick Fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index b423d182aefd..66efef93251f 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -46,6 +46,28 @@ }; }; + goodix_pins_a: goodix-0 { + /* + * touchscreen reset needs to be configured + * via the pinctrl not the driver (a pull-down resistor + * has been soldered onto the reset line which forces + * the touchscreen to reset state). + */ + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + /* + * Interrupt line must have a pull-down resistor + * in order to freeze the i2c address at 0x5D + */ + pins2 { + pinmux = ; + bias-pull-down; + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index e43bb9b74b87..970de441fbaa 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -288,6 +288,20 @@ }; }; }; + + goodix: goodix-ts@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins_a>; + interrupt-parent = <&gpiof>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + AVDD28-supply = <&scmi_v3v3_sw>; + VDDIO-supply = <&scmi_v3v3_sw>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + status = "okay" ; + }; }; &iwdg2 { -- cgit v1.2.3-58-ga151 From 4306c047415a227bc72f0e7ba9bde1ccdac10435 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 May 2024 23:58:15 +0200 Subject: ARM: dts: stm32: Add arm,no-tick-in-suspend to STM32MP15xx STGEN timer STM32MP15xx RM0436 Rev 6 section 46.3 System timer generator (STGEN) states " Arm recommends that the system counter is in an always-on power domain. This is not supported in the current implementation, therefore STGEN should be saved and restored before Standby mode entry, and restored at Standby exit by secure software. ... " Instead of piling up workarounds in the firmware which is difficult to update, add "arm,no-tick-in-suspend" DT property into the timer node to indicate the timer is stopped in suspend, and let the kernel fix the timer up. Fixes: 8471a20253eb ("ARM: dts: stm32: add stm32mp157c initial support") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 90c5c72c87ab..4f878ec102c1 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -50,6 +50,7 @@ , ; interrupt-parent = <&intc>; + arm,no-tick-in-suspend; }; clocks { -- cgit v1.2.3-58-ga151 From 7010a17fb12a0febd6002d5bae8c4bf14039ae8c Mon Sep 17 00:00:00 2001 From: Sean Nyekjaer Date: Wed, 22 May 2024 10:23:29 +0200 Subject: ARM: dts: stm32: osd32: move usb phy power to common According to the OSD32MP1 Power System overview[1] usb phy power is hard-wired internally in the SIP module to ldo4. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Sean Nyekjaer Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 8 -------- arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 8 -------- arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi | 8 ++++++++ 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 527c33be66cc..854dfecd801f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -211,11 +211,3 @@ &usbphyc { status = "okay"; }; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index cfaf8adde319..aa28043c30fb 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -590,14 +590,6 @@ baseboard_eeprom: &sip_eeprom { status = "okay"; }; -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; - &vrefbuf { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index aeb71c41a734..ae01e7a5339e 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -214,3 +214,11 @@ &rng1 { status = "okay"; }; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; -- cgit v1.2.3-58-ga151 From f37c8d3ba5262dc4aee83c58958817c8360f1455 Mon Sep 17 00:00:00 2001 From: Sean Nyekjaer Date: Wed, 22 May 2024 10:23:30 +0200 Subject: ARM: dts: stm32: osd32: move pwr_regulators to common According to the OSD32MP1 Power System overview[1] pwr_regulators; vdd-supply and vdd_3v3_usbfs-supply are hard-wired internally in the SIP module to vdd and ldo4. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Sean Nyekjaer Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 5 ----- arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 5 ----- arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi | 5 +++++ 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 854dfecd801f..36e6055b5665 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -147,11 +147,6 @@ status = "okay"; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index aa28043c30fb..c87fd96cbd91 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -379,11 +379,6 @@ baseboard_eeprom: &sip_eeprom { }; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index ae01e7a5339e..2022a1fa31ca 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -215,6 +215,11 @@ status = "okay"; }; +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; }; -- cgit v1.2.3-58-ga151 From f97e8c040e2c1130a8cc91861590510d5d40a878 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:10 +0200 Subject: dt-bindings: arm: stm32: Add compatible string for DH electronics STM32MP13xx DHCOR DHSBC board Add DT compatible string for DH electronics STM32MP13xx DHCOR SoM and DHSBC carrier board. This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC carrier board. The SoM contains the following peripherals: - STPMIC (power delivery) - 512MB DDR3L memory - eMMC and SDIO WiFi module The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - USB-A Host port, USB-C peripheral port, USB-C power supply plug - Expansion connector Signed-off-by: Marek Vasut Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bc2f43330ae4..58099949e8f3 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,6 +59,12 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 + - description: DH STM32MP135 DHCOR SoM based Boards + items: + - const: dh,stm32mp135f-dhcor-dhsbc + - const: dh,stm32mp135f-dhcor-som + - const: st,stm32mp135 + - description: DH STM32MP151 DHCOR SoM based Boards items: - const: dh,stm32mp151a-dhcor-testbench -- cgit v1.2.3-58-ga151 From e502de5d40f70eb3f2066d0231df0f40ff48742c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 17:46:05 +0200 Subject: arm64: dts: qcom: use defines for interrupts Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605154605.149051-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 ++++---- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 9949d2cd23d8..917fa246857d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -1093,10 +1093,10 @@ timer: timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; vph_pwr: vph-pwr-regulator { diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d591c83e4bac..26a0940d42ec 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1531,10 +1531,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; smp2p-adsp { diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f5921b80ef94..f202c1f3c89c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2601,10 +2601,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 98ab08356088..777c380c2fa0 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1588,10 +1588,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = ; + interrupts = , + , + , + ; clock-frequency = <19200000>; }; }; -- cgit v1.2.3-58-ga151 From 3c61c786d2f058636a92c5b648873fdd45444085 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 5 Jun 2024 13:43:30 +0200 Subject: arm64: dts: qcom: sm8650-hdk: allow more IOMMU SID for the first QUP instance When triggering I2S SE DMA transfers on the 6th Serial Element, we get some timeouts and finally a fatal SMMU crash because the I2C6 lines are shared with the secure firmware in order to handle the SMB1396 charger from the secure side. In order to make thing work flawlessly we need to allow more SIDs while running our SE DMA transfers, thus add the 0x3 mark to allow the 0xa0 SID to trigger while we trigger an 0xa3 SID from Linux. This crash doesn't happen on the QRD platform since the SE6 is configured differently, with FIFO mode disabled, thus GPI DMA is used and we cannot exercise SE DMA on this interface. The crash only happens when large tranfers occurs (>32 bytes) since the driver is designed to use the SE DMA in this case, and there's no way to mark the SE DMA as disabled or mark the GPI DMA as preferred since the FIFO/SE DMA will be used is FIFO is not disabled. Signed-off-by: Neil Armstrong Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605-topic-sm8650-upstream-hdk-iommu-fix-v1-1-9fd7233725fa@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 182864a3b6bd..5887d265a077 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -991,6 +991,8 @@ }; &qupv3_id_0 { + iommus = <&apps_smmu 0xa3 0x3>; + status = "okay"; }; -- cgit v1.2.3-58-ga151 From b7b545ccc08873e107aa24c461b1fdb123dd3761 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 5 Jun 2024 11:55:56 +0300 Subject: arm64: dts: qcom: qrb2210-rb1: switch I2C2 to i2c-gpio On the Qualcomm RB1 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: 616eda24edd4 ("arm64: dts: qcom: qrb2210-rb1: Set up HDMI") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov Reviewed-by: Caleb Connolly Link: https://lore.kernel.org/r/20240605-rb12-i2c2g-pio-v2-1-946f5d6b6948@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index bb5191422660..8c27d52139a1 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -59,6 +59,17 @@ }; }; + i2c2_gpio: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + leds { compatible = "gpio-leds"; @@ -199,7 +210,7 @@ status = "okay"; }; -&i2c2 { +&i2c2_gpio { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3-58-ga151 From f77e7bd40c3c2d79685e9cc80de874b69a976f55 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 5 Jun 2024 11:55:57 +0300 Subject: arm64: dts: qcom: qrb4210-rb2: switch I2C2 to i2c-gpio On the Qualcomm RB2 platform the I2C bus connected to the LT9611UXC bridge under some circumstances can go into a state when all transfers timeout. This causes both issues with fetching of EDID and with updating of the bridge's firmware. While we are debugging the issue, switch corresponding I2C bus to use i2c-gpio driver. While using i2c-gpio no communication issues are observed. This patch is asusmed to be a temporary fix, so it is implemented in a non-intrusive manner to simply reverting it later. Fixes: f7b01e07e89c ("arm64: dts: qcom: qrb4210-rb2: Enable display out") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov Reviewed-by: Caleb Connolly Link: https://lore.kernel.org/r/20240605-rb12-i2c2g-pio-v2-2-946f5d6b6948@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 2c39bb1b97db..cb8a62714a30 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -60,6 +60,17 @@ }; }; + i2c2_gpio: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + leds { compatible = "gpio-leds"; @@ -190,7 +201,7 @@ }; }; -&i2c2 { +&i2c2_gpio { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3-58-ga151 From d6c6b85bf5582bbe2efefa9a083178b5f7eef439 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 5 Jun 2024 12:00:49 +0300 Subject: arm64: dts: qcom: qrb4210-rb2: make L9A always-on The L9A regulator is used to further control voltage regulators on the board. It can be used to disable VBAT_mains, 1.8V, 3.3V, 5V rails). Make sure that is stays always on to prevent undervolting of these volage rails. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605-rb2-l9a-aon-v2-1-0d493d0d107c@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index cb8a62714a30..1c7de7f2db79 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -414,6 +414,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; }; vreg_l10a_1p8: l10 { -- cgit v1.2.3-58-ga151 From 0e8a41e511c98f5f5796c0dca8ff983d1c967b93 Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 3 Jun 2024 02:28:57 -0400 Subject: ARM: dts: qcom: Add initial support for HTC One (M8) Add initial device tree for the HTC One (M8) smartphone. Initial support includes: - eMMC - Power button - USB - Vibrator - Volume buttons (GPIO) - Wi-Fi Signed-off-by: Alexandre Messier Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240603-m8-support-v1-2-c7b6a1941ed2@me.ssier.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 353 ++++++++++++++++++++++ 2 files changed, 354 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index e6114a95428b..e9a8bc74195e 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-htc-m8.dtb \ qcom-msm8974pro-oneplus-bacon.dtb \ qcom-msm8974pro-samsung-klte.dtb \ qcom-msm8974pro-samsung-kltechn.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts new file mode 100644 index 000000000000..b896cc1ad6f7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "qcom-msm8974pro.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" +#include + +/ { + model = "HTC One (M8)"; + compatible = "htc,m8", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volume-down { + label = "volume_down"; + gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 28 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + }; + + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&boost_bypass_n_pin>; + pinctrl-names = "default"; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; +}; + +&pm8941_vib { + status = "okay"; +}; + +&pronto { + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; + + pinctrl-0 = <&wcnss_pin_a>; + pinctrl-names = "default"; + + status = "okay"; + + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "okay"; + }; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&smbb { + status = "okay"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + bias-pull-up; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active-state { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + drive-strength = <6>; + bias-pull-down; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 5b8baed4b88132c12010ce6ca1b56f00d122e376 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 4 Jun 2024 11:36:58 +0530 Subject: arm64: dts: qcom: sc7180: Disable SuperSpeed instances in park mode On SC7180, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7180 to mitigate this issue. Reported-by: Doug Anderson Cc: stable@vger.kernel.org Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240604060659.1449278-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 52d074a4fbf3..9ab0c98cac05 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3066,6 +3066,7 @@ iommus = <&apps_smmu 0x540 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; -- cgit v1.2.3-58-ga151 From 3d930f1750ce30a6c36dbc71f8ff7e20322b94d7 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 4 Jun 2024 11:36:59 +0530 Subject: arm64: dts: qcom: sc7280: Disable SuperSpeed instances in park mode On SC7280, in host mode, it is observed that stressing out controller results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instances in park mode for SC7280 to mitigate this issue. Reported-by: Doug Anderson Cc: stable@vger.kernel.org Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240604060659.1449278-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c3aaa09b8187..ba43fba2c551 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4232,6 +4232,7 @@ iommus = <&apps_smmu 0xe0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; -- cgit v1.2.3-58-ga151 From 0e500122d0e9932f985ba13b9f66e191ff604ffd Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 3 Jun 2024 11:17:17 +0300 Subject: arm64: dts: qcom: x1e80100: Disable the SMB2360 4th instance by default The CRD board doesn't have the 4th SMB2360 PMIC populated while the QCP does. So enable it on QCP only. This fixes the warning for the missing PMIC on CRD as well. Fixes: 2559e61e7ef4 ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240603-x1e80100-dts-pmics-drop-4th-smb2360-from-crd-v2-1-fb63973cc07d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 ++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index a5662d39fdff..e34e70922cd3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -522,6 +522,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + smb2360_3_eusb2_repeater: phy@fd00 { compatible = "qcom,smb2360-eusb2-repeater"; reg = <0xfd00>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 97c81667c6ca..3e72024b72a7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -515,6 +515,10 @@ status = "okay"; }; +&smb2360_3 { + status = "okay"; +}; + &smb2360_0_eusb2_repeater { vdd18-supply = <&vreg_l3d_1p8>; vdd3-supply = <&vreg_l2b_3p0>; -- cgit v1.2.3-58-ga151 From 336e26f80d79d0d686220b4ff062fb9a0db025ab Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 3 Jun 2024 02:28:56 -0400 Subject: dt-bindings: arm: qcom: add HTC One (M8) Add a compatible for the HTC One (M8), which is based on the MSM8974Pro SoC. Signed-off-by: Alexandre Messier Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240603-m8-support-v1-1-c7b6a1941ed2@me.ssier.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 34d32f70a856..1be21a16ba36 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -185,6 +185,7 @@ properties: - items: - enum: - fairphone,fp2 + - htc,m8 - oneplus,bacon - samsung,klte - sony,xperia-castor -- cgit v1.2.3-58-ga151 From 62ae64ceb9a55333f3b259fef8acd0bf1598638a Mon Sep 17 00:00:00 2001 From: Joe Mason Date: Sat, 1 Jun 2024 11:53:57 +0000 Subject: arm64: dts: qcom: msm8916-samsung-gprimeltecan: Add NFC The Samsung Galaxy Grand Prime CAN has a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by: Joe Mason [Stephan: Put NFC pinctrl into common dtsi to share it with other variants] Signed-off-by: Stephan Gerhold [Raymond: Use interrupts-extended. Keep &blsp_i2c6 enabled by default] Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240601115321.25314-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 38 ++++++++++++++++++++++ .../boot/dts/qcom/msm8916-samsung-gprimeltecan.dts | 17 ++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 4f05cae68b37..4cc83b64e256 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { aliases { @@ -227,6 +228,10 @@ }; }; +&blsp_i2c6 { + status = "okay"; +}; + &blsp_uart2 { status = "okay"; }; @@ -346,6 +351,29 @@ bias-disable; }; + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc-pins { + pins = "gpio20", "gpio49"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + nfc_i2c_default: nfc-i2c-default-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; @@ -367,3 +395,13 @@ bias-disable; }; }; + +&pm8916_gpios { + nfc_clk_req: nfc-clk-req-state { + pins = "gpio2"; + function = "func1"; + power-source = ; + bias-disable; + input-enable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 4dc74e8bf1d8..7ac86fd3c703 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -29,6 +29,23 @@ status = "okay"; }; +&blsp_i2c6 { + nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-0 = <&nfc_default>, <&nfc_clk_req>; + pinctrl-names = "default"; + }; +}; + &mpss_mem { /* Firmware for gprimeltecan needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; -- cgit v1.2.3-58-ga151 From 834cfba67835ff2440ef7402e1448a40d3c61250 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sat, 1 Jun 2024 11:54:14 +0000 Subject: arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add S3FWRN5 NFC Some variants of Samsung Galaxy Core Prime LTE / Grand Prime LTE have a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240601115321.25314-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 29 ++++++++++++++++++++++ .../boot/dts/qcom/msm8916-samsung-gprimeltecan.dts | 4 +++ .../dts/qcom/msm8916-samsung-rossa-common.dtsi | 4 +++ 3 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 4cc83b64e256..b5b7beab2209 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -79,6 +79,35 @@ max-microvolt = <3300000>; }; + i2c_nfc: i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&nfc_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + s3fwrn5_nfc: nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-0 = <&nfc_default>, <&nfc_clk_req>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + reg_motor_vdd: regulator-motor-vdd { compatible = "regulator-fixed"; regulator-name = "motor_vdd"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 7ac86fd3c703..589dd006a746 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -46,6 +46,10 @@ }; }; +&i2c_nfc { + /* nfc@27 is on &blsp_i2c6 */ +}; + &mpss_mem { /* Firmware for gprimeltecan needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 13a848d97b9d..e7f265e3c2ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -33,6 +33,10 @@ status = "disabled"; }; +&s3fwrn5_nfc { + status = "okay"; +}; + &st_accel { compatible = "st,lis2hh12"; mount-matrix = "1", "0", "0", -- cgit v1.2.3-58-ga151 From ca4afdfdbbbd64cc08eee834bee97596bb649413 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sat, 1 Jun 2024 11:54:32 +0000 Subject: arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add PMIC and charger The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy Core Prime LTE - Samsung Galaxy Grand Prime Cc: Jakob Hauser Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240601115321.25314-4-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8216-samsung-fortuna3g.dts | 6 +++ .../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 47 ++++++++++++++++++++++ .../boot/dts/qcom/msm8916-samsung-gprimeltecan.dts | 41 +++++++++++++++++++ .../dts/qcom/msm8916-samsung-grandprimelte.dts | 6 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts | 6 +++ 5 files changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts index e7f6df229f9a..fba68bf8bf79 100644 --- a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts +++ b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts @@ -10,6 +10,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &st_accel { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index b5b7beab2209..81b3e0760154 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -27,6 +27,12 @@ }; }; + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + clk_pwm_backlight: backlight { compatible = "pwm-backlight"; pwms = <&clk_pwm 0 100000>; @@ -234,6 +240,8 @@ pinctrl-0 = <&fg_alert_default>; pinctrl-names = "default"; + + power-supplies = <&charger>; }; }; @@ -259,6 +267,38 @@ &blsp_i2c6 { status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; }; &blsp_uart2 { @@ -403,6 +443,13 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 589dd006a746..677e4e286ac0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -21,6 +21,12 @@ }; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &bosch_accel { status = "okay"; }; @@ -30,6 +36,9 @@ }; &blsp_i2c6 { + /* pmic@34 is on i2c_nfc instead */ + /delete-node/ pmic@34; + nfc@27 { compatible = "samsung,s3fwrn5-i2c"; reg = <0x27>; @@ -48,6 +57,38 @@ &i2c_nfc { /* nfc@27 is on &blsp_i2c6 */ + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts index cffad734c4df..582bfcb09684 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts @@ -10,6 +10,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &bosch_accel { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts index ebaa13c6b016..1981bb71f6a9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts @@ -10,6 +10,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <700000>; + constant-charge-voltage-max-microvolt = <4400000>; +}; + &mpss_mem { /* Firmware for rossa needs more space */ reg = <0x0 0x86800000 0x0 0x5800000>; -- cgit v1.2.3-58-ga151 From 6c9b5ba73ca77ef3863cda6560856fdfe7dc237a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 28 May 2024 15:31:59 +0200 Subject: arm64: dts: amlogic: ad402: move thermal-zones to top node It appears that this accidentally got added into the spi node, causing a warning. arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts:119.16-161.4: Warning (spi_bus_reg): /soc/spi@fd000400/thermal-zones: missing or empty reg property Fixes: 593ab951232b ("arm64: dts: amlogic: ad402: setup thermal-zones") Signed-off-by: Arnd Bergmann Acked-by: Neil Armstrong Link: https://lore.kernel.org/r/20240528133215.2266419-1-arnd@kernel.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts | 62 +++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts index c8579b6e67cf..6883471a93b4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts @@ -84,37 +84,6 @@ vin-supply = <&vddao_3v3>; regulator-always-on; }; -}; - -/* Bluetooth HCI H4 */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; -}; - -&uart_AO_B { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_1v8>; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&spifc_pins>; - pinctrl-names = "default"; - - flash@0 { - compatible = "spi-nand"; - status = "okay"; - reg = <0>; - spi-max-frequency = <96000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; thermal-zones { soc_thermal: soc_thermal { @@ -161,6 +130,37 @@ }; }; +/* Bluetooth HCI H4 */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; +}; + +&uart_AO_B { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_1v8>; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&spifc_pins>; + pinctrl-names = "default"; + + flash@0 { + compatible = "spi-nand"; + status = "okay"; + reg = <0>; + spi-max-frequency = <96000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &usb2_phy1 { phy-supply = <&vcc_3v3>; }; -- cgit v1.2.3-58-ga151 From f36596adb56f0381c0c46c5fab23ffd201f7e646 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 4 Jun 2024 08:41:33 +0000 Subject: dt-bindings: arm: amlogic: add GXLX/S905L/p271 reference board Add support for an Amlogic GXLX based S905L SoC and P271 reference design board. The S905L is a low-cost design similar to the P281 (S905W) and is similarly derived from P212 (S905X). However S905L omits support for the VP9 codec and uses Mali 450-MP2 (not MP3). Signed-off-by: Christian Hewitt Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240604084134.3315841-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index a374b98080fe..77f8dfa86e6a 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -107,6 +107,13 @@ properties: - const: amlogic,s905d - const: amlogic,meson-gxl + - description: Boards with the Amlogic Meson GXLX S905L SoC + items: + - enum: + - amlogic,p271 + - const: amlogic,s905l + - const: amlogic,meson-gxlx + - description: Boards with the Amlogic Meson GXM S912 SoC items: - enum: -- cgit v1.2.3-58-ga151 From f6386b5afa81724164263c30c48de733e0aab74c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 4 Jun 2024 08:41:34 +0000 Subject: arm64: dts: meson: add GXLX/S905L/p271 support Add a device-tree for the GXLX Amlogic P271 (S905L) reference design board. This is a low-cost design similar to P281 (S905W) but with silicon differences to omit VP9 and use Mali 450-MP2 (not MP3). The SoC is marked with S905L and "2" (believed to denote MP2) resulting in chip distributor stock lists and Android STB marketing sometimes describing it as an S905L2 chip. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240604084134.3315841-2-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxlx-s905l-p271.dts | 51 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0f29517da5ec..0746e01b5853 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxlx-s905l-p271.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts b/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts new file mode 100644 index 000000000000..1221f4545130 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxlx"; + model = "Amlogic Meson GXLX (S905L) P271 Development Board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + sound { + model = "P271"; + }; +}; + +&apb { + mali: gpu@c0000 { + /* Mali 450-MP2 */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1"; + }; +}; + +&saradc { + compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc"; +}; + +&usb { + dr_mode = "host"; +}; + +&vdec { + compatible = "amlogic,gxlx-vdec", "amlogic,gx-vdec"; +}; -- cgit v1.2.3-58-ga151 From 1d1239a1b0e502faffe43b97d530232285b9f061 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 6 Jun 2024 09:06:15 +0000 Subject: arm64: dts: meson: radxa-zero2: add pwm-fan support The A311D on Zero2 needs active cooling and the board includes a header to connect a simple fan. Add pwm-fan support with basic thermal properties so the fan runs when connected. Suggested-by: Yuntian Zhang Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240606090615.3946433-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 890f5bfebb03..8445701100d0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -33,6 +33,13 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + pwms = <&pwm_AO_ab 0 40000 0>; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; poll-interval = <100>; @@ -286,6 +293,23 @@ clock-latency = <50000>; }; +&cpu_thermal { + trips { + cpu_active: cpu-active { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_active>; + cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &frddr_a { status = "okay"; }; -- cgit v1.2.3-58-ga151 From c830ead0d16131de93d2020369ede4d670a4123b Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Wed, 29 May 2024 11:10:35 +0800 Subject: arm64: dts: amlogic: a4: add power domain controller node Add power domain controller node for Amlogic A4 SoC Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240529-a4_secpowerdomain-v2-3-47502fc0eaf3@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi index 73ca1d7eed81..de10e7aebf21 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -4,6 +4,7 @@ */ #include "amlogic-a4-common.dtsi" +#include / { cpus { #address-cells = <2>; @@ -37,4 +38,13 @@ enable-method = "psci"; }; }; + + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,a4-pwrc"; + #power-domain-cells = <1>; + }; + }; }; -- cgit v1.2.3-58-ga151 From 0354ab18ef5ef11f3139c7252f573c5d4af87c60 Mon Sep 17 00:00:00 2001 From: Aboothahir U Date: Thu, 6 Jun 2024 16:47:28 +0200 Subject: arm64: dts: qcom: pm660: Add rradc, charger MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add charger to PM660 PMIC. Readings from round-robin ADC are needed for charger to function, so add it as well. Signed-off-by: Aboothahir U Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20240606-pm660-charger-rrdac-v1-1-a95d4da24f3b@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 98dc04962fe3..ed2c8e485cdd 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -74,6 +74,23 @@ }; }; + pm660_charger: charger@1000 { + compatible = "qcom,pm660-charger"; + reg = <0x1000>; + + interrupts = <0x0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usb-plugin", "bat-ov", "wdog-bark", "usbin-icl-change"; + + io-channels = <&pm660_rradc 3>, + <&pm660_rradc 4>; + io-channel-names = "usbin_i", "usbin_v"; + + status = "disabled"; + }; + pm660_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -181,6 +198,14 @@ }; }; + pm660_rradc: adc@4500 { + compatible = "qcom,pm660-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + + status = "disabled"; + }; + pm660_gpios: gpio@c000 { compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; -- cgit v1.2.3-58-ga151 From bc90f56a169987975072efa56c3b595eda19668a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 14:50:22 +0200 Subject: arm64: dts: sm8650-hdk: add support for the Display Card overlay With the SM8650-HDK, a Display Card kit can be connected to provide a VTDR6130 display with Goodix Berlin Touch controller. In order to route the DSI lanes to the connector for the Display Card kit, a switch must be changed on the board. The HDMI nodes are disabled since the DSI lanes are shared with the DSI to HDMI transceiver. Add support for this card as an overlay and apply it it at build-time to the sm8650-hdk dtb. Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240606-topic-sm8650-upstream-hdk-v6-1-fb034fe864cc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/sm8650-hdk-display-card.dtso | 141 +++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 56992fc3fc59..0c1cebd16649 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -250,6 +250,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb + +sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso new file mode 100644 index 000000000000..cb102535838d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/* + * Display Card kit overlay + * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */ + +&i2c6 { + status = "disabled"; +}; + +<9611_1v2 { + status = "disabled"; +}; + +<9611_3v3 { + status = "disabled"; +}; + +&vreg_bob_3v3 { + status = "disabled"; +}; + +<9611_codec { + status = "disabled"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&spi4 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <162 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio162"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; -- cgit v1.2.3-58-ga151 From aa48a8a5d642b5806a7bdae52457c87fee3118f8 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 6 Jun 2024 13:41:52 +0300 Subject: arm64: dts: qcom: x1e80100: Add remote endpoints between PHYs and DPs Describe the port/endpoints graph between the USB/DP combo PHYs and their corresponding DP controllers. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-1-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index fe7ca2a73f9d..9944c654851e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2567,6 +2567,7 @@ reg = <2>; usb_1_ss0_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2634,6 +2635,7 @@ reg = <2>; usb_1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; @@ -2701,6 +2703,7 @@ reg = <2>; usb_1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -3995,6 +3998,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; }; @@ -4077,6 +4081,7 @@ reg = <1>; mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; }; @@ -4156,6 +4161,10 @@ port@1 { reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; + }; }; }; -- cgit v1.2.3-58-ga151 From 24b7616a1cd3eeefa91417afc1467981c4cbaf61 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 6 Jun 2024 13:41:53 +0300 Subject: arm64: dts: qcom: x1e80100-crd: Add pmic-glink node with all 3 connectors Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use retimers. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-2-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 122 ++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index f19d89d3d6e1..d0f28d8547b1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -49,6 +49,104 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Right-side port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + reserved-memory { linux,cma { compatible = "shared-dma-pool"; @@ -915,6 +1013,14 @@ dr_mode = "host"; }; +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l2j_1p2>; @@ -939,6 +1045,14 @@ dr_mode = "host"; }; +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l2j_1p2>; @@ -962,3 +1076,11 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; }; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; +}; -- cgit v1.2.3-58-ga151 From 830a24be7dc1711c4e5be82cb319b575af7760f8 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 6 Jun 2024 13:41:54 +0300 Subject: arm64: dts: qcom: x1e80100-qcp: Add pmic-glink node with all 3 connectors Add the pmic-glink node and describe all 3 USB Type-C connectors. Do this for USB only, for now. The DP ports will come at a later stage since they use muxes. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240606-x1e80100-dts-pmic-glink-v2-3-972c902e3e6b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 119 ++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 1b2caa63859b..b045b7bac9e0 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -23,6 +23,101 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + reserved-memory { linux,cma { compatible = "shared-dma-pool"; @@ -615,6 +710,14 @@ dr_mode = "host"; }; +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l2j_1p2>; @@ -639,6 +742,14 @@ dr_mode = "host"; }; +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l2j_1p2>; @@ -662,3 +773,11 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; }; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; +}; -- cgit v1.2.3-58-ga151 From d044c0e36d095996f7b29a928e06c9475c4075e6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 18:00:29 +0200 Subject: arm64: dts: qcom: sm6350-pdx213: correct touchscreen interrupt flags Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605160032.150587-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 88ee04973a2f..bf23033a294e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -293,7 +293,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <22 0x2008>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm6350_l11>; avdd-supply = <&touch_en_vreg>; -- cgit v1.2.3-58-ga151 From fa2c8cad202195bfa87b18dc44ff4981d45085b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 18:00:30 +0200 Subject: arm64: dts: qcom: sm6375-pdx225: correct touchscreen interrupt flags Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605160032.150587-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index cca2c2eb88ad..e04a3b8f81c5 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -142,7 +142,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <22 0x2008>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm6125_l13>; avdd-supply = <&touch_avdd>; -- cgit v1.2.3-58-ga151 From 46822d2750822dbe58bcd999cbedf24147cb5fc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 18:00:31 +0200 Subject: arm64: dts: qcom: sm8250-sony-xperia: correct touchscreen interrupt flags Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240605160032.150587-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index e07d0311ecb5..f6870d3f2886 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -520,7 +520,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <39 0x2008>; + interrupts = <39 IRQ_TYPE_LEVEL_LOW>; /* It's "vddio" downstream but it works anyway! */ vdd-supply = <&vreg_l1c_1p8>; avdd-supply = <&vreg_l10c_3p3>; -- cgit v1.2.3-58-ga151 From 05d84f973d84d23e0a249ae5b3f6d7572fdc5e1e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 18:00:32 +0200 Subject: arm64: dts: qcom: sm8450-sony-xperia: correct touchscreen interrupt flags Interrupt flags 0x2008 looks like some downstream copy-paste, because generic GPIOLIB code, used by Qualcomm pin controller drivers, ignores flags outside of IRQ_TYPE_SENSE_MASK. Probably the intention was to pass just 0x8, so IRQ_TYPE_LEVEL_LOW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # SM8450 PDX223 Link: https://lore.kernel.org/r/20240605160032.150587-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 8b29fcf483a3..17dbb67868ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -488,7 +488,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <21 0x2008>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm8350c_l2>; avdd-supply = <&pm8350c_l3>; -- cgit v1.2.3-58-ga151 From 13f1e1245bb51633d6d1a398fedab7c281beafc3 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Jun 2024 14:42:30 -0700 Subject: arm64: dts: qcom: sc7180: quackingstick: Disable instead of delete usb_c1 It's simpler to reason about things if we disable nodes instead of deleting them. Disable the second usb type-c connector node on quackingstick instead of deleting it so that we can reason about ports more easily. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240604214233.3551692-2-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 5f06842c683b..b7de9fd3fa20 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -10,9 +10,6 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" -/* This board only has 1 USB Type-C port. */ -/delete-node/ &usb_c1; - / { ppvar_lcd: ppvar-lcd-regulator { compatible = "regulator-fixed"; @@ -136,6 +133,11 @@ pp3300_disp_on: &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; +/* This board only has 1 USB Type-C port. */ +&usb_c1 { + status = "disabled"; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ /* -- cgit v1.2.3-58-ga151 From 5abfd513988248b5d27f3a72d71a33129dfb1054 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Jun 2024 14:42:31 -0700 Subject: arm64: dts: qcom: sc7180: pazquel: Add missing comment header We put a header before modifying pinctrl nodes defined in sc7180-trogdor.dtsi in every other file. Add one here so we know that this section is for pinctrl modifications. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240604214233.3551692-3-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 8823edbb4d6e..73aa75621721 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -83,6 +83,8 @@ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + &en_pp3300_dx_edp { pins = "gpio67"; }; -- cgit v1.2.3-58-ga151 From 38b68e62c0d662d8a23aa47799b4ac83c54a8de8 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Jun 2024 14:42:32 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Make clamshell/detachable fragments At a high-level, detachable Trogdors (sometimes known as Strongbads) don't have a cros_ec keyboard, while all clamshell Trogdors (only known as Trogdors) always have a cros_ec keyboard. Looking closer though, all clamshells have a USB type-A connector and a hardwired USB camera. And all detachables replace the USB camera with a MIPI based one and swap the USB type-a connector for the detachable keyboard pogo pins. Split the detachable and clamshell bits into different files so we can describe these differences in one place instead of in each board that includes sc7180-trogdor.dtsi. For now this is just the keyboard part, but eventually this will include the type-a port and the pogo pins. Cc: cros-qcom-dts-watchers@chromium.org Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Pin-yen Lin Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240604214233.3551692-4-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 5 +---- arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 9 +-------- arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 7 +------ arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 3 +-- arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 5 +---- 11 files changed, 31 insertions(+), 31 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi new file mode 100644 index 000000000000..d91533b80e76 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for clamshells + * + * Copyright 2024 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */ +#include diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 7765c8f64905..6e6a4643c4dd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -7,6 +7,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-detachable.dtsi" /* Deleted nodes from sc7180-trogdor.dtsi */ @@ -80,10 +81,6 @@ }; &cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; - cros_ec_proximity: proximity { compatible = "google,cros-ec-mkbp-proximity"; label = "proximity-wifi"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi new file mode 100644 index 000000000000..7c5d8a57ef7f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for detachables + * + * Copyright 2024 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */ +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 2ba3bbf3b9ad..8846a7c4e636 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,9 +5,8 @@ * Copyright 2021 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ - #include "sc7180-trogdor-rt5682i-sku.dtsi" +#include "sc7180-trogdor-detachable.dtsi" / { /* BOARD-SPECIFIC TOP LEVEL NODES */ @@ -135,12 +134,6 @@ ap_ts_pen_1v8: &i2c4 { status = "okay"; }; -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - &panel { compatible = "samsung,atna33xc20"; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index d6db7d83adcf..655bea928e52 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -9,7 +9,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" #include "sc7180-trogdor-rt5682s-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index e9f213d27711..c3fd6760de7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,8 +5,7 @@ * Copyright 2020 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ -#include +#include "sc7180-trogdor-clamshell.dtsi" &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 73aa75621721..cc2c5610a279 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -5,8 +5,7 @@ * Copyright 2021 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ -#include +#include "sc7180-trogdor-clamshell.dtsi" &ap_sar_sensor { compatible = "semtech,sx9324"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 067813f5f437..8214a61276fe 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,8 +6,7 @@ */ #include "sc7180-trogdor.dtsi" -/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index b7de9fd3fa20..00229b1515e6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -9,6 +9,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" +#include "sc7180-trogdor-detachable.dtsi" / { ppvar_lcd: ppvar-lcd-regulator { @@ -44,12 +45,6 @@ status = "okay"; }; -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - &gpio_keys { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index c9667751a990..d393a2712ce6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,8 +8,7 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" -/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 305ad127246e..1d9fc61b6550 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-detachable.dtsi" / { avdd_lcd: avdd-lcd-regulator { @@ -104,10 +105,6 @@ base_detection: cbas { compatible = "google,cros-cbas"; }; - - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; }; &i2c4 { -- cgit v1.2.3-58-ga151 From 1095ad0e92175d19cb7f0b5256af300c921a2d63 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:08 +0200 Subject: arm64: dts: amlogic: meson-g12b-bananapi: remove invalid fan on wrong pwm_cd controller The fan is connected to the GPIOAO_10 pin, which can be connected to the pwm_AO_cd controller, but this one is already used for the vddcpu_b regulator. The fan was wrongly described as using the pwm_cd with the invalid "pwm-gpios" property, both are wrong so remove the fan until we find an acceptable solution. This fixes the following error: pwm@1a000: 'pwm-gpios' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml# Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-1-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 4b8db872bbf3..6a346cb86a53 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -44,13 +44,6 @@ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-levels = <0 120 170 220>; - pwms = <&pwm_cd 1 40000 0>; - }; - hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -374,13 +367,6 @@ clock-names = "clkin0"; }; -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_d_x6_pins>; - pinctrl-names = "default"; - pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>; -}; - &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>; -- cgit v1.2.3-58-ga151 From cf42ea27fd7f087b43da27b709267211e7e0e8c4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:09 +0200 Subject: arm64: dts: amlogic: move ao_pinctrl into aobus The AO pinctrl was mis-described as beeing part of AO rti sysctrl, move it it into aobus like it's also done in GX SoCs, and remove the now invalid '#address-cells', '#size-cells' & 'ranges from the sys-ctrl@0 node. This fixes: sys-ctrl@0: '#address-cells', '#size-cells', 'ranges' do not match any of the regexes: 'pinctrl-[0-9]+' Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-2-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 427 +++++++++++----------- 1 file changed, 212 insertions(+), 215 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index b058ed78faf0..138fb18c6480 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1741,9 +1741,6 @@ compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; clkc_AO: clock-controller { compatible = "amlogic,meson-g12a-aoclkc"; @@ -1752,278 +1749,278 @@ clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "mpeg-clk"; }; + }; - ao_pinctrl: pinctrl { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + ao_pinctrl: pinctrl@14 { + compatible = "amlogic,meson-g12a-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x14 0x0 0x8>, + <0x0 0x1c 0x0 0x8>, + <0x0 0x24 0x0 0x14>; + reg-names = "mux", + "ds", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ao_pinctrl 0 0 15>; + }; - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; + i2c_ao_sck_pins: i2c_ao_sck_pins { + mux { + groups = "i2c_ao_sck"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; + i2c_ao_sda_pins: i2c_ao_sda { + mux { + groups = "i2c_ao_sda"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; + i2c_ao_sck_e_pins: i2c_ao_sck_e { + mux { + groups = "i2c_ao_sck_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; + i2c_ao_sda_e_pins: i2c_ao_sda_e { + mux { + groups = "i2c_ao_sda_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; + mclk0_ao_pins: mclk0-ao { + mux { + groups = "mclk0_ao"; + function = "mclk0_ao"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; + tdm_ao_b_din0_pins: tdm-ao-b-din0 { + mux { + groups = "tdm_ao_b_din0"; + function = "tdm_ao_b"; + bias-disable; }; + }; - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; + spdif_ao_out_pins: spdif-ao-out { + mux { + groups = "spdif_ao_out"; + function = "spdif_ao_out"; + drive-strength-microamp = <500>; + bias-disable; }; + }; - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; + tdm_ao_b_din1_pins: tdm-ao-b-din1 { + mux { + groups = "tdm_ao_b_din1"; + function = "tdm_ao_b"; + bias-disable; }; + }; - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; + tdm_ao_b_din2_pins: tdm-ao-b-din2 { + mux { + groups = "tdm_ao_b_din2"; + function = "tdm_ao_b"; + bias-disable; }; + }; - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; + tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { + mux { + groups = "tdm_ao_b_dout0"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; + tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { + mux { + groups = "tdm_ao_b_dout1"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; + tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { + mux { + groups = "tdm_ao_b_dout2"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; + tdm_ao_b_fs_pins: tdm-ao-b-fs { + mux { + groups = "tdm_ao_b_fs"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; + tdm_ao_b_sclk_pins: tdm-ao-b-sclk { + mux { + groups = "tdm_ao_b_sclk"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; }; + }; - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; + tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { + mux { + groups = "tdm_ao_b_slv_fs"; + function = "tdm_ao_b"; + bias-disable; }; + }; - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; + tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { + mux { + groups = "tdm_ao_b_slv_sclk"; + function = "tdm_ao_b"; + bias-disable; }; + }; - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; + uart_ao_a_pins: uart-a-ao { + mux { + groups = "uart_ao_a_tx", + "uart_ao_a_rx"; + function = "uart_ao_a"; + bias-disable; }; + }; - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; + uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { + mux { + groups = "uart_ao_a_cts", + "uart_ao_a_rts"; + function = "uart_ao_a"; + bias-disable; }; + }; - uart_ao_b_2_3_pins: uart-ao-b-2-3 { - mux { - groups = "uart_ao_b_tx_2", - "uart_ao_b_rx_3"; - function = "uart_ao_b"; - bias-disable; - }; + uart_ao_b_2_3_pins: uart-ao-b-2-3 { + mux { + groups = "uart_ao_b_tx_2", + "uart_ao_b_rx_3"; + function = "uart_ao_b"; + bias-disable; }; + }; - uart_ao_b_8_9_pins: uart-ao-b-8-9 { - mux { - groups = "uart_ao_b_tx_8", - "uart_ao_b_rx_9"; - function = "uart_ao_b"; - bias-disable; - }; + uart_ao_b_8_9_pins: uart-ao-b-8-9 { + mux { + groups = "uart_ao_b_tx_8", + "uart_ao_b_rx_9"; + function = "uart_ao_b"; + bias-disable; }; + }; - uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { - mux { - groups = "uart_ao_b_cts", - "uart_ao_b_rts"; - function = "uart_ao_b"; - bias-disable; - }; + uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { + mux { + groups = "uart_ao_b_cts", + "uart_ao_b_rts"; + function = "uart_ao_b"; + bias-disable; }; + }; - pwm_a_e_pins: pwm-a-e { - mux { - groups = "pwm_a_e"; - function = "pwm_a_e"; - bias-disable; - }; + pwm_a_e_pins: pwm-a-e { + mux { + groups = "pwm_a_e"; + function = "pwm_a_e"; + bias-disable; }; + }; - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; + pwm_ao_a_pins: pwm-ao-a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + bias-disable; }; + }; - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; + pwm_ao_b_pins: pwm-ao-b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + bias-disable; }; + }; - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; + pwm_ao_c_4_pins: pwm-ao-c-4 { + mux { + groups = "pwm_ao_c_4"; + function = "pwm_ao_c"; + bias-disable; }; + }; - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; + pwm_ao_c_6_pins: pwm-ao-c-6 { + mux { + groups = "pwm_ao_c_6"; + function = "pwm_ao_c"; + bias-disable; }; + }; - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; + pwm_ao_d_5_pins: pwm-ao-d-5 { + mux { + groups = "pwm_ao_d_5"; + function = "pwm_ao_d"; + bias-disable; }; + }; - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; + pwm_ao_d_10_pins: pwm-ao-d-10 { + mux { + groups = "pwm_ao_d_10"; + function = "pwm_ao_d"; + bias-disable; }; + }; - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; + pwm_ao_d_e_pins: pwm-ao-d-e { + mux { + groups = "pwm_ao_d_e"; + function = "pwm_ao_d"; }; + }; - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; + remote_input_ao_pins: remote-input-ao { + mux { + groups = "remote_ao_input"; + function = "remote_ao_input"; + bias-disable; }; }; }; -- cgit v1.2.3-58-ga151 From 2478d7bee215cdf6a3a581239d12a17407e30771 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:11 +0200 Subject: arm64: dts: amlogic: sm1: fix tdm audio-controller clock order Fix the clock order in the tdm audio-controller nodes, this fixes the following errors: audio-controller-0: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-4-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 643f94d9d08e..6822c2f3cfed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -17,10 +17,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>, + <&clkc_audio AUD_CLKID_MST_A_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; @@ -28,10 +28,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>, + <&clkc_audio AUD_CLKID_MST_B_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; @@ -39,10 +39,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>, + <&clkc_audio AUD_CLKID_MST_C_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 94befcb819d47b155554997ccfac52354d1b4380 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:12 +0200 Subject: arm64: dts: amlogic: sm1: fix tdm controllers compatible Fixes the following: audio-controller@300: compatible: ['amlogic,sm1-tdmin', 'amlogic,axg-tdmin'] is too long from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml# audio-controller@340: compatible: ['amlogic,sm1-tdmin', 'amlogic,axg-tdmin'] is too long from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml# audio-controller@380: compatible: ['amlogic,sm1-tdmin', 'amlogic,axg-tdmin'] is too long from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml# audio-controller@3c0: compatible: ['amlogic,sm1-tdmin', 'amlogic,axg-tdmin'] is too long from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml# Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-5-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 6822c2f3cfed..d13cf5b4aac7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -275,8 +275,7 @@ }; tdmin_a: audio-controller@300 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; + compatible = "amlogic,sm1-tdmin"; reg = <0x0 0x300 0x0 0x40>; sound-name-prefix = "TDMIN_A"; resets = <&clkc_audio AUD_RESET_TDMIN_A>; @@ -291,8 +290,7 @@ }; tdmin_b: audio-controller@340 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; + compatible = "amlogic,sm1-tdmin"; reg = <0x0 0x340 0x0 0x40>; sound-name-prefix = "TDMIN_B"; resets = <&clkc_audio AUD_RESET_TDMIN_B>; @@ -307,8 +305,7 @@ }; tdmin_c: audio-controller@380 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; + compatible = "amlogic,sm1-tdmin"; reg = <0x0 0x380 0x0 0x40>; sound-name-prefix = "TDMIN_C"; resets = <&clkc_audio AUD_RESET_TDMIN_C>; @@ -323,8 +320,7 @@ }; tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; + compatible = "amlogic,sm1-tdmin"; reg = <0x0 0x3c0 0x0 0x40>; sound-name-prefix = "TDMIN_LB"; resets = <&clkc_audio AUD_RESET_TDMIN_LB>; -- cgit v1.2.3-58-ga151 From 4b7df533684032233f65ea1157ec94215ab3f3da Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:13 +0200 Subject: arm64: dts: amlogic: g12a-u200: drop invalid sound-dai-cells This fixes the following: audio-amplifier-0: '#sound-dai-cells' does not match any of the regexes: 'pinctrl-[0-9]+' Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-6-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 3da7922d83f1..f1a071e13dee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -24,7 +24,6 @@ compatible = "simple-audio-amplifier"; enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; VCC-supply = <&vcc_5v>; - #sound-dai-cells = <0>; sound-name-prefix = "10U2"; }; -- cgit v1.2.3-58-ga151 From 5dab35f183b30c40fb7fb99015811edde96f90d6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:14 +0200 Subject: arm64: dts: amlogic: g12a-u200: add missing AVDD-supply to acodec This fixes the following: audio-controller@32000: 'AVDD-supply' is a required property Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-7-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index f1a071e13dee..0e239939ade6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -373,6 +373,7 @@ }; &acodec { + AVDD-supply = <&vddao_1v8>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 0cb2a3b0d10a3938df546913d738bca121667455 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:15 +0200 Subject: arm64: dts: amlogic: axg: fix tdm audio-controller clock order This fixes the following: audio-controller-0: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:2: 'mclk' was expected Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-8-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 6d12b760b90f..e9b22868983d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -25,10 +25,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>, + <&clkc_audio AUD_CLKID_MST_A_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; @@ -36,10 +36,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>, + <&clkc_audio AUD_CLKID_MST_B_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; @@ -47,10 +47,10 @@ compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; + clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>, + <&clkc_audio AUD_CLKID_MST_C_MCLK>; + clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From e5d4d006a8c5504dfebce7f090ddfb75444491ba Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:16 +0200 Subject: arm64: dts: amlogic: c3: use correct compatible for gpio_intc node This fixes the following: interrupt-controller@4080: compatible: 'oneOf' conditional failed, one must be fixed: ['amlogic,meson-gpio-intc', 'amlogic,c3-gpio-intc'] is too long 'amlogic,meson-gpio-intc' is not one of ['amlogic,meson8-gpio-intc', 'amlogic,meson8b-gpio-intc', 'amlogic,meson-gxbb-gpio-intc', 'amlogic,meson-gxl-gpio-intc', 'amlogic,meson-axg-gpio-intc', 'amlogic,meson-g12a-gpio-intc', 'amlogic,meson-sm1-gpio-intc', 'amlogic,meson-a1-gpio-intc', 'amlogic,meson-s4-gpio-intc', 'amlogic,c3-gpio-intc', 'amlogic,t7-gpio-intc'] 'amlogic,meson-gpio-intc' was expected Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-9-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 32a754fe7990..f8fb060c49ae 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -111,8 +111,7 @@ }; gpio_intc: interrupt-controller@4080 { - compatible = "amlogic,meson-gpio-intc", - "amlogic,c3-gpio-intc"; + compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc"; reg = <0x0 0x4080 0x0 0x0020>; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.2.3-58-ga151 From ea99706a438f19cf352242ffabab46bbc76a03d3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:17 +0200 Subject: arm64: dts: amlogic: a1: use correct node name for mmc controller This fixes the following: sd@10000: $nodename:0: 'sd@10000' does not match '^mmc(@.*)?$' Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-10-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index a3ff266fb17d..c16f57b5ce9f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -432,7 +432,7 @@ clock-names = "fixpll_in", "hifipll_in"; }; - sd_emmc: sd@10000 { + sd_emmc: mmc@10000 { compatible = "amlogic,meson-axg-mmc"; reg = <0x0 0x10000 0x0 0x800>; interrupts = ; -- cgit v1.2.3-58-ga151 From edc15ee0e43948568fa5380c9147feb9a767ae67 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:18 +0200 Subject: arm64: dts: amlogic: a1: drop the invalid reset-name for usb@fe004400 This fixes the following: usb@fe004400: 'reset-name' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+' Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-11-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index c16f57b5ce9f..e5366d4239b1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -466,7 +466,6 @@ assigned-clocks = <&clkc_periphs CLKID_USB_BUS>; assigned-clock-rates = <64000000>; resets = <&reset RESET_USBCTRL>; - reset-name = "usb_ctrl"; dr_mode = "otg"; -- cgit v1.2.3-58-ga151 From e822ce43968daf9da4368617d2c948c22ccf93f9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 6 Jun 2024 10:48:19 +0200 Subject: arm64: dts: amlogic: gxbb-odroidc2: fix invalid reset-gpio property This fixes the following: hub@1: 'reset-gpio' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/genesys,gl850g.yaml# Tested-by: Christian Hewitt Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-12-62e812729541@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index c431986e6a33..c37cc6b036cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -408,6 +408,6 @@ compatible = "usb5e3,610"; reg = <1>; vdd-supply = <&p5v0>; - reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3-58-ga151 From 2bb78d9fb7c997f13309838600eead88cc99e96b Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 27 May 2024 15:41:27 +0200 Subject: arm64: dts: renesas: r8a779h0: Add video capture nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the VIN, CSI-2 and CSISP related nodes found on R-Car V4M. One thing to note is that both CSISP0 and CSISP1 are in the same power domain, this is different from other Gen4 SoCs (R-Car V4H). The reason for this is that R-Car V4M only has one ISP core which is connected to CSISP0 while R-Car V4H has two ISP cores, one connected to each CSISP. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20240527134129.1695450-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 666 ++++++++++++++++++++++++++++++ 1 file changed, 666 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 6d791024cabe..6af0d59e275f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -939,6 +939,454 @@ status = "disabled"; }; + vin00: video@e6ef0000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 730>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 730>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin00isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin00>; + }; + }; + }; + }; + + vin01: video@e6ef1000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 731>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 731>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin01isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin01>; + }; + }; + }; + }; + + vin02: video@e6ef2000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 800>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 800>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin02isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin02>; + }; + }; + }; + }; + + vin03: video@e6ef3000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 801>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 801>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin03isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin03>; + }; + }; + }; + }; + + vin04: video@e6ef4000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 802>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin04isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin04>; + }; + }; + }; + }; + + vin05: video@e6ef5000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 803>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 803>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin05isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin05>; + }; + }; + }; + }; + + vin06: video@e6ef6000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 804>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin06isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin06>; + }; + }; + }; + }; + + vin07: video@e6ef7000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 805>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin07isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin07>; + }; + }; + }; + }; + + vin08: video@e6ef8000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef8000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 806>; + renesas,id = <8>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin08isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin08>; + }; + }; + }; + }; + + vin09: video@e6ef9000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6ef9000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 807>; + renesas,id = <9>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin09isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin09>; + }; + }; + }; + }; + + vin10: video@e6efa000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6efa000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 808>; + renesas,id = <10>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin10isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin10>; + }; + }; + }; + }; + + vin11: video@e6efb000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6efb000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 809>; + renesas,id = <11>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin11isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin11>; + }; + }; + }; + }; + + vin12: video@e6efc000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6efc000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 810>; + renesas,id = <12>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin12isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin12>; + }; + }; + }; + }; + + vin13: video@e6efd000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6efd000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 811>; + renesas,id = <13>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin13isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin13>; + }; + }; + }; + }; + + vin14: video@e6efe000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6efe000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 812>; + renesas,id = <14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin14isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin14>; + }; + }; + }; + }; + + vin15: video@e6eff000 { + compatible = "renesas,vin-r8a779h0"; + reg = <0 0xe6eff000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 813>; + renesas,id = <15>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin15isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin15>; + }; + }; + }; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; @@ -1152,6 +1600,224 @@ interrupts = ; }; + csi40: csi2@fe500000 { + compatible = "renesas,r8a779h0-csi2"; + reg = <0 0xfe500000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 331>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi40isp0: endpoint { + remote-endpoint = <&isp0csi40>; + }; + }; + }; + }; + + csi41: csi2@fe540000 { + compatible = "renesas,r8a779h0-csi2"; + reg = <0 0xfe540000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_MOD 400>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 400>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi41isp1: endpoint { + remote-endpoint = <&isp1csi41>; + }; + }; + }; + }; + + isp0: isp@fed00000 { + compatible = "renesas,r8a779h0-isp"; + reg = <0 0xfed00000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 612>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 612>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp0csi40: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi40isp0>; + }; + }; + + port@1 { + reg = <1>; + isp0vin00: endpoint { + remote-endpoint = <&vin00isp0>; + }; + }; + + port@2 { + reg = <2>; + isp0vin01: endpoint { + remote-endpoint = <&vin01isp0>; + }; + }; + + port@3 { + reg = <3>; + isp0vin02: endpoint { + remote-endpoint = <&vin02isp0>; + }; + }; + + port@4 { + reg = <4>; + isp0vin03: endpoint { + remote-endpoint = <&vin03isp0>; + }; + }; + + port@5 { + reg = <5>; + isp0vin04: endpoint { + remote-endpoint = <&vin04isp0>; + }; + }; + + port@6 { + reg = <6>; + isp0vin05: endpoint { + remote-endpoint = <&vin05isp0>; + }; + }; + + port@7 { + reg = <7>; + isp0vin06: endpoint { + remote-endpoint = <&vin06isp0>; + }; + }; + + port@8 { + reg = <8>; + isp0vin07: endpoint { + remote-endpoint = <&vin07isp0>; + }; + }; + }; + }; + + isp1: isp@fed20000 { + compatible = "renesas,r8a779h0-isp"; + reg = <0 0xfed20000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 613>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp1csi41: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi41isp1>; + }; + }; + + port@1 { + reg = <1>; + isp1vin08: endpoint { + remote-endpoint = <&vin08isp1>; + }; + }; + + port@2 { + reg = <2>; + isp1vin09: endpoint { + remote-endpoint = <&vin09isp1>; + }; + }; + + port@3 { + reg = <3>; + isp1vin10: endpoint { + remote-endpoint = <&vin10isp1>; + }; + }; + + port@4 { + reg = <4>; + isp1vin11: endpoint { + remote-endpoint = <&vin11isp1>; + }; + }; + + port@5 { + reg = <5>; + isp1vin12: endpoint { + remote-endpoint = <&vin12isp1>; + }; + }; + + port@6 { + reg = <6>; + isp1vin13: endpoint { + remote-endpoint = <&vin13isp1>; + }; + }; + + port@7 { + reg = <7>; + isp1vin14: endpoint { + remote-endpoint = <&vin14isp1>; + }; + }; + + port@8 { + reg = <8>; + isp1vin15: endpoint { + remote-endpoint = <&vin15isp1>; + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- cgit v1.2.3-58-ga151 From 28930820bf8928c8247d6b001e042ce7e0037350 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:24 +0200 Subject: arm64: dts: qcom: ipq6018-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-1-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a84cf62d843c..9694140881c6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -923,7 +923,6 @@ thermal-zones { nss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; trips { @@ -937,7 +936,6 @@ nss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; trips { @@ -951,7 +949,6 @@ wcss-phya0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; trips { @@ -979,7 +976,6 @@ cpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 13>; trips { @@ -1009,7 +1005,6 @@ lpass-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 14>; trips { @@ -1023,7 +1018,6 @@ ddrss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 15>; trips { -- cgit v1.2.3-58-ga151 From bebd3c6476c97d0aee8985eb9544dfd82f6e8e36 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:25 +0200 Subject: arm64: dts: qcom: ipq8074-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-2-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 27cf8d50f254..92682d3c9478 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -982,7 +982,6 @@ thermal-zones { nss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -997,7 +996,6 @@ nss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -1012,7 +1010,6 @@ nss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -1027,7 +1024,6 @@ wcss-phya0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -1042,7 +1038,6 @@ wcss-phya1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -1057,7 +1052,6 @@ cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; @@ -1072,7 +1066,6 @@ cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 10>; @@ -1087,7 +1080,6 @@ cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 11>; @@ -1102,7 +1094,6 @@ cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 12>; @@ -1117,7 +1108,6 @@ cluster_thermal: cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 13>; @@ -1132,7 +1122,6 @@ wcss-phyb0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 14>; @@ -1147,7 +1136,6 @@ wcss-phyb1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 15>; -- cgit v1.2.3-58-ga151 From 88dd10e237ee1cfc70595c0feb37c8a71e521bfc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:26 +0200 Subject: arm64: dts: qcom: ipq9574-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Reviewed-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-3-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index d21937b09b4b..04ba09a9156c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -758,8 +758,6 @@ thermal-zones { nss-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 3>; trips { @@ -772,8 +770,6 @@ }; ubi-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 4>; trips { @@ -786,8 +782,6 @@ }; ubi-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 5>; trips { @@ -800,8 +794,6 @@ }; ubi-2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 6>; trips { @@ -814,8 +806,6 @@ }; ubi-3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 7>; trips { @@ -828,8 +818,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 8>; trips { @@ -842,8 +830,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 9>; trips { @@ -856,8 +842,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 10>; trips { @@ -886,8 +870,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 11>; trips { @@ -916,8 +898,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 12>; trips { @@ -946,8 +926,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 13>; trips { @@ -976,8 +954,6 @@ }; wcss-phyb-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 14>; trips { @@ -990,8 +966,6 @@ }; top-glue-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 15>; trips { -- cgit v1.2.3-58-ga151 From b3f0d522b548e969b138c48c0fd4098703363c53 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:27 +0200 Subject: arm64: dts: qcom: msm8916-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-4-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 46bb322ae133..bdedbcdc36d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -2626,7 +2626,6 @@ thermal-zones { cpu0-1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2656,7 +2655,6 @@ cpu2-3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -2686,7 +2684,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2713,7 +2710,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -2728,7 +2724,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; -- cgit v1.2.3-58-ga151 From 19c658e5bfe71b01ae41e85dab076da051814857 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:28 +0200 Subject: arm64: dts: qcom: msm8939-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-5-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 95487de2ca6a..e309ef909ea7 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -2299,7 +2299,6 @@ thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2330,7 +2329,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -2361,7 +2359,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -2392,7 +2389,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -2423,7 +2419,6 @@ cpu4567-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; @@ -2454,7 +2449,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -2482,7 +2476,6 @@ modem1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -2497,7 +2490,6 @@ modem2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2512,7 +2504,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; -- cgit v1.2.3-58-ga151 From 1a43ff5b5f5a51c2dd0859bc46020e7f1c282414 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:29 +0200 Subject: arm64: dts: qcom: msm8953-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-6-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 17 ++++++++--------- arch/arm64/boot/dts/qcom/pm8953.dtsi | 3 --- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index c322d630dd09..1b61a63710a6 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1968,8 +1968,9 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 9>; + trips { cpu0_alert: trip-point0 { temperature = <80000>; @@ -1991,8 +1992,9 @@ }; cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 10>; + trips { cpu1_alert: trip-point0 { temperature = <80000>; @@ -2014,8 +2016,9 @@ }; cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 11>; + trips { cpu2_alert: trip-point0 { temperature = <80000>; @@ -2037,8 +2040,9 @@ }; cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 12>; + trips { cpu3_alert: trip-point0 { temperature = <80000>; @@ -2060,7 +2064,6 @@ }; cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; trips { cpu4_alert: trip-point0 { @@ -2083,7 +2086,6 @@ }; cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; trips { cpu5_alert: trip-point0 { @@ -2106,7 +2108,6 @@ }; cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; trips { cpu6_alert: trip-point0 { @@ -2129,7 +2130,6 @@ }; cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; trips { cpu7_alert: trip-point0 { @@ -2153,7 +2153,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 1067e141be6c..64258505f9ba 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -9,9 +9,6 @@ / { thermal-zones { pm8953-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8953_temp>; trips { -- cgit v1.2.3-58-ga151 From adfb64b78f2f0e894c2520b8e2ff8bd5f2d49825 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:30 +0200 Subject: arm64: dts: qcom: msm8976-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-7-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 9b0f6d1f08be..e299d42c5d98 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1659,7 +1659,6 @@ thermal-zones { aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -1674,7 +1673,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; trips { @@ -1688,7 +1686,6 @@ qdsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; trips { @@ -1702,7 +1699,6 @@ cam-isp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; trips { @@ -1716,7 +1712,7 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 4>; trips { @@ -1740,7 +1736,7 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 5>; trips { @@ -1764,7 +1760,7 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 6>; trips { @@ -1788,7 +1784,7 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 7>; trips { @@ -1812,7 +1808,7 @@ big-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 8>; trips { @@ -1836,7 +1832,7 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 9>; trips { @@ -1860,7 +1856,7 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 10>; trips { -- cgit v1.2.3-58-ga151 From 612f017315fb466bc9348fb9a5f1d9506f4b5260 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:31 +0200 Subject: arm64: dts: qcom: msm8996-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-8-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 14 -------------- arch/arm64/boot/dts/qcom/pm8994.dtsi | 1 - 2 files changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 785ba327f08c..2b20cedfe26c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3729,7 +3729,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3750,7 +3749,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -3771,7 +3769,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3792,7 +3789,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -3813,7 +3809,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -3835,7 +3830,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -3857,7 +3851,6 @@ m4m-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3872,7 +3865,6 @@ l3-or-venus-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3887,7 +3879,6 @@ cluster0-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3902,7 +3893,6 @@ cluster1-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -3917,7 +3907,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -3932,7 +3921,6 @@ q6-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -3947,7 +3935,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -3962,7 +3949,6 @@ modemtx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index d44a95caf04a..353e4a6bd088 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -8,7 +8,6 @@ thermal-zones { pm8994-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm8994_temp>; -- cgit v1.2.3-58-ga151 From 47d92455f59f7e8414ebc962f60bd7a990563a7c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:32 +0200 Subject: arm64: dts: qcom: msm8998-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-9-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 19 ------------------- arch/arm64/boot/dts/qcom/pm8998.dtsi | 1 - 2 files changed, 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 580b7cabf757..3c94d823a514 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -488,7 +488,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -509,7 +508,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -530,7 +528,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -551,7 +548,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -572,7 +568,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -593,7 +588,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -614,7 +608,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -635,7 +628,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -656,7 +648,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -671,7 +662,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -686,7 +676,6 @@ clust0-mhm-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -701,7 +690,6 @@ clust1-mhm-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -716,7 +704,6 @@ cluster1-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -731,7 +718,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -746,7 +732,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -761,7 +746,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -776,7 +760,6 @@ q6-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -791,7 +774,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -806,7 +788,6 @@ multimedia-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 3f82715392c6..3ecb330590e5 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -11,7 +11,6 @@ thermal-zones { pm8998-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm8998_temp>; -- cgit v1.2.3-58-ga151 From d96854de5d69a08a893d4a137d69c65f2feb40d5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:33 +0200 Subject: arm64: dts: qcom: pm7550ba: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-10-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7550ba.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi index 8b00ece987d1..853a1d83a7f0 100644 --- a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm7550ba-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm7550ba_temp_alarm>; -- cgit v1.2.3-58-ga151 From 1a78b5da8164afc1d60bec7c02b8fd8e6451f0f3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:34 +0200 Subject: arm64: dts: qcom: pms405: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-11-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pms405.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 461ad97032f7..3f9100c7eff4 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -12,7 +12,6 @@ thermal-zones { pms405-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pms405_temp>; -- cgit v1.2.3-58-ga151 From 8e49df9200591c469dfbdd29c93ee6cbe970aa2a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:35 +0200 Subject: arm64: dts: qcom: pmx75: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-12-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmx75.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmx75.dtsi b/arch/arm64/boot/dts/qcom/pmx75.dtsi index 373e45f63dff..2e61b7849c92 100644 --- a/arch/arm64/boot/dts/qcom/pmx75.dtsi +++ b/arch/arm64/boot/dts/qcom/pmx75.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmx75-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmx75_temp_alarm>; -- cgit v1.2.3-58-ga151 From d3eb8179f21f86439053745bb1504791236d38bf Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:36 +0200 Subject: arm64: dts: qcom: qcm2290-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-13-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 106110a9f551..e1d176b277ce 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1924,9 +1924,6 @@ thermal-zones { mapss-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -1951,9 +1948,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -1978,9 +1972,6 @@ }; wlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -2005,9 +1996,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -2032,9 +2020,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -2059,9 +2044,6 @@ }; mdm0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -2086,9 +2068,6 @@ }; mdm1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -2113,9 +2092,6 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -2140,9 +2116,6 @@ }; hm-center-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2167,9 +2140,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { -- cgit v1.2.3-58-ga151 From 8d7807d24746af11ba966bce854ef3cd8df5267e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:37 +0200 Subject: arm64: dts: qcom: qcs404-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-14-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 26a0940d42ec..c291bbed6073 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1600,7 +1600,6 @@ thermal-zones { aoss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -1615,7 +1614,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -1630,7 +1628,6 @@ lpass-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -1645,7 +1642,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -1660,7 +1656,6 @@ cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -1694,7 +1689,6 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -1728,7 +1722,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -1762,7 +1755,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -1796,7 +1788,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -1830,7 +1821,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; -- cgit v1.2.3-58-ga151 From a759962163af22b7f50c8f43ed8b3fc5e09bec19 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:38 +0200 Subject: arm64: dts: qcom: sa8775p-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-15-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 8 +-- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 82 ----------------------------- 2 files changed, 4 insertions(+), 86 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index eaa43f022a65..1369c3d43f86 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -10,7 +10,7 @@ thermal-zones { pmm8654au_0_thermal: pm8775-0-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; trips { @@ -30,7 +30,7 @@ pmm8654au_1_thermal: pm8775-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; trips { @@ -50,7 +50,7 @@ pmm8654au_2_thermal: pm8775-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; trips { @@ -70,7 +70,7 @@ pmm8654au_3_thermal: pm8775-3-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index efd588fa2abb..3808fafd6bec 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3511,9 +3511,6 @@ thermal-zones { aoss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -3533,7 +3530,6 @@ cpu-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -3554,7 +3550,6 @@ cpu-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -3575,7 +3570,6 @@ cpu-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -3596,7 +3590,6 @@ cpu-0-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -3617,7 +3610,6 @@ gpuss-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -3638,7 +3630,6 @@ gpuss-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -3659,7 +3650,6 @@ gpuss-2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -3679,9 +3669,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -3700,9 +3687,6 @@ }; camss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -3721,9 +3705,6 @@ }; pcie-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -3742,9 +3723,6 @@ }; cpuss-0-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -3763,9 +3741,6 @@ }; aoss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -3785,7 +3760,6 @@ cpu-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -3806,7 +3780,6 @@ cpu-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -3827,7 +3800,6 @@ cpu-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -3848,7 +3820,6 @@ cpu-0-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -3869,7 +3840,6 @@ gpuss-3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -3890,7 +3860,6 @@ gpuss-4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -3911,7 +3880,6 @@ gpuss-5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -3931,9 +3899,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -3952,9 +3917,6 @@ }; camss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -3973,9 +3935,6 @@ }; pcie-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -3994,9 +3953,6 @@ }; cpuss-0-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { @@ -4015,9 +3971,6 @@ }; aoss-2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 0>; trips { @@ -4037,7 +3990,6 @@ cpu-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 1>; @@ -4058,7 +4010,6 @@ cpu-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 2>; @@ -4079,7 +4030,6 @@ cpu-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 3>; @@ -4100,7 +4050,6 @@ cpu-1-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 4>; @@ -4121,7 +4070,6 @@ nsp-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 5>; @@ -4142,7 +4090,6 @@ nsp-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 6>; @@ -4163,7 +4110,6 @@ nsp-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 7>; @@ -4184,7 +4130,6 @@ nsp-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 8>; @@ -4205,7 +4150,6 @@ nsp-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; @@ -4226,7 +4170,6 @@ nsp-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; @@ -4246,9 +4189,6 @@ }; ddrss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 11>; trips { @@ -4267,9 +4207,6 @@ }; cpuss-1-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 12>; trips { @@ -4288,9 +4225,6 @@ }; aoss-3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 0>; trips { @@ -4310,7 +4244,6 @@ cpu-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 1>; @@ -4331,7 +4264,6 @@ cpu-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 2>; @@ -4352,7 +4284,6 @@ cpu-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 3>; @@ -4373,7 +4304,6 @@ cpu-1-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 4>; @@ -4394,7 +4324,6 @@ nsp-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 5>; @@ -4415,7 +4344,6 @@ nsp-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 6>; @@ -4436,7 +4364,6 @@ nsp-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 7>; @@ -4457,7 +4384,6 @@ nsp-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 8>; @@ -4478,7 +4404,6 @@ nsp-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 9>; @@ -4499,7 +4424,6 @@ nsp-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 10>; @@ -4519,9 +4443,6 @@ }; ddrss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 11>; trips { @@ -4540,9 +4461,6 @@ }; cpuss-1-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 12>; trips { -- cgit v1.2.3-58-ga151 From 7cd2d9080a6eb281701f7303b1699719640380d0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:39 +0200 Subject: arm64: dts: qcom: sc7180-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-16-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 3 --- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 - .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 1 - .../arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 3 --- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 ---------------------- 8 files changed, 1 insertion(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 6de6ed562d97..b4f4d700800d 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -13,7 +13,7 @@ thermal-zones { pm6150_thermal: pm6150-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm6150_temp>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 0fce45276e5c..334f976f1154 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -10,9 +10,6 @@ / { thermal-zones { pm6150l-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6150l_temp>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 6e6a4643c4dd..3c124bbe2f4c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -26,7 +26,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <965>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 8846a7c4e636..b2df22faafe8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -44,7 +44,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <965>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 8214a61276fe..ac8d4589e3fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -13,9 +13,6 @@ / { thermal-zones { 5v-choke-thermal { - polling-delay-passive = <0>; - polling-delay = <250>; - thermal-sensors = <&pm6150_adc_tm 1>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 1d9fc61b6550..af89d80426ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -51,7 +51,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <574>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 8513be297120..4d33c3fbedff 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -21,9 +21,6 @@ / { thermal-zones { charger_thermal: charger-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6150_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 9ab0c98cac05..b5ebf8980325 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -4036,7 +4036,6 @@ thermal-zones { cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; sustainable-power = <1052>; @@ -4085,7 +4084,6 @@ cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; sustainable-power = <1052>; @@ -4134,7 +4132,6 @@ cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; sustainable-power = <1052>; @@ -4183,7 +4180,6 @@ cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; sustainable-power = <1052>; @@ -4232,7 +4228,6 @@ cpu4_thermal: cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; sustainable-power = <1052>; @@ -4281,7 +4276,6 @@ cpu5_thermal: cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; sustainable-power = <1052>; @@ -4330,7 +4324,6 @@ cpu6_thermal: cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; sustainable-power = <1425>; @@ -4371,7 +4364,6 @@ cpu7_thermal: cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; sustainable-power = <1425>; @@ -4412,7 +4404,6 @@ cpu8_thermal: cpu8-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; sustainable-power = <1425>; @@ -4453,7 +4444,6 @@ cpu9_thermal: cpu9-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; sustainable-power = <1425>; @@ -4494,7 +4484,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -4515,7 +4504,6 @@ cpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -4535,7 +4523,6 @@ cpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -4555,7 +4542,6 @@ gpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -4583,7 +4569,6 @@ gpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -4611,7 +4596,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -4632,7 +4616,6 @@ cwlan-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -4653,7 +4636,6 @@ audio-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -4674,7 +4656,6 @@ ddr-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -4695,7 +4676,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -4716,7 +4696,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -4737,7 +4716,6 @@ mdm-core-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -4758,7 +4736,6 @@ mdm-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -4779,7 +4756,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -4800,7 +4776,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 9>; -- cgit v1.2.3-58-ga151 From 7747a49db7e54978151d74b22907a373c9b4de1b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:40 +0200 Subject: arm64: dts: qcom: sc7280-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-17-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 1 - arch/arm64/boot/dts/qcom/pm7325.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 14 +++---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 45 ---------------------- 4 files changed, 8 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 7dc7262f1537..0761e6b5fd8d 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -11,7 +11,6 @@ thermal-zones { pm7250b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm7250b_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi index d1c5476af5ee..6e29468505b2 100644 --- a/arch/arm64/boot/dts/qcom/pm7325.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -35,7 +35,7 @@ &thermal_zones { pm7325_thermal: pm7325-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm7325_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 8cd2fe80dbb2..db42ce917fb0 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -167,7 +167,7 @@ thermal-zones { camera-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -181,7 +181,7 @@ chg-skin-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -195,7 +195,7 @@ conn-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 1>; trips { @@ -209,7 +209,7 @@ quiet-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -223,7 +223,7 @@ rear-cam-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -237,7 +237,7 @@ sdm-skin-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -251,7 +251,7 @@ xo-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ba43fba2c551..f8256d5a8f6b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -6147,7 +6147,6 @@ thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -6191,7 +6190,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -6235,7 +6233,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -6279,7 +6276,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -6323,7 +6319,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -6367,7 +6362,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -6411,7 +6405,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -6455,7 +6448,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -6499,7 +6491,6 @@ cpu8-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -6543,7 +6534,6 @@ cpu9-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -6587,7 +6577,6 @@ cpu10-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -6631,7 +6620,6 @@ cpu11-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -6675,7 +6663,6 @@ aoss0-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -6696,7 +6683,6 @@ aoss1-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -6717,7 +6703,6 @@ cpuss0-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -6737,7 +6722,6 @@ cpuss1-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -6757,7 +6741,6 @@ gpuss0-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -6785,7 +6768,6 @@ gpuss1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -6812,9 +6794,6 @@ }; nspss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -6833,9 +6812,6 @@ }; nspss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -6854,9 +6830,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -6875,9 +6848,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -6896,9 +6866,6 @@ }; mdmss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -6917,9 +6884,6 @@ }; mdmss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -6938,9 +6902,6 @@ }; mdmss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -6959,9 +6920,6 @@ }; mdmss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -6980,9 +6938,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { -- cgit v1.2.3-58-ga151 From 1f57b1cff485c02678ea2dfe0ff7efa3b9f51e9d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:41 +0200 Subject: arm64: dts: qcom: sc8180x-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-18-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 -- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 26 -------------------------- 2 files changed, 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index ddc84282f142..1c6f12fafe1d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -13,7 +13,6 @@ thermal-zones { pmc8180-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmc8180_temp>; @@ -40,7 +39,6 @@ pmc8180c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmc8180c_temp>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 32886aaec126..955e792c10cd 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3768,7 +3768,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3783,7 +3782,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3798,7 +3796,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3813,7 +3810,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -3828,7 +3824,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3843,7 +3838,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3858,7 +3852,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -3873,7 +3866,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -3888,7 +3880,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -3903,7 +3894,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -3918,7 +3908,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -3933,7 +3922,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -3948,7 +3936,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -3963,7 +3950,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -3978,7 +3964,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -3993,7 +3978,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -4015,7 +3999,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -4030,7 +4013,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -4045,7 +4027,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -4060,7 +4041,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -4075,7 +4055,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -4090,7 +4069,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -4105,7 +4083,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -4120,7 +4097,6 @@ mdm-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -4135,7 +4111,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -4150,7 +4125,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; -- cgit v1.2.3-58-ga151 From e388421387e8b1b51c507883aaf13f40277fe137 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:42 +0200 Subject: arm64: dts: qcom: sc8280xp-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-19-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 13 ------------- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index cd914fffcf06..19efa49240ec 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -299,7 +299,7 @@ thermal-zones { skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8280_adc_tm 5>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 945de77911de..1e3babf2e40d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -14,7 +14,7 @@ thermal-zones { pm8280_1_thermal: pm8280-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8280_1_temp_alarm>; trips { @@ -34,7 +34,7 @@ pm8280_2_thermal: pm8280-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8280_2_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index bdfe87b2539f..82c601ef3369 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5879,7 +5879,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -5894,7 +5893,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -5909,7 +5907,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -5924,7 +5921,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -5939,7 +5935,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5954,7 +5949,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5969,7 +5963,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -5984,7 +5977,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -5999,7 +5991,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -6013,9 +6004,6 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 2>; trips { @@ -6029,7 +6017,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 15>; -- cgit v1.2.3-58-ga151 From 82162bf535a76f87e20a6eece83375d2dd791655 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:43 +0200 Subject: arm64: dts: qcom: sdm660-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-20-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660.dtsi | 1 - arch/arm64/boot/dts/qcom/pm660l.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 9 --------- 3 files changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index ed2c8e485cdd..156b2ddff0dc 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm660-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm660_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 6fdbf507c262..0094e0ef058b 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm660l-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm660l_temp>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f202c1f3c89c..1f3e6d8f599a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2422,7 +2422,6 @@ thermal-zones { aoss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -2437,7 +2436,6 @@ cpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -2452,7 +2450,6 @@ cpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2467,7 +2464,6 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -2488,7 +2484,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -2509,7 +2504,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2530,7 +2524,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -2557,7 +2550,6 @@ pwr-cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -2578,7 +2570,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; -- cgit v1.2.3-58-ga151 From 2e58dbeae40e5fc7b2742bed05957cae32031387 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:44 +0200 Subject: arm64: dts: qcom: sdm845-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-21-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ------------ arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 --------------------- 2 files changed, 33 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 76bfa786612c..2391f842c903 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -51,9 +51,6 @@ thermal-zones { xo_thermal: xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 1>; trips { @@ -66,9 +63,6 @@ }; msm_thermal: msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 2>; trips { @@ -81,9 +75,6 @@ }; pa_thermal: pa-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 3>; trips { @@ -96,9 +87,6 @@ }; quiet_thermal: quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 4>; trips { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 493c99c8ce10..3400e30e1829 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5433,7 +5433,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -5460,7 +5459,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -5487,7 +5485,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -5514,7 +5511,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -5541,7 +5537,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -5568,7 +5563,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -5595,7 +5589,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -5622,7 +5615,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -5649,7 +5641,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -5664,7 +5655,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5684,7 +5674,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5704,7 +5693,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -5726,7 +5714,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -5748,7 +5735,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -5763,7 +5749,6 @@ q6-modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -5778,7 +5763,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -5793,7 +5777,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -5808,7 +5791,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -5823,7 +5805,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -5838,7 +5819,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -5853,7 +5833,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; -- cgit v1.2.3-58-ga151 From 190f743561a44cf0176707b6e2f37b1a1b7ff367 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:45 +0200 Subject: arm64: dts: qcom: sm6115-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-22-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi632.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6115.dtsi | 32 -------------------------------- 2 files changed, 33 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index b4313728f3e7..8c899d148e46 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -11,7 +11,6 @@ thermal-zones { pmi632-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmi632_temp>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 5896868d9e6b..98782004257d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -3013,8 +3013,6 @@ thermal-zones { mapss-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -3033,8 +3031,6 @@ }; cdsp-hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -3053,8 +3049,6 @@ }; wlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -3073,8 +3067,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -3093,8 +3085,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -3113,8 +3103,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -3133,8 +3121,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -3159,8 +3145,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -3185,8 +3169,6 @@ }; cpu6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -3211,8 +3193,6 @@ }; cpu7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -3237,8 +3217,6 @@ }; cpu45-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -3263,8 +3241,6 @@ }; cpu67-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -3289,8 +3265,6 @@ }; cpu0123-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -3315,8 +3289,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -3335,8 +3307,6 @@ }; display-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -3355,8 +3325,6 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 15>; cooling-maps { -- cgit v1.2.3-58-ga151 From d1a12560ef38021ce42ac31408fc53d2b8e08cc8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:46 +0200 Subject: arm64: dts: qcom: sm6125-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-23-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 8 -------- arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 6 ------ 3 files changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 99369a0cdb61..d0db28336fa9 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm6125-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm6125_temp>; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 08046f866f60..dcd05f303b78 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -90,8 +90,6 @@ thermal-zones { rf-pa0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 0>; trips { @@ -104,8 +102,6 @@ }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <5000>; thermal-sensors = <&pm6125_adc_tm 1>; trips { @@ -118,8 +114,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 2>; trips { @@ -132,8 +126,6 @@ }; rf-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 3>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index a49d3ebb1931..994fb0412fcb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -84,8 +84,6 @@ thermal-zones { rf-pa0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 0>; trips { @@ -98,8 +96,6 @@ }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <5000>; thermal-sensors = <&pm6125_adc_tm 1>; trips { @@ -112,8 +108,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 2>; trips { -- cgit v1.2.3-58-ga151 From 2aad3fd3820d047fa70b62906565c185d830465c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:47 +0200 Subject: arm64: dts: qcom: sm6350-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-24-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6350.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6350.dtsi | 81 ----------------------- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 -- 3 files changed, 86 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index 3a2a841e83f1..a20ee2457101 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm6350-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm6350_temp>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1ac626d963b8..6452f0f5d9ac 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2883,9 +2883,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -2898,9 +2895,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2913,9 +2907,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; trips { @@ -2928,9 +2919,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -2943,9 +2931,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -2971,9 +2956,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -2999,9 +2981,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -3027,9 +3006,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -3055,9 +3031,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -3083,9 +3056,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -3111,9 +3081,6 @@ }; cpu6-left-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -3139,9 +3106,6 @@ }; cpu6-right-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -3167,9 +3131,6 @@ }; cpu7-left-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -3195,9 +3156,6 @@ }; cpu7-right-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; trips { @@ -3223,9 +3181,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -3238,9 +3193,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -3253,9 +3205,6 @@ }; cwlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; trips { @@ -3268,9 +3217,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -3283,9 +3229,6 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; trips { @@ -3311,9 +3254,6 @@ }; gpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; trips { @@ -3339,9 +3279,6 @@ }; modem-core0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -3354,9 +3291,6 @@ }; modem-core1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -3369,9 +3303,6 @@ }; modem-scl-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -3384,9 +3315,6 @@ }; modem-vec-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -3399,9 +3327,6 @@ }; npu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -3414,9 +3339,6 @@ }; q6-hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -3429,9 +3351,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index d2632f011353..6d7ab931e56b 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -95,8 +95,6 @@ thermal-zones { chg-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -109,8 +107,6 @@ }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 1>; trips { -- cgit v1.2.3-58-ga151 From 088d826d5af3cda20deb04dce406c95ef1ed8563 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:48 +0200 Subject: arm64: dts: qcom: sm6375-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-25-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 78 ------------------------------------ 1 file changed, 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f40509d91bbd..ddea681b536d 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1837,9 +1837,6 @@ thermal-zones { mapss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -1864,9 +1861,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -1891,9 +1885,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -1918,9 +1909,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -1945,9 +1933,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -1972,9 +1957,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -1999,9 +1981,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -2026,9 +2005,6 @@ }; cluster0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -2053,9 +2029,6 @@ }; cluster1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2080,9 +2053,6 @@ }; cpu6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -2107,9 +2077,6 @@ }; cpu7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -2134,9 +2101,6 @@ }; cpu-unk0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -2161,9 +2125,6 @@ }; cpu-unk1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; trips { @@ -2188,9 +2149,6 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; trips { @@ -2215,9 +2173,6 @@ }; gpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; trips { @@ -2242,9 +2197,6 @@ }; mapss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2269,9 +2221,6 @@ }; cwlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; trips { @@ -2296,9 +2245,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; trips { @@ -2323,9 +2269,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -2350,9 +2293,6 @@ }; q6hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -2377,9 +2317,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -2404,9 +2341,6 @@ }; mdm-core0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -2431,9 +2365,6 @@ }; mdm-core1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -2458,9 +2389,6 @@ }; mdm-vec-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -2485,9 +2413,6 @@ }; msm-scl-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -2512,9 +2437,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { -- cgit v1.2.3-58-ga151 From fc2f92b522019a5bfd464c946b15d180c31b092b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:49 +0200 Subject: arm64: dts: qcom: sm8150-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-26-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 1 - arch/arm64/boot/dts/qcom/pm8150b.dtsi | 1 - arch/arm64/boot/dts/qcom/pm8150l.dtsi | 1 - arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 1 - arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ---------------------------- 6 files changed, 33 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 3ba3ba5d8fce..a74a7ff660d2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm8150-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 1aee3270ce7b..3f7b0b6a1d10 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -12,7 +12,6 @@ thermal-zones { pm8150b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150b_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index ac08a09c64c2..3911d6d0d2e2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -12,7 +12,6 @@ thermal-zones { pm8150l-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150l_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index dbd4b91dfe06..5084de66fc46 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -12,7 +12,6 @@ thermal-zones { pmm8155au-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmm8155au_1_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 1cee20ac2c9c..555e4a456ef1 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -11,7 +11,6 @@ thermal-zones { pmm8155au-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmm8155au_2_temp>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index cb878b7305c2..f034145c0675 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4581,7 +4581,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -4625,7 +4624,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -4669,7 +4667,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -4713,7 +4710,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -4757,7 +4753,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -4801,7 +4796,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -4845,7 +4839,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -4889,7 +4882,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -4933,7 +4925,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -4977,7 +4968,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -5021,7 +5011,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -5065,7 +5054,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -5109,7 +5097,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -5124,7 +5111,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5144,7 +5130,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5164,7 +5149,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -5186,7 +5170,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -5201,7 +5184,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -5216,7 +5198,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -5231,7 +5212,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -5246,7 +5226,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -5261,7 +5240,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -5276,7 +5254,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -5291,7 +5268,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -5306,7 +5282,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -5321,7 +5296,6 @@ modem-vec-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 9>; @@ -5336,7 +5310,6 @@ modem-scl-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 10>; @@ -5351,7 +5324,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; -- cgit v1.2.3-58-ga151 From 2d10e2e28df7a690d670b3452d4891b50011dc42 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:50 +0200 Subject: arm64: dts: qcom: sm8250-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-27-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 10 ---------- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 14 -------------- arch/arm64/boot/dts/qcom/sm8250.dtsi | 25 ------------------------- 3 files changed, 49 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index c52357214de5..f22821c13367 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -110,8 +110,6 @@ thermal-zones { conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150b_adc_tm 0>; trips { @@ -124,8 +122,6 @@ }; pm8150l-pcb-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 1>; trips { @@ -138,8 +134,6 @@ }; skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 0>; trips { @@ -152,8 +146,6 @@ }; wifi-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 1>; trips { @@ -166,8 +158,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 7ef99038cb37..21b2ca1def83 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -53,8 +53,6 @@ thermal-zones { camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 0>; trips { @@ -67,8 +65,6 @@ }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150b_adc_tm 0>; trips { @@ -81,8 +77,6 @@ }; mmw-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 2>; trips { @@ -95,8 +89,6 @@ }; mmw-pa2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 2>; trips { @@ -109,8 +101,6 @@ }; skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 1>; trips { @@ -123,8 +113,6 @@ }; skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 1>; trips { @@ -137,8 +125,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f3f9dea0550b..3bd7d6cd1b7c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6299,7 +6299,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -6343,7 +6342,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -6387,7 +6385,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -6431,7 +6428,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -6475,7 +6471,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -6519,7 +6514,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -6563,7 +6557,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -6607,7 +6600,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -6651,7 +6643,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -6695,7 +6686,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -6739,7 +6729,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -6783,7 +6772,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -6827,7 +6815,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -6842,7 +6829,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -6862,7 +6848,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -6882,7 +6867,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -6904,7 +6888,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -6919,7 +6902,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -6934,7 +6916,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -6949,7 +6930,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -6964,7 +6944,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -6979,7 +6958,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -6994,7 +6972,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -7009,7 +6986,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -7024,7 +7000,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; -- cgit v1.2.3-58-ga151 From 07fab48327ad0d85c2b2763d26ce56c84043515a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:51 +0200 Subject: arm64: dts: qcom: sm8350-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-28-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8350.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8350b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmr735a.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmr735b.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 29 ----------------------------- 6 files changed, 5 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 9ed9ba23e81e..cb55b23688d6 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -10,7 +10,7 @@ thermal-zones { pm8350_thermal: pm8350-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index 05c105898892..cf82f8a64a9b 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -10,7 +10,7 @@ thermal-zones { pm8350b_thermal: pm8350b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350b_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index aa74e21fe0dc..1a24e6439e36 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -48,7 +48,7 @@ thermal-zones { pm8350c_thermal: pm8350c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index febda50779f9..f8efd8e5e68f 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -36,7 +36,7 @@ thermal-zones { pmr735a_thermal: pmr735a-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index f7473e247322..09affc05b397 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -10,7 +10,7 @@ thermal-zones { pmr735b_thermal: pmr735b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmr735b_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e01b4d4c07f1..a3f7065ba02d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3690,7 +3690,6 @@ thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3734,7 +3733,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3778,7 +3776,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3822,7 +3819,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -3866,7 +3862,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3910,7 +3905,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3954,7 +3948,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -3998,7 +3991,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -4042,7 +4034,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -4086,7 +4077,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -4130,7 +4120,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -4174,7 +4163,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -4218,7 +4206,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -4233,7 +4220,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -4253,7 +4239,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -4273,7 +4258,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -4288,7 +4272,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -4310,7 +4293,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -4332,7 +4314,6 @@ nspss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -4347,7 +4328,6 @@ nspss2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -4362,7 +4342,6 @@ nspss3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -4377,7 +4356,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -4392,7 +4370,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -4407,7 +4384,6 @@ modem1-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -4422,7 +4398,6 @@ modem2-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 9>; @@ -4437,7 +4412,6 @@ modem3-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 10>; @@ -4452,7 +4426,6 @@ modem4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; @@ -4467,7 +4440,6 @@ camera-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 12>; @@ -4482,7 +4454,6 @@ cam-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 13>; -- cgit v1.2.3-58-ga151 From d0730a729f1a723f06e7b9db7f1a540cf72de871 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:52 +0200 Subject: arm64: dts: qcom: sm8450-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-29-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8450.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 16 ++++----- arch/arm64/boot/dts/qcom/sm8450.dtsi | 64 ++++----------------------------- 3 files changed, 13 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8450.dtsi b/arch/arm64/boot/dts/qcom/pm8450.dtsi index ae5bce3cf46e..decb8809fd36 100644 --- a/arch/arm64/boot/dts/qcom/pm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8450.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8450-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8450_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 71dc06db7736..a754b8fe9167 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -138,7 +138,7 @@ thermal-zones { camera-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -152,7 +152,7 @@ rear-tof-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 5>; trips { @@ -166,7 +166,7 @@ skin-msm-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -180,7 +180,7 @@ therm1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -194,7 +194,7 @@ therm2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 6>; trips { @@ -208,7 +208,7 @@ usb-conn-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 7>; trips { @@ -222,7 +222,7 @@ wide-rfc-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -235,8 +235,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 216f4f703643..04340a794041 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4713,8 +4713,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -4733,8 +4731,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -4753,8 +4749,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -4773,8 +4767,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -4793,8 +4785,6 @@ }; cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -4813,8 +4803,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -4839,8 +4827,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -4865,8 +4851,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -4891,8 +4875,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -4917,8 +4899,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -4943,8 +4923,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -4969,8 +4947,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -4995,8 +4971,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -5021,8 +4995,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -5048,7 +5020,7 @@ gpu-top-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens0 14>; cooling-maps { @@ -5087,7 +5059,7 @@ gpu-bottom-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens0 15>; cooling-maps { @@ -5125,8 +5097,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -5145,8 +5115,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5171,8 +5139,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5197,8 +5163,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5223,8 +5187,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { @@ -5250,7 +5212,7 @@ cdsp0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 5>; trips { @@ -5282,7 +5244,7 @@ cdsp1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 6>; trips { @@ -5314,7 +5276,7 @@ cdsp2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 7>; trips { @@ -5345,8 +5307,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { @@ -5366,7 +5326,7 @@ mem-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 9>; trips { @@ -5391,8 +5351,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 10>; trips { @@ -5423,8 +5381,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 11>; trips { @@ -5455,8 +5411,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 12>; trips { @@ -5487,8 +5441,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 13>; trips { @@ -5519,8 +5471,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -5539,8 +5489,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { -- cgit v1.2.3-58-ga151 From fe5cb7d30795d81ed55888bcfb896086af3adc01 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:53 +0200 Subject: arm64: dts: qcom: sm8550-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-30-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8010.dtsi | 2 - arch/arm64/boot/dts/qcom/pm8550.dtsi | 1 - arch/arm64/boot/dts/qcom/pm8550b.dtsi | 1 - arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 1 - arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 4 -- arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 1 - arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8550.dtsi | 82 ++++++--------------------------- 8 files changed, 13 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi index 0ea641e12209..ef330194946b 100644 --- a/arch/arm64/boot/dts/qcom/pm8010.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8010-m-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8010_m_temp_alarm>; @@ -31,7 +30,6 @@ pm8010-n-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8010_n_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 797a18c249a4..896bcacb6490 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi index 72609f31c890..74d23b8970f4 100644 --- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550b_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi index 4dc1f03ab2c7..9d4734eabf5a 100644 --- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550ve-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550ve_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi index 97b1c18aa7d8..6426b431616b 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550vs-c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_c_temp_alarm>; @@ -31,7 +30,6 @@ pm8550vs-d-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_d_temp_alarm>; @@ -52,7 +50,6 @@ pm8550vs-e-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_e_temp_alarm>; @@ -73,7 +70,6 @@ pm8550vs-g-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_g_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi index 37daaefe3431..f9f1793d310e 100644 --- a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmr735d-k-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmr735d_k_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi index 3b470f6ac46f..d91fbd3bff10 100644 --- a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmr735d-l-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmr735d_l_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c55a818af935..58b2c550b3ec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4590,8 +4590,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -4610,8 +4608,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -4630,8 +4626,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -4650,8 +4644,6 @@ }; cpuss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -4670,8 +4662,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -4690,8 +4680,6 @@ }; cpu3-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -4716,8 +4704,6 @@ }; cpu3-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -4742,8 +4728,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -4768,8 +4752,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -4794,8 +4776,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -4820,8 +4800,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -4846,8 +4824,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -4872,8 +4848,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -4898,8 +4872,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -4924,8 +4896,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -4950,8 +4920,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 15>; trips { @@ -4976,8 +4944,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -4996,8 +4962,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5022,8 +4986,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5048,8 +5010,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5075,7 +5035,7 @@ cdsp0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; trips { @@ -5107,7 +5067,7 @@ cdsp1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; trips { @@ -5139,7 +5099,7 @@ cdsp2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; trips { @@ -5171,7 +5131,7 @@ cdsp3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; trips { @@ -5202,8 +5162,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { @@ -5223,7 +5181,7 @@ mem-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 9>; trips { @@ -5248,8 +5206,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 10>; trips { @@ -5280,8 +5236,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 11>; trips { @@ -5312,8 +5266,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 12>; trips { @@ -5344,8 +5296,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 13>; trips { @@ -5376,8 +5326,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -5396,8 +5344,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { @@ -5416,8 +5362,6 @@ }; aoss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 0>; trips { @@ -5437,7 +5381,7 @@ gpuss-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 1>; cooling-maps { @@ -5476,7 +5420,7 @@ gpuss-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 2>; cooling-maps { @@ -5515,7 +5459,7 @@ gpuss-2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 3>; cooling-maps { @@ -5554,7 +5498,7 @@ gpuss-3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; cooling-maps { @@ -5593,7 +5537,7 @@ gpuss-4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; cooling-maps { @@ -5632,7 +5576,7 @@ gpuss-5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; cooling-maps { @@ -5671,7 +5615,7 @@ gpuss-6-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; cooling-maps { @@ -5710,7 +5654,7 @@ gpuss-7-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; cooling-maps { -- cgit v1.2.3-58-ga151 From 92332cca0551b7c5c44f4236b8d1ce2828888e92 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 13:59:54 +0200 Subject: arm64: dts: qcom: sm8650-*: Remove thermal zone polling delays All of the thermal zone suppliers are interrupt-driven, remove the bogus and unnecessary polling that only wastes CPU time. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-msm-polling-cleanup-v2-31-436ca4218da2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 88 +++++++----------------------------- 1 file changed, 16 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bb0b3c48ee4b..9841d5cba4e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5342,8 +5342,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -5362,8 +5360,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -5382,8 +5378,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -5402,8 +5396,6 @@ }; cpuss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -5422,8 +5414,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -5442,8 +5432,6 @@ }; cpu2-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -5468,8 +5456,6 @@ }; cpu2-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -5494,8 +5480,6 @@ }; cpu3-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -5520,8 +5504,6 @@ }; cpu3-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -5546,8 +5528,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -5572,8 +5552,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -5598,8 +5576,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -5624,8 +5600,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -5650,8 +5624,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -5676,8 +5648,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -5702,8 +5672,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -5722,8 +5690,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5748,8 +5714,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5774,8 +5738,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5800,8 +5762,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { @@ -5826,8 +5786,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; trips { @@ -5853,7 +5811,7 @@ nsphvx0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; trips { @@ -5873,7 +5831,7 @@ nsphvx1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; trips { @@ -5893,7 +5851,7 @@ nsphmx0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; trips { @@ -5913,7 +5871,7 @@ nsphmx1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 9>; trips { @@ -5933,7 +5891,7 @@ nsphmx2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 10>; trips { @@ -5953,7 +5911,7 @@ nsphmx3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 11>; trips { @@ -5973,7 +5931,7 @@ video-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 12>; trips { @@ -5993,7 +5951,7 @@ ddr-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 13>; trips { @@ -6012,8 +5970,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -6032,8 +5988,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { @@ -6052,8 +6006,6 @@ }; aoss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 0>; trips { @@ -6073,7 +6025,7 @@ gpuss0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 1>; trips { @@ -6093,7 +6045,7 @@ gpuss1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 2>; trips { @@ -6113,7 +6065,7 @@ gpuss2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 3>; trips { @@ -6133,7 +6085,7 @@ gpuss3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; trips { @@ -6153,7 +6105,7 @@ gpuss4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; trips { @@ -6173,7 +6125,7 @@ gpuss5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; trips { @@ -6193,7 +6145,7 @@ gpuss6-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; trips { @@ -6213,7 +6165,7 @@ gpuss7-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; trips { @@ -6232,8 +6184,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; trips { @@ -6252,8 +6202,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; trips { @@ -6272,8 +6220,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 11>; trips { @@ -6292,8 +6238,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 12>; trips { -- cgit v1.2.3-58-ga151 From 7c05517e5e68205c9d5085c029df2ca4e6ad9237 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:30 +0200 Subject: arm64: dts: qcom: sc8180x: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-1-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 955e792c10cd..6e707d993aeb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3990,10 +3990,22 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; @@ -4137,10 +4149,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3-58-ga151 From f7fd6d04c1046107a87a0fc883ed044cf8b877a1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:31 +0200 Subject: arm64: dts: qcom: sc8280xp: Throttle the GPU when overheating Add an 85C passive trip point with 1C of hysteresis to ensure the thermal framework takes sufficient action to prevent reaching junction temperature. Also, add passive polling to ensure more than one temperature change event is recorded. Fixes: 014bbc990e27 ("arm64: dts: qcom: sc8280xp: Introduce additional tsens instances") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-2-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 82c601ef3369..80a57aa22839 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6004,10 +6004,25 @@ }; gpu-thermal { + polling-delay-passive = <250>; + thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu-crit { + gpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <110000>; hysteresis = <1000>; type = "critical"; -- cgit v1.2.3-58-ga151 From 545fef1e5e43fb73083d16507a13820179726ebe Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:32 +0200 Subject: arm64: dts: qcom: sdm630: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-3-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 1f3e6d8f599a..94057ebf767f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2582,10 +2582,22 @@ trips { gpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3-58-ga151 From b79dd56ed5fcc863f167eb53771b09e8b3d8e317 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:33 +0200 Subject: arm64: dts: qcom: sdm845: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-4-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 3400e30e1829..a0125f3d92b2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5705,10 +5705,22 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; @@ -5726,10 +5738,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; -- cgit v1.2.3-58-ga151 From c518b5f6def159222d73f3241fb1802bc846a477 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:34 +0200 Subject: arm64: dts: qcom: sm6115: Update GPU thermal zone settings Lower the thresholds to something more reasonable and introduce a passive polling delay to make sure more than one "passive" thermal point is taken into account when throttling. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-5-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 98782004257d..86ac6af2ef0f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -3325,6 +3325,8 @@ }; gpu-thermal { + polling-delay-passive = <250>; + thermal-sensors = <&tsens0 15>; cooling-maps { @@ -3336,13 +3338,13 @@ trips { gpu_alert0: trip-point0 { - temperature = <115000>; - hysteresis = <5000>; + temperature = <85000>; + hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <125000>; + temperature = <110000>; hysteresis = <1000>; type = "critical"; }; -- cgit v1.2.3-58-ga151 From 1a558bbffc2ee9b99226b146fd7928e41db79d41 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:35 +0200 Subject: arm64: dts: qcom: sm6350: Update GPU thermal zone settings Lower the thresholds to something more reasonable and introduce a passive polling delay to make sure more than one "passive" thermal point is taken into account when throttling. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-6-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 6452f0f5d9ac..46e122c4421c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -3229,18 +3229,20 @@ }; gpuss0-thermal { + polling-delay-passive = <250>; + thermal-sensors = <&tsens0 13>; trips { gpuss0_alert0: trip-point0 { - temperature = <95000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpuss0-crit { - temperature = <115000>; - hysteresis = <0>; + temperature = <110000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -3254,18 +3256,20 @@ }; gpuss1-thermal { + polling-delay-passive = <250>; + thermal-sensors = <&tsens0 14>; trips { gpuss1_alert0: trip-point0 { - temperature = <95000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpuss1-crit { - temperature = <115000>; - hysteresis = <0>; + temperature = <110000>; + hysteresis = <1000>; type = "critical"; }; }; -- cgit v1.2.3-58-ga151 From c61300433b7b89d5782fddf95bd96a6e819c0377 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:36 +0200 Subject: arm64: dts: qcom: sm8150: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-7-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f034145c0675..2471b158c76e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -5161,10 +5161,22 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; @@ -5336,10 +5348,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3-58-ga151 From c862b78b7203b72dd6806a77c0feff60fe96dee5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:37 +0200 Subject: arm64: dts: qcom: sm8250: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-8-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 3bd7d6cd1b7c..7a8b1ba2deb0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6879,10 +6879,22 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; @@ -7012,10 +7024,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 10a5555220ad20b2f8043060d76b0e7f83ae91fa Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:38 +0200 Subject: arm64: dts: qcom: sm8350: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-9-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a3f7065ba02d..38ee0850c335 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4284,10 +4284,22 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; @@ -4305,10 +4317,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; -- cgit v1.2.3-58-ga151 From 4be0dd44c39b083148ae9d4c4a7ef6d64e6c0062 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:39 +0200 Subject: arm64: dts: qcom: sm8450: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Remove the copypasta-from-downstream userspace governor entries while at it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-10-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 48 ++++++++++++++---------------------- 1 file changed, 18 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 04340a794041..1e762cc8085a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5031,28 +5031,22 @@ }; trips { - thermal-engine-config { - temperature = <125000>; + gpu_top_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu_top_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5070,28 +5064,22 @@ }; trips { - thermal-engine-config { - temperature = <125000>; + gpu_bottom_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu_bottom_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; -- cgit v1.2.3-58-ga151 From ed979c039ad1c9b02dd7e9fa6a0dd69209bac6ed Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:40 +0200 Subject: arm64: dts: qcom: sm8550: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Remove the copypasta-from-downstream userspace governor entries while at it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-11-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 208 ++++++++++++++--------------------- 1 file changed, 80 insertions(+), 128 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 58b2c550b3ec..4234c92aafe3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5386,34 +5386,28 @@ cooling-maps { map0 { - trip = <&gpu0_junction_config>; + trip = <&gpu0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu0_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu0_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5425,34 +5419,28 @@ cooling-maps { map0 { - trip = <&gpu1_junction_config>; + trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu1_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu1_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5464,34 +5452,28 @@ cooling-maps { map0 { - trip = <&gpu2_junction_config>; + trip = <&gpu2_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu2_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu2_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5503,34 +5485,28 @@ cooling-maps { map0 { - trip = <&gpu3_junction_config>; + trip = <&gpu3_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu3_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu3_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5542,34 +5518,28 @@ cooling-maps { map0 { - trip = <&gpu4_junction_config>; + trip = <&gpu4_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu4_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu4_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5581,34 +5551,28 @@ cooling-maps { map0 { - trip = <&gpu5_junction_config>; + trip = <&gpu5_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu5_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu5_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5620,34 +5584,28 @@ cooling-maps { map0 { - trip = <&gpu6_junction_config>; + trip = <&gpu6_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu6_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu6_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; @@ -5659,34 +5617,28 @@ cooling-maps { map0 { - trip = <&gpu7_junction_config>; + trip = <&gpu7_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu7_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu7_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; -- cgit v1.2.3-58-ga151 From 497624ed550604b3f713f53bc506e49ce5046e5f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 May 2024 14:58:41 +0200 Subject: arm64: dts: qcom: sm8650: Throttle the GPU when overheating Add an 85C passive trip point to ensure the thermal framework takes sufficient action to prevent reaching junction temperature and a 110C critical point to help avoid hw damage. Also, register the GPU as a cooling device and hook it up to the right thermal zones. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240510-topic-gpus_are_cool_now-v1-12-ababc269a438@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 169 ++++++++++++++++++++++++++++------- 1 file changed, 137 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 9841d5cba4e0..5b8b1d581a13 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2632,6 +2632,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -6028,16 +6029,29 @@ thermal-sensors = <&tsens2 1>; + cooling-maps { + map0 { + trip = <&gpu0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu0_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss0-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6048,16 +6062,29 @@ thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss1-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6068,16 +6095,29 @@ thermal-sensors = <&tsens2 3>; + cooling-maps { + map0 { + trip = <&gpu2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu2_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss2-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6088,16 +6128,29 @@ thermal-sensors = <&tsens2 4>; + cooling-maps { + map0 { + trip = <&gpu3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu3_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss3-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6108,16 +6161,29 @@ thermal-sensors = <&tsens2 5>; + cooling-maps { + map0 { + trip = <&gpu4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu4_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss4-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6128,16 +6194,29 @@ thermal-sensors = <&tsens2 6>; + cooling-maps { + map0 { + trip = <&gpu5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu5_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss5-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6148,16 +6227,29 @@ thermal-sensors = <&tsens2 7>; + cooling-maps { + map0 { + trip = <&gpu6_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu6_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss6-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6168,16 +6260,29 @@ thermal-sensors = <&tsens2 8>; + cooling-maps { + map0 { + trip = <&gpu7_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu7_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss7-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; -- cgit v1.2.3-58-ga151 From b32e036a7403289b2a10a438bb852da7ca651c86 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 12 Apr 2024 17:29:22 -0500 Subject: arm64: dts: sprd: Split PMU nodes for heterogeneous CPUs Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20240412222923.3873814-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/sprd/ums512.dtsi | 14 ++++++++++---- arch/arm64/boot/dts/sprd/ums9620.dtsi | 14 ++++++++++---- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index dbdb79f8e959..4c080df48724 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -136,16 +136,22 @@ ; /* Hipervisor PPI */ }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; interrupts = , , , , , - , - , + ; + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; + }; + + pmu-a75 { + compatible = "arm,cortex-a75-pmu"; + interrupts = , ; + interrupt-affinity = <&CPU6>, <&CPU7>; }; soc: soc { diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sprd/ums9620.dtsi index 2191f0a4811b..2458071320c9 100644 --- a/arch/arm64/boot/dts/sprd/ums9620.dtsi +++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi @@ -144,16 +144,22 @@ ; /* Hipervisor PPI */ }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; interrupts = , , , - , - , + ; + interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = , , , ; + interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; soc: soc { -- cgit v1.2.3-58-ga151 From dd2118bd10c1e74b8f0082750bd39c4bcb5fe5f7 Mon Sep 17 00:00:00 2001 From: Mohammad Shehar Yaar Tausif Date: Tue, 23 Apr 2024 20:37:25 +0530 Subject: ARM: dts: vt8500: replace "uhci" nodename with generic name "usb" Replace "uhci" nodenames with "usb" as it's generic and aligns with the schema binding. Signed-off-by: Mohammad Shehar Yaar Tausif Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240423150728.91527-1-sheharyaar48@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/vt8500/vt8500.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8505.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8650.dtsi | 2 +- arch/arm/boot/dts/vt8500/wm8750.dtsi | 4 ++-- arch/arm/boot/dts/vt8500/wm8850.dtsi | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi index b7e09eff5bb2..f23cb5ee11ae 100644 --- a/arch/arm/boot/dts/vt8500/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi @@ -115,7 +115,7 @@ interrupts = <43>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi index 168cd12b07bc..d9e1280372c5 100644 --- a/arch/arm/boot/dts/vt8500/wm8505.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -213,7 +213,7 @@ interrupts = <1>; }; - uhci@d8007300 { + usb@d8007300 { compatible = "platform-uhci"; reg = <0xd8007300 0x200>; interrupts = <0>; diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi index bc057b6f7d16..35d12d77efc0 100644 --- a/arch/arm/boot/dts/vt8500/wm8650.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -185,7 +185,7 @@ interrupts = <43>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi index 33aeb37491f4..b292f85d4e69 100644 --- a/arch/arm/boot/dts/vt8500/wm8750.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -257,13 +257,13 @@ interrupts = <26>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <26>; }; - uhci@d8008d00 { + usb@d8008d00 { compatible = "platform-uhci"; reg = <0xd8008d00 0x200>; interrupts = <26>; diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi index 65c9271050e6..c61717ebb4f1 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -244,13 +244,13 @@ interrupts = <26>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <26>; }; - uhci@d8008d00 { + usb@d8008d00 { compatible = "platform-uhci"; reg = <0xd8008d00 0x200>; interrupts = <26>; -- cgit v1.2.3-58-ga151 From 9edd534fc6553d83ac9f208a64d581f5d20214d7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:47:49 +0200 Subject: ARM: dts: vt8500: align panel timings node name with dtschema DT schema expects panel timings node to follow certain pattern, dtbs_check warnings: vt8500-bv07.dtb: display-timings: '800x480' does not match any of the regexes: '^timing', 'pinctrl-[0-9]+' Linux drivers do not care about node name, so this should not have effect on Linux. Link: https://lore.kernel.org/r/20240509104749.216605-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/vt8500/vt8500-bv07.dts | 2 +- arch/arm/boot/dts/vt8500/wm8505-ref.dts | 2 +- arch/arm/boot/dts/vt8500/wm8650-mid.dts | 2 +- arch/arm/boot/dts/vt8500/wm8850-w70v2.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts index e9f55bd30bd4..38a2da5e2c5d 100644 --- a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts @@ -16,7 +16,7 @@ bits-per-pixel = <16>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts index 2d77c087676e..8ce9e2ef0a81 100644 --- a/arch/arm/boot/dts/vt8500/wm8505-ref.dts +++ b/arch/arm/boot/dts/vt8500/wm8505-ref.dts @@ -16,7 +16,7 @@ bits-per-pixel = <32>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts index f6a42149a0a0..7977b6c1e8eb 100644 --- a/arch/arm/boot/dts/vt8500/wm8650-mid.dts +++ b/arch/arm/boot/dts/vt8500/wm8650-mid.dts @@ -17,7 +17,7 @@ display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts index c7a6fe0ce48f..5d409323b10c 100644 --- a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts @@ -28,7 +28,7 @@ bits-per-pixel = <16>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; -- cgit v1.2.3-58-ga151 From f3ed3b126a3653c7dc21bcf9a22ed2d7a62f83a2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:25 +0200 Subject: ARM: dts: cirrus: align panel timings node name with dtschema DT schema expects panel timings node to follow certain pattern. Linux drivers do not care about node name, so this should not have effect on Linux. Link: https://lore.kernel.org/r/20240509104825.216696-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/cirrus/ep7211-edb7211.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts index 7fb532f227af..808cd5778e27 100644 --- a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -30,7 +30,7 @@ display-timings { native-mode = <&timing0>; - timing0: 320x240 { + timing0: timing-320x240 { hactive = <320>; hback-porch = <0>; hfront-porch = <0>; -- cgit v1.2.3-58-ga151 From ba50141137fae205a731005e70687f4a52289050 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Tue, 30 Apr 2024 14:20:48 +0530 Subject: arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in phy_gmii_sel node Add missing bootph-all property for CPSW MAC's PHY node phy_gmii_sel. Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240430085048.3143665-1-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 3c45782ab2b7..96378b19c419 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -128,6 +128,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &main_pmx0 { /* First pad number is ALW package and second is AMC package */ main_uart0_pins_default: main-uart0-default-pins { -- cgit v1.2.3-58-ga151 From 674a20618b0de1afb62622b5051a5371117a1bfd Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 2 May 2024 14:39:58 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240502091002.3659435-2-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index d511b25d62e3..2fe6a582ceab 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,6 +27,7 @@ mmc1 = &main_sdhci1; i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; }; memory@80000000 { -- cgit v1.2.3-58-ga151 From 01bd39357b70ed41fb52b26c7e5b42de328fcdd4 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 2 May 2024 14:39:59 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes J784S4 SoC has MAIN CPSW2G and CPSW9G instances of the CPSW Ethernet Switch. CPSW2G has 1 external port and 1 host port while CPSW9G has 8 external ports and 1 host port. Add device-tree nodes for MAIN CPSW2G and CPSW9G and disable them by default. MAIN CPSW2G will be enabled in the board file while device-tree overlays will be used to enable CPSW9G. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240502091002.3659435-3-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 +++++++++++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 6a4554c6c9c1..e44ae0cfd457 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -48,6 +48,19 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + cpsw1_phy_gmii_sel: phy@4034 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4034 0x4>; + #phy-cells = <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; + reg = <0x4044 0x20>; + #phy-cells = <1>; + ti,qsgmii-main-ports = <7>, <7>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x00004080 0x30>; @@ -1427,6 +1440,180 @@ }; }; + main_cpsw0: ethernet@c000000 { + compatible = "ti,j784s4-cpswxg-nuss"; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw0_port1: port@1 { + reg = <1>; + label = "port1"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg = <2>; + label = "port2"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg = <3>; + label = "port3"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg = <4>; + label = "port4"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg = <5>; + label = "port5"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg = <6>; + label = "port6"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg = <7>; + label = "port7"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg = <8>; + label = "port8"; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 64 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw1_port1: port@1 { + reg = <1>; + label = "port1"; + phys = <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 62 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- cgit v1.2.3-58-ga151 From c2834656bb6d434bf0df0de7710210fbfe7ff927 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 2 May 2024 14:40:00 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it Enable MAIN CPSW2G and add alias for it to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240502091002.3659435-4-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 2fe6a582ceab..bc5c22383105 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,6 +28,7 @@ i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; + ethernet1 = &main_cpsw1_port1; }; memory@80000000 { @@ -281,6 +282,30 @@ &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins = < @@ -833,6 +858,31 @@ phy-handle = <&mcu_phy0>; }; +&main_cpsw1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_default_pins>; + status = "okay"; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; + status = "okay"; + + main_cpsw1_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw1_phy0>; + status = "okay"; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>; -- cgit v1.2.3-58-ga151 From 4ad0beeb7ae69ae11ec53c897d0b1af1df60454c Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 2 May 2024 14:40:01 +0530 Subject: arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240502091002.3659435-5-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 +++++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 2c327cc320cf..bb3ca0d17788 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ @@ -148,6 +149,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -168,7 +171,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ @@ -186,3 +190,4 @@ DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ +DTC_FLAGS_k3-j784s4-evm += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..dcd2c7c39ec3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + status = "okay"; +}; + +&main_cpsw0_port5 { + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; +}; + +&main_cpsw0_port6 { + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; +}; + +&main_cpsw0_port7 { + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; +}; + +&main_cpsw0_port8 { + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; +}; + +&main_cpsw0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + bus_freq = <1000000>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cpsw9g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status = "okay"; +}; + +&serdes2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + serdes2_qsgmii_link: phy@0 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>; + }; +}; -- cgit v1.2.3-58-ga151 From 838ceca36b2188899a0100461799f179c53de550 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 2 May 2024 14:40:02 +0530 Subject: arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Link: https://lore.kernel.org/r/20240502091002.3659435-6-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 ++++++++++++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index bb3ca0d17788..c4f72004581a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ @@ -151,6 +152,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -172,7 +175,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ - k3-j784s4-evm-quad-port-eth-exp1.dtb + k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..d5f8c8531923 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + pinctrl-names = "default"; + status = "okay"; +}; + +&main_cpsw0_port1 { + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + status = "okay"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */ + status = "okay"; +}; + +&serdes2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes2_usxgmii_link: phy@2 { + reg = <2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; -- cgit v1.2.3-58-ga151 From 6edad223553c7f1680fcaca25ded59eba7c6d82d Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 30 Apr 2024 16:22:51 +0530 Subject: arm64: dts: ti: k3-am62-main: Fix the reg-range for main_pktdma For main_pktdma node, the TX Channel Realtime Register region 'tchanrt' is 128KB and Ring Realtime Register region 'ringrt' is 2MB as shown in memory map in the TRM[0] (Table 2-1). So fix ranges for those register regions. [0]: Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20240430105253.203750-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 448a59dc53a7..0f2722c4bcc3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -141,8 +141,8 @@ compatible = "ti,am64-dmss-pktdma"; reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x4aa00000 0x00 0x20000>, + <0x00 0x4b800000 0x00 0x200000>, <0x00 0x485e0000 0x00 0x10000>, <0x00 0x484a0000 0x00 0x2000>, <0x00 0x484c0000 0x00 0x2000>, -- cgit v1.2.3-58-ga151 From d007a883a61f55b9b195c4c18bbe29de5b802822 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 30 Apr 2024 16:22:52 +0530 Subject: arm64: dts: ti: k3-am62a-main: Fix the reg-range for main_pktdma For main_pktdma node, the TX Channel Realtime Register region 'tchanrt' is 128KB and Ring Realtime Register region 'ringrt' is 2MB as shown in memory map in the TRM[0] (Table 2-1). So fix ranges for those register regions. [0]: Fixes: 3dad70def7ff ("arm64: dts: ti: k3-am62a-main: Add more peripheral nodes") Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20240430105253.203750-3-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index bf9c2d9c6439..ce4a2f105630 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -120,8 +120,8 @@ compatible = "ti,am64-dmss-pktdma"; reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x4aa00000 0x00 0x20000>, + <0x00 0x4b800000 0x00 0x200000>, <0x00 0x485e0000 0x00 0x10000>, <0x00 0x484a0000 0x00 0x2000>, <0x00 0x484c0000 0x00 0x2000>, -- cgit v1.2.3-58-ga151 From a6e6604c600aeedf9700de4a55255850391bc3fc Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 30 Apr 2024 16:22:53 +0530 Subject: arm64: dts: ti: k3-am62p-main: Fix the reg-range for main_pktdma For main_pktdma node, the TX Channel Realtime Register region 'tchanrt' is 128KB and Ring Realtime Register region 'ringrt' is 2MB as shown in memory map in the TRM[0] (Table 2-1). So fix ranges for those register regions. [0]: Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20240430105253.203750-4-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 900d1f9530a2..2b9bc77a0540 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -123,8 +123,8 @@ compatible = "ti,am64-dmss-pktdma"; reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x4aa00000 0x00 0x20000>, + <0x00 0x4b800000 0x00 0x200000>, <0x00 0x485e0000 0x00 0x10000>, <0x00 0x484a0000 0x00 0x2000>, <0x00 0x484c0000 0x00 0x2000>, -- cgit v1.2.3-58-ga151 From f3841b6a22f1a7635dc73b94b98596b94d153ed1 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Mon, 29 Apr 2024 12:58:30 -0700 Subject: arm64: dts: ti: phycore-am64: Add PMIC Add a PMIC node to the phycore-am64 device tree. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240429195830.4027250-2-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 125e507966fb..2c3b20ddfb8b 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -265,6 +265,50 @@ interrupts = <70 IRQ_TYPE_EDGE_FALLING>; wakeup-source; }; + + pmic@61 { + compatible = "ti,lp8733"; + reg = <0x61>; + + buck0-in-supply = <&vcc_5v0_som>; + buck1-in-supply = <&vcc_5v0_som>; + ldo0-in-supply = <&vdd_3v3>; + ldo1-in-supply = <&vdd_3v3>; + + regulators { + vdd_core: buck0 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3: buck1 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_ldo0: ldo0 { + regulator-name = "VDD_1V8_LDO0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdda_1v8: ldo1 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; &main_r5fss0_core0 { -- cgit v1.2.3-58-ga151 From 9dcc0e1065f3c40d0b2ad79a858bb4ebaba33167 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sat, 4 May 2024 13:35:54 +0200 Subject: arm64: dts: ti: k3-am642-hummingboard-t: correct rs485 rts polarity The RS485 transceiver RE (Receiver enable) and DE (Driver enable) are shorted and connected to both RTS/CTS of the SoC UART. RE is active-low, DE is active-high. Remove the "rs485-rts-active-low" flag to match RTS polarity with DE, and fix communication in both transmit and receive directions. Fixes: d60483faf914 ("arm64: dts: add description for solidrun am642 som and evaluation board") Signed-off-by: Josua Mayer Link: https://lore.kernel.org/r/20240504-ti-rs485-rts-v1-1-e88ef1c96f34@solid-run.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts index 234d76e4e944..5b5e9eeec5ac 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts @@ -282,7 +282,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart3_default_pins>; uart-has-rtscts; - rs485-rts-active-low; linux,rs485-enabled-at-boot-time; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 12a29fb4f9a0597ad598f2c986c8e2509a62b6ff Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 6 May 2024 16:32:03 +0530 Subject: arm64: boot: dts: ti: k3-*: Add memory node to bootloader stage Add the bootph-all property to the memory node so that it can be accessed by FDT functions at bootloader stage. The bootloader requires the memory node to be able to initialize and set the size of the DRAM banks. For this purpose, make sure all memory nodes are present and standardized, and modify them if not. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20240506110203.3230255-1-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 ++-- 8 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index aba0c52b1213..aa7139cc8a92 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -33,6 +33,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 0f4a5da0ebc4..2ebb7daa822f 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -11,9 +11,10 @@ / { memory@80000000 { device_type = "memory"; + bootph-all; /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; }; reserved_memory: reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d88651c297a2..102f8fbcc24f 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -35,8 +35,8 @@ device_type = "memory"; bootph-all; /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; }; reserved_memory: reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 7e6a584ac6f0..21fe194a5766 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -12,9 +12,10 @@ / { memory@80000000 { device_type = "memory"; + bootph-all; /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; }; reserved_memory: reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0c4575ad8d7c..a027cf2facee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -31,6 +31,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 1fae6495db07..5ba947771b84 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -12,6 +12,7 @@ / { memory@80000000 { device_type = "memory"; + bootph-all; /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 623c8421525d..82aacc01e8fe 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -13,9 +13,10 @@ / { memory@80000000 { device_type = "memory"; + bootph-all; /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; }; /* Reserving memory regions still pending */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index bc5c22383105..46706907423a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -35,8 +35,8 @@ device_type = "memory"; bootph-all; /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; }; reserved_memory: reserved-memory { -- cgit v1.2.3-58-ga151 From 2cdf63e73415ce6c8f6b3397cdc91d5f928855f9 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 7 May 2024 16:03:32 +0530 Subject: arm64: dts: ti: k3-j722s: Fix main domain GPIO count J722S does not pin out all of the GPIO same as AM62P and have more number of GPIO on the main_gpio1 instance. Fix the GPIO count on both instances by overriding the ti,ngpio property. Fixes: ea55b9335ad8 ("arm64: dts: ti: Introduce J722S family of SoCs") More details at J722S/AM67 Datasheet (Section 5.3.11, GPIO): https://www.ti.com/lit/ds/symlink/am67.pdf Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20240507103332.167928-1-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c75744edb143..9132b0232b0b 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -83,6 +83,14 @@ ti,interrupt-ranges = <7 71 21>; }; +&main_gpio0 { + ti,ngpio = <87>; +}; + +&main_gpio1 { + ti,ngpio = <73>; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; -- cgit v1.2.3-58-ga151 From 021d3d5f0741e5393a7a110ac909fc746b1e0a4d Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Tue, 30 Apr 2024 18:45:12 +0530 Subject: arm64: dts: ti: k3-j721e-sk: Add support for multiple CAN instances CAN instance 0 in the mcu domain is brought on the J721E-SK board through header J1. Thus, add its respective transceiver 1 dt node to add support for this CAN instance. CAN instances 0, 5 and 9 in the main domain are brought on the J721E-SK board through headers J5, J6 and J2 respectively. Thus, add their respective transceivers 2, 3 and 4 dt nodes to add support for these CAN instances. Signed-off-by: Beleswar Padhi Reviewed-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20240430131512.1327283-1-b-padhi@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 116 +++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index a027cf2facee..89fbfb21e5d3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -211,6 +211,42 @@ <3300000 0x1>; }; + transceiver1: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_gpio_pins_default>; + standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_gpio_pins_default>; + standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan9_gpio_pins_default>; + standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>; + }; + dp_pwr_3v3: fixedregulator-dp-prw { compatible = "regulator-fixed"; regulator-name = "dp-pwr"; @@ -368,6 +404,45 @@ >; }; + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ + J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ + >; + }; + + main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */ + >; + }; + + main_mcan5_pins_default: main-mcan5-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */ + J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */ + >; + }; + + main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */ + >; + }; + + main_mcan9_pins_default: main-mcan9-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */ + J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */ + >; + }; + + main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -556,6 +631,19 @@ >; }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */ + >; + }; + /* Reset for M.2 M Key slot on PCIe1 */ mkey_reset_pins_default: mkey-reset-pns-default-pins { pinctrl-single,pins = < @@ -1109,6 +1197,34 @@ num-lanes = <2>; }; +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&main_mcan5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; + +&main_mcan9 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan9_pins_default>; + phys = <&transceiver4>; + status = "okay"; +}; + &ufs_wrapper { status = "disabled"; }; -- cgit v1.2.3-58-ga151 From fadfb0e0cc3ee0251a1dba10f4603798b46bed8f Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Mon, 29 Apr 2024 13:44:45 -0500 Subject: arm64: dts: ti: k3-am62a-wakeup: Enable RTC node On-chip RTC is used as a wakeup source on am62a board designs. This patch removes the disabled status property to enable the RTC node. Signed-off-by: Vibhore Vardhan Tested-by: Kevin Hilman Link: https://lore.kernel.org/r/20240429184445.14876-1-vibhore@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 98043e9aa316..5c5aca4bb925 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -59,7 +59,6 @@ clock-names = "vbus", "osc32k"; power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; wakeup-source; - status = "disabled"; }; wkup_rti0: watchdog@2b000000 { -- cgit v1.2.3-58-ga151 From 4b5156e1a413eaa2094b3281d6ea4e6b31cea01b Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Fri, 12 Apr 2024 01:47:47 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add support for multiple CAN instances CAN instances 0 and 1 in the mcu domain and 16 in the main domain are brought on the evm through headers J42, J43 and J46 respectively. Thus, add their respective transceiver's 0, 1 and 2 dt nodes to add support for these CAN instances. CAN instance 4 in the main domain is brought on the evm through header J45. The CAN High and Low lines from the SoC are routed through a mux on the evm. The select lines need to be set for the CAN signals to reach to its transceiver on the evm. Therefore, add transceiver 3 dt node to add support for this CAN instance. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20240411201747.18697-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 107 +++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 46706907423a..500b70ffe0db 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -274,6 +274,45 @@ }; }; }; + + transceiver0: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; + }; }; &wkup_gpio0 { @@ -362,6 +401,20 @@ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ >; }; + + main_mcan4_pins_default: main-mcan4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ + >; + }; }; &wkup_pmx2 { @@ -441,6 +494,32 @@ J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + >; + }; }; &wkup_pmx1 { @@ -1156,3 +1235,31 @@ }; }; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver0>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver1>; +}; + +&main_mcan16 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan16_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan4_pins_default>; + phys = <&transceiver3>; +}; -- cgit v1.2.3-58-ga151 From 75843b63741b122711d07b8fd672485e69223419 Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Tue, 7 May 2024 15:25:44 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add support for USB Add support for the USB 3.0 controller Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Tested-by: Andrew Halaney # k3-j784s4-evm Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20240507095545.8210-2-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e44ae0cfd457..a41e78f0f9dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -88,6 +88,13 @@ , ; }; + + usb_serdes_mux: mux-controller@4000 { + compatible = "reg-mux"; + reg = <0x4000 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ + }; }; gic500: interrupt-controller@1800000 { @@ -581,6 +588,38 @@ status = "disabled"; }; + usbss0: usb@4104000 { + bootph-all; + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; /* Needs lane config */ + + usb0: usb@6000000 { + bootph-all; + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + }; + }; + main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x02000000 0x00 0x100>; -- cgit v1.2.3-58-ga151 From bed97e94ee2d422f54334bd509b50ae2a3577f67 Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Tue, 7 May 2024 15:25:45 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Enable USB3 support The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for USB. Add the pin mux data and enable USB3 support. Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Tested-by: Andrew Halaney # k3-j784s4-evm Link: https://lore.kernel.org/r/20240507095545.8210-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 500b70ffe0db..a29d302b16b7 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -415,6 +415,13 @@ J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ >; }; + + main_usbss0_pins_default: main-usbss0-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx2 { @@ -1171,6 +1178,40 @@ <&k3_clks 218 22>; }; +&serdes0 { + status = "okay"; + + serdes0_usb_link: phy@3 { + reg = <3>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + &serdes_wiz4 { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 1149215a442b47d54a154c378e6c6080339b3712 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 28 May 2024 09:31:57 +0530 Subject: arm64: dts: ti: k3-am68-sk-base-board: Add LP8733 and TPS6287 nodes Add DTS node for LP87334E PMIC and two TPS6287x high current buck converters. LP87334E is responsible for supplying power to the MCU and MAIN domains as well as to LPDDR4. The two TPS6287x supply power to the MAIN domain for AVS and other core supplies. Signed-off-by: Neha Malcom Francis Link: https://www.ti.com/lit/pdf/slda060 Link: https://lore.kernel.org/r/20240528040159.3919652-2-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index d743f023cdd9..90dbe31c5b81 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -414,6 +414,82 @@ pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + bootph-all; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + status = "okay"; + + lp8733: pmic@60 { + compatible = "ti,lp8733"; + reg = <0x60>; + buck0-in-supply = <&vsys_3v3>; + buck1-in-supply = <&vsys_3v3>; + ldo0-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + + lp8733_regulators: regulators { + lp8733_buck0_reg: buck0 { + /* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */ + regulator-name = "lp8733-buck0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8733_buck1_reg: buck1 { + /* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */ + regulator-name = "lp8733-buck1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8733_ldo0_reg: ldo0 { + /* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */ + regulator-name = "lp8733-ldo0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8733_ldo1_reg: ldo1 { + /* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */ + regulator-name = "lp8733-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + tps62873a: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + bootph-pre-ram; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible = "ti,tps62873"; + reg = <0x43>; + regulator-name = "VDD_CORE_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- cgit v1.2.3-58-ga151 From 80ad4406922cdeab683c6db22e0a97e54570cc07 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 28 May 2024 09:31:58 +0530 Subject: arm64: dts: ti: k3-am69-sk: Add TPS62873 node Add DTS node for two TPS6287x high current buck convertors. The two TPS6287x supply power to the MAIN domain for AVS and other core supplies. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20240528040159.3919652-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 102f8fbcc24f..6b301efbd1b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -814,6 +814,27 @@ }; }; }; + + tps62873a: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + bootph-pre-ram; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible = "ti,tps62873"; + reg = <0x43>; + regulator-name = "VDD_CORE_0V8"; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; }; &wkup_gpio0 { -- cgit v1.2.3-58-ga151 From 79160cabf3136992be4276c22858688e9e1925f2 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 28 May 2024 09:31:59 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add TPS62873 node Add Tulip TPS62873 nodes for J784S4 EVM. These are step-down regulators that supply VDD_CPU_AVS and VDD_CORE_0V8 to the SoC. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20240528040159.3919652-4-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index a29d302b16b7..41f423dc4eea 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -691,6 +691,27 @@ }; }; }; + + tps62873a: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + bootph-pre-ram; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1330000>; + regulator-boot-on; + regulator-always-on; + }; + + tps62873b: regulator@43 { + compatible = "ti,tps62873"; + reg = <0x43>; + regulator-name = "VDD_CORE_0V8"; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; }; &mcu_uart0 { -- cgit v1.2.3-58-ga151 From 53a3960410c2e703fda2f98706668570eff5ecd4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 29 May 2024 12:14:18 +0530 Subject: arm64: dts: ti: k3-am64-main: Add PRU system events for virtio PRU system events "vring" have been added to each PRU and RTU node in each of the ICSSG0 and ICSSG1 remote processor subsystems to enable the virtio/rpmsg communication between MPU and that PRU/RTU core. No events have been added to the Tx_PRU cores at present. The additions are done in the base k3-am64main.dtsi, and so are inherited by all the K3 AM64x boards. The PRU system events is the preferred approach over using TI mailboxes, as it eliminates an external peripheral access from the PRU/RTU-side, and keeps the interrupt generation internal to the ICSSG. The difference from MPU would be minimal in using one versus the other. Mailboxes can still be used if desired, but currently there is no support on firmware-side for K3 SoCs to use mailboxes. Either approach would require that an appropriate firmware image is loaded/booted on the PRU. Signed-off-by: Suman Anna Signed-off-by: Kishon Vijay Abraham I Acked-by: Ravi Gunasekaran Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20240529064420.571615-2-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 6f9aa5e02138..f8370dd03350 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1283,6 +1283,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu0_0: rtu@4000 { @@ -1292,6 +1295,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru0_0: txpru@a000 { @@ -1310,6 +1316,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu0_1: rtu@6000 { @@ -1319,6 +1328,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru0_1: txpru@c000 { @@ -1436,6 +1448,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu1_0: rtu@4000 { @@ -1445,6 +1460,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru1_0: txpru@a000 { @@ -1463,6 +1481,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-pru1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu1_1: rtu@6000 { @@ -1472,6 +1493,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am64x-rtu1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru1_1: txpru@c000 { -- cgit v1.2.3-58-ga151 From 8ec9ce361d55d995c4619346e0b9c56b9ba6e5d2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 29 May 2024 12:14:19 +0530 Subject: arm64: dts: ti: k3-am65-main: Add PRU system events for virtio A PRU system event "vring" has been added to each PRU and RTU node in each of the ICSSG0, ICSSG1 and ICSSG2 remote processor subsystems to enable the virtio/rpmsg communication between MPU and that PRU/RTU core. The additions are done in the base k3-am65-main.dtsi, and so are inherited by all the K3 AM65x boards. The PRU system events is the preferred approach over using TI mailboxes, as it eliminates an external peripheral access from the PRU/RTU-side, and keeps the interrupt generation internal to the ICSSG. The difference from MPU would be minimal in using one versus the other. Mailboxes can still be used if desired, but currently there is no support on firmware-side for K3 SoCs to use mailboxes. Either approach would require that an appropriate firmware image is loaded/booted on the PRU. Signed-off-by: Suman Anna Signed-off-by: Kishon Vijay Abraham I Acked-by: Ravi Gunasekaran Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20240529064420.571615-3-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ed71561c5bd9..1af3dedde1f6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1185,6 +1185,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu0_0: rtu@4000 { @@ -1194,6 +1197,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu0_0-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru0_0: txpru@a000 { @@ -1212,6 +1218,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu0_1: rtu@6000 { @@ -1221,6 +1230,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu0_1-fw"; + interrupt-parent = <&icssg0_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru0_1: txpru@c000 { @@ -1339,6 +1351,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu1_0: rtu@4000 { @@ -1348,6 +1363,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu1_0-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru1_0: txpru@a000 { @@ -1366,6 +1384,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu1_1: rtu@6000 { @@ -1375,6 +1396,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu1_1-fw"; + interrupt-parent = <&icssg1_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru1_1: txpru@c000 { @@ -1493,6 +1517,9 @@ <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; }; rtu2_0: rtu@4000 { @@ -1502,6 +1529,9 @@ <0x23400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <20 4 4>; + interrupt-names = "vring"; }; tx_pru2_0: txpru@a000 { @@ -1520,6 +1550,9 @@ <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-pru2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; }; rtu2_1: rtu@6000 { @@ -1529,6 +1562,9 @@ <0x23c00 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am65x-rtu2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <22 5 5>; + interrupt-names = "vring"; }; tx_pru2_1: txpru@c000 { -- cgit v1.2.3-58-ga151 From 4d0101e8c69b3324f30bb596d56b5242ffbc6972 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Mon, 29 Apr 2024 14:59:19 +0530 Subject: arm64: dts: ti: k3-am642-evm-icssg1-dualemac: add overlay for mii mode Add device tree overlay to enable both ICSSG1 ports available on AM64x-EVM in MII mode. Signed-off-by: MD Danish Anwar Reviewed-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20240429092919.657629-1-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso | 101 +++++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c4f72004581a..8245e719d015 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -44,6 +44,7 @@ k3-am642-hummingboard-t-usb3-dtbs := \ k3-am642-hummingboard-t.dtb k3-am642-hummingboard-t-usb3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb @@ -134,6 +135,8 @@ k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo +k3-am642-evm-icssg1-dualemac-mii-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ @@ -168,6 +171,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ + k3-am642-evm-icssg1-dualemac-mii.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso new file mode 100644 index 000000000000..423d6027278d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling both ICSSG1 port on AM642 EVM in MII mode + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_mii1_pins_default: icssg1-mii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */ + AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */ + >; + }; + + icssg1_mii2_pins_default: icssg1-mii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */ + AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */ + AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */ + AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */ + AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */ + AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */ + AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>; +}; + +&icssg1_emac0 { + phy-mode = "mii"; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "mii"; +}; -- cgit v1.2.3-58-ga151 From 6ee3ca0ec7fabc63603afdb3485da04164dc8747 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:40 +0530 Subject: arm64: dts: ti: k3-am62x: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: b94b43715e91 ("arm64: dts: ti: Enable audio on SK-AM62(-LP)") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-1-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 96378b19c419..f4948b937627 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -508,8 +508,6 @@ 0 0 0 0 0 0 0 0 >; - tx-num-evt = <32>; - rx-num-evt = <32>; }; &dss { -- cgit v1.2.3-58-ga151 From a931b81072921a11d5bb8e8201b6228b791d40a9 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:41 +0530 Subject: arm64: dts: ti: k3-am62a7: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: 4a2c5dddf9e9 ("arm64: dts: ti: k3-am62a7-sk: Enable audio on AM62A") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-2-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index fa43cd0b631e..e026f65738b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -701,8 +701,6 @@ 0 0 0 0 0 0 0 0 >; - tx-num-evt = <32>; - rx-num-evt = <32>; }; &dss { -- cgit v1.2.3-58-ga151 From d3fe4b4e2e44de64ed1f1585151bf4a3627adbaf Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:42 +0530 Subject: arm64: dts: ti: k3-am62p5: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: c00504ea42c0 ("arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-3-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6e7234659111..78d4d44e8bd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -549,8 +549,6 @@ 0 0 0 0 0 0 0 0 >; - tx-num-evt = <32>; - rx-num-evt = <32>; }; &fss { -- cgit v1.2.3-58-ga151 From 3b4a03357aee07a32a44a49bb6a71f5e82b1ecc1 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:43 +0530 Subject: arm64: dts: ti: k3-am625-beagleplay: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: 1f7226a5e52c ("arm64: dts: ti: k3-am625-beagleplay: Add HDMI support") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-4-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 18e3070a8683..70de288d728e 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -924,6 +924,4 @@ 0 0 0 0 0 0 0 0 >; - tx-num-evt = <32>; - rx-num-evt = <32>; }; -- cgit v1.2.3-58-ga151 From fb01352801f08740e9f37cbd71f73866c7044927 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:44 +0530 Subject: arm64: dts: ti: k3-am62-verdin: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Acked-by: Francesco Dolcini Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-5-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 2038c5e04639..359f53f3e019 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1364,8 +1364,6 @@ 0 0 0 0 >; tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -1382,8 +1380,6 @@ 0 0 0 0 >; tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; #sound-dai-cells = <0>; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 554dd562a5f2f5d7e838f7b229a1c612275678db Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:45 +0530 Subject: arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Drop McASP AFIFOs McASP AFIFOs are not necessary with UDMA-P/BCDMA as there is buffering on the DMA IP. Drop these for better audio latency. Fixes: 28c0cf16b308 ("arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add Audio Codec") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-6-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index 50d2573c840e..6c24e4d39ee8 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -441,8 +441,6 @@ 0 0 0 0 0 0 0 0 >; - tx-num-evt = <32>; - rx-num-evt = <32>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From e96e36ce1fdcf08a70e3f09cbe2da02b073c58ac Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 6 Jun 2024 13:37:46 +0530 Subject: arm64: dts: ti: k3-am62p5-sk: Fix pinmux for McASP1 TX On SK-AM62P, McASP1 uses two pins for communicating with the codec over I2S protocol. One of these pins (AXR0) is used for audio playback (TX) so the direction of the pin should be OUTPUT. Fixes: c00504ea42c0 ("arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM") Signed-off-by: Jai Luthra Link: https://lore.kernel.org/r/20240606-mcasp_fifo_drop-v2-7-8c317dabdd0a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 78d4d44e8bd4..fb980d46e304 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -207,7 +207,7 @@ pinctrl-single,pins = < AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ - AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ >; }; -- cgit v1.2.3-58-ga151 From 7a5775a3da906dab059b8de60a2b88f6016cb4b8 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 25 Apr 2024 15:19:25 -0700 Subject: arm64: dts: ti: am62-phyboard-lyra: Add overlay to increase cpu frequency to 1.4 GHz The am625 is capable of running at 1.4 GHz when VDD_CORE is increased from 0.75V to 0.85V. Increasing the voltage while the AM625 is running has not been validated by TI, so we provide an overlay so that people may choose to run at 1.4 GHz if they need the additional performance. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240425221925.1781226-1-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 3 +++ .../dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8245e719d015..381a7870c88f 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb @@ -110,6 +111,8 @@ k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso new file mode 100644 index 000000000000..6ec6d57ec49c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +&vdd_core { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; +}; + +&a53_opp_table { + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + }; +}; -- cgit v1.2.3-58-ga151 From 2116f8b73f69a02e42daa89ca3561f367a390e30 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 4 Jun 2024 16:14:25 +0530 Subject: arm64: dts: ti: k3-am62p: use eFuse MAC Address for CPSW3G Port 1 Add the "ethernet-mac-syscon" node within "wkup_conf" node corresponding to the CTRLMMR_MAC_IDx registers within the CTRL_MMR space. Assign the compatible "ti,am62p-cpsw-mac-efuse" to enable "syscon_regmap" operations on these registers. The MAC Address programmed in the eFuse is accessible through the CTRLMMR_MAC_IDx registers. The "ti,syscon-efuse" device-tree property points to the CTRLMMR_MAC_IDx registers, allowing the CPSW driver to fetch the MAC Address and assign it to the network interface associated with CPSW3G MAC Port 1. Signed-off-by: Siddharth Vadapalli Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240604104425.3770037-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 2b9bc77a0540..eed06506f617 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -749,6 +749,7 @@ label = "port1"; phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index c71d9624ea27..71784e10b4f1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -19,6 +19,11 @@ bootph-all; }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; -- cgit v1.2.3-58-ga151 From 8e05ce691af29db0c7f0d468c8d7c6e13273a9e6 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 29 May 2024 13:52:56 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add PCIe nodes TI's J784S4 SoC has four instances of Gen3 PCIe Controllers namely PCIe0, PCIe1, PCIe2 and PCIe3. PCIe0 and PCIe1 are 4-Lane controllers while PCIe2 and PCIe3 are 2-Lane controllers. Add support for the Root Complex Mode of operation of these PCIe instances. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20240529082259.1619695-2-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 10 ++- 2 files changed, 145 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index a41e78f0f9dd..fd3d3344efbe 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -61,6 +61,26 @@ ti,qsgmii-main-ports = <7>, <7>; }; + pcie0_ctrl: pcie0-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + + pcie1_ctrl: pcie1-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + + pcie2_ctrl: pcie2-ctrl@4078 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4078 0x4>; + }; + + pcie3_ctrl: pcie3-ctrl@407c { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x00004080 0x30>; @@ -959,6 +979,122 @@ status = "disabled"; }; + pcie0_rc: pcie@2900000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb012>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb012>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; + }; + + pcie2_rc: pcie@2920000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 334 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb012>; + msi-map = <0x0 &gic_its 0x20000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 335 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb012>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j784s4-wiz-10g"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index da7368ed6b52..73cc3c1fec08 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -238,7 +238,10 @@ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/ + <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/ + <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ @@ -248,7 +251,12 @@ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ + <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */ + <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ /* MCUSS_WKUP Range */ -- cgit v1.2.3-58-ga151 From 27ce26fe52d4dcb5bf58cdf5527e2f3a498c1fdf Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 29 May 2024 13:52:57 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Enable PCIe0 and PCIe1 instances of PCIe in Root Complex mode of operation on J784S4 EVM. The lanes of PCIe0 are connected to Serdes1 instance of Serdes while the lanes of PCIe1 are connected to Serdes0 instance of Serdes in J784S4 SoC. Despite both PCIe instances supporting up to 4 Lanes, since the physical connections to the PCIe connector corresponding to the PCIe1 instance of PCIe are limited to 2 Lanes on the J784S4 EVM, update the "num-lanes" property of PCIe1 accordingly. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20240529082259.1619695-3-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 41f423dc4eea..a4a6efcce362 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -1325,3 +1325,51 @@ pinctrl-0 = <&main_mcan4_pins_default>; phys = <&transceiver3>; }; + +&serdes0 { + status = "okay"; + + serdes0_pcie1_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, + <&serdes_wiz0 3>, <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&pcie1_rc { + status = "okay"; + num-lanes = <2>; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; +}; + +&serdes1 { + status = "okay"; + + serdes1_pcie0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie0_link>; + phy-names = "pcie-phy"; +}; -- cgit v1.2.3-58-ga151 From 7c4270de2806f80c06dc80c2cf2c8d6eb7c44c59 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 29 May 2024 13:52:58 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Add overlay to enable the PCIe0 and PCIe1 instances of PCIe on J784S4-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20240529082259.1619695-4-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 ++ .../boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 381a7870c88f..d956372a7163 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo @@ -156,6 +157,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \ @@ -182,6 +185,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso new file mode 100644 index 000000000000..685305092bd8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration + * on J784S4 EVM. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status = "disabled"; +}; + +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 332 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes1_pcie0_link>; + phy-names = "pcie-phy"; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; + }; +}; -- cgit v1.2.3-58-ga151 From 2f79e7408ac1b22ce8abc4a22b92793a57a3077d Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Wed, 29 May 2024 13:52:59 +0530 Subject: arm64: dts: ti: k3-am69-sk: Add PCIe support The AM69-SK board has 3 instances of PCIe namely PCIe0, PCIe1 and PCIe3. The x4 PCIe0 instance is connected to a Card Edge connector via SERDES1. The x2 PCIe1 instance is connected to an M.2 M Key connector via SERDES0. The x1 PCIe3 instance is connected to an M.2 E Key connector via SERDES0. Add device-tree support for enabling all 3 PCIe instances in Root-Complex mode of operation. Signed-off-by: Dasnavis Sabiya Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20240529082259.1619695-5-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 62 +++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 6b301efbd1b5..3f655852244e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -1224,3 +1224,65 @@ }; }; }; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <3>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; + }; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&serdes1 { + status = "okay"; + + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>; + }; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie3_rc { + status = "okay"; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; -- cgit v1.2.3-58-ga151 From ee5dcd7393af9af3494f533a6308faa539bd6718 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 6 Jun 2024 11:09:06 +0200 Subject: arm64: dts: qcom: qcm6490-fairphone-fp5: Use .mbn firmware for IPA Specify the file name for the squashed/non-split firmware with the .mbn extension instead of the split .mdt. The kernel can load both but the squashed version is preferred in dts nowadays. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-fp5-ipa-mbn-v1-1-183668affe58@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index db42ce917fb0..25ed74d4ebd2 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -551,7 +551,7 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mdt"; + firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn"; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 525b42832bd333e3e7ccb0efceb41b47347beab5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:00 +0200 Subject: dt-bindings: clock: Add Qcom QCM2290 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,qcm2290-gpucc.yaml | 77 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 +++++++++ 2 files changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,qcm2290-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 000000000000..734880805c1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required CX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h new file mode 100644 index 000000000000..7c76dd05278f --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_GFX3D_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GFX3D_CLK 8 +#define GPU_CC_GX_GFX3D_CLK_SRC 9 +#define GPU_CC_PLL0 10 +#define GPU_CC_SLEEP_CLK 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif -- cgit v1.2.3-58-ga151 From 4faeef52c8e69f4fa43bd572049b502175fc55c3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:03 +0200 Subject: arm64: dts: qcom: qcm2290: Add GPU nodes Describe the GPU hardware on the QCM2290. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-4-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 154 ++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index e1d176b277ce..8f3be4c75db3 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -758,6 +759,11 @@ reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; }; pmu@1b8e300 { @@ -1425,6 +1431,154 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-07000200", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 1>, + <&adreno_smmu 2 0>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ + opp-1123200000 { + opp-hz = /bits/ 64 <1123200000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&rpmpd_opp_turbo>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-921600000 { + opp-hz = /bits/ 64 <921600000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x7>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-peak-kBps = <3879000>; + opp-supported-hw = <0xf>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <2929000>; + opp-supported-hw = <0xf>; + }; + + opp-355200000 { + opp-hz = /bits/ 64 <355200000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <1720000>; + opp-supported-hw = <0xf>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,qcm2290-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; -- cgit v1.2.3-58-ga151 From 1ae60a51d175f5d43e2020a1c3f11346796ae6de Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:04 +0200 Subject: arm64: dts: qcom: qrb2210-rb1: Enable the GPU Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol). [1] https://docs.qualcomm.com/bundle/publicresource/87-61720-1_REV_A_QUALCOMM_ROBOTICS_RB1_PLATFORM__QUALCOMM_QRB2210__PRODUCT_BRIEF.pdf Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-5-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 8c27d52139a1..e19790464a11 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -210,6 +210,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; + }; +}; + &i2c2_gpio { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3-58-ga151 From f55a758fd355c1b5ed7c73434a99ae07d5741226 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sun, 9 Jun 2024 10:02:45 +0000 Subject: arm64: dts: qcom: msm8916-acer-a1-724: Add sound and modem Enable sound and modem for Acer Iconia Talk S A1-724. The setup is similar to most MSM8916 devices, i.e.: - QDSP6 audio - Earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240609100243.834169-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index b32c7a97394d..b4ce14a79370 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" #include #include @@ -135,6 +136,17 @@ status = "okay"; }; +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x4500000>; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <150 237 450 500 590>; + qcom,mbhc-vthreshold-high = <150 237 450 500 590>; + qcom,hphl-jack-type-normally-open; +}; + &pm8916_resin { linux,code = ; status = "okay"; @@ -170,6 +182,20 @@ status = "okay"; }; +&sound { + model = "acer-a1-724"; + audio-routing = + "DMIC1", "MIC BIAS External1", + "DMIC1", "Digital Mic1", + "AMIC2", "MIC BIAS Internal2", + "DMIC2", "MIC BIAS External1", + "DMIC2", "Digital Mic2"; + + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default &pri_mi2s_mclk_default &cdc_dmic_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep &pri_mi2s_mclk_sleep &cdc_dmic_sleep>; + pinctrl-names = "default", "sleep"; +}; + &usb { extcon = <&usb_id>, <&usb_id>; status = "okay"; -- cgit v1.2.3-58-ga151 From 5756101babc5334a9bc99601d1cc0d6776fa9ada Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sun, 9 Jun 2024 13:05:43 +0200 Subject: ARM: dts: qcom: motorola-falcon: add accelerometer, magnetometer Add the accelerometer and magnetometer that are present on the Motorola Moto G (2013) device. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/ZmWMh6fuLasvGkR/@standask-GA-A55M-S2HP Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index 029e1b1659c9..5dbca83f2230 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -96,6 +96,35 @@ }; }; +&blsp1_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak8963"; + reg = <0xc>; + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8226_l19>; + vid-supply = <&pm8226_lvs1>; + pinctrl-0 = <&mag_int_default &mag_reset_default>; + pinctrl-names = "default"; + }; + + accelerometer@19 { + compatible = "st,lis3dh-accel"; + reg = <0x19>; + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + st,drdy-int-pin = <1>; + }; +}; + &blsp1_i2c3 { status = "okay"; @@ -321,6 +350,30 @@ }; &tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_int_default: mag-int-default-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + reg_lcd_default: reg-lcd-default-state { pins = "gpio31", "gpio33"; function = "gpio"; -- cgit v1.2.3-58-ga151 From b82feb3a56e25919d6729b98c8152d950045fc5b Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 12 Jun 2024 13:38:26 -0500 Subject: arm64: dts: ti: k3-am642-sk: Add power supply temperature sensors The SK-AM64 board has two TMP100 temperature sensors, add these here. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240612183826.121856-1-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 5b028b3a3192..44ecbcf1c844 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -430,6 +430,18 @@ #gpio-cells = <2>; gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; }; + + /* SoC power supply temperature */ + tmp100@48 { + compatible = "ti,tmp100"; + reg = <0x48>; + }; + + /* DDR power supply temperature */ + tmp100@49 { + compatible = "ti,tmp100"; + reg = <0x49>; + }; }; /* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ -- cgit v1.2.3-58-ga151 From f560da940e3271166a19c17bfe8bcb45490d7767 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 9 May 2024 13:14:57 +0800 Subject: arm64: dts: imx8mp: Initialize audio PLLs from audiomix subsystem Initialize audio PLL1 as the parent clock for 8kHz series rates, audio PLL2 as the parent clock for 11kHz series rates. that PLL1 and PLL2 can together support full range of audio sample rates. Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index b92abb5a5c53..459c4a54d30e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1579,6 +1579,9 @@ "sai1", "sai2", "sai3", "sai5", "sai6", "sai7"; power-domains = <&pgc_audio>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; }; }; -- cgit v1.2.3-58-ga151 From 521568faa8a252c12341f13b2fd6cc95e48c0503 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 9 May 2024 13:14:58 +0800 Subject: arm64: dts: imx8mp-evk: add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 4a23c5373052..c2c708c492c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -133,6 +133,11 @@ regulator-max-microvolt = <3300000>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "wm8960-audio"; @@ -164,6 +169,25 @@ }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-hdmi { compatible = "fsl,imx-audio-hdmi"; model = "audio-hdmi"; @@ -627,6 +651,17 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -899,6 +934,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 -- cgit v1.2.3-58-ga151 From 245838888dbf3ebaff762e3424a18e35b681afc2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:34 +0200 Subject: ARM: dts: imx: align panel timings node name with dtschema DT schema expects panel timings node to follow certain pattern, dtbs_check warnings: imx6dl-gw54xx.dtb: display-timings: 'hsd100pxn1' does not match any of the regexes: '^timing', 'pinctrl-[0-9]+' Linux drivers do not care about node name, so this should not have effect on Linux. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx51-babbage.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts | 14 +++++++------- arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts | 6 +++--- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi | 16 ++++++++-------- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi | 16 ++++++++-------- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 14 +++++++------- 19 files changed, 47 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts index b61d55ca1467..f72e109342bc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts @@ -25,7 +25,7 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { - lw700 { + timing0: timing-lw700 { native-mode; clock-frequency = <33000033>; hactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index 16ff543f3fbf..f4a47e8348b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -89,7 +89,7 @@ status = "disabled"; display-timings { native-mode = <&timing1>; - timing1: claawvga { + timing1: timing-claawvga { clock-frequency = <27000000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 2bd0761c7e90..87a34cbdf233 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -58,7 +58,7 @@ pinctrl-0 = <&pinctrl_lcd>; display-timings { - 800x480p60 { + timing0: timing-800x480p60 { native-mode; clock-frequency = <30066000>; hactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts index 1353d985969c..f0f92ee7ba95 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -17,7 +17,7 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { - 800x480p60 { + timing0: timing-800x480p60 { native-mode; clock-frequency = <31500000>; hactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts index a7f77527269d..a02d77bb5672 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts @@ -67,7 +67,7 @@ }; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -83,7 +83,7 @@ pixelclk-active = <0>; }; - ETV570 { + timing-etc570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -99,7 +99,7 @@ pixelclk-active = <0>; }; - ET0350 { + timing-et0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -115,7 +115,7 @@ pixelclk-active = <0>; }; - ET0430 { + timing-et0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -131,7 +131,7 @@ pixelclk-active = <1>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -147,7 +147,7 @@ pixelclk-active = <0>; }; - ET0700 { /* same as ET0500 */ + timing-et0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -163,7 +163,7 @@ pixelclk-active = <0>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts index 6cdf2082c742..e10c179dbdb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts @@ -191,7 +191,7 @@ display-timings { native-mode = <&lvds0_timing0>; - lvds0_timing0: hsd100pxn1 { + lvds0_timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -207,7 +207,7 @@ pixelclk-active = <1>; }; - lvds0_timing1: nl12880bc20 { + lvds0_timing1: timing-nl12880bc20 { clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; @@ -233,7 +233,7 @@ display-timings { native-mode = <&lvds1_timing0>; - lvds1_timing0: hsd100pxn1 { + lvds1_timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts index dfa6f64d43cc..c75606fc4abd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -85,7 +85,7 @@ power-on-delay = <10>; display-timings { - 480x800p57 { + timing0: timing-480x800p57 { native-mode; clock-frequency = <27000027>; hactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts index a5ac79346854..0d86927819c2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts @@ -36,7 +36,7 @@ status = "okay"; display-timings { - 480x800p60 { + timing0: timing-480x800p60 { native-mode; clock-frequency = <30000000>; hactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts index 5a25bdbbeb68..66271daf97d9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts @@ -25,7 +25,7 @@ status = "okay"; display-timings { - 800x480p60 { + timing0: timing-800x480p60 { native-mode; clock-frequency = <33246000>; hactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index 48ffb3ee01bd..082a2e3a391f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -485,7 +485,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index 1eae438fbdae..8ec442038ea0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -482,7 +482,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index c2ec8572c8a5..9df9f79affae 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -529,7 +529,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index 7cee983da669..7693f92195d5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -584,7 +584,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index fbc704c064b6..9d0836df0fed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -486,7 +486,7 @@ display-timings { native-mode = <&timing0>; - timing0: g101evn010 { + timing0: timing-g101evn010 { clock-frequency = <68930000>; hactive = <1280>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 070506279186..f4cb9e1d34a9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -551,7 +551,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index 6656e2e762a1..0a3deaf92eea 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -786,7 +786,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi index 79f2354886b7..7ae495bdc48f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi @@ -110,7 +110,7 @@ }; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -126,7 +126,7 @@ pixelclk-active = <0>; }; - ETV570 { + timing-etv570 { u-boot,panel-name = "edt,et057090dhu"; clock-frequency = <25200000>; hactive = <640>; @@ -143,7 +143,7 @@ pixelclk-active = <0>; }; - ET0350 { + timing-et0350 { u-boot,panel-name = "edt,et0350g0dh6"; clock-frequency = <6413760>; hactive = <320>; @@ -160,7 +160,7 @@ pixelclk-active = <0>; }; - ET0430 { + timing-et0430 { u-boot,panel-name = "edt,et0430g0dh6"; clock-frequency = <9009000>; hactive = <480>; @@ -177,7 +177,7 @@ pixelclk-active = <1>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -193,7 +193,7 @@ pixelclk-active = <0>; }; - ET0700 { /* same as ET0500 */ + timing-et0700 { /* same as ET0500 */ u-boot,panel-name = "edt,etm0700g0dh6"; clock-frequency = <33264000>; hactive = <800>; @@ -210,7 +210,7 @@ pixelclk-active = <0>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; @@ -226,7 +226,7 @@ pixelclk-active = <0>; }; - CoMTFT { /* same as ET0700 but with inverted pixel clock */ + timing-comtft { /* same as ET0700 but with inverted pixel clock */ u-boot,panel-name = "edt,etm0700g0edh6"; clock-frequency = <33264000>; hactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi index 2ca2eb37e14f..dfbdbb87aec4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi @@ -127,7 +127,7 @@ }; display-timings { - hsd100pxn1 { + timing-hsd100pxn1 { u-boot,panel-name = "hannstar,hsd100pxn1"; clock-frequency = <65000000>; hactive = <1024>; @@ -142,7 +142,7 @@ pixelclk-active = <1>; }; - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -158,7 +158,7 @@ pixelclk-active = <0>; }; - nl12880bc20 { + timing-nl12880bc20 { u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; clock-frequency = <71000000>; hactive = <1280>; @@ -175,7 +175,7 @@ pixelclk-active = <1>; }; - ET0700 { + timing-et0700 { u-boot,panel-name = "edt,etm0700g0dh6"; clock-frequency = <33264000>; hactive = <800>; @@ -192,7 +192,7 @@ pixelclk-active = <0>; }; - ETV570 { + timing-etv570 { u-boot,panel-name = "edt,et057090dhu"; clock-frequency = <25200000>; hactive = <640>; @@ -224,7 +224,7 @@ }; display-timings { - hsd100pxn1 { + timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -238,7 +238,7 @@ pixelclk-active = <1>; }; - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -254,7 +254,7 @@ pixelclk-active = <0>; }; - nl12880bc20 { + timing-nl12880bc20 { clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 1db146ac1c17..864173e30709 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -405,7 +405,7 @@ status = "okay"; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -421,7 +421,7 @@ pixelclk-active = <1>; }; - ETV570 { + timing-etv570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -437,7 +437,7 @@ pixelclk-active = <1>; }; - ET0350 { + timing-et0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -453,7 +453,7 @@ pixelclk-active = <1>; }; - ET0430 { + timing-et0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -469,7 +469,7 @@ pixelclk-active = <0>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -485,7 +485,7 @@ pixelclk-active = <1>; }; - ET0700 { /* same as ET0500 */ + timing-et0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -501,7 +501,7 @@ pixelclk-active = <1>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; -- cgit v1.2.3-58-ga151 From 069e81ea96bdff4e771df4a644fbcf4913261e9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:35 +0200 Subject: ARM: dts: imx: correct choice of panel native mode Bindings and Linux driver expect native-mode to be a phandle to one of the timings node, not a boolean property. Correct the DTS to fix dtbs_check warnings like: imx53-m53evk.dtb: display-timings: timing-800x480p60: 'native-mode' does not match any of the regexes: 'pinctrl-[0-9]+' This should not have actual effect for Linux kernel (no real bug affecting choice of native-mode), because the first timing node is chosen in absence of proper native-mode property. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts index f72e109342bc..de6b7607510a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts @@ -25,8 +25,8 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { + native-mode = <&timing0>; timing0: timing-lw700 { - native-mode; clock-frequency = <33000033>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 87a34cbdf233..079bd3d14999 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -58,8 +58,8 @@ pinctrl-0 = <&pinctrl_lcd>; display-timings { + native-mode = <&timing0>; timing0: timing-800x480p60 { - native-mode; clock-frequency = <30066000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts index f0f92ee7ba95..ba0c62994f75 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -17,8 +17,8 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { + native-mode = <&timing0>; timing0: timing-800x480p60 { - native-mode; clock-frequency = <31500000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts index c75606fc4abd..ec806b8d503a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -85,8 +85,8 @@ power-on-delay = <10>; display-timings { + native-mode = <&timing0>; timing0: timing-480x800p57 { - native-mode; clock-frequency = <27000027>; hactive = <480>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts index 0d86927819c2..9ec038f1d0ff 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts @@ -36,8 +36,8 @@ status = "okay"; display-timings { + native-mode = <&timing0>; timing0: timing-480x800p60 { - native-mode; clock-frequency = <30000000>; hactive = <480>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts index 66271daf97d9..b3129832f471 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts @@ -25,8 +25,8 @@ status = "okay"; display-timings { + native-mode = <&timing0>; timing0: timing-800x480p60 { - native-mode; clock-frequency = <33246000>; hactive = <800>; vactive = <480>; -- cgit v1.2.3-58-ga151 From 04ee7d2d72c399d084ca9326f4808f952d1630b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:36 +0200 Subject: ARM: dts: imx6dl-aristainetos2_4: drop redundant 'power-on-delay' property LG4573 panel bindings do not allow 'power-on-delay' property. Linux driver does not use it, either. Reported by dtbs_check: imx6dl-aristainetos2_4.dtb: display@0: Unevaluated properties are not allowed ('power-on-delay' was unexpected) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts index ec806b8d503a..c9b2ea2b24b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -82,7 +82,6 @@ compatible = "lg,lg4573"; spi-max-frequency = <10000000>; reg = <0>; - power-on-delay = <10>; display-timings { native-mode = <&timing0>; -- cgit v1.2.3-58-ga151 From 63da595d80499728b33eda30110cee6ab431451e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:37 +0200 Subject: ARM: dts: imx: drop redundant 'u-boot,panel-name' property Panel timing bindings do not allow 'u-boot,panel-name' and there seems to be no users of it: neither Linux kernel drivers, nor U-boot as of v2024.07-rc2. Reported by dtbs_check: imx6qp-tx6qp-8037.dtb: display-timings: timing-et0700: 'u-boot,panel-name' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi | 5 ----- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi | 4 ---- 2 files changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi index 7ae495bdc48f..ded241a39906 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi @@ -127,7 +127,6 @@ }; timing-etv570 { - u-boot,panel-name = "edt,et057090dhu"; clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -144,7 +143,6 @@ }; timing-et0350 { - u-boot,panel-name = "edt,et0350g0dh6"; clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -161,7 +159,6 @@ }; timing-et0430 { - u-boot,panel-name = "edt,et0430g0dh6"; clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -194,7 +191,6 @@ }; timing-et0700 { /* same as ET0500 */ - u-boot,panel-name = "edt,etm0700g0dh6"; clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -227,7 +223,6 @@ }; timing-comtft { /* same as ET0700 but with inverted pixel clock */ - u-boot,panel-name = "edt,etm0700g0edh6"; clock-frequency = <33264000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi index dfbdbb87aec4..4eb53d5677a6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi @@ -128,7 +128,6 @@ display-timings { timing-hsd100pxn1 { - u-boot,panel-name = "hannstar,hsd100pxn1"; clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -159,7 +158,6 @@ }; timing-nl12880bc20 { - u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; @@ -176,7 +174,6 @@ }; timing-et0700 { - u-boot,panel-name = "edt,etm0700g0dh6"; clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -193,7 +190,6 @@ }; timing-etv570 { - u-boot,panel-name = "edt,et057090dhu"; clock-frequency = <25200000>; hactive = <640>; vactive = <480>; -- cgit v1.2.3-58-ga151 From 331929bd9edbf2217563e441be7e5748834b62ba Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:38 +0200 Subject: ARM: dts: imx28-tx28: drop redundant 'panel-name' property Panel timing bindings do not allow 'panel-name' and there seems to be no users of it: neither Linux kernel drivers, nor U-boot as of v2024.07-rc2. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts index 5485fe118dc4..d38183edf0fd 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -323,7 +323,6 @@ display-timings { native-mode = <&timing5>; timing0: timing0 { - panel-name = "VGA"; clock-frequency = <25175000>; hactive = <640>; vactive = <480>; @@ -340,7 +339,6 @@ }; timing1: timing1 { - panel-name = "ETV570"; clock-frequency = <25175000>; hactive = <640>; vactive = <480>; @@ -357,7 +355,6 @@ }; timing2: timing2 { - panel-name = "ET0350"; clock-frequency = <6500000>; hactive = <320>; vactive = <240>; @@ -374,7 +371,6 @@ }; timing3: timing3 { - panel-name = "ET0430"; clock-frequency = <9000000>; hactive = <480>; vactive = <272>; @@ -391,7 +387,6 @@ }; timing4: timing4 { - panel-name = "ET0500", "ET0700"; clock-frequency = <33260000>; hactive = <800>; vactive = <480>; @@ -408,7 +403,6 @@ }; timing5: timing5 { - panel-name = "ETQ570"; clock-frequency = <6400000>; hactive = <320>; vactive = <240>; -- cgit v1.2.3-58-ga151 From 11af40dc13f328c76648e16b8c8a6902b35bbd8c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 May 2024 03:06:42 +0200 Subject: arm64: dts: imx8mp: Enable HDMI on i.MX8MP DHCOM PDK2 and PDK3 Enable HDMI output on i.MX8MP DHCOM PDK2 and PDK3. The I2C5 on PDK2 and I2C mux port 1 on PDK3 respectively are used in regular I2C mode instead of HDMI DDC mode to permit connection of other I2C devices on those buses. The pinctrl_hdmi node is part of the SoM DTSI already. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 39 ++++++++++++++++++++++ .../arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 39 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 3b1c940860e0..ebdf13e97b4e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -69,6 +69,18 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "X38"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + led { compatible = "gpio-leds"; @@ -184,6 +196,33 @@ status = "okay"; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + &pcie_phy { clock-names = "ref"; clocks = <&hsio_blk_ctrl>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index ac7ec7533a3c..ef012e8365b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -75,6 +75,18 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "X28"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + led { compatible = "gpio-leds"; @@ -248,6 +260,33 @@ status = "okay"; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + ddc-i2c-bus = <&i2cmuxed1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + &pcie_phy { clocks = <&pcieclk 1>; clock-names = "ref"; -- cgit v1.2.3-58-ga151 From c5234fcd508ac90719c69b759102ee220bb68f6e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 16 May 2024 13:23:43 +0200 Subject: arm64: dts: imx8mp-tqma8mpql-mba8mpxl: Remove unused ocram node This node is unused and origins from downstream kernel where it is used for the DSP. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index c51ed7d991d1..ae64731266f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -222,11 +222,6 @@ #size-cells = <2>; ranges; - ocram: ocram@900000 { - no-map; - reg = <0 0x900000 0 0x70000>; - }; - /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; -- cgit v1.2.3-58-ga151 From f0504cca44f0bcc6c0699a247c38bdb9d5437542 Mon Sep 17 00:00:00 2001 From: Guido Günther Date: Mon, 20 May 2024 12:57:05 +0200 Subject: arm64: dts: imx8mq-librem5: Don't wake up on volume key press MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only key that should wake up the phone is power button press. This prevents accidental wakeup due to e.g. pressing the buttons in the pocket or backpack and is in line what userspace uses to unblank the device. Signed-off-by: Guido Günther Reviewed-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index ffb5fe61630d..1b39514d5c12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -45,7 +45,6 @@ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; - wakeup-source; }; key-vol-up { @@ -53,7 +52,6 @@ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; - wakeup-source; }; }; -- cgit v1.2.3-58-ga151 From 2cd7b542c84e19e92f0283809e7e8617481e8c32 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 May 2024 16:41:31 -0400 Subject: arm64: dts: freescale: ls1028a: Remove undocumented 'fsl,ls-pcie-ep' Remove the undocumented compatible string 'fsl,ls-pcie-ep' property from the ls1028a device tree source to fix DTB_CHECK warnings. arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb: pcie-ep@3400000: compatible: ['fsl,ls1028a-pcie-ep', 'fsl,ls-pcie-ep'] is too long from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 70b8731029c4..bac7a7b8b5a9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -674,7 +674,7 @@ }; pcie_ep1: pcie-ep@3400000 { - compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + compatible = "fsl,ls1028a-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000 0x80 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; @@ -713,7 +713,7 @@ }; pcie_ep2: pcie-ep@3500000 { - compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + compatible = "fsl,ls1028a-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000 0x88 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; -- cgit v1.2.3-58-ga151 From 044786935ec5f051c4bd1baef7831dd4bfb5ad52 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 May 2024 16:41:32 -0400 Subject: arm64: dts: freescale: ls1028a: Reorder sai dma-names to fix warning Reorder the SAI dma-names to ensure "rx" precedes "tx" as required to fixes the DTB_CHECK warning. arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb: audio-controller@f100000: dma-names:1: 'tx' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,sai.yaml# arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb: audio-controller@f110000: dma-names:1: 'tx' was expected Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 36 +++++++++++++------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index bac7a7b8b5a9..2eae0e358429 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -902,9 +902,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 4>, - <&edma0 1 3>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 3>, + <&edma0 1 4>; fsl,sai-asynchronous; status = "disabled"; }; @@ -923,9 +923,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 6>, - <&edma0 1 5>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 5>, + <&edma0 1 6>; fsl,sai-asynchronous; status = "disabled"; }; @@ -944,9 +944,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 8>, - <&edma0 1 7>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 7>, + <&edma0 1 8>; fsl,sai-asynchronous; status = "disabled"; }; @@ -965,9 +965,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 10>, - <&edma0 1 9>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 9>, + <&edma0 1 10>; fsl,sai-asynchronous; status = "disabled"; }; @@ -986,9 +986,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 12>, - <&edma0 1 11>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 11>, + <&edma0 1 12>; fsl,sai-asynchronous; status = "disabled"; }; @@ -1007,9 +1007,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 14>, - <&edma0 1 13>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 13>, + <&edma0 1 14>; fsl,sai-asynchronous; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From bd036febd03cb40b56911f057e3dacabd1521014 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 May 2024 00:22:02 +0200 Subject: ARM: dts: imx: Add LVDS port data mapping on M53 Menlo Describe LVDS data mapping of the LVDS-to-DPI decoder input port. This fixes a warning reported by lvds-codec driver: " lvds-codec lvds-decoder: missing 'data-mapping' DT property " Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 4d77b6077fc1..558751e730f3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -64,6 +64,7 @@ reg = <0>; lvds_decoder_in: endpoint { + data-mapping = "jeida-18"; remote-endpoint = <&lvds0_out>; }; }; -- cgit v1.2.3-58-ga151 From 7872f905b246982296d7833fe820f4ba5862cefb Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 11 Jun 2024 17:07:59 +0100 Subject: arm64: dts: exynos: gs101: reorder properties as per guidelines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * 'interrupts' & 'cpus' & 'clocks' are standard/common properties as per the Devicetree Sources (DTS) Coding Style and therefore should be sorted alphabetically within the standard/common section * vendor properties should be last * reg / ranges should be 2nd/3rd (after compatible) * status should be last Do so. Note: I've left the cpus{} node untouched to keep the grouping of relatedd properties. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240611-gs101-dts-cleanup-v1-1-877358cd6536@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 2 +- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 5e8ffe065081..b10bde2ec716 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -131,9 +131,9 @@ }; &usbdrd31 { - status = "okay"; vdd10-supply = <®_placeholder>; vdd33-supply = <®_placeholder>; + status = "okay"; }; &usbdrd31_dwc3 { diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a66e996666b8..eadb8822e6d4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -213,9 +213,9 @@ pmu-3 { compatible = "arm,dsu-pmu"; - interrupts = ; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + interrupts = ; }; psci { @@ -288,6 +288,8 @@ compatible = "google,gs101-mct", "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; interrupts = , , , @@ -300,17 +302,15 @@ , , ; - clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; - clock-names = "fin_pll", "mct"; }; watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>; - interrupts = ; clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, <&ext_24_5m>; clock-names = "watchdog", "watchdog_src"; + interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; status = "disabled"; @@ -319,10 +319,10 @@ watchdog_cl1: watchdog@10070000 { compatible = "google,gs101-wdt"; reg = <0x10070000 0x100>; - interrupts = ; clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, <&ext_24_5m>; clock-names = "watchdog", "watchdog_src"; + interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; status = "disabled"; @@ -776,12 +776,12 @@ compatible = "google,gs101-hsi2c", "samsung,exynosautov9-hsi2c"; reg = <0x10970000 0xc0>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; pinctrl-0 = <&hsi2c8_bus>; pinctrl-names = "default"; status = "disabled"; @@ -831,10 +831,10 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - interrupts = ; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + interrupts = ; pinctrl-0 = <&uart0_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; @@ -1157,12 +1157,12 @@ compatible = "google,gs101-hsi2c", "samsung,exynosautov9-hsi2c"; reg = <0x10d50000 0xc0>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; pinctrl-0 = <&hsi2c12_bus>; pinctrl-names = "default"; status = "disabled"; @@ -1277,13 +1277,14 @@ <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; - samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; }; usbdrd31: usb@11110000 { compatible = "google,gs101-dwusb3"; + ranges = <0x0 0x11110000 0x10000>; clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, @@ -1291,14 +1292,13 @@ clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x11110000 0x10000>; status = "disabled"; usbdrd31_dwc3: usb@0 { compatible = "snps,dwc3"; + reg = <0x0 0x10000>; clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; clock-names = "ref"; - reg = <0x0 0x10000>; interrupts = ; phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; phy-names = "usb2-phy", "usb3-phy"; -- cgit v1.2.3-58-ga151 From 0ce551af516a8d7361b7254ce5c742380f68284c Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Sat, 25 May 2024 22:48:53 +0530 Subject: arm64: dts: phygate-tauri-l: enable pcie phy I210 intel ethernet controller is connected to PCIe. Enable the PHY to use the ethernet controller. Signed-off-by: Parthiban Nallathambi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index 27a902569e2a..ba6ce3c7f477 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -7,6 +7,7 @@ #include #include +#include #include "imx8mm-phycore-som.dtsi" / { @@ -185,6 +186,15 @@ status = "okay"; }; +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; -- cgit v1.2.3-58-ga151 From 8d97083c0b5dda658621b769add0a5392fb88dcd Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Sat, 25 May 2024 22:48:54 +0530 Subject: arm64: dts: phygate-tauri-l: add overlays for RS232 and RS485 UART2 and UART4 can used in following combination, 2 x RS232: - UART2 and UART4 without flow control - MUX selection GPIO3_20 must be held low 1 x RS232 + 1 x RS485: - UART2 - RS232 - UART4 - RS485 - MUX selection GPIO3_20 must be held high - RE/DE for RS485 controlled with GPIO3_25 1 x RS232 with flow control: - UART2 - RS232 - MUX selection GPIO3_20 must be held low Signed-off-by: Parthiban Nallathambi Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++ .../imx8mm-phygate-tauri-l-rs232-rs232.dtso | 72 ++++++++++++++++++++ .../imx8mm-phygate-tauri-l-rs232-rs485.dtso | 76 ++++++++++++++++++++++ .../imx8mm-phygate-tauri-l-rs232-rts-cts.dtso | 41 ++++++++++++ 4 files changed, 197 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1b1e4db02071..eaa27649c28d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -266,6 +266,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb +imx8mm-phygate-tauri-l-rs232-rs232-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs232.dtbo +imx8mm-phygate-tauri-l-rs232-cts-rts-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rts-cts.dtbo +imx8mm-phygate-tauri-l-rs232-rs485-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs485.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs232.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-cts-rts.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb + dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso new file mode 100644 index 000000000000..bf3e04651ba0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Jens Lang + * + * Tauri-L 2 x RS232: + * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive) + */ + +#include +#include +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "phytec,imx8mm-phygate-tauri-l"; + +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrcl-0 = <&pinctrl_gpio3_hog>; + + uart4_rs485_en { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "uart4_rs485_en"; + }; +}; + +/* UART2 - RS232 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +/* UART4 - RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio3_hog: gpio3hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso new file mode 100644 index 000000000000..f4448cde0407 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Jens Lang + * + * Tauri-L RS232 + RS485: + * - GPIO3_20 uart4_rs485_en needs to be driven high (active) + * - GPIO3_25 RS485_DE Driver enable + */ + +#include +#include +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "phytec,imx8mm-phygate-tauri-l"; + +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrcl-0 = <&pinctrl_gpio3_hog>; + + uart4_rs485_en { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "uart4_rs485_en"; + }; +}; + +/* UART2 - RS232 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +/* UART4 - RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio3_hog: gpio3hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso new file mode 100644 index 000000000000..107f743fbb1c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Jens Lang + * + * Tauri-L RS232 with RTS/CTS hardware flow control: + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "phytec,imx8mm-phygate-tauri-l"; + +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00 + MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00 + >; + }; +}; -- cgit v1.2.3-58-ga151 From 85f2d113103660c2635e4b7ffb11fef15af433f1 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 27 May 2024 18:03:45 +0200 Subject: arm64: dts: freescale: imx8mm-verdin: don't limit i2c2 max. clock Verdin I2C2 may be used to access other I2C devices apart from serving as an HDMI DDC channel. Thus do not limit the used I2C clock frequency to 10kHz in the module specific device tree part. If an overlay configures i2c2 as DDC the overlay is also responsible to cope with an appropriate I2C clock. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 4768b05fd765..82bbcec525d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -547,7 +547,7 @@ /* Verdin I2C_2_DSI */ &i2c2 { - clock-frequency = <10000>; + clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; -- cgit v1.2.3-58-ga151 From 1232f98d27e25bb4b937de8b2605a155d26299b2 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 27 May 2024 18:03:46 +0200 Subject: arm64: dts: freescale: imx8mp-verdin: don't limit i2c2 max. clock Verdin I2C2 may be used to access other I2C devices apart from serving as an HDMI DDC channel. Thus do not limit the used I2C clock frequency to 10kHz in the module specific device tree part. If an overlay configures i2c2 as DDC the overlay is also responsible to cope with an appropriate I2C clock. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index aef4bef4bccd..3c6b47edd4c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -650,8 +650,7 @@ /* Verdin I2C_2_DSI */ &i2c2 { - /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ - clock-frequency = <10000>; + clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; -- cgit v1.2.3-58-ga151 From a27f49644fb4dfd010f7c8707fa58172803684cb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 28 May 2024 09:11:41 +0200 Subject: arm64: dts: imx8mp: Add imx8mp-specific irqsteer compatible i.MX8MP irqsteer has power-domain support, so use a dedicated compatible. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 459c4a54d30e..f25fc7a8358f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1949,7 +1949,7 @@ }; irqsteer_hdmi: interrupt-controller@32fc2000 { - compatible = "fsl,imx-irqsteer"; + compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; reg = <0x32fc2000 0x1000>; interrupts = ; interrupt-controller; -- cgit v1.2.3-58-ga151 From 9ebd81f0c73b40568749cc3ae52e3c644a3e10e4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 31 May 2024 17:50:14 -0400 Subject: arm64: dts: ls1012a: Reorder sai dma-names to clean up DTB_CHECK warning Change order of sai's dma-names to clearn up below DTB_CHECK warning. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: sai@2b50000: dma-names:1: 'tx' was expected arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: sai@2b60000: dma-names:1: 'tx' was expected Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index a0f7bbd691a0..454b61fa0e05 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -449,9 +449,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 46>, + <&edma0 1 47>; status = "disabled"; }; @@ -469,9 +469,9 @@ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 44>, + <&edma0 1 45>; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 67edf1eb1c4b6ad496f2714cb43140c19d241f9c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 31 May 2024 17:50:15 -0400 Subject: arm64: dts: ls1043a: Change I2C clock name to ipg to fix DTB_CHECK warning dt_binding require I2C's clock name is "ipg". Change it to "ipg" from "i2c" to fix below DTB_CHECK warning. arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: i2c@2190000: clock-names:0: 'ipg' was expecte Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 8ee6d8c0ef61..a4a476b04ebe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -533,7 +533,7 @@ #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 0x4>; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; dmas = <&edma0 1 38>, @@ -548,7 +548,7 @@ #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 0x4>; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -561,7 +561,7 @@ #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = <0 58 0x4>; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -574,7 +574,7 @@ #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; interrupts = <0 59 0x4>; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -- cgit v1.2.3-58-ga151 From 2c4c29b66908165a4772bcfe99d8250c2c8b26ed Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 31 May 2024 17:50:16 -0400 Subject: arm64: dts: ls208xa: Change I2C clock name to ipg to fix DTB_CHECK warning dt_binding require I2C's clock name is "ipg". Change it to "ipg" from "i2c" to fix below DTB_CHECK warning. arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dtb: i2c@2000000: clock-names:0: 'ipg' was expected Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index ccba0a135b24..9064e6de7d10 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1004,7 +1004,7 @@ #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; }; @@ -1016,7 +1016,7 @@ #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; }; @@ -1028,7 +1028,7 @@ #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; }; @@ -1040,7 +1040,7 @@ #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; }; -- cgit v1.2.3-58-ga151 From 81ad3889ba237bfd0adbd0fc61d9c2dfd2ffa956 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 31 May 2024 17:50:17 -0400 Subject: arm64: dts: ls2160a: Change I2C clock name to ipg to fix DTB_CHECK warning dt_binding require I2C's clock name is "ipg". Change it to "ipg" from "i2c" to fix below DTB_CHECK warning. arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dtb: i2c@2010000: clock-names:0: 'ipg' was expected Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 96055593204a..7dc98cb0ffc9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -745,7 +745,7 @@ #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -761,7 +761,7 @@ #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -777,7 +777,7 @@ #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -793,7 +793,7 @@ #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -809,7 +809,7 @@ #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -825,7 +825,7 @@ #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -841,7 +841,7 @@ #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; @@ -857,7 +857,7 @@ #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; + clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; -- cgit v1.2.3-58-ga151 From 23ea56ef2288d27a1673e62c7c513d9265f97e90 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 1 Jun 2024 08:52:29 -0500 Subject: arm64: dts: imx8mp-beacon-kit: Fix errors found from CHECK_DTBS The adv7535 has some unnecessary entries which can be removed since they were not setup properly anyway and the defaults work just fine. Removing them and adding some required regulators make the errors detected from CHECK_DTBS go away: reg-names:1: 'edid' was expected reg-names:2: 'cec' was expected 'avdd-supply' is a required property 'dvdd-supply' is a required property 'pvdd-supply' is a required property 'a2vdd-supply' is a required property 'v3p3-supply' is a required property Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index da836172ae46..17e2c19d8455 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -302,12 +302,18 @@ adv_bridge: hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + reg-names = "main"; interrupt-parent = <&gpio4>; interrupts = <27 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; #sound-dai-cells = <0>; + avdd-supply = <&buck5>; + dvdd-supply = <&buck5>; + pvdd-supply = <&buck5>; + a2vdd-supply = <&buck5>; + v1p2-supply = <&buck5>; + v3p3-supply = <&buck4>; ports { #address-cells = <1>; -- cgit v1.2.3-58-ga151 From 152f7a9908b11ff55f3feb357a5f6ff84f90e69b Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Tue, 4 Jun 2024 08:27:22 +0200 Subject: arm64: dts: ls1028a-rdb: Add EEPROM nodes to I2C bus The LS1028ARDB board contains three EEPROM devices, for storing boot code, DDR SPD and board information. Add the missing entries to the devicetree. Signed-off-by: Mike Looijmans Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index ecd2c1ea177f..757a34ba7da3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -201,6 +201,37 @@ #address-cells = <1>; #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + /* Atmel AT24C512C-XHD­B: 64 KB EEPROM */ + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* AT24C04C 512-byte DDR4 SPD EEPROM */ + /* Documentation says 0x51, but must be even and i2cdetect says 0x52 */ + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* Atmel AT24C02C-XHM­B: 256-byte EEPROM */ + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + i2c@1 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-58-ga151 From 7cedaa390bfb9b8b92a2a65f1eef6e312168e4eb Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 4 Jun 2024 16:22:48 +0200 Subject: dt-bindings: Drop Li Yang as maintainer for all bindings Remove Li Yang from all device tree bindings because mails to this address are bouncing. Commit fbdd90334a62 ("MAINTAINERS: Drop Li Yang as their email address stopped working") already removed the entry from the MAINTAINERS but didn't address all the in-file entries of the device tree bindings. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 - .../devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml | 1 - Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 1 - Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml | 1 - 4 files changed, 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..281f3dc71cc3 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -8,7 +8,6 @@ title: Freescale i.MX Platforms maintainers: - Shawn Guo - - Li Yang properties: $nodename: diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml index 887e565b9573..199b34fdbefc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape External Interrupt Controller maintainers: - Shawn Guo - - Li Yang description: | Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA, diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml index ce1a6505eb51..3fb0534ea597 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Device Configuration Unit maintainers: - Shawn Guo - - Li Yang description: | DCFG is the device configuration unit, that provides general purpose diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml index a6a511b00a12..2a456c8af992 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Supplemental Configuration Unit maintainers: - Shawn Guo - - Li Yang description: | SCFG is the supplemental configuration unit, that provides SoC specific -- cgit v1.2.3-58-ga151 From 3a5297c5071055c31f268c123289488a6ec47a3e Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 5 Jun 2024 10:39:50 +0200 Subject: ARM: dts: e60k02: fix aliases for mmc Since commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") mmc numbering are changed, confusing boot scripts. Fix that by adding proper aliases Signed-off-by: Andreas Kemnade Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/e60k02.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi index 13756d39fb7b..0029c12f16c8 100644 --- a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -14,6 +14,10 @@ #include / { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; chosen { stdout-path = &uart1; -- cgit v1.2.3-58-ga151 From 0943d92ca4a376bdd42cbf883c47a1405010d777 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 17:30:18 +0200 Subject: arm64: dts: freescale: use defines for interrupts Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 54 +++++----- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 108 ++++++++++---------- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 48 ++++----- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 136 ++++++++++++------------- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 +- 9 files changed, 181 insertions(+), 181 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 454b61fa0e05..7651d134e0f7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -74,15 +74,15 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + interrupts = ,/* Physical Secure PPI */ + ,/* Physical Non-Secure PPI */ + ,/* Virtual PPI */ + ;/* Hypervisor PPI */ }; pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; gic: interrupt-controller@1400000 { @@ -93,7 +93,7 @@ <0x0 0x1402000 0 0x2000>, /* GICC */ <0x0 0x1404000 0 0x2000>, /* GICH */ <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; reboot { @@ -159,7 +159,7 @@ esdhc0: esdhc@1560000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; voltage-ranges = <1800 1800 3300 3300>; @@ -178,7 +178,7 @@ esdhc1: esdhc@1580000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1580000 0x0 0x10000>; - interrupts = <0 65 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; voltage-ranges = <1800 1800 3300 3300>; @@ -305,7 +305,7 @@ tmu: tmu@1f00000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; fsl,tmu-calibration = <0x00000000 0x00000025>, @@ -355,7 +355,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; scl-gpios = <&gpio0 2 0>; @@ -367,7 +367,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; scl-gpios = <&gpio0 13 0>; @@ -379,7 +379,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clock-names = "dspi"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -391,7 +391,7 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; @@ -400,7 +400,7 @@ duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; status = "disabled"; @@ -409,7 +409,7 @@ gpio0: gpio@2300000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -419,7 +419,7 @@ gpio1: gpio@2310000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -430,7 +430,7 @@ compatible = "fsl,ls1012a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; big-endian; }; @@ -439,7 +439,7 @@ #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -459,7 +459,7 @@ #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -481,8 +481,8 @@ reg = <0x0 0x2c00000 0x0 0x10000>, <0x0 0x2c10000 0x0 0x10000>, <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, - <0 103 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "edma-tx", "edma-err"; dma-channels = <32>; big-endian; @@ -496,7 +496,7 @@ usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -509,7 +509,7 @@ reg = <0x0 0x3200000 0x0 0x10000>, <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; dma-coherent; @@ -519,7 +519,7 @@ usb1: usb@8600000 { compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = <0 139 0x4>; + interrupts = ; dr_mode = "host"; phy_type = "ulpi"; }; @@ -528,7 +528,7 @@ compatible = "fsl,ls1012a-msi"; reg = <0x0 0x1572000 0x0 0x8>; msi-controller; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pcie1: pcie@3400000 { @@ -536,8 +536,8 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ + interrupts = , /* controller interrupt */ + ; /* PME interrupt */ interrupt-names = "aer", "pme"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 2eae0e358429..6f7e84558d38 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -859,8 +859,8 @@ malidp0: display@f080000 { compatible = "arm,mali-dp500"; reg = <0x0 0xf080000 0x0 0x10000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 223 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "DE", "SE"; clocks = <&dpclk>, <&clockgen QORIQ_CLK_HWACCEL 2>, @@ -1024,7 +1024,7 @@ tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; fsl,tmu-calibration = <0x00000000 0x00000024>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index a4a476b04ebe..3625456d574e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -268,19 +268,19 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, /* Physical Secure PPI */ - <1 14 0xf08>, /* Physical Non-Secure PPI */ - <1 11 0xf08>, /* Virtual PPI */ - <1 10 0xf08>; /* Hypervisor PPI */ + interrupts = , + , + , + ; fsl,erratum-a008585; }; pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = <0 106 0x4>, - <0 107 0x4>, - <0 95 0x4>, - <0 97 0x4>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -295,7 +295,7 @@ <0x0 0x1402000 0 0x2000>, /* GICC */ <0x0 0x1404000 0 0x2000>, /* GICH */ <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 0xf08>; + interrupts = ; }; soc: soc { @@ -352,7 +352,7 @@ #size-cells = <1>; ranges = <0x0 0x00 0x1700000 0x100000>; reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = <0 75 0x4>; + interrupts = ; dma-coherent; sec_jr0: jr@10000 { @@ -360,7 +360,7 @@ "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x10000 0x10000>; - interrupts = <0 71 0x4>; + interrupts = ; }; sec_jr1: jr@20000 { @@ -368,7 +368,7 @@ "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x20000 0x10000>; - interrupts = <0 72 0x4>; + interrupts = ; }; sec_jr2: jr@30000 { @@ -376,7 +376,7 @@ "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x30000 0x10000>; - interrupts = <0 73 0x4>; + interrupts = ; }; sec_jr3: jr@40000 { @@ -384,7 +384,7 @@ "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x40000 0x10000>; - interrupts = <0 74 0x4>; + interrupts = ; }; }; @@ -405,7 +405,7 @@ ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = <0 43 0x4>; + interrupts = ; }; qspi: spi@1550000 { @@ -415,7 +415,7 @@ reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x4000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 99 0x4>; + interrupts = ; clock-names = "qspi_en", "qspi"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>, @@ -427,7 +427,7 @@ esdhc: esdhc@1560000 { compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; + interrupts = ; clock-frequency = <0>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; @@ -438,14 +438,14 @@ ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 144 0x4>; + interrupts = ; big-endian; }; tmu: tmu@1f00000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = <0x00000000 0x00000023>, @@ -518,7 +518,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 0x4>; + interrupts = ; clock-names = "dspi"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -532,7 +532,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 0x4>; + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -547,7 +547,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 0x4>; + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -560,7 +560,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = <0 58 0x4>; + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -573,7 +573,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = <0 59 0x4>; + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; @@ -584,7 +584,7 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; }; @@ -592,7 +592,7 @@ duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; }; @@ -600,7 +600,7 @@ duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = <0 55 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; }; @@ -608,7 +608,7 @@ duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = <0 55 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; }; @@ -616,7 +616,7 @@ gpio1: gpio@2300000 { compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 0x4>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -626,7 +626,7 @@ gpio2: gpio@2310000 { compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 0x4>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -636,7 +636,7 @@ gpio3: gpio@2320000 { compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 68 0x4>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -646,7 +646,7 @@ gpio4: gpio@2330000 { compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 134 0x4>; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -721,7 +721,7 @@ lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = <0 48 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg"; status = "disabled"; @@ -730,7 +730,7 @@ lpuart1: serial@2960000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = <0 49 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; @@ -740,7 +740,7 @@ lpuart2: serial@2970000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = <0 50 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; @@ -750,7 +750,7 @@ lpuart3: serial@2980000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = <0 51 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; @@ -760,7 +760,7 @@ lpuart4: serial@2990000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = <0 52 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; @@ -770,7 +770,7 @@ lpuart5: serial@29a0000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = <0 53 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "ipg"; @@ -780,7 +780,7 @@ wdog0: watchdog@2ad0000 { compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 0x4>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; clock-names = "wdog"; @@ -793,8 +793,8 @@ reg = <0x0 0x2c00000 0x0 0x10000>, <0x0 0x2c10000 0x0 0x10000>, <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 0x4>, - <0 103 0x4>; + interrupts = , + ; interrupt-names = "edma-tx", "edma-err"; dma-channels = <32>; big-endian; @@ -815,7 +815,7 @@ usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -827,7 +827,7 @@ usb1: usb@3000000 { compatible = "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -839,7 +839,7 @@ usb2: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -853,7 +853,7 @@ reg = <0x0 0x3200000 0x0 0x10000>, <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; dma-coherent; @@ -864,21 +864,21 @@ compatible = "fsl,ls1043a-msi"; reg = <0x0 0x1571000 0x0 0x8>; msi-controller; - interrupts = <0 116 0x4>; + interrupts = ; }; msi2: msi-controller2@1572000 { compatible = "fsl,ls1043a-msi"; reg = <0x0 0x1572000 0x0 0x8>; msi-controller; - interrupts = <0 126 0x4>; + interrupts = ; }; msi3: msi-controller3@1573000 { compatible = "fsl,ls1043a-msi"; reg = <0x0 0x1573000 0x0 0x8>; msi-controller; - interrupts = <0 160 0x4>; + interrupts = ; }; pcie1: pcie@3400000 { @@ -886,8 +886,8 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 118 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; @@ -913,8 +913,8 @@ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>, - <0 128 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; @@ -940,8 +940,8 @@ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 754a64be739c..e5fcfc690ffc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -441,7 +441,7 @@ tmu: tmu@1f00000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 604bf88d70b3..91589b907ec8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -118,7 +118,7 @@ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <2>; #size-cells = <2>; ranges; @@ -183,10 +183,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + interrupts = ,/* Physical Secure PPI */ + ,/* Physical Non-Secure PPI */ + ,/* Virtual PPI */ + ;/* Hypervisor PPI */ }; pmu { @@ -280,7 +280,7 @@ tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ @@ -347,7 +347,7 @@ reg = <0x0 0x21c0500 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; status = "disabled"; }; @@ -356,14 +356,14 @@ reg = <0x0 0x21c0600 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; status = "disabled"; }; gpio0: gpio@2300000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; little-endian; gpio-controller; #gpio-cells = <2>; @@ -374,7 +374,7 @@ gpio1: gpio@2310000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; little-endian; gpio-controller; #gpio-cells = <2>; @@ -385,7 +385,7 @@ gpio2: gpio@2320000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; little-endian; gpio-controller; #gpio-cells = <2>; @@ -396,7 +396,7 @@ gpio3: gpio@2330000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; little-endian; gpio-controller; #gpio-cells = <2>; @@ -407,7 +407,7 @@ ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; little-endian; #address-cells = <2>; #size-cells = <1>; @@ -419,7 +419,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; @@ -430,7 +430,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; @@ -441,7 +441,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; @@ -452,7 +452,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; @@ -477,7 +477,7 @@ esdhc: esdhc@2140000 { compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ + interrupts = ; clock-frequency = <0>; clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; @@ -490,7 +490,7 @@ usb0: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -501,7 +501,7 @@ usb1: usb@3110000 { compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -514,7 +514,7 @@ reg = <0x0 0x3200000 0x0 0x10000>, <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; dma-coherent; @@ -565,7 +565,7 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupts = ; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; @@ -604,7 +604,7 @@ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupts = ; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; @@ -642,7 +642,7 @@ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupts = ; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 8352197cea6f..e9bc1f4fa13c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -15,7 +15,7 @@ / { pmu { compatible = "arm,cortex-a57-pmu"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 245bbd615c81..60c422560e33 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -15,7 +15,7 @@ / { pmu { compatible = "arm,cortex-a72-pmu"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 9064e6de7d10..5ea4ef349a88 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -58,7 +58,7 @@ #size-cells = <2>; ranges; interrupt-controller; - interrupts = <1 9 0x4>; + interrupts = ; its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; @@ -314,7 +314,7 @@ tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; + interrupts = ; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; fsl,tmu-calibration = <0x00000000 0x00000026>, @@ -362,7 +362,7 @@ reg = <0x0 0x21c0500 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 0x4>; /* Level high type */ + interrupts = ; }; serial1: serial@21c0600 { @@ -370,7 +370,7 @@ reg = <0x0 0x21c0600 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 0x4>; /* Level high type */ + interrupts = ; }; serial2: serial@21d0500 { @@ -378,7 +378,7 @@ reg = <0x0 0x21d0500 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 33 0x4>; /* Level high type */ + interrupts = ; }; serial3: serial@21d0600 { @@ -386,7 +386,7 @@ reg = <0x0 0x21d0600 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 33 0x4>; /* Level high type */ + interrupts = ; }; cluster1_core0_watchdog: wdt@c000000 { @@ -883,48 +883,48 @@ #iommu-cells = <1>; stream-match-mask = <0x7C00>; dma-coherent; - interrupts = <0 13 4>, /* global secure fault */ - <0 14 4>, /* combined secure interrupt */ - <0 15 4>, /* global non-secure fault */ - <0 16 4>, /* combined non-secure interrupt */ + interrupts = , /* global secure fault */ + , /* combined secure interrupt */ + , /* global non-secure fault */ + , /* combined non-secure interrupt */ /* performance counter interrupts 0-7 */ - <0 211 4>, <0 212 4>, - <0 213 4>, <0 214 4>, - <0 215 4>, <0 216 4>, - <0 217 4>, <0 218 4>, + , , + , , + , , + , , /* per context interrupt, 64 interrupts */ - <0 146 4>, <0 147 4>, - <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, - <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, - <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, - <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, - <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, - <0 168 4>, <0 169 4>, - <0 170 4>, <0 171 4>, - <0 172 4>, <0 173 4>, - <0 174 4>, <0 175 4>, - <0 176 4>, <0 177 4>, - <0 178 4>, <0 179 4>, - <0 180 4>, <0 181 4>, - <0 182 4>, <0 183 4>, - <0 184 4>, <0 185 4>, - <0 186 4>, <0 187 4>, - <0 188 4>, <0 189 4>, - <0 190 4>, <0 191 4>, - <0 192 4>, <0 193 4>, - <0 194 4>, <0 195 4>, - <0 196 4>, <0 197 4>, - <0 198 4>, <0 199 4>, - <0 200 4>, <0 201 4>, - <0 202 4>, <0 203 4>, - <0 204 4>, <0 205 4>, - <0 206 4>, <0 207 4>, - <0 208 4>, <0 209 4>; + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; }; dspi: spi@2100000 { @@ -933,7 +933,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; clock-names = "dspi"; @@ -944,7 +944,7 @@ status = "disabled"; compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; voltage-ranges = <1800 1800 3300 3300>; @@ -956,7 +956,7 @@ gpio0: gpio@2300000 { compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ + interrupts = ; gpio-controller; little-endian; #gpio-cells = <2>; @@ -967,7 +967,7 @@ gpio1: gpio@2310000 { compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ + interrupts = ; gpio-controller; little-endian; #gpio-cells = <2>; @@ -978,7 +978,7 @@ gpio2: gpio@2320000 { compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ + interrupts = ; gpio-controller; little-endian; #gpio-cells = <2>; @@ -989,7 +989,7 @@ gpio3: gpio@2330000 { compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ + interrupts = ; gpio-controller; little-endian; #gpio-cells = <2>; @@ -1003,7 +1003,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; @@ -1015,7 +1015,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; @@ -1027,7 +1027,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; @@ -1039,7 +1039,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ + interrupts = ; clock-names = "ipg"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; @@ -1048,7 +1048,7 @@ ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ + interrupts = ; little-endian; #address-cells = <2>; #size-cells = <1>; @@ -1077,7 +1077,7 @@ pcie1: pcie@3400000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ + interrupts = ; interrupt-names = "intr"; #address-cells = <3>; #size-cells = <2>; @@ -1099,7 +1099,7 @@ pcie2: pcie@3500000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ + interrupts = ; interrupt-names = "intr"; #address-cells = <3>; #size-cells = <2>; @@ -1121,7 +1121,7 @@ pcie3: pcie@3600000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ + interrupts = ; interrupt-names = "intr"; #address-cells = <3>; #size-cells = <2>; @@ -1143,7 +1143,7 @@ pcie4: pcie@3700000 { compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ + interrupts = ; interrupt-names = "intr"; #address-cells = <3>; #size-cells = <2>; @@ -1166,7 +1166,7 @@ status = "disabled"; compatible = "fsl,ls2080a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>; - interrupts = <0 133 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; dma-coherent; @@ -1176,7 +1176,7 @@ status = "disabled"; compatible = "fsl,ls2080a-ahci"; reg = <0x0 0x3210000 0x0 0x10000>; - interrupts = <0 136 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; dma-coherent; @@ -1192,7 +1192,7 @@ usb0: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -1203,7 +1203,7 @@ usb1: usb@3110000 { compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ + interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; @@ -1215,7 +1215,7 @@ ccn@4000000 { compatible = "arm,ccn-504"; reg = <0x0 0x04000000 0x0 0x01000000>; - interrupts = <0 12 4>; + interrupts = ; }; rcpm: power-controller@1e34040 { @@ -1236,14 +1236,14 @@ ddr1: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 17 0x4>; + interrupts = ; little-endian; }; ddr2: memory-controller@1090000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1090000 0x0 0x1000>; - interrupts = <0 18 0x4>; + interrupts = ; little-endian; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 7dc98cb0ffc9..38723508abd0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -928,7 +928,7 @@ esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; dma-coherent; @@ -942,7 +942,7 @@ esdhc1: esdhc@2150000 { compatible = "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <0 63 0x4>; /* Level high type */ + interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; dma-coherent; -- cgit v1.2.3-58-ga151 From 645e59e613974eb2b415b92c172ab2b8f6c3d5bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 17:30:19 +0200 Subject: arm64: dts: ls208xa: use defines for timer interrupts Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. The comment was saying interrupt was active low, but the actual used value was active high, so assume that the code, not the comment, is correct. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 5ea4ef349a88..61c5c2e034e6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -241,10 +241,10 @@ timer: timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ - <1 14 4>, /* Physical Non-Secure PPI, active-low */ - <1 11 4>, /* Virtual PPI, active-low */ - <1 10 4>; /* Hypervisor PPI, active-low */ + interrupts = , /* Physical Secure PPI */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hypervisor PPI */ }; psci { -- cgit v1.2.3-58-ga151 From 1d8a9f043a770d0b278581ae87fb7c98471f4996 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 17:30:20 +0200 Subject: arm64: dts: imx8: use defines for interrupts Replace hard-coded interrupt flags with standard defines for readability. No changes in resulting DTBs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 90d1901df2b1..930e14fec423 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -400,7 +400,7 @@ pinctrl-0 = <&pinctrl_typec1>; reg = <0x50>; interrupt-parent = <&gpio2>; - interrupts = <11 8>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; status = "okay"; typec1_con: connector { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index c024be33fbcc..6d002fc1b2be 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -193,7 +193,7 @@ compatible = "isil,isl29023"; reg = <0x44>; interrupt-parent = <&lsio_gpio4>; - interrupts = <11 2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; }; pressure-sensor@60 { -- cgit v1.2.3-58-ga151 From 4880ee1c9046c88c7cadea5d8bc20bc51d79662b Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Tue, 11 Jun 2024 00:42:38 +0100 Subject: arm64: dts: imx8mp-debix-model-a: Enable HDMI output Enable the HDMI output on the Debix Model A SBC, using the HDMI encoder present in the i.MX8MP SoC. This has been tested with a generic 1080p HDMI display, along with a smaller 1280x800 HDMI display. Signed-off-by: Christopher Obbard Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-debix-model-a.dts | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 9b8f97a84e61..af02af9e5334 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -20,6 +20,18 @@ stdout-path = &uart2; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -94,6 +106,28 @@ }; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -239,6 +273,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -356,6 +394,15 @@ >; }; + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 -- cgit v1.2.3-58-ga151 From 62814204c6aebe0b5a71f3ee7360e08a8b60e275 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 10 Jun 2024 16:10:01 +0200 Subject: arm64: dts: freescale: imx8mp-verdin: add HDMI support Enable HDMI output on Verdin iMX8MP on all the supported carrier boards (dev, dahlia, mallow and yavia). HDMI DDC I2C is used in regular I2C mode, see link on the related dt-bindings patch. Fix CEC and HPD pinctrl, having a pull-down on HPD and a pull-up on CEC. Link: https://lore.kernel.org/all/20240515062753.111746-1-marex@denx.de/ Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 37 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 37 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mp-verdin-mallow.dtsi | 37 ++++++++++++++++++++++ .../boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi | 3 +- .../boot/dts/freescale/imx8mp-verdin-wifi.dtsi | 3 +- .../boot/dts/freescale/imx8mp-verdin-yavia.dtsi | 37 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 13 ++++++-- 7 files changed, 160 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 6e6b9c2c4640..fbcd93e33aea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -4,6 +4,18 @@ */ / { + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "X21"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&codec_dai>; @@ -94,6 +106,27 @@ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; }; +/* Verdin HDMI_1 */ +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; @@ -139,6 +172,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { vpcie-supply = <®_pcie>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index 42ed44a11711..09733fea036d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -4,6 +4,18 @@ */ / { + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "X37"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + reg_eth2phy: regulator-eth2phy { compatible = "regulator-fixed"; enable-active-high; @@ -103,6 +115,27 @@ vcc-supply = <®_1p8v>; }; +/* Verdin HDMI_1 */ +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; @@ -141,6 +174,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 1d15f7449c58..3a40338cf2d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -11,6 +11,18 @@ #include / { + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "X14"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +103,27 @@ status = "okay"; }; +/* Verdin HDMI_1 */ +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + /* Temperature sensor on Mallow */ &hwmon_temp { compatible = "ti,tmp1075"; @@ -117,6 +150,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi index 91d597391b7c..2ee91f31e7f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi @@ -41,8 +41,7 @@ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, - <&pinctrl_hdmi_hog>; + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; }; /* diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi index ef94f9a57e20..efcab00c0142 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -55,8 +55,7 @@ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, - <&pinctrl_hdmi_hog>; + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>; }; /* On-module Bluetooth */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index a7b261ff3e4c..533b7fe218ce 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -6,6 +6,18 @@ #include / { + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "J15"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + /* Carrier Board Supply +V1.8 */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -105,6 +117,27 @@ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; }; +/* Verdin HDMI_1 */ +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &hwmon_temp { status = "okay"; }; @@ -127,6 +160,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 3c6b47edd4c1..c96e74684e03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -457,6 +457,13 @@ "SODIMM_44"; }; +/* Verdin HDMI_1 */ +&hdmi_tx { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; + /* On-module I2C */ &i2c1 { clock-frequency = <400000>; @@ -1116,10 +1123,10 @@ ; /* SODIMM 252 */ }; - pinctrl_hdmi_hog: hdmihoggrp { + pinctrl_hdmi: hdmigrp { fsl,pins = - , /* SODIMM 63 */ - ; /* SODIMM 61 */ + , /* SODIMM 63 */ + ; /* SODIMM 61 */ }; /* On-module I2C */ -- cgit v1.2.3-58-ga151 From be3216d626774412d15fed1ab0d3ef916c0e5acb Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Wed, 12 Jun 2024 12:17:27 +0200 Subject: arm64: dts: imx8mp-msc-sm2s: Add HDMI output Enable the HDMI output of the MSC SM2-MB-EP1 carrier board based the SM2S-IMX8PLUS SMARC module. Signed-off-by: Luca Ceresoli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts index da4b1807c275..83194ea7cb81 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -46,6 +46,24 @@ }; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + &i2c1 { sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; @@ -92,6 +110,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_smarc_gpio>; + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 -- cgit v1.2.3-58-ga151 From caed3b59419989b624566cdfcc2049bb1d435b70 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 13 Jun 2024 10:32:07 -0400 Subject: arm64: dts: layerscape: Change node name from 'esdhc' to 'mmc' Use common node name 'mmc' to fix DTB_CHECK warning. Add compatible string 'fsl,ls2080a-esdhc' for fsl-lx2160a. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: esdhc@1560000: $nodename:0: 'esdhc@1560000' does not match '^mmc(@.*)?$' arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: esdhc@1560000: $nodename:0: 'esdhc@1560000' does not match '^mmc(@.*)?$' arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dtb: esdhc@1560000: $nodename:0: 'esdhc@1560000' does not match '^mmc(@.*)?$' arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dtb: esdhc@2140000: $nodename:0: 'esdhc@2140000' does not match '^mmc(@.*)?$' arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dtb: esdhc@2140000: $nodename:0: 'esdhc@2140000' does not match '^mmc(@.*)?$' arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dtb: esdhc@2140000: compatible:0: 'fsl,esdhc' is not one of ['fsl,mpc8536-esdhc', 'fsl,mpc8378-esdhc', 'fsl,p2020-esdhc', 'fsl,p4080-esdhc', 'fsl,t1040-esdhc', 'fsl,t4240-esdhc', 'fsl,ls1012a-esdhc', 'fsl,ls1028a-esdhc', 'fsl,ls1088a-esdhc', 'fsl,ls1043a-esdhc', 'fsl,ls1046a-esdhc', 'fsl,ls2080a-esdhc'] from schema $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml# arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dtb: esdhc@2140000: $nodename:0: 'esdhc@2140000' does not match '^mmc(@.*)?$' Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++---- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 7651d134e0f7..b2658fb759df 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -156,7 +156,7 @@ status = "disabled"; }; - esdhc0: esdhc@1560000 { + esdhc0: mmc@1560000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; @@ -175,7 +175,7 @@ big-endian; }; - esdhc1: esdhc@1580000 { + esdhc1: mmc@1580000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1580000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 3625456d574e..8d82e9519863 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -424,7 +424,7 @@ status = "disabled"; }; - esdhc: esdhc@1560000 { + esdhc: mmc@1560000 { compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index e5fcfc690ffc..30061c80f1cc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -308,7 +308,7 @@ status = "disabled"; }; - esdhc: esdhc@1560000 { + esdhc: mmc@1560000 { compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 91589b907ec8..8df016154e66 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -474,7 +474,7 @@ status = "disabled"; }; - esdhc: esdhc@2140000 { + esdhc: mmc@2140000 { compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 61c5c2e034e6..7f957971e5e2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -940,7 +940,7 @@ spi-num-chipselects = <5>; }; - esdhc: esdhc@2140000 { + esdhc: mmc@2140000 { status = "disabled"; compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 38723508abd0..a2625411c31e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -925,8 +925,8 @@ status = "disabled"; }; - esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; + esdhc0: mmc@2140000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -939,8 +939,8 @@ status = "disabled"; }; - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; + esdhc1: mmc@2150000 { + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL -- cgit v1.2.3-58-ga151 From 5bf0e05cd1d717a3dd8395b0cc80f11cd9f483d0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 13 Jun 2024 18:24:12 -0400 Subject: arm64: dts: layerscape: change thermal node name Add thermal subfix for thermal node name to fix DTB_CHECK warning: thermal-zones: '...' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$' Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 14 +++++++------- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 14 +++++++------- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 6f7e84558d38..96e7fd0c30c8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -155,7 +155,7 @@ }; thermal-zones { - ddr-controller { + ddr-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; @@ -175,7 +175,7 @@ }; }; - core-cluster { + core-cluster-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 8d82e9519863..2b9d77fe541b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -154,7 +154,7 @@ }; thermal-zones { - ddr-controller { + ddr-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; @@ -174,7 +174,7 @@ }; }; - serdes { + serdes-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; @@ -194,7 +194,7 @@ }; }; - fman { + fman-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 2>; @@ -214,7 +214,7 @@ }; }; - core-cluster { + core-cluster-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 3>; @@ -245,7 +245,7 @@ }; }; - sec { + sec-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 8df016154e66..336a6142d666 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -131,7 +131,7 @@ }; thermal-zones { - core-cluster { + core-cluster-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; @@ -166,7 +166,7 @@ }; }; - soc { + soc-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 7f957971e5e2..cfdc3e71aed1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -80,7 +80,7 @@ }; thermal-zones { - ddr-controller1 { + ddr-ctrl1-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; @@ -94,7 +94,7 @@ }; }; - ddr-controller2 { + ddr-ctrl2-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 2>; @@ -108,7 +108,7 @@ }; }; - ddr-controller3 { + ddr-ctrl3-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 3>; @@ -122,7 +122,7 @@ }; }; - core-cluster1 { + core-cluster1-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 4>; @@ -151,7 +151,7 @@ }; }; - core-cluster2 { + core-cluster2-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 5>; @@ -180,7 +180,7 @@ }; }; - core-cluster3 { + core-cluster3-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 6>; @@ -209,7 +209,7 @@ }; }; - core-cluster4 { + core-cluster4-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 7>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index a2625411c31e..e60fbe3e51dc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -449,7 +449,7 @@ }; thermal-zones { - cluster6-7 { + cluster6-7-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; @@ -492,7 +492,7 @@ }; }; - ddr-cluster5 { + ddr-cluster5-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; @@ -512,7 +512,7 @@ }; }; - wriop { + wriop-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 2>; @@ -532,7 +532,7 @@ }; }; - dce-qbman-hsio2 { + dce-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 3>; @@ -552,7 +552,7 @@ }; }; - ccn-dpaa-tbu { + ccn-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 4>; @@ -572,7 +572,7 @@ }; }; - cluster4-hsio3 { + cluster4-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 5>; @@ -592,7 +592,7 @@ }; }; - cluster2-3 { + cluster2-3-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 6>; -- cgit v1.2.3-58-ga151 From 469349d4c07fe7ca767fd9c09fec9d4dc999119f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 16 Jun 2024 14:21:49 -0300 Subject: arm64: dts: imx8mm-iot-gateway: Add initial support Add the initial support for the CompuLab i.MX8MM IoT Gateway board, which is based on the Compulab's UCM-iMX8M-Mini SoM. Board URL: https://www.compulab.com/products/iot-gateways/iot-gate-imx8-industrial-arm-iot-gateway/ SoM URL: https://www.compulab.com/products/computer-on-modules/ucm-imx8m-mini-nxp-i-mx-8m-mini-som-system-on-module-computer/ Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-iot-gateway.dts | 218 +++++++ arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi | 679 +++++++++++++++++++++ 3 files changed, 898 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index eaa27649c28d..fae82f75c46a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts new file mode 100644 index 000000000000..370558a8ba46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2020 CompuLab + +#include "imx8mm-ucm-som.dtsi" +#include +/ { + model = "CompuLab i.MX8MM IoT Gateway"; + compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm"; + + regulator-usbhub-ena { + compatible = "regulator-fixed"; + regulator-name = "usbhub_ena"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-usbhub-rst { + compatible = "regulator-fixed"; + regulator-name = "usbhub_rst"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-uart1-mode { + compatible = "regulator-fixed"; + regulator-name = "uart1_mode"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-uart1-duplex { + compatible = "regulator-fixed"; + regulator-name = "uart1_duplex"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-uart1-shdn { + compatible = "regulator-fixed"; + regulator-name = "uart1_shdn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-uart1-trmen { + compatible = "regulator-fixed"; + regulator-name = "uart1_trmen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 25 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + regulator-usdhc2-v { + compatible = "regulator-fixed"; + regulator-name = "usdhc2_v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-mpcie2-rst { + compatible = "regulator-fixed"; + regulator-name = "mpcie2_rst"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-mpcie2lora-dis { + compatible = "regulator-fixed"; + regulator-name = "mpcie2lora_dis"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + pcie0_refclk: clock-pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + usb-role-switch; + status = "okay"; + + usbhub@1 { + compatible = "usb424,9514"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb9514>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + mmc-ddr-1_8v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* mPCIe2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x140 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140 + >; + }; + + pinctrl_usb9514: usb9514grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x140 /* USB_PS_EN */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 /* HUB_RSTn */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi new file mode 100644 index 000000000000..d3b21203c5f4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi @@ -0,0 +1,679 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2018 CompuLab + +/dts-v1/; + +#include "imx8mm.dtsi" +#include + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + mmc0 = &usdhc3; + }; + + chosen { + stdout-path = &uart3; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 3000000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <222>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + heartbeat-led { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + wlreg_on: regulator-wlreg-on { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlreg_on"; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-always-on; + status = "okay"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + regulator-usdhc3rst { + compatible = "regulator-fixed"; + regulator-name = "usdhc3_rst"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + }; + + regulator-fec1rst { + compatible = "regulator-fixed"; + regulator-name = "fec1_rst"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + enable-active-high; + startup-delay-us = <500>; + regulator-boot-on; + }; +}; + +&A53_0 { + arm-supply = <&buck2>; +}; + +&cpu_alert0 { + temperature = <105000>; +}; + +&cpu_crit0 { + temperature = <115000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + #clock-cells = <0>; + clocks = <&pmic_osc>; + clock-names = "osc"; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8: BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7: LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc_i2c: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_backlight>; + status = "okay"; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + fsl,sai-asynchronous; + status = "okay"; +}; + +&snvs { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "disabled"; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + max-speed = <3000000>; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + disable-over-current; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + hnp-disable; + srp-disable; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + non-removable; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + no-1-8-v; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x190 + >; + }; + + pinctrl_bt: bt0grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 /* BT_REG_ON */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 /* BT_DEV_WU */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 /* BT_HST_WU */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_pwm_backlight: pwmbacklightgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x03 + >; + }; + + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x00 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit v1.2.3-58-ga151 From 5e3cbb8e4256e3923abc8eb65205ff5dde0ac0d7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Jun 2024 10:56:36 +0800 Subject: arm64: dts: freescale: add i.MX95 basic dtsi i.MX95 features 6 A55 Cores, ARM Mali GPU, ISP, ML acceleration NPU, and Edgelock secure enclave security. This patch is to add a minimal dtsi, with cpu cores, scmi, gic, uart, mu, sdhc, lpi2c added. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-clock.h | 187 +++++ arch/arm64/boot/dts/freescale/imx95-pinfunc.h | 865 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx95-power.h | 47 ++ arch/arm64/boot/dts/freescale/imx95.dtsi | 1042 +++++++++++++++++++++++++ 4 files changed, 2141 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-clock.h create mode 100644 arch/arm64/boot/dts/freescale/imx95-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx95-power.h create mode 100644 arch/arm64/boot/dts/freescale/imx95.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h new file mode 100644 index 000000000000..e1f91203e794 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __CLOCK_IMX95_H +#define __CLOCK_IMX95_H + +/* The index should match i.MX95 SCMI Firmware */ +#define IMX95_CLK_32K 1 +#define IMX95_CLK_24M 2 +#define IMX95_CLK_FRO 3 +#define IMX95_CLK_SYSPLL1_VCO 4 +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX95_CLK_SYSPLL1_PFD0 6 +#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX95_CLK_SYSPLL1_PFD1 9 +#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX95_CLK_SYSPLL1_PFD2 12 +#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX95_CLK_AUDIOPLL1_VCO 14 +#define IMX95_CLK_AUDIOPLL1 15 +#define IMX95_CLK_AUDIOPLL2_VCO 16 +#define IMX95_CLK_AUDIOPLL2 17 +#define IMX95_CLK_VIDEOPLL1_VCO 18 +#define IMX95_CLK_VIDEOPLL1 19 +#define IMX95_CLK_RESERVED20 20 +#define IMX95_CLK_RESERVED21 21 +#define IMX95_CLK_RESERVED22 22 +#define IMX95_CLK_RESERVED23 23 +#define IMX95_CLK_ARMPLL_VCO 24 +#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX95_CLK_ARMPLL_PFD0 26 +#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX95_CLK_ARMPLL_PFD1 28 +#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX95_CLK_ARMPLL_PFD2 30 +#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX95_CLK_ARMPLL_PFD3 32 +#define IMX95_CLK_DRAMPLL_VCO 33 +#define IMX95_CLK_DRAMPLL 34 +#define IMX95_CLK_HSIOPLL_VCO 35 +#define IMX95_CLK_HSIOPLL 36 +#define IMX95_CLK_LDBPLL_VCO 37 +#define IMX95_CLK_LDBPLL 38 +#define IMX95_CLK_EXT1 39 +#define IMX95_CLK_EXT2 40 + +#define IMX95_CCM_NUM_CLK_SRC 41 + +#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) +#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) +#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) +#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) +#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) +#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) +#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) +#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) +#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) +#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) +#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) +#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) +#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) +#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) +#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) +#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) +#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) +#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) +#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) +#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) +#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) +#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) +#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) +#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) +#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) +#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) +#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) +#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) +#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) +#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) +#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) +#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) +#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) +#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) +#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) +#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) +#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) +#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) +#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) +#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) +#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) +#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) +#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) +#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) +#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) +#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) +#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) +#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) +#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) +#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) +#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) +#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) +#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) +#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) +#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) +#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) +#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) +#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) +#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) +#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) +#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) +#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) +#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) +#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) +#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) +#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) +#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) +#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) +#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) +#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) +#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) +#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) +#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) +#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) +#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) +#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) +#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) +#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) +#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) +#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) +#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) +#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) +#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) +#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) +#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) +#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) +#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) +#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) +#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) +#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) +#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) +#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) +#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) +#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) +#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) +#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) +#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) +#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) +#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) +#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) +#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) +#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) +#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) +#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) +#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) +#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) +#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) +#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) +#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) +#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) +#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) +#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) +#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) +#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) +#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) +#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) +#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) +#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) +#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) +#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) +#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) +#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) +#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) +#define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + 0) +#define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + 1) +#define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + 2) +#define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + 3) +#define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + 4) +#define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + 5) +#define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + 6) +#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) +#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) +#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) + +#endif /* __CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-pinfunc.h b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h new file mode 100644 index 000000000000..9f614eea7c86 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h @@ -0,0 +1,865 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DTS_IMX95_PINFUNC_H +#define __DTS_IMX95_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00 +#define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00 + +#define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x0004 0x0208 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0208 0x0000 0x06 0x00 + +#define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x020C 0x060C 0x00 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x0008 0x020C 0x044C 0x02 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x0008 0x020C 0x0460 0x04 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x0008 0x020C 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x020C 0x056C 0x06 0x00 + +#define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x0210 0x0000 0x00 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x0210 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x000C 0x0210 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x0210 0x0444 0x03 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x000C 0x0210 0x0464 0x04 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x000C 0x0210 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x0210 0x0574 0x06 0x00 + +#define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x0010 0x0214 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x0214 0x0504 0x11 0x00 +#define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0214 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0214 0x0574 0x05 0x01 +#define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0214 0x0514 0x16 0x00 +#define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x0010 0x0214 0x0468 0x07 0x00 + +#define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x0014 0x0218 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x0218 0x0500 0x11 0x00 +#define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0218 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0218 0x0570 0x05 0x01 +#define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0218 0x0510 0x16 0x00 +#define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x0014 0x0218 0x046C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x0018 0x021C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x021C 0x050C 0x11 0x00 +#define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x021C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x021C 0x056C 0x05 0x01 +#define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x021C 0x051C 0x16 0x00 +#define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x0018 0x021C 0x0470 0x07 0x00 + +#define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x001C 0x0220 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x0220 0x0508 0x11 0x00 +#define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x0220 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x0220 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x0220 0x0518 0x16 0x00 +#define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x001C 0x0220 0x0474 0x07 0x00 + +#define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x0020 0x0224 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0224 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0224 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO04__CAN4_TX 0x0020 0x0224 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0224 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0224 0x0580 0x05 0x01 +#define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0224 0x051C 0x16 0x01 +#define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x0020 0x0224 0x0478 0x07 0x00 + +#define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x0024 0x0228 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0228 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0024 0x0228 0x040C 0x02 0x01 +#define IMX95_PAD_GPIO_IO05__CAN4_RX 0x0024 0x0228 0x044C 0x03 0x01 +#define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0228 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0228 0x057C 0x05 0x01 +#define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0228 0x0518 0x16 0x01 +#define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x0024 0x0228 0x047C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x0028 0x022C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x022C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0028 0x022C 0x0410 0x02 0x01 +#define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x022C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x022C 0x0578 0x05 0x01 +#define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x022C 0x0524 0x16 0x00 +#define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x0028 0x022C 0x0480 0x07 0x00 + +#define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x002C 0x0230 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x0230 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x0230 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x0230 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x0230 0x0520 0x16 0x00 +#define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x002C 0x0230 0x0484 0x07 0x00 + +#define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x0030 0x0234 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0234 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0234 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0234 0x0588 0x05 0x01 +#define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0234 0x0524 0x16 0x01 +#define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x0030 0x0234 0x0488 0x07 0x00 + +#define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x0034 0x0238 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0238 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0238 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0238 0x0584 0x05 0x01 +#define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0238 0x0520 0x16 0x01 +#define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x0034 0x0238 0x048C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x0038 0x023C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x023C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x023C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x023C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x023C 0x052C 0x16 0x00 +#define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x0038 0x023C 0x0490 0x07 0x00 + +#define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x003C 0x0240 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x0240 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x0240 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x0240 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x0240 0x0528 0x16 0x00 +#define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x003C 0x0240 0x0494 0x07 0x00 + +#define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x0040 0x0244 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0244 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0040 0x0244 0x0414 0x02 0x00 +#define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x0040 0x0244 0x0498 0x03 0x00 +#define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0244 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0244 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0244 0x052C 0x16 0x01 +#define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x0244 0x0590 0x07 0x00 + +#define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x0044 0x0248 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0248 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x0044 0x0248 0x0418 0x02 0x00 +#define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0248 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0248 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0248 0x0528 0x16 0x01 +#define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x0044 0x0248 0x049C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x0048 0x024C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x024C 0x055C 0x01 0x01 +#define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x024C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x024C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x024C 0x0568 0x06 0x01 +#define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x0048 0x024C 0x04A0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x004C 0x0250 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x0250 0x0558 0x01 0x01 +#define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x0250 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x0250 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x0250 0x0564 0x06 0x01 +#define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x004C 0x0250 0x04A4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x0050 0x0254 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0254 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0050 0x0254 0x0414 0x02 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0254 0x0554 0x04 0x01 +#define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0254 0x0538 0x05 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0254 0x0560 0x06 0x01 +#define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x0050 0x0254 0x04A8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x0054 0x0258 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0258 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0258 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0258 0x0534 0x05 0x01 +#define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0258 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x0054 0x0258 0x04AC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x0058 0x025C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x025C 0x058C 0x01 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x025C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x025C 0x0530 0x05 0x01 +#define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x025C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x0058 0x025C 0x04B0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x005C 0x0260 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x0260 0x0590 0x01 0x01 +#define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x005C 0x0260 0x0418 0x02 0x01 +#define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x005C 0x0260 0x04B4 0x03 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x0260 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x0260 0x0540 0x05 0x01 +#define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x0260 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x005C 0x0260 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x0060 0x0264 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x0060 0x0264 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0060 0x0264 0x040C 0x02 0x02 +#define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0264 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0264 0x0544 0x05 0x01 +#define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0264 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x0060 0x0264 0x04B8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x0064 0x0268 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x0064 0x0268 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0268 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x0064 0x0268 0x04BC 0x03 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0268 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0268 0x053C 0x05 0x01 +#define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0268 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0268 0x058C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x0068 0x026C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x026C 0x05C8 0x01 0x00 +#define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x026C 0x0454 0x02 0x02 +#define IMX95_PAD_GPIO_IO22__CAN5_TX 0x0068 0x026C 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x026C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x026C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x026C 0x0514 0x16 0x01 +#define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x0068 0x026C 0x04C0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x006C 0x0270 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x0270 0x05CC 0x01 0x00 +#define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x0270 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO23__CAN5_RX 0x006C 0x0270 0x0450 0x03 0x00 +#define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x0270 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x0270 0x0510 0x16 0x01 +#define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x006C 0x0270 0x04C4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x0070 0x0274 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0274 0x05D0 0x01 0x00 +#define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0274 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0274 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0274 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x0070 0x0274 0x04C8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x0074 0x0278 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0278 0x05D4 0x01 0x00 +#define IMX95_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0278 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0278 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0278 0x060C 0x05 0x01 +#define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0278 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x0074 0x0278 0x04CC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x0078 0x027C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x027C 0x05D8 0x01 0x00 +#define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0078 0x027C 0x0410 0x02 0x02 +#define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x0078 0x027C 0x0458 0x03 0x01 +#define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x027C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x027C 0x0610 0x05 0x01 +#define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x027C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x027C 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x007C 0x0280 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x0280 0x05DC 0x01 0x00 +#define IMX95_PAD_GPIO_IO27__CAN2_RX 0x007C 0x0280 0x0444 0x02 0x02 +#define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x0280 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x0280 0x0614 0x05 0x01 +#define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x0280 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x007C 0x0280 0x045C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x0080 0x0284 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0284 0x0504 0x11 0x01 +#define IMX95_PAD_GPIO_IO28__CAN3_TX 0x0080 0x0284 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x0080 0x0284 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x0084 0x0288 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0288 0x0500 0x11 0x01 +#define IMX95_PAD_GPIO_IO29__CAN3_RX 0x0084 0x0288 0x0448 0x02 0x01 +#define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x0084 0x0288 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x0088 0x028C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x0088 0x028C 0x050C 0x11 0x01 +#define IMX95_PAD_GPIO_IO30__CAN5_TX 0x0088 0x028C 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x0088 0x028C 0x0460 0x07 0x01 + +#define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x008C 0x0290 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x008C 0x0290 0x0508 0x11 0x01 +#define IMX95_PAD_GPIO_IO31__CAN5_RX 0x008C 0x0290 0x0450 0x02 0x01 +#define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x008C 0x0290 0x0464 0x07 0x01 + +#define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x0090 0x0294 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x0294 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x0090 0x0294 0x0580 0x02 0x00 +#define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x0090 0x0294 0x0538 0x04 0x00 + +#define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x0094 0x0298 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x0094 0x0298 0x057C 0x02 0x00 +#define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x0094 0x0298 0x0534 0x04 0x00 + +#define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x0098 0x029C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x0098 0x029C 0x0578 0x02 0x00 +#define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x0098 0x029C 0x0530 0x04 0x00 + +#define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x009C 0x02A0 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x009C 0x02A0 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x009C 0x02A0 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x009C 0x02A0 0x0540 0x04 0x00 + +#define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00A0 0x02A4 0x0544 0x04 0x00 +#define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00A0 0x02A4 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00A0 0x02A4 0x0588 0x02 0x00 + +#define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00A4 0x02A8 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00A4 0x02A8 0x0584 0x02 0x00 +#define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00A4 0x02A8 0x053C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00A8 0x02AC 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00A8 0x02AC 0x0434 0x01 0x00 +#define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00A8 0x02AC 0x0458 0x04 0x00 +#define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00A8 0x02AC 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00AC 0x02B0 0x0000 0x05 0x00 +#define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00AC 0x02B0 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00AC 0x02B0 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00AC 0x02B0 0x045C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00B0 0x02B4 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00B0 0x02B4 0x0438 0x01 0x00 +#define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00B0 0x02B4 0x0000 0x02 0x00 +#define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00B0 0x02B4 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00B0 0x02B4 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00B4 0x02B8 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00B4 0x02B8 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00B4 0x02B8 0x0448 0x02 0x00 +#define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00B4 0x02B8 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00B4 0x02B8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00B8 0x02BC 0x0424 0x00 0x00 +#define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00B8 0x02BC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00B8 0x02BC 0x04F8 0x02 0x00 +#define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00B8 0x02BC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00B8 0x02BC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00B8 0x02BC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00BC 0x02C0 0x0428 0x00 0x00 +#define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00BC 0x02C0 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00BC 0x02C0 0x04FC 0x02 0x00 +#define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00BC 0x02C0 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00BC 0x02C0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00BC 0x02C0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00C0 0x02C4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00C0 0x02C4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00C0 0x02C4 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00C0 0x02C4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00C0 0x02C4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00C4 0x02C8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00C4 0x02C8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00C4 0x02C8 0x0444 0x02 0x01 +#define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00C4 0x02C8 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00C4 0x02C8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00C4 0x02C8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00C8 0x02CC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00C8 0x02CC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00C8 0x02CC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00C8 0x02CC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00C8 0x02CC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00C8 0x02CC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00C8 0x02CC 0x0000 0x06 0x00 +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00C8 0x02CC 0x0000 0x07 0x00 + +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00CC 0x02D0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00CC 0x02D0 0x055C 0x01 0x00 +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00CC 0x02D0 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00CC 0x02D0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00CC 0x02D0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00D0 0x02D4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00D0 0x02D4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00D0 0x02D4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00D0 0x02D4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00D0 0x02D4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00D4 0x02D8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00D4 0x02D8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00D4 0x02D8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00D4 0x02D8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00D8 0x02DC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00D8 0x02DC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00D8 0x02DC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00D8 0x02DC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00D8 0x02DC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00D8 0x02DC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00DC 0x02E0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00DC 0x02E0 0x042C 0x01 0x00 +#define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00DC 0x02E0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00DC 0x02E0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00E0 0x02E4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00E0 0x02E4 0x0558 0x01 0x00 +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00E0 0x02E4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00E0 0x02E4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00E0 0x02E4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00E4 0x02E8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00E4 0x02E8 0x0554 0x01 0x00 +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00E4 0x02E8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00E4 0x02E8 0x0548 0x03 0x00 +#define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00E4 0x02E8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00E4 0x02E8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00E8 0x02EC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00E8 0x02EC 0x042C 0x02 0x01 +#define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00E8 0x02EC 0x054C 0x03 0x00 +#define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00E8 0x02EC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00E8 0x02EC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00EC 0x02F0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00EC 0x02F0 0x0550 0x03 0x00 +#define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00EC 0x02F0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00EC 0x02F0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00F0 0x02F4 0x0424 0x00 0x01 +#define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00F0 0x02F4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00F0 0x02F4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00F0 0x02F4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00F0 0x02F4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00F4 0x02F8 0x0428 0x00 0x01 +#define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00F4 0x02F8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00F4 0x02F8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00F4 0x02F8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00F4 0x02F8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00F8 0x02FC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00F8 0x02FC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00F8 0x02FC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00F8 0x02FC 0x0000 0x00 0x00 + +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00FC 0x0300 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00FC 0x0300 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00FC 0x0300 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00FC 0x0300 0x05A4 0x03 0x00 +#define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00FC 0x0300 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00FC 0x0300 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x0100 0x0304 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x0100 0x0304 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x0100 0x0304 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x0100 0x0304 0x05A0 0x03 0x00 +#define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x0100 0x0304 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x0100 0x0304 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x0100 0x0304 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0104 0x0308 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x0104 0x0308 0x0568 0x01 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x0104 0x0308 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x0104 0x0308 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x0104 0x0308 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x0104 0x0308 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0104 0x0308 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0108 0x030C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x0108 0x030C 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0108 0x030C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0108 0x030C 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x0108 0x030C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x0108 0x030C 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x010C 0x0310 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x010C 0x0310 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x010C 0x0310 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x010C 0x0310 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x010C 0x0310 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x0110 0x0314 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x0110 0x0314 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x0110 0x0314 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x0110 0x0314 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x0110 0x0314 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x0110 0x0314 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0114 0x0318 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0114 0x0318 0x0430 0x01 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x0114 0x0318 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x0114 0x0318 0x059C 0x03 0x00 +#define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x0114 0x0318 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x0114 0x0318 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0118 0x031C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x0118 0x031C 0x0564 0x01 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x0118 0x031C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x0118 0x031C 0x0594 0x03 0x00 +#define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x0118 0x031C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x0118 0x031C 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0118 0x031C 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x011C 0x0320 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x011C 0x0320 0x0454 0x01 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x011C 0x0320 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x011C 0x0320 0x0598 0x03 0x00 +#define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x011C 0x0320 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x011C 0x0320 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x011C 0x0320 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x0120 0x0324 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x0120 0x0324 0x0560 0x01 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x0120 0x0324 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x0120 0x0324 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x0120 0x0324 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x0120 0x0324 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0120 0x0324 0x0430 0x06 0x01 + +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0124 0x0328 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x0124 0x0328 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x0124 0x0328 0x0454 0x02 0x01 +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0124 0x0328 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x0124 0x0328 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x0124 0x0328 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x0128 0x032C 0x0488 0x04 0x01 +#define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x0128 0x032C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x0128 0x032C 0x0000 0x00 0x00 + +#define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x012C 0x0330 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x012C 0x0330 0x048C 0x04 0x01 +#define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x012C 0x0330 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x0130 0x0334 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x0130 0x0334 0x0490 0x04 0x01 +#define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x0130 0x0334 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x0134 0x0338 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x0134 0x0338 0x0494 0x04 0x01 +#define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x0134 0x0338 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x0138 0x033C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x0138 0x033C 0x0498 0x04 0x01 +#define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x0138 0x033C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0138 0x033C 0x0000 0x06 0x00 + +#define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x013C 0x0340 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x013C 0x0340 0x0000 0x01 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x013C 0x0340 0x049C 0x04 0x01 +#define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x013C 0x0340 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x0140 0x0344 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0140 0x0344 0x04E4 0x01 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x0140 0x0344 0x04A0 0x04 0x01 +#define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x0140 0x0344 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x0140 0x0344 0x05FC 0x06 0x00 + +#define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x0144 0x0348 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0144 0x0348 0x04E8 0x01 0x00 +#define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x0144 0x0348 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x0144 0x0348 0x04A4 0x04 0x01 +#define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x0144 0x0348 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x0144 0x0348 0x0600 0x06 0x00 + +#define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x0148 0x034C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0148 0x034C 0x04EC 0x01 0x00 +#define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x0148 0x034C 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x0148 0x034C 0x04A8 0x04 0x01 +#define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x0148 0x034C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x0148 0x034C 0x0604 0x06 0x00 + +#define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x014C 0x0350 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x014C 0x0350 0x04F0 0x01 0x00 +#define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x014C 0x0350 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x014C 0x0350 0x04AC 0x04 0x01 +#define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x014C 0x0350 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x014C 0x0350 0x0608 0x06 0x00 + +#define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x0150 0x0354 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0150 0x0354 0x04D0 0x01 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x0150 0x0354 0x04B0 0x04 0x01 +#define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x0150 0x0354 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x0150 0x0354 0x05E4 0x06 0x00 + +#define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0154 0x0358 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x0154 0x0358 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0154 0x0358 0x0550 0x02 0x01 +#define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x0154 0x0358 0x04B4 0x04 0x01 +#define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x0154 0x0358 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0154 0x0358 0x0420 0x06 0x01 + +#define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x0158 0x035C 0x05C8 0x00 0x01 +#define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0158 0x035C 0x04F4 0x01 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x0158 0x035C 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x0158 0x035C 0x05AC 0x03 0x00 +#define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x0158 0x035C 0x04B8 0x04 0x01 +#define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x0158 0x035C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CLK__XSPI_CLK 0x0158 0x035C 0x05E8 0x06 0x00 + +#define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x015C 0x0360 0x05CC 0x00 0x01 +#define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x015C 0x0360 0x0000 0x01 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x015C 0x0360 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x015C 0x0360 0x05BC 0x03 0x00 +#define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x015C 0x0360 0x04BC 0x04 0x01 +#define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x015C 0x0360 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CMD__XSPI_CS 0x015C 0x0360 0x05E0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x0160 0x0364 0x05D0 0x00 0x01 +#define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x0160 0x0364 0x04D4 0x01 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x0160 0x0364 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x0160 0x0364 0x05A8 0x03 0x00 +#define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x0160 0x0364 0x04C0 0x04 0x01 +#define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x0160 0x0364 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x0160 0x0364 0x05EC 0x06 0x00 + +#define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x0164 0x0368 0x05D4 0x00 0x01 +#define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x0164 0x0368 0x04D8 0x01 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x0164 0x0368 0x05B0 0x02 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x0164 0x0368 0x0000 0x03 0x00 +#define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x0164 0x0368 0x04C4 0x04 0x01 +#define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x0164 0x0368 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x0164 0x0368 0x05F0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x0168 0x036C 0x05D8 0x00 0x01 +#define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x0168 0x036C 0x04DC 0x01 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x0168 0x036C 0x05B4 0x02 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x0168 0x036C 0x05C4 0x03 0x00 +#define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x0168 0x036C 0x04C8 0x04 0x01 +#define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x0168 0x036C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x0168 0x036C 0x05F4 0x06 0x00 + +#define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x016C 0x0370 0x05DC 0x00 0x01 +#define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x016C 0x0370 0x04E0 0x01 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x016C 0x0370 0x05B8 0x02 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x016C 0x0370 0x05C0 0x03 0x00 +#define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x016C 0x0370 0x04CC 0x04 0x01 +#define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x016C 0x0370 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x016C 0x0370 0x05F8 0x06 0x00 + +#define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x0170 0x0374 0x04D4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x0170 0x0374 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x0170 0x0374 0x05A0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x0170 0x0374 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x0170 0x0374 0x05EC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x0170 0x0374 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x0174 0x0378 0x04D8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x0174 0x0378 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x0174 0x0378 0x05A4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x0174 0x0378 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x0174 0x0378 0x05F0 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x0174 0x0378 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x0178 0x037C 0x04DC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x0178 0x037C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x0178 0x037C 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x0178 0x037C 0x05F4 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x0178 0x037C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x017C 0x0380 0x04E0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x017C 0x0380 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x017C 0x0380 0x0598 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x017C 0x0380 0x05F8 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x017C 0x0380 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0180 0x0384 0x04E4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x0180 0x0384 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x0180 0x0384 0x05B0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x0180 0x0384 0x05FC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x0180 0x0384 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0184 0x0388 0x04E8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x0184 0x0388 0x05C4 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x0184 0x0388 0x05B4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0184 0x0388 0x043C 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x0184 0x0388 0x0600 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x0184 0x0388 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0188 0x038C 0x04EC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x0188 0x038C 0x05C0 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x0188 0x038C 0x05B8 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x0188 0x038C 0x0440 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x0188 0x038C 0x0604 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x0188 0x038C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x018C 0x0390 0x04F0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x018C 0x0390 0x05AC 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x018C 0x0390 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x018C 0x0390 0x0608 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x018C 0x0390 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x0190 0x0394 0x04D0 0x00 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x0190 0x0394 0x05BC 0x01 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x0190 0x0394 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0190 0x0394 0x043C 0x03 0x01 +#define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x0190 0x0394 0x05E4 0x04 0x01 +#define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x0190 0x0394 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x0194 0x0398 0x04F4 0x00 0x01 +#define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x0194 0x0398 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x0194 0x0398 0x059C 0x02 0x01 +#define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x0194 0x0398 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x0194 0x0398 0x05E8 0x04 0x01 +#define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x0194 0x0398 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x0198 0x039C 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x0198 0x039C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0198 0x039C 0x0594 0x02 0x01 +#define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x0198 0x039C 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x0198 0x039C 0x05E0 0x04 0x01 +#define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x0198 0x039C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x019C 0x03A0 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x019C 0x03A0 0x05A8 0x01 0x01 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x019C 0x03A0 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x019C 0x03A0 0x0440 0x03 0x01 +#define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x019C 0x03A0 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01A0 0x03A4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01A0 0x03A4 0x0434 0x01 0x01 +#define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01A0 0x03A4 0x04F8 0x02 0x01 +#define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01A0 0x03A4 0x0468 0x04 0x01 +#define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01A0 0x03A4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01A4 0x03A8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01A4 0x03A8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01A4 0x03A8 0x04FC 0x02 0x01 +#define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01A4 0x03A8 0x046C 0x04 0x01 +#define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01A4 0x03A8 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01A4 0x03A8 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01A8 0x03AC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01A8 0x03AC 0x0438 0x01 0x01 +#define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01A8 0x03AC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01A8 0x03AC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01A8 0x03AC 0x0470 0x04 0x01 +#define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01A8 0x03AC 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01A8 0x03AC 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01AC 0x03B0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01AC 0x03B0 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01AC 0x03B0 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01AC 0x03B0 0x0474 0x04 0x01 +#define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01AC 0x03B0 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01AC 0x03B0 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01B0 0x03B4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01B0 0x03B4 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01B0 0x03B4 0x0444 0x02 0x03 +#define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01B0 0x03B4 0x0478 0x04 0x01 +#define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01B0 0x03B4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01B4 0x03B8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01B4 0x03B8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01B4 0x03B8 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01B4 0x03B8 0x047C 0x04 0x01 +#define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01B4 0x03B8 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01B8 0x03BC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01B8 0x03BC 0x0548 0x01 0x01 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01B8 0x03BC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01B8 0x03BC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01B8 0x03BC 0x0480 0x04 0x01 +#define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01B8 0x03BC 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01BC 0x03C0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01BC 0x03C0 0x054C 0x01 0x01 +#define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01BC 0x03C0 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01BC 0x03C0 0x0484 0x04 0x01 +#define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01BC 0x03C0 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01C0 0x03C4 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01C0 0x03C4 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01C0 0x03C4 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01C0 0x03C4 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01C0 0x03C4 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01C0 0x03C4 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01C4 0x03C8 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01C4 0x03C8 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01C4 0x03C8 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01C4 0x03C8 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01C4 0x03C8 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01C4 0x03C8 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01C8 0x03CC 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01C8 0x03CC 0x0000 0x01 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01C8 0x03CC 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01C8 0x03CC 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01C8 0x03CC 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01C8 0x03CC 0x0000 0x05 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01C8 0x03CC 0x0000 0x06 0x00 + +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01CC 0x03D0 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01CC 0x03D0 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01CC 0x03D0 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01CC 0x03D0 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01CC 0x03D0 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01D0 0x03D4 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01D0 0x03D4 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01D0 0x03D4 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01D0 0x03D4 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01D0 0x03D4 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01D4 0x03D8 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01D4 0x03D8 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01D4 0x03D8 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01D4 0x03D8 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01D4 0x03D8 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01D8 0x03DC 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01D8 0x03DC 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01D8 0x03DC 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01D8 0x03DC 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01D8 0x03DC 0x041C 0x04 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01D8 0x03DC 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01DC 0x03E0 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01DC 0x03E0 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01DC 0x03E0 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01DC 0x03E0 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01DC 0x03E0 0x0000 0x05 0x00 + +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01E0 0x03E4 0x0000 0x00 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01E0 0x03E4 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01E0 0x03E4 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01E0 0x03E4 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01E0 0x03E4 0x0000 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01E4 0x03E8 0x040C 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01E4 0x03E8 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01E4 0x03E8 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01E4 0x03E8 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01E4 0x03E8 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01E4 0x03E8 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01E4 0x03E8 0x0408 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01E8 0x03EC 0x0410 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01E8 0x03EC 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01E8 0x03EC 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01E8 0x03EC 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01E8 0x03EC 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01E8 0x03EC 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01E8 0x03EC 0x0420 0x06 0x00 + +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01EC 0x03F0 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01EC 0x03F0 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01EC 0x03F0 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01EC 0x03F0 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01EC 0x03F0 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01EC 0x03F0 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01F0 0x03F4 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01F0 0x03F4 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01F0 0x03F4 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01F0 0x03F4 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01F0 0x03F4 0x0408 0x04 0x01 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01F0 0x03F4 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01F4 0x03F8 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01F4 0x03F8 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01F4 0x03F8 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01F4 0x03F8 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01F4 0x03F8 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01F4 0x03F8 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01F8 0x03FC 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01F8 0x03FC 0x041C 0x01 0x01 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01F8 0x03FC 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01F8 0x03FC 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01F8 0x03FC 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01F8 0x03FC 0x0000 0x05 0x00 + +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01FC 0x0400 0x0000 0x00 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01FC 0x0400 0x0000 0x01 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01FC 0x0400 0x0000 0x05 0x00 +#endif /* __DTS_IMX95_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-power.h b/arch/arm64/boot/dts/freescale/imx95-power.h new file mode 100644 index 000000000000..0b7f0bc30e19 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-power.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX95_POWER_H__ +#define __IMX95_POWER_H__ + +#define IMX95_PD_ANA 0 +#define IMX95_PD_AON 1 +#define IMX95_PD_BBSM 2 +#define IMX95_PD_CAMERA 3 +#define IMX95_PD_CCMSRCGPC 4 +#define IMX95_PD_A55C0 5 +#define IMX95_PD_A55C1 6 +#define IMX95_PD_A55C2 7 +#define IMX95_PD_A55C3 8 +#define IMX95_PD_A55C4 9 +#define IMX95_PD_A55C5 10 +#define IMX95_PD_A55P 11 +#define IMX95_PD_DDR 12 +#define IMX95_PD_DISPLAY 13 +#define IMX95_PD_GPU 14 +#define IMX95_PD_HSIO_TOP 15 +#define IMX95_PD_HSIO_WAON 16 +#define IMX95_PD_M7 17 +#define IMX95_PD_NETC 18 +#define IMX95_PD_NOC 19 +#define IMX95_PD_NPU 20 +#define IMX95_PD_VPU 21 +#define IMX95_PD_WAKEUP 22 + +#define IMX95_PERF_ELE 0 +#define IMX95_PERF_M33 1 +#define IMX95_PERF_WAKEUP 2 +#define IMX95_PERF_M7 3 +#define IMX95_PERF_DRAM 4 +#define IMX95_PERF_HSIO 5 +#define IMX95_PERF_NPU 6 +#define IMX95_PERF_NOC 7 +#define IMX95_PERF_A55 8 +#define IMX95_PERF_GPU 9 +#define IMX95_PERF_VPU 10 +#define IMX95_PERF_CAM 11 +#define IMX95_PERF_DISP 12 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi new file mode 100644 index 000000000000..f98cec944eee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include + +#include "imx95-clock.h" +#include "imx95-pinfunc.h" +#include "imx95-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + A55_4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + enable-method = "psci"; + #cooling-cells = <2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l4>; + }; + + A55_5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + power-domains = <&scmi_devpd IMX95_PERF_A55>; + power-domain-names = "perf"; + enable-method = "psci"; + #cooling-cells = <2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l5>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l4: l2-cache-l4 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l5: l2-cache-l5 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + + core4 { + cpu = <&A55_4>; + }; + + core5 { + cpu = <&A55_5>; + }; + }; + }; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + sai1_mclk: clock-sai-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai1_mclk"; + }; + + sai2_mclk: clock-sai-mclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai2_mclk"; + }; + + sai3_mclk: clock-sai-mclk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai3_mclk"; + }; + + sai4_mclk: clock-sai-mclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai4_mclk"; + }; + + sai5_mclk: clock-sai-mclk5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <0>; + clock-output-names = "sai5_mclk"; + }; + + osc_24m: clock-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + sram1: sram@204c0000 { + compatible = "mmio-sram"; + reg = <0x0 0x204c0000 0x0 0x18000>; + ranges = <0x0 0x0 0x204c0000 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + thermal-zones { + a55-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + dma-noncoherent; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42430000 { + compatible = "fsl,imx95-mu"; + reg = <0x42430000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART3>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART6>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART7>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART8>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + mu8: mailbox@42730000 { + compatible = "fsl,imx95-mu"; + reg = <0x42730000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, + <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x1000>; + clocks = <&scmi_clk IMX95_CLK_TPM2>; + #pwm-cells = <3>; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPI2C2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPSPI2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_LPUART2>; + clock-names = "ipg"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX95_CLK_ADC>; + clock-names = "ipg"; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX95_CLK_M33>, + <&scmi_clk IMX95_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 112 16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + aips4: bus@49000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x49000000 0x0 0x800000>; + ranges = <0x49000000 0x0 0x49000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + smmu: iommu@490d0000 { + compatible = "arm,smmu-v3"; + reg = <0x490d0000 0x100000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3-58-ga151 From b8f771037e9e34f46bd6ef6a0ae568d2a782e6e1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Jun 2024 10:56:37 +0800 Subject: arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Add a minimal dts for i.MX95 19x19 EVK board: - lpuart1 as console - sdhc1/2 as storage Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index fae82f75c46a..42ad3abde4fc 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts new file mode 100644 index 000000000000..675abb70aa18 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include "imx95.dtsi" + +/ { + model = "NXP i.MX95 19X19 board"; + compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; -- cgit v1.2.3-58-ga151 From 0565d20cd8c22e44ca42937be08bfc0349e31521 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Jun 2024 11:11:45 +0800 Subject: arm64: dts: freescale: Support i.MX93 9x9 Quick Start Board Add the board device tree with sdhc1/2, cm33, mu, lpuart1, lpi2c1/2, usb enabled and etc, which to support the i.MX 93 quick start evaluation kit that provides a low-cost platform to evaluate the i.MX 93 applications processors in a 9x9mm package. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 492 ++++++++++++++++++++++++ 2 files changed, 493 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 42ad3abde4fc..06d47aa49813 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts new file mode 100644 index 000000000000..950dece83c24 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "VREF_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_rpi_3v3: regulator-rpi { + compatible = "regulator-fixed"; + regulator-name = "VDD_RPI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-mmc; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; -- cgit v1.2.3-58-ga151 From 67b82a35425388f1a5785eb13f9645894f64a43c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 16 Jun 2024 14:21:48 -0300 Subject: dt-bindings: arm: fsl: Document Compulab IOT-GATE-iMX8 Document Compulab's IOT-GATE-iMX8 board, which is based on Compulab's UCM-iMX8M-Mini SoM. Board URL: https://www.compulab.com/products/iot-gateways/iot-gate-imx8-industrial-arm-iot-gateway/ SoM URL: https://www.compulab.com/products/computer-on-modules/ucm-imx8m-mini-nxp-i-mx-8m-mini-som-system-on-module-computer/ Signed-off-by: Fabio Estevam Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 281f3dc71cc3..69a1008b6caf 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -945,6 +945,13 @@ properties: - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm + - description: Compulab i.MX8MM UCM SoM based boards + items: + - enum: + - compulab,imx8mm-iot-gateway # i.MX8MM Compulab IoT-Gateway + - const: compulab,imx8mm-ucm-som # i.MX8MM Compulab UCM SoM + - const: fsl,imx8mm + - description: Emtop i.MX8MM based Boards items: - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 -- cgit v1.2.3-58-ga151 From ba4478013c19b8a894f83c1e73194b47c76eb56c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Jun 2024 10:56:35 +0800 Subject: dt-bindings: arm: fsl: add i.MX95 19x19 EVK board Add DT compatible string for NXP i.MX95 19x19 EVK board. Acked-by: Conor Dooley Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 69a1008b6caf..2e81362897bb 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1281,6 +1281,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MX95 based Boards + items: + - enum: + - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: -- cgit v1.2.3-58-ga151 From 9270c5f84bf250c874654763030b1699d6b8ad28 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 17 Jun 2024 11:11:44 +0800 Subject: dt-bindings: arm: fsl: add i.MX93 9x9 QSB board Add compatible string for i.MX93 9x9 Quick Start Board. Acked-by: Conor Dooley Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2e81362897bb..d2553857d00d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1278,6 +1278,7 @@ properties: - description: i.MX93 based Boards items: - enum: + - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 -- cgit v1.2.3-58-ga151 From b2774d0292e875861c70ea75dc3baf88d4cec1ad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:07 +0200 Subject: arm64: zynqmp: Align nvmem node with dt schema Use new soc-nvmem node name and swich to nvmem fixed layout. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7796804c7c7dd8bb2c93bdfe028c22746a24fe54.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 95796d6b5515..cb74d1ffb825 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -207,13 +207,16 @@ mbox-names = "tx", "rx"; }; - nvmem-firmware { + soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc-revision@0 { - reg = <0x0 0x4>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; }; }; -- cgit v1.2.3-58-ga151 From 4e07d2281e2e847a36fa1c44b12681ae7bddf4e4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:08 +0200 Subject: arm64: zynqmp: Use fpga-region as node name Based on commit 85f838adad54 ("dt-bindings: fpga: Convert fpga-region binding to yaml") fpga/programmable logic should use fpga-region as node name that's why move to it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9133aed74a24ad5cd9af5a6d5aa7ee9a160f94ee.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index cb74d1ffb825..a43c64625402 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -255,7 +255,7 @@ ; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; -- cgit v1.2.3-58-ga151 From 0596963139717297fd2ae126d9727bd56cc51f15 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:09 +0200 Subject: arm64: zynqmp: Add missing description for efuses The commit 737c0c8d07b5 ("nvmem: zynqmp_nvmem: Add support to access efuse") added support for efuses that's why also describe them in DT. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/beb8002f8dae47ce6f38f7f961d024e65372b654.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a43c64625402..635b67c06c4e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -217,6 +217,61 @@ soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse-aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse-pufuser@100 { + reg = <0x100 0x7F>; + }; }; }; -- cgit v1.2.3-58-ga151 From f88eac0b68310f82c8d7dc6ab3903887fe9d3c28 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:10 +0200 Subject: arm64: zynqmp: Describe USB wakeup interrupt Describe usb wakeup interrupt. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8c11ac7d73c822ee207cecd1445205f19fcaf004.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 635b67c06c4e..c70def3d464b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -1084,10 +1084,11 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = , , - ; + , + ; clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; @@ -1115,10 +1116,11 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = , , - ; + , + ; clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; -- cgit v1.2.3-58-ga151 From 7ab06833e0787905a239e311cd27f92c40902636 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:11 +0200 Subject: arm64: zynqmp: Describe OCM controller Describe OCM controller which brings EDAC functionality. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/679736679fdf7897d68684295f6ed8256fb5f18e.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c70def3d464b..f1094f553366 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -827,6 +827,13 @@ power-domains = <&zynqmp_firmware PD_I2C_1>; }; + ocm: memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0x0 0xff960000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; -- cgit v1.2.3-58-ga151 From a520fcceb9609823bf50818fd838cf22ee97341c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:12 +0200 Subject: arm64: zynqmp: Remove address/size-cells from ams node Remove unused address/size-cells properties without defining child. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/39f73999bbec0233264ce40f05c0885c46e423be.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index f1094f553366..b1b31dcf6291 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -1176,8 +1176,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; -- cgit v1.2.3-58-ga151 From a082e297fa18d96a41ccc308eb31675ffd3a47f8 Mon Sep 17 00:00:00 2001 From: Tejas Bhumkar Date: Mon, 27 May 2024 11:34:13 +0200 Subject: arm64: zynqmp: Disable Tri-state for SDIO Since the zynqmp pinctrl driver now includes support for the tri-state registers, ensure that the pins needing output-enable are correctly configured for SOMs. Currently, there is an issue with the detection of the MMC for the SOM kv260, resulting in the following error: ZynqMP> mmc dev 1 Card did not respond to voltage select! : -110 To address this problem, configure the SDIO pins for output-enable to enable MMC detection. Signed-off-by: Tejas Bhumkar Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/540f83f7d88b80441c9fa3d771dd7b000b0710a4.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index d7535a77b45e..a09909a6f885 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -321,6 +321,7 @@ slew-rate = ; power-source = ; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a7b8fffad499..b3b8875f8f7a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -305,6 +305,7 @@ slew-rate = ; power-source = ; bias-disable; + output-enable; }; conf-cd { -- cgit v1.2.3-58-ga151 From 894221b5a52a046f1d9469ec7145e5fc46fb0e63 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:14 +0200 Subject: arm64: zynqmp: Add compatible string for kv260 The commit dbcd27526e6a ("dt-bindings: soc: xilinx: Add support for KV260 CC") added description for kv260 kit and it should be also reflected in DTs. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1e436f82182a92187f3892401664db2507482870.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index a09909a6f885..0e5597e2fe10 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -22,6 +22,12 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-revA", + "xlnx,zynqmp-sk-kv260-revY", + "xlnx,zynqmp-sk-kv260-revZ", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revA"; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index b3b8875f8f7a..fb37c06cfd69 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -17,6 +17,12 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", + "xlnx,zynqmp-sk-kv260-revB", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revB"; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3-58-ga151 From 385cc4f769b44ab8ecf8502429d8f710e0f234c9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:15 +0200 Subject: arm64: zynqmp: Add description for ina260 on kv260 The commit f7ab2d180e6a ("dt-bindings: hwmon: ina2xx: Describe ina260 chip"), commit f29996d0295e ("dt-bindings: hwmon: ina2xx: Describe #io-channel-cells property") and commit eea32fafadd3 ("dt-bindings: hwmon: ina2xx: Add label property") added description for ina260 that's why describe them on kv260 Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/944cba76ef5df932f1bebde6c5e64ec9d201356d.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 12 +++++++++++- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 14 ++++++++++++-- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 0e5597e2fe10..95d16904d765 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -28,6 +28,11 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revA"; + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,7 +79,12 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index fb37c06cfd69..3ada04781950 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -23,6 +23,11 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -69,8 +74,13 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ - /* u43 - 0x2d - usb5744 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + /* u43 - 0x2d - USB hub */ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; -- cgit v1.2.3-58-ga151 From 0d7835cf2d1ffceaa969e2106aa8d6a00ca343c0 Mon Sep 17 00:00:00 2001 From: Vishal Sagar Date: Mon, 27 May 2024 11:34:16 +0200 Subject: arm64: zynqmp: Describe DisplayPort connector for Kria Add a device tree node to describe the DisplayPort connector, and connect it to the DPSUB output. The patch was tested on kv260-revB/rev2. Signed-off-by: Vishal Sagar Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4f69489c005719d280b8df97f3e82a5ce0cd9660.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 3ada04781950..a74d0ac7e07a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -63,6 +63,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -97,6 +109,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { -- cgit v1.2.3-58-ga151 From 89562ff4f0b8eac2915e8388ebdd76a4c2006eb8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2024 11:34:17 +0200 Subject: arm64: zynqmp: Add support for K26 rev2 boards Revision 2 is SW compatible with revision 1 but it is necessary to reflect it in model and compatible properties which are parsed by user space. Rev 2 has improved a power on boot reset and MIO34 shutdown glich improvement done via an additional filter in the GreenPak chip. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/458698666fdfcaaac70967d9f755422a480bed99.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 8 +++++--- arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 51622896b1b1..2841be11ae66 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SM-K26 rev1/B/A + * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -17,8 +18,9 @@ #include / { - model = "ZynqMP SM-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", + model = "ZynqMP SM-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-sm-k26-rev2", + "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts index 85b0d1677240..b804abe89d1d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A + * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -10,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts" / { - model = "ZynqMP SMK-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", + model = "ZynqMP SMK-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-smk-k26-rev2", + "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; -- cgit v1.2.3-58-ga151 From f9508ef9976e8596f8a1139430ec439691f3337f Mon Sep 17 00:00:00 2001 From: Vishal Patel Date: Mon, 27 May 2024 11:34:18 +0200 Subject: arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property Add pwm-fan node to control fan through hwmon and change pwm-cells property to 3 to allow fancontrol utility to function correctly. Signed-off-by: Vishal Patel Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ff6b4dbfc9bb1b53769ffbf7d0e932c7a8be7c08.1716802450.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 2841be11ae66..86e6c4990560 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -103,12 +103,23 @@ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 0>; + }; }; &modepin_gpio { label = "modepin"; }; +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; -- cgit v1.2.3-58-ga151 From c249e17c37d3a767cb9aa57fe1e429e155fd4171 Mon Sep 17 00:00:00 2001 From: Henry Bell Date: Thu, 23 May 2024 21:55:37 +0000 Subject: dt-bindings: riscv: starfive: add Star64 board compatible Add pine64,star64 to JH7110 compatibility. The Pine64 Star64 is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 1x USB 3.0 host port - 3x USB 2.0 host port - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 2x 1Gbps Ethernet port - 1x HDMI port - 1x 4-lane DSI - 1x 2-lane CSI - 1x PCIe 2.0 x1 lane Signed-off-by: Henry Bell Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index b672f8521949..4d5c857b3cac 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - milkv,mars + - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b - const: starfive,jh7110 -- cgit v1.2.3-58-ga151 From 2606bf583b9623694b864c220fd6b3d2ed13ba13 Mon Sep 17 00:00:00 2001 From: Henry Bell Date: Thu, 23 May 2024 21:55:38 +0000 Subject: riscv: dts: starfive: add Star64 board devicetree The Pine64 Star64 is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 1x USB 3.0 host port - 3x USB 2.0 host port - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 2x 1Gbps Ethernet port - 1x HDMI port - 1x 4-lane DSI - 1x 2-lane CSI - 1x PCIe 2.0 x1 lane Signed-off-by: Henry Bell Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/Makefile | 1 + .../boot/dts/starfive/jh7110-pine64-star64.dts | 61 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 2fa0cd7f31c3..7a163a7d6ba3 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts new file mode 100644 index 000000000000..2d41f18e0359 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Henry Bell + */ + +/dts-v1/; +#include "jh7110-common.dtsi" + +/ { + model = "Pine64 Star64"; + compatible = "pine64,star64", "starfive,jh7110"; + aliases { + ethernet1 = &gmac1; + }; +}; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; +}; + +&gmac1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + starfive,tx-use-rgmii-clk; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&phy0 { + rx-internal-delay-ps = <1900>; + tx-internal-delay-ps = <1500>; + motorcomm,rx-clk-drv-microamp = <2910>; + motorcomm,rx-data-drv-microamp = <2910>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-10-inverted; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; +}; + +&phy1 { + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <300>; + motorcomm,rx-clk-drv-microamp = <2910>; + motorcomm,rx-data-drv-microamp = <2910>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-10-inverted; + motorcomm,tx-clk-100-inverted; +}; -- cgit v1.2.3-58-ga151 From c61fea676bcb5f14adcd882a7f7d9c5b082fe922 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 30 May 2024 19:18:35 +0800 Subject: riscv: dts: thead: th1520: Add PMU event node T-HEAD th1520 uses standard C910 chip and its pmu is already supported by OpenSBI. Add the pmu event description for T-HEAD th1520 SoC. Signed-off-by: Inochi Amaoto Link: https://www.xrvm.com/product/xuantie/4240217381324001280?spm=xrvm.27140568.0.0.7f979b29nzIa1m Reviewed-by: Guo Ren Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 81 +++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d2fa25839012..3c9974062c20 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -122,6 +122,87 @@ }; }; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0x0007fff8>, + <0x00004 0x00004 0x0007fff8>, + <0x00005 0x00005 0x0007fff8>, + <0x00006 0x00006 0x0007fff8>, + <0x00007 0x00007 0x0007fff8>, + <0x00008 0x00008 0x0007fff8>, + <0x00009 0x00009 0x0007fff8>, + <0x0000a 0x0000a 0x0007fff8>, + <0x10000 0x10000 0x0007fff8>, + <0x10001 0x10001 0x0007fff8>, + <0x10002 0x10002 0x0007fff8>, + <0x10003 0x10003 0x0007fff8>, + <0x10010 0x10010 0x0007fff8>, + <0x10011 0x10011 0x0007fff8>, + <0x10012 0x10012 0x0007fff8>, + <0x10013 0x10013 0x0007fff8>; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000001>, + <0x00004 0x00000000 0x00000002>, + <0x00006 0x00000000 0x00000006>, + <0x00005 0x00000000 0x00000007>, + <0x00007 0x00000000 0x00000008>, + <0x00008 0x00000000 0x00000009>, + <0x00009 0x00000000 0x0000000a>, + <0x0000a 0x00000000 0x0000000b>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10010 0x00000000 0x00000010>, + <0x10011 0x00000000 0x00000011>, + <0x10012 0x00000000 0x00000012>, + <0x10013 0x00000000 0x00000013>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, + <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; + }; + osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc_24m"; -- cgit v1.2.3-58-ga151 From edbce932b16c8ae93eb916c31d762356679ad353 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 3 Jun 2024 17:07:55 +0200 Subject: riscv: dts: starfive: Update flash partition layout Up to now, the describe flash partition layout has some gaps. Use the whole flash chip by getting rid of the gaps. Suggested-by: Heinrich Schuchardt Signed-off-by: Matthias Brugger Reviewed-by: Emil Renner Berthing Reviewed-by: Heinrich Schuchardt Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 8ff6ea64f048..37b4c294ffcc 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -321,16 +321,13 @@ #size-cells = <1>; spl@0 { - reg = <0x0 0x80000>; + reg = <0x0 0xf0000>; }; uboot-env@f0000 { reg = <0xf0000 0x10000>; }; uboot@100000 { - reg = <0x100000 0x400000>; - }; - reserved-data@600000 { - reg = <0x600000 0xa00000>; + reg = <0x100000 0xf00000>; }; }; }; -- cgit v1.2.3-58-ga151 From 76ed031dc750eb0846818ada1856a8c56d527892 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 27 Mar 2024 12:24:36 +0000 Subject: dt-bindings: riscv: microchip: document beaglev-fire The BeagleV Fire is a BeagleBone Black form-factor board with a PolarFire SoC. Link: https://www.beagleboard.org/boards/beaglev-fire Acked-by: Rob Herring Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 4a29c890619a..78ce76ae1b6d 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -29,6 +29,7 @@ properties: - enum: - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp + - beagle,beaglev-fire - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs -- cgit v1.2.3-58-ga151 From 3f41368fbfe1b3d5922d317fe1a0a0cab6846802 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 27 Mar 2024 12:24:40 +0000 Subject: riscv: dts: microchip: add an initial devicetree for the BeagleV Fire Add an initial devicetree for the BeagleV Fire. This devicetree differs from that in the BeagleBoard BSP as it has a different memory configuration, however it will boot on the same FPGA images. PCI is disabled for now, as the Linux PCI driver (and the binding) assume which root port instance is in use. This will need to be fixed before PCI can be enabled. Link: https://www.beagleboard.org/boards/beaglev-fire Co-developed-by: Jamie Gibbons Signed-off-by: Jamie Gibbons Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-beaglev-fire-fabric.dtsi | 82 ++++++++ .../riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 223 +++++++++++++++++++++ 3 files changed, 306 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index e177815bf1a2..f51aeeb9fd3b 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi new file mode 100644 index 000000000000..e153eaf9b90e --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + fabric-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */ + <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */ + <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */ + <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */ + <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */ + + cape_gpios_p8: gpio@41100000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x41100000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34", + "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38", + "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42", + "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46"; + }; + + cape_gpios_p9: gpio@41200000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x41200000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14", + "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18", + "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24", + "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28", + "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42"; + }; + + hsi_gpios: gpio@44000000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x44000000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", + "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P", + "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID", + "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID", + "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID", + "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK", + "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N"; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts new file mode 100644 index 000000000000..47cf693beb68 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/dts-v1/; + +#include +#include "mpfs.dtsi" +#include "mpfs-beaglev-fire-fabric.dtsi" + +/* Clock frequency (in Hz) of MTIMER */ +#define MTIMER_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "BeagleBoard BeagleV-Fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer@103fc00000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + }; + + imx219_clk: camera-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + imx219_vana: fixedregulator-0 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + imx219_vdig: fixedregulator-1 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vdig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + imx219_vddl: fixedregulator-2 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + ngpios=<32>; + gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2", + "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5", + "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8", + "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11", + "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20", + "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26", + "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1", + "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET"; + status = "okay"; + + vio-enable-hog { + gpio-hog; + gpios = <30 30>; + output-high; + line-name = "VIO_ENABLE"; + }; + + sd-det-hog { + gpio-hog; + gpios = <31 31>; + input; + line-name = "SD_DET"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + microchip,bitstream-flash = <&sys_ctrl_flash>; + status = "okay"; +}; + +&syscontroller_qspi { + status = "okay"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +}; -- cgit v1.2.3-58-ga151 From f53f477bfcb8aa7490b3bd3030e3bef1b95dbdce Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Mon, 3 Jun 2024 16:59:38 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add node for EHRPWMs Add dts nodes for 6 EHRPWM instances on SoC. Signed-off-by: Dasnavis Sabiya Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20240603112938.2188510-1-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 66 ++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index fd3d3344efbe..a3e91ff87b4a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -115,6 +115,72 @@ #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3000000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3010000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3020000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3030000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3040000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x3050000 0x00 0x100>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; + clock-names = "tbclk", "fck"; + power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; + #pwm-cells = <3>; + status = "disabled"; }; gic500: interrupt-controller@1800000 { -- cgit v1.2.3-58-ga151 From 927718d246fcf14b2b642691936f2abe2e80917e Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 12:50:11 -0700 Subject: arm64: dts: ti: am642-phyboard-electra: Remove PCIe pinmuxing Remove pinmuxing for PCIe so that we can add it in an overlay. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240613195012.1925920-2-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 6df331ccb970..30729b49dd69 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -190,18 +190,6 @@ >; }; - pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ - >; - }; - - pcie0_pins_default: pcie0-default-pins { - pinctrl-single,pins = < - AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ - >; - }; - user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */ -- cgit v1.2.3-58-ga151 From e9bb631b3eb41309063fd8ad804a3935665009a4 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 12:50:12 -0700 Subject: arm64: dts: ti: am642-phyboard-electra: Add overlay to enable PCIe Add an overlay to enable PCIe on the am642-phyboard-electra. The serdes is muxed from USB to PCIe, so we are restricted to USB2 while using this overlay. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240613195012.1925920-3-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 3 + .../ti/k3-am642-phyboard-electra-pcie-usb2.dtso | 87 ++++++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index d956372a7163..47e73ea3ece3 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -143,6 +144,8 @@ k3-am642-evm-icssg1-dualemac-mii-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo +k3-am642-phyboard-electra-pcie-usb2-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso new file mode 100644 index 000000000000..7a5ce4bc02f3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT overlay for PCIe support (limits USB to 2.0/high-speed) + * + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee + * + * Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + pcie_refclk0: pcie-refclk0 { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_usb_sel_pins_default>; + clocks = <&serdes_refclk>; + #clock-cells = <0>; + enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&main_pmx0 { + pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ + >; + }; + + pcie_pins_default: pcie-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ + >; + }; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins_default>; + reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_usb_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "okay"; +}; + +&serdes0_pcie_usb_link { + cdns,phy-type = ; +}; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +/* + * Assign pcie_refclk0 to serdes_wiz0 as ext_ref_clk. + * This makes sure that the clock generator gets enabled at the right time. + */ +&serdes_wiz0 { + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&pcie_refclk0>; +}; + +&usbss0 { + ti,usb2-only; +}; + +&usb0 { + maximum-speed = "high-speed"; +}; -- cgit v1.2.3-58-ga151 From 9c0fa304fa561abfe83d328ffc4f638c0152bead Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 13 Jun 2024 15:07:06 +0530 Subject: arm64: dts: ti: k3-j721e: Add overlay for J721E Infotainment Expansion Board J721E common processor board can be interfaced with the infotainment expansion board[0] to enable the following audio/video interfaces in addition to the peripherals provided by the common processor board: - Two Audio codecs each with three Stereo Inputs and four Stereo Outputs - Audio input over FPD Link III - Digital Audio Interface TX/RX - HDMI/FPD LINK III Display out - LI/OV Camera input Add support for TFP410 HDMI bridge located on the Infotainment Expansion Board (connected to J46 & J51). Add a HDMI connector node and connect the endpoints as below: DSS => TFP410 bridge => HDMI connector Also add the pinmux data and board muxes for DPI. Rest of the peripherals are not added as of now. [0]: Signed-off-by: Tomi Valkeinen [j-choudhary@ti.com: minor cleanup] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20240613093706.480700-1-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-j721e-common-proc-board-infotainment.dtso | 164 +++++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 47e73ea3ece3..eb9de38a2890 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb # Boards with J721e SoC k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board-infotainment.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo @@ -154,6 +155,8 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-common-proc-board-infotainment.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ @@ -185,6 +188,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ + k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso new file mode 100644 index 000000000000..65a7e54f0884 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Infotainment Expansion Board for j721e-evm + * User Guide: + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&main_i2c1>; + digital; + /* P12 - HDMI_HPD */ + hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tfp410"; + /* P10 - HDMI_PDn */ + powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = + <&hdmi_connector_in>; + }; + }; + }; +}; + +&main_pmx0 { + main_i2c1_exp6_pins_default: main-i2c1-exp6-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */ + >; + }; + + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ + J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ + J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ + J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ + J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ + J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ + J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ + J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ + J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ + J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ + J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ + J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ + J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ + J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ + J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ + J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ + J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ + J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ + J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ + J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ + J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ + J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ + J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ + J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ + J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ + J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ + J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ + J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ + >; + }; +}; + +&exp1 { + p14-hog { + /* P14 - VINOUT_MUX_SEL0 */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "VINOUT_MUX_SEL0"; + }; + + p15-hog { + /* P15 - VINOUT_MUX_SEL1 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VINOUT_MUX_SEL1"; + }; +}; + +&main_i2c1 { + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + exp6: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_exp6_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + p11-hog { + /* P11 - HDMI_DDC_OE */ + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "HDMI_DDC_OE"; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; -- cgit v1.2.3-58-ga151 From 1fc3858a906bf3e8c48a14587106bb61c2f8d7c5 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 16:07:56 -0700 Subject: arm64: dts: ti: k3-am64-phycore-som: Add serial_flash label Label the spi nor as serial_flash. This allows us to disable the flash with an overlay common to all am6xx-phycore-som boards. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240613230759.1984966-2-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 2c3b20ddfb8b..ea7c58fb67e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -340,7 +340,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0 { + serial_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; -- cgit v1.2.3-58-ga151 From 1322b1796d7143dfa75e10e036c6099927ef510d Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 16:07:57 -0700 Subject: arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable eth phy Add an overlay to disable the eth phy for all am6xx-phycore-som boards. The EEPROM on am6xx-phycore-soms contains information about the configuration of the SOM. The standard configuration of the SOM has an ethernet phy, but if no ethernet phy is populated, the EEPROM will indicate that change and we can use this overlay to cleanly disable the ethernet phy. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240613230759.1984966-3-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 7 +++++++ .../boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index eb9de38a2890..14c7377cb9b0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -57,6 +57,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +# Common overlays for the phyCORE-AM6* family of boards +dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo + # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ k3-am654-base-board-rocktech-rk101-panel.dtbo \ @@ -116,6 +119,8 @@ k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo +k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am6xx-phycore-disable-eth-phy.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ @@ -143,6 +148,8 @@ k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-am642-evm-icssg1-dualemac-mii-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo +k3-am642-phyboard-electra-disable-eth-phy-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso new file mode 100644 index 000000000000..356c82bbe143 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023 PHYTEC America, LLC + * Author: Garrett Giordano + * + * Copyright (C) 2024 PHYTEC America, LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +&cpsw3g_phy1 { + status = "disabled"; +}; + +&cpsw_port1 { + status = "disabled"; +}; -- cgit v1.2.3-58-ga151 From a0b552605f8c588fdd9ea062886fb90d50534a8d Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 16:07:58 -0700 Subject: arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable rtc Add an overlay to disable the rtc for all am6xx-phycore-som boards. The EEPROM on am6xx-phycore-soms contains information about the configuration of the SOM. The standard configuration of the SOM has an rtc, but if no rtc is populated, the EEPROM will indicate that change and we can use this overlay to cleanly disable the rtc. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240613230759.1984966-4-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 +++++ arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso | 15 +++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 14c7377cb9b0..6c816446df8f 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo # Common overlays for the phyCORE-AM6* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ @@ -121,6 +122,8 @@ k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-eth-phy.dtbo +k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am6xx-phycore-disable-rtc.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ @@ -150,6 +153,8 @@ k3-am642-evm-icssg1-dualemac-mii-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo k3-am642-phyboard-electra-disable-eth-phy-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo +k3-am642-phyboard-electra-disable-rtc-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-rtc.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso new file mode 100644 index 000000000000..8b24191f5948 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023 PHYTEC America, LLC + * Author: Garrett Giordano + * + * Copyright (C) 2024 PHYTEC America, LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +&i2c_som_rtc { + status = "disabled"; +}; -- cgit v1.2.3-58-ga151 From 9a32378884931d8f66d0d7122873156199fa422f Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Thu, 13 Jun 2024 16:07:59 -0700 Subject: arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable spi nor Add an overlay to disable the spi nor for all am6xx-phycore-som boards. The EEPROM on am6xx-phycore-soms contains information about the configuration of the SOM. The standard configuration of the SOM has an ospi nor, but if no nor is populated, the EEPROM will indicate that change and we can use this overlay to cleanly disable the spi nor. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240613230759.1984966-5-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 +++++ .../boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso | 15 +++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6c816446df8f..31b870601247 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo # Common overlays for the phyCORE-AM6* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-spi-nor.dtbo # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ @@ -124,6 +125,8 @@ k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-eth-phy.dtbo k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-rtc.dtbo +k3-am625-phyboard-lyra-disable-spi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am6xx-phycore-disable-spi-nor.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ @@ -155,6 +158,8 @@ k3-am642-phyboard-electra-disable-eth-phy-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-eth-phy.dtbo k3-am642-phyboard-electra-disable-rtc-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-rtc.dtbo +k3-am642-phyboard-electra-disable-spi-nor-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-spi-nor.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso new file mode 100644 index 000000000000..cc0cf269b6e4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023 PHYTEC America, LLC + * Author: Garrett Giordano + * + * Copyright (C) 2024 PHYTEC America, LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +&serial_flash { + status = "disabled"; +}; -- cgit v1.2.3-58-ga151 From 117937ff2fbf1f67e6e7cbe1635bbe1cc72dbee2 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 14 Jun 2024 18:06:42 +0300 Subject: arm64: dts: ti: am642-evm: Add overlay for NAND expansion card The NAND expansion card plugs in over the HSE (High Speed Expansion) connector. Add support for it. We add the ranges property to the GPMC node instead of the NAND overlay file to prevent below warnings. /fragment@3/__overlay__: Relying on default #address-cells value /fragment@3/__overlay__: Relying on default #size-cells value As GPMC is dedicated for NAND use on this board, it should be OK. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20240614-am642-evm-nand-v5-1-acf760896239@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso | 138 ++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 4 + 3 files changed, 144 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 31b870601247..1e6fcd1ff7ba 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -49,6 +49,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb +k3-am642-evm-nand-dtbs := k3-am642-evm.dtb k3-am642-evm-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso new file mode 100644 index 000000000000..dc70b6fbc3d7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for HSE NAND expansion card on AM642 EVM + * + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + gpmc0_pins_default: gpmc0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */ + AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */ + AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */ + AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */ + AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */ + AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */ + AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */ + AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */ + AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */ + AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */ + AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */ + AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */ + AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */ + AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */ + AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */ + AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */ + AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */ + AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */ + AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */ + AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */ + AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */ + AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */ + AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */ + AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */ + AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */ + AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */ + AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */ + >; + }; +}; + +&main_gpio0 { + gpio0-36 { + gpio-hog; + gpios = <36 0>; + input; + line-name = "GPMC0_MUX_DIR"; + }; +}; + +&elm0 { + status = "okay"; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + #address-cells = <2>; + #size-cells = <1>; + + nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00200000>; /* 2M */ + }; + partition@200000 { + label = "NAND.tispl"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 2M */ + reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ + }; + partition@600000 { + label = "NAND.u-boot"; + reg = <0x00600000 0x00400000>; /* 4M */ + }; + partition@a00000 { + label = "NAND.u-boot-env"; + reg = <0x00a00000 0x00040000>; /* 256K */ + }; + partition@a40000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00a40000 0x00040000>; /* 256K */ + }; + partition@a80000 { + label = "NAND.file-system"; + reg = <0x00a80000 0x3f580000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e20e4ffd0f1f..9f691ed97791 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -817,3 +817,7 @@ rx-internal-delay-ps = <2000>; }; }; + +&gpmc0 { + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ +}; -- cgit v1.2.3-58-ga151 From 3ad6579f106db8f94fb8495063cb4b0f0eaaaa9a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:53 +0530 Subject: arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi The AM62P and J722S SoCs share most of the peripherals. With the aim of reusing the existing k3-am62p-{mcu,main,thermal,wakeup}.dtsi files for J722S SoC, rename them to indicate that they are shared with the J722S SoC. The peripherals that are not shared will be moved in the upcoming patches to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in the filename, emphasizing that they are not shared. Signed-off-by: Siddharth Vadapalli Acked-by: Andrew Davis Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-2-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 1095 ++++++++++++++++++++ .../boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 208 ++++ .../boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi | 50 + .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 114 ++ arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1094 ------------------- arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi | 207 ---- arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi | 50 - arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 113 -- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 8 +- 9 files changed, 1471 insertions(+), 1468 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi delete mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi delete mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi delete mode 100644 arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi delete mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi new file mode 100644 index 000000000000..ff97e4a59e3b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: bus@100000 { + compatible = "simple-bus"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + bootph-all; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + bootph-all; + }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <5 69 35>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>, + <0x00 0x48420000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "bchan"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x20000>, + <0x00 0x4b800000 0x00 0x200000>, + <0x00 0x485e0000 0x00 0x10000>, + <0x00 0x484a0000 0x00 0x2000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x1000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "rflow"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + bootph-all; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; + }; + + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + #dma-cells = <3>; + msi-parent = <&inta_main_dmss_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + bootph-all; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + bootph-all; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + bootph-all; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + bootph-all; + }; + }; + + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + bootph-all; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + bootph-all; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + bootph-all; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 0>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 142 0>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 143 0>; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <92>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <52>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am64-sdhci-8bit"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 2>; + assigned-clock-parents = <&k3_clks 57 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + status = "disabled"; + }; + + usbss0: usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; + status = "disabled"; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29010000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30102000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5000 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = ; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi new file mode 100644 index 000000000000..1d4e5fc8b4e0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the MCU domain peripherals shared by AM62P and J722S + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + bootph-all; + }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + status = "reserved"; + bootph-pre-ram; + }; + + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + status = "disabled"; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + status = "disabled"; + }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + status = "disabled"; + }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62p-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi new file mode 100644 index 000000000000..c7486fb2a5b4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi new file mode 100644 index 000000000000..315d0092e736 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: bus@43000000 { + compatible = "simple-bus"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + bootph-all; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + bootph-all; + }; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi deleted file mode 100644 index eed06506f617..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ /dev/null @@ -1,1094 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Device Tree file for the AM62P main domain peripherals - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_main { - oc_sram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x10000>; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x01 0x00000000 0x00 0x2000>, /* GICC */ - <0x01 0x00010000 0x00 0x1000>, /* GICH */ - <0x01 0x00020000 0x00 0x2000>; /* GICV */ - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_conf: bus@100000 { - compatible = "simple-bus"; - reg = <0x00 0x00100000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x20000>; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock-controller@4130 { - compatible = "ti,am62-epwm-tbclk"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - }; - - dmss: bus@48000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - dma-ranges; - ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; - bootph-all; - - ti,sci-dev-id = <25>; - - secure_proxy_main: mailbox@4d000000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x4d000000 0x00 0x80000>, - <0x00 0x4a600000 0x00 0x80000>, - <0x00 0x4a400000 0x00 0x80000>; - interrupt-names = "rx_012"; - interrupts = ; - bootph-all; - }; - - inta_main_dmss: interrupt-controller@48000000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x48000000 0x00 0x100000>; - #interrupt-cells = <0>; - interrupt-controller; - interrupt-parent = <&gic500>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <28>; - ti,interrupt-ranges = <5 69 35>; - ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; - }; - - main_bcdma: dma-controller@485c0100 { - compatible = "ti,am64-dmss-bcdma"; - reg = <0x00 0x485c0100 0x00 0x100>, - <0x00 0x4c000000 0x00 0x20000>, - <0x00 0x4a820000 0x00 0x20000>, - <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>, - <0x00 0x48600000 0x00 0x8000>, - <0x00 0x484a4000 0x00 0x2000>, - <0x00 0x484c2000 0x00 0x2000>, - <0x00 0x48420000 0x00 0x2000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", - "ring", "tchan", "rchan", "bchan"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <3>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <26>; - ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ - ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ - ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ - bootph-all; - }; - - main_pktdma: dma-controller@485c0000 { - compatible = "ti,am64-dmss-pktdma"; - reg = <0x00 0x485c0000 0x00 0x100>, - <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x20000>, - <0x00 0x4b800000 0x00 0x200000>, - <0x00 0x485e0000 0x00 0x10000>, - <0x00 0x484a0000 0x00 0x2000>, - <0x00 0x484c0000 0x00 0x2000>, - <0x00 0x48430000 0x00 0x1000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", - "ring", "tchan", "rchan", "rflow"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <2>; - bootph-all; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <30>; - ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ - <0x24>, /* CPSW_TX_CHAN */ - <0x25>, /* SAUL_TX_0_CHAN */ - <0x26>; /* SAUL_TX_1_CHAN */ - ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ - <0x11>, /* RING_CPSW_TX_CHAN */ - <0x12>, /* RING_SAUL_TX_0_CHAN */ - <0x13>; /* RING_SAUL_TX_1_CHAN */ - ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ - <0x2b>, /* CPSW_RX_CHAN */ - <0x2d>, /* SAUL_RX_0_CHAN */ - <0x2f>, /* SAUL_RX_1_CHAN */ - <0x31>, /* SAUL_RX_2_CHAN */ - <0x33>; /* SAUL_RX_3_CHAN */ - ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ - <0x2c>, /* FLOW_CPSW_RX_CHAN */ - <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ - <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ - }; - }; - - dmss_csi: bus@4e000000 { - compatible = "simple-bus"; - ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; - #address-cells = <2>; - #size-cells = <2>; - dma-ranges; - ti,sci-dev-id = <198>; - - inta_main_dmss_csi: interrupt-controller@4e400000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x4e400000 0x00 0x8000>; - #interrupt-cells = <0>; - interrupt-controller; - interrupt-parent = <&gic500>; - msi-controller; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <200>; - ti,interrupt-ranges = <0 237 8>; - ti,unmapped-event-sources = <&main_bcdma_csi>; - }; - - main_bcdma_csi: dma-controller@4e230000 { - compatible = "ti,am62a-dmss-bcdma-csirx"; - reg = <0x00 0x4e230000 0x00 0x100>, - <0x00 0x4e180000 0x00 0x8000>, - <0x00 0x4e100000 0x00 0x10000>; - reg-names = "gcfg", "rchanrt", "ringrt"; - #dma-cells = <3>; - msi-parent = <&inta_main_dmss_csi>; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <199>; - ti,sci-rm-range-rchan = <0x21>; - }; - }; - - dmsc: system-controller@44043000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - mbox-names = "rx", "tx"; - mboxes = <&secure_proxy_main 12>, - <&secure_proxy_main 13>; - reg-names = "debug_messages"; - reg = <0x00 0x44043000 0x00 0xfe0>; - bootph-all; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - bootph-all; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - bootph-all; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - bootph-all; - }; - }; - - crypto: crypto@40900000 { - compatible = "ti,am62-sa3ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - - dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, - <&main_pktdma 0x7507 0>; - dma-names = "tx", "rx1", "rx2"; - }; - - secure_proxy_sa3: mailbox@43600000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - bootph-all; - }; - - main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - bootph-all; - }; - - main_esm: esm@420000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x420000 0x00 0x1000>; - ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; - bootph-pre-ram; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 36 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 36 2>; - assigned-clock-parents = <&k3_clks 36 3>; - power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - bootph-all; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 37 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 37 2>; - assigned-clock-parents = <&k3_clks 37 3>; - power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 38 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 38 2>; - assigned-clock-parents = <&k3_clks 38 3>; - power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 39 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 39 2>; - assigned-clock-parents = <&k3_clks 39 3>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 40 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 40 2>; - assigned-clock-parents = <&k3_clks 40 3>; - power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 41 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 41 2>; - assigned-clock-parents = <&k3_clks 41 3>; - power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 42 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 42 2>; - assigned-clock-parents = <&k3_clks 42 3>; - power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = ; - clocks = <&k3_clks 43 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 43 2>; - assigned-clock-parents = <&k3_clks 43 3>; - power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 152 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 154 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 155 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@20000000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20000000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c1: i2c@20010000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20010000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 103 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c2: i2c@20020000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20020000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 104 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c3: i2c@20030000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20030000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_spi0: spi@20100000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x20100000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 141 0>; - status = "disabled"; - }; - - main_spi1: spi@20110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20110000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 142 0>; - status = "disabled"; - }; - - main_spi2: spi@20120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20120000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 143 0>; - status = "disabled"; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <3>; - ti,interrupt-ranges = <0 32 16>; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <190>, <191>, <192>, - <193>, <194>, <195>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <92>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 77 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00601000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <180>, <181>, <182>, - <183>, <184>, <185>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <52>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 78 0>; - clock-names = "gpio"; - }; - - sdhci0: mmc@fa10000 { - compatible = "ti,am64-sdhci-8bit"; - reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; - interrupts = ; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 57 2>; - assigned-clock-parents = <&k3_clks 57 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - ti,clkbuf-sel = <0x7>; - ti,strobe-sel = <0x77>; - ti,trm-icp = <0x8>; - ti,otap-del-sel-legacy = <0x1>; - ti,otap-del-sel-mmc-hs = <0x1>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,itap-del-sel-ddr52 = <0x3>; - status = "disabled"; - }; - - sdhci1: mmc@fa00000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; - interrupts = ; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; - clock-names = "clk_ahb", "clk_xin"; - bus-width = <4>; - ti,clkbuf-sel = <0x7>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - status = "disabled"; - }; - - sdhci2: mmc@fa20000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; - interrupts = ; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; - clock-names = "clk_ahb", "clk_xin"; - bus-width = <4>; - ti,clkbuf-sel = <0x7>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - status = "disabled"; - }; - - usbss0: usb@f900000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>, - <0x00 0x0f908000 0x00 0x400>; - clocks = <&k3_clks 161 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb0: usb@31000000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31000000 0x00 0x50000>; - interrupts = , /* irq.0 */ - ; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,usb2-gadget-lpm-disable; - snps,usb2-lpm-disable; - }; - }; - - usbss1: usb@f910000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>, - <0x00 0x0f918000 0x00 0x400>; - clocks = <&k3_clks 162 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb1: usb@31100000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31100000 0x00 0x50000>; - interrupts = , /* irq.0 */ - ; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,usb2-gadget-lpm-disable; - snps,usb2-lpm-disable; - }; - }; - - fss: bus@fc00000 { - compatible = "simple-bus"; - reg = <0x00 0x0fc00000 0x00 0x70000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@fc40000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x0fc40000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 75 7>; - assigned-clocks = <&k3_clks 75 7>; - assigned-clock-parents = <&k3_clks 75 8>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - cpsw3g: ethernet@8000000 { - compatible = "ti,am642-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x08000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; - clocks = <&k3_clks 13 0>; - assigned-clocks = <&k3_clks 13 3>; - assigned-clock-parents = <&k3_clks 13 11>; - clock-names = "fck"; - power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - - dmas = <&main_pktdma 0xc600 15>, - <&main_pktdma 0xc601 15>, - <&main_pktdma 0xc602 15>, - <&main_pktdma 0xc603 15>, - <&main_pktdma 0xc604 15>, - <&main_pktdma 0xc605 15>, - <&main_pktdma 0xc606 15>, - <&main_pktdma 0xc607 15>, - <&main_pktdma 0x4600 15>; - dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", - "tx7", "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel 1>; - mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; - status = "disabled"; - }; - - cpsw_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - phys = <&phy_gmii_sel 2>; - mac-address = [00 00 00 00 00 00]; - status = "disabled"; - }; - }; - - cpsw3g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 13 0>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 13 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - hwspinlock: spinlock@2a000000 { - compatible = "ti,am64-hwspinlock"; - reg = <0x00 0x2a000000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@29000000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29000000 0x00 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster1: mailbox@29010000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29010000 0x00 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster2: mailbox@29020000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29020000 0x00 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster3: mailbox@29030000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29030000 0x00 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - ecap0: pwm@23100000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23100000 0x00 0x100>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 51 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@23110000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23110000 0x00 0x100>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 52 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap2: pwm@23120000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23120000 0x00 0x100>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 53 0>; - clock-names = "fck"; - status = "disabled"; - }; - - main_mcan0: can@20701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20701000 0x00 0x200>, - <0x00 0x20708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@20711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20711000 0x00 0x200>, - <0x00 0x20718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; - clock-names = "hclk", "cclk"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; - }; - - main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; - }; - - main_rti2: watchdog@e020000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e020000 0x00 0x100>; - clocks = <&k3_clks 127 0>; - power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 127 0>; - assigned-clock-parents = <&k3_clks 127 2>; - }; - - main_rti3: watchdog@e030000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e030000 0x00 0x100>; - clocks = <&k3_clks 128 0>; - power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 128 0>; - assigned-clock-parents = <&k3_clks 128 2>; - }; - - main_rti15: watchdog@e0f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e0f0000 0x00 0x100>; - clocks = <&k3_clks 130 0>; - power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 130 0>; - assigned-clock-parents = <&k3_clks 130 2>; - }; - - epwm0: pwm@23000000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23000000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm1: pwm@23010000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23010000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm2: pwm@23020000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23020000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - mcasp0: audio-controller@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b00000 0x00 0x2000>, - <0x00 0x02b08000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 190 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 190 0>; - assigned-clock-parents = <&k3_clks 190 2>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: audio-controller@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b10000 0x00 0x2000>, - <0x00 0x02b18000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 191 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 191 0>; - assigned-clock-parents = <&k3_clks 191 2>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: audio-controller@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b20000 0x00 0x2000>, - <0x00 0x02b28000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 192 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 192 0>; - assigned-clock-parents = <&k3_clks 192 2>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - ti_csi2rx0: ticsi2rx@30102000 { - compatible = "ti,j721e-csi2rx-shim"; - reg = <0x00 0x30102000 0x00 0x1000>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - dmas = <&main_bcdma_csi 0 0x5000 0>; - dma-names = "rx0"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - - cdns_csi2rx0: csi-bridge@30101000 { - compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; - reg = <0x00 0x30101000 0x00 0x1000>; - clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, - <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; - clock-names = "sys_clk", "p_clk", "pixel_if0_clk", - "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; - phys = <&dphy0>; - phy-names = "dphy"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi0_port0: port@0 { - reg = <0>; - status = "disabled"; - }; - - csi0_port1: port@1 { - reg = <1>; - status = "disabled"; - }; - - csi0_port2: port@2 { - reg = <2>; - status = "disabled"; - }; - - csi0_port3: port@3 { - reg = <3>; - status = "disabled"; - }; - - csi0_port4: port@4 { - reg = <4>; - status = "disabled"; - }; - }; - }; - }; - - dphy0: phy@30110000 { - compatible = "cdns,dphy-rx"; - reg = <0x00 0x30110000 0x00 0x1100>; - #phy-cells = <0>; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - vpu: video-codec@30210000 { - compatible = "ti,j721s2-wave521c", "cnm,wave521c"; - reg = <0x00 0x30210000 0x00 0x10000>; - interrupts = ; - clocks = <&k3_clks 204 2>; - power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi deleted file mode 100644 index b973b550eb9d..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Device Tree file for the AM62P MCU domain peripherals - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu { - mcu_pmx0: pinctrl@4084000 { - compatible = "pinctrl-single"; - reg = <0x00 0x04084000 0x00 0x88>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - bootph-all; - }; - - mcu_esm: esm@4100000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins = <0>, <1>, <2>, <85>; - status = "reserved"; - bootph-pre-ram; - }; - - /* - * The MCU domain timer interrupts are routed only to the ESM module, - * and not currently available for Linux. The MCU domain timers are - * of limited use without interrupts, and likely reserved by the ESM. - */ - mcu_timer0: timer@4800000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4800000 0x00 0x400>; - clocks = <&k3_clks 35 2>; - clock-names = "fck"; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer1: timer@4810000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4810000 0x00 0x400>; - clocks = <&k3_clks 48 2>; - clock-names = "fck"; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer2: timer@4820000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4820000 0x00 0x400>; - clocks = <&k3_clks 49 2>; - clock-names = "fck"; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer3: timer@4830000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4830000 0x00 0x400>; - clocks = <&k3_clks 50 2>; - clock-names = "fck"; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_uart0: serial@4a00000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x04a00000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_i2c0: i2c@4900000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x04900000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 2>; - clock-names = "fck"; - status = "disabled"; - }; - - mcu_spi0: spi@4b00000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x04b00000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 147 0>; - status = "disabled"; - }; - - mcu_spi1: spi@4b10000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x04b10000 0x00 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 148 0>; - status = "disabled"; - }; - - mcu_gpio_intr: interrupt-controller@4210000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x04210000 0x00 0x200>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <5>; - ti,interrupt-ranges = <0 104 4>; - }; - - mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x4201000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&mcu_gpio_intr>; - interrupts = <30>, <31>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <24>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 79 0>; - clock-names = "gpio"; - }; - - mcu_rti0: watchdog@4880000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x04880000 0x00 0x100>; - clocks = <&k3_clks 131 0>; - power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 131 0>; - assigned-clock-parents = <&k3_clks 131 2>; - /* Tightly coupled to M4F */ - status = "reserved"; - }; - - mcu_mcan0: can@4e08000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e08000 0x00 0x200>, - <0x00 0x4e00000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - interrupts = , - ; - interrupt-names = "int0", "int1"; - status = "disabled"; - }; - - mcu_mcan1: can@4e18000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e18000 0x00 0x200>, - <0x00 0x4e10000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - interrupts = , - ; - interrupt-names = "int0", "int1"; - status = "disabled"; - }; - - mcu_r5fss0: r5fss@79000000 { - compatible = "ti,am62-r5fss"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x79000000 0x00 0x79000000 0x8000>, - <0x79020000 0x00 0x79020000 0x8000>; - power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - - mcu_r5fss0_core0: r5f@79000000 { - compatible = "ti,am62-r5f"; - reg = <0x79000000 0x00008000>, - <0x79020000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <9>; - ti,sci-proc-ids = <0x03 0xff>; - resets = <&k3_reset 9 1>; - firmware-name = "am62p-mcu-r5f0_0-fw"; - ti,atcm-enable = <0>; - ti,btcm-enable = <1>; - ti,loczrama = <0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi deleted file mode 100644 index c7486fb2a5b4..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include - -thermal_zones: thermal-zones { - main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - main0_crit: main0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - main1_crit: main1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - main2_crit: main2-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi deleted file mode 100644 index 71784e10b4f1..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Device Tree file for the AM62P wakeup domain peripherals - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_wakeup { - wkup_conf: bus@43000000 { - compatible = "simple-bus"; - reg = <0x00 0x43000000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x43000000 0x20000>; - bootph-all; - - chipid: chipid@14 { - compatible = "ti,am654-chipid"; - reg = <0x14 0x4>; - bootph-all; - }; - - cpsw_mac_syscon: ethernet-mac-syscon@200 { - compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; - reg = <0x200 0x8>; - }; - - usb0_phy_ctrl: syscon@4008 { - compatible = "ti,am62-usb-phy-ctrl", "syscon"; - reg = <0x4008 0x4>; - }; - - usb1_phy_ctrl: syscon@4018 { - compatible = "ti,am62-usb-phy-ctrl", "syscon"; - reg = <0x4018 0x4>; - }; - }; - - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_i2c0: i2c@2b200000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2b200000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 4>; - clock-names = "fck"; - status = "disabled"; - }; - - wkup_rtc0: rtc@2b1f0000 { - compatible = "ti,am62-rtc"; - reg = <0x00 0x2b1f0000 0x00 0x100>; - interrupts = ; - clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; - clock-names = "vbus", "osc32k"; - power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; - wakeup-source; - }; - - wkup_rti0: watchdog@2b000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2b000000 0x00 0x100>; - clocks = <&k3_clks 132 0>; - power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 132 0>; - assigned-clock-parents = <&k3_clks 132 2>; - /* Used by DM firmware */ - status = "reserved"; - }; - - wkup_vtm0: temperature-sensor@b00000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0xb00000 0x00 0x400>, - <0x00 0xb01000 0x00 0x400>; - power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - wkup_r5fss0: r5fss@78000000 { - compatible = "ti,am62-r5fss"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x78000000 0x00 0x78000000 0x8000>, - <0x78100000 0x00 0x78100000 0x8000>; - power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - - wkup_r5fss0_core0: r5f@78000000 { - compatible = "ti,am62-r5f"; - reg = <0x78000000 0x00008000>, - <0x78100000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <121>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 121 1>; - firmware-name = "am62-wkup-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 94babc412575..2d11c80107b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -116,10 +116,10 @@ }; }; - #include "k3-am62p-thermal.dtsi" + #include "k3-am62p-j722s-common-thermal.dtsi" }; /* Now include peripherals for each bus segment */ -#include "k3-am62p-main.dtsi" -#include "k3-am62p-mcu.dtsi" -#include "k3-am62p-wakeup.dtsi" +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" -- cgit v1.2.3-58-ga151 From 77044cfb9346d1601bfe8759b7d785c664a73f84 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:54 +0530 Subject: arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi The USB1 instance of USB controller on AM62P is different from the USB1 instance of USB controller on J722S. Thus, move the USB1 instance from the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific "k3-am62p-main.dtsi" file. Include "k3-am62p-main.dtsi" in "k3-am62p.dtsi". Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-3-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 26 ----------------- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 34 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 3 ++ 3 files changed, 37 insertions(+), 26 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index ff97e4a59e3b..870c95081ef5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -662,32 +662,6 @@ }; }; - usbss1: usb@f910000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>, - <0x00 0x0f918000 0x00 0x400>; - clocks = <&k3_clks 162 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb1: usb@31100000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31100000 0x00 0x50000>; - interrupts = , /* irq.0 */ - ; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,usb2-gadget-lpm-disable; - snps,usb2-lpm-disable; - }; - }; - fss: bus@fc00000 { compatible = "simple-bus"; reg = <0x00 0x0fc00000 0x00 0x70000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..9caab7db5440 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the AM62P MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + usbss1: usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 2d11c80107b5..75a15c368c11 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -123,3 +123,6 @@ #include "k3-am62p-j722s-common-main.dtsi" #include "k3-am62p-j722s-common-mcu.dtsi" #include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include AM62P specific peripherals */ +#include "k3-am62p-main.dtsi" -- cgit v1.2.3-58-ga151 From 731626cc3180b263216805f82e006ca1f1df02c3 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:55 +0530 Subject: arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals that are specific to J722S SoC and are not shared with AM62P. The USB1 instance of the USB controller on J722S is different from that on AM62P. Thus, add the USB1 node in "k3-j722s-main.dtsi". Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-4-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 40 +++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi new file mode 100644 index 000000000000..84378fc839d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + usbss1: usb@f920000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x0f920000 0x00 0x100>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb1: usb@31200000{ + compatible = "cdns,usb3"; + reg = <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names = "otg", + "xhci", + "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; +}; -- cgit v1.2.3-58-ga151 From 18fb2b7c8a09ca454709b806efc5c38b8a012ab4 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:56 +0530 Subject: arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in order to reuse the nodes shared with AM62P. Also include the J722S specific "k3-j722s-main.dtsi". Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as: k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes" switch the "k3-j722s.dtsi" file to the same convention. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-5-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 158 ++++++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 9132b0232b0b..705b99e35f05 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,11 +10,133 @@ #include #include -#include "k3-am62p5.dtsi" +#include "k3-pinctrl.h" / { model = "Texas Instruments K3 J722S SoC"; compatible = "ti,j722s"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; cbass_main: bus@f0000 { compatible = "simple-bus"; @@ -74,9 +196,43 @@ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; }; + + #include "k3-am62p-j722s-common-thermal.dtsi" }; +/* Include peripherals shared with AM62P */ +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include J722S specific peripherals */ +#include "k3-j722s-main.dtsi" + /* Main domain overrides */ &inta_main_dmss { -- cgit v1.2.3-58-ga151 From 6f9323f6ad818008fc58d2f804ee4140c1b8424d Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:57 +0530 Subject: arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-6-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ -- cgit v1.2.3-58-ga151 From 628e0a0118e69bed9dad14e7dbd8a8802652f5f2 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:58 +0530 Subject: arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller. Since SERDES and PCIe are not present on AM62P SoC, add the device-tree nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi" file. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-7-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 133 ++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 84378fc839d6..b16f3a7cb109 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -5,7 +5,123 @@ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clk-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; + &cbass_main { + serdes_wiz0: phy@f000000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + serdes_wiz1: phy@f010000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 280 1>; + assigned-clock-parents = <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f010000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb010>; + cdns,no-bar-match-nbits = <64>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + status = "disabled"; + }; + usbss1: usb@f920000 { compatible = "ti,j721e-usb"; reg = <0x00 0x0f920000 0x00 0x100>; @@ -38,3 +154,20 @@ }; }; }; + +&main_conf { + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x14>; + #mux-control-cells = <1>; + mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ + <0x10 0x3>; /* SERDES1 lane0 select */ + }; +}; + +&wkup_conf { + pcie0_ctrl: pcie0-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; +}; -- cgit v1.2.3-58-ga151 From 485705df5d5fc0ad6bc5b3657fa63a96a421770d Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:45:59 +0530 Subject: arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0 of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to interface with the Type-C port via the USB hub, by configuring the pin P05 of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed mode of operation with Lane 0 of the SERDES0 instance of SERDES. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-8-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 +++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index bf3c246d13d1..253b02f0437d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; #include +#include #include "k3-j722s.dtsi" +#include "k3-serdes.h" / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; &cpsw3g { @@ -301,6 +309,13 @@ "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; }; }; @@ -384,3 +399,61 @@ status = "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states = , + ; +}; + +&serdes0 { + status = "okay"; + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + status = "okay"; + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; -- cgit v1.2.3-58-ga151 From ed07d82f9e3e8220d8e2f92afd323d718b860f21 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sat, 15 Jun 2024 13:46:00 +0530 Subject: arm64: dts: ti: k3-am62p-j722s: Move SoC-specific node properties Certain device-tree node properties of shared device-tree nodes are different between the AM62P and J722S SoCs. To avoid overriding the properties and to avoid redefining the nodes in the k3-{soc}-main.dtsi having such SoC specific properties, move the properties to the SoC specific k3-{soc}-main.dtsi files. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros Link: https://lore.kernel.org/r/20240615081600.3602462-9-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 5 ----- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 19 ------------------- 4 files changed, 34 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 870c95081ef5..e787f9386eb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -8,10 +8,8 @@ &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x10000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x10000>; }; gic500: interrupt-controller@1800000 { @@ -92,7 +90,6 @@ msi-controller; ti,sci = <&dmsc>; ti,sci-dev-id = <28>; - ti,interrupt-ranges = <5 69 35>; ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; }; @@ -539,7 +536,6 @@ <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <92>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; @@ -556,7 +552,6 @@ <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <52>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 9caab7db5440..f8a7f0cbd327 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -32,3 +32,20 @@ }; }; }; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x10000>; + ranges = <0x00 0x00 0x70000000 0x10000>; +}; + +&inta_main_dmss { + ti,interrupt-ranges = <5 69 35>; +}; + +&main_gpio0 { + ti,ngpio = <92>; +}; + +&main_gpio1 { + ti,ngpio = <52>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index b16f3a7cb109..228c6c89245c 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -171,3 +171,20 @@ reg = <0x4070 0x4>; }; }; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&main_gpio0 { + ti,ngpio = <87>; +}; + +&main_gpio1 { + ti,ngpio = <73>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 705b99e35f05..14c6c6a332ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -232,22 +232,3 @@ /* Include J722S specific peripherals */ #include "k3-j722s-main.dtsi" - -/* Main domain overrides */ - -&inta_main_dmss { - ti,interrupt-ranges = <7 71 21>; -}; - -&main_gpio0 { - ti,ngpio = <87>; -}; - -&main_gpio1 { - ti,ngpio = <73>; -}; - -&oc_sram { - reg = <0x00 0x70000000 0x00 0x40000>; - ranges = <0x00 0x00 0x70000000 0x40000>; -}; -- cgit v1.2.3-58-ga151 From 175133a32b48a092363828ce3041a0adaab01ffc Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 14 Jun 2024 18:05:32 +0530 Subject: arm64: dts: ti: k3-am62x-sk-common: Add bootph-all for I2C1 instance pinmux I2C1 controller controls io-expander which provides power to voltage regulator vdd_mmc1 for MMC SD using a gpio line. Add bootph-all to the pinmux node for this instance, as this is used during SPL stage too by the bootloader while using SD boot mode as without this the SD boot mode fails with below error when using this device-tree in u-boot: "Timed out in wait_for_event: status=0000 Check if pads/pull-ups of bus are properly configured Timed out in wait_for_event: status=0000 Check if pads/pull-ups of bus are properly configured " Signed-off-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20240614123532.203983-1-devarsht@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index f4948b937627..ce7ab338f468 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -160,6 +160,7 @@ }; main_i2c1_pins_default: main-i2c1-default-pins { + bootph-all; pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ -- cgit v1.2.3-58-ga151 From 5fb89782a9e94936c14f2621637ef9df7c4ac0f0 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Fri, 14 Jun 2024 15:38:29 +0530 Subject: arm64: dts: ti: k3-am642-evm: Enable "SYNC_OUT0" output The IEP0 SYNC_OUT0 pins are used for PPS out on AM64 EVM. Configure its PINMUX here. Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20240614100829.3919008-1-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 9f691ed97791..6bb1ad2e56ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -466,6 +466,12 @@ AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ >; }; + + icssg1_iep0_pins_default: icssg1-iep0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ + >; + }; }; &main_uart0 { @@ -821,3 +827,8 @@ &gpmc0 { ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ }; + +&icssg1_iep0 { + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_iep0_pins_default>; +}; -- cgit v1.2.3-58-ga151 From 2510bca4810801c98260e0975c13cf2306d28e96 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 18 Jun 2024 10:01:33 +0100 Subject: arm64: dts: exynos: gs101-oriole: add placeholder regulators for USB phy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The USB phy requires various power supplies to work. While we don't have a PMIC driver yet, the supplies should still be added to the DT. Add some placeholders, which will be replaced with the real ones once we implement PMIC. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240618-gs101-usb-regulators-in-dt-v3-1-6a749207052e@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index b10bde2ec716..387fb779bd29 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -145,6 +145,13 @@ }; &usbdrd31_phy { + /* TODO: Update these once PMIC is implemented */ + pll-supply = <®_placeholder>; + dvdd-usb20-supply = <®_placeholder>; + vddh-usb20-supply = <®_placeholder>; + vdd33-usb20-supply = <®_placeholder>; + vdda-usbdp-supply = <®_placeholder>; + vddh-usbdp-supply = <®_placeholder>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 8373767b94e16652a3453e3ba2ac9ebd32d1949e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 18 May 2024 22:39:02 +0200 Subject: dt-bindings: arm: arm,juno-fpga-apb-regs: document FPGA syscon Add dedicated bindings for the FPGA syscon registers on ARM Juno board, to fully document the block and also fix dtbs_check warning: juno.dtb: apbregs@10000: compatible: ['syscon', 'simple-mfd'] is too short Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240518203903.119608-1-krzysztof.kozlowski@linaro.org Signed-off-by: Sudeep Holla --- .../bindings/arm/arm,juno-fpga-apb-regs.yaml | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml new file mode 100644 index 000000000000..ce5f2e1ec1ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Juno FPGA APB Registers + +maintainers: + - Sudeep Holla + +properties: + compatible: + items: + - const: arm,juno-fpga-apb-regs + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "^led@[0-9a-f]+,[0-9a-f]$": + $ref: /schemas/leds/register-bit-led.yaml# + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + syscon@10000 { + compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd"; + reg = <0x010000 0x1000>; + ranges = <0x0 0x10000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "vexpress:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; -- cgit v1.2.3-58-ga151 From 850888d2d978d6af6f170d14a029a634c2d66336 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 18 May 2024 22:39:03 +0200 Subject: arm64: dts: juno: add dedicated FPGA syscon compatible Each syscon node must come with a dedicated/specific compatible, which is also reported by dtbs_check: juno.dtb: apbregs@10000: compatible: ['syscon', 'simple-mfd'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240518203903.119608-2-krzysztof.kozlowski@linaro.org Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index be42932f7e21..6ca73f41408d 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -158,7 +158,8 @@ }; apbregs@10000 { - compatible = "syscon", "simple-mfd"; + compatible = "arm,juno-fpga-apb-regs", + "syscon", "simple-mfd"; reg = <0x010000 0x1000>; ranges = <0x0 0x10000 0x1000>; #address-cells = <1>; -- cgit v1.2.3-58-ga151 From 75895aa2bc1e0dbf062a33ec1f754ef6801d64dd Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 19 Jun 2024 16:31:37 +0100 Subject: arm64: dts: juno: Enable GPU Both Mali-T620 and Juno's HDLCD are now supported by upstream Mesa in recent distros, so there's little reason not to enable the GPU by default. At the very least it should offer a little extra CI coverage for Panfrost probing and wiggling SCMI. Signed-off-by: Robin Murphy Acked-by: Liviu Dudau Link: https://lore.kernel.org/r/07e45a015ff8934c4571617c8e8e90205e430eb6.1718811097.git.robin.murphy@arm.com Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 98ed2b329ed6..055764d0b9e5 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -663,7 +663,6 @@ dma-coherent; /* The SMMU is only really of interest to bare-metal hypervisors */ /* iommus = <&smmu_gpu 0>; */ - status = "disabled"; }; sram: sram@2e000000 { -- cgit v1.2.3-58-ga151 From 1ef3a30f4dc953a8da7aa68ee4658dc7c3710aac Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 14 Jun 2024 02:43:42 +0300 Subject: arm64: dts: qcom: sdm845: describe connections of USB/DP port Describe links between the first USB3 host and the DisplayPort that is routed to the same pins. Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240614-yoga-ec-driver-v7-5-9f0b9b40ae76@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 53 +++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index a0125f3d92b2..23b101bb3842 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4031,6 +4031,35 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; usb_2_qmpphy: phy@88eb000 { @@ -4111,6 +4140,26 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -4601,7 +4650,9 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; }; }; -- cgit v1.2.3-58-ga151 From 060a1ebd91c1f1bdce8433d559f214204b835add Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 14 Jun 2024 02:43:43 +0300 Subject: arm64: dts: qcom: c630: Add Embedded Controller node The Embedded Controller in the Lenovo Yoga C630 is accessible on &i2c1 and provides battery and adapter status, as well as altmode notifications for the second USB Type-C port. Add a definition for the EC. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240614-yoga-ec-driver-v7-6-9f0b9b40ae76@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 8402ea2d93a7..f18050848cd8 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -370,6 +370,66 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + + embedded-controller@70 { + compatible = "lenovo,yoga-c630-ec"; + reg = <0x70>; + + interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&ec_int_state>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + ucsi0_sbu: endpoint { + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + /* + * connected to the onboard USB hub, orientation is + * handled by the controller + */ + }; + }; }; &i2c3 { @@ -695,6 +755,13 @@ bias-disable; }; + + ec_int_state: ec-int-state { + pins = "gpio20"; + function = "gpio"; + + bias-disable; + }; }; &uart6 { @@ -742,6 +809,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi0_hs_in>; +}; + &usb_1_hsphy { status = "okay"; @@ -762,6 +833,10 @@ vdda-pll-supply = <&vdda_usb1_ss_core>; }; +&usb_1_qmpphy_out { + remote-endpoint = <&ucsi0_ss_in>; +}; + &usb_2 { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 831f66d3423c22457ec1d686e565e152b10fbd91 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 14 Jun 2024 13:18:26 +0300 Subject: arm64: dts: qcom: sm8450: drop second clock name from clock-output-names There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. The driver generates it on its own, in order to remain compatible with the older DT. Drop the clock name. Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-3-730d1811acf4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1e762cc8085a..9bafb3b350ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2087,7 +2087,7 @@ "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + clock-output-names = "pcie_1_pipe_clk"; #clock-cells = <1>; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From 84ea430eb0719ebe4c423bdc9c92e0f94a46a47e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 14 Jun 2024 13:18:27 +0300 Subject: arm64: dts: qcom: sm8550: drop second clock name from clock-output-names There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. The driver generates it on its own, in order to remain compatible with the older DT. Drop the clock name. Fixes: 0cc97d9e3fdf ("arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-4-730d1811acf4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4234c92aafe3..be4f0609c436 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1939,7 +1939,7 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; #clock-cells = <1>; - clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; + clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From dc323623c3b87c48c99fe8dbbd1962f0129d3da9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 14 Jun 2024 13:18:28 +0300 Subject: arm64: dts: qcom: sm8650: drop second clock name from clock-output-names There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. The driver generates it on its own, in order to remain compatible with the older DT. Drop the clock name. Fixes: d00b42f170df ("arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-5-730d1811acf4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 5b8b1d581a13..5df2e00fdb5b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2474,7 +2474,7 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; #clock-cells = <1>; - clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; + clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; -- cgit v1.2.3-58-ga151 From 99e94768c890c7522af020ff0e5e5317b2d046d9 Mon Sep 17 00:00:00 2001 From: "Nícolas F. R. A. Prado" Date: Fri, 14 Jun 2024 16:59:36 -0400 Subject: arm64: dts: qcom: sc7180-trogdor: Disable pwmleds node where unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the keyboard backlight is described in the common sc7180-trogdor dtsi as an led node below a pwmleds node, and the led node is set to disabled. Only the boards that have a keyboard backlight enable it. However, since the parent pwmleds node is still enabled everywhere, even on boards that don't have keyboard backlight it is probed and fails, resulting in an error: leds_pwm pwmleds: probe with driver leds_pwm failed with error -22 as well as a failure in the DT kselftest: not ok 45 /pwmleds Fix this by controlling the status of the parent pwmleds node instead of the child led, based on the presence of keyboard backlight. This is what is done on sc7280 already. While at it add a missing blank line before the child node to follow the coding style. Fixes: 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: Konrad Dybcio Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240614-sc7180-pwmleds-probe-v1-1-e2c3f1b42a43@collabora.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 5 +++-- 9 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts index 919bfaea6189..340cb119d0a0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts @@ -12,6 +12,6 @@ compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index eb20157f6af9..d45e60e3eb9e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -17,6 +17,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts index 45d34718a1bc..e906ce877b8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts @@ -18,6 +18,6 @@ compatible = "google,lazor-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts index 79028d0dd1b0..4b9ee15b09f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts @@ -22,6 +22,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index 3459b81c5628..a960553f3994 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -21,6 +21,6 @@ "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index ff8f47da109d..82bd9ed7e21a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -25,6 +25,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts index faf527972977..6278c1715d3f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -18,6 +18,6 @@ compatible = "google,lazor-rev9-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index d737fd0637fb..0ec1697ae2c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -22,6 +22,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 4d33c3fbedff..74ab321d3333 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -356,10 +356,11 @@ #sound-dai-cells = <0>; }; - pwmleds { + pwmleds: pwmleds { compatible = "pwm-leds"; + status = "disabled"; + keyboard_backlight: led-0 { - status = "disabled"; label = "cros_ec::kbd_backlight"; function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; -- cgit v1.2.3-58-ga151 From 367fb3f0aaa6eac9101dc683dd27c268b4cc702e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 18 Jun 2024 14:57:11 +0530 Subject: arm64: dts: qcom: qdu1000: Add secure qfprom node Add secure qfprom node and also add properties for multi channel DDR. This is required for LLCC driver to pick the correct LLCC configuration. Fixes: 6209038f131f ("arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller") Signed-off-by: Komal Bajaj Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Ojha Link: https://lore.kernel.org/r/20240618092711.15037-1-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 7a77f7a55498..27f9fc87079c 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1584,6 +1584,21 @@ reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; + + nvmem-cells = <&multi_chan_ddr>; + nvmem-cell-names = "multi-chan-ddr"; + }; + + sec_qfprom: efuse@221c8000 { + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + multi_chan_ddr: multi-chan-ddr@12b { + reg = <0x12b 0x1>; + bits = <0 2>; + }; }; }; -- cgit v1.2.3-58-ga151 From 4c3849513fa1b4d9f6fbe08ecd65e2d6ae19c1fb Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 18 Jun 2024 15:30:54 +0200 Subject: arm64: dts: qcom: qcm6490-fairphone-fp5: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240618-qcm6490-regulator-name-v1-1-69fa05e9f58e@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 25ed74d4ebd2..c66c7eda6a69 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -271,46 +271,54 @@ qcom,pmic-id = "b"; vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s7b: smps7 { + regulator-name = "vreg_s7b"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b: smps8 { + regulator-name = "vreg_s8b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; /* Constrained for UFS VCC, at least until UFS driver scales voltage */ regulator-min-microvolt = <2952000>; regulator-max-microvolt = <2952000>; @@ -318,66 +326,77 @@ }; vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -389,60 +408,70 @@ qcom,pmic-id = "c"; vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; regulator-initial-mode = ; }; vreg_s9c: smps9 { + regulator-name = "vreg_s9c"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; regulator-initial-mode = ; }; vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1950000>; regulator-initial-mode = ; }; vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3400000>; regulator-initial-mode = ; }; vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -451,36 +480,42 @@ }; vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c: ldo11 { + regulator-name = "vreg_l11c"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob: bob { + regulator-name = "vreg_bob"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; regulator-initial-mode = ; -- cgit v1.2.3-58-ga151 From e160c41b96b6d6f38b8646e3c914c630da21e105 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 18 Jun 2024 15:30:55 +0200 Subject: arm64: dts: qcom: qcm6490-shift-otter: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Caleb Connolly Link: https://lore.kernel.org/r/20240618-qcm6490-regulator-name-v1-2-69fa05e9f58e@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index e82938cab953..4667e47a74bc 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -235,46 +235,54 @@ qcom,pmic-id = "b"; vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s7b: smps7 { + regulator-name = "vreg_s7b"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b: smps8 { + regulator-name = "vreg_s8b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; /* Constrained for UFS VCC, at least until UFS driver scales voltage */ regulator-min-microvolt = <2952000>; regulator-max-microvolt = <2952000>; @@ -282,66 +290,77 @@ }; vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -353,96 +372,112 @@ qcom,pmic-id = "c"; vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; regulator-initial-mode = ; }; vreg_s9c: smps9 { + regulator-name = "vreg_s9c"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; regulator-initial-mode = ; }; vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1950000>; regulator-initial-mode = ; }; vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3400000>; regulator-initial-mode = ; }; vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c: ldo11 { + regulator-name = "vreg_l11c"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob: bob { + regulator-name = "vreg_bob"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; regulator-initial-mode = ; -- cgit v1.2.3-58-ga151 From a39e850037fa520b3e089d4d11b3c3baef4de41e Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Wed, 19 Jun 2024 11:15:29 +0000 Subject: arm64: dts: qcom: msm8916-gplus-fl8005a: Add sound and modem Enable sound and modem for the GPLUS FL8005A. The setup is similar to most MSM8916 devices, i.e.: - QDSP6 audio - Earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX Signed-off-by: Lin, Meng-Bo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619111523.54301-1-linmengbo06890@proton.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index b748d140b52e..e6ed5544a11b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" #include #include @@ -111,6 +112,17 @@ status = "okay"; }; +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5000000>; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <150 180 237 450 500>; + qcom,mbhc-vthreshold-high = <150 180 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + &pm8916_resin { linux,code = ; status = "okay"; @@ -141,6 +153,14 @@ status = "okay"; }; +&sound { + model = "msm8916-1mic"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; +}; + &usb { extcon = <&usb_id>, <&usb_id>; status = "okay"; -- cgit v1.2.3-58-ga151 From 4908128724491de1feadee87aba9955eccaf5269 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 5 Jun 2024 14:27:26 +0200 Subject: arm64: dts: qcom: sm8550-qrd: add the Wifi node Describe the ath12k WLAN on-board the WCN7850 module present on the board. [Neil: authored the initial version of the change] Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Tested-by: Amit Pundir Tested-by: Neil Armstrong # on SM8550-QRD Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240605122729.24283-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 97 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 2 files changed, 98 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index d27820fb5fc0..361b0792db4f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -214,6 +214,68 @@ regulator-always-on; regulator-boot-on; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&pmk8550_sleep_clk>; + + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s5g_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s2g_0p85>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p8-supply = <&vreg_s6g_1p86>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -808,6 +870,23 @@ status = "okay"; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; @@ -891,6 +970,17 @@ status = "okay"; }; +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -1064,6 +1154,13 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index be4f0609c436..4c9820adcf52 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1784,7 +1784,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; -- cgit v1.2.3-58-ga151 From a05737bf76316677ae1d7af93df6218dcf1ae494 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 5 Jun 2024 14:27:27 +0200 Subject: arm64: dts: qcom: sm8650-qrd: add the Wifi node Describe the ath12k WLAN on-board the WCN7850 module present on the board. [Neil: authored the initial version of the change] Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240605122729.24283-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 89 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 98f6a272ce5a..6e3c4d8dcc19 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -203,6 +203,71 @@ }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -844,6 +909,23 @@ status = "okay"; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -1138,6 +1220,13 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; &uart14 { diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 5df2e00fdb5b..8af151d924f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2300,7 +2300,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; -- cgit v1.2.3-58-ga151 From 4d76a2314810b78b0469c96bcb265af1af7e13a5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 5 Jun 2024 14:27:28 +0200 Subject: arm64: dts: qcom: sm8650-hdk: add the Wifi node Describe the ath12k WLAN on-board the WCN7850 module present on the board. Signed-off-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240605122729.24283-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 89 +++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 5887d265a077..eb2f910b4f58 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -266,6 +266,71 @@ #sound-dai-cells = <1>; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -893,6 +958,23 @@ status = "okay"; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -1155,6 +1237,13 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; &uart14 { -- cgit v1.2.3-58-ga151 From bd37ce2eeb84cd42ec8edebaa3cb8cffade2dc0c Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 5 Jun 2024 14:27:29 +0200 Subject: arm64: dts: qcom: qrb5165-rb5: add the Wifi node Add a node for the PMU module of the QCA6391 present on the RB5 board. Assign its LDO power outputs to the existing Bluetooth module. Add a node for the PCIe port to sm8250.dtsi and define the WLAN node on it in the board's .dts and also make it consume the power outputs of the PMU. Tested-by: Caleb Connolly # OnePlus 8T Signed-off-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240605122729.24283-5-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 103 +++++++++++++++++++++++++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 2 files changed, 93 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index f22821c13367..ccff6cd73fdf 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -108,6 +108,67 @@ regulator-always-on; }; + qca6390-pmu { + compatible = "qcom,qca6390-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + + vddaon-supply = <&vreg_s6a_0p95>; + vddpmu-supply = <&vreg_s2f_0p95>; + vddrfa0p95-supply = <&vreg_s2f_0p95>; + vddrfa1p3-supply = <&vreg_s8c_1p3>; + vddrfa1p9-supply = <&vreg_s5a_1p9>; + vddpcie1p3-supply = <&vreg_s8c_1p3>; + vddpcie1p9-supply = <&vreg_s5a_1p9>; + vddio-supply = <&vreg_s4a_1p8>; + + wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; + thermal-zones { conn-thermal { thermal-sensors = <&pm8150b_adc_tm 0>; @@ -724,6 +785,23 @@ vdda-pll-supply = <&vreg_l9a_1p2>; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1101"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie1 { status = "okay"; }; @@ -1293,6 +1371,14 @@ function = "gpio"; bias-pull-up; }; + + wlan_en_state: wlan-default-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; }; &uart6 { @@ -1301,17 +1387,12 @@ bluetooth { compatible = "qcom,qca6390-bt"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_en_state>; - - enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; - - vddio-supply = <&vreg_s4a_1p8>; - vddpmu-supply = <&vreg_s2f_0p95>; - vddaon-supply = <&vreg_s6a_0p95>; - vddrfa0p9-supply = <&vreg_s2f_0p95>; - vddrfa1p3-supply = <&vreg_s8c_1p3>; - vddrfa1p9-supply = <&vreg_s5a_1p9>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7a8b1ba2deb0..9d6c97d1fd9d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2204,7 +2204,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; -- cgit v1.2.3-58-ga151 From 38b55ddb4a9f364b68cb1db174cadfae7cf4696e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 17 Jun 2024 17:26:24 +0530 Subject: arm64: dts: qcom: qdu1000: fix usb interrupts properties Update the usb interrupts properties to fix the following bindings check errors: usb@a6f8800: interrupt-names:0: 'pwr_event' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:1: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names: ['hs_phy_irq', 'ss_phy_irq', 'dm_hs_phy_irq', 'dp_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# Fixes: dd1bd5bf7420 ("arm64: dts: qcom: qdu1000: Add USB3 and PHY support") Cc: Krishna Kurapati Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406171241.YKuCm3SC-lkp@intel.com/ Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240617115624.29875-1-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 27f9fc87079c..31329cbe0976 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -976,13 +976,15 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 8 IRQ_TYPE_EDGE_RISING>, - <&pdc 9 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq"; + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; -- cgit v1.2.3-58-ga151 From 6d97b93acf9d0b29d3eddf38186d9556e5360368 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Tue, 18 Jun 2024 15:21:59 +0800 Subject: dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Document QCS8550 SoC and the AIM300 AIoT board bindings. QCS8550 is derived from SM8550. The difference between SM8550 and QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used in IoT scenarios. AIM300 Series is a highly optimized family of modules designed to support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip etc. AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240618072202.2516025-2-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1be21a16ba36..d839691a900c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | msm8996 msm8998 qcs404 + qcs8550 qcm2290 qcm6490 qdu1000 @@ -1018,6 +1019,13 @@ properties: - sony,pdx234 - const: qcom,sm8550 + - items: + - enum: + - qcom,qcs8550-aim300-aiot + - const: qcom,qcs8550-aim300 + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - qcom,sm8650-hdk -- cgit v1.2.3-58-ga151 From bb8a2dc3bd89628a7f4aac577894d47dd0f4db3c Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Tue, 18 Jun 2024 15:22:00 +0800 Subject: arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi QCS8550 is derived from SM8550. The difference between SM8550 and QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used in IoT products. QCS8550 firmware has different memory map compared to SM8550. The memory map will be runtime added through bootloader. There are 3 types of reserved memory regions here: 1. Firmware related regions which aren't shared with kernel. The device tree source in kernel doesn't need to have node to indicate the firmware related reserved information. Bootloader converys the information by updating devicetree at runtime. This will be described as: UEFI saves the physical address of the UEFI System Table to dts file's chosen node. Kernel read this table and add reserved memory regions to efi config table. Current reserved memory region may have reserved region which was not yet used, release note of the firmware have such kind of information. 2. Firmware related memory regions which are shared with Kernel The device tree source in the kernel needs to include nodes that indicate fimware-related shared information. A label name is suggested because this type of shared information needs to be referenced by specific drivers for handling purposes. Unlike previous platforms, QCS8550 boots using EFI and describes most reserved regions in the ESRT memory map. As a result, reserved memory regions which aren't relevant to the kernel(like the hypervisor region) don't need to be described in DT. 3. Remoteproc regions. Remoteproc regions will be reserved and then assigned to subsystem firmware later. Here is a reserved memory map for this platform: 0x80000000 +-------------------+ | | | Firmware Related | | | 0x8a800000 +-------------------+ | | | Remoteproc Region | | | 0xa7000000 +-------------------+ | | | Kernel Available | | | 0xd4d00000 +-------------------+ | | | Firmware Related | | | 0x100000000 +-------------------+ Reviewed-by: Dmitry Baryshkov Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240618072202.2516025-3-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8550.dtsi | 162 ++++++++++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi new file mode 100644 index 000000000000..07b314834d88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sm8550.dtsi" + +/delete-node/ &reserved_memory; + +/ { + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + + /* These are 3 types of reserved memory regions here: + * 1. Firmware related regions which aren't shared with kernel. + * The device tree source in kernel doesn't need to have node to + * indicate the firmware related reserved information. Bootloader + * conveys the information by updating devicetree at runtime. + * This will be described as: UEFI saves the physical address of + * the UEFI System Table to dts file's chosen node. Kernel read this + * table and add reserved memory regions to efi config table. Current + * reserved memory region may have reserved region which was not yet + * used, release note of the firmware have such kind of information. + * 2. Firmware related memory regions which are shared with Kernel + * The device tree source in the kernel needs to include nodes + * that indicate fimware-related shared information. A label name + * is suggested because this type of shared information needs to + * be referenced by specific drivers for handling purposes. + * Unlike previous platforms, QCS8550 boots using EFI and describes + * most reserved regions in the ESRT memory map. As a result, reserved + * memory regions which aren't relevant to the kernel(like the hypervisor + ( region) don't need to be described in DT. + * 3. Remoteproc regions. + * Remoteproc regions will be reserved and then assigned to + * subsystem firmware later. + * Here is a reserved memory map for this platform: + * 0x80000000 +-------------------+ + * | | + * | Firmware Related | + * | | + * 0x8a800000 +-------------------+ + * | | + * | Remoteproc Region | + * | | + * 0xa7000000 +-------------------+ + * | | + * | Kernel Available | + * | | + * 0xd4d00000 +-------------------+ + * | | + * | Firmware Related | + * | | + * 0x100000000 +-------------------+ + */ + + aop_image_mem: aop-image-region@81c00000 { + reg = <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x20000>; + }; + + smem_mem: smem-region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg = <0x0 0x8a800000 0x0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg = <0x0 0x9b000000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg = <0x0 0x9b080000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg = <0x0 0x9b090000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg = <0x0 0x9b09a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg = <0x0 0x9b100000 0x0 0x180000>; + no-map; + }; + + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 { + reg = <0x0 0x9b280000 0x0 0x80000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg = <0x0 0x9b300000 0x0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg = <0x0 0x9bb00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg = <0x0 0x9c200000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0x0 0x9c900000 0x0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg = <0x0 0x9e900000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg = <0x0 0x9e980000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x4080000>; + no-map; + }; + + mpss_dsm_mem: mpss_dsm_region@d4d00000 { + reg = <0x0 0xd4d00000 0x0 0x3300000>; + no-map; + }; + }; +}; -- cgit v1.2.3-58-ga151 From 0b12da4e28d8f6ecb492c98313e325eff11b5bb8 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Tue, 18 Jun 2024 15:22:01 +0800 Subject: arm64: dts: qcom: add base AIM300 dtsi AIM300 Series is a highly optimized family of modules designed to support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip etc. Here is a diagram of AIM300 SoM: +----------------------------------------+ |AIM300 SoM | | | | +-----+ | | |--->| UFS | | | | +-----+ | | | | | | | 3.7v | +-----------------+ | +---------+ | ---------->| PMIC |----->| QCS8550 | | | +-----------------+ +---------+ | | | | | | | | | +-----+ | | |--->| ... | | | +-----+ | | | +----------------------------------------+ Co-developed-by: Fenglin Wu Signed-off-by: Fenglin Wu Reviewed-by: Dmitry Baryshkov Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240618072202.2516025-4-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 405 +++++++++++++++++++++++++++ 1 file changed, 405 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi new file mode 100644 index 000000000000..f6960e2d466a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = ; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; +}; + +&pcie0 { + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; +}; + +&pcie1 { + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_hsphy { + phys = <&pm8550b_eusb2_repeater>; + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- cgit v1.2.3-58-ga151 From e7931a52c7b68fb5143e118778092a23cfc5b0fc Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Tue, 18 Jun 2024 15:22:02 +0800 Subject: arm64: dts: qcom: aim300: add AIM300 AIoT Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe, I2C functions support. Here is a diagram of AIM300 AIoT Carrie Board and SoM +--------------------------------------------------+ | AIM300 AIOT Carrier Board | | | | +-----------------+ | |power----->| Fixed regulator |---------+ | | +-----------------+ | | | | | | v VPH_PWR | | +----------------------------------------------+ | | | AIM300 SOM | | | | | |VPH_PWR | | | | v | | | | +-------+ +--------+ +------+ | | | | | UFS | | QCS8550| |PMIC | | | | | +-------+ +--------+ +------+ | | | | | | | +----------------------------------------------+ | | | | +----+ +------+ | | |USB | | UART | | | +----+ +------+ | +--------------------------------------------------+ Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Ziyue Zhang Signed-off-by: Ziyue Zhang Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20240618072202.2516025-5-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts | 315 +++++++++++++++++++++++ 2 files changed, 316 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0c1cebd16649..5576c7d6ea06 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts new file mode 100644 index 000000000000..2e2e46f214c7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include "qcs8550-aim300.dtsi" +#include "pm8010.dtsi" +#include "pmr735d_a.dtsi" +#include "pmr735d_b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT"; + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550", + "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + debounce-interval = <15>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + }; + + regulators-3 { + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + }; + + regulators-4 { + vdd-s4-supply = <&vph_pwr>; + }; + + regulators-5 { + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + }; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + + typec-retimer@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0 { + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-0 = <&dsi_active>, <&te_default>; + pinctrl-1 = <&dsi_suspend>, <&te_default>; + pinctrl-names = "default", "sleep"; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8550/adsp.mbn", + "qcom/qcs8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8550/cdsp.mbn", + "qcom/qcs8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&swr1 { + status = "okay"; +}; + +&swr2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + dsi_active: dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + dsi_suspend: dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + te_default: te-default-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_dp_qmpphy { + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; -- cgit v1.2.3-58-ga151 From b5477d5f5272a079e2ddeffd00490528884f5aa5 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Sat, 8 Jun 2024 17:55:26 +0200 Subject: arm64: dts: qcom: sc8280xp-x13s: enable pm8008 camera pmic Enable the PM8008 PMIC which is used to power the camera sensors. Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240608155526.12996-13-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 19efa49240ec..40da95b202da 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -297,6 +297,27 @@ }; thermal-zones { + pm8008-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + skin-temp-thermal { polling-delay-passive = <250>; @@ -670,6 +691,85 @@ }; }; +&i2c11 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_default>; + + status = "okay"; + + pm8008: pmic@c { + compatible = "qcom,pm8008"; + reg = <0xc>; + + interrupts-extended = <&tlmm 41 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 42 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s11b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1q: ldo1 { + regulator-name = "vreg_l1q"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2q: ldo2 { + regulator-name = "vreg_l2q"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3q: ldo3 { + regulator-name = "vreg_l3q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l4q: ldo4 { + regulator-name = "vreg_l4q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l5q: ldo5 { + regulator-name = "vreg_l5q"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6q: ldo6 { + regulator-name = "vreg_l6q"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l7q: ldo7 { + regulator-name = "vreg_l7q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; +}; + &i2c21 { clock-frequency = <400000>; @@ -1355,6 +1455,13 @@ bias-disable; }; + i2c11_default: i2c11-default-state { + pins = "gpio18", "gpio19"; + function = "qup11"; + drive-strength = <16>; + bias-disable; + }; + i2c21_default: i2c21-default-state { pins = "gpio81", "gpio82"; function = "qup21"; @@ -1458,6 +1565,22 @@ }; }; + pm8008_default: pm8008-default-state { + int-pins { + pins = "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-n-pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + spkr_1_sd_n_default: spkr-1-sd-n-default-state { perst-n-pins { pins = "gpio178"; -- cgit v1.2.3-58-ga151 From 11926848eb550ea3018ad9e14761785a6f7f25df Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Tue, 18 Jun 2024 18:11:13 +0530 Subject: arm64: dts: ti: k3-am62a-main: Enable crypto accelerator Add the node for sa3ul crypto accelerator. Signed-off-by: Jayesh Choudhary Signed-off-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20240617-crytpo-am62a-v2-1-dc7a14f2635b@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index ce4a2f105630..08b3aea1d30f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -216,6 +216,14 @@ }; }; + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + secure_proxy_sa3: mailbox@43600000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; -- cgit v1.2.3-58-ga151 From b6861f152b4bf6f194b5e5162ee238f2c97e5aec Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Wed, 19 Jun 2024 15:27:25 +0530 Subject: arm64: dts: ti: k3-am62*-main: Remove unwanted properties from crypto As there is no child node in crypto node, remove the properties that are not needed. Signed-off-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20240618-remove-ranges-v1-1-35d68147e9bf@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 2 -- 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 0f2722c4bcc3..00776a9987c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -207,10 +207,6 @@ crypto: crypto@40900000 { compatible = "ti,am62-sa3ul"; reg = <0x00 0x40900000 0x00 0x1200>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index e787f9386eb5..9701fc69aed9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -227,8 +227,6 @@ reg = <0x00 0x40900000 0x00 0x1200>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; -- cgit v1.2.3-58-ga151 From 532857c2a76ba3553302cf2a2cbec7679fb5b4fe Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:46 -0500 Subject: dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks Add the required clock bindings for the GPADC. Signed-off-by: Chris Morgan Acked-by: Jernej Skrabec Reviewed-by: Andre Przywara Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + include/dt-bindings/reset/sun50i-h616-ccu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 6f8f01e67628..ebb146ab7f8c 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -112,5 +112,6 @@ #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 +#define CLK_BUS_GPADC 129 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index 1bd8bb0a11be..ed177c04afdd 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -66,5 +66,6 @@ #define RST_BUS_TVE0 57 #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 +#define RST_BUS_GPADC 60 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ -- cgit v1.2.3-58-ga151 From 59678cc9cc54e556f83a58c52aaac8c149edab67 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:48 -0500 Subject: arm64: dts: allwinner: h616: Add GPADC device node The H616 has a GPADC controller which is identical to the one found on the D1/T113s/R329/T507 SoCs. Reviewed-by: Andre Przywara Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240605172049.231108-4-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 20564cc02267..b07d7aee1896 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -626,6 +626,17 @@ status = "disabled"; }; + gpadc: adc@5070000 { + compatible = "allwinner,sun50i-h616-gpadc", + "allwinner,sun20i-d1-gpadc"; + reg = <0x05070000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <1>; + }; + ths: thermal-sensor@5070400 { compatible = "allwinner,sun50i-h616-ths"; reg = <0x05070400 0x400>; -- cgit v1.2.3-58-ga151 From e41e5973bf4559b0918c59d243ba8612f070f854 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:49 -0500 Subject: arm64: dts: allwinner: anbernic-rg35xx-h: Add ADC joysticks Add support for the ADC joysticks found on the Anbernic RG35XX-H. The joysticks use one channel of the GPADC which is muxed 4 ways by an ADC mux. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240605172049.231108-5-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- .../allwinner/sun50i-h700-anbernic-rg35xx-h.dts | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts index 63036256917f..ff453336eab1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -9,6 +9,78 @@ / { model = "Anbernic RG35XX H"; compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; + + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_pin>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "left_y", "right_x", "right_y"; + #io-channel-cells = <1>; + io-channels = <&gpadc 0>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&pio 8 1 GPIO_ACTIVE_LOW>, + <&pio 8 2 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; +}; + +&gpadc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + }; }; &gpio_keys_gamepad { @@ -34,3 +106,10 @@ &ohci1 { status = "okay"; }; + +&pio { + joy_mux_pin: joy-mux-pin { + pins = "PI0"; + function = "gpio_out"; + }; +}; -- cgit v1.2.3-58-ga151 From b05f15d0fc15a21ffe480226b02d9352bddfa2e5 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Fri, 7 Jun 2024 21:20:34 +1200 Subject: arm64: dts: allwinner: h616: add additional CPU OPPs for the H700 The H700 now shows stable operation with the 1.008, 1.032 and 1.512 GHz DVFS operating points. The 1.5GHz OPP requires a VDD-CPU of 1.16V, obtained from the vendor BSP. This voltage is slightly above the recommended operating voltage for the H616 (H700 datasheet not publicly available) but well within the absolute maximum of 1.3V. Add the additional 1.032 GHz operating point to the H616 CPU-OPP table, and enable the 1.008 and 1.512 points for the H700. Signed-off-by: Ryan Walklin Tested-by: Philippe Simons Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240607092140.33112-3-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi | 25 ++++++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi index aca22a7f0191..dd10aaf472b6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -11,7 +11,7 @@ opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-600000000 { @@ -25,7 +25,7 @@ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-792000000 { @@ -50,8 +50,16 @@ opp-microvolt-speed2 = <950000>; opp-microvolt-speed3 = <950000>; opp-microvolt-speed4 = <1020000>; + opp-microvolt-speed5 = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; + }; + + opp-1032000000 { + opp-hz = /bits/ 64 <1032000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x20>; }; opp-1104000000 { @@ -59,8 +67,9 @@ opp-microvolt-speed0 = <1000000>; opp-microvolt-speed2 = <1000000>; opp-microvolt-speed3 = <1000000>; + opp-microvolt-speed5 = <950000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1200000000 { @@ -70,8 +79,9 @@ opp-microvolt-speed2 = <1050000>; opp-microvolt-speed3 = <1050000>; opp-microvolt-speed4 = <1100000>; + opp-microvolt-speed5 = <1020000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-1320000000 { @@ -85,15 +95,16 @@ opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-microvolt-speed1 = <1100000>; opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed5 = <1160000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; + opp-supported-hw = <0x2a>; }; }; }; -- cgit v1.2.3-58-ga151 From e1e61fe3452d511e53aa50720833148b11719269 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Fri, 7 Jun 2024 21:20:35 +1200 Subject: arm64: dts: allwinner: rg35xx: Enable DVFS CPU frequency scaling The Anbernic RG35XX device variants (-2024, -H, -Plus and -SP) are the only currently known devices to have an Allwinner H700 SoC. The closely related RG28XX also has the H700 but a mainline DT for this device has not yet been submitted. Include the H616 CPU OPP table in the base device DTS, and increase the DCDC1 regulator (vdd-cpu) upper voltage range to 1.16V, allowing the CPU to reach 1.5GHz. Signed-off-by: Ryan Walklin Tested-by: Philippe Simons Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240607092140.33112-4-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index ee30584b6ad7..afb49e65859f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" - +#include "sun50i-h616-cpu-opp.dtsi" #include #include #include @@ -221,7 +221,7 @@ reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; + regulator-max-microvolt = <1160000>; regulator-name = "vdd-cpu"; }; -- cgit v1.2.3-58-ga151 From 4c54173d5965937b9e8280b7ec900fdec65d0c36 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jun 2024 15:59:56 +0200 Subject: MAINTAINERS: ARM: moxa: add Krzysztof Kozlowski as maintainer There is no maintainers entry for the ARM MOXA ART SoC, thus patches end up nowhere. Add such entry, because even if platform is orphaned and on its way out of the kernel, it is nice to take patches if someone sends something. I do not plan to actively support/maintain MOXA but I can take odd fixes now and then. Cc: Jonas Jensen Link: https://lore.kernel.org/r/20240613135956.8899-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d6c90161c7bf..103b5f335481 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2524,6 +2524,15 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut +ARM/MOXA ART SOC +M: Krzysztof Kozlowski +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Odd Fixes +F: Documentation/devicetree/bindings/arm/moxart.yaml +F: Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt +F: arch/arm/boot/dts/moxa/ +F: drivers/clk/clk-moxart.c + ARM/MStar/Sigmastar Armv7 SoC support M: Daniel Palmer M: Romain Perier -- cgit v1.2.3-58-ga151 From 296c0bb50e31f9077c391e57bf43f3e23a73835e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jun 2024 15:49:10 +0200 Subject: MAINTAINERS: ARM: axm: add Krzysztof Kozlowski as maintainer There is no maintainers entry for the ARM LSI AXM SoC, thus patches end up nowhere. Add such entry, because even if platform is orphaned and on its way out of the kernel, it is nice to take patches if someone sends something. I do not plan to actively support/maintain AXM but I can take odd fixes now and then. Link: https://lore.kernel.org/r/20240613134910.7862-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 103b5f335481..11c5937cca90 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2094,6 +2094,14 @@ F: arch/arm/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ N: aspeed +ARM/AXM LSI SOC +M: Krzysztof Kozlowski +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Odd Fixes +F: Documentation/devicetree/bindings/arm/axxia.yaml +F: arch/arm/boot/dts/intel/axm/ +F: arch/arm/mach-axxia/ + ARM/BITMAIN ARCHITECTURE M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3-58-ga151 From 084e77a12c3a1c255ea0e944e9d77d21c9d2247d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jun 2024 08:46:12 +0200 Subject: MAINTAINERS: ARM: vt8500: add Alexey and Krzysztof as maintainers The ARM VIA/WonderMedia VT8500 platform became orphaned in commit 8f1b7ba55c61 ("MAINTAINERS: ARM/VT8500, remove defunct e-mail") and clearly it is on the way out of the kernel. However few folks send patches to it and it is nice to actually take them, till the platform is in the kernel. Alexey Charkov still has VT8500 hardware and plans to work on upstream, so add Alexey as the maintainer. Krzysztof will collect patches. Extend the maintainer entry to cover also VT8500 DTS. Cc: Alexey Charkov Acked-by: Alexey Charkov Link: https://lore.kernel.org/r/20240613064612.8589-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 11c5937cca90..e3133b443667 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3120,9 +3120,12 @@ W: http://www.armlinux.org.uk/ F: arch/arm/vfp/ ARM/VT8500 ARM ARCHITECTURE +M: Alexey Charkov +M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Orphan +S: Odd Fixes F: Documentation/devicetree/bindings/i2c/i2c-wmt.txt +F: arch/arm/boot/dts/vt8500/ F: arch/arm/mach-vt8500/ F: drivers/clocksource/timer-vt8500.c F: drivers/i2c/busses/i2c-viai2c-wmt.c -- cgit v1.2.3-58-ga151 From 997148228410f8e2fda78b848ae16fdc525158e9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 16:17:40 +0200 Subject: MAINTAINERS: ARM: nspire: add Krzysztof Kozlowski as maintainer Apparently there was never a maintainers entry for the ARM Texas Instruments Nspire SoC, thus patches end up nowhere. Add such entry, because even if platform is orphaned and on its way out of the kernel, it is nice to take patches if someone sends something. I do not plan to actively support/maintain Nspire platform but I can take odd fixes now and then. Cc: Daniel Tang Cc: Andrew Davis Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20240612141740.8470-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e3133b443667..7e91c83a4b0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3051,6 +3051,15 @@ F: Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* +ARM/TEXAS INSTRUMENTS NSPIRE ARCHITECTURE +M: Krzysztof Kozlowski +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Odd Fixes +F: Documentation/devicetree/bindings/*/*/ti,nspire* +F: Documentation/devicetree/bindings/*/ti,nspire* +F: Documentation/devicetree/bindings/arm/ti/nspire.yaml +F: arch/arm/boot/dts/nspire/ + ARM/TOSHIBA VISCONTI ARCHITECTURE M: Nobuhiro Iwamatsu L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3-58-ga151 From af88df12762dab540d02c13324a0767473322f1e Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 12 Jun 2024 10:13:13 -0500 Subject: ARM: dts: nspire: Add unit name addresses to memory nodes Fixes the following DTB check warning: > node has a reg or ranges property, but no unit name Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240612151314.27967-1-afd@ti.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nspire/nspire-classic.dtsi | 2 +- arch/arm/boot/dts/nspire/nspire-cx.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nspire/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi index a6e9cbf51524..0ee53d3ecd54 100644 --- a/arch/arm/boot/dts/nspire/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire/nspire-classic.dtsi @@ -55,7 +55,7 @@ }; / { - memory { + memory@10000000 { device_type = "memory"; reg = <0x10000000 0x2000000>; /* 32 MB */ }; diff --git a/arch/arm/boot/dts/nspire/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts index 29f0181e5b38..debeff0ec010 100644 --- a/arch/arm/boot/dts/nspire/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire/nspire-cx.dts @@ -122,7 +122,7 @@ model = "TI-NSPIRE CX"; compatible = "ti,nspire-cx"; - memory { + memory@10000000 { device_type = "memory"; reg = <0x10000000 0x4000000>; /* 64 MB */ }; -- cgit v1.2.3-58-ga151 From c322d10fe52138b2d47e3b8dd65c20d705e1c313 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 12 Jun 2024 10:13:14 -0500 Subject: ARM: dts: nspire: Add full compatible for watchdog node The watchdog appears to be an ARM SP805, add the full compatible and the needed clocks properties. Leave this disabled for now as functionality is not fully tested. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240612151314.27967-2-afd@ti.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nspire/nspire.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nspire/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi index d56fef7250db..95588b716c6f 100644 --- a/arch/arm/boot/dts/nspire/nspire.dtsi +++ b/arch/arm/boot/dts/nspire/nspire.dtsi @@ -170,9 +170,12 @@ }; watchdog: watchdog@90060000 { - compatible = "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x90060000 0x1000>; interrupts = <3>; + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; }; rtc: rtc@90090000 { -- cgit v1.2.3-58-ga151 From 3974eeb925657091884a2a44f8b71ab56befdce7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 16:10:18 +0200 Subject: MAINTAINERS: ARM: alphascale: add Krzysztof Kozlowski as maintainer Apparently there was never a maintainers entry for the ARM Alphascale ASM9260 SoC, thus patches end up nowhere. Add such entry, because even if platform is orphaned and on its way out of the kernel, it is nice to take patches if someone sends something. I do not plan to actively support/maintain ARM Alphascale but I can take odd fixes now and then. Cc: Oleksij Rempel Link: https://lore.kernel.org/r/20240612141018.7348-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e91c83a4b0b..24141b89aa42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1931,6 +1931,16 @@ N: allwinner N: sun[x456789]i N: sun[25]0i +ARM/ALPHASCALE ARCHITECTURE +M: Krzysztof Kozlowski +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Odd Fixes +F: arch/arm/boot/dts/alphascale/ +F: drivers/clk/clk-asm9260.c +F: drivers/clocksource/asm9260_timer.c +F: drivers/rtc/rtc-asm9260.c +F: drivers/watchdog/asm9260_wdt.c + ARM/AMD PENSANDO ARM64 ARCHITECTURE M: Brad Larson L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3-58-ga151 From f873f24375c6d46bea92a2ed8ffe55b2f9d5509c Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 31 May 2024 14:31:04 -0500 Subject: arm: dts: nuvoton: Use standard 'i2c' bus node name The standard node name for I2C buses is 'i2c'. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240531193104.3814663-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts | 22 +++++++++++----------- .../dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts index 5787ae95d3b4..1f07ba382910 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts @@ -525,7 +525,7 @@ }; }; - i2c-bus@4 { + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -537,7 +537,7 @@ }; }; - i2c-bus@5 { + i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; @@ -549,7 +549,7 @@ }; }; - i2c-bus@6 { + i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; @@ -561,7 +561,7 @@ }; }; - i2c-bus@7 { + i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; @@ -580,7 +580,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@2 { + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -620,7 +620,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@0 { + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -632,7 +632,7 @@ }; }; - i2c-bus@1 { + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -691,7 +691,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@3 { + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -703,7 +703,7 @@ }; }; - i2c-bus@4 { + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -715,7 +715,7 @@ }; }; - i2c-bus@5 { + i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; @@ -726,7 +726,7 @@ reg = <0x28>; }; }; - i2c-bus@6 { + i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index baa39d0c1032..087f4ac43187 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -215,43 +215,43 @@ reg = <0x70>; i2c-mux-idle-disconnect; - i2c_slot1a: i2c-bus@0 { + i2c_slot1a: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; - i2c_slot1b: i2c-bus@1 { + i2c_slot1b: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; - i2c_slot2a: i2c-bus@2 { + i2c_slot2a: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; }; - i2c_slot2b: i2c-bus@3 { + i2c_slot2b: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; - i2c_slot3: i2c-bus@4 { + i2c_slot3: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; - i2c_slot4: i2c-bus@5 { + i2c_slot4: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; - i2c_slot5: i2c-bus@6 { + i2c_slot5: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; @@ -265,24 +265,24 @@ #size-cells = <0>; i2c-mux-idle-disconnect; - i2c_m2_s1: i2c-bus@0 { + i2c_m2_s1: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; - i2c_m2_s2: i2c-bus@1 { + i2c_m2_s2: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; - i2c_m2_s3: i2c-bus@2 { + i2c_m2_s3: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; }; - i2c_m2_s4: i2c-bus@3 { + i2c_m2_s4: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; -- cgit v1.2.3-58-ga151 From 11afaf16a6540754d618179bd01791fc03480146 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 31 May 2024 14:31:14 -0500 Subject: arm: dts: aspeed: Use standard 'i2c' bus node name The standard node name for I2C buses is 'i2c'. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240531193115.3814887-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/aspeed/aspeed-g4.dtsi | 28 ++++++++++++++-------------- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 28 ++++++++++++++-------------- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 32 ++++++++++++++++---------------- 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi index 857cb26ed6d7..c669ec202085 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -463,7 +463,7 @@ interrupt-controller; }; - i2c0: i2c-bus@40 { + i2c0: i2c@40 { #address-cells = <1>; #size-cells = <0>; @@ -478,7 +478,7 @@ /* Does not need pinctrl properties */ }; - i2c1: i2c-bus@80 { + i2c1: i2c@80 { #address-cells = <1>; #size-cells = <0>; @@ -493,7 +493,7 @@ /* Does not need pinctrl properties */ }; - i2c2: i2c-bus@c0 { + i2c2: i2c@c0 { #address-cells = <1>; #size-cells = <0>; @@ -509,7 +509,7 @@ status = "disabled"; }; - i2c3: i2c-bus@100 { + i2c3: i2c@100 { #address-cells = <1>; #size-cells = <0>; @@ -525,7 +525,7 @@ status = "disabled"; }; - i2c4: i2c-bus@140 { + i2c4: i2c@140 { #address-cells = <1>; #size-cells = <0>; @@ -541,7 +541,7 @@ status = "disabled"; }; - i2c5: i2c-bus@180 { + i2c5: i2c@180 { #address-cells = <1>; #size-cells = <0>; @@ -557,7 +557,7 @@ status = "disabled"; }; - i2c6: i2c-bus@1c0 { + i2c6: i2c@1c0 { #address-cells = <1>; #size-cells = <0>; @@ -573,7 +573,7 @@ status = "disabled"; }; - i2c7: i2c-bus@300 { + i2c7: i2c@300 { #address-cells = <1>; #size-cells = <0>; @@ -589,7 +589,7 @@ status = "disabled"; }; - i2c8: i2c-bus@340 { + i2c8: i2c@340 { #address-cells = <1>; #size-cells = <0>; @@ -605,7 +605,7 @@ status = "disabled"; }; - i2c9: i2c-bus@380 { + i2c9: i2c@380 { #address-cells = <1>; #size-cells = <0>; @@ -621,7 +621,7 @@ status = "disabled"; }; - i2c10: i2c-bus@3c0 { + i2c10: i2c@3c0 { #address-cells = <1>; #size-cells = <0>; @@ -637,7 +637,7 @@ status = "disabled"; }; - i2c11: i2c-bus@400 { + i2c11: i2c@400 { #address-cells = <1>; #size-cells = <0>; @@ -653,7 +653,7 @@ status = "disabled"; }; - i2c12: i2c-bus@440 { + i2c12: i2c@440 { #address-cells = <1>; #size-cells = <0>; @@ -669,7 +669,7 @@ status = "disabled"; }; - i2c13: i2c-bus@480 { + i2c13: i2c@480 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index e6f3cf3c721e..6e05cbcce49c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -592,7 +592,7 @@ interrupt-controller; }; - i2c0: i2c-bus@40 { + i2c0: i2c@40 { #address-cells = <1>; #size-cells = <0>; @@ -607,7 +607,7 @@ /* Does not need pinctrl properties */ }; - i2c1: i2c-bus@80 { + i2c1: i2c@80 { #address-cells = <1>; #size-cells = <0>; @@ -622,7 +622,7 @@ /* Does not need pinctrl properties */ }; - i2c2: i2c-bus@c0 { + i2c2: i2c@c0 { #address-cells = <1>; #size-cells = <0>; @@ -638,7 +638,7 @@ status = "disabled"; }; - i2c3: i2c-bus@100 { + i2c3: i2c@100 { #address-cells = <1>; #size-cells = <0>; @@ -654,7 +654,7 @@ status = "disabled"; }; - i2c4: i2c-bus@140 { + i2c4: i2c@140 { #address-cells = <1>; #size-cells = <0>; @@ -670,7 +670,7 @@ status = "disabled"; }; - i2c5: i2c-bus@180 { + i2c5: i2c@180 { #address-cells = <1>; #size-cells = <0>; @@ -686,7 +686,7 @@ status = "disabled"; }; - i2c6: i2c-bus@1c0 { + i2c6: i2c@1c0 { #address-cells = <1>; #size-cells = <0>; @@ -702,7 +702,7 @@ status = "disabled"; }; - i2c7: i2c-bus@300 { + i2c7: i2c@300 { #address-cells = <1>; #size-cells = <0>; @@ -718,7 +718,7 @@ status = "disabled"; }; - i2c8: i2c-bus@340 { + i2c8: i2c@340 { #address-cells = <1>; #size-cells = <0>; @@ -734,7 +734,7 @@ status = "disabled"; }; - i2c9: i2c-bus@380 { + i2c9: i2c@380 { #address-cells = <1>; #size-cells = <0>; @@ -750,7 +750,7 @@ status = "disabled"; }; - i2c10: i2c-bus@3c0 { + i2c10: i2c@3c0 { #address-cells = <1>; #size-cells = <0>; @@ -766,7 +766,7 @@ status = "disabled"; }; - i2c11: i2c-bus@400 { + i2c11: i2c@400 { #address-cells = <1>; #size-cells = <0>; @@ -782,7 +782,7 @@ status = "disabled"; }; - i2c12: i2c-bus@440 { + i2c12: i2c@440 { #address-cells = <1>; #size-cells = <0>; @@ -798,7 +798,7 @@ status = "disabled"; }; - i2c13: i2c-bus@480 { + i2c13: i2c@480 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 7fb421153596..0c00882f111a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -905,7 +905,7 @@ #include "aspeed-g6-pinctrl.dtsi" &i2c { - i2c0: i2c-bus@80 { + i2c0: i2c@80 { #address-cells = <1>; #size-cells = <0>; reg = <0x80 0x80>; @@ -919,7 +919,7 @@ status = "disabled"; }; - i2c1: i2c-bus@100 { + i2c1: i2c@100 { #address-cells = <1>; #size-cells = <0>; reg = <0x100 0x80>; @@ -933,7 +933,7 @@ status = "disabled"; }; - i2c2: i2c-bus@180 { + i2c2: i2c@180 { #address-cells = <1>; #size-cells = <0>; reg = <0x180 0x80>; @@ -947,7 +947,7 @@ status = "disabled"; }; - i2c3: i2c-bus@200 { + i2c3: i2c@200 { #address-cells = <1>; #size-cells = <0>; reg = <0x200 0x80>; @@ -961,7 +961,7 @@ status = "disabled"; }; - i2c4: i2c-bus@280 { + i2c4: i2c@280 { #address-cells = <1>; #size-cells = <0>; reg = <0x280 0x80>; @@ -975,7 +975,7 @@ status = "disabled"; }; - i2c5: i2c-bus@300 { + i2c5: i2c@300 { #address-cells = <1>; #size-cells = <0>; reg = <0x300 0x80>; @@ -989,7 +989,7 @@ status = "disabled"; }; - i2c6: i2c-bus@380 { + i2c6: i2c@380 { #address-cells = <1>; #size-cells = <0>; reg = <0x380 0x80>; @@ -1003,7 +1003,7 @@ status = "disabled"; }; - i2c7: i2c-bus@400 { + i2c7: i2c@400 { #address-cells = <1>; #size-cells = <0>; reg = <0x400 0x80>; @@ -1017,7 +1017,7 @@ status = "disabled"; }; - i2c8: i2c-bus@480 { + i2c8: i2c@480 { #address-cells = <1>; #size-cells = <0>; reg = <0x480 0x80>; @@ -1031,7 +1031,7 @@ status = "disabled"; }; - i2c9: i2c-bus@500 { + i2c9: i2c@500 { #address-cells = <1>; #size-cells = <0>; reg = <0x500 0x80>; @@ -1045,7 +1045,7 @@ status = "disabled"; }; - i2c10: i2c-bus@580 { + i2c10: i2c@580 { #address-cells = <1>; #size-cells = <0>; reg = <0x580 0x80>; @@ -1059,7 +1059,7 @@ status = "disabled"; }; - i2c11: i2c-bus@600 { + i2c11: i2c@600 { #address-cells = <1>; #size-cells = <0>; reg = <0x600 0x80>; @@ -1073,7 +1073,7 @@ status = "disabled"; }; - i2c12: i2c-bus@680 { + i2c12: i2c@680 { #address-cells = <1>; #size-cells = <0>; reg = <0x680 0x80>; @@ -1087,7 +1087,7 @@ status = "disabled"; }; - i2c13: i2c-bus@700 { + i2c13: i2c@700 { #address-cells = <1>; #size-cells = <0>; reg = <0x700 0x80>; @@ -1101,7 +1101,7 @@ status = "disabled"; }; - i2c14: i2c-bus@780 { + i2c14: i2c@780 { #address-cells = <1>; #size-cells = <0>; reg = <0x780 0x80>; @@ -1115,7 +1115,7 @@ status = "disabled"; }; - i2c15: i2c-bus@800 { + i2c15: i2c@800 { #address-cells = <1>; #size-cells = <0>; reg = <0x800 0x80>; -- cgit v1.2.3-58-ga151 From 7613195d37d69ff92c9bc55599037615212ce19c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 18 May 2024 22:44:42 +0200 Subject: dt-bindings: soc: hisilicon: document hi3660-usb3-otg-bc Add dedicated bindings for the Hisilicon Kirin 960 USB OTG Syscon, to fully document the block and also fix dtbs_check warning: hi3660-hikey960.dtb: usb3_otg_bc@ff200000: compatible: ['syscon', 'simple-mfd'] is too short Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240518204443.122586-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml diff --git a/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml b/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml new file mode 100644 index 000000000000..5c77c4925d19 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin 960 USB OTG Battery Charging Syscon + +maintainers: + - Mauro Carvalho Chehab + +properties: + compatible: + items: + - const: hisilicon,hi3660-usb3-otg-bc + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + usb-phy: + $ref: /schemas/phy/hisilicon,hi3660-usb3.yaml + description: USB Phy node + +required: + - compatible + - reg + - usb-phy + +additionalProperties: false + +examples: + - | + syscon@ff200000 { + compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd"; + reg = <0xff200000 0x1000>; + + usb-phy { + compatible = "hisilicon,hi3660-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,eye-diagram-param = <0x22466e4>; + }; + }; -- cgit v1.2.3-58-ga151 From bc9ec165d066af29661ece91f9cbf74e18ec0a5a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 18 May 2024 22:44:43 +0200 Subject: arm64: dts: hisilicon: hi3660: add dedicated hi3660-usb3-otg-bc compatible Each syscon node must come with a dedicated/specific compatible, which is also reported by dtbs_check: hi3660-hikey960.dtb: usb3_otg_bc@ff200000: compatible: ['syscon', 'simple-mfd'] is too short Link: https://lore.kernel.org/r/20240518204443.122586-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 7e137a884ae5..957a1b41f19b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1161,7 +1161,7 @@ }; usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; + compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd"; reg = <0x0 0xff200000 0x0 0x1000>; usb_phy: usb-phy { -- cgit v1.2.3-58-ga151 From 65896f4a3f852f868bd5bbc0abea072b2f6e0470 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 9 May 2024 16:06:52 +0200 Subject: ARM: dts: rockchip: Add D-PHY for RK3128 The InnoSilicon D-PHY found in RK3128 SoCs supports DSI/LVDS/TTL with a maximum transfer rate of 1 Gbps per lane. While adding it, also add it's clocks to RK3128_PD_VIO powerdomain as the phy is part of it. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240509140653.168591-7-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..2e8ab8e8796a 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,8 @@ <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_MIPI_24M>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -496,6 +498,18 @@ }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + #phy-cells = <0>; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + status = "disabled"; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; -- cgit v1.2.3-58-ga151 From 171ea1ff14e42041af420ed3745f6f480612baa0 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 9 May 2024 16:06:53 +0200 Subject: ARM: dts: rockchip: Add DSI for RK3128 Add the Designware MIPI DSI controller and it's port nodes. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240509140653.168591-8-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 2e8ab8e8796a..a7ab0904564f 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -277,6 +277,43 @@ reg = <0>; remote-endpoint = <&hdmi_in_vop>; }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + + dsi: dsi@10110000 { + compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x10110000 0x4000>; + interrupts = ; + clocks = <&cru PCLK_MIPI>; + clock-names = "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_VIO_MIPI_DSI>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + dsi_out: port@1 { + reg = <1>; + }; }; }; -- cgit v1.2.3-58-ga151 From f87427158d268fe4747cc223de7a2523617b7475 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 6 May 2024 17:51:02 +0200 Subject: ARM: dts: rockchip: Add i2s nodes for RK3128 RK3128 SoCs have two i2s controllers. i2s_8ch has 8 tx and 2 rx channels and is internally hard-wired to the hdmi-controller respectivly the SoC's analog codec. i2s_2ch has 2 tx and 2 rx channels and can also be used externally as it's pins are exposed though pinctrl. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240506155103.206592-2-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index a7ab0904564f..2c41a123c96a 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -399,6 +399,18 @@ status = "disabled"; }; + i2s_8ch: i2s@10200000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10200000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -447,6 +459,21 @@ status = "disabled"; }; + i2s_2ch: i2s@10220000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10220000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + nfc: nand-controller@10500000 { compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; reg = <0x10500000 0x4000>; -- cgit v1.2.3-58-ga151 From d244d6cc718a048672bfb148a6bc9c593a0e1207 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Mon, 6 May 2024 17:51:03 +0200 Subject: ARM: dts: rockchip: Add spdif node for RK3128 The SoC has a S/PDIF TX controller which is fully compatible with older generation Rockchip SoCs. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240506155103.206592-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 2c41a123c96a..4ced1f1fabea 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -411,6 +411,20 @@ status = "disabled"; }; + spdif: spdif@10204000 { + compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; + reg = <0x10204000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; -- cgit v1.2.3-58-ga151 From 041f240e4df6c49d5a928e0dd4c672d0d3326466 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 18 Jun 2024 14:02:25 +0200 Subject: ARM: dts: rockchip: add hdmi-sound node to rk3066a Add hdmi-sound node to rk3066a.dtsi, so that it can be reused by boards with HDMI support. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/5fe7c2fe-4a38-436a-8017-66989959329a@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3066a.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi index 30139f21de64..a4e815cd6707 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3066a.dtsi @@ -53,6 +53,22 @@ ports = <&vop0_out>, <&vop1_out>; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; -- cgit v1.2.3-58-ga151 From 81fc54e62b5b391d78f741bf33c3a91f18464ffb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Jun 2024 14:07:07 +0200 Subject: ARM: dts: qcom: use generic node names for Adreno and QFPROM Use recommended generic node names for the Adreno GPU and QFPROM fused values device nodes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240623120707.45764-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 178a3b424670..d73ea1434b36 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -666,7 +666,7 @@ qcom,controller-type = "pmic-arbiter"; }; - qfprom: qfprom@700000 { + qfprom: efuse@700000 { compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; @@ -992,7 +992,7 @@ reg = <0x1a400000 0x100>; }; - gpu: adreno-3xx@4300000 { + gpu: gpu@4300000 { compatible = "qcom,adreno-320.2", "qcom,adreno"; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index ca53dff820ef..2b52e5d5eb51 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -245,7 +245,7 @@ reg = <0xfc190000 0x10000>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 12cf85441a0b..da0fd75f4711 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -372,7 +372,7 @@ qcom,controller-type = "pmic-arbiter"; }; - qfprom: qfprom@700000 { + qfprom: efuse@700000 { compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 270973e85625..b2f92ad6499a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -635,7 +635,7 @@ reg = <0xfc4ab000 0x4>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; #address-cells = <1>; @@ -1046,7 +1046,7 @@ }; }; - gpu: adreno@fdb00000 { + gpu: gpu@fdb00000 { compatible = "qcom,adreno-305.18", "qcom,adreno"; reg = <0xfdb00000 0x10000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 1bea3cef4ba7..f9820d996910 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1235,7 +1235,7 @@ reg = <0xfc4ab000 0x4>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x2100>; #address-cells = <1>; @@ -2131,7 +2131,7 @@ }; }; - gpu: adreno@fdb00000 { + gpu: gpu@fdb00000 { compatible = "qcom,adreno-330.1", "qcom,adreno"; reg = <0xfdb00000 0x10000>; reg-names = "kgsl_3d0_reg_memory"; -- cgit v1.2.3-58-ga151 From 54c799c3c4abe2c5e2c22d47dbcba5c34ec99aae Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 6 Jun 2024 16:34:02 +0200 Subject: ARM: dts: rockchip: Add SFC for RK3128 Add the Serial Flash Controller and it's pincontrols. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240606143401.32454-7-knaerzche@gmail.com [reference HCLK_SFC by its numeric id to prevent conflicts with the clock binding/controller changes] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 4ced1f1fabea..5019aae1be32 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -425,6 +425,15 @@ status = "disabled"; }; + sfc: spi@1020c000 { + compatible = "rockchip,sfc"; + reg = <0x1020c000 0x8000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru 479>; + clock-names = "clk_sfc", "hclk_sfc"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -1196,6 +1205,32 @@ }; }; + sfc { + sfc_bus2: sfc-bus2 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>; + }; + + sfc_bus4: sfc-bus4 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>, + <1 RK_PD2 3 &pcfg_pull_default>, + <1 RK_PD3 3 &pcfg_pull_default>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>; + }; + }; + spdif { spdif_tx: spdif-tx { rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; -- cgit v1.2.3-58-ga151 From 5014e1e970dede6410c7b758c4f3665a0875bb7e Mon Sep 17 00:00:00 2001 From: Valeriy Klimin Date: Fri, 21 Jun 2024 17:26:43 +0300 Subject: ARM: dts: qcom: Add Sony Xperia Z3 Compact smartphone Add the dts for the Z3 Compact. This is currently almost the same as the plain Z3 as they share almost the same hardware and nothing device-specific is currently supported. Signed-off-by: Valeriy Klimin Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240621-sony-aries-v2-2-dddf10722522@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../qcom-msm8974pro-sony-xperia-shinano-aries.dts | 44 ++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index e9a8bc74195e..ccd4ce6353df 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974pro-oneplus-bacon.dtb \ qcom-msm8974pro-samsung-klte.dtb \ qcom-msm8974pro-samsung-kltechn.dtb \ + qcom-msm8974pro-sony-xperia-shinano-aries.dtb \ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-msm8974pro-sony-xperia-shinano-leo.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts new file mode 100644 index 000000000000..2621c5928b6a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro-sony-xperia-shinano-common.dtsi" + +/ { + model = "Sony Xperia Z3 Compact"; + compatible = "sony,xperia-aries", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + gpio-keys { + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; +}; + +&gpio_keys_pin_a { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; +}; + +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <2100000>; + qcom,fast-charge-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4280000>; + qcom,minimum-input-voltage = <4200000>; + + status = "okay"; +}; + +&synaptics_touchscreen { + vio-supply = <&pm8941_s3>; +}; -- cgit v1.2.3-58-ga151 From f1a77eff4c60b9814d8b59abae21cfa80c00df79 Mon Sep 17 00:00:00 2001 From: Valeriy Klimin Date: Fri, 21 Jun 2024 17:26:44 +0300 Subject: ARM: dts: qcom: msm8974-sony-shinano: increase load on l21 for sdhc2 SD cards would exhibit errors similar to ones described in commit 27fe0fc05f35 ("ARM: dts: msm8974-FP2: Increase load on l20 for sdhci") This patch applies the same change to the regulator for sdhc2. Signed-off-by: Valeriy Klimin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240621-sony-aries-v2-3-dddf10722522@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi index e129bb1bd6ec..6af7c71c7158 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -380,6 +380,8 @@ pm8941_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; regulator-boot-on; }; -- cgit v1.2.3-58-ga151 From a69274e1c6f557c2fa7f35f194acb51d723adbc8 Mon Sep 17 00:00:00 2001 From: Valeriy Klimin Date: Fri, 21 Jun 2024 17:26:42 +0300 Subject: dt-bindings: arm: qcom: Add Sony Xperia Z3 Compact Add the compatible for this device. Signed-off-by: Valeriy Klimin Acked-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240621-sony-aries-v2-1-dddf10722522@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d839691a900c..ec1c10a12470 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -189,6 +189,7 @@ properties: - htc,m8 - oneplus,bacon - samsung,klte + - sony,xperia-aries - sony,xperia-castor - sony,xperia-leo - const: qcom,msm8974pro -- cgit v1.2.3-58-ga151 From 61ba969e0e7d26a9260bcc658c54d2bf9a1f0a2b Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Fri, 21 Jun 2024 14:13:33 +0000 Subject: arm64: dts: qcom: msm8916-gplus-fl8005a: Add BMS There is PM8916 Battery voltage monitor on GPLUS FL8005A. Add PM8916 BMS and the battery to the device tree. Signed-off-by: Lin, Meng-Bo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240621141319.347088-1-linmengbo06890@proton.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index e6ed5544a11b..f7be7e371820 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -24,6 +24,28 @@ stdout-path = "serial0"; }; + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + voltage-min-design-microvolt = <3700000>; + voltage-max-design-microvolt = <4200000>; + energy-full-design-microwatt-hours = <13690000>; + charge-full-design-microamp-hours = <3700000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = + <4186000 100>, <4126000 95>, <4078000 90>, + <4036000 85>, <3997000 80>, <3962000 75>, + <3932000 70>, <3904000 65>, <3874000 60>, + <3839000 55>, <3809000 50>, <3792000 45>, + <3780000 40>, <3772000 35>, <3764000 30>, + <3752000 25>, <3731000 20>, <3704000 16>, + <3677000 13>, <3670000 11>, <3668000 10>, + <3666000 9>, <3662000 8>, <3658000 7>, <3648000 6>, + <3624000 5>, <3580000 4>, <3518000 3>, <3434000 2>, + <3310000 1>, <3000000 0>; + }; + flash-led-controller { /* Actually qcom,leds-gpio-flash */ compatible = "sgmicro,sgm3140"; @@ -116,6 +138,11 @@ reg = <0x0 0x86800000 0x0 0x5000000>; }; +&pm8916_bms { + monitored-battery = <&battery>; + status = "okay"; +}; + &pm8916_codec { qcom,micbias-lvl = <2800>; qcom,mbhc-vthreshold-low = <150 180 237 450 500>; -- cgit v1.2.3-58-ga151 From d315b45ab8b312d6e74d85064ef916aafd1bbdef Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 21 Jun 2024 10:42:30 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Configure PM8008 regulators PM8008 regulators are used for the cameras found on FP4. Configure the chip and its voltages. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240621-fp4-fp5-pm8008-v1-1-dbedcd6f00f1@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 109 +++++++++++++++++++++- 1 file changed, 108 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 6d7ab931e56b..a74f3ac09a5e 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -117,6 +117,25 @@ }; }; }; + + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; }; @@ -404,7 +423,79 @@ }; &i2c10 { - /* PM8008 PMIC @ 8 and 9 */ + clock-frequency = <400000>; + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 59 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s8e>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s2a>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2904000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3140000>; + }; + }; + }; + /* PX8618 @ 26 */ /* SMB1395 PMIC @ 34 */ /* awinic,aw8695 @ 5a */ @@ -717,6 +808,22 @@ */ bias-pull-up; }; + + pm8008_default: pm8008-default-state { + int-pins { + pins = "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-n-pins { + pins = "gpio58"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &uart1 { -- cgit v1.2.3-58-ga151 From 2cf5ec58e87bf4df1b360ab45c047d2b311930c8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 21 Jun 2024 10:42:31 +0200 Subject: arm64: dts: qcom: qcm6490-fairphone-fp5: Configure PM8008 regulators PM8008 regulators are used for the cameras found on FP5. Configure the chip and its voltages. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240621-fp4-fp5-pm8008-v1-2-dbedcd6f00f1@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 105 ++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index c66c7eda6a69..8ab30c01712e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -207,6 +207,25 @@ }; }; + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + quiet-thermal { polling-delay-passive = <0>; @@ -557,7 +576,76 @@ &i2c1 { status = "okay"; - /* PM8008 PMIC @ 8 and 9 */ + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pm8350c_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s8b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + /* Pixelworks @ 26 */ /* FSA4480 USB audio switch @ 42 */ /* AW86927FCR haptics @ 5a */ @@ -688,6 +776,14 @@ }; }; +&pm8350c_gpios { + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + &pmk8350_rtc { status = "okay"; }; @@ -845,6 +941,13 @@ bias-pull-up; }; + pm8008_int_default: pm8008-int-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins = "gpio28"; function = "gpio"; -- cgit v1.2.3-58-ga151 From 4e915987ff5b91ea531e716367373ff4442d9614 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 21 Jun 2024 10:20:06 +0300 Subject: arm64: dts: qcom: x1e80100: Enable tsens and thermal zone nodes Add tsens and thermal zones nodes for x1e80100 SoC. Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240621-x1e80100-dts-thermal-v3-1-abd6f416b609@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1214 ++++++++++++++++++++++++++++++++ 1 file changed, 1214 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9944c654851e..09fd6c8e53bb 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2505,6 +2505,66 @@ }; }; + tsens0: thermal-sensor@c271000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, + <0 0x0c222000 0 0x1000>; + + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, + <0 0x0c223000 0 0x1000>; + + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, + <0 0x0c224000 0 0x1000>; + + interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c274000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c274000 0 0x1000>, + <0 0x0c225000 0 0x1000>; + + interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + usb_1_ss0_hsphy: phy@fd3000 { compatible = "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -5469,4 +5529,1158 @@ , ; }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-top-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-btm-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mem-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu1-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-top-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-btm-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu2-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss2-top-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss2-btm-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp2-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp3-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens3 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens3 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; -- cgit v1.2.3-58-ga151 From 368a5aed131271600e75c715a5b79f0b613f0225 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 18:42:27 +0200 Subject: ARM: dts: qcom: msm8974: Use mboxes in smsm node With the smsm bindings and driver finally supporting mboxes, switch to that and stop using apcs as syscon. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-smsm-mbox-dts-v1-1-268ab7eef779@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index f9820d996910..15568579459a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -294,9 +294,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; -- cgit v1.2.3-58-ga151 From d605f9c75949997150dbb32bf082695326d3e110 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 18:42:28 +0200 Subject: arm64: dts: qcom: msm8916: Use mboxes in smsm node With the smsm bindings and driver finally supporting mboxes, switch to that and stop using apcs as syscon. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-smsm-mbox-dts-v1-2-268ab7eef779@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index bdedbcdc36d3..7383bcc603ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -410,8 +410,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; -- cgit v1.2.3-58-ga151 From 9f8b7c4e3d8bbb6eb787752ad14a82e714d917ff Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 18:42:29 +0200 Subject: arm64: dts: qcom: msm8939: Use mboxes in smsm node With the smsm bindings and driver finally supporting mboxes, switch to that and stop using apcs as syscon. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-smsm-mbox-dts-v1-3-268ab7eef779@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index e309ef909ea7..46d9480cd464 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -443,8 +443,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs1_mbox 8 13>; - qcom,ipc-3 = <&apcs1_mbox 8 19>; + mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>; apps_smsm: apps@0 { reg = <0>; -- cgit v1.2.3-58-ga151 From e36402b55684c64af23575f39e0a6ce27272b5f7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 18:42:30 +0200 Subject: arm64: dts: qcom: msm8953: Use mboxes in smsm node With the smsm bindings and driver finally supporting mboxes, switch to that and stop using apcs as syscon. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-smsm-mbox-dts-v1-4-268ab7eef779@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 1b61a63710a6..a4bfb624fb8a 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -411,8 +411,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; -- cgit v1.2.3-58-ga151 From 585141c57a49315f6522d5f7265a3f1aa05424c1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 18:42:31 +0200 Subject: arm64: dts: qcom: msm8976: Use mboxes in smsm node With the smsm bindings and driver finally supporting mboxes, switch to that and stop using apcs as syscon. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-smsm-mbox-dts-v1-5-268ab7eef779@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index e299d42c5d98..d62dcb76fa48 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -439,9 +439,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; -- cgit v1.2.3-58-ga151 From d7aeff30093888649789dcad070fe954745adf53 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 May 2024 14:55:05 +0200 Subject: arm64: dts: qcom: sa8775p: add a dedicated memory carveout for TZ Add a 20MB reserved memory region for use by SCM calls. Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20240527-shm-bridge-v10-15-ce7afaa58d3a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3808fafd6bec..23f1b2e5e624 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -221,6 +221,7 @@ firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; + memory-region = <&tz_ffi_mem>; }; }; @@ -431,6 +432,12 @@ no-map; }; + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { reg = <0x0 0x93b00000 0x0 0xf00000>; no-map; -- cgit v1.2.3-58-ga151 From 7d7dd631d1af471a6c909e197be2ef3df526d00f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 22 Jun 2024 13:51:16 +0000 Subject: dt-bindings: arm: amlogic: add OSMC Vero 4K Add support for the OSMC Vero 4K Linux-based STB Signed-off-by: Christian Hewitt Acked-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240622135117.2608890-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 77f8dfa86e6a..9b84a18cf41f 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -91,6 +91,7 @@ properties: - libretech,aml-s905x-cc - libretech,aml-s905x-cc-v2 - nexbox,a95x + - osmc,vero4k - const: amlogic,s905x - const: amlogic,meson-gxl -- cgit v1.2.3-58-ga151 From 5feff053b08ce5d2167b9f44bcea3b466b5a81a0 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 22 Jun 2024 13:51:17 +0000 Subject: arm64: dts: meson: add support for OSMC Vero 4K The OSMC Vero 4K device is based on the Amlogic S905X (P212) reference design with the following specifications: - 2GB DDR4 RAM - 16GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100 Ethernet - AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2) - 2x USB 2.0 ports (1x OTG) - IR receiver (internal) - IR extender port (external) - 1x micro SD card slot - 1x Power LED (red) - 1x Reset button (in AV jack) Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240622135117.2608890-2-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxl-s905x-vero4k.dts | 199 +++++++++++++++++++++ 2 files changed, 200 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0746e01b5853..9fe3d6bba9b1 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-vero4k.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxlx-s905l-p271.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts new file mode 100644 index 000000000000..de996e930b82 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxl-s905x-p212.dtsi" +#include +#include +#include + +/ { + compatible = "osmc,vero4k", "amlogic,s905x", "amlogic,meson-gxl"; + model = "OSMC Vero 4K"; + + reserved-memory { + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + button { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-standby { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + }; + + dio2133: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&hdmi_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + sound-name-prefix = "DIT"; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "VERO4K"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLP", + "AU2 INR", "ACODEC LORP", + "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-5 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 4132d13bfcdb3551b0d1a6a74e2063351b4bfcaa Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 22 Jun 2024 14:01:10 +0000 Subject: dt-bindings: add dream vendor prefix Add a vendor prefix for Dream Property GmbH Signed-off-by: Christian Hewitt Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240622140112.2609534-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..a6cb1eb8e5e0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -394,6 +394,8 @@ patternProperties: description: DPTechnics "^dragino,.*": description: Dragino Technology Co., Limited + "^dream,.*": + description: Dream Property GmbH "^ds,.*": description: DaSheng, Inc. "^dserve,.*": -- cgit v1.2.3-58-ga151 From 96cf7ca12bdcd44fcfdca74e56389c40ae47a7b1 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 22 Jun 2024 14:01:11 +0000 Subject: dt-bindings: arm: amlogic: add support for Dreambox One/Two Dreambox One and Dreambox Two are DVBS/T2 receiver boxes based on the Amlogic W400 reference board with an S922X chip. Signed-off-by: Christian Hewitt Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240622140112.2609534-2-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 9b84a18cf41f..0647851ae1f5 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -177,6 +177,8 @@ properties: - azw,gtking - azw,gtking-pro - bananapi,bpi-m2s + - dream,dreambox-one + - dream,dreambox-two - hardkernel,odroid-go-ultra - hardkernel,odroid-n2 - hardkernel,odroid-n2l -- cgit v1.2.3-58-ga151 From 83a6f4c62cb12aa902043fc1910fdbe483193f3c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 22 Jun 2024 14:01:12 +0000 Subject: arm64: dts: meson: add initial support for Dreambox One/Two Dreambox One and Dreambox Two are based on the Amlogic W400 reference board with an S922X chip and the following specs: - 2GB DDR3 RAM - 16GB eMMC - 10/100/1000 Base-T Ethernet - AP6356 Wireless (802.11 b/g/n/ac, BT 5.0) - HDMI 2.1 video - S/PDIF optical output - 2x DVB-S2/T2 - Smartcard Reader Slot - 2x USB 2.0 port (1x micro-USB for service) - 1x USB 3.0 port - IR receiver - 1x Power LED (blue) - 1x Power button (top) - 1x Update/Reset button (underside) - 1x micro SD card slot Dreambox Two differences: - 3" Colour LCD display (MIPI-DSI) - Common Interface Slot Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240622140112.2609534-3-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 2 + .../boot/dts/amlogic/meson-g12b-dreambox-one.dts | 17 +++ .../boot/dts/amlogic/meson-g12b-dreambox-two.dts | 20 +++ .../boot/dts/amlogic/meson-g12b-dreambox.dtsi | 154 +++++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 9fe3d6bba9b1..29417f04f886 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -21,6 +21,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3-ts050.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-mnt-reform2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-one.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-two.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts new file mode 100644 index 000000000000..ecfa1c683dde --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-dreambox.dtsi" + +/ { + compatible = "dream,dreambox-one", "amlogic,s922x", "amlogic,g12b"; + model = "Dreambox One"; +}; + +&sd_emmc_a { + sd-uhs-sdr12; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts new file mode 100644 index 000000000000..df0d71983c3d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-dreambox.dtsi" + +/ { + compatible = "dream,dreambox-two", "amlogic,s922x", "amlogic,g12b"; + model = "Dreambox Two"; +}; + +&sd_emmc_a { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi new file mode 100644 index 000000000000..3a24c2411552 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Christian Hewitt + */ + +#include "meson-g12b-w400.dtsi" +#include +#include +#include + +/ { + cvbs-connector { + status = "disabled"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOA_11 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + spdif_dit: audio-codec-1 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "DREAMBOX"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "SPDIFOUT_A IN 0", "FRDDR_A OUT 3", + "SPDIFOUT_A IN 1", "FRDDR_B OUT 3", + "SPDIFOUT_A IN 2", "FRDDR_C OUT 3"; + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* spdif hdmi or toslink interface */ + dai-link-4 { + sound-dai = <&spdifout_a>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-5 { + sound-dai = <&spdifout_b>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-6 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + linux,rc-map-name = "rc-dreambox"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +&spdifout_a { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdifout_b { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From ca88b172eebfaa923ea752f6eb41ec5c9cb587c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 24 Jun 2024 10:59:36 +0200 Subject: arm64: dts: amlogic: ad402: fix thermal zone node name Fixes the following: thermal-zones: 'soc_thermal' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml# Fixes: 593ab951232b ("arm64: dts: amlogic: ad402: setup thermal-zones") Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240624-topic-amlogic-upstream-bindings-fixes-dts-round-2-v1-1-0a21f456eb8d@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts index 6883471a93b4..0d92f5253b64 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad402.dts @@ -86,7 +86,7 @@ }; thermal-zones { - soc_thermal: soc_thermal { + soc_thermal: soc-thermal { polling-delay = <1000>; polling-delay-passive = <100>; sustainable-power = <130>; -- cgit v1.2.3-58-ga151 From c04774af7ae392322e204dd20117e6c5162e0fe4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 20 Jun 2024 12:16:56 +0200 Subject: arm: dts: mediatek: Declare drive-strength numerically On some devicetrees, the drive-strength property gets assigned a MTK_DRIVE_(x)_mA definition, which matches with (x). For example, MTK_DRIVE_8mA equals to 8 and MTK_DRIVE_30mA equals to 30. Also keeping in mind that the drive-strength property is, by (binding) definition, taking a number in milliamperes unit, change all devicetrees to avoid the usage of any MTK_DRIVE_(x) definition. Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240620101656.1096374-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt2701-evb.dts | 2 +- arch/arm/boot/dts/mediatek/mt7623.dtsi | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts index 9c7325f18933..4c76366aa938 100644 --- a/arch/arm/boot/dts/mediatek/mt2701-evb.dts +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts @@ -231,7 +231,7 @@ , , ; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index f0b4a09004b3..814586abc297 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -1143,13 +1143,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <2>; bias-pull-up = ; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <2>; bias-pull-down = ; }; @@ -1167,14 +1167,14 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins-clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <4>; }; pins-wp { @@ -1197,13 +1197,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; }; @@ -1211,7 +1211,7 @@ nand_pins_default: nanddefault { pins-ale { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -1226,13 +1226,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up; }; pins-we { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; -- cgit v1.2.3-58-ga151 From 2f6b62e80a9662becd22599ae553de397efacc85 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 29 May 2024 11:29:30 +0200 Subject: dt-bindings: fuse: Document R-Car E-FUSE / PFC Document support for E-FUSE non-volatile memory accessible through PFC on R-Car V3U and S4-8. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/03e43e97941df238ef1a618852aecd7be68adbb0.1716974502.git.geert+renesas@glider.be --- .../bindings/fuse/renesas,rcar-efuse.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml diff --git a/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml b/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml new file mode 100644 index 000000000000..d7e289244e72 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/renesas,rcar-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: R-Car E-FUSE connected to PFC + +maintainers: + - Geert Uytterhoeven + +description: + The E-FUSE is a type of non-volatile memory, which is accessible through the + Pin Function Controller (PFC) on some R-Car Gen4 SoCs. + +properties: + compatible: + enum: + - renesas,r8a779a0-efuse # R-Car V3U + - renesas,r8a779f0-efuse # R-Car S4-8 + + reg: + maxItems: 1 + description: PFC System Group Fuse Control and Monitor register block + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + fuse: fuse@e6078800 { + compatible = "renesas,r8a779a0-efuse"; + reg = <0xe6078800 0x100>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; -- cgit v1.2.3-58-ga151 From 8a3d2ad6129c1c43b683550802a93a9ca7f9645b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 29 May 2024 11:29:31 +0200 Subject: dt-bindings: fuse: Document R-Car E-FUSE / OTP_MEM Document support for E-FUSE non-volatile memory accessible through OTP_MEM on R-Car V4H and V4M. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/436506babe4ce468fda19380d9373470468e3752.1716974502.git.geert+renesas@glider.be --- .../devicetree/bindings/fuse/renesas,rcar-otp.yaml | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml diff --git a/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml b/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml new file mode 100644 index 000000000000..d74872ae9ff3 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: R-Car E-FUSE connected to OTP_MEM + +maintainers: + - Geert Uytterhoeven + +description: + The E-FUSE is a type of non-volatile memory, which is accessible through the + One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs. + +properties: + compatible: + enum: + - renesas,r8a779g0-otp # R-CarV4H + - renesas,r8a779h0-otp # R-CarV4M + + reg: + items: + - description: OTP_MEM_0 + - description: OTP_MEM_1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + otp: otp@e61be000 { + compatible = "renesas,r8a779g0-otp"; + reg = <0xe61be000 0x1000>, <0xe61bf000 0x1000>; + }; -- cgit v1.2.3-58-ga151 From 99a2b6d16b37258bcbdc2e07eb55e129362a182f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 20 Jun 2024 16:11:38 +0200 Subject: ARM: dts: rockchip: enable hdmi_sound and i2s0 for mk808 hdmi Enable the hdmi_sound node and add i2s0 as sound source for mk808 hdmi. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/aa79ff87-ea94-4f6d-a81b-5110724243f4@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3066a-mk808.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts index 06790f05b395..4de9a45c4883 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts @@ -143,6 +143,14 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + &mmc0 { bus-width = <4>; cap-mmc-highspeed; -- cgit v1.2.3-58-ga151 From 01eeea6b1afbe6c40a0915e40644efc0bebdb42a Mon Sep 17 00:00:00 2001 From: Sebastian Kropatsch Date: Sun, 16 Jun 2024 23:48:29 +0200 Subject: dt-bindings: arm: rockchip: Add FriendlyElec CM3588 NAS Add devicetree bindings for the FriendlyElec CM3588 NAS board. The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. Acked-by: Krzysztof Kozlowski Signed-off-by: Sebastian Kropatsch Link: https://lore.kernel.org/r/20240616215354.40999-2-seb-dev@mail.de Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 77469270b271..eca0a42eb384 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -248,6 +248,13 @@ properties: - const: friendlyarm,nanopc-t6 - const: rockchip,rk3588 + - description: FriendlyElec CM3588-based boards + items: + - enum: + - friendlyarm,cm3588-nas + - const: friendlyarm,cm3588 + - const: rockchip,rk3588 + - description: GameForce Chi items: - const: gameforce,chi -- cgit v1.2.3-58-ga151 From e23819cf273c110662fdc392dcb55a75b3888609 Mon Sep 17 00:00:00 2001 From: Sebastian Kropatsch Date: Sun, 16 Jun 2024 23:48:30 +0200 Subject: arm64: dts: rockchip: Add FriendlyElec CM3588 NAS board The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. To reflect the hardware setup, add device tree sources for the SoM and the NAS daughter board as separate files. Hardware features: - Rockchip RK3588 SoC - 4GB/8GB/16GB LPDDR4x RAM - 64GB eMMC - MicroSD card slot - 1x RTL8125B 2.5G Ethernet - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs - 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A - 1x USB 3.0 Type-C with DP AltMode support - 2x HDMI 2.1 out, 1x HDMI in - MIPI-CSI Connector, MIPI-DSI Connector - 40-pin GPIO header - 4 buttons: power, reset, recovery, MASK, user button - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector PCIe bifurcation is used to handle all four M.2 sockets at PCIe 3.0 x1 speed. Data lane mapping in the DT is done like described in commit f8020dfb311d ("phy: rockchip-snps-pcie3: fix bifurcation on rk3588"). This device tree includes support for eMMC, SD card, ethernet, all USB2 and USB3 ports, all four M.2 slots, GPU, beeper, IR, RTC, UART debugging as well as the buttons and LEDs. The GPIOs are labeled according to the schematics. Reviewed-by: Space Meyer Signed-off-by: Sebastian Kropatsch Link: https://lore.kernel.org/r/20240616215354.40999-3-seb-dev@mail.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-friendlyelec-cm3588-nas.dts | 778 +++++++++++++++++++++ .../dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 653 +++++++++++++++++ 3 files changed, 1432 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d80809038e8a..909217846a07 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -121,6 +121,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts new file mode 100644 index 000000000000..83103e4c7216 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588-friendlyelec-cm3588.dtsi" + +/ { + model = "FriendlyElec CM3588 NAS"; + compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588"; + + adc_key_recovery: adc-key-recovery { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_detect>; + + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "realtek,rt5616-codec"; + + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + buzzer: pwm-beeper { + compatible = "pwm-beeper"; + amp-supply = <&vcc_5v0_sys>; + beeper-hz = <500>; + pwms = <&pwm8 0 500000 0>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 80 120 160 220>; + fan-supply = <&vcc_5v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button-user { + debounce-interval = <50>; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "User Button"; + linux,code = ; + wakeup-source; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc_12v_dcin: regulator-vcc-12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_3v3_m2_a: regulator-vcc-3v3-m2-a { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_b: regulator-vcc-3v3-m2-b { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_c: regulator-vcc-3v3-m2-c { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_c"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_d: regulator-vcc-3v3-m2-d { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_d"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* vcc_5v0_sys powers the peripherals */ + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* SY6280AAC power switch (U14 in schematics) */ + vcc_5v0_host_20: regulator-vcc-5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host20_en>; + regulator-name = "vcc_5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U8 in schematics) */ + vcc_5v0_host_30_p1: regulator-vcc-5v0-host-30-p1 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p1_en>; + regulator-name = "vcc_5v0_host_30_p1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U9 in schematics) */ + vcc_5v0_host_30_p2: regulator-vcc-5v0-host-30-p2 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p2_en>; + regulator-name = "vcc_5v0_host_30_p2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U10 in schematics) */ + vbus_5v0_typec: regulator-vbus-5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_5v_pwr_en>; + regulator-name = "vbus_5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; +}; + +/* vcc_4v0_sys powers the RK806 and RK860's */ +&vcc_4v0_sys { + vin-supply = <&vcc_12v_dcin>; +}; + +/* Combo PHY 1 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 2 (pcie2x1l0) */ +&combphy1_ps { + status = "okay"; +}; + +/* Combo PHY 2 is configured to act as USB3 PHY */ +/* Used by USB 3.0 OTG 2 controller (USB 3.0 Type-A port 2) */ +/* CM3588 USB Controller Config Table: USB30 HOST2 */ +&combphy2_psu { + status = "okay"; +}; + +/* GPIO names are in the format "Human-readable-name [SIGNAL_LABEL]" */ +/* Signal labels match the official CM3588 NAS SDK schematic revision 2309 */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "MicroSD detect [SDMMC_DET_L]", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "", + /* GPIO0 D0-D7 */ + "", "", "", "USB3 Type-C [CC_INT_L]", + "IR receiver [PWM3_IR_M0]", "User Button", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "", + "USB2 Type-A [USB2_PWREN]", "", "", "Pin 15", + /* GPIO1 B0-B7 */ + "Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]", + "Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]", + /* GPIO1 C0-C7 */ + "", "", "", "", + "Headphone detect [HP_DET_L]", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "USB3 Type-C [TYPEC5V_PWREN_H]", "5V Fan [PWM1_M1]", + "", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "SPI NOR Flash [FSPI_D0_M1]", "SPI NOR Flash [FSPI_D1_M1]", + /* GPIO2 B0-B7 */ + "SPI NOR Flash [FSPI_D2_M1]", "SPI NOR Flash [FSPI_D3_M1]", "", "SPI NOR Flash [FSPI_CLK_M1]", + "SPI NOR Flash [FSPI_CSN0_M1]", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]", + "Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]", + /* GPIO3 B0-B7 */ + "Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16", + "Pin 18", "Pin 29 [UART3_TX_M1/PWM12_M0]", "Pin 31 [UART3_RX_M1/PWM13_M0]", "Pin 12", + /* GPIO3 C0-C7 */ + "DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]", + "", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]", + /* GPIO3 D0-D7 */ + "DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "M.2 M-Key Slot4 [M2_D_PERST_L]", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "USB3-A #1 [USB3_TYPEC1_PWREN]", "", "", "M.2 M-Key Slot3 [M2_C_PERST_L]", + "M.2 M-Key Slot2 [M2_B_PERST_L]", "M.2 M-Key Slot1 [M2_A_CLKREQ_L]", "M.2 M-Key Slot1 [M2_A_PERST_L]", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +/* Connected to MIPI-DSI0 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + status = "disabled"; +}; + +&i2c6 { + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = ; + try-power-role = "source"; + vbus-supply = <&vbus_5v0_typec>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +/* Connected to MIPI-CSI1 */ +/* &i2c7 */ + +/* GPIO Connector, connected to 40-pin GPIO header */ +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; +}; + +&pcie2x1l0 { + /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_b>; + status = "okay"; +}; + +&pcie2x1l1 { + /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_d>; + status = "okay"; +}; + +&pcie30phy { + /* + * Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports) + * port 0 lane 0 - always mapped to controller 0 (4L) + * port 0 lane 1 - map to controller 2 (1L0) + * port 1 lane 0 - map to controller 1 (2L) + * port 1 lane 1 - map to controller 3 (1L1) + */ + data-lanes = <1 3 2 4>; + status = "okay"; +}; + +&pcie3x4 { + /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_a>; + status = "okay"; +}; + +&pcie3x2 { + /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_c>; + status = "okay"; +}; + +&pinctrl { + audio { + headphone_detect: headphone-detect { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc_5v0_host20_en: vcc-5v0-host20-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p1_en: vcc-5v0-host30p1-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p2_en: vcc-5v0-host30p2-en { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_5v_pwr_en: typec-5v-pwr-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* Connected to 5V Fan */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +/* Connected to MIPI-DSI0 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +/* Connected to IR Receiver */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART0 */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +/* Connected to Buzzer */ +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm8m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm9 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&pwm10 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm10m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm13 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm13m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Optimized for infrared applications */ +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + status = "disabled"; +}; + +/* microSD card */ +&sdmmc { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART4, UART7 and PWM10 */ +&spi0 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART8 */ +&spi4 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM4 */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM12 and PWM13 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; +}; + +/* USB2 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB20 OTG0 */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0_typec>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB20 OTG1 */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc_5v0_host_30_p1>; + status = "okay"; +}; + +/* USB2 PHY for USB 2.0 Type-A */ +/* CM3588 USB Controller Config Table: USB20 HOST0 */ +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_host_20>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 2 */ +/* CM3588 USB Controller Config Table: USB20 HOST1 */ +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc_5v0_host_30_p2>; + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ehci { + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-C */ +/* PHYs: <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3> */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + dwc3_0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ehci { + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ohci { + status = "okay"; +}; + +/* Upper USB 3.0 Type-A (port 1) */ +/* PHYs: <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3> */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHYs: <&combphy2_psu PHY_TYPE_USB3> */ +&usb_host2_xhci { + status = "okay"; +}; + +/* USB3 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB30 OTG0 */ +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +/* USB3 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB30 OTG1 */ +&usbdp_phy1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi new file mode 100644 index 000000000000..e3a9598b99fc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "FriendlyElec CM3588"; + compatible = "friendlyarm,cm3588", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_sys_pin>; + }; + + led_usr: led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_usr_pin>; + }; + }; + + /* vcc_4v0_sys powers the RK806 and RK860's */ + vcc_4v0_sys: regulator-vcc-4v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + }; + + vcc_3v3_pcie20: regulator-vcc-3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-1v1-nldo-s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_4v0_sys>; + }; +}; + +/* Combo PHY 0 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 4 (pcie2x1l2) */ +&combphy0_ps { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: audio-codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + /* r8125 ethernet, @fe190000 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + led_sys_pin: led-sys-pin { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_usr_pin: led-usr-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +/* microSD card */ +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + rk806_single: pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc_4v0_sys>; + vcc2-supply = <&vcc_4v0_sys>; + vcc3-supply = <&vcc_4v0_sys>; + vcc4-supply = <&vcc_4v0_sys>; + vcc5-supply = <&vcc_4v0_sys>; + vcc6-supply = <&vcc_4v0_sys>; + vcc7-supply = <&vcc_4v0_sys>; + vcc8-supply = <&vcc_4v0_sys>; + vcc9-supply = <&vcc_4v0_sys>; + vcc10-supply = <&vcc_4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +/* Debug UART */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; +}; -- cgit v1.2.3-58-ga151 From def88eb4d8365a4aa064d28405d03550a9d0a3be Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 9 Jun 2024 10:58:19 +0200 Subject: arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their contents appropriately, to prepare them for the ability to specify different CPU and GPU OPPs for each of the supported RK3588 SoC variants. As already discussed, [1][2][3][4] some of the RK3588 SoC variants require different OPPs, and it makes more sense to have the OPPs already defined when a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file to also include a separate rk3588*-opp.dtsi file. The choice of the SoC variant is already made by the inclusion of the SoC dtsi file into the board dts(i) file, and it doesn't make much sense to, effectively, allow the board dts(i) file to include and use an incompatible set of OPPs for the already selected RK3588 SoC variant. The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra" suffixes to denote the DT data shared between all RK5588 SoC variants, and the DT data shared between the unrestricted SoC variants, respectively. For example, the DT data for the RK3588 includes both rk3588-base.dtsi and rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT data for the RK3588S variant includes rk3588-base.dtsi only, because it's a restricted SoC variant, feature- and interface-wise. This achieves a more logical naming of the RK3588 SoC dtsi files, which reflects the way DT data for the SoC variants is built by "stacking" the SoC variant features made available through the "-base" and "-extra" SoC dtsi files. Additionally, the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are no longer parents to any other SoC variant dtsi files, which should help with making the new "stacking" approach cleaner and easier to follow. The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake of consistency. This also keeps the "-base" and "-extra" groups of the dtsi files together when looked at in a directory listing, which is helpful. The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no more than one SoC variant uses those OPPs, or be put into a separate "-opp" dtsi file that's shared between and included from two or more SoC variant dtsi files. An example for the former is the non-shared OPP data that should go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and an example for the latter is the shared OPP data that should be put into rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if the OPPs for the RK3588 and RK3588S SoC variants are ever made different, the shared rk3588-opp.dtsi file should be deleted and the new OPPs should be put directly into rk3588.dtsi and rk3588s.dtsi. [4] No functional changes are introduced, which was validated by decompiling and comparing all affected dtb files before and after these changes. As a side note, due to the nature of introduced changes, this commit is best viewed using the --break-rewrites option for git-log(1). [1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/ [2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/ [3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/ [4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 3447 ++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2670 +++++++++++++++ .../boot/dts/rockchip/rk3588-extra-pinctrl.dtsi | 516 +++ arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 413 +++ arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi | 516 --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 412 +-- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 3447 -------------------- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2669 +-------------- 9 files changed, 7053 insertions(+), 7039 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi delete mode 100644 arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi delete mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi new file mode 100644 index 000000000000..30db12c4fc82 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi @@ -0,0 +1,3447 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + auddsm { + /omit-if-no-ref/ + auddsm_pins: auddsm-pins { + rockchip,pins = + /* auddsm_ln */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PA2 4 &pcfg_pull_none>, + /* auddsm_rn */ + <3 RK_PA3 4 &pcfg_pull_none>, + /* auddsm_rp */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <4 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <0 RK_PC0 11 &pcfg_pull_none>, + /* can0_tx_m0 */ + <0 RK_PB7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <4 RK_PD5 9 &pcfg_pull_none>, + /* can0_tx_m1 */ + <4 RK_PD4 9 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <3 RK_PB5 9 &pcfg_pull_none>, + /* can1_tx_m0 */ + <3 RK_PB6 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <4 RK_PB2 12 &pcfg_pull_none>, + /* can1_tx_m1 */ + <4 RK_PB3 12 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rx_m0 */ + <3 RK_PC4 9 &pcfg_pull_none>, + /* can2_tx_m0 */ + <3 RK_PC5 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rx_m1 */ + <0 RK_PD4 10 &pcfg_pull_none>, + /* can2_tx_m1 */ + <0 RK_PD5 10 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_d10 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d11 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d12 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d13 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d14 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d15 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d1 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d2 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d3 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d4 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d5 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_d6 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* cif_d7 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_big0_avs */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* cpu_big1_avs */ + <0 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + /omit-if-no-ref/ + ddrphych0_pins: ddrphych0-pins { + rockchip,pins = + /* ddrphych0_dtb0 */ + <4 RK_PA0 7 &pcfg_pull_none>, + /* ddrphych0_dtb1 */ + <4 RK_PA1 7 &pcfg_pull_none>, + /* ddrphych0_dtb2 */ + <4 RK_PA2 7 &pcfg_pull_none>, + /* ddrphych0_dtb3 */ + <4 RK_PA3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + /omit-if-no-ref/ + ddrphych1_pins: ddrphych1-pins { + rockchip,pins = + /* ddrphych1_dtb0 */ + <4 RK_PA4 7 &pcfg_pull_none>, + /* ddrphych1_dtb1 */ + <4 RK_PA5 7 &pcfg_pull_none>, + /* ddrphych1_dtb2 */ + <4 RK_PA6 7 &pcfg_pull_none>, + /* ddrphych1_dtb3 */ + <4 RK_PA7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + /omit-if-no-ref/ + ddrphych2_pins: ddrphych2-pins { + rockchip,pins = + /* ddrphych2_dtb0 */ + <4 RK_PB0 7 &pcfg_pull_none>, + /* ddrphych2_dtb1 */ + <4 RK_PB1 7 &pcfg_pull_none>, + /* ddrphych2_dtb2 */ + <4 RK_PB2 7 &pcfg_pull_none>, + /* ddrphych2_dtb3 */ + <4 RK_PB3 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + /omit-if-no-ref/ + ddrphych3_pins: ddrphych3-pins { + rockchip,pins = + /* ddrphych3_dtb0 */ + <4 RK_PB4 7 &pcfg_pull_none>, + /* ddrphych3_dtb1 */ + <4 RK_PB5 7 &pcfg_pull_none>, + /* ddrphych3_dtb2 */ + <4 RK_PB6 7 &pcfg_pull_none>, + /* ddrphych3_dtb3 */ + <4 RK_PB7 7 &pcfg_pull_none>; + }; + }; + + dp0 { + /omit-if-no-ref/ + dp0m0_pins: dp0m0-pins { + rockchip,pins = + /* dp0_hpdin_m0 */ + <4 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m1_pins: dp0m1-pins { + rockchip,pins = + /* dp0_hpdin_m1 */ + <0 RK_PC4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m2_pins: dp0m2-pins { + rockchip,pins = + /* dp0_hpdin_m2 */ + <1 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + /omit-if-no-ref/ + dp1m0_pins: dp1m0-pins { + rockchip,pins = + /* dp1_hpdin_m0 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m1_pins: dp1m1-pins { + rockchip,pins = + /* dp1_hpdin_m1 */ + <0 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m2_pins: dp1m2-pins { + rockchip,pins = + /* dp1_hpdin_m2 */ + <1 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = + /* emmc_data_strobe */ + <2 RK_PA2 1 &pcfg_pull_down>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1_pins: eth1-pins { + rockchip,pins = + /* eth1_refclko_25m */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspim0_pins: fspim0-pins { + rockchip,pins = + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim0_cs1: fspim0-cs1 { + rockchip,pins = + /* fspi_cs1n_m0 */ + <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_pins: fspim2-pins { + rockchip,pins = + /* fspi_clk_m2 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m2 */ + <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m2 */ + <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m2 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m2 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m2 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_cs1: fspim2-cs1 { + rockchip,pins = + /* fspi_cs1n_m2 */ + <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1_miim: gmac1-miim { + rockchip,pins = + /* gmac1_mdc */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* gmac1_mdio */ + <3 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_clkinout: gmac1-clkinout { + rockchip,pins = + /* gmac1_mclkinout */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* gmac1_rxd1 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* gmac1_rxdv_crs */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclk */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* gmac1_txclk */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins = + /* gmac1_ppsclk */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins = + /* gmac1_ppstrig */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins = + /* gmac1_ptp_ref_clk */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_txer: gmac1-txer { + rockchip,pins = + /* gmac1_txer */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_rx_cec: hdmim0-rx-cec { + rockchip,pins = + /* hdmim0_rx_cec */ + <4 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_hpdin: hdmim0-rx-hpdin { + rockchip,pins = + /* hdmim0_rx_hpdin */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_scl: hdmim0-rx-scl { + rockchip,pins = + /* hdmim0_rx_scl */ + <0 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_sda: hdmim0-rx-sda { + rockchip,pins = + /* hdmim0_rx_sda */ + <0 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = + /* hdmim0_tx0_cec */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = + /* hdmim0_tx0_hpd */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = + /* hdmim0_tx0_scl */ + <4 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = + /* hdmim0_tx0_sda */ + <4 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_hpd: hdmim0-tx1-hpd { + rockchip,pins = + /* hdmim0_tx1_hpd */ + <1 RK_PA6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins = + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins = + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins = + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_cec: hdmim1-tx0-cec { + rockchip,pins = + /* hdmim1_tx0_cec */ + <0 RK_PD1 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_hpd: hdmim1-tx0-hpd { + rockchip,pins = + /* hdmim1_tx0_hpd */ + <3 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_scl: hdmim1-tx0-scl { + rockchip,pins = + /* hdmim1_tx0_scl */ + <0 RK_PD5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_sda: hdmim1-tx0-sda { + rockchip,pins = + /* hdmim1_tx0_sda */ + <0 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_cec: hdmim1-tx1-cec { + rockchip,pins = + /* hdmim1_tx1_cec */ + <0 RK_PD2 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_hpd: hdmim1-tx1-hpd { + rockchip,pins = + /* hdmim1_tx1_hpd */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_scl: hdmim1-tx1-scl { + rockchip,pins = + /* hdmim1_tx1_scl */ + <3 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_sda: hdmim1-tx1-sda { + rockchip,pins = + /* hdmim1_tx1_sda */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim2_rx_cec: hdmim2-rx-cec { + rockchip,pins = + /* hdmim2_rx_cec */ + <1 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_hpdin: hdmim2-rx-hpdin { + rockchip,pins = + /* hdmim2_rx_hpdin */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_scl: hdmim2-rx-scl { + rockchip,pins = + /* hdmim2_rx_scl */ + <1 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_sda: hdmim2-rx-sda { + rockchip,pins = + /* hdmim2_rx_sda */ + <1 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_scl: hdmim2-tx0-scl { + rockchip,pins = + /* hdmim2_tx0_scl */ + <3 RK_PC7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_sda: hdmim2-tx0-sda { + rockchip,pins = + /* hdmim2_tx0_sda */ + <3 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_cec: hdmim2-tx1-cec { + rockchip,pins = + /* hdmim2_tx1_cec */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_scl: hdmim2-tx1-scl { + rockchip,pins = + /* hdmim2_tx1_scl */ + <1 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_sda: hdmim2-tx1-sda { + rockchip,pins = + /* hdmim2_tx1_sda */ + <1 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug0: hdmi-debug0 { + rockchip,pins = + /* hdmi_debug0 */ + <1 RK_PA7 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug1: hdmi-debug1 { + rockchip,pins = + /* hdmi_debug1 */ + <1 RK_PB0 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug2: hdmi-debug2 { + rockchip,pins = + /* hdmi_debug2 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug3: hdmi-debug3 { + rockchip,pins = + /* hdmi_debug3 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug4: hdmi-debug4 { + rockchip,pins = + /* hdmi_debug4 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug5: hdmi-debug5 { + rockchip,pins = + /* hdmi_debug5 */ + <1 RK_PB4 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug6: hdmi-debug6 { + rockchip,pins = + /* hdmi_debug6 */ + <1 RK_PA0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PB3 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <0 RK_PD1 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <0 RK_PD2 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <0 RK_PB0 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <0 RK_PB1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins = + /* i2c1_scl_m2 */ + <0 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m2 */ + <0 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins = + /* i2c1_scl_m3 */ + <2 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m3 */ + <2 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins = + /* i2c1_scl_m4 */ + <1 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m4 */ + <1 RK_PD3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins = + /* i2c2_scl_m2 */ + <2 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m2 */ + <2 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins = + /* i2c2_scl_m4 */ + <1 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m4 */ + <1 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + /* i2c3_scl_m2 */ + <4 RK_PA4 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <4 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins = + /* i2c3_scl_m4 */ + <4 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m4 */ + <4 RK_PD1 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins = + /* i2c4_scl_m2 */ + <0 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m2 */ + <0 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins = + /* i2c4_scl_m3 */ + <1 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m3 */ + <1 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins = + /* i2c4_scl_m4 */ + <1 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m4 */ + <1 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PD0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + /* i2c5_scl_m2 */ + <4 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <4 RK_PA7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins = + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PC2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins = + /* i2c6_scl_m3 */ + <4 RK_PB1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m3 */ + <4 RK_PB0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins = + /* i2c6_scl_m4 */ + <3 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m4 */ + <3 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins = + /* i2c7_scl_m2 */ + <3 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m2 */ + <3 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins = + /* i2c7_scl_m3 */ + <4 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m3 */ + <4 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins = + /* i2c8_scl_m0 */ + <4 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m0 */ + <4 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins = + /* i2c8_scl_m2 */ + <1 RK_PD6 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m2 */ + <1 RK_PD7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins = + /* i2c8_scl_m3 */ + <4 RK_PC0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m3 */ + <4 RK_PC1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0_lrck: i2s0-lrck { + rockchip,pins = + /* i2s0_lrck */ + <1 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_mclk: i2s0-mclk { + rockchip,pins = + /* i2s0_mclk */ + <1 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sclk: i2s0-sclk { + rockchip,pins = + /* i2s0_sclk */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins = + /* i2s0_sdi0 */ + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins = + /* i2s0_sdi1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins = + /* i2s0_sdi2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins = + /* i2s0_sdi3 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins = + /* i2s0_sdo0 */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins = + /* i2s0_sdo1 */ + <1 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins = + /* i2s0_sdo2 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins = + /* i2s0_sdo3 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1m0_lrck */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1m0_sclk */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <4 RK_PA5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1m1_lrck */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1m1_sclk */ + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <0 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <0 RK_PD2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <0 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2m1_sclk */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3_lrck: i2s3-lrck { + rockchip,pins = + /* i2s3_lrck */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_mclk: i2s3-mclk { + rockchip,pins = + /* i2s3_mclk */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sclk: i2s3-sclk { + rockchip,pins = + /* i2s3_sclk */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdi: i2s3-sdi { + rockchip,pins = + /* i2s3_sdi */ + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdo: i2s3-sdo { + rockchip,pins = + /* i2s3_sdo */ + <3 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <4 RK_PD2 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <4 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <4 RK_PD0 5 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <4 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2_pins: jtagm2-pins { + rockchip,pins = + /* jtag_tck_m2 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + litcpu { + /omit-if-no-ref/ + litcpu_pins: litcpu-pins { + rockchip,pins = + /* litcpu_avs */ + <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcum0_pins: mcum0-pins { + rockchip,pins = + /* mcu_jtag_tck_m0 */ + <4 RK_PD4 5 &pcfg_pull_none>, + /* mcu_jtag_tms_m0 */ + <4 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mcum1_pins: mcum1-pins { + rockchip,pins = + /* mcu_jtag_tck_m1 */ + <3 RK_PD4 6 &pcfg_pull_none>, + /* mcu_jtag_tms_m1 */ + <3 RK_PD5 6 &pcfg_pull_none>; + }; + }; + + mipi { + /omit-if-no-ref/ + mipim0_camera0_clk: mipim0-camera0-clk { + rockchip,pins = + /* mipim0_camera0_clk */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera1_clk: mipim0-camera1-clk { + rockchip,pins = + /* mipim0_camera1_clk */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera2_clk: mipim0-camera2-clk { + rockchip,pins = + /* mipim0_camera2_clk */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera3_clk: mipim0-camera3-clk { + rockchip,pins = + /* mipim0_camera3_clk */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera4_clk: mipim0-camera4-clk { + rockchip,pins = + /* mipim0_camera4_clk */ + <1 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera0_clk: mipim1-camera0-clk { + rockchip,pins = + /* mipim1_camera0_clk */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera1_clk: mipim1-camera1-clk { + rockchip,pins = + /* mipim1_camera1_clk */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera2_clk: mipim1-camera2-clk { + rockchip,pins = + /* mipim1_camera2_clk */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera3_clk: mipim1-camera3-clk { + rockchip,pins = + /* mipim1_camera3_clk */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera4_clk: mipim1-camera4-clk { + rockchip,pins = + /* mipim1_camera4_clk */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te0: mipi-te0 { + rockchip,pins = + /* mipi_te0 */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te1: mipi-te1 { + rockchip,pins = + /* mipi_te1 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + /omit-if-no-ref/ + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m0 */ + <3 RK_PC7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m0 */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m1 */ + <4 RK_PC1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins = + /* pcie20x1_2_button_rstn */ + <4 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + /omit-if-no-ref/ + pcie30phy_pins: pcie30phy-pins { + rockchip,pins = + /* pcie30phy_dtb0 */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* pcie30phy_dtb1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m0 */ + <0 RK_PC0 12 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m0 */ + <0 RK_PC5 12 &pcfg_pull_none>, + /* pcie30x1_0_waken_m0 */ + <0 RK_PC4 12 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m0 */ + <0 RK_PB5 12 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m0 */ + <0 RK_PB7 12 &pcfg_pull_none>, + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m1 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m1 */ + <4 RK_PA4 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m1 */ + <4 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m1 */ + <4 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m2 */ + <1 RK_PB5 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m2 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m2 */ + <1 RK_PB3 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m2 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m2 */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins = + /* pcie30x1_0_button_rstn */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins = + /* pcie30x1_1_button_rstn */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m0 */ + <0 RK_PD1 12 &pcfg_pull_none>, + /* pcie30x2_perstn_m0 */ + <0 RK_PD4 12 &pcfg_pull_none>, + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m2 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m2 */ + <3 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m3 */ + <1 RK_PD7 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m3 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins = + /* pcie30x2_button_rstn */ + <3 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + /omit-if-no-ref/ + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m0 */ + <0 RK_PC6 12 &pcfg_pull_none>, + /* pcie30x4_perstn_m0 */ + <0 RK_PD0 12 &pcfg_pull_none>, + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m1 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m2 */ + <3 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m2 */ + <3 RK_PC6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m3 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m3 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins = + /* pcie30x4_button_rstn */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + /omit-if-no-ref/ + pdm0m0_clk: pdm0m0-clk { + rockchip,pins = + /* pdm0_clk0_m0 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins = + /* pdm0m0_clk1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins = + /* pdm0m0_sdi0 */ + <1 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins = + /* pdm0m0_sdi1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins = + /* pdm0m0_sdi2 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins = + /* pdm0m0_sdi3 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm0m1_clk: pdm0m1-clk { + rockchip,pins = + /* pdm0_clk0_m1 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins = + /* pdm0m1_clk1 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins = + /* pdm0m1_sdi0 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins = + /* pdm0m1_sdi1 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins = + /* pdm0m1_sdi2 */ + <0 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins = + /* pdm0m1_sdi3 */ + <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + /omit-if-no-ref/ + pdm1m0_clk: pdm1m0-clk { + rockchip,pins = + /* pdm1_clk0_m0 */ + <4 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins = + /* pdm1m0_clk1 */ + <4 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins = + /* pdm1m0_sdi0 */ + <4 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins = + /* pdm1m0_sdi1 */ + <4 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins = + /* pdm1m0_sdi2 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins = + /* pdm1m0_sdi3 */ + <4 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm1m1_clk: pdm1m1-clk { + rockchip,pins = + /* pdm1_clk0_m1 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins = + /* pdm1m1_clk1 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins = + /* pdm1m1_sdi0 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins = + /* pdm1m1_sdi1 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins = + /* pdm1m1_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins = + /* pdm1m1_sdi3 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_int_l */ + <0 RK_PA7 0 &pcfg_pull_up>, + /* pmic_sleep1 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pmic_sleep2 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pmic_sleep3 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* pmic_sleep4 */ + <0 RK_PC2 1 &pcfg_pull_none>, + /* pmic_sleep5 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pmic_sleep6 */ + <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m2_pins: pwm0m2-pins { + rockchip,pins = + /* pwm0_m2 */ + <1 RK_PA2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m2_pins: pwm1m2-pins { + rockchip,pins = + /* pwm1_m2 */ + <1 RK_PA3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <3 RK_PB1 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_ir_m0 */ + <0 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_ir_m1 */ + <3 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m2_pins: pwm3m2-pins { + rockchip,pins = + /* pwm3_ir_m2 */ + <1 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m3_pins: pwm3m3-pins { + rockchip,pins = + /* pwm3_ir_m3 */ + <1 RK_PA7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <0 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <4 RK_PC1 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_ir_m0 */ + <0 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_ir_m1 */ + <4 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m2_pins: pwm7m2-pins { + rockchip,pins = + /* pwm7_ir_m2 */ + <1 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <4 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m2_pins: pwm8m2-pins { + rockchip,pins = + /* pwm8_m2 */ + <3 RK_PD0 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <4 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m2_pins: pwm9m2-pins { + rockchip,pins = + /* pwm9_m2 */ + <3 RK_PD1 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PA0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <4 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m2_pins: pwm10m2-pins { + rockchip,pins = + /* pwm10_m2 */ + <3 RK_PD3 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_ir_m0 */ + <3 RK_PA1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_ir_m1 */ + <4 RK_PB4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m2_pins: pwm11m2-pins { + rockchip,pins = + /* pwm11_ir_m2 */ + <1 RK_PC4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m3_pins: pwm11m3-pins { + rockchip,pins = + /* pwm11_ir_m3 */ + <3 RK_PD5 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PB5 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m2_pins: pwm13m2-pins { + rockchip,pins = + /* pwm13_m2 */ + <1 RK_PB7 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m2_pins: pwm14m2-pins { + rockchip,pins = + /* pwm14_m2 */ + <1 RK_PD6 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_ir_m0 */ + <3 RK_PC3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_ir_m1 */ + <4 RK_PB3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m2_pins: pwm15m2-pins { + rockchip,pins = + /* pwm15_ir_m2 */ + <1 RK_PC6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m3_pins: pwm15m3-pins { + rockchip,pins = + /* pwm15_ir_m3 */ + <1 RK_PD7 11 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cp_pod */ + <0 RK_PC6 13 &pcfg_pull_none>, + /* sata_cpdet */ + <0 RK_PD4 13 &pcfg_pull_none>, + /* sata_mp_switch */ + <0 RK_PD5 13 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0m0_pins: sata0m0-pins { + rockchip,pins = + /* sata0_act_led_m0 */ + <4 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata0m1_pins: sata0m1-pins { + rockchip,pins = + /* sata0_act_led_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1m0_pins: sata1m0-pins { + rockchip,pins = + /* sata1_act_led_m0 */ + <4 RK_PB5 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata1m1_pins: sata1m1-pins { + rockchip,pins = + /* sata1_act_led_m1 */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2m0_pins: sata2m0-pins { + rockchip,pins = + /* sata2_act_led_m0 */ + <4 RK_PB1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata2m1_pins: sata2m1-pins { + rockchip,pins = + /* sata2_act_led_m1 */ + <1 RK_PB7 6 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom1_pins: sdiom1-pins { + rockchip,pins = + /* sdio_clk_m1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* sdio_cmd_m1 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* sdio_d0_m1 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* sdio_d1_m1 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* sdio_d2_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* sdio_d3_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + /omit-if-no-ref/ + spdif0m0_tx: spdif0m0-tx { + rockchip,pins = + /* spdif0m0_tx */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif0m1_tx: spdif0m1-tx { + rockchip,pins = + /* spdif0m1_tx */ + <4 RK_PB4 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + /omit-if-no-ref/ + spdif1m0_tx: spdif1m0-tx { + rockchip,pins = + /* spdif1m0_tx */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m1_tx: spdif1m1-tx { + rockchip,pins = + /* spdif1m1_tx */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m2_tx: spdif1m2-tx { + rockchip,pins = + /* spdif1m2_tx */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0_m0 */ + <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1_m0 */ + <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0_m1 */ + <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1_m1 */ + <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m2_pins: spi0m2-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + /* spi0_cs0_m2 */ + <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins = + /* spi0_cs1_m2 */ + <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m3_pins: spi0m3-pins { + rockchip,pins = + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins = + /* spi0_cs0_m3 */ + <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins = + /* spi0_cs1_m3 */ + <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0_m1 */ + <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins = + /* spi1_cs1_m1 */ + <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_pins: spi1m2-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins = + /* spi1_cs0_m2 */ + <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins = + /* spi1_cs1_m2 */ + <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0_m0 */ + <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1_m0 */ + <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0_m1 */ + <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1_m1 */ + <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_pins: spi2m2-pins { + rockchip,pins = + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins = + /* spi2_cs0_m2 */ + <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins = + /* spi2_cs1_m2 */ + <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0_m1 */ + <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1_m1 */ + <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_pins: spi3m2-pins { + rockchip,pins = + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins = + /* spi3_cs0_m2 */ + <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins = + /* spi3_cs1_m2 */ + <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_pins: spi3m3-pins { + rockchip,pins = + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins = + /* spi3_cs0_m3 */ + <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins = + /* spi3_cs1_m3 */ + <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi4 { + /omit-if-no-ref/ + spi4m0_pins: spi4m0-pins { + rockchip,pins = + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins = + /* spi4_cs0_m0 */ + <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins = + /* spi4_cs1_m0 */ + <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_pins: spi4m1-pins { + rockchip,pins = + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins = + /* spi4_cs0_m1 */ + <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins = + /* spi4_cs1_m1 */ + <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_pins: spi4m2-pins { + rockchip,pins = + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins = + /* spi4_cs0_m2 */ + <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut: tsadc-shut { + rockchip,pins = + /* tsadc_shut */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB0 4 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <4 RK_PA4 10 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <4 RK_PA3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PB7 10 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB6 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PD7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PD6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <0 RK_PD2 10 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <0 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <0 RK_PD0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <0 RK_PC7 10 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB6 10 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <4 RK_PD1 10 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <4 RK_PD0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <3 RK_PB2 10 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <3 RK_PB1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2_ctsn: uart2-ctsn { + rockchip,pins = + /* uart2_ctsn */ + <3 RK_PB4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2_rtsn: uart2-rtsn { + rockchip,pins = + /* uart2_rtsn */ + <3 RK_PB3 10 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <1 RK_PC0 10 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <1 RK_PC1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PB6 10 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <4 RK_PA6 10 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <4 RK_PA5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <1 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <1 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <1 RK_PD3 10 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <1 RK_PD2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <3 RK_PD0 10 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <3 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PB2 10 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PB3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <1 RK_PC7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <1 RK_PC5 10 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <4 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <4 RK_PD2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <4 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PC5 10 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PC4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <2 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <2 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PD5 10 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <1 RK_PA0 10 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <1 RK_PA1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <1 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <1 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m2_xfer: uart6m2-xfer { + rockchip,pins = + /* uart6_rx_m2 */ + <1 RK_PD1 10 &pcfg_pull_up>, + /* uart6_tx_m2 */ + <1 RK_PD0 10 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <3 RK_PC1 10 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <3 RK_PC0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <3 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <3 RK_PC2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rx_m2 */ + <1 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m2 */ + <1 RK_PB5 10 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <4 RK_PB1 10 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <4 RK_PB0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <4 RK_PB3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <4 RK_PB2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PA3 10 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PA2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PA5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <3 RK_PA4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8_xfer: uart8-xfer { + rockchip,pins = + /* uart8_rx_ */ + <4 RK_PB1 10 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <4 RK_PB5 10 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <4 RK_PB4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins = + /* uart9m1_ctsn */ + <4 RK_PA1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins = + /* uart9m1_rtsn */ + <4 RK_PA0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rx_m2 */ + <3 RK_PD4 10 &pcfg_pull_up>, + /* uart9_tx_m2 */ + <3 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins = + /* uart9m2_ctsn */ + <3 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins = + /* uart9m2_rtsn */ + <3 RK_PD2 10 &pcfg_pull_none>; + }; + }; + + vop { + /omit-if-no-ref/ + vop_pins: vop-pins { + rockchip,pins = + /* vop_post_empty */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + bt656 { + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi new file mode 100644 index 000000000000..629049f3dc16 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -0,0 +1,2670 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-level = <3>; + cache-unified; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + spll: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <702000000>; + clock-output-names = "spll"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; + + xin24m: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + pmu_sram: sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + ranges = <0 0x0 0x0010f000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible = "mmio-sram"; + reg = <0x0 0xfd600000 0x0 0x100000>; + ranges = <0x0 0x0 0xfd600000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf = <&php_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart0m1_xfer>; + pinctrl-names = "default"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #address-cells = <1>; + #power-domain-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = ; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPU1 { + reg = ; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_NPU2 { + reg = ; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu2>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + #power-domain-cells = <0>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = ; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = ; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VENC0 { + reg = ; + clocks = <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VENC1 { + reg = ; + clocks = <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = ; + clocks = <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + + power-domain@RK3588_PD_AV1 { + reg = ; + clocks = <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos = <&qos_av1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg = ; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = ; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RGA30 { + reg = ; + clocks = <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos = <&qos_rga3_0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = ; + clocks = <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VO0 { + reg = ; + clocks = <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos = <&qos_hdcp0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg = ; + clocks = <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VI { + reg = ; + clocks = <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_ISP1 { + reg = ; + clocks = <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_FEC { + reg = ; + clocks = <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = ; + clocks = <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos = <&qos_rga3_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_USB { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru ACLK_USB>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_GMAC { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_PCIE { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_AUDIO { + reg = ; + clocks = <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDMMC { + reg = ; + pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; + }; + }; + }; + + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = , + , + , + ; + rockchip,pmu = <&pmu1grf>; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + interrupt-controller; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; + ranges; + #address-cells = <2>; + #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c1m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart1m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart2m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart3m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 9>, <&dmac1 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart4m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 11>, <&dmac1 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart5m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 13>, <&dmac1 14>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart6m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 7>, <&dmac2 8>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart7m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 9>, <&dmac2 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart8m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 11>, <&dmac2 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart9m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c6m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-0 = <&i2c8m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + hdptxphy_hdmi0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + status = "disabled"; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + + system_sram2: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3588-base-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi new file mode 100644 index 000000000000..244c66faa161 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk32k { + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko_25m */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + }; + + fspi { + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins = + /* fspi_clk_m1 */ + <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m1 */ + <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m1 */ + <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m1 */ + <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m1 */ + <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim1_cs1: fspim1-cs1 { + rockchip,pins = + /* fspi_cs1n_m1 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <4 RK_PC4 1 &pcfg_pull_none>, + /* gmac0_mdio */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* gmac0_rxdv_crs */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins = + /* gmac0_ppsclk */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppstring: gmac0-ppstring { + rockchip,pins = + /* gmac0_ppstring */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins = + /* gmac0_ptp_refclk */ + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_txer: gmac0-txer { + rockchip,pins = + /* gmac0_txer */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_tx1_cec: hdmim0-tx1-cec { + rockchip,pins = + /* hdmim0_tx1_cec */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_scl: hdmim0-tx1-scl { + rockchip,pins = + /* hdmim0_tx1_scl */ + <2 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_sda: hdmim0-tx1-sda { + rockchip,pins = + /* hdmim0_tx1_sda */ + <2 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PC0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins = + /* i2c3_scl_m3 */ + <2 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m3 */ + <2 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <2 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <2 RK_PB4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins = + /* i2c5_scl_m4 */ + <2 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m4 */ + <2 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins = + /* i2c6_scl_m2 */ + <2 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m2 */ + <2 RK_PC2 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins = + /* i2c7_scl_m1 */ + <4 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m1 */ + <4 RK_PC4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins = + /* i2c8_scl_m1 */ + <2 RK_PB0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m1 */ + <2 RK_PB1 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m2_pins: pwm2m2-pins { + rockchip,pins = + /* pwm2_m2 */ + <4 RK_PC2 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <4 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m2_pins: pwm5m2-pins { + rockchip,pins = + /* pwm5_m2 */ + <4 RK_PC4 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <4 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m3_pins: pwm7m3-pins { + rockchip,pins = + /* pwm7_ir_m3 */ + <4 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom0_pins: sdiom0-pins { + rockchip,pins = + /* sdio_clk_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* sdio_cmd_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>, + /* sdio_d0_m0 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* sdio_d1_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* sdio_d2_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* sdio_d3_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m0 */ + <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m0 */ + <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0_m0 */ + <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1_m0 */ + <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clk_m0 */ + <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m0 */ + <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m0 */ + <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0_m0 */ + <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1_m0 */ + <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <2 RK_PB6 10 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <2 RK_PB7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PC1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PC0 10 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <2 RK_PA6 10 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <2 RK_PA7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PB1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB0 10 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <2 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <2 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <4 RK_PC6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <4 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PC4 10 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi new file mode 100644 index 000000000000..37101768999b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-base.dtsi" +#include "rk3588-extra-pinctrl.dtsi" + +/ { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi deleted file mode 100644 index 244c66faa161..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - clk32k { - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko_25m */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - }; - - fspi { - /omit-if-no-ref/ - fspim1_pins: fspim1-pins { - rockchip,pins = - /* fspi_clk_m1 */ - <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m1 */ - <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m1 */ - <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m1 */ - <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m1 */ - <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m1 */ - <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim1_cs1: fspim1-cs1 { - rockchip,pins = - /* fspi_cs1n_m1 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <4 RK_PC4 1 &pcfg_pull_none>, - /* gmac0_mdio */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PC1 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PC2 1 &pcfg_pull_none>, - /* gmac0_rxdv_crs */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_txd1 */ - <2 RK_PB7 1 &pcfg_pull_none>, - /* gmac0_txen */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PB0 1 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA6 1 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA7 1 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PB1 1 &pcfg_pull_none>, - /* gmac0_txd3 */ - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppsclk: gmac0-ppsclk { - rockchip,pins = - /* gmac0_ppsclk */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppstring: gmac0-ppstring { - rockchip,pins = - /* gmac0_ppstring */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ptp_refclk: gmac0-ptp-refclk { - rockchip,pins = - /* gmac0_ptp_refclk */ - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_txer: gmac0-txer { - rockchip,pins = - /* gmac0_txer */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_tx1_cec: hdmim0-tx1-cec { - rockchip,pins = - /* hdmim0_tx1_cec */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_scl: hdmim0-tx1-scl { - rockchip,pins = - /* hdmim0_tx1_scl */ - <2 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_sda: hdmim0-tx1-sda { - rockchip,pins = - /* hdmim0_tx1_sda */ - <2 RK_PB4 4 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m1_xfer: i2c0m1-xfer { - rockchip,pins = - /* i2c0_scl_m1 */ - <4 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c0_sda_m1 */ - <4 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_scl_m1 */ - <2 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m1 */ - <2 RK_PC0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m3_xfer: i2c3m3-xfer { - rockchip,pins = - /* i2c3_scl_m3 */ - <2 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m3 */ - <2 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_scl_m1 */ - <2 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m1 */ - <2 RK_PB4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m4_xfer: i2c5m4-xfer { - rockchip,pins = - /* i2c5_scl_m4 */ - <2 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m4 */ - <2 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m2_xfer: i2c6m2-xfer { - rockchip,pins = - /* i2c6_scl_m2 */ - <2 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m2 */ - <2 RK_PC2 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m1_xfer: i2c7m1-xfer { - rockchip,pins = - /* i2c7_scl_m1 */ - <4 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m1 */ - <4 RK_PC4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m1_xfer: i2c8m1-xfer { - rockchip,pins = - /* i2c8_scl_m1 */ - <2 RK_PB0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m1 */ - <2 RK_PB1 9 &pcfg_pull_none_smt>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m2_pins: pwm2m2-pins { - rockchip,pins = - /* pwm2_m2 */ - <4 RK_PC2 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m1_pins: pwm4m1-pins { - rockchip,pins = - /* pwm4_m1 */ - <4 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m2_pins: pwm5m2-pins { - rockchip,pins = - /* pwm5_m2 */ - <4 RK_PC4 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m2_pins: pwm6m2-pins { - rockchip,pins = - /* pwm6_m2 */ - <4 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m3_pins: pwm7m3-pins { - rockchip,pins = - /* pwm7_ir_m3 */ - <4 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom0_pins: sdiom0-pins { - rockchip,pins = - /* sdio_clk_m0 */ - <2 RK_PB3 2 &pcfg_pull_none>, - /* sdio_cmd_m0 */ - <2 RK_PB2 2 &pcfg_pull_none>, - /* sdio_d0_m0 */ - <2 RK_PA6 2 &pcfg_pull_none>, - /* sdio_d1_m0 */ - <2 RK_PA7 2 &pcfg_pull_none>, - /* sdio_d2_m0 */ - <2 RK_PB0 2 &pcfg_pull_none>, - /* sdio_d3_m0 */ - <2 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clk_m0 */ - <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m0 */ - <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m0 */ - <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0_m0 */ - <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1_m0 */ - <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clk_m0 */ - <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m0 */ - <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m0 */ - <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0_m0 */ - <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1_m0 */ - <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rx_m0 */ - <2 RK_PB6 10 &pcfg_pull_up>, - /* uart1_tx_m0 */ - <2 RK_PB7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PC1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PC0 10 &pcfg_pull_none>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rx_m0 */ - <2 RK_PA6 10 &pcfg_pull_up>, - /* uart6_tx_m0 */ - <2 RK_PA7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PB1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB0 10 &pcfg_pull_none>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rx_m0 */ - <2 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m0 */ - <2 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <4 RK_PC6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <4 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <4 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <4 RK_PC4 10 &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5984016b5f96..0bbeee399a63 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -1,413 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include "rk3588s.dtsi" -#include "rk3588-pinctrl.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; - }; - - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 22>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S8_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s6_8ch: i2s@fddf4000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf4000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 4>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S6_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s7_8ch: i2s@fddf8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 21>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S7_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s10_8ch: i2s@fde00000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfde00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 24>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S10_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0x0f>; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, - <0 0 0 2 &pcie3x4_intc 1>, - <0 0 0 3 &pcie3x4_intc 2>, - <0 0 0 4 &pcie3x4_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <3>; - msi-map = <0x0000 &its1 0x0000 0x1000>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x4_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x2: pcie@fe160000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, - <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, - <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <1>; - max-link-speed = <3>; - msi-map = <0x1000 &its1 0x1000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, - <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, - <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, - <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, - <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, - <0 0 0 2 &pcie2x1l0_intc 1>, - <0 0 0 3 &pcie2x1l0_intc 2>, - <0 0 0 4 &pcie2x1l0_intc 3>; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its0 0x2000 0x1000>; - num-lanes = <1>; - phys = <&combphy1_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, - <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, - <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata1: sata@fe220000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe220000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, - <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy1_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; - - pcie30phy: phy@fee80000 { - compatible = "rockchip,rk3588-pcie3-phy"; - reg = <0x0 0xfee80000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; - resets = <&cru SRST_PCIE30_PHY>; - reset-names = "phy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; -}; +#include "rk3588-extra.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 38b9dbf38a21..0bbeee399a63 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -4,4 +4,4 @@ * */ -#include "rk3588.dtsi" +#include "rk3588-extra.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi deleted file mode 100644 index 30db12c4fc82..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +++ /dev/null @@ -1,3447 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - auddsm { - /omit-if-no-ref/ - auddsm_pins: auddsm-pins { - rockchip,pins = - /* auddsm_ln */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* auddsm_lp */ - <3 RK_PA2 4 &pcfg_pull_none>, - /* auddsm_rn */ - <3 RK_PA3 4 &pcfg_pull_none>, - /* auddsm_rp */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <4 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <4 RK_PB7 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <4 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rx_m0 */ - <0 RK_PC0 11 &pcfg_pull_none>, - /* can0_tx_m0 */ - <0 RK_PB7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rx_m1 */ - <4 RK_PD5 9 &pcfg_pull_none>, - /* can0_tx_m1 */ - <4 RK_PD4 9 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rx_m0 */ - <3 RK_PB5 9 &pcfg_pull_none>, - /* can1_tx_m0 */ - <3 RK_PB6 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rx_m1 */ - <4 RK_PB2 12 &pcfg_pull_none>, - /* can1_tx_m1 */ - <4 RK_PB3 12 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rx_m0 */ - <3 RK_PC4 9 &pcfg_pull_none>, - /* can2_tx_m0 */ - <3 RK_PC5 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rx_m1 */ - <0 RK_PD4 10 &pcfg_pull_none>, - /* can2_tx_m1 */ - <0 RK_PD5 10 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PB0 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB2 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PC4 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PC5 1 &pcfg_pull_none>, - /* cif_d10 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d11 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d12 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d13 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d14 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d15 */ - <3 RK_PD3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d1 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d2 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d3 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d4 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d5 */ - <4 RK_PA5 1 &pcfg_pull_none>, - /* cif_d6 */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* cif_d7 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_big0_avs */ - <0 RK_PD1 2 &pcfg_pull_none>, - /* cpu_big1_avs */ - <0 RK_PD5 2 &pcfg_pull_none>; - }; - }; - - ddrphych0 { - /omit-if-no-ref/ - ddrphych0_pins: ddrphych0-pins { - rockchip,pins = - /* ddrphych0_dtb0 */ - <4 RK_PA0 7 &pcfg_pull_none>, - /* ddrphych0_dtb1 */ - <4 RK_PA1 7 &pcfg_pull_none>, - /* ddrphych0_dtb2 */ - <4 RK_PA2 7 &pcfg_pull_none>, - /* ddrphych0_dtb3 */ - <4 RK_PA3 7 &pcfg_pull_none>; - }; - }; - - ddrphych1 { - /omit-if-no-ref/ - ddrphych1_pins: ddrphych1-pins { - rockchip,pins = - /* ddrphych1_dtb0 */ - <4 RK_PA4 7 &pcfg_pull_none>, - /* ddrphych1_dtb1 */ - <4 RK_PA5 7 &pcfg_pull_none>, - /* ddrphych1_dtb2 */ - <4 RK_PA6 7 &pcfg_pull_none>, - /* ddrphych1_dtb3 */ - <4 RK_PA7 7 &pcfg_pull_none>; - }; - }; - - ddrphych2 { - /omit-if-no-ref/ - ddrphych2_pins: ddrphych2-pins { - rockchip,pins = - /* ddrphych2_dtb0 */ - <4 RK_PB0 7 &pcfg_pull_none>, - /* ddrphych2_dtb1 */ - <4 RK_PB1 7 &pcfg_pull_none>, - /* ddrphych2_dtb2 */ - <4 RK_PB2 7 &pcfg_pull_none>, - /* ddrphych2_dtb3 */ - <4 RK_PB3 7 &pcfg_pull_none>; - }; - }; - - ddrphych3 { - /omit-if-no-ref/ - ddrphych3_pins: ddrphych3-pins { - rockchip,pins = - /* ddrphych3_dtb0 */ - <4 RK_PB4 7 &pcfg_pull_none>, - /* ddrphych3_dtb1 */ - <4 RK_PB5 7 &pcfg_pull_none>, - /* ddrphych3_dtb2 */ - <4 RK_PB6 7 &pcfg_pull_none>, - /* ddrphych3_dtb3 */ - <4 RK_PB7 7 &pcfg_pull_none>; - }; - }; - - dp0 { - /omit-if-no-ref/ - dp0m0_pins: dp0m0-pins { - rockchip,pins = - /* dp0_hpdin_m0 */ - <4 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m1_pins: dp0m1-pins { - rockchip,pins = - /* dp0_hpdin_m1 */ - <0 RK_PC4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m2_pins: dp0m2-pins { - rockchip,pins = - /* dp0_hpdin_m2 */ - <1 RK_PA0 5 &pcfg_pull_none>; - }; - }; - - dp1 { - /omit-if-no-ref/ - dp1m0_pins: dp1m0-pins { - rockchip,pins = - /* dp1_hpdin_m0 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m1_pins: dp1m1-pins { - rockchip,pins = - /* dp1_hpdin_m1 */ - <0 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m2_pins: dp1m2-pins { - rockchip,pins = - /* dp1_hpdin_m2 */ - <1 RK_PA1 5 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_data_strobe: emmc-data-strobe { - rockchip,pins = - /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_down>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1_pins: eth1-pins { - rockchip,pins = - /* eth1_refclko_25m */ - <3 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspim0_pins: fspim0-pins { - rockchip,pins = - /* fspi_clk_m0 */ - <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m0 */ - <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m0 */ - <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m0 */ - <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m0 */ - <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m0 */ - <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim0_cs1: fspim0-cs1 { - rockchip,pins = - /* fspi_cs1n_m0 */ - <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_pins: fspim2-pins { - rockchip,pins = - /* fspi_clk_m2 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m2 */ - <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m2 */ - <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m2 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m2 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m2 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_cs1: fspim2-cs1 { - rockchip,pins = - /* fspi_cs1n_m2 */ - <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1_miim: gmac1-miim { - rockchip,pins = - /* gmac1_mdc */ - <3 RK_PC2 1 &pcfg_pull_none>, - /* gmac1_mdio */ - <3 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_clkinout: gmac1-clkinout { - rockchip,pins = - /* gmac1_mclkinout */ - <3 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rx_bus2: gmac1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* gmac1_rxd1 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* gmac1_rxdv_crs */ - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_tx_bus2: gmac1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* gmac1_txd1 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* gmac1_txen */ - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_clk: gmac1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclk */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* gmac1_txclk */ - <3 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_bus: gmac1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* gmac1_rxd3 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* gmac1_txd2 */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* gmac1_txd3 */ - <3 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppsclk: gmac1-ppsclk { - rockchip,pins = - /* gmac1_ppsclk */ - <3 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppstrig: gmac1-ppstrig { - rockchip,pins = - /* gmac1_ppstrig */ - <3 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { - rockchip,pins = - /* gmac1_ptp_ref_clk */ - <3 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_txer: gmac1-txer { - rockchip,pins = - /* gmac1_txer */ - <3 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_rx_cec: hdmim0-rx-cec { - rockchip,pins = - /* hdmim0_rx_cec */ - <4 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_hpdin: hdmim0-rx-hpdin { - rockchip,pins = - /* hdmim0_rx_hpdin */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_scl: hdmim0-rx-scl { - rockchip,pins = - /* hdmim0_rx_scl */ - <0 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_sda: hdmim0-rx-sda { - rockchip,pins = - /* hdmim0_rx_sda */ - <0 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_cec: hdmim0-tx0-cec { - rockchip,pins = - /* hdmim0_tx0_cec */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_hpd: hdmim0-tx0-hpd { - rockchip,pins = - /* hdmim0_tx0_hpd */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_scl: hdmim0-tx0-scl { - rockchip,pins = - /* hdmim0_tx0_scl */ - <4 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_sda: hdmim0-tx0-sda { - rockchip,pins = - /* hdmim0_tx0_sda */ - <4 RK_PC0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_hpd: hdmim0-tx1-hpd { - rockchip,pins = - /* hdmim0_tx1_hpd */ - <1 RK_PA6 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim1_rx_cec: hdmim1-rx-cec { - rockchip,pins = - /* hdmim1_rx_cec */ - <3 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_hpdin: hdmim1-rx-hpdin { - rockchip,pins = - /* hdmim1_rx_hpdin */ - <3 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_scl: hdmim1-rx-scl { - rockchip,pins = - /* hdmim1_rx_scl */ - <3 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_sda: hdmim1-rx-sda { - rockchip,pins = - /* hdmim1_rx_sda */ - <3 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_cec: hdmim1-tx0-cec { - rockchip,pins = - /* hdmim1_tx0_cec */ - <0 RK_PD1 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_hpd: hdmim1-tx0-hpd { - rockchip,pins = - /* hdmim1_tx0_hpd */ - <3 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_scl: hdmim1-tx0-scl { - rockchip,pins = - /* hdmim1_tx0_scl */ - <0 RK_PD5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_sda: hdmim1-tx0-sda { - rockchip,pins = - /* hdmim1_tx0_sda */ - <0 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_cec: hdmim1-tx1-cec { - rockchip,pins = - /* hdmim1_tx1_cec */ - <0 RK_PD2 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_hpd: hdmim1-tx1-hpd { - rockchip,pins = - /* hdmim1_tx1_hpd */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_scl: hdmim1-tx1-scl { - rockchip,pins = - /* hdmim1_tx1_scl */ - <3 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_sda: hdmim1-tx1-sda { - rockchip,pins = - /* hdmim1_tx1_sda */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim2_rx_cec: hdmim2-rx-cec { - rockchip,pins = - /* hdmim2_rx_cec */ - <1 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_hpdin: hdmim2-rx-hpdin { - rockchip,pins = - /* hdmim2_rx_hpdin */ - <1 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_scl: hdmim2-rx-scl { - rockchip,pins = - /* hdmim2_rx_scl */ - <1 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_sda: hdmim2-rx-sda { - rockchip,pins = - /* hdmim2_rx_sda */ - <1 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_scl: hdmim2-tx0-scl { - rockchip,pins = - /* hdmim2_tx0_scl */ - <3 RK_PC7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_sda: hdmim2-tx0-sda { - rockchip,pins = - /* hdmim2_tx0_sda */ - <3 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_cec: hdmim2-tx1-cec { - rockchip,pins = - /* hdmim2_tx1_cec */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_scl: hdmim2-tx1-scl { - rockchip,pins = - /* hdmim2_tx1_scl */ - <1 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_sda: hdmim2-tx1-sda { - rockchip,pins = - /* hdmim2_tx1_sda */ - <1 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug0: hdmi-debug0 { - rockchip,pins = - /* hdmi_debug0 */ - <1 RK_PA7 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug1: hdmi-debug1 { - rockchip,pins = - /* hdmi_debug1 */ - <1 RK_PB0 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug2: hdmi-debug2 { - rockchip,pins = - /* hdmi_debug2 */ - <1 RK_PB1 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug3: hdmi-debug3 { - rockchip,pins = - /* hdmi_debug3 */ - <1 RK_PB2 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug4: hdmi-debug4 { - rockchip,pins = - /* hdmi_debug4 */ - <1 RK_PB3 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug5: hdmi-debug5 { - rockchip,pins = - /* hdmi_debug5 */ - <1 RK_PB4 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug6: hdmi-debug6 { - rockchip,pins = - /* hdmi_debug6 */ - <1 RK_PA0 7 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m0_xfer: i2c0m0-xfer { - rockchip,pins = - /* i2c0_scl_m0 */ - <0 RK_PB3 2 &pcfg_pull_none_smt>, - /* i2c0_sda_m0 */ - <0 RK_PA6 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c0m2_xfer: i2c0m2-xfer { - rockchip,pins = - /* i2c0_scl_m2 */ - <0 RK_PD1 3 &pcfg_pull_none_smt>, - /* i2c0_sda_m2 */ - <0 RK_PD2 3 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1m0_xfer: i2c1m0-xfer { - rockchip,pins = - /* i2c1_scl_m0 */ - <0 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m0 */ - <0 RK_PB6 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m1_xfer: i2c1m1-xfer { - rockchip,pins = - /* i2c1_scl_m1 */ - <0 RK_PB0 2 &pcfg_pull_none_smt>, - /* i2c1_sda_m1 */ - <0 RK_PB1 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m2_xfer: i2c1m2-xfer { - rockchip,pins = - /* i2c1_scl_m2 */ - <0 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m2 */ - <0 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m3_xfer: i2c1m3-xfer { - rockchip,pins = - /* i2c1_scl_m3 */ - <2 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m3 */ - <2 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m4_xfer: i2c1m4-xfer { - rockchip,pins = - /* i2c1_scl_m4 */ - <1 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m4 */ - <1 RK_PD3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_scl_m0 */ - <0 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m0 */ - <0 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m2_xfer: i2c2m2-xfer { - rockchip,pins = - /* i2c2_scl_m2 */ - <2 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m2 */ - <2 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m3_xfer: i2c2m3-xfer { - rockchip,pins = - /* i2c2_scl_m3 */ - <1 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m3 */ - <1 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m4_xfer: i2c2m4-xfer { - rockchip,pins = - /* i2c2_scl_m4 */ - <1 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m4 */ - <1 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_scl_m0 */ - <1 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m0 */ - <1 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_scl_m1 */ - <3 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m1 */ - <3 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - /* i2c3_scl_m2 */ - <4 RK_PA4 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m2 */ - <4 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m4_xfer: i2c3m4-xfer { - rockchip,pins = - /* i2c3_scl_m4 */ - <4 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m4 */ - <4 RK_PD1 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_scl_m0 */ - <3 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m0 */ - <3 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m2_xfer: i2c4m2-xfer { - rockchip,pins = - /* i2c4_scl_m2 */ - <0 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m2 */ - <0 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m3_xfer: i2c4m3-xfer { - rockchip,pins = - /* i2c4_scl_m3 */ - <1 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m3 */ - <1 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m4_xfer: i2c4m4-xfer { - rockchip,pins = - /* i2c4_scl_m4 */ - <1 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m4 */ - <1 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_scl_m0 */ - <3 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m0 */ - <3 RK_PD0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_scl_m1 */ - <4 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m1 */ - <4 RK_PB7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m2_xfer: i2c5m2-xfer { - rockchip,pins = - /* i2c5_scl_m2 */ - <4 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m2 */ - <4 RK_PA7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m3_xfer: i2c5m3-xfer { - rockchip,pins = - /* i2c5_scl_m3 */ - <1 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m3 */ - <1 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m0_xfer: i2c6m0-xfer { - rockchip,pins = - /* i2c6_scl_m0 */ - <0 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m0 */ - <0 RK_PC7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m1_xfer: i2c6m1-xfer { - rockchip,pins = - /* i2c6_scl_m1 */ - <1 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m1 */ - <1 RK_PC2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m3_xfer: i2c6m3-xfer { - rockchip,pins = - /* i2c6_scl_m3 */ - <4 RK_PB1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m3 */ - <4 RK_PB0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m4_xfer: i2c6m4-xfer { - rockchip,pins = - /* i2c6_scl_m4 */ - <3 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m4 */ - <3 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m0_xfer: i2c7m0-xfer { - rockchip,pins = - /* i2c7_scl_m0 */ - <1 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m0 */ - <1 RK_PD1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m2_xfer: i2c7m2-xfer { - rockchip,pins = - /* i2c7_scl_m2 */ - <3 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m2 */ - <3 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m3_xfer: i2c7m3-xfer { - rockchip,pins = - /* i2c7_scl_m3 */ - <4 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m3 */ - <4 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m0_xfer: i2c8m0-xfer { - rockchip,pins = - /* i2c8_scl_m0 */ - <4 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m0 */ - <4 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m2_xfer: i2c8m2-xfer { - rockchip,pins = - /* i2c8_scl_m2 */ - <1 RK_PD6 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m2 */ - <1 RK_PD7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m3_xfer: i2c8m3-xfer { - rockchip,pins = - /* i2c8_scl_m3 */ - <4 RK_PC0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m3 */ - <4 RK_PC1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m4_xfer: i2c8m4-xfer { - rockchip,pins = - /* i2c8_scl_m4 */ - <3 RK_PC2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m4 */ - <3 RK_PC3 9 &pcfg_pull_none_smt>; - }; - }; - - i2s0 { - /omit-if-no-ref/ - i2s0_lrck: i2s0-lrck { - rockchip,pins = - /* i2s0_lrck */ - <1 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_mclk: i2s0-mclk { - rockchip,pins = - /* i2s0_mclk */ - <1 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sclk: i2s0-sclk { - rockchip,pins = - /* i2s0_sclk */ - <1 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi0: i2s0-sdi0 { - rockchip,pins = - /* i2s0_sdi0 */ - <1 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi1: i2s0-sdi1 { - rockchip,pins = - /* i2s0_sdi1 */ - <1 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi2: i2s0-sdi2 { - rockchip,pins = - /* i2s0_sdi2 */ - <1 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi3: i2s0-sdi3 { - rockchip,pins = - /* i2s0_sdi3 */ - <1 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo0: i2s0-sdo0 { - rockchip,pins = - /* i2s0_sdo0 */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo1: i2s0-sdo1 { - rockchip,pins = - /* i2s0_sdo1 */ - <1 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo2: i2s0-sdo2 { - rockchip,pins = - /* i2s0_sdo2 */ - <1 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo3: i2s0-sdo3 { - rockchip,pins = - /* i2s0_sdo3 */ - <1 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrck: i2s1m0-lrck { - rockchip,pins = - /* i2s1m0_lrck */ - <4 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <4 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclk: i2s1m0-sclk { - rockchip,pins = - /* i2s1m0_sclk */ - <4 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <4 RK_PA5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <4 RK_PA7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <4 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <4 RK_PB4 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - i2s1m1_lrck: i2s1m1-lrck { - rockchip,pins = - /* i2s1m1_lrck */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclk: i2s1m1-sclk { - rockchip,pins = - /* i2s1m1_sclk */ - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <0 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <0 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <0 RK_PD2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <0 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <0 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrck: i2s2m1-lrck { - rockchip,pins = - /* i2s2m1_lrck */ - <3 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = - /* i2s2m1_sclk */ - <3 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <3 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3_lrck: i2s3-lrck { - rockchip,pins = - /* i2s3_lrck */ - <3 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_mclk: i2s3-mclk { - rockchip,pins = - /* i2s3_mclk */ - <3 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sclk: i2s3-sclk { - rockchip,pins = - /* i2s3_sclk */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdi: i2s3-sdi { - rockchip,pins = - /* i2s3_sdi */ - <3 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdo: i2s3-sdo { - rockchip,pins = - /* i2s3_sdo */ - <3 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtagm0_pins: jtagm0-pins { - rockchip,pins = - /* jtag_tck_m0 */ - <4 RK_PD2 5 &pcfg_pull_none>, - /* jtag_tms_m0 */ - <4 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm1_pins: jtagm1-pins { - rockchip,pins = - /* jtag_tck_m1 */ - <4 RK_PD0 5 &pcfg_pull_none>, - /* jtag_tms_m1 */ - <4 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm2_pins: jtagm2-pins { - rockchip,pins = - /* jtag_tck_m2 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* jtag_tms_m2 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - }; - - litcpu { - /omit-if-no-ref/ - litcpu_pins: litcpu-pins { - rockchip,pins = - /* litcpu_avs */ - <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcum0_pins: mcum0-pins { - rockchip,pins = - /* mcu_jtag_tck_m0 */ - <4 RK_PD4 5 &pcfg_pull_none>, - /* mcu_jtag_tms_m0 */ - <4 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mcum1_pins: mcum1-pins { - rockchip,pins = - /* mcu_jtag_tck_m1 */ - <3 RK_PD4 6 &pcfg_pull_none>, - /* mcu_jtag_tms_m1 */ - <3 RK_PD5 6 &pcfg_pull_none>; - }; - }; - - mipi { - /omit-if-no-ref/ - mipim0_camera0_clk: mipim0-camera0-clk { - rockchip,pins = - /* mipim0_camera0_clk */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera1_clk: mipim0-camera1-clk { - rockchip,pins = - /* mipim0_camera1_clk */ - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera2_clk: mipim0-camera2-clk { - rockchip,pins = - /* mipim0_camera2_clk */ - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera3_clk: mipim0-camera3-clk { - rockchip,pins = - /* mipim0_camera3_clk */ - <1 RK_PD6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera4_clk: mipim0-camera4-clk { - rockchip,pins = - /* mipim0_camera4_clk */ - <1 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera0_clk: mipim1-camera0-clk { - rockchip,pins = - /* mipim1_camera0_clk */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera1_clk: mipim1-camera1-clk { - rockchip,pins = - /* mipim1_camera1_clk */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera2_clk: mipim1-camera2-clk { - rockchip,pins = - /* mipim1_camera2_clk */ - <3 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera3_clk: mipim1-camera3-clk { - rockchip,pins = - /* mipim1_camera3_clk */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera4_clk: mipim1-camera4-clk { - rockchip,pins = - /* mipim1_camera4_clk */ - <3 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te0: mipi-te0 { - rockchip,pins = - /* mipi_te0 */ - <3 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te1: mipi-te1 { - rockchip,pins = - /* mipi_te1 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - }; - - pcie20x1 { - /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m0 */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m1 */ - <4 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { - rockchip,pins = - /* pcie20x1_2_button_rstn */ - <4 RK_PB3 4 &pcfg_pull_none>; - }; - }; - - pcie30phy { - /omit-if-no-ref/ - pcie30phy_pins: pcie30phy-pins { - rockchip,pins = - /* pcie30phy_dtb0 */ - <1 RK_PC4 4 &pcfg_pull_none>, - /* pcie30phy_dtb1 */ - <1 RK_PD1 4 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, - /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, - /* pcie30x1_1_waken_m0 */ - <0 RK_PB6 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m2 */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { - rockchip,pins = - /* pcie30x1_0_button_rstn */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { - rockchip,pins = - /* pcie30x1_1_button_rstn */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, - /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, - /* pcie30x2_waken_m0 */ - <0 RK_PD2 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x2_waken_m1 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_waken_m2 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, - /* pcie30x2_waken_m3 */ - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_button_rstn: pcie30x2-button-rstn { - rockchip,pins = - /* pcie30x2_button_rstn */ - <3 RK_PC1 4 &pcfg_pull_none>; - }; - }; - - pcie30x4 { - /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, - /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, - /* pcie30x4_waken_m0 */ - <0 RK_PC7 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m1 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m2 */ - <3 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie30x4_waken_m3 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4_button_rstn: pcie30x4-button-rstn { - rockchip,pins = - /* pcie30x4_button_rstn */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pdm0 { - /omit-if-no-ref/ - pdm0m0_clk: pdm0m0-clk { - rockchip,pins = - /* pdm0_clk0_m0 */ - <1 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_clk1: pdm0m0-clk1 { - rockchip,pins = - /* pdm0m0_clk1 */ - <1 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi0: pdm0m0-sdi0 { - rockchip,pins = - /* pdm0m0_sdi0 */ - <1 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi1: pdm0m0-sdi1 { - rockchip,pins = - /* pdm0m0_sdi1 */ - <1 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi2: pdm0m0-sdi2 { - rockchip,pins = - /* pdm0m0_sdi2 */ - <1 RK_PD2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi3: pdm0m0-sdi3 { - rockchip,pins = - /* pdm0m0_sdi3 */ - <1 RK_PD3 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm0m1_clk: pdm0m1-clk { - rockchip,pins = - /* pdm0_clk0_m1 */ - <0 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_clk1: pdm0m1-clk1 { - rockchip,pins = - /* pdm0m1_clk1 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi0: pdm0m1-sdi0 { - rockchip,pins = - /* pdm0m1_sdi0 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi1: pdm0m1-sdi1 { - rockchip,pins = - /* pdm0m1_sdi1 */ - <0 RK_PD0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi2: pdm0m1-sdi2 { - rockchip,pins = - /* pdm0m1_sdi2 */ - <0 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi3: pdm0m1-sdi3 { - rockchip,pins = - /* pdm0m1_sdi3 */ - <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pdm1 { - /omit-if-no-ref/ - pdm1m0_clk: pdm1m0-clk { - rockchip,pins = - /* pdm1_clk0_m0 */ - <4 RK_PD5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_clk1: pdm1m0-clk1 { - rockchip,pins = - /* pdm1m0_clk1 */ - <4 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi0: pdm1m0-sdi0 { - rockchip,pins = - /* pdm1m0_sdi0 */ - <4 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi1: pdm1m0-sdi1 { - rockchip,pins = - /* pdm1m0_sdi1 */ - <4 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi2: pdm1m0-sdi2 { - rockchip,pins = - /* pdm1m0_sdi2 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi3: pdm1m0-sdi3 { - rockchip,pins = - /* pdm1m0_sdi3 */ - <4 RK_PD0 2 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm1m1_clk: pdm1m1-clk { - rockchip,pins = - /* pdm1_clk0_m1 */ - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_clk1: pdm1m1-clk1 { - rockchip,pins = - /* pdm1m1_clk1 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi0: pdm1m1-sdi0 { - rockchip,pins = - /* pdm1m1_sdi0 */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi1: pdm1m1-sdi1 { - rockchip,pins = - /* pdm1m1_sdi1 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi2: pdm1m1-sdi2 { - rockchip,pins = - /* pdm1m1_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi3: pdm1m1-sdi3 { - rockchip,pins = - /* pdm1m1_sdi3 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_int_l */ - <0 RK_PA7 0 &pcfg_pull_up>, - /* pmic_sleep1 */ - <0 RK_PA2 1 &pcfg_pull_none>, - /* pmic_sleep2 */ - <0 RK_PA3 1 &pcfg_pull_none>, - /* pmic_sleep3 */ - <0 RK_PC1 1 &pcfg_pull_none>, - /* pmic_sleep4 */ - <0 RK_PC2 1 &pcfg_pull_none>, - /* pmic_sleep5 */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* pmic_sleep6 */ - <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug */ - <0 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <1 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m2_pins: pwm0m2-pins { - rockchip,pins = - /* pwm0_m2 */ - <1 RK_PA2 11 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <1 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m2_pins: pwm1m2-pins { - rockchip,pins = - /* pwm1_m2 */ - <1 RK_PA3 11 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <3 RK_PB1 11 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3m0_pins: pwm3m0-pins { - rockchip,pins = - /* pwm3_ir_m0 */ - <0 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m1_pins: pwm3m1-pins { - rockchip,pins = - /* pwm3_ir_m1 */ - <3 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m2_pins: pwm3m2-pins { - rockchip,pins = - /* pwm3_ir_m2 */ - <1 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m3_pins: pwm3m3-pins { - rockchip,pins = - /* pwm3_ir_m3 */ - <1 RK_PA7 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m0_pins: pwm4m0-pins { - rockchip,pins = - /* pwm4_m0 */ - <0 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m0_pins: pwm5m0-pins { - rockchip,pins = - /* pwm5_m0 */ - <0 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm5m1_pins: pwm5m1-pins { - rockchip,pins = - /* pwm5_m1 */ - <0 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m0_pins: pwm6m0-pins { - rockchip,pins = - /* pwm6_m0 */ - <0 RK_PC7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm6m1_pins: pwm6m1-pins { - rockchip,pins = - /* pwm6_m1 */ - <4 RK_PC1 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m0_pins: pwm7m0-pins { - rockchip,pins = - /* pwm7_ir_m0 */ - <0 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m1_pins: pwm7m1-pins { - rockchip,pins = - /* pwm7_ir_m1 */ - <4 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m2_pins: pwm7m2-pins { - rockchip,pins = - /* pwm7_ir_m2 */ - <1 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PA7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <4 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m2_pins: pwm8m2-pins { - rockchip,pins = - /* pwm8_m2 */ - <3 RK_PD0 11 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <4 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m2_pins: pwm9m2-pins { - rockchip,pins = - /* pwm9_m2 */ - <3 RK_PD1 11 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PA0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <4 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m2_pins: pwm10m2-pins { - rockchip,pins = - /* pwm10_m2 */ - <3 RK_PD3 11 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_ir_m0 */ - <3 RK_PA1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_ir_m1 */ - <4 RK_PB4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m2_pins: pwm11m2-pins { - rockchip,pins = - /* pwm11_ir_m2 */ - <1 RK_PC4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m3_pins: pwm11m3-pins { - rockchip,pins = - /* pwm11_ir_m3 */ - <3 RK_PD5 11 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PB5 11 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m2_pins: pwm13m2-pins { - rockchip,pins = - /* pwm13_m2 */ - <1 RK_PB7 11 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m2_pins: pwm14m2-pins { - rockchip,pins = - /* pwm14_m2 */ - <1 RK_PD6 11 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_ir_m0 */ - <3 RK_PC3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_ir_m1 */ - <4 RK_PB3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m2_pins: pwm15m2-pins { - rockchip,pins = - /* pwm15_ir_m2 */ - <1 RK_PC6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m3_pins: pwm15m3-pins { - rockchip,pins = - /* pwm15_ir_m3 */ - <1 RK_PD7 11 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_out */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cp_pod */ - <0 RK_PC6 13 &pcfg_pull_none>, - /* sata_cpdet */ - <0 RK_PD4 13 &pcfg_pull_none>, - /* sata_mp_switch */ - <0 RK_PD5 13 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0m0_pins: sata0m0-pins { - rockchip,pins = - /* sata0_act_led_m0 */ - <4 RK_PB6 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata0m1_pins: sata0m1-pins { - rockchip,pins = - /* sata0_act_led_m1 */ - <1 RK_PB3 6 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1m0_pins: sata1m0-pins { - rockchip,pins = - /* sata1_act_led_m0 */ - <4 RK_PB5 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata1m1_pins: sata1m1-pins { - rockchip,pins = - /* sata1_act_led_m1 */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2m0_pins: sata2m0-pins { - rockchip,pins = - /* sata2_act_led_m0 */ - <4 RK_PB1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata2m1_pins: sata2m1-pins { - rockchip,pins = - /* sata2_act_led_m1 */ - <1 RK_PB7 6 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom1_pins: sdiom1-pins { - rockchip,pins = - /* sdio_clk_m1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* sdio_cmd_m1 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* sdio_d0_m1 */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* sdio_d1_m1 */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* sdio_d2_m1 */ - <3 RK_PA2 2 &pcfg_pull_none>, - /* sdio_d3_m1 */ - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - /omit-if-no-ref/ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - /* sdmmc_d0 */ - <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d1 */ - <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d2 */ - <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d3 */ - <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_clk: sdmmc-clk { - rockchip,pins = - /* sdmmc_clk */ - <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - /* sdmmc_cmd */ - <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_det: sdmmc-det { - rockchip,pins = - /* sdmmc_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - /* sdmmc_pwren */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - spdif0 { - /omit-if-no-ref/ - spdif0m0_tx: spdif0m0-tx { - rockchip,pins = - /* spdif0m0_tx */ - <1 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif0m1_tx: spdif0m1-tx { - rockchip,pins = - /* spdif0m1_tx */ - <4 RK_PB4 6 &pcfg_pull_none>; - }; - }; - - spdif1 { - /omit-if-no-ref/ - spdif1m0_tx: spdif1m0-tx { - rockchip,pins = - /* spdif1m0_tx */ - <1 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m1_tx: spdif1m1-tx { - rockchip,pins = - /* spdif1m1_tx */ - <4 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m2_tx: spdif1m2-tx { - rockchip,pins = - /* spdif1m2_tx */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clk_m0 */ - <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m0 */ - <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m0 */ - <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0_m0 */ - <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1_m0 */ - <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clk_m1 */ - <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m1 */ - <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m1 */ - <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0_m1 */ - <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = - /* spi0_cs1_m1 */ - <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m2_pins: spi0m2-pins { - rockchip,pins = - /* spi0_clk_m2 */ - <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m2 */ - <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m2 */ - <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = - /* spi0_cs0_m2 */ - <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs1: spi0m2-cs1 { - rockchip,pins = - /* spi0_cs1_m2 */ - <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m3_pins: spi0m3-pins { - rockchip,pins = - /* spi0_clk_m3 */ - <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m3 */ - <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m3 */ - <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs0: spi0m3-cs0 { - rockchip,pins = - /* spi0_cs0_m3 */ - <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs1: spi0m3-cs1 { - rockchip,pins = - /* spi0_cs1_m3 */ - <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clk_m1 */ - <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m1 */ - <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m1 */ - <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0_m1 */ - <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs1: spi1m1-cs1 { - rockchip,pins = - /* spi1_cs1_m1 */ - <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_pins: spi1m2-pins { - rockchip,pins = - /* spi1_clk_m2 */ - <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m2 */ - <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m2 */ - <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs0: spi1m2-cs0 { - rockchip,pins = - /* spi1_cs0_m2 */ - <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs1: spi1m2-cs1 { - rockchip,pins = - /* spi1_cs1_m2 */ - <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clk_m0 */ - <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m0 */ - <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m0 */ - <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0_m0 */ - <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1_m0 */ - <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clk_m1 */ - <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m1 */ - <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m1 */ - <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0_m1 */ - <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1_m1 */ - <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_pins: spi2m2-pins { - rockchip,pins = - /* spi2_clk_m2 */ - <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m2 */ - <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m2 */ - <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs0: spi2m2-cs0 { - rockchip,pins = - /* spi2_cs0_m2 */ - <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs1: spi2m2-cs1 { - rockchip,pins = - /* spi2_cs1_m2 */ - <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clk_m1 */ - <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m1 */ - <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m1 */ - <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0_m1 */ - <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1_m1 */ - <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_pins: spi3m2-pins { - rockchip,pins = - /* spi3_clk_m2 */ - <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m2 */ - <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m2 */ - <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs0: spi3m2-cs0 { - rockchip,pins = - /* spi3_cs0_m2 */ - <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs1: spi3m2-cs1 { - rockchip,pins = - /* spi3_cs1_m2 */ - <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_pins: spi3m3-pins { - rockchip,pins = - /* spi3_clk_m3 */ - <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m3 */ - <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m3 */ - <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs0: spi3m3-cs0 { - rockchip,pins = - /* spi3_cs0_m3 */ - <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs1: spi3m3-cs1 { - rockchip,pins = - /* spi3_cs1_m3 */ - <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi4 { - /omit-if-no-ref/ - spi4m0_pins: spi4m0-pins { - rockchip,pins = - /* spi4_clk_m0 */ - <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m0 */ - <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m0 */ - <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs0: spi4m0-cs0 { - rockchip,pins = - /* spi4_cs0_m0 */ - <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs1: spi4m0-cs1 { - rockchip,pins = - /* spi4_cs1_m0 */ - <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_pins: spi4m1-pins { - rockchip,pins = - /* spi4_clk_m1 */ - <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m1 */ - <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m1 */ - <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs0: spi4m1-cs0 { - rockchip,pins = - /* spi4_cs0_m1 */ - <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs1: spi4m1-cs1 { - rockchip,pins = - /* spi4_cs1_m1 */ - <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_pins: spi4m2-pins { - rockchip,pins = - /* spi4_clk_m2 */ - <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m2 */ - <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m2 */ - <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_cs0: spi4m2-cs0 { - rockchip,pins = - /* spi4_cs0_m2 */ - <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut: tsadc-shut { - rockchip,pins = - /* tsadc_shut */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut_org: tsadc-shut-org { - rockchip,pins = - /* tsadc_shut_org */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0m0_xfer: uart0m0-xfer { - rockchip,pins = - /* uart0_rx_m0 */ - <0 RK_PC4 4 &pcfg_pull_up>, - /* uart0_tx_m0 */ - <0 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m1_xfer: uart0m1-xfer { - rockchip,pins = - /* uart0_rx_m1 */ - <0 RK_PB0 4 &pcfg_pull_up>, - /* uart0_tx_m1 */ - <0 RK_PB1 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m2_xfer: uart0m2-xfer { - rockchip,pins = - /* uart0_rx_m2 */ - <4 RK_PA4 10 &pcfg_pull_up>, - /* uart0_tx_m2 */ - <4 RK_PA3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC6 4 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rx_m1 */ - <1 RK_PB7 10 &pcfg_pull_up>, - /* uart1_tx_m1 */ - <1 RK_PB6 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <1 RK_PD7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <1 RK_PD6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_xfer: uart1m2-xfer { - rockchip,pins = - /* uart1_rx_m2 */ - <0 RK_PD2 10 &pcfg_pull_up>, - /* uart1_tx_m2 */ - <0 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m2_ctsn: uart1m2-ctsn { - rockchip,pins = - /* uart1m2_ctsn */ - <0 RK_PD0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_rtsn: uart1m2-rtsn { - rockchip,pins = - /* uart1m2_rtsn */ - <0 RK_PC7 10 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rx_m0 */ - <0 RK_PB6 10 &pcfg_pull_up>, - /* uart2_tx_m0 */ - <0 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rx_m1 */ - <4 RK_PD1 10 &pcfg_pull_up>, - /* uart2_tx_m1 */ - <4 RK_PD0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m2_xfer: uart2m2-xfer { - rockchip,pins = - /* uart2_rx_m2 */ - <3 RK_PB2 10 &pcfg_pull_up>, - /* uart2_tx_m2 */ - <3 RK_PB1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2_ctsn: uart2-ctsn { - rockchip,pins = - /* uart2_ctsn */ - <3 RK_PB4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart2_rtsn: uart2-rtsn { - rockchip,pins = - /* uart2_rtsn */ - <3 RK_PB3 10 &pcfg_pull_none>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rx_m0 */ - <1 RK_PC0 10 &pcfg_pull_up>, - /* uart3_tx_m0 */ - <1 RK_PC1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rx_m1 */ - <3 RK_PB6 10 &pcfg_pull_up>, - /* uart3_tx_m1 */ - <3 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m2_xfer: uart3m2-xfer { - rockchip,pins = - /* uart3_rx_m2 */ - <4 RK_PA6 10 &pcfg_pull_up>, - /* uart3_tx_m2 */ - <4 RK_PA5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3_ctsn: uart3-ctsn { - rockchip,pins = - /* uart3_ctsn */ - <1 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3_rtsn: uart3-rtsn { - rockchip,pins = - /* uart3_rtsn */ - <1 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rx_m0 */ - <1 RK_PD3 10 &pcfg_pull_up>, - /* uart4_tx_m0 */ - <1 RK_PD2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rx_m1 */ - <3 RK_PD0 10 &pcfg_pull_up>, - /* uart4_tx_m1 */ - <3 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m2_xfer: uart4m2-xfer { - rockchip,pins = - /* uart4_rx_m2 */ - <1 RK_PB2 10 &pcfg_pull_up>, - /* uart4_tx_m2 */ - <1 RK_PB3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4_ctsn: uart4-ctsn { - rockchip,pins = - /* uart4_ctsn */ - <1 RK_PC7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4_rtsn: uart4-rtsn { - rockchip,pins = - /* uart4_rtsn */ - <1 RK_PC5 10 &pcfg_pull_none>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rx_m0 */ - <4 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m0 */ - <4 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <4 RK_PD2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <4 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rx_m1 */ - <3 RK_PC5 10 &pcfg_pull_up>, - /* uart5_tx_m1 */ - <3 RK_PC4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m1_ctsn: uart5m1-ctsn { - rockchip,pins = - /* uart5m1_ctsn */ - <2 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_rtsn: uart5m1-rtsn { - rockchip,pins = - /* uart5m1_rtsn */ - <2 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m2_xfer: uart5m2-xfer { - rockchip,pins = - /* uart5_rx_m2 */ - <2 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m2 */ - <2 RK_PD5 10 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rx_m1 */ - <1 RK_PA0 10 &pcfg_pull_up>, - /* uart6_tx_m1 */ - <1 RK_PA1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m1_ctsn: uart6m1-ctsn { - rockchip,pins = - /* uart6m1_ctsn */ - <1 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_rtsn: uart6m1-rtsn { - rockchip,pins = - /* uart6m1_rtsn */ - <1 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m2_xfer: uart6m2-xfer { - rockchip,pins = - /* uart6_rx_m2 */ - <1 RK_PD1 10 &pcfg_pull_up>, - /* uart6_tx_m2 */ - <1 RK_PD0 10 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rx_m1 */ - <3 RK_PC1 10 &pcfg_pull_up>, - /* uart7_tx_m1 */ - <3 RK_PC0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m1_ctsn: uart7m1-ctsn { - rockchip,pins = - /* uart7m1_ctsn */ - <3 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_rtsn: uart7m1-rtsn { - rockchip,pins = - /* uart7m1_rtsn */ - <3 RK_PC2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rx_m2 */ - <1 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m2 */ - <1 RK_PB5 10 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rx_m0 */ - <4 RK_PB1 10 &pcfg_pull_up>, - /* uart8_tx_m0 */ - <4 RK_PB0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <4 RK_PB3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <4 RK_PB2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rx_m1 */ - <3 RK_PA3 10 &pcfg_pull_up>, - /* uart8_tx_m1 */ - <3 RK_PA2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m1_ctsn: uart8m1-ctsn { - rockchip,pins = - /* uart8m1_ctsn */ - <3 RK_PA5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_rtsn: uart8m1-rtsn { - rockchip,pins = - /* uart8m1_rtsn */ - <3 RK_PA4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8_xfer: uart8-xfer { - rockchip,pins = - /* uart8_rx_ */ - <4 RK_PB1 10 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rx_m1 */ - <4 RK_PB5 10 &pcfg_pull_up>, - /* uart9_tx_m1 */ - <4 RK_PB4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_ctsn: uart9m1-ctsn { - rockchip,pins = - /* uart9m1_ctsn */ - <4 RK_PA1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_rtsn: uart9m1-rtsn { - rockchip,pins = - /* uart9m1_rtsn */ - <4 RK_PA0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rx_m2 */ - <3 RK_PD4 10 &pcfg_pull_up>, - /* uart9_tx_m2 */ - <3 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_ctsn: uart9m2-ctsn { - rockchip,pins = - /* uart9m2_ctsn */ - <3 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_rtsn: uart9m2-rtsn { - rockchip,pins = - /* uart9m2_rtsn */ - <3 RK_PD2 10 &pcfg_pull_none>; - }; - }; - - vop { - /omit-if-no-ref/ - vop_pins: vop-pins { - rockchip,pins = - /* vop_post_empty */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - bt656 { - /omit-if-no-ref/ - bt656_pins: bt656-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpio-func { - /omit-if-no-ref/ - tsadc_gpio_func: tsadc-gpio-func { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 6ac5ac8b48ab..a379269147c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1,2670 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3588"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu_b2>; - }; - core1 { - cpu = <&cpu_b3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_b0: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b0>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b1: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b1>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b2: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b2>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b3: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b3>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l2: l2-cache-l2 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l3: l2-cache-l3 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b0: l2-cache-b0 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b1: l2-cache-b1 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b2: l2-cache-b2 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b3: l2-cache-b3 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - spll: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <702000000>; - clock-output-names = "spll"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; - - xin24m: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - mmu600_pcie: iommu@fc900000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfc900000 0x0 0x200000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - mmu600_php: iommu@fcb00000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfcb00000 0x0 0x200000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; - }; - - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - - vop_grf: syscon@fd5a4000 { - compatible = "rockchip,rk3588-vop-grf", "syscon"; - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; - clocks = <&cru PCLK_VO1GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - - pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - - pipe_phy2_grf: syscon@fd5c4000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - hdptxphy0_grf: syscon@fd5e0000 { - compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; - reg = <0x0 0xfd5e0000 0x0 0x100>; - }; - - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; - }; - - system_sram1: sram@fd600000 { - compatible = "mmio-sram"; - reg = <0x0 0xfd600000 0x0 0x100000>; - ranges = <0x0 0x0 0xfd600000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - cru: clock-controller@fd7c0000 { - compatible = "rockchip,rk3588-cru"; - reg = <0x0 0xfd7c0000 0x0 0x5c000>; - assigned-clocks = - <&cru PLL_PPLL>, <&cru PLL_AUPLL>, - <&cru PLL_NPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CENTER_ROOT>, - <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, - <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, - <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, - <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, - <&cru CLK_GPU>; - assigned-clock-rates = - <1100000000>, <786432000>, - <850000000>, <1188000000>, - <702000000>, - <400000000>, <500000000>, - <800000000>, <100000000>, - <400000000>, <100000000>, - <200000000>, <500000000>, - <375000000>, <150000000>, - <200000000>; - rockchip,grf = <&php_grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@fd880000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfd880000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart0m1_xfer>; - pinctrl-names = "default"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pwm0: pwm@fd8b0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0000 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fd8b0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0010 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fd8b0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0020 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fd8b0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0030 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fd8d8000 { - compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfd8d8000 0x0 0x400>; - - power: power-controller { - compatible = "rockchip,rk3588-power-controller"; - #address-cells = <1>; - #power-domain-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPUTOP { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>, - <&cru HCLK_NPU_CM0_ROOT>; - pm_qos = <&qos_npu0_mwr>, - <&qos_npu0_mro>, - <&qos_mcu_npu>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPU1 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_NPU2 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu2>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { - reg = ; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - pm_qos = <&qos_gpu_m0>, - <&qos_gpu_m1>, - <&qos_gpu_m2>, - <&qos_gpu_m3>; - #power-domain-cells = <0>; - }; - /* These power domains are grouped by VD_VCODEC */ - power-domain@RK3588_PD_VCODEC { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>, - <&cru ACLK_RKVDEC_CCU>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC1>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VENC0 { - reg = ; - clocks = <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>; - pm_qos = <&qos_rkvenc0_m0ro>, - <&qos_rkvenc0_m1ro>, - <&qos_rkvenc0_m2wo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VENC1 { - reg = ; - clocks = <&cru HCLK_RKVENC1>, - <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>, - <&cru ACLK_RKVENC1>; - pm_qos = <&qos_rkvenc1_m0ro>, - <&qos_rkvenc1_m1ro>, - <&qos_rkvenc1_m2wo>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3588_PD_VDPU { - reg = ; - clocks = <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_LOW_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_JPEG_DECODER_ROOT>, - <&cru ACLK_IEP2P0>, - <&cru HCLK_IEP2P0>, - <&cru ACLK_JPEG_ENCODER0>, - <&cru HCLK_JPEG_ENCODER0>, - <&cru ACLK_JPEG_ENCODER1>, - <&cru HCLK_JPEG_ENCODER1>, - <&cru ACLK_JPEG_ENCODER2>, - <&cru HCLK_JPEG_ENCODER2>, - <&cru ACLK_JPEG_ENCODER3>, - <&cru HCLK_JPEG_ENCODER3>, - <&cru ACLK_JPEG_DECODER>, - <&cru HCLK_JPEG_DECODER>, - <&cru ACLK_RGA2>, - <&cru HCLK_RGA2>; - pm_qos = <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc0>, - <&qos_jpeg_enc1>, - <&qos_jpeg_enc2>, - <&qos_jpeg_enc3>, - <&qos_rga2_mro>, - <&qos_rga2_mwo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - - power-domain@RK3588_PD_AV1 { - reg = ; - clocks = <&cru PCLK_AV1>, - <&cru ACLK_AV1>, - <&cru HCLK_VDPU_ROOT>; - pm_qos = <&qos_av1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RGA30 { - reg = ; - clocks = <&cru ACLK_RGA3_0>, - <&cru HCLK_RGA3_0>; - pm_qos = <&qos_rga3_0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VOP { - reg = ; - clocks = <&cru PCLK_VOP_ROOT>, - <&cru HCLK_VOP_ROOT>, - <&cru ACLK_VOP>; - pm_qos = <&qos_vop_m0>, - <&qos_vop_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VO0 { - reg = ; - clocks = <&cru PCLK_VO0_ROOT>, - <&cru PCLK_VO0_S_ROOT>, - <&cru HCLK_VO0_S_ROOT>, - <&cru ACLK_VO0_ROOT>, - <&cru HCLK_HDCP0>, - <&cru ACLK_HDCP0>, - <&cru HCLK_VOP_ROOT>; - pm_qos = <&qos_hdcp0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VO1 { - reg = ; - clocks = <&cru PCLK_VO1_ROOT>, - <&cru PCLK_VO1_S_ROOT>, - <&cru HCLK_VO1_S_ROOT>, - <&cru HCLK_HDCP1>, - <&cru ACLK_HDCP1>, - <&cru ACLK_HDMIRX_ROOT>, - <&cru HCLK_VO1USB_TOP_ROOT>; - pm_qos = <&qos_hdcp1>, - <&qos_hdmirx>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VI { - reg = ; - clocks = <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>, - <&cru HCLK_ISP0>, - <&cru ACLK_ISP0>, - <&cru HCLK_VICAP>, - <&cru ACLK_VICAP>; - pm_qos = <&qos_isp0_mro>, - <&qos_isp0_mwo>, - <&qos_vicap_m0>, - <&qos_vicap_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_ISP1 { - reg = ; - clocks = <&cru HCLK_ISP1>, - <&cru ACLK_ISP1>, - <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_isp1_mwo>, - <&qos_isp1_mro>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_FEC { - reg = ; - clocks = <&cru HCLK_FISHEYE0>, - <&cru ACLK_FISHEYE0>, - <&cru HCLK_FISHEYE1>, - <&cru ACLK_FISHEYE1>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_fisheye0>, - <&qos_fisheye1>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_RGA31 { - reg = ; - clocks = <&cru HCLK_RGA3_1>, - <&cru ACLK_RGA3_1>; - pm_qos = <&qos_rga3_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_USB { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_USB_ROOT>, - <&cru ACLK_USB>, - <&cru HCLK_USB_ROOT>, - <&cru HCLK_HOST0>, - <&cru HCLK_HOST_ARB0>, - <&cru HCLK_HOST1>, - <&cru HCLK_HOST_ARB1>; - pm_qos = <&qos_usb3_0>, - <&qos_usb3_1>, - <&qos_usb2host_0>, - <&qos_usb2host_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_GMAC { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_PCIE { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDIO { - reg = ; - clocks = <&cru HCLK_SDIO>, - <&cru HCLK_NVM_ROOT>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_AUDIO { - reg = ; - clocks = <&cru HCLK_AUDIO_ROOT>, - <&cru PCLK_AUDIO_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDMMC { - reg = ; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - }; - }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; - - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 0>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S4_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s5_8ch: i2s@fddf0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 2>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S5_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s9_8ch: i2s@fddfc000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddfc000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 23>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S9_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; - }; - - qos_gpu_m1: qos@fdf35200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35200 0x0 0x20>; - }; - - qos_gpu_m2: qos@fdf35400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35400 0x0 0x20>; - }; - - qos_gpu_m3: qos@fdf35600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35600 0x0 0x20>; - }; - - qos_rga3_1: qos@fdf36000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf36000 0x0 0x20>; - }; - - qos_sdio: qos@fdf39000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf39000 0x0 0x20>; - }; - - qos_sdmmc: qos@fdf3d800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3d800 0x0 0x20>; - }; - - qos_usb3_1: qos@fdf3e000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e000 0x0 0x20>; - }; - - qos_usb3_0: qos@fdf3e200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e200 0x0 0x20>; - }; - - qos_usb2host_0: qos@fdf3e400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e400 0x0 0x20>; - }; - - qos_usb2host_1: qos@fdf3e600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e600 0x0 0x20>; - }; - - qos_fisheye0: qos@fdf40000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40000 0x0 0x20>; - }; - - qos_fisheye1: qos@fdf40200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40200 0x0 0x20>; - }; - - qos_isp0_mro: qos@fdf40400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40400 0x0 0x20>; - }; - - qos_isp0_mwo: qos@fdf40500 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40500 0x0 0x20>; - }; - - qos_vicap_m0: qos@fdf40600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40600 0x0 0x20>; - }; - - qos_vicap_m1: qos@fdf40800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40800 0x0 0x20>; - }; - - qos_isp1_mwo: qos@fdf41000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41000 0x0 0x20>; - }; - - qos_isp1_mro: qos@fdf41100 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41100 0x0 0x20>; - }; - - qos_rkvenc0_m0ro: qos@fdf60000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60000 0x0 0x20>; - }; - - qos_rkvenc0_m1ro: qos@fdf60200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60200 0x0 0x20>; - }; - - qos_rkvenc0_m2wo: qos@fdf60400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60400 0x0 0x20>; - }; - - qos_rkvenc1_m0ro: qos@fdf61000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61000 0x0 0x20>; - }; - - qos_rkvenc1_m1ro: qos@fdf61200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61200 0x0 0x20>; - }; - - qos_rkvenc1_m2wo: qos@fdf61400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61400 0x0 0x20>; - }; - - qos_rkvdec0: qos@fdf62000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf62000 0x0 0x20>; - }; - - qos_rkvdec1: qos@fdf63000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf63000 0x0 0x20>; - }; - - qos_av1: qos@fdf64000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf64000 0x0 0x20>; - }; - - qos_iep: qos@fdf66000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66000 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fdf66200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66200 0x0 0x20>; - }; - - qos_jpeg_enc0: qos@fdf66400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66400 0x0 0x20>; - }; - - qos_jpeg_enc1: qos@fdf66600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66600 0x0 0x20>; - }; - - qos_jpeg_enc2: qos@fdf66800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66800 0x0 0x20>; - }; - - qos_jpeg_enc3: qos@fdf66a00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66a00 0x0 0x20>; - }; - - qos_rga2_mro: qos@fdf66c00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66c00 0x0 0x20>; - }; - - qos_rga2_mwo: qos@fdf66e00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66e00 0x0 0x20>; - }; - - qos_rga3_0: qos@fdf67000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67000 0x0 0x20>; - }; - - qos_vdpu: qos@fdf67200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67200 0x0 0x20>; - }; - - qos_npu1: qos@fdf70000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf70000 0x0 0x20>; - }; - - qos_npu2: qos@fdf71000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf71000 0x0 0x20>; - }; - - qos_npu0_mwr: qos@fdf72000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72000 0x0 0x20>; - }; - - qos_npu0_mro: qos@fdf72200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72200 0x0 0x20>; - }; - - qos_mcu_npu: qos@fdf72400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72400 0x0 0x20>; - }; - - qos_hdcp0: qos@fdf80000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf80000 0x0 0x20>; - }; - - qos_hdcp1: qos@fdf81000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81000 0x0 0x20>; - }; - - qos_hdmirx: qos@fdf81200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81200 0x0 0x20>; - }; - - qos_vop_m0: qos@fdf82000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82000 0x0 0x20>; - }; - - qos_vop_m1: qos@fdf82200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = , - , - , - ; - rockchip,pmu = <&pmu1grf>; - }; - - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; - clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, - <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, - <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, - <0 0 0 2 &pcie2x1l1_intc 1>, - <0 0 0 3 &pcie2x1l1_intc 2>, - <0 0 0 4 &pcie2x1l1_intc 3>; - linux,pci-domain = <3>; - max-link-speed = <2>; - msi-map = <0x3000 &its0 0x3000 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, - <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, - <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &its0 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, - <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata0: sata@fe210000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe210000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, - <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy0_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sata2: sata@fe230000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe230000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, - <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy2_psu PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power RK3588_PD_SDMMC>; - status = "disabled"; - }; - - sdio: mmc@fe2d0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x00 0xfe2d0000 0x00 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - power-domains = <&power RK3588_PD_SDIO>; - status = "disabled"; - }; - - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; - pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, - <&emmc_cmd>, <&emmc_data_strobe>; - pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdi2 - &i2s0_sdi3 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe480000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe480000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_lrck - &i2s1m0_sclk - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe490000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe490000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 0>, <&dmac1 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe4a0000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe4a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi - &i2s3_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe600000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = ; - interrupt-controller; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; - ranges; - #address-cells = <2>; - #interrupt-cells = <4>; - #size-cells = <2>; - - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_partition1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; - }; - }; - }; - - dmac0: dma-controller@fea10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fea30000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea30000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fea90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfea90000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c1m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@feaa0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeaa0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@feab0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeab0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@feac0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeac0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fead0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfead0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@feae0000 { - compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfeae0000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = ; - }; - - spi0: spi@feb00000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@feb10000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb10000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@feb20000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@feb30000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb30000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 17>, <&dmac1 18>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@feb40000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb40000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@feb50000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb50000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@feb60000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb60000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@feb70000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb70000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 9>, <&dmac1 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@feb80000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb80000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 11>, <&dmac1 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@feb90000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb90000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 13>, <&dmac1 14>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@feba0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeba0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 7>, <&dmac2 8>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@febb0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebb0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 9>, <&dmac2 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@febc0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebc0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 11>, <&dmac2 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@febd0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@febd0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@febd0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@febd0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@febe0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@febe0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@febe0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@febe0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@febf0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@febf0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@febf0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@febf0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; - interrupts = ; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC>; - assigned-clock-rates = <2000000>; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; - reset-names = "tsadc-apb", "tsadc"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shut>; - pinctrl-names = "gpio", "otpout"; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: adc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c6: i2c@fec80000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec80000 0x0 0x1000>; - clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c6m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@fec90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec90000 0x0 0x1000>; - clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c7m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@feca0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeca0000 0x0 0x1000>; - clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c8m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@fecb0000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfecb0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac2 13>, <&dmac2 14>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - otp: efuse@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, - <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; - clock-names = "otp", "apb_pclk", "phy", "arb"; - resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, - <&cru SRST_OTPC_ARB>; - reset-names = "otp", "apb", "arb"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - - otp_id: id@7 { - reg = <0x07 0x10>; - }; - - cpub0_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - - cpub1_leakage: cpu-leakage@18 { - reg = <0x18 0x1>; - }; - - cpul_leakage: cpu-leakage@19 { - reg = <0x19 0x1>; - }; - - log_leakage: log-leakage@1a { - reg = <0x1a 0x1>; - }; - - gpu_leakage: gpu-leakage@1b { - reg = <0x1b 0x1>; - }; - - otp_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - - npu_leakage: npu-leakage@28 { - reg = <0x28 0x1>; - }; - - codec_leakage: codec-leakage@29 { - reg = <0x29 0x1>; - }; - }; - - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - hdptxphy_hdmi0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, - <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, - <&cru SRST_HDPTX0_LCPLL>; - reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", - "lcpll"; - rockchip,grf = <&hdptxphy0_grf>; - status = "disabled"; - }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; - - combphy2_psu: phy@fee20000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee20000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy2_grf>; - status = "disabled"; - }; - - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3588-pinctrl"; - ranges; - rockchip,grf = <&ioc>; - #address-cells = <2>; - #size-cells = <2>; - - gpio0: gpio@fd8a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfd8a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fec20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec20000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fec30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec30000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fec40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec40000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fec50000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec50000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3588s-pinctrl.dtsi" +#include "rk3588-base.dtsi" -- cgit v1.2.3-58-ga151 From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:51 +0400 Subject: arm64: dts: rockchip: add thermal zones information on RK3588 This includes the necessary device tree data to allow thermal monitoring on RK3588(s) using the on-chip TSADC device, along with trip points for automatic thermal management. Each of the CPU clusters (one for the little cores and two for the big cores) get a passive cooling trip point at 85C, which will trigger DVFS throttling of the respective cluster upon reaching a high temperature condition. All zones also have a critical trip point at 115C, which will trigger a reset. Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 629049f3dc16..78bc9dc97044 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3588"; @@ -2368,6 +2369,158 @@ status = "disabled"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore0_alert: bigcore0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore0_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + bigcore2_alert: bigcore2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore2_alert>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + tsadc: tsadc@fec00000 { compatible = "rockchip,rk3588-tsadc"; reg = <0x0 0xfec00000 0x0 0x400>; -- cgit v1.2.3-58-ga151 From 2f8064b9c4a012b4d4e8383818f13b682b6c156a Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:52 +0400 Subject: arm64: dts: rockchip: enable thermal management on all RK3588 boards This enables the on-chip thermal monitoring sensor (TSADC) on all RK3588(s) boards that don't have it enabled yet. It provides temperature monitoring for the SoC and emergency thermal shutdowns, and is thus important to have in place before CPU DVFS is enabled, as high CPU operating performance points can overheat the chip quickly in the absence of thermal management. Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-2-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ 8 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 98c622b27647..c667704ba985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -673,6 +673,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 709d348cf06b..03fd193be253 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -466,3 +466,7 @@ }; }; }; + +&tsadc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 7be2190244ba..7c3696a3ad3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -1131,6 +1131,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 009566d881f3..230e630820b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -376,6 +376,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 4e2bf4eaef2b..afcc38a5bed8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -749,6 +749,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 9090c5c99f2a..d0021524e7f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -648,6 +648,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6b9206ce4a03..77bcf0f6b028 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -601,6 +601,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 8e2a07612d17..c671a61d3aef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -697,6 +697,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; -- cgit v1.2.3-58-ga151 From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:53 +0400 Subject: arm64: dts: rockchip: add passive GPU cooling on RK3588 As the GPU support on RK3588 has been merged upstream, along with OPP values, add a corresponding cooling map for passive cooling using the GPU. Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 78bc9dc97044..6cc1ca46ac11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2493,17 +2493,31 @@ }; gpu_thermal: gpu-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsadc 5>; trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { temperature = <115000>; hysteresis = <0>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; npu_thermal: npu-thermal { -- cgit v1.2.3-58-ga151 From 4a152231b050590af771fa3cc8462ed08b691a24 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:54 +0400 Subject: arm64: dts: rockchip: enable automatic fan control on Rock 5B This links the PWM fan on Radxa Rock 5B as an active cooling device managed automatically by the thermal subsystem, with a target SoC temperature of 65C and a minimum-spin interval from 55C to 65C to ensure airflow when the system gets warm Helped-by: Dragan Simic Reviewed-by: Dragan Simic Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-4-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 32 ++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index afcc38a5bed8..2e47f8091cda 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ fan: pwm-fan { compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; + cooling-levels = <0 120 150 180 210 240 255>; fan-supply = <&vcc5v0_sys>; pwms = <&pwm1 0 50000 0>; #cooling-cells = <2>; @@ -286,6 +286,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>; -- cgit v1.2.3-58-ga151 From 9204a7ecca96403ee3d61c14cb9eb87ec89b0fcd Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sun, 23 Jun 2024 11:33:27 +0900 Subject: arm64: dts: rockchip: add SFC support for Radxa ROCK 5B This commit adds support for SPI NOR flash on Radxa ROCK 5B. SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20240623023329.1044-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 2e47f8091cda..d0ba3bf16fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -448,6 +448,20 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; -- cgit v1.2.3-58-ga151 From 00224650dd45e166ea6eb1593f5f064583963ccf Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sun, 23 Jun 2024 11:33:28 +0900 Subject: arm64: dts: rockchip: add (but disabled) SFC node for Radxa ROCK 5A This commit adds SFC node for Radxa ROCK 5A. since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot be enabled both nodes at the same time. so status = "okay" is omitted here. you may be able to enable sfc (and disable sdhci) by fdt overlay. SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index c671a61d3aef..4cc1790ebd08 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -376,6 +376,19 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; -- cgit v1.2.3-58-ga151 From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sun, 23 Jun 2024 11:33:29 +0900 Subject: arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK 3C SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index b242409d378c..f2cc086e5001 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -633,7 +633,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; - spi-max-frequency = <120000000>; + spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; }; -- cgit v1.2.3-58-ga151 From c7f024956d9f35d8b305fe90fe33d7f15055ef25 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 23 Jun 2024 21:46:14 +0100 Subject: arm64: dts: rockchip: Enable SPI flash on PinePhone Pro The PinePhone Pro as SPI flash on board so enable the SPI interface and the flash. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20240623204616.1344806-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index e5709c7ee06a..f474c2268753 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -565,6 +565,16 @@ status = "okay"; }; +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; -- cgit v1.2.3-58-ga151 From ee9b6b6414790223e8315ef0e25df69b3b5e6e50 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 23 Jun 2024 17:53:20 +0100 Subject: arm64: dts: rockchip: Add Pinephone Pro support for GPIO LEDs The PinePhone Pro has a cluster of 3 single RGB GPIO LEDs. Add the GPIO entries for the 3 red/green/blue LEDs and an entry for the multi-color group to allow them to be used as a combined RGB LED. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20240623165326.1273944-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinephone-pro.dts | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index f474c2268753..f1209dc3f761 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -12,6 +12,7 @@ /dts-v1/; #include #include +#include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -69,6 +70,34 @@ }; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&red_led_pin &green_led_pin &blue_led_pin>; + + led_red: led-0 { + color = ; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led_green: led-1 { + color = ; + gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led-2 { + color = ; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_INDICATOR; + leds = <&led_red>, <&led_green>, <&led_blue>; + }; + vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -481,6 +510,20 @@ }; }; + leds { + red_led_pin: red-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + green_led_pin: green-led-pin { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led_pin: blue-led-pin { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -- cgit v1.2.3-58-ga151 From c1d9ced35621bdc894321ad284a29922dd3e7251 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 23 Jun 2024 17:53:21 +0100 Subject: arm64: dts: rockchip: Enable PinePhone Pro IMU sensor Enable the IMU sensor on the PinePhone Pro including the i2c4 bus that it's attached to. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20240623165326.1273944-2-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index f1209dc3f761..6ce115db155a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -436,6 +436,21 @@ }; }; +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + /* Accelerometer/gyroscope */ + mpu6500@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = ; + vddio-supply = <&vcc_1v8>; + }; +}; + &cluster0_opp { opp04 { status = "disabled"; -- cgit v1.2.3-58-ga151 From 3f9cfd4f5e453aa33ca4dc40959a1cc524501160 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 23 Jun 2024 17:53:22 +0100 Subject: arm64: dts: rockchip: Enable PinePhone Pro vibrator The PinePhone Pro has a vibrator attached via GPIO so lets enable it. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20240623165326.1273944-3-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 6ce115db155a..ef754ea30a94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -181,6 +181,12 @@ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + vcc-supply = <&vcc3v3_sys>; + }; }; &cpu_alert0 { -- cgit v1.2.3-58-ga151 From 79cba74263d96ab1848eb04862f72f8988eb0486 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 23 Jun 2024 11:01:13 +0200 Subject: dt-bindings: vendor-prefixes: Add Neardi Technology Add vendor prefix for Shanghai Neardi Technology Co., Ltd. (http://neardi.com/) Signed-off-by: Alex Bee Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240623090116.670607-2-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..6e879abec71d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -995,6 +995,8 @@ patternProperties: description: MYIR Tech Limited "^national,.*": description: National Semiconductor + "^neardi,.*": + description: Shanghai Neardi Technology Co., Ltd. "^nec,.*": description: NEC LCD Technologies, Ltd. "^neonode,.*": -- cgit v1.2.3-58-ga151 From a30a6386ecc1f6ff71d4f7606bed25b7075476ab Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 23 Jun 2024 11:01:14 +0200 Subject: dt-bindings: arm: rockchip: Add Neardi LBA3368 Add Neardi LBA3368, a RK3368 based industrial board. Signed-off-by: Alex Bee Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240623090116.670607-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index eca0a42eb384..d2e887415d5d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -634,6 +634,11 @@ properties: - const: mqmaker,miqi - const: rockchip,rk3288 + - description: Neardi LBA3368 + items: + - const: neardi,lba3368 + - const: rockchip,rk3368 + - description: Netxeon R89 board items: - const: netxeon,r89 -- cgit v1.2.3-58-ga151 From 7b4a8097e58b608638d416bd57469f8a9ab70e7b Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 23 Jun 2024 11:01:16 +0200 Subject: arm64: dts: rockchip: Add Neardi LBA3368 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LBA3368 is a RK3368 based industrial board from Neardi. Specs: - 1 GB DDR3 DRAM - 8/16 GB eMMC - µSD slot - 100 mbit ethernet (optional 12V PoE) - Ampak AP6255 Wifi/BT combo - ADC button - 4 x USB 2.0 via onboard GL852G HUB connected to SoC's ehci host - 2 exposed as USB-A - 2 via 2-mm-4-pin connectors - micro USB OTG connector - 2 x UART TTL (2-mm-4-pin connectors) - CSI connector - DSI connector - eDP connector - HDMI 2.0a output (type A) - touchpad connector (I2C, 3.3V) - ALC5640 audio codec - combined headphone/microphone jack - speaker connector pads Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20240623090116.670607-5-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts | 659 ++++++++++++++++++++++++ 2 files changed, 660 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 909217846a07..5775cdd4d056 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lba3368.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts new file mode 100644 index 000000000000..e0cc4da7f392 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3368.dtsi" + +/ { + model = "Neardi LBA3368"; + compatible = "neardi,lba3368", "rockchip,rk3368"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio0; + rtc0 = &hym8563; + rtc1 = &rk808; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + adc-key { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s_8ch_p0>; + hp-det-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + label = "alc5640"; + routing = "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speakers"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + hub_avdd: hub-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "hub_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + power-led { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = ; + default-state = "on"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + enable-active-high; + regulator-always-on; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + regulator-always-on; + }; + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + enable-active-high; + regulator-always-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + vdd10_usb: vdd10-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd10_usb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + vin-supply = <&vdd_10>; + regulator-always-on; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + cap-mmc-highspeed; + non-removable; + no-sd; + no-sdio; + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_lan>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + reset-assert-us = <10000>; + reset-deassert-us = <1000000>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + }; + }; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_18>; + gpio1830-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vdd1v8_wl>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupts-extended = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "xin32k_wifi_bt"; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &pmic_sleep>; + system-power-controller; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: DCDC_REG2 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <1000000>; + regulator-on-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca3v0_codec: LDO_REG2 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <1000000>; + regulator-on-in-suspend; + }; + }; + + vdd1v8_wl: LDO_REG4 { + regulator-name = "vdd1v8_wl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-suspend-microvolt = <1800000>; + regulator-on-in-suspend; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_tp: SWITCH_REG1 { + regulator-name = "vcc_tp"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG2 { + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,dmic1-data-pin = ; + realtek,dmic2-data-pin = ; + realtek,in1-differential; + #sound-dai-cells = <0>; + + port { + rt5640_p0_0: endpoint { + remote-endpoint = <&i2s_8ch_p0_0>; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&i2s_8ch { + status = "okay"; + + i2s_8ch_p0: port { + i2s_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&rt5640_p0_0>; + }; + }; +}; + +&pinctrl { + bluetooth { + bt_host_wake: bt-host-wake { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on: bt-reg-on { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + power_led: power-led { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + phy { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det: hp-det { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vdd1v8_wl>; + assigned-clocks = <&cru SCLK_SDIO0>; + assigned-clock-parents = <&cru PLL_CPLL>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + cap-sd-highspeed; + cap-sdio-irq; + no-sd; + no-mmc; + non-removable; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupts-extended = <&gpio3 RK_PA6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&sdmmc { + bus-width = <4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_cd>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + interrupts-extended = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + max-speed = <15000000>; + vbat-supply = <&vcc_io>; + vddio-supply = <&vdd1v8_wl>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_reg_on>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + vdd-supply = <&hub_avdd>; + }; +}; + +&usb_otg { + vbus-supply = <&vcc_otg>; + vusb_a-supply = <&vcc_io>; + vusb_d-supply = <&vdd10_usb>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 21 Jun 2024 07:44:35 +0900 Subject: arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W align with other Radxa products. - mmc0 is eMMC - mmc1 is microSD for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0 is microSD as exception. Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E") Signed-off-by: FUKAUMI Naoki Changes in v3: - fix syntax error in rk3566-radxa-zero-3e.dts Changes in v2: - microSD is mmc0 instead of mmc1 for ZERO 3E Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ---- arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 + arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi index 623d5939d194..081be841b286 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi @@ -6,10 +6,6 @@ #include "rk3566.dtsi" / { - aliases { - mmc0 = &sdmmc0; - }; - chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts index e166d66990b9..4a830eb09f0b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts @@ -10,6 +10,7 @@ aliases { ethernet0 = &gmac1; + mmc0 = &sdmmc0; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts index 9bf4f464915f..f92475c59deb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts @@ -9,7 +9,8 @@ compatible = "radxa,zero-3w", "rockchip,rk3566"; aliases { - mmc1 = &sdhci; + mmc0 = &sdhci; + mmc1 = &sdmmc0; mmc2 = &sdmmc1; }; -- cgit v1.2.3-58-ga151 From 0ba0560982bc8d0c3fb3ca209fd0ed29f81402ac Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:55 +0400 Subject: arm64: dts: rockchip: Add CPU/memory regulator coupling for 2 RK3588 boards RK3588 chips allow for their CPU cores to be powered by a different supply vs. their corresponding memory interfaces, and two of the boards currently upstream do that (EVB1 and QuartzPro64). The voltage of the memory interface though has to match that of the CPU cores that use it, which downstream kernels achieve by the means of a custom cpufreq driver which adjusts both at the same time. It seems that regulator coupling is a more appropriate generic interface for it, so this patch introduces coupling to affected device trees to ensure that memory interface voltage is also updated whenever cpufreq switches between CPU OPPs. Note that other boards, such as Radxa Rock 5B, define both the CPU and memory interface regulators as aliases to the same DT node, so this doesn't apply there. Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-5-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 7c3696a3ad3a..00f660d50127 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -878,6 +878,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -890,6 +892,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -902,6 +906,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -926,6 +932,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -939,6 +947,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -963,6 +973,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index b4f22d95ac0e..baeb08d665c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -832,6 +832,8 @@ regulator-name = "vdd_cpu_big1_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -845,6 +847,8 @@ regulator-name = "vdd_cpu_big0_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -858,6 +862,8 @@ regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -884,6 +890,8 @@ regulator-name = "vdd_cpu_big1_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -898,6 +906,8 @@ regulator-name = "vdd_cpu_big0_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -924,6 +934,8 @@ regulator-name = "vdd_cpu_lit_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; -- cgit v1.2.3-58-ga151 From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:56 +0400 Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq. OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], stripping them down to the minimum frequency and voltage combinations as expected by the generic upstream cpufreq-dt driver, and also dropping those OPPs that don't differ in voltage but only in frequency (keeping the top frequency OPP in each case). Note that this patch ignores voltage scaling for the CPU memory interface which the downstream kernel does through a custom cpufreq driver, and which is why the downstream version has two sets of voltage values for each OPP (the second one being meant for the memory interface supply regulator). This is done instead via regulator coupling between CPU and memory interface supplies on affected boards. This has been tested on Rock 5B with u-boot 2023.11 compiled from Collabora's integration tree [2] with binary bl31 and appears to be stable both under active cooling and passive cooling (with throttling) [1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi [2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 + 3 files changed, 151 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi new file mode 100644 index 000000000000..35bbc3c2134f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 0bbeee399a63..7462cc1e1007 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -5,3 +5,4 @@ */ #include "rk3588-extra.dtsi" +#include "rk3588-opp.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index a379269147c4..c7fecf8fe7ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -5,3 +5,4 @@ */ #include "rk3588-base.dtsi" +#include "rk3588-opp.dtsi" -- cgit v1.2.3-58-ga151 From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:57 +0400 Subject: arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j RK3588j is the 'industrial' variant of RK3588, and it uses a different set of OPPs both in terms of allowed frequencies and in terms of applicable voltages at each frequency setpoint. Add the OPPs that apply to RK3588j (and apparently RK3588m too) to enable dynamic CPU frequency scaling. OPP values are derived from Rockchip downstream sources [1] by taking only those OPPs which have the highest frequency for a given voltage level and dropping the rest (if they are included, the kernel complains at boot time about them being inefficient) [1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 0bbeee399a63..b7e69553857b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -5,3 +5,111 @@ */ #include "rk3588-extra.dtsi" + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>; + clock-latency-ns = <40000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; +}; -- cgit v1.2.3-58-ga151 From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 17 Jun 2024 22:28:58 +0400 Subject: arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j RK3588j uses a different set of OPPs for its GPU, both in terms of allowed frequencies and in terms of voltages. Move the GPU OPPs table into per-variant .dtsi files to accommodate for this difference. The table for RK3588j is adapted from Rockchip downstream sources [1], while RK3588 one is moved verbatim into the per-variant .dtsi file. The values provided for RK3588 in the downstream sources match those in the original commit. [1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node") Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 ------------------------- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++++++++ 3 files changed, 74 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 6cc1ca46ac11..b6e4df180f0b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -451,46 +451,8 @@ , ; interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; power-domains = <&power RK3588_PD_GPU>; status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; }; usb_host0_xhci: usb@fc000000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi index 35bbc3c2134f..0f1a77697351 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi @@ -114,6 +114,43 @@ clock-latency-ns = <40000>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; }; &cpu_b0 { @@ -147,3 +184,7 @@ &cpu_l3 { operating-points-v2 = <&cluster0_opp_table>; }; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index b7e69553857b..bce72bac4503 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -80,6 +80,35 @@ clock-latency-ns = <40000>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <787500 787500 850000>; + }; + }; }; &cpu_b0 { @@ -113,3 +142,7 @@ &cpu_l3 { operating-points-v2 = <&cluster0_opp_table>; }; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; -- cgit v1.2.3-58-ga151 From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Wed, 19 Jun 2024 21:32:49 -0400 Subject: arm64: dts: rockchip: add gpio-line-names to radxa-zero-3 Add names to the pins of the general-purpose expansion header as given in the Radxa documentation[1] following the conventions in the kernel[2] to make it easier for users to correlate pins with functions when using utilities such as 'gpioinfo'. [1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface [2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt Signed-off-by: Trevor Woerner Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi index 081be841b286..9cc7aa3298d0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi @@ -105,6 +105,78 @@ cpu-supply = <&vdd_cpu>; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", + "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", + "", "pin-37 [GPIO1_A4]", "", + "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", + "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", + "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", + /* GPIO3_B0 - B7 */ + "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", + "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", + "", "", + /* GPIO3_C0 - C7 */ + "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", + "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", + "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO4_B0 - B7 */ + "", "", "pin-27 [GPIO4_B2]", + "pin-28 [GPIO4_B3]", "", "", "", "", + /* GPIO4_C0 - C7 */ + "", "", "pin-23 [GPIO4_C2]", + "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", + "pin-24 [GPIO4_C6]", "", + /* GPIO4_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &gpu { mali-supply = <&vdd_gpu_npu>; status = "okay"; -- cgit v1.2.3-58-ga151 From 0f2ddb128fa20f8441d903285632f2c69e90fae1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Jun 2024 17:03:52 +0000 Subject: arm64: dts: rockchip: Increase VOP clk rate on RK3328 The VOP on RK3328 needs to run at a higher rate in order to produce a proper 3840x2160 signal. Change to use 300MHz for VIO clk and 400MHz for VOP clk, same rates used by vendor 4.4 kernel. Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240615170417.3134517-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 07dcc949b899..b01efd6d042c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -850,8 +850,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, + <300000000>, <100000000>, + <400000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>, -- cgit v1.2.3-58-ga151 From b0aba467c329a89e8b325eda0cf60776958353fe Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 25 Jun 2024 13:18:43 +0200 Subject: arm64: dts: amlogic: sm1: fix spdif compatibles The spdif input and output of g12 and sm1 are compatible but sm1 should use the related compatible since it exists. Fixes: 86f2159468d5 ("arm64: dts: meson-sm1: add spdifin and pdifout nodes") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20240625111845.928192-1-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index d13cf5b4aac7..75c8aa815eff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -335,7 +335,7 @@ }; spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", + compatible = "amlogic,sm1-spdifin", "amlogic,axg-spdifin"; reg = <0x0 0x400 0x0 0x30>; #sound-dai-cells = <0>; @@ -349,7 +349,7 @@ }; spdifout_a: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", + compatible = "amlogic,sm1-spdifout", "amlogic,axg-spdifout"; reg = <0x0 0x480 0x0 0x50>; #sound-dai-cells = <0>; -- cgit v1.2.3-58-ga151 From 84f6ab5fedf735a447080e2fd286eff9859cd199 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 25 Jun 2024 13:54:41 +0200 Subject: arm64: dts: amlogic: g12: bump spdif output drive strength Spdif output currently uses a 0.5mA drive strength by default. While the result depends on how the spdif output is hooked to rest of the system, this is a bit weak and signal quality may be poor. This was reported on the vim3l for example. Increase the drive strength to 3mA, as used for TDM, to be on the safe side. Fixes: 649675db939d ("arm64: dts: meson: g12a: add spdifouts") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20240625115443.934763-1-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 138fb18c6480..4057ee808a58 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -987,7 +987,7 @@ mux { groups = "spdif_out_h"; function = "spdif_out"; - drive-strength-microamp = <500>; + drive-strength-microamp = <3000>; bias-disable; }; }; @@ -996,7 +996,7 @@ mux { groups = "spdif_out_a11"; function = "spdif_out"; - drive-strength-microamp = <500>; + drive-strength-microamp = <3000>; bias-disable; }; }; @@ -1005,7 +1005,7 @@ mux { groups = "spdif_out_a13"; function = "spdif_out"; - drive-strength-microamp = <500>; + drive-strength-microamp = <3000>; bias-disable; }; }; @@ -1826,7 +1826,7 @@ mux { groups = "spdif_ao_out"; function = "spdif_ao_out"; - drive-strength-microamp = <500>; + drive-strength-microamp = <3000>; bias-disable; }; }; -- cgit v1.2.3-58-ga151 From a8cce1ad72caa8ed305b40dec7c075bbebd1c2f3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 24 Jun 2024 17:33:41 +0100 Subject: arm64: dts: qcom: x1e80100-qcp: add audio support Add audio support to QCP platform which includes 2 x Speakers Headset Mic and Headset support. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20240624-qcp-audio-v1-1-323a6b5e1fe5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 155 ++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index b045b7bac9e0..4edec3212dde 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -19,6 +19,32 @@ serial0 = &uart21; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -127,6 +153,66 @@ }; }; + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-QCP"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -520,6 +606,16 @@ }; }; +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -638,6 +734,57 @@ vdd3-supply = <&vreg_l8b_3p0>; }; +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + #sound-dai-cells = <0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + #sound-dai-cells = <0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -679,6 +826,14 @@ bias-pull-up; }; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart21 { -- cgit v1.2.3-58-ga151 From b7a28d8a7b80dd5630a72d8d8cb9f2d1bde6a1ad Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 25 Jun 2024 23:16:18 +0300 Subject: arm64: dts: qcom: pm8916: add temp-alarm thermal zone Define the themal zones using the temperature values in stage1 for this platform so that the spmi-temp-alarm driver becomes active. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20240625-pm8916-tz-v1-1-a4c1f61e92dd@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 4b2e8fb47d2d..2def48f2d101 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -4,8 +4,37 @@ #include #include -&spmi_bus { +/ { + thermal-zones { + pm8150-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8916_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; +&spmi_bus { pm8916_0: pmic@0 { compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; -- cgit v1.2.3-58-ga151 From 213e1b58475096e234abf6772183d23513782b5f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:32 +0530 Subject: dt-bindings: clock: qcom: Update SM8450 videocc header file name Correct the videocc header file name in SM8450 videocc bindings. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240602114439.1611-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d3..b135aa2e9f06 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also: include/dt-bindings/clock/qcom,sm8450-videocc.h properties: compatible: -- cgit v1.2.3-58-ga151 From a6a61b9701d1add3bb6d86d8e259d833ea91a1a6 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:33 +0530 Subject: dt-bindings: clock: qcom: Add SM8650 video clock controller SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-videocc.yaml | 6 +++++- include/dt-bindings/clock/qcom,sm8650-videocc.h | 23 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index b135aa2e9f06..8ce5972a65d5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das + - Jagadeesh Kona description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also: include/dt-bindings/clock/qcom,sm8450-videocc.h + See also: + include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h new file mode 100644 index 000000000000..4e3c2d87280f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H + +#include "qcom,sm8450-videocc.h" + +/* SM8650 introduces below new clocks and resets compared to SM8450 */ + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 + +/* VIDEO_CC resets */ +#define VIDEO_CC_XO_CLK_ARES 7 + +#endif -- cgit v1.2.3-58-ga151 From 6e18795a6acfd04cec3af23680e9051237d4fa94 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:34 +0530 Subject: clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240602114439.1611-4-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8550.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..25133cf5a2b8 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = { -- cgit v1.2.3-58-ga151 From da1f361c887c17e34a8c440690a5b3f347802ff7 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:35 +0530 Subject: clk: qcom: videocc-sm8550: Add SM8650 video clock controller Add support to the SM8650 video clock controller by extending the SM8550 video clock controller, which is mostly identical but SM8650 has few additional clocks and minor differences. Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240602114439.1611-5-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8550.c | 153 +++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index 25133cf5a2b8..c601c35e6724 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2300000000, 0 }, }; -static const struct alpha_pll_config video_cc_pll0_config = { +static struct alpha_pll_config video_cc_pll0_config = { .l = 0x25, .alpha = 0x8000, .config_ctl_val = 0x20485699, @@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = { }, }; -static const struct alpha_pll_config video_cc_pll1_config = { +static struct alpha_pll_config video_cc_pll1_config = { .l = 0x36, .alpha = 0xb000, .config_ctl_val = 0x20485699, @@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = { { .hw = &video_cc_pll1.clkr.hw }, }; +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, +}; + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), @@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = { + F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0x8000, .mnd_width = 0, @@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0x8018, .mnd_width = 0, @@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = { }, }; +static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0x810c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + static struct clk_regmap_div video_cc_mvs0_div_clk_src = { .reg = 0x80c4, .shift = 0, @@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = { }, }; +static struct clk_branch video_cc_mvs0_shift_clk = { + .halt_reg = 0x8128, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8128, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8128, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs0c_clk = { .halt_reg = 0x8064, .halt_check = BRANCH_HALT, @@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = { }, }; +static struct clk_branch video_cc_mvs0c_shift_clk = { + .halt_reg = 0x812c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x812c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x812c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1_clk = { .halt_reg = 0x80e0, .halt_check = BRANCH_HALT_SKIP, @@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = { }, }; +static struct clk_branch video_cc_mvs1_shift_clk = { + .halt_reg = 0x8130, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8130, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1c_clk = { .halt_reg = 0x8090, .halt_check = BRANCH_HALT, @@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = { }, }; +static struct clk_branch video_cc_mvs1c_shift_clk = { + .halt_reg = 0x8134, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8134, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc video_cc_mvs0c_gdsc = { .gdscr = 0x804c, .en_rest_wait_val = 0x2, @@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = { [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, + [VIDEO_CC_XO_CLK_SRC] = NULL, }; static struct gdsc *video_cc_sm8550_gdscs[] = { @@ -403,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = { static const struct of_device_id video_cc_sm8550_match_table[] = { { .compatible = "qcom,sm8550-videocc" }, + { .compatible = "qcom,sm8650-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); @@ -411,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; + u32 sleep_clk_offset = 0x8140; ret = devm_pm_runtime_enable(&pdev->dev); if (ret) @@ -426,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) return PTR_ERR(regmap); } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { + sleep_clk_offset = 0x8150; + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.alpha = 0xa000; + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.alpha = 0xc000; + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650; + video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; + } + clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); -- cgit v1.2.3-58-ga151 From 2bce2ce7ab20f85a33c3e45cb57fe8e400d4f2b0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:36 +0530 Subject: dt-bindings: clock: qcom: Update the order of SC8280XP camcc header Update the order of SC8280XP camcc header file in SM8450 camcc bindings. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20240602114439.1611-6-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index fa0e5b6b02b8..645080b848f0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -13,10 +13,10 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: + See also: + include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h - include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: -- cgit v1.2.3-58-ga151 From 1ae3f0578e0e623e774db45870c0e34c47d8dd15 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:37 +0530 Subject: dt-bindings: clock: qcom: Add SM8650 camera clock controller Add device tree bindings for the camera clock controller on Qualcomm SM8650 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski Acked-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-camcc.yaml | 3 + include/dt-bindings/clock/qcom,sm8650-camcc.h | 195 +++++++++++++++++++++ 2 files changed, 198 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8650-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 645080b848f0..f58edfc10f4c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450 maintainers: - Vladimir Zapolskiy + - Jagadeesh Kona description: | Qualcomm camera clock control module provides the clocks, resets and power @@ -17,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h + include/dt-bindings/clock/qcom,sm8650-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -28,6 +30,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,sm8650-camcc - qcom,x1e80100-camcc clocks: diff --git a/include/dt-bindings/clock/qcom,sm8650-camcc.h b/include/dt-bindings/clock/qcom,sm8650-camcc.h new file mode 100644 index 000000000000..df73bf35f4bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_BPS_SHIFT_CLK 4 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK 6 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7 +#define CAM_CC_CAMNOC_DCD_XO_CLK 8 +#define CAM_CC_CAMNOC_XO_CLK 9 +#define CAM_CC_CCI_0_CLK 10 +#define CAM_CC_CCI_0_CLK_SRC 11 +#define CAM_CC_CCI_1_CLK 12 +#define CAM_CC_CCI_1_CLK_SRC 13 +#define CAM_CC_CCI_2_CLK 14 +#define CAM_CC_CCI_2_CLK_SRC 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPAS_AHB_CLK 17 +#define CAM_CC_CPAS_BPS_CLK 18 +#define CAM_CC_CPAS_CRE_CLK 19 +#define CAM_CC_CPAS_FAST_AHB_CLK 20 +#define CAM_CC_CPAS_IFE_0_CLK 21 +#define CAM_CC_CPAS_IFE_1_CLK 22 +#define CAM_CC_CPAS_IFE_2_CLK 23 +#define CAM_CC_CPAS_IFE_LITE_CLK 24 +#define CAM_CC_CPAS_IPE_NPS_CLK 25 +#define CAM_CC_CPAS_SBI_CLK 26 +#define CAM_CC_CPAS_SFE_0_CLK 27 +#define CAM_CC_CPAS_SFE_1_CLK 28 +#define CAM_CC_CPAS_SFE_2_CLK 29 +#define CAM_CC_CPHY_RX_CLK_SRC 30 +#define CAM_CC_CRE_AHB_CLK 31 +#define CAM_CC_CRE_CLK 32 +#define CAM_CC_CRE_CLK_SRC 33 +#define CAM_CC_CSI0PHYTIMER_CLK 34 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI1PHYTIMER_CLK 36 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI2PHYTIMER_CLK 38 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI3PHYTIMER_CLK 40 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI4PHYTIMER_CLK 42 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSI5PHYTIMER_CLK 44 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45 +#define CAM_CC_CSI6PHYTIMER_CLK 46 +#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47 +#define CAM_CC_CSI7PHYTIMER_CLK 48 +#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49 +#define CAM_CC_CSID_CLK 50 +#define CAM_CC_CSID_CLK_SRC 51 +#define CAM_CC_CSID_CSIPHY_RX_CLK 52 +#define CAM_CC_CSIPHY0_CLK 53 +#define CAM_CC_CSIPHY1_CLK 54 +#define CAM_CC_CSIPHY2_CLK 55 +#define CAM_CC_CSIPHY3_CLK 56 +#define CAM_CC_CSIPHY4_CLK 57 +#define CAM_CC_CSIPHY5_CLK 58 +#define CAM_CC_CSIPHY6_CLK 59 +#define CAM_CC_CSIPHY7_CLK 60 +#define CAM_CC_DRV_AHB_CLK 61 +#define CAM_CC_DRV_XO_CLK 62 +#define CAM_CC_FAST_AHB_CLK_SRC 63 +#define CAM_CC_GDSC_CLK 64 +#define CAM_CC_ICP_AHB_CLK 65 +#define CAM_CC_ICP_CLK 66 +#define CAM_CC_ICP_CLK_SRC 67 +#define CAM_CC_IFE_0_CLK 68 +#define CAM_CC_IFE_0_CLK_SRC 69 +#define CAM_CC_IFE_0_FAST_AHB_CLK 70 +#define CAM_CC_IFE_0_SHIFT_CLK 71 +#define CAM_CC_IFE_1_CLK 72 +#define CAM_CC_IFE_1_CLK_SRC 73 +#define CAM_CC_IFE_1_FAST_AHB_CLK 74 +#define CAM_CC_IFE_1_SHIFT_CLK 75 +#define CAM_CC_IFE_2_CLK 76 +#define CAM_CC_IFE_2_CLK_SRC 77 +#define CAM_CC_IFE_2_FAST_AHB_CLK 78 +#define CAM_CC_IFE_2_SHIFT_CLK 79 +#define CAM_CC_IFE_LITE_AHB_CLK 80 +#define CAM_CC_IFE_LITE_CLK 81 +#define CAM_CC_IFE_LITE_CLK_SRC 82 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_CSID_CLK 84 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85 +#define CAM_CC_IPE_NPS_AHB_CLK 86 +#define CAM_CC_IPE_NPS_CLK 87 +#define CAM_CC_IPE_NPS_CLK_SRC 88 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89 +#define CAM_CC_IPE_PPS_CLK 90 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91 +#define CAM_CC_IPE_SHIFT_CLK 92 +#define CAM_CC_JPEG_1_CLK 93 +#define CAM_CC_JPEG_CLK 94 +#define CAM_CC_JPEG_CLK_SRC 95 +#define CAM_CC_MCLK0_CLK 96 +#define CAM_CC_MCLK0_CLK_SRC 97 +#define CAM_CC_MCLK1_CLK 98 +#define CAM_CC_MCLK1_CLK_SRC 99 +#define CAM_CC_MCLK2_CLK 100 +#define CAM_CC_MCLK2_CLK_SRC 101 +#define CAM_CC_MCLK3_CLK 102 +#define CAM_CC_MCLK3_CLK_SRC 103 +#define CAM_CC_MCLK4_CLK 104 +#define CAM_CC_MCLK4_CLK_SRC 105 +#define CAM_CC_MCLK5_CLK 106 +#define CAM_CC_MCLK5_CLK_SRC 107 +#define CAM_CC_MCLK6_CLK 108 +#define CAM_CC_MCLK6_CLK_SRC 109 +#define CAM_CC_MCLK7_CLK 110 +#define CAM_CC_MCLK7_CLK_SRC 111 +#define CAM_CC_PLL0 112 +#define CAM_CC_PLL0_OUT_EVEN 113 +#define CAM_CC_PLL0_OUT_ODD 114 +#define CAM_CC_PLL1 115 +#define CAM_CC_PLL1_OUT_EVEN 116 +#define CAM_CC_PLL2 117 +#define CAM_CC_PLL3 118 +#define CAM_CC_PLL3_OUT_EVEN 119 +#define CAM_CC_PLL4 120 +#define CAM_CC_PLL4_OUT_EVEN 121 +#define CAM_CC_PLL5 122 +#define CAM_CC_PLL5_OUT_EVEN 123 +#define CAM_CC_PLL6 124 +#define CAM_CC_PLL6_OUT_EVEN 125 +#define CAM_CC_PLL7 126 +#define CAM_CC_PLL7_OUT_EVEN 127 +#define CAM_CC_PLL8 128 +#define CAM_CC_PLL8_OUT_EVEN 129 +#define CAM_CC_PLL9 130 +#define CAM_CC_PLL9_OUT_EVEN 131 +#define CAM_CC_PLL9_OUT_ODD 132 +#define CAM_CC_PLL10 133 +#define CAM_CC_PLL10_OUT_EVEN 134 +#define CAM_CC_QDSS_DEBUG_CLK 135 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 136 +#define CAM_CC_QDSS_DEBUG_XO_CLK 137 +#define CAM_CC_SBI_CLK 138 +#define CAM_CC_SBI_FAST_AHB_CLK 139 +#define CAM_CC_SBI_SHIFT_CLK 140 +#define CAM_CC_SFE_0_CLK 141 +#define CAM_CC_SFE_0_CLK_SRC 142 +#define CAM_CC_SFE_0_FAST_AHB_CLK 143 +#define CAM_CC_SFE_0_SHIFT_CLK 144 +#define CAM_CC_SFE_1_CLK 145 +#define CAM_CC_SFE_1_CLK_SRC 146 +#define CAM_CC_SFE_1_FAST_AHB_CLK 147 +#define CAM_CC_SFE_1_SHIFT_CLK 148 +#define CAM_CC_SFE_2_CLK 149 +#define CAM_CC_SFE_2_CLK_SRC 150 +#define CAM_CC_SFE_2_FAST_AHB_CLK 151 +#define CAM_CC_SFE_2_SHIFT_CLK 152 +#define CAM_CC_SLEEP_CLK 153 +#define CAM_CC_SLEEP_CLK_SRC 154 +#define CAM_CC_SLOW_AHB_CLK_SRC 155 +#define CAM_CC_TITAN_TOP_SHIFT_CLK 156 +#define CAM_CC_XO_CLK_SRC 157 + +/* CAM_CC power domains */ +#define CAM_CC_TITAN_TOP_GDSC 0 +#define CAM_CC_BPS_GDSC 1 +#define CAM_CC_IFE_0_GDSC 2 +#define CAM_CC_IFE_1_GDSC 3 +#define CAM_CC_IFE_2_GDSC 4 +#define CAM_CC_IPE_0_GDSC 5 +#define CAM_CC_SBI_GDSC 6 +#define CAM_CC_SFE_0_GDSC 7 +#define CAM_CC_SFE_1_GDSC 8 +#define CAM_CC_SFE_2_GDSC 9 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_DRV_BCR 1 +#define CAM_CC_ICP_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_QDSS_DEBUG_BCR 7 +#define CAM_CC_SBI_BCR 8 +#define CAM_CC_SFE_0_BCR 9 +#define CAM_CC_SFE_1_BCR 10 +#define CAM_CC_SFE_2_BCR 11 + +#endif -- cgit v1.2.3-58-ga151 From 09ea421652a832083ea380a72addf383965f3682 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:38 +0530 Subject: clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8650 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-8-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sm8650.c | 3591 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 3600 insertions(+) create mode 100644 drivers/clk/qcom/camcc-sm8650.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1bb51a058872..46369edfc07a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -827,6 +827,14 @@ config SM_CAMCC_8550 Support for the camera clock controller on SM8550 devices. Say Y if you want to support camera devices and camera functionality. +config SM_CAMCC_8650 + tristate "SM8650 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8650 + help + Support for the camera clock controller on SM8650 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_6115 tristate "SM6115 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec5b6db6860..28bffa1eb8dd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o +obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm8650.c new file mode 100644 index 000000000000..a37e52a67ed4 --- /dev/null +++ b/drivers/clk/qcom/camcc-sm8650.c @@ -0,0 +1,3591 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL7_OUT_EVEN, + P_CAM_CC_PLL8_OUT_EVEN, + P_CAM_CC_PLL9_OUT_EVEN, + P_CAM_CC_PLL9_OUT_ODD, + P_CAM_CC_PLL10_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco rivian_ole_vco[] = { + { 777000000, 1285000000, 0 }, +}; + +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x31, + .alpha = 0x7aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x10000030, + .config_ctl_hi_val = 0x80890263, + .config_ctl_hi1_val = 0x00000217, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .vco_table = rivian_ole_vco, + .num_vco = ARRAY_SIZE(rivian_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll7_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll7 = { + .offset = 0x7000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { + .offset = 0x7000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll7_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll8_config = { + .l = 0x14, + .alpha = 0xd555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll8 = { + .offset = 0x8000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { + .offset = 0x8000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll8_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll9_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll9 = { + .offset = 0x9000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = { + .offset = 0x9000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll9_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = { + .offset = 0x9000, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll9_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll10_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll10 = { + .offset = 0xa000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = { + .offset = 0xa000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll10_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll10.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL9_OUT_ODD, 4 }, + { P_CAM_CC_PLL9_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL8_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll8_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll7_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL10_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll10_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_10[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_10[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_11_ao[] = { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_11_ao[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { + .cmd_rcgr = 0x1325c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x131cc, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x131e8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src = { + .cmd_rcgr = 0x13204, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x1104c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src = { + .cmd_rcgr = 0x13144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cre_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x15144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x15164, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x15184, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = { + .cmd_rcgr = 0x151a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = { + .cmd_rcgr = 0x151c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x13238, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x131a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_clk_src = { + .cmd_rcgr = 0x12068, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_ife_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x10094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x13168, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x1329c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { + F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_0_clk_src = { + .cmd_rcgr = 0x1306c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_7, + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk_src", + .parent_data = cam_cc_parent_data_7, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { + F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_1_clk_src = { + .cmd_rcgr = 0x130bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_8, + .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk_src", + .parent_data = cam_cc_parent_data_8, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = { + F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_2_clk_src = { + .cmd_rcgr = 0x1310c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_9, + .freq_tbl = ftbl_cam_cc_sfe_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk_src", + .parent_data = cam_cc_parent_data_9, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x132f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_10, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_10, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x132d4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_11_ao, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_11_ao, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x1004c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1004c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x10068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_shift_clk = { + .halt_reg = 0x10078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x10078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { + .halt_reg = 0x13284, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13284, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_nrt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_rt_clk = { + .halt_reg = 0x13274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x13290, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13290, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk = { + .halt_reg = 0x13294, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13294, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x131e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x13200, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13200, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk = { + .halt_reg = 0x1321c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1321c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x132d0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x132d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x13220, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13220, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x10074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_cre_clk = { + .halt_reg = 0x13160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x1322c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1322c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x1103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1103c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk = { + .halt_reg = 0x1203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_2_clk = { + .halt_reg = 0x1208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1208c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x13024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x100b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sbi_clk = { + .halt_reg = 0x10104, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10104, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_0_clk = { + .halt_reg = 0x13090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_1_clk = { + .halt_reg = 0x130e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_2_clk = { + .halt_reg = 0x13130, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk = { + .halt_reg = 0x13164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk = { + .halt_reg = 0x1315c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1315c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x1513c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1513c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x1515c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1515c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x1517c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1517c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x1519c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1519c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi6phytimer_clk = { + .halt_reg = 0x151bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi6phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi7phytimer_clk = { + .halt_reg = 0x151dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi7phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x13250, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13250, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x15140, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x15160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x15180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x151a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy6_clk = { + .halt_reg = 0x151c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy7_clk = { + .halt_reg = 0x151e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x131c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x131bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_shift_clk = { + .halt_reg = 0x11064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x11064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0x12030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { + .halt_reg = 0x12048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_shift_clk = { + .halt_reg = 0x1204c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1204c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_clk = { + .halt_reg = 0x12080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { + .halt_reg = 0x12098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_shift_clk = { + .halt_reg = 0x1209c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1209c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x13018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x1304c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1304c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x13040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x100d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x100ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x100d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x100bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x100d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_shift_clk = { + .halt_reg = 0x100dc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x100dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_1_clk = { + .halt_reg = 0x1318c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1318c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x13180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x132b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x132b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_clk = { + .halt_reg = 0x100f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_fast_ahb_clk = { + .halt_reg = 0x10108, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10108, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_shift_clk = { + .halt_reg = 0x1010c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1010c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_clk = { + .halt_reg = 0x13084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { + .halt_reg = 0x1309c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1309c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_shift_clk = { + .halt_reg = 0x130a0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_clk = { + .halt_reg = 0x130d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { + .halt_reg = 0x130ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_shift_clk = { + .halt_reg = 0x130f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_clk = { + .halt_reg = 0x13124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13124, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = { + .halt_reg = 0x1313c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1313c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_shift_clk = { + .halt_reg = 0x13140, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x13140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_titan_top_shift_clk = { + .halt_reg = 0x1330c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1330c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_titan_top_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x132bc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_bps_gdsc = { + .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_bps_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc = { + .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_2_gdsc = { + .gdscr = 0x12054, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x10080, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sbi_gdsc = { + .gdscr = 0x100e4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sbi_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_0_gdsc = { + .gdscr = 0x13058, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_1_gdsc = { + .gdscr = 0x130a8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_2_gdsc = { + .gdscr = 0x130f8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_sm8650_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr, + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, + [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, + [CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr, + [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr, + [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr, + [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr, + [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr, + [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, + [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, + [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr, + [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL7] = &cam_cc_pll7.clkr, + [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, + [CAM_CC_PLL9] = &cam_cc_pll9.clkr, + [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr, + [CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr, + [CAM_CC_PLL10] = &cam_cc_pll10.clkr, + [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, + [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr, + [CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr, + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr, + [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, + [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, + [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, + [CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr, + [CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr, + [CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr, + [CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr, + [CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_sm8650_gdscs[] = { + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, + [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc, + [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, + [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc, + [CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc, +}; + +static const struct qcom_reset_map cam_cc_sm8650_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_DRV_BCR] = { 0x13310 }, + [CAM_CC_ICP_BCR] = { 0x131a0 }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IFE_1_BCR] = { 0x12000 }, + [CAM_CC_IFE_2_BCR] = { 0x12050 }, + [CAM_CC_IPE_0_BCR] = { 0x1007c }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 }, + [CAM_CC_SBI_BCR] = { 0x100e0 }, + [CAM_CC_SFE_0_BCR] = { 0x13054 }, + [CAM_CC_SFE_1_BCR] = { 0x130a4 }, + [CAM_CC_SFE_2_BCR] = { 0x130f4 }, +}; + +static const struct regmap_config cam_cc_sm8650_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1603c, + .fast_io = true, +}; + +static struct qcom_cc_desc cam_cc_sm8650_desc = { + .config = &cam_cc_sm8650_regmap_config, + .clks = cam_cc_sm8650_clocks, + .num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks), + .resets = cam_cc_sm8650_resets, + .num_resets = ARRAY_SIZE(cam_cc_sm8650_resets), + .gdscs = cam_cc_sm8650_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs), +}; + +static const struct of_device_id cam_cc_sm8650_match_table[] = { + { .compatible = "qcom,sm8650-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); + +static int cam_cc_sm8650_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); + clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); + clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); + + /* Keep clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */ + + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver cam_cc_sm8650_driver = { + .probe = cam_cc_sm8650_probe, + .driver = { + .name = "camcc-sm8650", + .of_match_table = cam_cc_sm8650_match_table, + }, +}; + +module_platform_driver(cam_cc_sm8650_driver); + +MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3-58-ga151 From 0bdb730e63f6628b0f8deb3f11991b1d10f9bca5 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:39 +0530 Subject: arm64: dts: qcom: sm8650: Add video and camera clock controllers Add device nodes for video and camera clock controllers on Qualcomm SM8650 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240602114439.1611-9-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 8af151d924f9..9d9bbb9aca64 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -3316,6 +3318,30 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8650-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8650-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8650-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- cgit v1.2.3-58-ga151 From 2b5004956affaa6dd1d23d431876ad533f10418b Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 7 Jun 2024 23:09:27 +0530 Subject: arm64: dts: qcom: sc7280: Add clocks for QOS configuration Add clocks which need to be enbaled for configuring QoS on sc7280. Signed-off-by: Odelu Kukatla Reviewed-by: Konrad Dybcio Acked-by: Georgi Djakov Link: https://lore.kernel.org/r/20240607173927.26321-5-quic_okukatla@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f8256d5a8f6b..06d0e59e7125 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2130,6 +2130,8 @@ reg = <0 0x016e0000 0 0x1c080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -2137,6 +2139,7 @@ compatible = "qcom,sc7280-aggre2-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { -- cgit v1.2.3-58-ga151 From 65ec35baeb937e91970c5d88118c5638d8582bb3 Mon Sep 17 00:00:00 2001 From: André Apitzsch Date: Mon, 17 Jun 2024 23:22:27 +0200 Subject: ARM: dts: qcom: msm8926-motorola-peregrine: Add accelerometer, magnetometer, regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the accelerometer, magnetometer and regulator that are present on the Motorola Moto G 4G (2013) device. Signed-off-by: André Apitzsch Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240617-peregrine-v2-1-c8835d2da7af@apitzsch.eu Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8926-motorola-peregrine.dts | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 0cbe2d2fbbb1..50ae3cfc95bb 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -68,9 +68,60 @@ }; }; +&blsp1_i2c2 { + clock-frequency = <100000>; + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak8963"; + reg = <0xc>; + interrupts-extended = <&tlmm 38 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8226_l19>; + pinctrl-0 = <&mag_int_default &mag_reset_default>; + pinctrl-names = "default"; + }; + + accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + interrupts-extended = <&tlmm 1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l19>; + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + }; +}; + &blsp1_i2c3 { + clock-frequency = <400000>; status = "okay"; + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + pinctrl-0 = <®_lcd_default>; + pinctrl-names = "default"; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; + }; + }; + sensor@48 { compatible = "ti,tmp108"; reg = <0x48>; @@ -278,6 +329,40 @@ status = "okay"; }; +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_int_default: mag-int-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + reg_lcd_default: reg-lcd-default-state { + pins = "gpio31", "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + &usb { extcon = <&smbb>; dr_mode = "peripheral"; -- cgit v1.2.3-58-ga151 From c9c86387ea1c4034fec34690c7cf2a96f9c21196 Mon Sep 17 00:00:00 2001 From: André Apitzsch Date: Mon, 17 Jun 2024 23:22:28 +0200 Subject: ARM: dts: qcom: msm8926-motorola-peregrine: Update temperature sensor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add alert interrupt for the temperature sensor of Motorola Moto G 4G (2013), although not used by the driver yet. Signed-off-by: André Apitzsch Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240617-peregrine-v2-2-c8835d2da7af@apitzsch.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 50ae3cfc95bb..cff9415baa46 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -125,6 +125,10 @@ sensor@48 { compatible = "ti,tmp108"; reg = <0x48>; + interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&temp_alert_default>; + pinctrl-names = "default"; + #thermal-sensor-cells = <0>; }; }; @@ -361,6 +365,14 @@ bias-disable; output-high; }; + + temp_alert_default: temp-alert-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; }; &usb { -- cgit v1.2.3-58-ga151 From fed1c79fc7fe10900d99a79a36e40443f3267ef3 Mon Sep 17 00:00:00 2001 From: André Apitzsch Date: Mon, 17 Jun 2024 23:22:29 +0200 Subject: ARM: dts: qcom: msm8926-motorola-peregrine: Add framebuffer supplies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add regulators used by the framebuffer of Motorola Moto G 4G (2013). Signed-off-by: André Apitzsch Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240617-peregrine-v2-3-c8835d2da7af@apitzsch.eu Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8926-motorola-peregrine.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index cff9415baa46..376a33125941 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -29,6 +29,10 @@ height = <1280>; stride = <(720 * 3)>; format = "r8g8b8"; + vsp-supply = <®_lcd_pos>; + vsn-supply = <®_lcd_neg>; + vdd-supply = <&pm8226_l28>; + vddio-supply = <&vddio_disp_vreg>; }; }; @@ -51,6 +55,18 @@ }; }; + vddio_disp_vreg: regulator-vddio-disp { + compatible = "regulator-fixed"; + regulator-name = "vddio_disp"; + gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + regulator-boot-on; + vin-supply = <&pm8226_l8>; + pinctrl-0 = <&disp_vddio_default>; + pinctrl-names = "default"; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -342,6 +358,14 @@ output-disable; }; + disp_vddio_default: disp-vddio-default-state { + pins = "gpio34"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + mag_int_default: mag-int-default-state { pins = "gpio38"; function = "gpio"; -- cgit v1.2.3-58-ga151 From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 20 Jun 2024 23:01:22 +0800 Subject: arm64: dts: qcom: ipq6018: add sdhci node Add node to support mmc controller inside of IPQ6018. This controller supports both eMMC and SD cards. Tested with: eMMC (HS200) SD Card (SDR50/SDR104) Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9694140881c6..b3b98f050cfd 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -457,6 +457,25 @@ }; }; + sdhc: mmc@7804000 { + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; + max-frequency = <192000000>; + status = "disabled"; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; -- cgit v1.2.3-58-ga151 From 740bc66960527754d4980e649953fb8ccecf67e5 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 24 Jun 2024 14:52:14 +0530 Subject: arm64: dts: qcom: x1e80100: Add BWMONs Add the CPU and LLCC BWMONs on X1E80100 SoCs. Tested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20240624092214.146935-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 123 +++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 09fd6c8e53bb..8b3c35136153 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5359,6 +5359,129 @@ }; }; + pmu@24091000 { + compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + }; + }; + + /* cluster0 */ + pmu@240b3400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b3400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4800000>; + }; + + opp-1 { + opp-peak-kBps = <7464000>; + }; + + opp-2 { + opp-peak-kBps = <9600000>; + }; + + opp-3 { + opp-peak-kBps = <12896000>; + }; + + opp-4 { + opp-peak-kBps = <14928000>; + }; + + opp-5 { + opp-peak-kBps = <17064000>; + }; + }; + }; + + /* cluster2 */ + pmu@240b5400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b5400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster1 */ + pmu@240b6400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b6400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + system-cache-controller@25000000 { compatible = "qcom,x1e80100-llcc"; reg = <0 0x25000000 0 0x200000>, -- cgit v1.2.3-58-ga151 From 653f0a1e7d6123e2d6f1f9366f6093aa9b908229 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 24 Jun 2024 15:32:14 +0530 Subject: arm64: dts: qcom: x1e80100: Add fastrpc nodes Add fastrpc nodes for ADSP and CDSP on X1E80100 SoC. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20240624100214.189991-1-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 144 +++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 8b3c35136153..72abfab0f1f7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5551,6 +5551,55 @@ label = "lpass"; qcom,remote-pid = <2>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; @@ -5640,6 +5689,101 @@ label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x20>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x20>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0c07 0x20>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0c08 0x20>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x0c0c 0x20>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x0c0d 0x20>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0c0e 0x20>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0c0f 0x20>; + dma-coherent; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 66d83a42f2a3f545c347a9612e9af39cc3804e9d Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Mon, 24 Jun 2024 14:08:36 +0200 Subject: arm64: dts: qcom: sm6115: add resets for sdhc_1 These are documented and supported everywhere, but not described in DT. Add them. Signed-off-by: Caleb Connolly Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240624120849.2550621-2-caleb.connolly@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 86ac6af2ef0f..ac5f071a8db3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1088,6 +1088,8 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; + resets = <&gcc GCC_SDCC1_BCR>; + power-domains = <&rpmpd SM6115_VDDCX>; operating-points-v2 = <&sdhc1_opp_table>; interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG -- cgit v1.2.3-58-ga151 From f1ab099d6591a353899a2ee09c89de0fc908e2d2 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 25 Jun 2024 16:50:15 +0200 Subject: arm64: dts: amlogic: add power domain to hdmitx HDMI Tx needs HDMI Tx memory power domain turned on. This power domain is handled under the VPU power domain. The HDMI Tx currently works because it is enabling the PD by directly poking the power controller register. It is should not do that but properly use the power domain controller. Fix this by adding the power domain to HDMI Tx. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20240625145017.1003346-3-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 4 ++++ 4 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi index e732df3f3114..664912d1beaa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi @@ -363,6 +363,10 @@ power-domains = <&pwrc PWRC_G12A_ETH_ID>; }; +&hdmi_tx { + power-domains = <&pwrc PWRC_G12A_VPU_ID>; +}; + &vpu { power-domains = <&pwrc PWRC_G12A_VPU_ID>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 12ef6e81c8bd..d8a386c31914 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -315,6 +315,7 @@ <&clkc CLKID_CLK81>, <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; }; &sysctrl { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 17bcfa4702e1..82386feb5177 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -327,6 +327,7 @@ <&clkc CLKID_CLK81>, <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; }; &sysctrl { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 75c8aa815eff..97e4b52066dc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -514,6 +514,10 @@ "amlogic,meson-gpio-intc"; }; +&hdmi_tx { + power-domains = <&pwrc PWRC_SM1_VPU_ID>; +}; + &pcie { power-domains = <&pwrc PWRC_SM1_PCIE_ID>; }; -- cgit v1.2.3-58-ga151 From 93ba8817f2ea13593d1c43e02a819cb7d9be048b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 May 2024 12:48:13 +0200 Subject: ARM: dts: ti: align panel timings node name with dtschema DT schema expects panel timings node to follow certain pattern, dtbs_check warnings: am335x-pdu001.dtb: display-timings: '240x320p16' does not match any of the regexes: '^timing', 'pinctrl-[0-9]+' Linux drivers do not care about node name, so this should not have effect on Linux. Acked-by: Bartosz Golaszewski # For DaVinci Link: https://lore.kernel.org/r/20240509104813.216655-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/ti/davinci/da850-evm.dts | 2 +- arch/arm/boot/dts/ti/omap/am335x-guardian.dts | 2 +- arch/arm/boot/dts/ti/omap/am335x-pdu001.dts | 2 +- arch/arm/boot/dts/ti/omap/am335x-pepper.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts index 6c5936278e75..1f5cd35f8b74 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -65,7 +65,7 @@ display-timings { native-mode = <&timing0>; - timing0: 480x272 { + timing0: timing-480x272 { clock-frequency = <9000000>; hactive = <480>; vactive = <272>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts index 56e5d954a490..4b070e634b28 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -74,7 +74,7 @@ pinctrl-1 = <&lcd_pins_sleep>; display-timings { - 320x240 { + timing-320x240 { hactive = <320>; vactive = <240>; hback-porch = <68>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index f38f5bff2b96..17574d0d0525 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -67,7 +67,7 @@ }; display-timings { - 240x320p16 { + timing-240x320p16 { clock-frequency = <6500000>; hactive = <240>; vactive = <320>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts index d5a4a21889d1..e7d561a527fd 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -202,7 +202,7 @@ }; display-timings { native-mode = <&timing0>; - timing0: 480x272 { + timing0: timing-480x272 { clock-frequency = <18400000>; hactive = <480>; vactive = <272>; -- cgit v1.2.3-58-ga151 From 68c402fe5c5e5aa9a04c8bba9d99feb08a68afa7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 May 2024 16:22:45 +0200 Subject: dt-bindings: soc: sti: st,sti-syscon: document codec node st,stih407-core-syscfg syscon block comes with a child - the audio codec, whose binding is still in TXT format. Document the child to fix dtbs_check validation errors, while allowing later the binding to be converted to DT schema: stih410-b2260.dtb: core-syscfg@92b0000: 'sti-sasg-codec' does not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240517142245.178556-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml b/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml index 5f97d9ff17fb..fc933d70d138 100644 --- a/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml @@ -30,6 +30,15 @@ properties: reg: maxItems: 1 + sti-sasg-codec: + description: STi internal audio codec + type: object + additionalProperties: true + + properties: + compatible: + const: st,stih407-sas-codec + required: - compatible - reg -- cgit v1.2.3-58-ga151 From 90b6de4550aac6ac97448d3d26429a0a55dbaa34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 15 Jun 2024 19:49:04 +0200 Subject: ARM: dts: omap am5729-beagleboneai: drop unneeded ti,enable-id-detection There is a ti,enable-id-detection property in the Extcon Palmas (extcon-palmas), but not in the Extcon USB GPIO binding and driver. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406152004.F2fNnorG-lkp@intel.com/ Link: https://lore.kernel.org/r/20240615174904.39012-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index eb1ec85aba28..e6a18954e449 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -196,7 +196,6 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; - ti,enable-id-detection; id-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; }; }; -- cgit v1.2.3-58-ga151 From e11997428fb3c7efe602eca698c739d186c009cb Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 20 May 2024 08:02:22 +0200 Subject: ARM: dts: nxp: imx6: convert NVMEM content to layout syntax MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use cleaner (and non-deprecated) bindings syntax. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Rafał Miłecki Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi | 12 ++++++++---- arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi index 238f3af42822..807f3c95e3ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi @@ -22,12 +22,16 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; vcc-supply = <®_mba6_3p3v>; - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi index a587bc88f76f..789733a45b95 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi @@ -32,12 +32,16 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; vcc-supply = <®_mba6_3p3v>; - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; }; -- cgit v1.2.3-58-ga151 From f1cc2d88fddce24d978ace094bd89e5c05e011a0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 May 2024 12:09:16 -0400 Subject: arm64: dts: imx8-ss-conn: add gpmi nand node Add gpmi nand support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 69 +++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4aaf5a0c1ed8..a4a10ce03bfe 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -28,6 +28,13 @@ conn_ipg_clk: clock-conn-ipg { clock-output-names = "conn_ipg_clk"; }; +conn_bch_clk: clock-conn-bch { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "conn_bch_clk"; +}; + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -302,4 +309,66 @@ conn_subsys: bus@5b000000 { "usb3_aclk"; power-domains = <&pd IMX_SC_R_USB_2_PHY>; }; + + rawnand_0_lpcg: clock-controller@5b290000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, + <&conn_axi_clk>, + <&conn_axi_clk>; + clock-indices = , , + , ; + clock-output-names = "gpmi_bch", + "gpmi_io", + "gpmi_apb", + "gpmi_bch_apb"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + rawnand_4_lpcg: clock-controller@5b290004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b290004 0x10000>; + #clock-cells = <1>; + clocks = <&conn_axi_clk>; + clock-indices = ; + clock-output-names = "apbhdma_hclk"; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + dma_apbh: dma-controller@5b810000 { + compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x5b810000 0x2000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>; + power-domains = <&pd IMX_SC_R_NAND>; + }; + + gpmi: nand-controller@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; + reg-names = "gpmi-nand", "bch"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-names = "bch"; + clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>, + <&rawnand_0_lpcg IMX_LPCG_CLK_4>, + <&rawnand_0_lpcg IMX_LPCG_CLK_0>, + <&rawnand_0_lpcg IMX_LPCG_CLK_5>; + clock-names = "gpmi_io", "gpmi_apb", + "gpmi_bch", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd IMX_SC_R_NAND>; + assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; }; -- cgit v1.2.3-58-ga151 From 2fca3b6ba38034855dd0e2cfd6dbb877d5b2d25c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 May 2024 12:09:17 -0400 Subject: arm64: dts: imx8dxl-ss-conn: add gpmi nand Update gpmi nand and dma_apbh interrupt number for imx8dxl. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 6d13e4fafb76..1e02b04494e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -108,6 +108,13 @@ }; +&dma_apbh { + interrupts = , + , + , + ; +}; + &enet0_lpcg { clocks = <&conn_enet0_root_clk>, <&conn_enet0_root_clk>, @@ -127,6 +134,10 @@ assigned-clock-rates = <125000000>; }; +&gpmi { + interrupts = ; +}; + &usdhc1 { compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; interrupts = ; -- cgit v1.2.3-58-ga151 From 5041dc71d478721243533a8a7443f07b9cf67bcb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 17 Jun 2024 10:12:28 +0200 Subject: dt-bindings: arm: add MBa8MP-RAS314 SBC MBa8MP-RAS314 is an SBC based on the embedded module TQMa8MPxL. All relevant interfaces integrated in the CPU have been implemented on the MBa8MP-RAS314 for (an) industrial usage. Due to the numerous interfaces and the small size of this SBC the use in different applications is possible without the need of a [special,custom] design. Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d2553857d00d..7a7f04fc74fc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1151,8 +1151,9 @@ properties: version as an industrial computing device. items: - enum: - - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL - - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM + - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL + - tq,imx8mp-tqma8mpql-mba8mp-ras314 # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MP-RAS314 + - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM - const: fsl,imx8mp - description: i.MX8MQ based Boards -- cgit v1.2.3-58-ga151 From 189375a4b36ac4b845541acce20485116f137ec9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:40 +0200 Subject: dt-bindings: arm: fsl: document Kontron SMARC-sAMX6i boards The Kontron SMARC-sAMX6i is just a module. There was no device tree for an actual board for now. Document the binding to use the module on the evaluation carrier. Acked-by: Krzysztof Kozlowski Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7a7f04fc74fc..80747d79418a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -362,6 +362,12 @@ properties: - const: gw,ventana - const: fsl,imx6q + - description: i.MX6Q Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0 + items: + - const: kontron,imx6q-samx6i-ads2 + - const: kontron,imx6q-samx6i + - const: fsl,imx6q + - description: i.MX6Q PHYTEC phyBOARD-Mira items: - enum: @@ -543,6 +549,12 @@ properties: - const: gw,ventana - const: fsl,imx6dl + - description: i.MX6DL Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0 + items: + - const: kontron,imx6dl-samx6i-ads2 + - const: kontron,imx6dl-samx6i + - const: fsl,imx6dl + - description: i.MX6DL PHYTEC phyBOARD-Mira items: - enum: -- cgit v1.2.3-58-ga151 From 0df3c7d7a73d75153090637392c0b73a63cdc24a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:29 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix phy-mode The i.MX6 cannot add any RGMII delays. The PHY has to add both the RX and TX delays on the RGMII interface. Fix the interface mode. While at it, use the new phy-connection-type property name. Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 85aeebc9485d..d8c1dfb8c9ab 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -259,7 +259,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; mdio { -- cgit v1.2.3-58-ga151 From edfea889a049abe80f0d55c0365bf60fbade272f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:30 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset The PHY reset line is connected to both the SoC (GPIO1_25) and the CPLD. We must not use the GPIO1_25 as it will drive against the output buffer of the CPLD. Instead there is another GPIO (GPIO2_01), an input to the CPLD, which will tell the CPLD to assert the PHY reset line. Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module") Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index d8c1dfb8c9ab..d6c049b9a9c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -269,7 +269,7 @@ ethphy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; }; }; @@ -516,7 +516,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */ >; }; -- cgit v1.2.3-58-ga151 From b972d6b3b46345023aee56a95df8e2c137aa4ee4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:31 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix board reset On i.MX6 the board is reset by the watchdog. But in turn to do a complete board reset, we have to assert the WDOG_B output which is routed also to the CPLD which then do a complete power-cycle of the board. Fixes: 2125212785c9 ("ARM: dts: imx6qdl-kontron-samx6i: add Kontron SMARC SoM Support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index d6c049b9a9c6..700780bf64f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -817,5 +817,6 @@ /* CPLD is feeded by watchdog (hardwired) */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 73243146246f40fe01a6e2c5106ea160976e6f58 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:32 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: cleanup the PMIC node Remove the comment, remove the unused phandle name for the VGEN5 output. VGEN5 is not used at all. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 700780bf64f5..8c7f21f986e1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -356,10 +356,6 @@ regulator-always-on; }; - /* - * Per schematics, of all VGEN's, only VGEN5 has some - * usage ... but even that - over DNI resistor - */ vgen1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; @@ -380,8 +376,7 @@ regulator-max-microvolt = <3300000>; }; - reg_2p5v_s0: vgen5 { - regulator-name = "V_2V5_S0"; + vgen5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; -- cgit v1.2.3-58-ga151 From 74e1c956a68a65d642447d852e95b3fbb69bebaa Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:33 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix SPI0 chip selects There is a comment in the imx6q variant dtsi claiming that these modules will have one more chip select than the imx6dl variant. This is wrong. Ordinary GPIOs are used for chip selects and both variants of the module share the very same PCB and both have this GPIO routed to the SPI0_CS1# pin of the SMARC connector. Fix it by moving the third chip select description to the common dtsi. Fixes: 2125212785c9 ("ARM: dts: imx6qdl-kontron-samx6i: add Kontron SMARC SoM Support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi | 23 ---------------------- .../boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 5 ++++- 2 files changed, 4 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi index 4d6a0c3e8455..ff062f4fd726 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi @@ -5,31 +5,8 @@ #include "imx6q.dtsi" #include "imx6qdl-kontron-samx6i.dtsi" -#include / { model = "Kontron SMARC sAMX6i Quad/Dual"; compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; }; - -/* Quad/Dual SoMs have 3 chip-select signals */ -&ecspi4 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, - <&gpio3 29 GPIO_ACTIVE_LOW>, - <&gpio3 25 GPIO_ACTIVE_LOW>; -}; - -&pinctrl_ecspi4 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - - /* SPI4_IMX_CS2# - connected to internal flash */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 - /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 - >; -}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 8c7f21f986e1..4a6ab7e7908a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -244,7 +244,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, - <&gpio3 29 GPIO_ACTIVE_LOW>; + <&gpio3 29 GPIO_ACTIVE_LOW>, + <&gpio3 25 GPIO_ACTIVE_LOW>; status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ @@ -459,6 +460,8 @@ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 >; }; -- cgit v1.2.3-58-ga151 From 2005b36923dc74ac2e69475cdef6673716af96a7 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:34 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix product name The correct name of the product is "Kontron SMARC-sAMX6i". See also https://www.kontron.com/en/products/smarc-samx6i/p89810 Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi index a864fdbd5f16..5a9b819d7ee8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi @@ -7,6 +7,6 @@ #include "imx6qdl-kontron-samx6i.dtsi" / { - model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; + model = "Kontron SMARC-sAMX6i Dual-Lite/Solo"; compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi index ff062f4fd726..e76963436079 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi @@ -7,6 +7,6 @@ #include "imx6qdl-kontron-samx6i.dtsi" / { - model = "Kontron SMARC sAMX6i Quad/Dual"; + model = "Kontron SMARC-sAMX6i Quad/Dual"; compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; }; -- cgit v1.2.3-58-ga151 From fa5a518c8078a4b7dc9dcb8b5cf2c9181a3b48c3 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:35 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: always enable eMMC There are no variants of this module without an eMMC. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 4a6ab7e7908a..4d3cd338a707 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -800,7 +800,6 @@ /* SDMMC */ &usdhc4 { - /* Internal eMMC, optional on some boards */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; @@ -809,6 +808,7 @@ non-removable; vmmc-supply = <®_3p3v_s0>; vqmmc-supply = <®_1p8v_s0>; + status = "okay"; }; &wdog1 { -- cgit v1.2.3-58-ga151 From ad851864b4d29e388368a1fdb662923855f76ad5 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:36 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: add SDIO_PWR_EN support The module can enable/disable the SD card power supply and has it's dedicated pin SDIO_PWR_EN for that reason. This is esp. useful to be able to reset the SD card if it was in an UHS mode. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 4d3cd338a707..b0fa07ade76d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -61,6 +61,18 @@ vin-supply = <®_smarc_suppy>; }; + reg_sdio: regulator-sdio { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sdio>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + }; + reg_smarc_lcdbklt: regulator-smarc-lcdbklt { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -640,6 +652,12 @@ >; }; + pinctrl_reg_sdio: reg-sdiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* SDIO_PWR_EN */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 @@ -692,7 +710,6 @@ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ >; }; @@ -795,6 +812,7 @@ pinctrl-0 = <&pinctrl_usdhc3>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sdio>; no-1-8-v; }; -- cgit v1.2.3-58-ga151 From ffd0b96c3889ea9f65b31e863a76357b6b3a265b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:37 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix node names Rename the nodes according to the schema. In particular, rename the bit bang I2C controller to "i2c-N" and the mux nodes of the audmux to "mux-*". While at it, fix the typo "adu", which should have been "aud". Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index b0fa07ade76d..7eeffd6eb476 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -149,7 +149,7 @@ status = "disabled"; }; - i2c_intern: i2c-gpio-intern { + i2c_intern: i2c-0 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_intern>; @@ -160,7 +160,7 @@ #size-cells = <0>; }; - i2c_lcd: i2c-gpio-lcd { + i2c_lcd: i2c-1 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; @@ -172,7 +172,7 @@ status = "disabled"; }; - i2c_cam: i2c-gpio-cam { + i2c_cam: i2c-2 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_cam>; @@ -190,7 +190,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | @@ -202,7 +202,7 @@ >; }; - audmux_adu3 { + mux-aud3 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -210,7 +210,7 @@ >; }; - audmux_ssi2 { + mux-ssi2 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | @@ -222,7 +222,7 @@ >; }; - audmux_adu4 { + mux-aud4 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN -- cgit v1.2.3-58-ga151 From df35c6e9027cf9affe699e632a48082ab1bbba4c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:38 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: fix PCIe reset polarity The PCIe reset line is active low. Fix it. Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 7eeffd6eb476..17abebc006df 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -744,7 +744,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; }; /* LCD_BKLT_PWM */ -- cgit v1.2.3-58-ga151 From 62ee222c92aba06f32d2bedace4741a610370ac0 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:39 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: remove wake-up-gpio property Remove the "wake-up-gpio" property within the PCIe controller node. There is no such property, thus just remove it. This will also make the schema validation happy. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 17abebc006df..99b5e78458aa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -743,7 +743,6 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3-58-ga151 From dac1c5043a083c570592dd048266e9f87b001c4e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 17 Jun 2024 11:13:41 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: add actual device trees For now, there wasn't any in-tree users of the dtsi files for the Kontron SMARC-sAMX6i board. Let's add device trees, for this board on a Kontron SMARC Eval 2.0 Carrier. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts | 12 ++ .../boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts | 12 ++ .../dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi | 148 +++++++++++++++++++++ 4 files changed, 174 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 231c0d73a53e..92e291603ea1 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-kontron-samx6i-ads2.dtb \ imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ imx6dl-mba6a.dtb \ @@ -207,6 +208,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-icore-ofcap10.dtb \ imx6q-icore-ofcap12.dtb \ imx6q-icore-rqs.dtb \ + imx6q-kontron-samx6i-ads2.dtb \ imx6q-kp-tpc.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts new file mode 100644 index 000000000000..6a0c53f23a15 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include "imx6qdl-kontron-samx6i-ads2.dtsi" + +/ { + model = "Kontron SMARC-sAMX6i Dual-Lite/Solo on SMARC Eval 2.0 carrier"; + compatible = "kontron,imx6dl-samx6i-ads2", "kontron,imx6dl-samx6i", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts new file mode 100644 index 000000000000..94c395cc020e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include "imx6qdl-kontron-samx6i-ads2.dtsi" + +/ { + model = "Kontron SMARC-sAMX6i Quad/Dual on SMARC Eval 2.0 carrier"; + compatible = "kontron,imx6q-samx6i-ads2", "kontron,imx6q-samx6i", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi new file mode 100644 index 000000000000..b4a79245b7b6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree include for the Kontron SMARC-sAMX6i board on a SMARC Eval + * 2.0 carrier (ADS2). + * + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + sound { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out Jack", + "Microphone", "Microphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "LINEOUTR", + "Line Out Jack", "LINEOUTL", + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN2L", "Microphone Jack", + "IN2R", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + }; + + reg_codec_mic: regulator-codec-mic { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MIC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_codec_1p8v: regulator-codec-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S0_CODEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&ecspi4 { + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <100000000>; + m25p,fast-read; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "mclk"; + AVDD-supply = <®_codec_1p8v>; + CPVDD-supply = <®_codec_1p8v>; + DBVDD-supply = <®_codec_1p8v>; + DCVDD-supply = <®_codec_1p8v>; + MICVDD-supply = <®_codec_mic>; + }; +}; + +&i2c3 { + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From e227c1e14dfe06a54844014c076d11e9cdef87e4 Mon Sep 17 00:00:00 2001 From: Junyi Zhao Date: Thu, 13 Jun 2024 19:46:36 +0800 Subject: arm64: dts: amlogic: Add Amlogic S4 PWM Add device nodes for PWM_AB, PWM_CD, PWM_EF, PWM_GH and PWM_IJ along with GPIO PIN configs of each channel. Signed-off-by: Junyi Zhao Reviewed-by: George Stark Signed-off-by: Kelvin Zhang Link: https://lore.kernel.org/r/20240613-s4-pwm-v8-2-b5bd0a768282@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 199 ++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index 10896f9df682..b686eacb9662 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -312,6 +312,160 @@ }; }; + pwm_a_pins1: pwm-a-pins1 { + mux { + groups = "pwm_a_d"; + function = "pwm_a"; + }; + }; + + pwm_a_pins2: pwm-a-pins2 { + mux { + groups = "pwm_a_x"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm-b-pins1 { + mux { + groups = "pwm_b_d"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm-b-pins2 { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm-c-pins1 { + mux { + groups = "pwm_c_d"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm-c-pins2 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm-d-pins1 { + mux { + groups = "pwm_d_d"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm-d-pins2 { + mux { + groups = "pwm_d_h"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm-e-pins1 { + mux { + groups = "pwm_e_x"; + function = "pwm_e"; + }; + }; + + pwm_e_pins2: pwm-e-pins2 { + mux { + groups = "pwm_e_z"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm-f-pins1 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm-f-pins2 { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm-g-pins1 { + mux { + groups = "pwm_g_d"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm-g-pins2 { + mux { + groups = "pwm_g_z"; + function = "pwm_g"; + }; + }; + + pwm_h_pins: pwm-h-pins { + mux { + groups = "pwm_h"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm-i-pins1 { + mux { + groups = "pwm_i_d"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm-i-pins2 { + mux { + groups = "pwm_i_h"; + function = "pwm_i"; + }; + }; + + pwm_j_pins: pwm-j-pins { + mux { + groups = "pwm_j"; + function = "pwm_j"; + }; + }; + + pwm_a_hiz_pins: pwm-a-hiz-pins { + mux { + groups = "pwm_a_hiz"; + function = "pwm_a_hiz"; + }; + }; + + pwm_b_hiz_pins: pwm-b-hiz-pins { + mux { + groups = "pwm_b_hiz"; + function = "pwm_b_hiz"; + }; + }; + + pwm_c_hiz_pins: pwm-c-hiz-pins { + mux { + groups = "pwm_c_hiz"; + function = "pwm_c_hiz"; + }; + }; + + pwm_g_hiz_pins: pwm-g-hiz-pins { + mux { + groups = "pwm_g_hiz"; + function = "pwm_g_hiz"; + }; + }; + spicc0_pins_x: spicc0-pins_x { mux { groups = "spi_a_mosi_x", @@ -399,6 +553,51 @@ status = "disabled"; }; + pwm_ab: pwm@58000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x0 0x58000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_A>, + <&clkc_periphs CLKID_PWM_B>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@5a000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x0 0x5a000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_C>, + <&clkc_periphs CLKID_PWM_D>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@5c000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x0 0x5c000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_E>, + <&clkc_periphs CLKID_PWM_F>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@5e000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x0 0x5e000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_G>, + <&clkc_periphs CLKID_PWM_H>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@60000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x0 0x60000 0x0 0x24>; + clocks = <&clkc_periphs CLKID_PWM_I>, + <&clkc_periphs CLKID_PWM_J>; + #pwm-cells = <3>; + status = "disabled"; + }; + i2c0: i2c@66000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x66000 0x0 0x20>; -- cgit v1.2.3-58-ga151 From 666b76e9ae7ed2fd7ac5ed000807ad9bc9a344b7 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:03 +0100 Subject: dt-bindings: vendor-prefixes: add Cudy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy is a Chinese company providing networking products. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..e474055359f1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -338,6 +338,8 @@ patternProperties: description: Czech Technical University in Prague "^cubietech,.*": description: Cubietech, Ltd. + "^cudy,.*": + description: Shenzhen Cudy Technology Co., Ltd. "^cui,.*": description: CUI Devices "^cypress,.*": -- cgit v1.2.3-58-ga151 From c016058b950470bacad0d06628bf396ef4feaba0 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:04 +0100 Subject: dt-bindings: arm64: dts: mediatek: Add Cudy WR3000 V1 router MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-3-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 09f9ffd3ff7b..1cf47db94c57 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -85,6 +85,7 @@ properties: - const: mediatek,mt7629 - items: - enum: + - cudy,wr3000-v1 - xiaomi,ax3000t - const: mediatek,mt7981b - items: -- cgit v1.2.3-58-ga151 From 62b24c7fdf0a039814e3eed33de0dced3fc10aa4 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:05 +0100 Subject: arm64: dts: mediatek: mt7981: add pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 contains on-SoC PIN controller that is also a GPIO provider. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-4-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4feff3d1c5f4..95c6fe888083 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,6 +86,28 @@ #pwm-cells = <2>; }; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + gpio-ranges = <&pio 0 0 56>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- cgit v1.2.3-58-ga151 From deb26f5bce5a2aec514a99141431f6a4360a12b1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:06 +0100 Subject: arm64: dts: mediatek: Add Cudy WR3000 V1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. It has 256 MiB of RAM, some LEDs & buttons and (not described yet) 4 Ethernet ports. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-5-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts | 74 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 37b4ca3a87c9..96da4ad640aa 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts new file mode 100644 index 000000000000..54101cc08a25 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7981b.dtsi" + +/ { + compatible = "cudy,wr3000-v1", "mediatek,mt7981b"; + model = "Cudy WR3000 V1"; + + memory@40000000 { + reg = <0 0x40000000 0 0x10000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-wps { + label = "WPS"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-reset { + label = "RESET"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_WAN_ONLINE; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; -- cgit v1.2.3-58-ga151 From e4b4f4d21aa63cfe6bebc5ca734a965faef095c0 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 9 Mar 2024 10:32:14 +0100 Subject: dt-bindings: arm64: dts: airoha: Add en7581 entry Introduce Airoha EN7581 entry in Airoha dts binding. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/ee9cda964dac62d38d1c239f7b189f707d3708a0.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml index 3292c669ee11..7c38c08dbf3f 100644 --- a/Documentation/devicetree/bindings/arm/airoha.yaml +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -22,6 +22,10 @@ properties: - enum: - airoha,en7523-evb - const: airoha,en7523 + - items: + - enum: + - airoha,en7581-evb + - const: airoha,en7581 additionalProperties: true -- cgit v1.2.3-58-ga151 From ab52c59103002b49f2455371e4b9c56ba3ef1781 Mon Sep 17 00:00:00 2001 From: Daniel Danzberger Date: Sat, 9 Mar 2024 10:32:15 +0100 Subject: arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Daniel Danzberger Co-developed-by: Lorenzo Bianconi Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/f05a36dd7e8ef34ead8a63aa10fcffb542229404.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 26 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 154 ++++++++++++++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..21cd3a87f385 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazon diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile new file mode 100644 index 000000000000..ebea112ce1d7 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts new file mode 100644 index 000000000000..cf58e43dd5b2 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi new file mode 100644 index 000000000000..55eb1762fb11 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu-binary@84000000 { + no-map; + reg = <0x0 0x84000000 0x0 0xa00000>; + }; + + npu-flag@84b0000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x100000>; + }; + + npu-pkt@85000000 { + no-map; + reg = <0x0 0x85000000 0x0 0x1a00000>; + }; + + npu-phyaddr@86b00000 { + no-map; + reg = <0x0 0x86b00000 0x0 0x100000>; + }; + + npu-rxdesc@86d00000 { + no-map; + reg = <0x0 0x86d00000 0x0 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + }; + }; +}; -- cgit v1.2.3-58-ga151 From 85f9e6c303600dc887ea05de7b54240b040c859d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Mar 2024 15:15:37 +0100 Subject: arm64: dts: mediatek: Complete chassis-type for MT8183 Chromebooks Define the chassis type on the remaining MT8183 Chromebooks. Link: https://lore.kernel.org/r/20240313141538.1438167-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts | 1 + 11 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts index 072133fb0f01..f34964afe39b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -9,6 +9,7 @@ / { model = "Google cozmo board"; + chassis-type = "laptop"; compatible = "google,cozmo", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index b595622e7bee..72852b760038 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku1 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; pwmleds { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 5a1c39318a6c..757d0afd14fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku6 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts index 3ea4fdb40118..6641b087e7c5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku7 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts index 3fc5a6181d7e..877256eab262 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku2 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts index 23ad0b91e977..b981dd31a430 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku0 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts index e5bd9191e426..f3ac9c074226 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -9,6 +9,7 @@ / { model = "Google kappa board"; + chassis-type = "laptop"; compatible = "google,kappa", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts index 8fa89db03e63..e8241587949b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -9,5 +9,6 @@ / { model = "Google kenzo sku17 board"; + chassis-type = "laptop"; compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts index 89208b843b27..928b205a616a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -9,6 +9,7 @@ / { model = "Google willow board sku0"; + chassis-type = "laptop"; compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts index c7b20441d053..71307a8052d6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -9,5 +9,6 @@ / { model = "Google willow board sku1"; + chassis-type = "laptop"; compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts index 7739358008ee..5a416143b4a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku32 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183"; }; -- cgit v1.2.3-58-ga151 From 42aa8daecd80d18bc12c43d7be6fd82c6fd526a1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Mar 2024 15:15:38 +0100 Subject: arm64: dts: mediatek: Add missing chassis-type to MT8192 Chromebooks None of the MT8192 Chromebooks had their chassis-type specified: add the right definition for each. Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20240313141538.1438167-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index fd2cb8765a15..ac2673e56fb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev1"; + chassis-type = "convertible"; compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts index 3127ee5f6172..cd86ad9ba28a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev5"; + chassis-type = "convertible"; compatible = "google,hayato-rev5-sku2", "google,hayato-sku2", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index bc88866ab2f5..29aa87e93888 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev0 - 3)"; + chassis-type = "laptop"; compatible = "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts index 0039158c9e60..5e9e598bab90 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev4)"; + chassis-type = "laptop"; compatible = "google,spherion-rev4", "google,spherion", "mediatek,mt8192"; -- cgit v1.2.3-58-ga151 From b376befe9c8897780dc7a92fca76f79b5053f8a1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 22 Mar 2024 10:28:42 +0100 Subject: dt-bindings: soc: mediatek: Add support for MT8188 VPPSYS Add compatible for MT8188 VPP mutex, having different bits to activate mute for various hardware IPs. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240322092845.381313-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index ba2014a8725c..a10326a9683d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex - mediatek,mt8188-disp-mutex + - mediatek,mt8188-vpp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex - mediatek,mt8195-vpp-mutex -- cgit v1.2.3-58-ga151 From 09346afaba0a89652da38966293ad321e2170a90 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 13 Feb 2024 14:00:44 +0100 Subject: arm64: dts: mediatek: mt7988: add XHCI controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add bindings of two on-SoC XHCI controllers. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240213130044.1976-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 32 ++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bba97de4fb44..3eb5396dea22 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT +#include #include +#include / { compatible = "mediatek,mt7988a"; @@ -78,7 +80,7 @@ #interrupt-cells = <3>; }; - clock-controller@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -103,6 +105,34 @@ #clock-cells = <1>; }; + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + + usb@11200000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; -- cgit v1.2.3-58-ga151 From 8f5a9d6b304a6599d5dfb315bb0b0de9edf5dce0 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 21 Feb 2024 09:55:47 +0100 Subject: arm64: dts: mediatek: mt7981: add watchdog & WiFi controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 (Filogic 820) is a low cost version of MT7986 (Filogic 830) with the same watchdog controller. It also comes with on-SoC 802.11ax wireless. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240221085547.27840-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 95c6fe888083..5674ac81d1f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "mediatek,mt7981b"; @@ -62,12 +63,19 @@ #clock-cells = <1>; }; - clock-controller@1001b000 { + topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7981-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; @@ -114,6 +122,22 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = , + , + , + ; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + }; }; timer { -- cgit v1.2.3-58-ga151 From 341e4a070dc288ca6c2f3e47db23c112b7bdd0bd Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 15 Sep 2023 16:12:11 +0800 Subject: dt-bindings: arm64: mediatek: add mt8390-evk board 1. Add compatible for MT8390. 2. Add bindings for the MediaTek mt8390-evk board, also known as the "Genio 700-EVK". The MT8390 and MT8188 belong to the same SoC family, with only minor differences in their physical characteristics. They utilize unique efuse values for differentiation. The booting process and configurations are managed by boot loaders, firmware, and TF-A. Consequently, the part numbers and procurement channels vary. Signed-off-by: Macpaul Lin Reviewed-by: Krzysztof Kozlowski Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230915081212.13959-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 1cf47db94c57..d986b160fed1 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -352,6 +352,11 @@ properties: - enum: - mediatek,mt8365-evk - const: mediatek,mt8365 + - items: + - enum: + - mediatek,mt8390-evk + - const: mediatek,mt8390 + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8395-evk -- cgit v1.2.3-58-ga151 From 7982bf7ec2e378bd60b8d785e379de0af85fecf1 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 15 Sep 2023 16:12:12 +0800 Subject: arm64: dts: mediatek: add device-tree for Genio 700 EVK board Add basic device-tree for the Genio 700 EVK board. The Genio 700 EVK is based on MediaTek MT8390 SoC. MT8390 hardware register maps are identical to MT8188. The Genio 700 EVK has following features: - MT8390 SoC - MT6365 PMIC - MT6319 Buck IC - 12V DC Jack - 2x4GB LPDDR4X - 64GB eMMC 5.1 - 64Mb SPI NOR - M.2 Key A-E slot with PCIe Gen2 and USB 2.0 - 2x DSI LCM ports - 2x touch sensor ports - 2x MIPI-CSI, as camera daughter board slots - USB 2 micro USB connector - USB 3 with 1 to 2 hub: - M.2 Key B slot - Type-C connector, with DisplayPort over Type-C - HDMI 2.0 TX port with Type A HDMI connector - eDP port - Gigabit Ethernet with RJ45 connector - SD card slot - Earphone Jack - Analog Microphone - 2x Digital Microphone - 3x UART with serial-to-usb converters and micro USB connectors Signed-off-by: Chris-QJ Chen Signed-off-by: Pablo Sun Signed-off-by: Macpaul Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230915081212.13959-2-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 880 +++++++++++++++++++++ 2 files changed, 881 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 96da4ad640aa..cae5fcc7ca0c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -77,5 +77,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts new file mode 100644 index 000000000000..6bb1d5d112ef --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Chris Chen + * Pablo Sun + * Macpaul Lin + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "MediaTek Genio-700 EVK"; + compatible = "mediatek,mt8390-evk", "mediatek,mt8390", + "mediatek,mt8188"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + }; + + common_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "5v_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + edp_panel_fixed_3v3: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "edp_panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + }; + + gpio_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "gpio_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_1v8: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "sdio_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_3v3: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "sdio_card"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + touch0_fixed_3v3: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_hub_fixed_3v3: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ + startup-delay-us = <10000>; + enable-active-high; + }; + + usb_hub_reset_1v8: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_reset"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */ + vin-supply = <&usb_hub_fixed_3v3>; + }; + + usb_p0_vbus: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "usb_p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "usb_p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "usb_p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&touch0_fixed_3v3>; + VDDIO-supply = <&mt6359_vio18_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&rt1715_int_pins>; + clock-frequency = <1000000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + dptx_pins: dptx-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-mdio { + pinmux = , + ; + drive-strength = ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + gpio_key_pins: gpio-key-pins { + pins { + pinmux = , + , + ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-pcm { + pinmux = ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc2_dat1_pins: mmc2-dat1-pins { + pins-dat1 { + pinmux = ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + panel_default_pins: panel-default-pins { + pins-dcdc { + pinmux = ; + output-low; + }; + + pins-en { + pinmux = ; + output-low; + }; + + pins-rst { + pinmux = ; + output-high; + }; + }; + + rt1715_int_pins: rt1715-int-pins { + pins_cmd0_dat { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-high; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + usb_default_pins: usb-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = ; + input-enable; + }; + + pins-vbus { + pinmux = ; + output-high; + }; + + }; + + usb1_default_pins: usb1-default-pins { + pins-valid { + pinmux = ; + input-enable; + }; + + pins-usb-hub-3v3-en { + pinmux = ; + output-high; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins-wifi-enable { + pinmux = ; + output-low; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_hub_reset_1v8>; +}; + +&xhci2 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; -- cgit v1.2.3-58-ga151 From b2b6f2edb82a08abe8942535bc77da55a0f43e14 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:00 +0200 Subject: arm64: dts: mediatek: mt8195: Fix GPU thermal zone name for SVS This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: 1e5b6725199f ("arm64: dts: mediatek: mt8195: Add AP domain thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d8b68f86ce4..2ee45752583c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3880,7 +3880,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; -- cgit v1.2.3-58-ga151 From 86beeec5dd2b8e28217f67815a3fb15752031667 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:01 +0200 Subject: arm64: dts: mediatek: mt8192: Fix GPU thermal zone name for SVS This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: c7a728051f4e ("arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 84cbdf6e9eb0..47dea10dd3b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -2234,7 +2234,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8192_AP_GPU0>; -- cgit v1.2.3-58-ga151 From 4a5191c5dd28c9016600af5e4be1db3a74791ab1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:02 +0200 Subject: arm64: dts: mediatek: mt8183: Refactor thermal zones The thermal zones in MT8183 had cryptic names and all of them, apart from the cpu-thermal zone, had no thermal trips, hence those were not probed at all. Refactor the tzts1..5 and tztsABB thermal zones to add the correct thermal trips and give them a meaningful name, corresponding to the actually monitored thermal zone. While at it, also rename the thermal sensor node to "thermal-sensor". Now the thermal zones are probing and their temperatures can be read. Fixes: b325ce39785b ("arm64: dts: mt8183: add thermal zone node") Link: https://lore.kernel.org/r/20240410083002.1357857-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 136 +++++++++++++++++++++++-------- 1 file changed, 102 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 774ae5d9143f..fbf145639b8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1183,7 +1183,7 @@ status = "disabled"; }; - thermal: thermal@1100b000 { + thermal: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; reg = <0 0x1100b000 0 0xc00>; @@ -2090,61 +2090,129 @@ }; }; - /* The tzts1 ~ tzts6 don't need to polling */ - /* The tzts1 ~ tzts6 don't need to thermal throttle */ - - tzts1: tzts1 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts1: soc-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 1>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + trips { + soc_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts2: tzts2 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts2: gpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 2>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + gpu_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts3: tzts3 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts3: md1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 3>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + md1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts4: tzts4 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts4: cpu-little-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 4>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpul_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpul_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts5: tzts5 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts5: cpu-big-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 5>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpub_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpub_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tztsABB: tztsABB { - polling-delay-passive = <0>; - polling-delay = <0>; + tztsABB: tsabb-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 6>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + tsabb_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + tsabb_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 32b33be8894f3389d15b409140d663acbdf9de1d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:08 +0200 Subject: arm64: dts: medaitek: mt8395-nio-12l: Set i2c6 pins to bias-disable GPIOs 25 and 26 do not support pull-up/pull-down when those are muxed as I2C6's SDA6/SCL6 lines: set those to bias-disable to avoid warning messages from the pinctrl driver. Fixes: 96564b1e2ea4 ("arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board") Link: https://lore.kernel.org/r/20240409114211.310462-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index e5d9b671a405..97634cc04e65 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -528,7 +528,7 @@ pins { pinmux = , ; - bias-pull-up = ; + bias-disable; }; }; -- cgit v1.2.3-58-ga151 From 048a70e3141a660d116bb86fe7e158235a9c4656 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:09 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Define RSEL in microamperes The paris pinctrl driver supports specifying the RSEL drive strength in microamperes as well as internal bits definitions: choose to specify those in uA to avoid using hardware specific values in device trees. Link: https://lore.kernel.org/r/20240409114211.310462-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 97634cc04e65..abd6612b8624 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -434,6 +434,8 @@ }; &pio { + mediatek,rsel-resistance-in-si-unit; + eth_default_pins: eth-default-pins { pins-cc { pinmux = , @@ -509,7 +511,7 @@ pins-bus { pinmux = , ; - bias-pull-up = ; + bias-pull-up = <1000>; drive-strength = <6>; drive-strength-microamp = <1000>; }; @@ -519,7 +521,7 @@ pins-bus { pinmux = , ; - bias-pull-up = ; + bias-pull-up = <1000>; drive-strength-microamp = <1000>; }; }; -- cgit v1.2.3-58-ga151 From 9af42385908bb4c33adf9f39af51ba269dbf9882 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:10 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch Enable the PCIe0 PHY to be able to set calibrations read from eFuses, improving the stability and performance of the PCIe link. While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing the USB ports to finally switch to gadget mode if needed, and configure the VBUS/ID pins of both USB ports for the same. Link: https://lore.kernel.org/r/20240409114211.310462-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index abd6612b8624..dfd0cbd71607 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -685,6 +685,26 @@ }; }; + usb3_port0_pins: usb3p0-default-pins { + pins-vbus { + pinmux = ; + input-enable; + }; + }; + + usb2_port0_pins: usb2p0-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-vbus { + pinmux = ; + output-low; + }; + }; + wifi_vreg_pins: wifi-vreg-pins { pins-wifi-pmu-en { pinmux = ; @@ -709,6 +729,10 @@ status = "okay"; }; +&pciephy { + status = "okay"; +}; + &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; @@ -776,6 +800,18 @@ }; }; +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + &uart0 { /* Exposed at 40 pin connector */ pinctrl-0 = <&uart0_pins>; @@ -791,6 +827,8 @@ }; &ssusb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3_port0_pins>; role-switch-default-mode = "host"; usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; @@ -804,6 +842,8 @@ }; &ssusb2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_port0_pins>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 7ca7bbd28983e640c7b58e231d69911a84f5ec8a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:11 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Add power supplies for CPU/GPU scaling Add the necessary power supplies to safely enable CPU and GPU frequency scaling. Link: https://lore.kernel.org/r/20240409114211.310462-6-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index dfd0cbd71607..4b5f6cf16f70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -140,6 +140,38 @@ }; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -343,6 +375,14 @@ }; }; +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + /* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ &mmc0 { pinctrl-names = "default", "state_uhs"; -- cgit v1.2.3-58-ga151 From e9a9055fdcdc1e5a27cef118c5b4f09cdd2fa28e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Apr 2024 15:56:12 +0800 Subject: arm64: dts: mediatek: mt8183-kukui: Drop bogus output-enable property The "output-enable" property is set on uart1's RTS pin. This is bogus because the hardware does not actually have a controllable output buffer. Secondly, the implementation incorrectly treats this property as a request to switch the pin to GPIO output. This does not fit the intended semantic of "output-enable" and it does not have any affect either because the pin is muxed to the UART function, not the GPIO function. Drop the property. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240412075613.1200048-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 100191c6453b..feb8a5acf2cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -803,7 +803,6 @@ }; pins-rts { pinmux = ; - output-enable; }; pins-cts { pinmux = ; @@ -822,7 +821,6 @@ }; pins-rts { pinmux = ; - output-enable; }; pins-cts { pinmux = ; -- cgit v1.2.3-58-ga151 From 27f0974a982998d59c645489da9dd99e4c6bafb2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Apr 2024 15:55:14 +0800 Subject: arm64: dts: mediatek: Drop mediatek,drive-strength-adv usage The "mediatek,drive-strength-adv" pin config property has been deprecated in favor of the generic "drive-strength-microamp" property. Drop or convert all instances. A value of 0 disables the advanced mode, which is the hardware default. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240412075516.1199846-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 6 ------ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 ------ arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 6 ------ arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 4 +--- 4 files changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 681deddffc2a..f04baea5d6cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -160,7 +160,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -169,7 +168,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -178,7 +176,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -187,7 +184,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -196,7 +192,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -205,7 +200,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index feb8a5acf2cd..5472cd0be63a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -533,7 +533,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -542,7 +541,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -551,7 +549,6 @@ pinmux = , ; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -560,7 +557,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -569,7 +565,6 @@ pinmux = , ; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -578,7 +573,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 333c516af490..81f6c205fa98 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -197,7 +197,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -206,7 +205,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -215,7 +213,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -224,7 +221,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -233,7 +229,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -242,7 +237,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 341b6e074139..83456d649ff7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -74,7 +74,6 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -84,7 +83,6 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -94,7 +92,7 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <7>; + drive-strength-microamp = <1000>; }; }; -- cgit v1.2.3-58-ga151 From 87728e3ccf352dd9fd482f894e73d12102bf9014 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 16 Apr 2024 09:14:09 +0200 Subject: arm64: dts: mediatek: mt8195-cherry: Specify sound DAI links and routing The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-18-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 4a11918da370..e35adff02469 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -240,6 +240,7 @@ spk_amplifier: rt1019p { compatible = "realtek,rt1019p"; label = "rt1019p"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rt1019p_pins_default>; sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; @@ -366,6 +367,7 @@ &dp_tx { status = "okay"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&dptx_pin>; @@ -436,6 +438,7 @@ /* Realtek RT5682i or RT5682s, sharing the same configuration */ reg = <0x1a>; interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <0>; realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; @@ -1162,6 +1165,48 @@ "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; pinctrl-names = "default"; pinctrl-0 = <&aud_pins_default>; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Ext Spk", "Speaker"; + + mm-dai-link { + link-name = "ETDM1_IN_BE"; + mediatek,clk-provider = "cpu"; + }; + + hs-playback-dai-link { + link-name = "ETDM1_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + hs-capture-dai-link { + link-name = "ETDM2_IN_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + spk-playback-dai-link { + link-name = "ETDM2_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&spk_amplifier>; + }; + }; + + displayport-dai-link { + link-name = "DPTX_BE"; + codec { + sound-dai = <&dp_tx>; + }; + }; }; &spi0 { -- cgit v1.2.3-58-ga151 From 458d92b55b87d2586d586f1e9ab010ce068dd14c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 16 Apr 2024 09:14:10 +0200 Subject: arm64: dts: mediatek: mt8186-corsola: Specify sound DAI links and routing The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-19-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 42 +++++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index 1807e9d6cb0e..afdab5724eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -42,7 +42,7 @@ default-brightness-level = <576>; }; - bt-sco-codec { + bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; }; @@ -223,12 +223,44 @@ mediatek,adsp = <&adsp>; mediatek,platform = <&afe>; - playback-codecs { - sound-dai = <&it6505dptx>, <&rt1019p>; + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Speakers", "Speaker", + "HDMI1", "TX"; + + hs-playback-dai-link { + link-name = "I2S0"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; + }; + + hs-capture-dai-link { + link-name = "I2S1"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; }; - headset-codec { - sound-dai = <&rt5682s 0>; + spk-share-dai-link { + link-name = "I2S2"; + mediatek,clk-provider = "cpu"; + }; + + spk-hdmi-playback-dai-link { + link-name = "I2S3"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + /* RT1019P and IT6505 connected to the same I2S line */ + codec { + sound-dai = <&it6505dptx>, <&rt1019p>; + }; }; }; -- cgit v1.2.3-58-ga151 From a43bf5bebd24e7bb5fc1b47f8c95d1a52378fc8a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 14 Mar 2024 11:34:59 +0100 Subject: dt-bindings: arm: mediatek: Add MT8195 HP Chromebook x360 13b-ca0002sa Add the MT8195 Cherry platform's Dojo machine, a convertible design commercially known as the HP Chromebook x360 (13b-ca0002sa). Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240314103500.93158-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index d986b160fed1..e93d23849353 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -343,6 +343,14 @@ properties: - const: google,tomato-rev3 - const: google,tomato - const: mediatek,mt8195 + - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa) + items: + - const: google,dojo-sku7 + - const: google,dojo-sku5 + - const: google,dojo-sku3 + - const: google,dojo-sku1 + - const: google,dojo + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8195-demo -- cgit v1.2.3-58-ga151 From 52b7afd5b9afa96b36633256abebd995872f1c76 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 14 Mar 2024 11:35:00 +0100 Subject: arm64: mediatek: mt8195-cherry: Introduce the MT8195 Dojo Chromebook Add a devicetree for the Cherry Dojo (HP Chromebook x360 13b-ca0002sa) convertible type machine. Differences with the already supported Tomato machines include: - Different speaker amplifiers (Dual MAX98380, one per channel) - I2C Touchscreen is on a different address (though still a HID device) - Has NVMe storage on the PCIe0 controller - Slightly different keyboard top row keymap Link: https://lore.kernel.org/r/20240314103500.93158-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8195-cherry-dojo-r1.dts | 114 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 5 + 3 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index cae5fcc7ca0c..3542e42acfff 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts new file mode 100644 index 000000000000..88123842c818 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "HP Dojo (sku 1, 3, 5, 7) board"; + chassis-type = "convertible"; + compatible = "google,dojo-sku7", "google,dojo-sku5", + "google,dojo-sku3", "google,dojo-sku1", + "google,dojo", "mediatek,mt8195"; +}; + +&audio_codec { + compatible = "realtek,rt5682s"; + realtek,amic-delay-ms = <250>; +}; + +&i2c2 { + spk_r_amp: amplifier@38 { + compatible = "maxim,max98390"; + reg = <0x38>; + reset-gpios = <&pio 100 GPIO_ACTIVE_LOW>; + sound-name-prefix = "Right"; + #sound-dai-cells = <0>; + }; + + spk_l_amp: amplifier@39 { + compatible = "maxim,max98390"; + reg = <0x39>; + sound-name-prefix = "Left"; + #sound-dai-cells = <0>; + }; +}; + +&i2c4 { + touchscreen@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x0001>; + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + vdd-supply = <&pp3300_s3>; + }; +}; + +&keyboard_controller { + linux,keymap = < + CROS_STD_MAIN_KEYMAP + + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE) + MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE) + MATRIX_KEY(0x00, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x00, 0x01, KEY_MUTE) + MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN) + MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP) + >; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-down; + }; +}; + +&sound { + compatible = "mediatek,mt8195_mt6359_max98390_rt5682"; + model = "m8195_m98390_5682s"; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Right Spk", "Right BE_OUT", + "Left Spk", "Left BE_OUT"; + + spk-playback-dai-link { + codec { + sound-dai = <&spk_r_amp>, <&spk_l_amp>; + }; + }; +}; + +&spk_amplifier { + /* Disable RT1019P, not present on Dojo */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e35adff02469..fe5400e17b0f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1434,6 +1434,11 @@ MATRIX_KEY(0x02, 0x09, 0) /* T8 */ MATRIX_KEY(0x01, 0x09, 0) /* T9 */ MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + + /* T11 to T13 are present only on Dojo */ + MATRIX_KEY(0x00, 0x01, 0) /* T11 */ + MATRIX_KEY(0x01, 0x05, 0) /* T12 */ + MATRIX_KEY(0x03, 0x05, 0) /* T13 */ >; linux,keymap = < -- cgit v1.2.3-58-ga151 From 666e6f39faff05fe12bfc64c64aa9015135ce783 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 16 Feb 2024 17:57:51 +0800 Subject: arm64: dts: mediatek: mt8395-genio-1200-evk: add u3port1 for xhci1 This patch fixes an issue where xhci1 was not functioning properly because the state and PHY settings were incorrect. The introduction of the 'force-mode' property in the phy-mtk-tphy driver allows for the correct initialization of xhci1 by updating the Device Tree settings accordingly. The necessary fixup which added support for the 'force-mode' switch in the phy-mtk-tphy driver. commit 9b27303003f5 ("phy: mediatek: tphy: add support force phy mode switch") Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com Prior to this fix, the system would exhibit the following probe failure messages for xhci1: xhci-mtk 11290000.usb: supply vbus not found, using dummy regulator xhci-mtk 11290000.usb: uwk - reg:0x400, version:104 xhci-mtk 11290000.usb: xHCI Host Controller xhci-mtk 11290000.usb: new USB bus registered, assigned bus number 5 xhci-mtk 11290000.usb: clocks are not stable (0x1003d0f) xhci-mtk 11290000.usb: can't setup: -110 xhci-mtk 11290000.usb: USB bus 5 deregistered xhci-mtk: probe of 11290000.usb failed with error -110 With the application of this dts fixup, the aforementioned initialization errors are resolved and xhci1 is working. Signed-off-by: Macpaul Lin Link: https://lore.kernel.org/r/20240216095751.4937-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 1558649f633c..a1b613808780 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -854,6 +854,10 @@ &u3phy1 { status = "okay"; + + u3port1: usb-phy@700 { + mediatek,force-mode; + }; }; &u3phy2 { @@ -900,6 +904,8 @@ }; &xhci1 { + phys = <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 1b4472430f659369694fe7483995fd39c8d543b6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 8 Apr 2024 10:08:15 +0200 Subject: dt-bindings: arm64: mediatek: add Kontron 3.5"-SBC-i1200 Add the compatible string for the Kontron 3.5"-SBC-i1200 single board computer. Signed-off-by: Michael Walle Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240408080816.4134370-1-mwalle@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index e93d23849353..eccc3f7cc4e6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -367,6 +367,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk - radxa,nio-12l - const: mediatek,mt8395 -- cgit v1.2.3-58-ga151 From 94aaf79a6af5d64bad9f6de72a241722a1d8b9df Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 8 Apr 2024 10:08:16 +0200 Subject: arm64: dts: mediatek: add Kontron 3.5"-SBC-i1200 Add basic support for the Kontron 3.5" single board computer featuring a Mediatek i1200 SoC (MT8395/MT8195). Signed-off-by: Michael Walle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240408080816.4134370-2-mwalle@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts | 1127 ++++++++++++++++++++ 2 files changed, 1128 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3542e42acfff..12f67959f257 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -79,5 +79,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts new file mode 100644 index 000000000000..e4b2af9489a8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Kontron Europe GmbH + * + * Author: Michael Walle + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include +#include +#include +#include +#include +#include + +/ { + model = "Kontron 3.5\"-SBC-i1200"; + compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + gpios = <&pio 107 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + function = LED_FUNCTION_POWER; + color = ; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x0 0x80000000>; + }; + + vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; + + thermal_sensor0: thermal-sensor-0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor1: thermal-sensor-1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 1>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor2: thermal-sensor-2 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 2>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; +}; + +&auxadc { + status = "okay"; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpu { + status = "okay"; + mali-supply = <&mt6315_7_vbuck1>; +}; + +/* CSI1/CSI2 connector */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* CSI3 connector */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + /* LVDS bridge @f */ +}; + +/* Touch panel connector */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* B2B connector */ +&i2c4 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + #interrupt-cells = <1>; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN1-supply = <&vsys>; + LDO_VIN2-supply = <&vsys>; + LDO_VIN3-supply = <&vsys>; + + mt6360_buck1: BUCK1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: BUCK2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: LDO1 { + regulator-name = "mt6360_ldo1"; /* Test point */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo2: LDO2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: LDO3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: LDO5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo6: LDO6 { + regulator-name = "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: LDO7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + hs400-ds-delay = <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>; + pinctrl-1 = <&mmc1_default_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-reset { + pinmux = ; + output-high; + }; + + pins-interrupt { + pinmux = ; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + + pins-cc { + pinmux = , + , + , + ; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_detect_pins: mmc1-detect-pins { + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux = , + , + ; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs { + pinmux = ; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie0_pins_default: pcie0-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie1_pins_default: pcie1-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up = ; + }; + }; + + led_pins: led-pins { + pins-power-en { + pinmux = ; + output-high; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + }; + + uart1_pins: uart1-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-rts { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-rts { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + }; + + uart3_pins: uart3-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + + pins-tx { + pinmux = ; + }; + }; + + uart4_pins: uart4-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + firmware-name = "mediatek/mt8195/scp.img"; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-name = "Vgpu"; + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +/* USB3.2 front port */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + tpm: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <18500000>; + }; +}; + +/* B2B connector */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&thermal_zones { + cpu-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor0>; + + trips { + trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-top-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor1>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-bottom-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor2>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +/* USB3 */ +&u3phy0 { + status = "okay"; +}; + +/* PCIe1/USB2 */ +&u3phy1 { + status = "okay"; +}; + +/* USB2 */ +&u3phy2 { + status = "okay"; +}; + +/* USB2 */ +&u3phy3 { + status = "okay"; +}; + +/* USB3.2 front port */ +&xhci0 { + status = "okay"; +}; + +/* USB2.0 M.2 Key-B */ +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&xhci2 { + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&xhci3 { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 897a7edba9330974726c564dfdbf4fb5e203b9ac Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Thu, 2 May 2024 23:39:51 +0800 Subject: arm64: dts: mediatek: mt8192-asurada: Add off-on-delay-us for pp3300_mipibrdg Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it complies with the panel's unprepare delay (the time to power down completely) of the power sequence. Explicit configuration on the regulator node is required because mt8192-asurada uses the same power supply for the panel and the anx7625 DP bridge. For example, the power sequence could be violated in this sequence: 1. Bridge on: panel goes off, but regulator doesn't turn off (refcount=1). 2. Bridge off: regulator turns off (refcount=0). 3. Bridge resume -> regulator turns on but the bridge driver doesn't check the delay. Or in this sequence: 1. Bridge on: panel goes off. The regulator doesn't turn off (refcount=1), but the .unprepared_time in panel_edp is still updated. 2. Bridge off, regulator goes off (refcount=0). 3. Panel on, but the panel driver uses the wrong .unprepared_time to check the unprepare delay. Fixes: f9f00b1f6b9b ("arm64: dts: mediatek: asurada: Add display regulators") Signed-off-by: Pin-yen Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240502154455.3427793-1-treapking@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 7a704246678f..08d71ddf3668 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -147,6 +147,7 @@ regulator-boot-on; gpio = <&pio 127 GPIO_ACTIVE_HIGH>; vin-supply = <&pp3300_g>; + off-on-delay-us = <500000>; }; /* separately switched 3.3V power rail */ -- cgit v1.2.3-58-ga151 From f14cdf03d1b9c1ce45b3752a54c500c36d26d3dc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 29 May 2024 14:06:14 +0200 Subject: arm64: dts: mediatek: mt7986a: bpi-r3: Convert to sugar syntax Overlay syntactic sugar for generating target-path fragments is supported by the version of dtc supplied with the kernel since commit 50aafd60898a8b3e ("scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc"). Hence convert the Bananapi R3 overlay devicetree source files to sugar syntax, improving readability. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/2fd900a30b5a0f7de4ea68f60bac250794b8cdb4.1716984213.git.geert+renesas@glider.be Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso | 28 +++---- .../dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 74 +++++++++--------- .../dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 90 +++++++++++----------- .../dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 16 ++-- 4 files changed, 98 insertions(+), 110 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso index 779dc6782bb1..047a8388811e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -9,21 +9,17 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 7b97c5c91bd0..24398f8a7da4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -9,46 +9,44 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - spi_nand: flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x280000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "reserved"; + reg = <0x100000 0x280000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso index e48881be4ed6..6a0d529b54ac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -9,54 +9,52 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@80000 { - label = "reserved2"; - reg = <0x80000 0x80000>; - }; - - partition@100000 { - label = "fip"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "recovery"; - reg = <0x180000 0xa80000>; - }; - - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso index f623bce075ce..d9e01967acc4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -9,15 +9,11 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From f80cfe9616b7448eca709a3e87ca57201cd5787c Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 5 Apr 2024 12:50:30 +0200 Subject: arm64: dts: mediatek: mt7981: fix code alignment for PWM clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align "clocks" array entries to start at the same column. Fixes: cf29427573cc ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T") Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240405105030.24559-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5674ac81d1f8..8a6263cc569c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,10 +86,10 @@ compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; #pwm-cells = <2>; }; -- cgit v1.2.3-58-ga151 From 454880d6168cc908d5f45a81a9aa6bdddf2ebc55 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 14 May 2024 03:51:54 +0200 Subject: arm64: dts: mediatek: mt7981: add efuse block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 (Filogic 820) uses efuse for storing calibration data. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240514015154.11206-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 8a6263cc569c..0fc7c6d33d72 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -116,6 +116,13 @@ #interrupt-cells = <2>; }; + efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- cgit v1.2.3-58-ga151 From 4e293c219e8e6b4a0c3aeeb4388836947ca478e3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 10 May 2024 11:57:06 +0200 Subject: dt-bindings: arm64: mediatek: add BananaPi R3 Mini Add MT7988A based BananaPi R3 Mini. Signed-off-by: Frank Wunderlich Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240510095707.6895-2-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index eccc3f7cc4e6..f73dd2edeb9e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -92,6 +92,7 @@ properties: - enum: - acelink,ew-7886cax - bananapi,bpi-r3 + - bananapi,bpi-r3mini - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items: -- cgit v1.2.3-58-ga151 From a098310bee5dbdfdea1265f137afad3e96d5ae86 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 10 May 2024 11:57:07 +0200 Subject: arm64: dts: mediatek: Add mt7986 based Bananapi R3 Mini Add devicetree for Bananapi R3 Mini SBC. Key features: - MediaTek MT7986A(Filogic 830) Quad core ARM Cortex A53 - Wifi 6 2.4G/5G (MT7976C) - 2G DDR RAM - 8G eMMC flash - 128MB Nand flash - 2x 2.5GbE network port - 1x M.2 Key B USB interface - 1x M.2 KEY M PCIe interface - 1x USB2.0 interface source: https://wiki.banana-pi.org/Banana_Pi_BPI-R3_Mini Co-developed-by: Eric Woudstra Signed-off-by: Eric Woudstra Co-developed-by: Tianling Shen Signed-off-by: Tianling Shen Signed-off-by: Frank Wunderlich Reviewed-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240510095707.6895-3-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts | 493 +++++++++++++++++++++ 2 files changed, 494 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 12f67959f257..39226a832312 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts new file mode 100644 index 000000000000..e2a2fea7adf0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Frank Wunderlich + * Eric Woudstra + * Tianling Shen + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3 Mini"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* + * The signal is inverted on this board and the PWM driver + * does not support polarity inversion. + */ + /* cooling level (0, 1, 2) */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000>; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + usb_vbus: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + en8811_a: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "phy1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 16 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + en8811_b: regulator-phy2 { + compatible = "regulator-fixed"; + regulator-name = "phy2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 17 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + map1 { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_med>; + }; + + map2 { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_low>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + /* MAC Address EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-width = <8>; + pagesize = <8>; + size = <256>; + }; +}; + +&mdio { + phy0: ethernet-phy@14 { + reg = <14>; + interrupts-extended = <&pio 48 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_a_gpio5 */ + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_a_gpio4 */ + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; + + phy1: ethernet-phy@15 { + reg = <15>; + interrupts-extended = <&pio 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_b_gpio5 */ + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_b_gpio4 */ + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + usb_ngff_pins: usb-ngff-pins { + ngff-gnss-off-conf { + pins = "GPIO_6"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pe-rst-conf { + pins = "GPIO_7"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-wwan-off-conf { + pins = "GPIO_8"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pwr-off-conf { + pins = "GPIO_9"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-rst-conf { + pins = "GPIO_10"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-coex-conf { + pins = "SPI1_CS"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ssusb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_ngff_pins>; + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; +}; + -- cgit v1.2.3-58-ga151 From 1061f1b6610a87e1064cc914cb20210a0ca7b83d Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:31 +0200 Subject: dt-bindings: vendor-prefixes: add OpenWrt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt project (with the help of MediaTek and Banana Pi) has produced its very first own hardware. It needs its own prefix. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index e474055359f1..eabc353b8512 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1084,6 +1084,8 @@ patternProperties: description: OpenPandora GmbH "^openrisc,.*": description: OpenRISC.io + "^openwrt,.*": + description: OpenWrt "^option,.*": description: Option NV "^oranth,.*": -- cgit v1.2.3-58-ga151 From ff31b980c4e198e9807092c25bc96ed89231dd8a Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:32 +0200 Subject: dt-bindings: arm64: dts: mediatek: Add OpenWrt One MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt One is the first ever OpenWrt product. It's based on MT7981B and has entered an early production stage. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-3-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index f73dd2edeb9e..11331fd6a616 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: - cudy,wr3000-v1 + - openwrt,one - xiaomi,ax3000t - const: mediatek,mt7981b - items: -- cgit v1.2.3-58-ga151 From 95c465c439541bd5f38ced2f827f0f069bcc118e Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:33 +0200 Subject: arm64: dts: mediatek: Add OpenWrt One MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt One is the first ever OpenWrt product. It's based on MT7981B (AKA Filogic 820) and has 1 GiB or DDR4 RAM. The rest of peripherals remains to be added later. Signed-off-by: Rafał Miłecki Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-4-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 39226a832312..56d551da917e 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts new file mode 100644 index 000000000000..4f6cbb491287 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible = "openwrt,one", "mediatek,mt7981b"; + model = "OpenWrt One"; + + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; + }; +}; -- cgit v1.2.3-58-ga151 From 09ff2216a035709967096210cea144563bbc3259 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:43:01 +0200 Subject: arm64: dts: mediatek: mt7988: add PWM controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7988 has on-SoC controller that can control up to 8 PWM interfaces. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604064302.487-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 3eb5396dea22..27098f724b7a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -105,6 +105,25 @@ #clock-cells = <1>; }; + pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; + #pwm-cells = <2>; + status = "disabled"; + }; + usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, -- cgit v1.2.3-58-ga151 From 660c230bf30280334931bfcb4fb815998433ff57 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:43:02 +0200 Subject: arm64: dts: mediatek: mt7988: add I2C controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7988 has three on-SoC I2C controllers that are the same hardware blocks as already noticed on MT7981 chipsets. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604064302.487-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 27098f724b7a..aa728331e876 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -124,6 +124,45 @@ status = "disabled"; }; + i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11004000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11005000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, -- cgit v1.2.3-58-ga151 From aebba1030a5766cdf894ed4ab0cac7aed5aee9c1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 09:49:16 +0200 Subject: arm64: dts: mediatek: mt7622: fix "emmc" pinctrl mux MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Value "emmc_rst" is a group name and should be part of the "groups" property. This fixes: arch/arm64/boot/dts/mediatek/mt7622-rfb1.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# Fixes: 3725ba3f5574 ("arm64: dts: mt7622: add pinctrl related device nodes") Fixes: 0b6286dd96c0 ("arm64: dts: mt7622: add bananapi BPI-R64 board") Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240604074916.7929-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 224bb289660c..2791de5b28f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -329,8 +329,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 41629769bdc8..8c3e2e2578bc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -268,8 +268,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", -- cgit v1.2.3-58-ga151 From c3e87229b0fd8917af8dad6af94744c94929ed95 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:31:59 +0200 Subject: arm64: dts: mediatek: mt7981: add I2C controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 has one on-SoC I2C controller that differs from recent Mediatek blocks by having a different SLAVE_ADDR register offset (thus a custom binding compatible string). Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604063159.29216-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 0fc7c6d33d72..64aeeb24efac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -94,6 +94,21 @@ #pwm-cells = <2>; }; + i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, -- cgit v1.2.3-58-ga151 From 1e8a1a9ea21831a32555e25174b7587668326bbc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:19 +0200 Subject: arm64: dts: mediatek: mt8365: drop incorrect power-domain-cells The top SCPSYS node is not a power domain provider. It's child "power-controller" is instead. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-1-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..455c2ae3b30a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -302,7 +302,6 @@ scpsys: syscon@10006000 { compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { -- cgit v1.2.3-58-ga151 From cc827572ad153d63b5f1a3b376727681bcba567e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:20 +0200 Subject: arm64: dts: mediatek: mt8365: use a specific SCPSYS compatible SoCs should use dedicated compatibles for each of their syscon nodes to precisely describe the block. Using an incorrect compatible does not allow to properly match/validate children of the syscon device. Replace SYSCFG compatible, which does not have children, with a new dedicated one for SCPSYS block. Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-2-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 455c2ae3b30a..eb449bfa8803 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -300,7 +300,7 @@ }; scpsys: syscon@10006000 { - compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; /* System Power Manager */ -- cgit v1.2.3-58-ga151 From b220332f9849e82b55d566a40f9c8457b177e232 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:21 +0200 Subject: arm64: dts: mediatek: mt8173-elm: drop PMIC's syscon node According to AngeloGioacchino Del Regno, the syscon node in PMIC is neither needed nor used. It looks like a solution to expose some of the registers of PMIC. Drop it to solve also incorrect number of entries in the "reg" property and fix dtbs_check warning: mt8173-elm.dtb: syscon@c000: reg: [[0, 49152], [0, 264]] is too long Link: https://lore.kernel.org/all/671a4b1e-3d95-438c-beae-d967e0ad1c77@collabora.com/ Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-3-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 6d962d437e02..b4d85147b77b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1134,12 +1134,6 @@ rtc: mt6397rtc { compatible = "mediatek,mt6397-rtc"; }; - - syscfg_pctl_pmic: syscon@c000 { - compatible = "mediatek,mt6397-pctl-pmic-syscfg", - "syscon"; - reg = <0 0x0000c000 0 0x0108>; - }; }; }; -- cgit v1.2.3-58-ga151 From 45682a4fffdd9abd6e2df9c5c534d22f2eda94f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:05 +0200 Subject: arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes In preparation for adding multimedia nodes and power domains, add support for the two Global Command Engine (GCE) mailboxes found in this SoC. Link: https://lore.kernel.org/r/20240527093908.97574-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index b4315c9214dc..06fa3b862c31 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -413,6 +414,22 @@ clock-names = "spi", "wrap"; }; + gce0: mailbox@10320000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8188-scp"; reg = <0 0x10500000 0 0x100000>, -- cgit v1.2.3-58-ga151 From e15d0dd73eacf8cce08725631b99e45ff58061f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:06 +0200 Subject: arm64: dts: mediatek: mt8188: Add VDOSYS0/1 support for multimedia Add support for the two VDOSYS blocks in MT8188, later on used for various Multimedia related IP, including display and video codecs. Link: https://lore.kernel.org/r/20240527093908.97574-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 06fa3b862c31..84f2809eae7a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -969,5 +969,22 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + vdosys0: syscon@1c01d000 { + compatible = "mediatek,mt8188-vdosys0", "syscon"; + reg = <0 0x1c01d000 0 0x1000>; + #clock-cells = <1>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8188-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; + }; }; }; -- cgit v1.2.3-58-ga151 From eaf73e4224a348ef228de6b0b6fa0c7da91d0e25 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:07 +0200 Subject: arm64: dts: mediatek: mt8188: Add support for SoC power domains In preparation for adding support for hardware IP that requires power switching, add the necessary power domains nodes for the MT8188 SoC. Link: https://lore.kernel.org/r/20240527093908.97574-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 323 +++++++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 84f2809eae7a..0bca6c9f15fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -384,6 +384,329 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8188-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG1 { + reg = ; + clocks = <&topckgen CLK_APMIXED_MFGPLL>, + <&topckgen CLK_TOP_MFG_CORE_TMP>; + clock-names = "mfg", "alt"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "top", "cam", "ccu", "img", "venc", + "vdec", "wpe", "cfgck", "cfgxo", + "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", + "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", + "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", + "ss-sram-rdr", "ss-iommu", "ss-imgcam", + "ss-emi", "ss-subcmn-rdr", "ss-rsi", + "ss-cmn-l4", "ss-vdec1", "ss-wpe", + "ss-cvdo-ve1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_APB_BUS>; + clock-names = "cfgck", "cfgxo", "ss-gals", + "ss-cmn", "ss-emi", "ss-iommu", + "ss-larb", "ss-rsi", "ss-bus"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, + <&vppsys1 CLK_VPP1_GALS5>, + <&vppsys1 CLK_VPP1_GALS6>, + <&vppsys1 CLK_VPP1_LARB5>, + <&vppsys1 CLK_VPP1_LARB6>; + clock-names = "cfgck", "cfgxo", + "ss-vpp1-g5", "ss-vpp1-g6", + "ss-vpp1-l5", "ss-vpp1-l6"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg = ; + clocks = <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC0 { + reg = ; + clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { + reg = ; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_CCU_AHB>, + <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; + clock-names = "cam", "ccu", "bus", "cfgck"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { + reg = ; + clocks = <&camsys CLK_CAM_MAIN_LARB13>, + <&camsys CLK_CAM_MAIN_LARB14>, + <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; + clock-names= "ss-cam-l13", "ss-cam-l14", + "ss-cam-mm0", "ss-cam-mm1", + "ss-camsys"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { + reg = ; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names = "ss-camb-sub", + "ss-camb-raw", + "ss-camb-yuv"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { + reg =; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names = "ss-cama-sub", + "ss-cama-raw", + "ss-cama-yuv"; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "cfgck", "cfgxo", "ss-larb2", + "ss-larb3", "ss-gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_HDMI_TX { + reg = ; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP_24M>; + clock-names = "bus", "hdcp"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_DP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_EDP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VENC { + reg = ; + clocks = <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_VENC>, + <&vencsys CLK_VENC1_GALS>, + <&vencsys CLK_VENC1_GALS_SRAM>; + clock-names = "ss-ve1-larb", "ss-ve1-core", + "ss-ve1-gals", "ss-ve1-sram"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_WPE { + reg = ; + clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, + <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; + clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names = "ss-pextp-fmem"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names = "seninf0", "seninf1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP_AO { + reg = ; + clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_ADSP>; + clock-names = "bus", "main"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { + reg = ; + clocks = <&topckgen CLK_TOP_ASM_H>; + clock-names = "asm"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; + clock-names = "a1sys", "intbus", "adspck"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_ETHER { + reg = ; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ethermac"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8188-wdt"; reg = <0 0x10007000 0 0x100>; -- cgit v1.2.3-58-ga151 From c44589a890ffd64fbb2813eaadab143c347ef909 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:08 +0200 Subject: arm64: dts: mediatek: mt8188: Add support for Mali GPU on Panfrost Add the necessary OPP table for the GPU and also add a GPU node to enable support for the Valhall-JM G57 MC3 found on this SoC, using the Panfrost driver. Link: https://lore.kernel.org/r/20240527093908.97574-6-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 0bca6c9f15fe..29d012d28edb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -294,6 +294,112 @@ clock-output-names = "clk32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-microvolt = <575000>; + opp-supported-hw = <0xff>; + }; + opp-431000000 { + opp-hz = /bits/ 64 <431000000>; + opp-microvolt = <587500>; + opp-supported-hw = <0xff>; + }; + opp-473000000 { + opp-hz = /bits/ 64 <473000000>; + opp-microvolt = <600000>; + opp-supported-hw = <0xff>; + }; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + opp-microvolt = <612500>; + opp-supported-hw = <0xff>; + }; + opp-556000000 { + opp-hz = /bits/ 64 <556000000>; + opp-microvolt = <625000>; + opp-supported-hw = <0xff>; + }; + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <637500>; + opp-supported-hw = <0xff>; + }; + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-microvolt = <650000>; + opp-supported-hw = <0xff>; + }; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-microvolt = <662500>; + opp-supported-hw = <0xff>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <675000>; + opp-supported-hw = <0xff>; + }; + opp-730000000 { + opp-hz = /bits/ 64 <730000000>; + opp-microvolt = <687500>; + opp-supported-hw = <0xff>; + }; + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-microvolt = <700000>; + opp-supported-hw = <0xff>; + }; + opp-790000000 { + opp-hz = /bits/ 64 <790000000>; + opp-microvolt = <712500>; + opp-supported-hw = <0xff>; + }; + opp-835000000 { + opp-hz = /bits/ 64 <835000000>; + opp-microvolt = <731250>; + opp-supported-hw = <0xff>; + }; + opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0xff>; + }; + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x8f>; + }; + opp-915000000-5 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <762500>; + opp-supported-hw = <0x30>; + }; + opp-915000000-6 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <800000>; + opp-supported-hw = <0x8f>; + }; + opp-950000000-5 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x30>; + }; + opp-950000000-6 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -1167,6 +1273,23 @@ #clock-cells = <1>; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; + reg = <0 0x13000000 0 0x4000>; + + clocks = <&mfgcfg CLK_MFGCFG_BG3D>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, + <&spm MT8188_POWER_DOMAIN_MFG3>, + <&spm MT8188_POWER_DOMAIN_MFG4>; + power-domain-names = "core0", "core1", "core2"; + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8188-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; -- cgit v1.2.3-58-ga151 From 95173af725e6f41eb470466a52ddf2054439409c Mon Sep 17 00:00:00 2001 From: Hsin-Te Yuan Date: Thu, 13 Jun 2024 11:58:54 +0000 Subject: arm64: dts: mediatek: mt8183-kukui: Fix the value of `dlg,jack-det-rate` mismatch According to Documentation/devicetree/bindings/sound/dialog,da7219.yaml, the value of `dlg,jack-det-rate` property should be "32_64" instead of "32ms_64ms". Fixes: dc0ff0fa3a9b ("ASoC: da7219: Add Jack insertion detection polarity") Signed-off-by: Hsin-Te Yuan Link: https://lore.kernel.org/r/20240613-jack-rate-v2-1-ebc5f9f37931@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 8b57706ac814..586eee79c73c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -27,7 +27,7 @@ dlg,btn-cfg = <50>; dlg,mic-det-thr = <500>; dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-det-rate = "32_64"; dlg,jack-rem-deb = <1>; dlg,a-d-btn-thr = <0xa>; -- cgit v1.2.3-58-ga151 From 0b2f9d0e397b6c2d510d118bac036f7f6bb3c3db Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Wed, 15 Nov 2023 12:35:01 +0800 Subject: arm64: dts: mt8173: Add G2Touch touchscreen node Lenovo Ideapad C330 Chromebook (MTK) uses G2Touch touchscreen as a second source component. Signed-off-by: Pin-yen Lin Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20231115043511.2670477-1-treapking@chromium.org [Angelo: Rebased and added comment] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index 90cbbc18a483..8d1cbc92bce3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -27,6 +27,15 @@ hid-descr-addr = <0x0020>; interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>; }; + + /* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */ + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + hid-descr-addr = <0x0001>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; }; &i2c4 { -- cgit v1.2.3-58-ga151 From 70bf81dd2c2dedbed1f19dfc5d1d2f22474a5296 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 Jan 2024 16:40:41 +0800 Subject: arm64: dts: mediatek: mt8183-pico6: Fix wake-on-X event node names The wake-on-bt and wake-on-wlan nodes don't have a button- or event- prefix that the gpio-keys binding requires. Fix up the node names to satisfy the binding. While at it, also fix up the GPIO overriding structure for the wake-on-wlan node. Instead of referencing the gpio-keys node and then open coding the node, add a label for the event node, and use that to reference and override the GPIO settings. Fixes: 055ef10ccdd4 ("arm64: dts: mt8183: Add jacuzzi pico/pico6 board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131084043.3970576-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 8 +++----- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index 6a7ae616512d..0d5a11c93c68 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -17,7 +17,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_pins_wakeup>; - wobt { + event-wobt { label = "Wake on BT"; gpios = <&pio 42 GPIO_ACTIVE_HIGH>; linux,code = ; @@ -47,10 +47,8 @@ }; }; -&wifi_wakeup { - wowlan { - gpios = <&pio 113 GPIO_ACTIVE_LOW>; - }; +&wifi_wakeup_event { + gpios = <&pio 113 GPIO_ACTIVE_LOW>; }; &wifi_pwrseq { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 5472cd0be63a..a9e40c291d0e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_wakeup>; - button-wowlan { + wifi_wakeup_event: event-wowlan { label = "Wake on WiFi"; gpios = <&pio 113 GPIO_ACTIVE_HIGH>; linux,code = ; -- cgit v1.2.3-58-ga151 From 4055416e6c51347e7dd5784065263fe0ced0bb7d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 Jan 2024 16:39:29 +0800 Subject: arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add ports node for anx7625 The anx7625 binding requires a "ports" node as a container for the "port" nodes. The jacuzzi dtsi file is missing it. Add a "ports" node under the anx7625 node, and move the port related nodes and properties under it. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131083931.3970388-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 25 ++++++++++++---------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 7592e3b86037..fa4ab4d2899f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -155,21 +155,24 @@ vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&vddio_mipibrdg>; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - anx7625_in: endpoint { - remote-endpoint = <&dsi_out>; + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - anx7625_out: endpoint { - remote-endpoint = <&panel_in>; + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; }; }; -- cgit v1.2.3-58-ga151 From db77778a405aa0431835939f8482bea0adb26fe5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 20 Jun 2024 12:18:30 +0200 Subject: arm64: dts: mediatek: Makefile: Generate symbols for DTBO support Add DTC_FLAGS '-@' for mt7986a-bananapi-bpi-r3 and -mini to instruct the devicetree compiler to enable generation of symbols. This allows proper support for Device Tree Overlay(s) for those boards; future boards that need DTBO support are expected to add their own DTC_FLAGS_{dtb-name}. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240620101830.1097548-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 56d551da917e..5dbb695d053f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -84,3 +84,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb + +# Device tree overlays support +DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ +DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ -- cgit v1.2.3-58-ga151 From 9b4e41428498651da04e0ceca879958a6703b4dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jun 2024 17:47:37 +0800 Subject: dt-bindings: arm: mediatek: Add MT8186 Voltorb Chromebooks Add an entry for the MT8186 based Voltorb Chromebooks, also known as the Acer Chromebook 311 (C723/C723T). The device is a clamshell style laptop with an optional touchscreen. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240620094746.2404753-3-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 11331fd6a616..1d4bb50fcd8d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -296,6 +296,13 @@ properties: - const: google,tentacruel-sku327683 - const: google,tentacruel - const: mediatek,mt8186 + - description: Google Voltorb (Acer Chromebook 311 C723/C732T) + items: + - enum: + - google,voltorb-sku589824 + - google,voltorb-sku589825 + - const: google,voltorb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8186-evb -- cgit v1.2.3-58-ga151 From 321ad586e6073e33dd576ec33ae1803db3b1e717 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jun 2024 17:47:38 +0800 Subject: arm64: dts: mediatek: Add MT8186 Voltorb Chromebooks Add device trees for the MT8186 based Voltorb Chromebooks, also known as the Acer Chromebook 311 (C723/C723T). The devices are clamshell style laptops with an optional touchscreen. The devices differ from the other existing MT8186 Chromebooks in that it uses a higher speced / binned SoC which also requires a separate PMIC for the big core cluster. Also, a different codec is used for the internal speakers. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240620094746.2404753-4-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt8186-corsola-voltorb-sku589824.dts | 13 +++ .../mediatek/mt8186-corsola-voltorb-sku589825.dts | 25 +++++ .../boot/dts/mediatek/mt8186-corsola-voltorb.dtsi | 103 +++++++++++++++++++++ 4 files changed, 143 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5dbb695d053f..8fd7b2bb7a15 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts new file mode 100644 index 000000000000..d16834eec87a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589824 board"; + compatible = "google,voltorb-sku589824", "google,voltorb", + "mediatek,mt8186"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts new file mode 100644 index 000000000000..45e57f7706cc --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589825 board"; + compatible = "google,voltorb-sku589825", "google,voltorb", + "mediatek,mt8186"; +}; + +&i2c1 { + touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi new file mode 100644 index 000000000000..52ec58128d56 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +#include +#include + +#include "mt8186-corsola-steelix.dtsi" + +/ { + chassis-type = "laptop"; + + max98360a: max98360a { + compatible = "maxim,max98360a"; + sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&cpu6 { + proc-supply = <&mt6319_buck1>; +}; + +&cpu7 { + proc-supply = <&mt6319_buck1>; +}; + +&gpio_keys { + status = "disabled"; +}; + +&keyboard_controller { + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&mt6366_vproc11_reg { + status = "disabled"; +}; + +&cluster1_opp_14 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1118750>; +}; + +&cluster1_opp_15 { + opp-hz = /bits/ 64 <2200000000>; +}; + +&rt1019p{ + status = "disabled"; +}; + +&sound { + compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound"; + status = "okay"; + + spk-hdmi-playback-dai-link { + codec { + sound-dai = <&it6505dptx>, <&max98360a>; + }; + }; +}; + +&spmi { + pinctrl-names = "default"; + pinctrl-0 = <&spmi_pins>; + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6319_buck1: vbuck1 { + regulator-name = "ppvar_dvdd_proc_bc_mt6319"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&touchscreen { + status = "disabled"; +}; -- cgit v1.2.3-58-ga151 From df768350a87031971a3c834b480aef6ad6f1f1a0 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Thu, 16 May 2024 22:48:47 +0200 Subject: arm64: dts: mt7622: fix switch probe on bananapi-r64 After commit 868ff5f4944a ("net: dsa: mt7530-mdio: read PHY address of switch from device tree") the mt7531 switch on Bananapi-R64 was not detected. mt7530-mdio mdio-bus:00: reset timeout mt7530-mdio mdio-bus:00: probe with driver mt7530-mdio failed with error -110 Fix this by adding phy address in devicetree. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20240516204847.171029-1-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 2791de5b28f6..d12eac9b3eeb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -149,9 +149,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <0x1f>; interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3-58-ga151 From d79603c2be61ca9d4fafa89ac7f5d8cc78568af4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 20 Jun 2024 12:16:55 +0200 Subject: arm64: dts: mediatek: Declare drive-strength numerically On some devicetrees, the drive-strength property gets assigned a MTK_DRIVE_(x)_mA definition, which matches with (x). For example, MTK_DRIVE_8mA equals to 8 and MTK_DRIVE_30mA equals to 30. Also keeping in mind that the drive-strength property is, by (binding) definition, taking a number in milliamperes unit, change all devicetrees to avoid the usage of any MTK_DRIVE_(x) definition. Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240620101656.1096374-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 4 +-- .../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 8 ++--- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 12 +++---- .../mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts | 2 +- .../mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts | 2 +- .../dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 6 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 8 ++--- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 4 +-- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 26 +++++++------- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 4 +-- .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 40 +++++++++++----------- .../boot/dts/mediatek/mt8395-genio-1200-evk.dts | 28 +++++++-------- 12 files changed, 72 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 234e3b23d7a8..c84c47c1352f 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -137,7 +137,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; rx_pins { pinmux = , @@ -151,7 +151,7 @@ mdio_pins { pinmux = , ; - drive-strength = ; + drive-strength = <8>; input-enable; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 7364c7278276..91de920c2245 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -288,25 +288,25 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 3fab21f59d18..bb4671c18e3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -213,14 +213,14 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins_clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <4>; }; pins_insert { @@ -241,13 +241,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <2>; bias-pull-up = ; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <2>; bias-pull-down = ; }; @@ -265,13 +265,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts index 4eb2a0d571af..ddb993521bbf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts index 6a733361e8ae..10c4f920a7d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index 0d5a11c93c68..cce326aec1aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -66,16 +66,16 @@ &mmc1_pins_default { pins-cmd-dat { - drive-strength = ; + drive-strength = <6>; }; pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a9e40c291d0e..6345e969efae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -488,7 +488,7 @@ , , ; /*8ch-i2s to it6505*/ - drive-strength = ; + drive-strength = <6>; }; }; @@ -502,7 +502,7 @@ ; input-enable; bias-pull-down; - drive-strength = ; + drive-strength = <2>; }; }; @@ -673,14 +673,14 @@ , , ; - drive-strength = ; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 81f6c205fa98..1aa668c3ccf9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -350,14 +350,14 @@ , , ; - drive-strength = ; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index b82f7176b4a1..31d424b8fc7c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -305,14 +305,14 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-cc { pinmux = , , , ; - drive-strength = ; + drive-strength = <8>; }; pins-rxd { pinmux = , @@ -377,7 +377,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -392,13 +392,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -406,7 +406,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -421,19 +421,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -441,7 +441,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -452,7 +452,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; @@ -465,7 +465,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -476,7 +476,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 50cbaefa1a99..4211a992dd9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -308,7 +308,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { clk-pins { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -319,7 +319,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 6bb1d5d112ef..1474bef7e754 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -383,13 +383,13 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-mdio { pinmux = , ; - drive-strength = ; + drive-strength = <8>; input-enable; }; @@ -404,7 +404,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-txd { @@ -412,7 +412,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; }; @@ -520,7 +520,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -535,13 +535,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -549,7 +549,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -564,19 +564,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -584,7 +584,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -595,7 +595,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; @@ -608,7 +608,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -619,7 +619,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -627,7 +627,7 @@ mmc2_default_pins: mmc2-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; @@ -638,7 +638,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; @@ -650,7 +650,7 @@ mmc2_uhs_pins: mmc2-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; @@ -661,7 +661,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -678,7 +678,7 @@ pins-dat1 { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index a1b613808780..a06610fff8ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -475,7 +475,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-mdio { @@ -502,7 +502,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; }; @@ -567,7 +567,7 @@ pinmux = , ; bias-pull-up = ; - drive-strength = ; + drive-strength = <6>; }; }; @@ -582,7 +582,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -597,13 +597,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -611,7 +611,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -626,19 +626,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -646,7 +646,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -657,7 +657,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -665,7 +665,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -676,7 +676,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; -- cgit v1.2.3-58-ga151 From 0c85e2e377c368e1e0f04ea28dcbc5aa06302551 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 16 Jun 2024 23:40:56 +0100 Subject: arm64: dts: allwinner: h616: add IOMMU node The Allwinner H616 contains a scatter-gather IOMMU connected to some video related devices. It's almost compatible to the one used in the H6, though with minor incompatibilities. Add the DT node describing its resources, so that devices like the video or display engine can connect to it. Signed-off-by: Andre Przywara Tested-by: Ryan Walklin Link: https://lore.kernel.org/r/20240616224056.29159-6-andre.przywara@arm.com [wens@csie.org: Move IOMMU node after GIC node for address order] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b07d7aee1896..bf4d41ecbfdc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -343,6 +343,15 @@ #interrupt-cells = <3>; }; + iommu: iommu@30f0000 { + compatible = "allwinner,sun50i-h616-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_IOMMU>; + resets = <&ccu RST_BUS_IOMMU>; + #iommu-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h616-mmc", "allwinner,sun50i-a100-mmc"; -- cgit v1.2.3-58-ga151 From d45db4fcd3ae0d13191c8db00583f0bc49d9795d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 24 Jun 2024 19:43:29 +0200 Subject: ARM: dts: rockchip: add #sound-dai-cells to hdmi node no rk3036 '#sound-dai-cells' is required to properly interpret the list of DAI specified in the 'sound-dai' property, so add them to the 'hdmi' node for 'rk3036.dtsi'. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/55d302e5-c018-4b93-84c1-8cf75162e939@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3036.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 04af224005f8..96279d1e02fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -402,6 +402,7 @@ rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; + #sound-dai-cells = <0>; status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From 313da6f69fa41d044b03f2ea37e56fe49f1e8a42 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 24 Jun 2024 19:26:48 +0200 Subject: ARM: dts: rockchip: add #sound-dai-cells to hdmi node on rk3128 '#sound-dai-cells' is required to properly interpret the list of DAI specified in the 'sound-dai' property, so add them to the 'hdmi' node for 'rk3128.dtsi'. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/9d0fabb0-70b0-4b4b-ac7c-389b1c7afe20@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 5019aae1be32..23e633387c24 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -566,6 +566,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; power-domains = <&power RK3128_PD_VIO>; + #sound-dai-cells = <0>; status = "disabled"; ports { -- cgit v1.2.3-58-ga151 From fd513b922e34edb0db1284a4abee7f6c10ffd9a7 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 28 May 2024 19:49:54 +0530 Subject: arm64: dts: qcom: qcs6490-rb3gen2: enable hdmi bridge Rb3Gen2 has a lt9611uxc DSI-to-HDMI bridge on i2c0, with reset gpio from pm7250b gpio2 and irq gpio from tlmm gpio24. Bridge supplies are Vdd connected to input supply directly and vcc to L11c. Enable HDMI output, bridge and corresponding DSI output. Signed-off-by: Venkata Prahlad Valluru Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240528141954.7567-1-quic_vvalluru@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 94 ++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index c4cde4328e3d..0d45662b8028 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -52,6 +52,25 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -538,6 +557,46 @@ status = "okay"; }; +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <&vreg_l11c_2p8>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + &i2c1 { status = "okay"; @@ -595,6 +654,21 @@ remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + &mdss_edp { status = "okay"; }; @@ -726,3 +800,23 @@ function = "gpio"; bias-disable; }; + +&pm7250b_gpios { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio2"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; +}; + +&tlmm { + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-58-ga151 From 0602ba0dcd0e76067a0b7543e92b2de3fb231073 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 26 Jun 2024 17:27:30 +0200 Subject: arm64: dts: amlogic: gx: correct hdmi clocks The clocks provided to HDMI tx are not consistent between gx and g12: * gx receives the peripheral clock as 'isfr' while g12 receives it as 'iahb' * g12 gets the HDMI system clock as 'isfr' but gx does not even get it. It surely needs that clock since the driver is directly poking around the clock controller's registers for that clock. Align gx SoCs with g12 and provide: * the HDMI peripheral clock as 'iahb' * the HDMI system clock as 'isfr' Fixes: 6939db7e0dbf ("ARM64: dts: meson-gx: Add support for HDMI output") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20240626152733.1350376-2-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index d8a386c31914..041c37b809f2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -311,8 +311,8 @@ <&reset RESET_HDMI_SYSTEM_RESET>, <&reset RESET_HDMI_TX>; reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, + clocks = <&clkc CLKID_HDMI>, + <&clkc CLKID_HDMI_PCLK>, <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; power-domains = <&pwrc PWRC_GXBB_VPU_ID>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 82386feb5177..067108800a58 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -323,8 +323,8 @@ <&reset RESET_HDMI_SYSTEM_RESET>, <&reset RESET_HDMI_TX>; reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, + clocks = <&clkc CLKID_HDMI>, + <&clkc CLKID_HDMI_PCLK>, <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -- cgit v1.2.3-58-ga151 From 1443b6ea806dfcdcee6c894784332c9c947ac319 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 26 Jun 2024 17:27:31 +0200 Subject: arm64: dts: amlogic: setup hdmi system clock HDMI Tx needs the system clock set on the xtal rate. This clock is managed by the main clock controller of the related SoCs. Currently 2 part of the display drivers race to setup the HDMI system clock by directly poking the controller register. The clock API should be used to setup the rate instead. Use assigned-clock to setup the HDMI system clock. Fixes: 6939db7e0dbf ("ARM64: dts: meson-gx: Add support for HDMI output") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20240626152733.1350376-3-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 5 +++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 4057ee808a58..d08c97797010 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -215,6 +215,11 @@ #sound-dai-cells = <0>; status = "disabled"; + assigned-clocks = <&clkc CLKID_HDMI_SEL>, + <&clkc CLKID_HDMI>; + assigned-clock-parents = <&xtal>, <0>; + assigned-clock-rates = <0>, <24000000>; + /* VPU VENC Input */ hdmi_tx_venc_port: port@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 041c37b809f2..ed00e67e6923 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -316,6 +316,11 @@ <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; power-domains = <&pwrc PWRC_GXBB_VPU_ID>; + + assigned-clocks = <&clkc CLKID_HDMI_SEL>, + <&clkc CLKID_HDMI>; + assigned-clock-parents = <&xtal>, <0>; + assigned-clock-rates = <0>, <24000000>; }; &sysctrl { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 067108800a58..f58d1790de1c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -328,6 +328,11 @@ <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; power-domains = <&pwrc PWRC_GXBB_VPU_ID>; + + assigned-clocks = <&clkc CLKID_HDMI_SEL>, + <&clkc CLKID_HDMI>; + assigned-clock-parents = <&xtal>, <0>; + assigned-clock-rates = <0>, <24000000>; }; &sysctrl { -- cgit v1.2.3-58-ga151 From e00d100a94a15531eec0caf2dddfeec439690097 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Wed, 20 Mar 2024 22:33:49 +0100 Subject: ARM: dts: st: add thermal property on stih410.dtsi and stih418.dtsi "#thermal-sensor-cells" is required and missing in thermal nodes. Add it. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih410.dtsi | 1 + arch/arm/boot/dts/st/stih418.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index 29e95e9d3229..a69231854f78 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -270,6 +270,7 @@ clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = ; + #thermal-sensor-cells = <0>; }; cec@94a087c { diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b35b9b7a7ccc..0f0db988a907 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -113,6 +113,7 @@ clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = ; + #thermal-sensor-cells = <0>; }; }; }; -- cgit v1.2.3-58-ga151 From b664f6f7a77a41b0e8da7e12534debc94c9d23db Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Tue, 25 Jun 2024 23:32:42 +0200 Subject: ARM: dts: sti: add thermal-zones support on stih418 Add a 'thermal-zones' node for stih418. A thermal-zone needs three components: - thermal sensors, described in an earlier commit[1] - cooling devices, specified for each CPU - a thermal zone, describing the overall behavior. The thermal zone needs references to both CPUs and thermal sensors, which phandle are also added. The thermal management will then be achieved on CPUs using the cpufreq framework. [1] https://lore.kernel.org/lkml/20240320-thermal-v3-2-700296694c4a@gmail.com/ Reviewed-by: Patrice Chotard Signed-off-by: Raphael Gallais-Pou Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih407-family.dtsi | 6 +++-- arch/arm/boot/dts/st/stih418.dtsi | 41 +++++++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 29302e74aa1d..35a55aef7f4b 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -33,7 +33,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -52,8 +52,9 @@ clock-latency = <100000>; cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -66,6 +67,7 @@ 1200000 0 800000 0 500000 0>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index 0f0db988a907..8fb8b3af5e49 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -6,23 +6,26 @@ #include "stih418-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; }; @@ -44,6 +47,38 @@ reset-names = "global", "port"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + + thermal-sensors = <&thermal>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; @@ -107,7 +142,7 @@ assigned-clock-rates = <200000000>; }; - thermal@91a0000 { + thermal: thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; clock-names = "thermal"; -- cgit v1.2.3-58-ga151 From 7ef44e179af0e84962b5c450f09ea92a427981d8 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:32 +0200 Subject: arm64: dts: rockchip: Add PCIe endpoint mode support Add a device tree node representing PCIe endpoint mode. The controller can either be configured to run in Root Complex or Endpoint mode. If a user wants to run the controller in endpoint mode, the user has to disable the pcie3x4 node and enable the pcie3x4_ep node. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240607-rockchip-pcie-ep-v1-v5-12-0a042d6b0049@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 37101768999b..0ce0934ec6b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -186,6 +186,41 @@ }; }; + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + pcie3x2: pcie@fe160000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; -- cgit v1.2.3-58-ga151 From 40658534756f8369e93b84fa75c20bde6528cb82 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:33 +0200 Subject: arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel Link: https://lore.kernel.org/r/20240607-rockchip-pcie-ep-v1-v5-13-0a042d6b0049@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 ++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5775cdd4d056..adfb168759dd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -129,6 +129,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; -- cgit v1.2.3-58-ga151 From 406a554b382200abfabd1df423a425f6efee53e0 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sat, 22 Jun 2024 00:57:20 +0300 Subject: arm64: dts: rockchip: Drop invalid mic-in-differential on rk3568-rock-3a The 'mic-in-differential' DT property supported by the RK809/RK817 audio codec driver is actually valid if prefixed with 'rockchip,': DTC_CHK arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb rk3568-rock-3a.dtb: pmic@20: codec: 'mic-in-differential' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# However, the board doesn't make use of differential signaling, hence drop the incorrect property and the now unnecessary 'codec' node. Fixes: 22a442e6586c ("arm64: dts: rockchip: add basic dts for the radxa rock3 model a") Reported-by: Jonas Karlman Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20240622-rk809-fixes-v2-3-c0db420d3639@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ebdedea15ad1..59f1403b4fa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -531,10 +531,6 @@ }; }; }; - - codec { - mic-in-differential; - }; }; }; -- cgit v1.2.3-58-ga151 From e643e4eb4bef6a2f95bf0c61a20c991bccecb212 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sat, 22 Jun 2024 00:57:21 +0300 Subject: arm64: dts: rockchip: Fix mic-in-differential usage on rk3566-roc-pc The 'mic-in-differential' DT property supported by the RK809/RK817 audio codec driver is actually valid if prefixed with 'rockchip,': DTC_CHK arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dtb rk3566-roc-pc.dtb: pmic@20: codec: 'mic-in-differential' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# Make use of the correct property name. Fixes: a8e35c4bebe4 ("arm64: dts: rockchip: add audio nodes to rk3566-roc-pc") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20240622-rk809-fixes-v2-4-c0db420d3639@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts index 63eea27293fe..67e7801bd489 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -269,7 +269,7 @@ vcc9-supply = <&vcc3v3_sys>; codec { - mic-in-differential; + rockchip,mic-in-differential; }; regulators { -- cgit v1.2.3-58-ga151 From ec03073888ad23223ebb986e62583c20a9ed3c07 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sat, 22 Jun 2024 00:57:22 +0300 Subject: arm64: dts: rockchip: Fix mic-in-differential usage on rk3568-evb1-v10 The 'mic-in-differential' DT property supported by the RK809/RK817 audio codec driver is actually valid if prefixed with 'rockchip,': DTC_CHK arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dtb rk3568-evb1-v10.dtb: pmic@20: codec: 'mic-in-differential' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# Make use of the correct property name. Fixes: 3e4c629ca680 ("arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20240622-rk809-fixes-v2-5-c0db420d3639@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 19f8fc369b13..8c3ab07d3807 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -475,7 +475,7 @@ }; codec { - mic-in-differential; + rockchip,mic-in-differential; }; }; }; -- cgit v1.2.3-58-ga151 From 9417909e253ffa57f014822a79cca9b1f2b25492 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 2 Jun 2024 08:25:38 +0200 Subject: arm64: dts: rockchip: Delete the SoC variant dtsi for RK3399Pro The commit 587b4ee24fc7 ("arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs") describes the RK3399Pro's PCI Express interface as the way built-in NPU communicates with the rest of the SoC. All available evidence shows this not to be accurate, as described in detail below. Moreover, the rk3399pro.dtsi isn't used anywhere, so let's delete it. The publicly available schematics of the Radxa Rock Pi N10 carrier board [1] and the Vamrs VMARC RK3399Pro SoM, [2] which put together form the currently single supported RK3399Pro-based board, clearly show that the PCI Express x4 interface of this SoC is fully functional and actually not used by the SoC to communicate with the built-in NPU. In more detail, the VMARC SoM exports the SoC's PCI Express interface at its board-to-board connector, and the Rock Pi N10 routes it to an M.2 M-key slot with four PCI Express lanes. Both the Rockchip RK3399Pro datasheet, version 1.1, [3] and the Rockchip RK3399Pro technical reference manual (TRM), first part of the version 1.0, [4] don't describe that the SoC's PCI Express interface is reserved for the NPU. Instead, the RK3399Pro TRM describes that the NPU uses AHB and AXI interfaces as the host interface (HIF). The RK3399Pro datasheet clearly describes that the PCI Express x4 interface is available for general-purpose use, just like it's the case with the standard Rockchip RK3399 SoC, [5] albeit with a bit shorter feature list provided in the RK3399Pro datasheet. Even the publicly available reference RK3399Pro schematic from Rockchip [6] shows the availability of a standard PCI Express slot with four lanes, which would be pretty much impossible if the PCI Express interface was reserved for the communication with the built-in NPU. Based on the RK3399Pro datasheet [3] and the board schematics, [2][6] the built-in NPU actually exports NPU_PCIE as a separate PCI Express x2 interface that's partially pinmuxed with the NPU's separate USB 3.0 interface, which is described further in the next paragraph. However, the NPU's separate PCI Express x2 interface is left undocumented in the publicly available RK3399Pro documentation, in which it's clearly described as reserved for internal use and not intended for the communication with the NPU. Finally, the evidently independent nature of the separate NPU_PCIE x2 interface makes ignoring it safe when it comes to determining the nature and the availability of the RK3399Pro's main PCI Express x4 interface. The actual application-level communication with the built-in NPU, including powering it up and down and uploading the NPU firmware, is performed through the separate USB 2.0 and USB 3.0 interfaces exported by the NPU, [7] which the VMARC SoM [2] and the reference board design from Rockchip [6] route to the SoC's standard USB 2.0 and USB 3.0 interfaces, to make the NPU accessible to software running on the SoC's ARM cores. [1] https://dl.radxa.com/rockpin10/docs/hw/rockpi_n10_sch_v1.1_20190909.pdf [2] https://dl.radxa.com/rockpin10/docs/hw/VMARC_RK3399Pro_sch_V1.1_20190619.pdf [3] https://www.rockchip.fr/RK3399Pro%20datasheet%20V1.1.pdf [4] https://www.rockchip.fr/Rockchip%20RK3399Pro%20TRM%20V1.0%20Part1.pdf [5] https://www.rockchip.fr/RK3399%20datasheet%20V1.8.pdf [6] https://opensource.rock-chips.com/images/e/e4/RK_EVB_RK3399PRO_LP3S178P332SD8_V11_20181113_RZF.pdf [7] https://wiki.radxa.com/RockpiN10/dev/NPU-booting Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/4449f7d4eead787308300e2d1d37b88c9d1446b2.1717308862.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 ---------------------- 1 file changed, 22 deletions(-) delete mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi deleted file mode 100644 index bb5ebf6608b9..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. - -#include "rk3399.dtsi" - -/ { - compatible = "rockchip,rk3399pro"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie_phy { - status = "okay"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie0 { - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; -- cgit v1.2.3-58-ga151 From 2af8d8a583a483530ce3cbb06a953fa5aacdb557 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 24 Jun 2024 16:53:54 +0200 Subject: ARM: dts: armada-{370-xp,375,38x,39x}: Drop #size-cells from mpic node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The marvell,mpic interrupt controller has no children nodes. Drop the Signed-off-by: Marek Behún Link: https://lore.kernel.org/r/20240624145355.8034-2-kabel@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/marvell/armada-370-xp.dtsi | 1 - arch/arm/boot/dts/marvell/armada-375.dtsi | 1 - arch/arm/boot/dts/marvell/armada-38x.dtsi | 1 - arch/arm/boot/dts/marvell/armada-39x.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi index 0b8c2a64b36f..954c891e5aee 100644 --- a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi @@ -168,7 +168,6 @@ mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; }; diff --git a/arch/arm/boot/dts/marvell/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi index ddc49547d786..99778b4b7e7b 100644 --- a/arch/arm/boot/dts/marvell/armada-375.dtsi +++ b/arch/arm/boot/dts/marvell/armada-375.dtsi @@ -376,7 +376,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 446861b6b17b..1181b13deabc 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -408,7 +408,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; diff --git a/arch/arm/boot/dts/marvell/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi index 9d1cac49c022..6d05835efb42 100644 --- a/arch/arm/boot/dts/marvell/armada-39x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-39x.dtsi @@ -268,7 +268,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; -- cgit v1.2.3-58-ga151 From f7e642bcd622e1fccd150eae5b894ad3fe38930e Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 24 Jun 2024 16:53:55 +0200 Subject: dt-bindings: interrupt-controller: convert marvell,mpic binding to YAML MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert the marvell,mpic device-tree binding to YAML. Add myself as maintainer. Signed-off-by: Marek Behún Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240624145355.8034-3-kabel@kernel.org Signed-off-by: Arnd Bergmann --- .../marvell,armada-370-xp-mpic.txt | 38 ------------- .../interrupt-controller/marvell,mpic.yaml | 63 ++++++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 64 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt deleted file mode 100644 index 5fc03134a999..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +++ /dev/null @@ -1,38 +0,0 @@ -Marvell Armada 370, 375, 38x, XP Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible: Should be "marvell,mpic" -- interrupt-controller: Identifies the node as an interrupt controller. -- msi-controller: Identifies the node as an PCI Message Signaled - Interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. Should be 1. - The cell is the IRQ number - -- reg: Should contain PMIC registers location and length. First pair - for the main interrupt registers, second pair for the per-CPU - interrupt registers. For this last pair, to be compliant with SMP - support, the "virtual" must be use (For the record, these registers - automatically map to the interrupt controller registers of the - current CPU) - -Optional properties: - -- interrupts: If defined, then it indicates that this MPIC is - connected as a slave to another interrupt controller. This is - typically the case on Armada 375 and Armada 38x, where the MPIC is - connected as a slave to the Cortex-A9 GIC. The provided interrupt - indicate to which GIC interrupt the MPIC output is connected. - -Example: - - mpic: interrupt-controller@d0020000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - reg = <0xd0020a00 0x1d0>, - <0xd0021070 0x58>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml new file mode 100644 index 000000000000..616a41c87352 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller + +maintainers: + - Marek Behún + +description: | + The top-level interrupt controller on Marvell Armada 370 and XP. On these + platforms it also provides inter-processor interrupts. + + On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC. + + Provides MSI handling for the PCIe controllers. + +properties: + compatible: + const: marvell,mpic + + reg: + items: + - description: main registers + - description: per-cpu registers + + interrupts: + items: + - description: | + Parent interrupt on platforms where MPIC is not the top-level + interrupt controller. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + msi-controller: true + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - msi-controller + +additionalProperties: false + +examples: + - | + #include + #include + + interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + msi-controller; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2ca8f35dfe03..17f1ea1eacf3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2211,6 +2211,7 @@ F: Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm F: Documentation/devicetree/bindings/bus/moxtet.txt F: Documentation/devicetree/bindings/firmware/cznic,turris-mox-rwtm.txt F: Documentation/devicetree/bindings/gpio/gpio-moxtet.txt +F: Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml F: Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt F: drivers/bus/moxtet.c -- cgit v1.2.3-58-ga151 From b1a4e71d4fc463934b6b00cc3460f93b4816816d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 27 Jun 2024 21:57:38 +0200 Subject: arm: dts: arm: Drop redundant fixed-factor clocks There's not much reason to have multiple fixed-factor-clock instances which are all the same factor and clock input. Drop the nodes, but keep the labels to minimize the changes and keep some distinction of the different clocks. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/20240528191536.1444649-1-robh@kernel.org Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20240627-arm-dts-fixes-v1-1-40a2cb7d344b@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/arm/arm-realview-eb.dtsi | 42 +-------------------------- arch/arm/boot/dts/arm/arm-realview-pb1176.dts | 34 +--------------------- arch/arm/boot/dts/arm/arm-realview-pb11mp.dts | 42 +-------------------------- arch/arm/boot/dts/arm/arm-realview-pbx.dtsi | 42 +-------------------------- arch/arm/boot/dts/arm/integratorap.dts | 10 +------ arch/arm/boot/dts/arm/mps2.dtsi | 34 +--------------------- 6 files changed, 6 insertions(+), 198 deletions(-) diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi index fbb2258b451f..ed3ed5a4f0f7 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -53,7 +53,7 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -67,46 +67,6 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ pclk: pclk@0 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index d99bac02232b..ab2c9b71da69 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -63,7 +63,7 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -77,38 +77,6 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ pclk: pclk@0 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts index 89103d54ecc1..a4c2d96aa5c8 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -163,7 +163,7 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -183,46 +183,6 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ pclk: pclk@0 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi index ec1507c5147c..61dbe041c69b 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -62,7 +62,7 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -82,46 +82,6 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ pclk: pclk@0 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts index d9927d3181dc..27498e0f93f6 100644 --- a/arch/arm/boot/dts/arm/integratorap.dts +++ b/arch/arm/boot/dts/arm/integratorap.dts @@ -57,20 +57,12 @@ }; /* 24 MHz chrystal on the Integrator/AP development board */ - xtal24mhz: xtal24mhz@24M { + xtal24mhz: pclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* The UART clock is 14.74 MHz divided by an ICS525 */ uartclk: uartclk@14.74M { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi index ce308820765b..d930168fbd91 100644 --- a/arch/arm/boot/dts/arm/mps2.dtsi +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -78,7 +78,7 @@ clock-frequency = <75000000>; }; - sysclk: clk-sys { + sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys { compatible = "fixed-factor-clock"; clocks = <&oscclk0>; #clock-cells = <0>; @@ -102,38 +102,6 @@ clock-mult = <1>; }; - spiclcd: clk-cpiclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - spicon: clk-spicon { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2cclcd: clk-i2cclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2caud: clk-i2caud { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - soc { compatible = "simple-bus"; ranges; -- cgit v1.2.3-58-ga151 From 5e4bbe52207c3927dd2690e46bdbef6392d7bde4 Mon Sep 17 00:00:00 2001 From: Vedant Deshpande Date: Thu, 27 Jun 2024 21:53:16 +0000 Subject: arm64: tegra: Restructure Orin NX/Nano device tree The Orin NX and Orin Nano boards share a common carrier board and the module boards for both platforms are very similar. Therefore, restructure the Orin NX/Nano device-tree source files to adhere to a simple hierarchical format. This will help make clear where changes should go, and eliminates redundancy within the files. Previously the carrier board file was independent. However, given that it is so tightly coupled with the module design, it will be more practical to combine files together for a simpler layout. Following changes are made to restructure the device tree source files: 1) Change include hierarchy. Top-level dts includes board dtsi. Board dtsi includes module dtsi. Module dtsi includes SoC dtsi. 2) Data from the top level dts file that is common to both Orin NX and Orin Nano is in tegra234-p3768-0000+p3767.dtsi. 3) Only data that is unique to NX/Nano is present in the top-level dts. Signed-off-by: Vedant Deshpande Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra234-p3768-0000+p3767-0000.dts | 77 +----- .../dts/nvidia/tegra234-p3768-0000+p3767-0005.dts | 31 +-- .../boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi | 270 +++++++++++++++++++++ .../arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi | 244 ------------------- 4 files changed, 272 insertions(+), 350 deletions(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi delete mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts index 1607ee14216f..82a59e33c46c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -1,11 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include -#include - -#include "tegra234-p3767.dtsi" -#include "tegra234-p3768-0000.dtsi" +#include "tegra234-p3768-0000+p3767.dtsi" / { compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234"; @@ -29,83 +25,12 @@ status = "okay"; }; - pwm@32a0000 { - assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; - assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; - status = "okay"; - }; - hda@3510000 { nvidia,model = "NVIDIA Jetson Orin NX HDA"; }; - - padctl@3520000 { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - }; - }; - - pwm-fan { - cooling-levels = <0 88 187 255>; - }; - - vdd_3v3_pcie: regulator-vdd-3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_PCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; }; sound { label = "NVIDIA Jetson Orin NX APE"; }; - - thermal-zones { - tj-thermal { - cooling-maps { - map-active-0 { - cooling-device = <&fan 0 1>; - trip = <&tj_trip_active0>; - }; - - map-active-1 { - cooling-device = <&fan 1 2>; - trip = <&tj_trip_active1>; - }; - - map-active-2 { - cooling-device = <&fan 2 3>; - trip = <&tj_trip_active2>; - }; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts index dc2d4bef1e83..9f5e07012b87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -1,11 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include -#include - -#include "tegra234-p3767.dtsi" -#include "tegra234-p3768-0000.dtsi" +#include "tegra234-p3768-0000+p3767.dtsi" / { compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; @@ -17,32 +13,7 @@ }; }; - pwm-fan { - cooling-levels = <0 88 187 255>; - }; - sound { label = "NVIDIA Jetson Orin Nano APE"; }; - - thermal-zones { - tj-thermal { - cooling-maps { - map-active-0 { - cooling-device = <&fan 0 1>; - trip = <&tj_trip_active0>; - }; - - map-active-1 { - cooling-device = <&fan 1 2>; - trip = <&tj_trip_active1>; - }; - - map-active-2 { - cooling-device = <&fan 2 3>; - trip = <&tj_trip_active2>; - }; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi new file mode 100644 index 000000000000..6d64a24fa251 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +#include "tegra234-p3767.dtsi" + +/ { + + aliases { + serial0 = &tcu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + label = "system"; + vcc-supply = <&vdd_1v8_sys>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + serial@31d0000 { + current-speed = <115200>; + status = "okay"; + }; + + pwm@32a0000 { + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + status = "okay"; + }; + + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + }; + + ports { + /* recovery port */ + usb2-0 { + mode = "otg"; + vbus-supply = <&vdd_5v0_sys>; + status = "okay"; + usb-role-switch; + }; + + /* hub */ + usb2-1 { + mode = "host"; + vbus-supply = <&vdd_1v1_hub>; + status = "okay"; + }; + + /* M.2 Key-E */ + usb2-2 { + mode = "host"; + vbus-supply = <&vdd_5v0_sys>; + status = "okay"; + }; + + /* hub */ + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + /* J5 */ + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-0"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", + "usb3-1"; + }; + + /* C8 - Ethernet */ + pcie@140a0000 { + status = "okay"; + + num-lanes = <2>; + + phys = <&p2u_gbe_2>, <&p2u_gbe_3>; + phy-names = "p2u-0", "p2u-1"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + }; + + /* C1 - M.2 Key-E */ + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + /* C4 - M.2 Key-M */ + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + /* C7 - M.2 Key-M */ + pcie@141e0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + #cooling-cells = <2>; + cooling-levels = <0 88 187 255>; + }; + + vdd_1v8_sys: regulator-vdd-1v8-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v1_hub: regulator-vdd-1v1-hub { + compatible = "regulator-fixed"; + regulator-name = "VDD_AV10_HUB"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vdd_5v0_sys>; + regulator-always-on; + }; + + vdd_3v3_pcie: regulator-vdd-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serial { + status = "okay"; + }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + + map-active-2 { + cooling-device = <&fan 2 3>; + trip = <&tj_trip_active2>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi deleted file mode 100644 index 5d0298b6c30d..000000000000 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - compatible = "nvidia,p3768-0000"; - - aliases { - serial0 = &tcu; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - bus@0 { - i2c@3160000 { - status = "okay"; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8_sys>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - serial@31d0000 { - current-speed = <115200>; - status = "okay"; - }; - - pwm@32a0000 { - assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; - assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; - status = "okay"; - }; - - padctl@3520000 { - status = "okay"; - - pads { - usb2 { - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - usb3 { - lanes { - usb3-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb3-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* recovery port */ - usb2-0 { - mode = "otg"; - vbus-supply = <&vdd_5v0_sys>; - status = "okay"; - usb-role-switch; - }; - - /* hub */ - usb2-1 { - mode = "host"; - vbus-supply = <&vdd_1v1_hub>; - status = "okay"; - }; - - /* M.2 Key-E */ - usb2-2 { - mode = "host"; - vbus-supply = <&vdd_5v0_sys>; - status = "okay"; - }; - - /* hub */ - usb3-0 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - - /* J5 */ - usb3-1 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - }; - }; - - usb@3550000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; - phy-names = "usb2-0", "usb3-0"; - }; - - usb@3610000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", - "usb3-1"; - }; - - /* C8 - Ethernet */ - pcie@140a0000 { - status = "okay"; - - num-lanes = <2>; - - phys = <&p2u_gbe_2>, <&p2u_gbe_3>; - phy-names = "p2u-0", "p2u-1"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - }; - - /* C1 - M.2 Key-E */ - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; - }; - - /* C4 - M.2 Key-M */ - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, - <&p2u_hsio_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - /* C7 - M.2 Key-M */ - pcie@141e0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_gbe_0>, <&p2u_gbe_1>; - phy-names = "p2u-0", "p2u-1"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - }; - - key-power { - label = "Power"; - gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - #cooling-cells = <2>; - }; - - vdd_1v8_sys: regulator-vdd-1v8-sys { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_SYS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_1v1_hub: regulator-vdd-1v1-hub { - compatible = "regulator-fixed"; - regulator-name = "VDD_AV10_HUB"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vdd_5v0_sys>; - regulator-always-on; - }; - - vdd_3v3_pcie: regulator-vdd-3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_PCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - serial { - status = "okay"; - }; -}; -- cgit v1.2.3-58-ga151 From 8f2cf4442b49365031f62f7d97484989251b0707 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 22 Jun 2024 23:07:30 +0800 Subject: riscv: dts: allwinner: d1s-t113: Add system LDOs Now that the bindings for the system LDOs have been merged, the nodes for the system LDOs can be added. These are used on the ClockworkPi. This was originally part of Samuel's D1 device tree series [1], but was dropped in v5 as the regulator bindings weren't merged at the time. [1] https://lore.kernel.org/linux-sunxi/20221231233851.24923-1-samuel@sholland.org/ Link: https://lore.kernel.org/r/20240622150731.1105901-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 5a9d7f5a75b4..e4175adb028d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -396,6 +396,17 @@ ranges; #address-cells = <1>; #size-cells = <1>; + + regulators@3000150 { + compatible = "allwinner,sun20i-d1-system-ldos"; + reg = <0x3000150 0x4>; + + reg_ldoa: ldoa { + }; + + reg_ldob: ldob { + }; + }; }; dma: dma-controller@3002000 { -- cgit v1.2.3-58-ga151 From 0ce1d34678e5d214746ee4887f9f7714c39e331f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 22 Jun 2024 23:07:31 +0800 Subject: riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible "ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC. The R-01 contains only the CPU, DRAM, and always-on voltage regulation; it does not merit a separate devicetree. The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an X-Powers AXP228 PMIC for managing a Li-ion battery. The DevTerm is a complete system which extends the ClockworkPi mainboard with a MIPI-DSI panel and a pair of expansion boards. These expansion boards provide a fan, a USB keyboard, speakers, and a thermal printer. Acked-by: Palmer Dabbelt Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20240622150731.1105901-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/Makefile | 2 + .../dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts | 252 +++++++++++++++++++++ .../boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts | 36 +++ 3 files changed, 290 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile index 87f70b1af6b4..1c91be38ea16 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts new file mode 100644 index 000000000000..750aec6cf2f2 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model = "ClockworkPi v3.14 (R-01)"; + compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1"; + + aliases { + ethernet0 = &ap6256; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */ + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pb10_pins>; + pinctrl-names = "default"; + status = "okay"; + + axp221: pmic@34 { + compatible = "x-powers,axp228", "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */ + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp221-ac-power-supply"; + }; + + axp_adc: adc { + compatible = "x-powers,axp221-adc"; + #io-channel-cells = <1>; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp221-battery-power-supply"; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + regulators { + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + regulator-name = "sys-3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "sys-1v8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_aldo1: aldo1 { + regulator-name = "aud-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_aldo2: aldo2 { + regulator-name = "disp-3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_aldo3: aldo3 { + regulator-name = "vdd-wifi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* DLDO1 and ELDO1-3 are connected in parallel. */ + reg_dldo1: dldo1 { + regulator-name = "vbat-wifi-a"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* DLDO2-DLDO4 are connected in parallel. */ + reg_dldo2: dldo2 { + regulator-name = "vcc-3v3-ext-a"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dldo3: dldo3 { + regulator-name = "vcc-3v3-ext-b"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dldo4: dldo4 { + regulator-name = "vcc-3v3-ext-c"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo1: eldo1 { + regulator-name = "vbat-wifi-b"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo2: eldo2 { + regulator-name = "vbat-wifi-c"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo3: eldo3 { + regulator-name = "vbat-wifi-d"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp221-usb-power-supply"; + status = "disabled"; + }; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ap6256: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pg-supply = <®_ldoa>; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + interrupt-parent = <&pio>; + interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */ + device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */ + shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */ + max-speed = <1500000>; + vbat-supply = <®_dldo1>; + vddio-supply = <®_aldo3>; + }; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_vbus_power-supply = <&ac_power_supply>; + usb1_vbus-supply = <®_vcc>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts new file mode 100644 index 000000000000..bc5c84f22762 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-clockworkpi-v3.14.dts" + +/ { + model = "Clockwork DevTerm (R-01)"; + compatible = "clockwork,r-01-devterm-v3.14", + "clockwork,r-01-clockworkpi-v3.14", + "allwinner,sun20i-d1"; + + fan { + compatible = "gpio-fan"; + gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */ + gpio-fan,speed-map = <0 0>, + <6000 1>; + #cooling-cells = <2>; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */ + scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */ + #address-cells = <1>; + #size-cells = <0>; + + adc@54 { + compatible = "ti,adc101c"; + reg = <0x54>; + interrupt-parent = <&pio>; + interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */ + vref-supply = <®_dldo2>; + #io-channel-cells = <1>; + }; + }; +}; -- cgit v1.2.3-58-ga151 From c0304446611536a771462f27d98db6775d222b38 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 19 May 2024 20:42:23 +0200 Subject: arm64: dts: apm: Add dedicated syscon poweroff compatibles syscon nodes should always have dedicated compatible for full/accurate hardware description. Link: https://lore.kernel.org/r/20240519-dt-bindings-mfd-syscon-split-v1-8-aaf996e2313a@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-merlin.dts | 2 +- arch/arm64/boot/dts/apm/apm-mustang.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 6e05cf1a3df6..b1160780a2a6 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -32,7 +32,7 @@ }; poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; + compatible = "apm,merlin-poweroff-mailbox", "syscon"; reg = <0x0 0x10548000 0x0 0x30>; }; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index e7644cddf06f..2ef658796746 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -32,7 +32,7 @@ }; poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; + compatible = "apm,mustang-poweroff-mailbox", "syscon"; reg = <0x0 0x10548000 0x0 0x30>; }; -- cgit v1.2.3-58-ga151 From f3acb237a17962349b61eed813f62dddf7aead29 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:38:45 +0200 Subject: arm64: dts: renesas: r8a779h0: Drop "opp-shared" from opp-table-0 The four Cortex-A76 CPU cores on R-Car V4M share their Operating Performance Points (OPP) table, but they have independent clocks. All cores in the cluster can switch DVFS states independently, hence the cluster's OPP table should not have an "opp-shared" property. Fixes: 6bd8b0bc444eae56 ("arm64: dts: renesas: r8a779h0: Add CA76 operating points") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/4e0227ff4388485cdb1ca2855ee6df92754e756e.1718890585.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 6af0d59e275f..25e12aa47487 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -16,7 +16,6 @@ cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; - opp-shared; opp-500000000 { opp-hz = /bits/ 64 <500000000>; -- cgit v1.2.3-58-ga151 From 6fca24a07e1de664c3d0b280043302e0387726df Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:31 +0200 Subject: arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 834c310f541839b6 ("arm64: dts: renesas: Add Renesas R8A779A0 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/671416fb31e3992101c32fe7e46147fe4cd623ae.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index cfa70b441e32..d76347001cc1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2919,6 +2919,9 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From b1c34567aebe300f9a0f70320eaeef0b3d56ffc7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:32 +0200 Subject: arm64: dts: renesas: r8a779f0: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: c62331e8222f8f21 ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/46deba1008f73e4b6864f937642d17f9d4ae7205.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 72cf30341fc4..9629adb47d99 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1324,7 +1324,10 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; ufs30_clk: ufs30-clk { -- cgit v1.2.3-58-ga151 From 6775165fc95052a03acc91e25bc20fcf286910a7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:33 +0200 Subject: arm64: dts: renesas: r8a779g0: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/5eeabbeaea1c5fd518a608f2e8013d260b00fd7e.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 2ee306305d83..c33d8c01e301 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2353,6 +2353,9 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From 4036bae6dfd782d414040e7d714abc525b2e8792 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:34 +0200 Subject: arm64: dts: renesas: r9a07g043u: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/15cc7a7522b1658327a2bd0c4990d0131bbcb4d7.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 165bfcfef3bc..18ef297db933 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -50,7 +50,10 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From ecbc5206a1a0532258144a4703cccf4e70f3fe6c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:35 +0200 Subject: arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 68a45525297b2e9a ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's") Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/21f556eb7e903d5b9f4c96188fd4b6ae0db71856.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index c07ddd8124e6..d3838e5820fc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1334,6 +1334,9 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From 2918674704aad620215c41979a331021fe3f1ec4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:36 +0200 Subject: arm64: dts: renesas: r9a07g054: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC") Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/834244e77e5f407ee6fab1ab5c10c98a8a933085.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 8448afa8be54..1de2e5f0917d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1342,6 +1342,9 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From 10f9badc473d43ebfddd1ddedbcb8eb3f8f3fdd9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:37 +0200 Subject: arm64: dts: renesas: r9a08g045: Add missing hypervisor virtual timer IRQ Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: e20396d65b959a65 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC") Signed-off-by: Geert Uytterhoeven Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea Link: https://lore.kernel.org/884c683fb6c1d1bf7d0d383a8df8f65a0a424dc7.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 2162c247d6de..0d5c47a65e46 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -294,6 +294,9 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -- cgit v1.2.3-58-ga151 From 9d30bd7bdfe373f3e9f7e3e047afd8dd2e585feb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:38 +0200 Subject: ARM: dts: renesas: Add interrupt-names to arch timer nodes Add interrupt-names properties to device nodes that represent ARM architected timers for clarity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/b964e2f916cc23b6272e158c7b24597c971a82a5.1718890849.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7742.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7743.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7744.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7745.dtsi | 1 + arch/arm/boot/dts/renesas/r8a77470.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7790.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7791.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7792.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7793.dtsi | 1 + arch/arm/boot/dts/renesas/r8a7794.dtsi | 1 + arch/arm/boot/dts/renesas/r9a06g032.dtsi | 1 + 12 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index 9a2ae282a46b..85261684b5d5 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -58,6 +58,7 @@ , , ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; tmu0: timer@e61e0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi index d55c344c1cd2..3a5d6b434d09 100644 --- a/arch/arm/boot/dts/renesas/r8a7742.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi @@ -1938,6 +1938,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi index d917c0a971f5..8833898d5557 100644 --- a/arch/arm/boot/dts/renesas/r8a7743.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7743.dtsi @@ -1846,6 +1846,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi index 754859c38a93..c66c1102fb72 100644 --- a/arch/arm/boot/dts/renesas/r8a7744.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7744.dtsi @@ -1832,6 +1832,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi index 168298300490..6ddde364782b 100644 --- a/arch/arm/boot/dts/renesas/r8a7745.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7745.dtsi @@ -1636,6 +1636,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi index 2375438d83c9..a8a12275c98a 100644 --- a/arch/arm/boot/dts/renesas/r8a77470.dtsi +++ b/arch/arm/boot/dts/renesas/r8a77470.dtsi @@ -1061,6 +1061,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index 583b74a9f071..20e4d4c6e748 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -2012,6 +2012,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index de08ceb62230..f9c9e1d8f669 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -1938,6 +1938,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 7defeb8e4cd1..dd3bc32668b7 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -990,5 +990,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index d32a9d5d3faa..24e66ddf37e0 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -1517,6 +1517,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index f37f094cecc8..8e6386a79aea 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -1484,6 +1484,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 466077a8f0ac..7548291c8d7e 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -484,6 +484,7 @@ , , ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; usbphy: usb-phy { -- cgit v1.2.3-58-ga151 From 659c0b4444b24c872ab19e5fa4b96d32043a0a6c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 Jun 2024 15:57:39 +0200 Subject: arm64: dts: renesas: Add interrupt-names to arch timer nodes Add interrupt-names properties to device nodes that represent ARM architected timers for clarity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/e5e2767011322daaebcc8dd6ecfcadc6966042d5.1718890849.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 1 + 14 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index a8a44fe5e83b..1dbf9d56c68d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2853,6 +2853,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 4fff511e994c..10f22c52e79e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2704,6 +2704,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 1ef43d78c3a5..3e2af50ce7c6 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1990,6 +1990,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index be55ae83944c..1eeb4c7b4c4b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2985,6 +2985,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index bea4edd17d53..96f3b5fe7e92 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3473,6 +3473,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 7846fea8e40d..1122c470b72f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -3068,6 +3068,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 58f9286a5ab5..bf1130af7de3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2889,6 +2889,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 692940662d38..f02d1547b881 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2877,6 +2877,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clocks - can be overridden by the board */ diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index d2d3cecc76d5..64fb95b1c89a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1223,5 +1223,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index c0ba110c74d6..0c2b157036e7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1630,5 +1630,6 @@ IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 37063e3f4e1b..233af3081e84 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2157,5 +2157,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 89990dd8ebf7..5f0828a4675b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1476,5 +1476,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 25e12aa47487..706f91a65ac0 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1860,5 +1860,7 @@ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index e008236c3d2d..9a4cbef704c1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -372,5 +372,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; -- cgit v1.2.3-58-ga151 From bd8d7546f9f74a0a70ea79885d5abcf3d66ad5c0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Jun 2024 00:16:24 +0000 Subject: arm64: dts: renesas: r8a779g0: Tidy up sound DT settings R-Car V4H (R8A779G0) supports only 1 AUDIO_CLKOUT and 1 SSI, thus, #clock-cells / #sound-dai-cells are both fixed to zero. (#sound-dai-cells is needed for Simple-Audio-Card, but not needed for Audio-Graph-Card). Fix this up. Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/87frt3kxew.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso | 4 ---- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++------------ 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso index e6f53377ecd9..e6cf304c77ee 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso @@ -155,11 +155,7 @@ pinctrl-0 = <&sound_clk_pins>, <&sound_pins>; pinctrl-names = "default"; - /* Single DAI */ - #sound-dai-cells = <0>; - /* audio_clkout */ - #clock-cells = <0>; clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */ // clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */ diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index c33d8c01e301..53d1d4d8197a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1718,18 +1718,6 @@ }; rcar_sound: sound@ec5a0000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>; - */ compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4"; reg = <0 0xec5a0000 0 0x020>, <0 0xec540000 0 0x1000>, @@ -1739,6 +1727,11 @@ clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; clock-names = "ssiu.0", "ssi.0", "clkin"; + /* #clock-cells is fixed */ + #clock-cells = <0>; + /* #sound-dai-cells is fixed */ + #sound-dai-cells = <0>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 2926>, <&cpg 2927>; reset-names = "ssiu.0", "ssi.0"; -- cgit v1.2.3-58-ga151 From 07e777318911d76fa787fc57f02b595481382291 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Jun 2024 00:16:30 +0000 Subject: arm64: dts: renesas: r8a779h0: R-Car Sound support Add sound support for R-Car V4M. [Kuninori: adjusted to latest upstream kernel] Co-developed-by: Khanh Le Signed-off-by: Khanh Le Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/87ed8nkxeq.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 68 +++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 706f91a65ac0..a03ab2b6a859 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -14,6 +14,13 @@ #address-cells = <2>; #size-cells = <2>; + /* External Audio clock - to be overridden by boards that provide it */ + audio_clkin: audio_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; @@ -1458,6 +1465,67 @@ <&ipmmu_ds0 22>, <&ipmmu_ds0 23>; }; + rcar_sound: sound@ec400000 { + compatible = "renesas,rcar_sound-r8a779h0", "renesas,rcar_sound-gen4"; + reg = <0 0xec400000 0 0x40000>, + <0 0xec540000 0 0x1000>, + <0 0xec541000 0 0x050>, + <0 0xec5a0000 0 0x020>; + reg-names = "sdmc", "ssiu", "ssi", "adg"; + clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; + clock-names = "ssiu.0", "ssi.0", "clkin"; + /* #clock-cells is fixed */ + #clock-cells = <0>; + /* #sound-dai-cells is fixed */ + #sound-dai-cells = <0>; + + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 2926>, <&cpg 2927>; + reset-names = "ssiu.0", "ssi.0"; + status = "disabled"; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&dmac1 0x6e>, <&dmac1 0x6f>; + dma-names = "tx", "rx"; + }; + ssiu01: ssiu-1 { + dmas = <&dmac1 0x6c>, <&dmac1 0x6d>; + dma-names = "tx", "rx"; + }; + ssiu02: ssiu-2 { + dmas = <&dmac1 0x6a>, <&dmac1 0x6b>; + dma-names = "tx", "rx"; + }; + ssiu03: ssiu-3 { + dmas = <&dmac1 0x68>, <&dmac1 0x69>; + dma-names = "tx", "rx"; + }; + ssiu04: ssiu-4 { + dmas = <&dmac1 0x66>, <&dmac1 0x67>; + dma-names = "tx", "rx"; + }; + ssiu05: ssiu-5 { + dmas = <&dmac1 0x64>, <&dmac1 0x65>; + dma-names = "tx", "rx"; + }; + ssiu06: ssiu-6 { + dmas = <&dmac1 0x62>, <&dmac1 0x63>; + dma-names = "tx", "rx"; + }; + ssiu07: ssiu-7 { + dmas = <&dmac1 0x60>, <&dmac1 0x61>; + dma-names = "tx", "rx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + }; + }; + }; + mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779h0", "renesas,rcar-gen4-sdhi"; -- cgit v1.2.3-58-ga151 From 2904244a8c46bdd0fee181df693a495f4628a575 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Fri, 21 Jun 2024 16:22:31 +0800 Subject: riscv: dts: starfive: add PCIe dts configuration for JH7110 Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has one exposed PCIe port, so only the Mars and VisionFive 2 get two enabled. Signed-off-by: Minda Chen Reviewed-by: Hal Feng [conor: squash in star64's single exposed port] Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 62 ++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 7 ++ .../boot/dts/starfive/jh7110-pine64-star64.dts | 4 + .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 ++++++++++++++++++++++ 5 files changed, 167 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 37b4c294ffcc..20bc8c03b821 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -294,6 +294,20 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; +}; + &pwmdac { pinctrl-names = "default"; pinctrl-0 = <&pwmdac_pins>; @@ -473,6 +487,54 @@ }; }; + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + pwmdac_pins: pwmdac-0 { pwmdac-pins { pinmux = ; }; +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; &phy0 { motorcomm,tx-clk-adj-enabled; diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts index 2d41f18e0359..b720cdd15ed6 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -39,6 +39,10 @@ }; }; +&pcie1 { + status = "okay"; +}; + &phy0 { rx-internal-delay-ps = <1900>; tx-internal-delay-ps = <1500>; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 9d70f21c86fc..18f38fc790a4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -32,3 +32,11 @@ &mmc0 { non-removable; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 18047195c600..5ac70759e0ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1214,5 +1214,91 @@ #reset-cells = <1>; power-domains = <&pwrc JH7110_PD_VOUT>; }; + + pcie0: pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts = <57>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; }; -- cgit v1.2.3-58-ga151 From 64c7ea42fcc2b972fc8d108642f4b8fabf0999c3 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 18 Jun 2024 15:45:23 -0500 Subject: arm64: dts: exynos850: Enable TRNG Add True Random Number Generator (TRNG) node to Exynos850 SoC dtsi. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240618204523.9563-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 0706c8534ceb..f1c8b4613cbc 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -416,6 +416,14 @@ interrupts = ; }; + trng: rng@12081400 { + compatible = "samsung,exynos850-trng"; + reg = <0x12081400 0x100>; + clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, + <&cmu_core CLK_GOUT_SSS_PCLK>; + clock-names = "secss", "pclk"; + }; + pinctrl_hsi: pinctrl@13430000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x13430000 0x1000>; -- cgit v1.2.3-58-ga151 From 04515932e52cbe517cf0e933fd22b254034874c4 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 1 Jul 2024 13:30:09 +0200 Subject: ARM: dts: turris-omnia: Add MCU system-controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turris Omnia's MCU provides various features that can be configured over I2C at address 0x2a. Add device-tree node. This does not carry a Fixes tag - we do not want this to get backported to stable kernels for the following reason: U-Boot since v2022.10 inserts a phy-reset-gpio property into the WAN ethernet node pointing to the MCU node if it finds the MCU node with a cznic,turris-omnia-mcu compatible. Thus if this change got backported to a stable kernel, the WAN interface driver would defer probe indefinitely (since it would wait for the turris-omnia-mcu driver which would not be present). Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Reviewed-by: Andy Shevchenko Reviewed-by: Conor Dooley Acked-by: Bartosz Golaszewski Acked-by: Alexandre Belloni Link: https://lore.kernel.org/r/20240701113010.16447-8-kabel@kernel.org Signed-off-by: Arnd Bergmann --- .../boot/dts/marvell/armada-385-turris-omnia.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 7b755bb4e4e7..59079d63fe27 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -218,7 +218,22 @@ #size-cells = <0>; reg = <0>; - /* STM32F0 command interface at address 0x2a */ + mcu: system-controller@2a { + compatible = "cznic,turris-omnia-mcu"; + reg = <0x2a>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcu_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_NONE>; + + gpio-controller; + #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + }; led-controller@2b { compatible = "cznic,turris-omnia-leds"; @@ -501,6 +516,11 @@ }; &pinctrl { + mcu_pins: mcu-pins { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pcawan_pins: pcawan-pins { marvell,pins = "mpp46"; marvell,function = "gpio"; -- cgit v1.2.3-58-ga151 From ade990619444234d96ee5a79ca6305474c6c687b Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 1 Jul 2024 13:30:10 +0200 Subject: ARM: dts: turris-omnia: Add GPIO key node for front button MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we have the MCU device-tree node, which acts as a GPIO controller, add GPIO key node for the front button. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Reviewed-by: Andy Shevchenko Reviewed-by: Conor Dooley Acked-by: Bartosz Golaszewski Acked-by: Alexandre Belloni Link: https://lore.kernel.org/r/20240701113010.16447-9-kabel@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 59079d63fe27..43202890c959 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -112,6 +112,19 @@ status = "disabled"; }; + gpio-keys { + compatible = "gpio-keys"; + + front-button { + label = "Front Button"; + linux,code = ; + linux,can-disable; + gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>; + /* debouncing is done by the microcontroller */ + debounce-interval = <0>; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; -- cgit v1.2.3-58-ga151 From 04f08ef291d4b8d76f8d198bf2929ad43b96eecf Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Sun, 30 Jun 2024 00:15:35 +0200 Subject: arm/arm64: dts: arm: Use generic clock and regulator nodenames With the recent defining of preferred naming for fixed clock and regulator nodes, convert the Arm Ltd. boards to use the preferred names. In the cases which had a unit-address, warnings about missing "reg" property are fixed. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: Sudeep Holla Link: https://lore.kernel.org/20240528191536.1444649-2-robh@kernel.org Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20240630-arm-dts-fixes-2-v1-1-a32ba57e5b1d@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi | 2 +- arch/arm/boot/dts/arm/arm-realview-eb.dtsi | 6 +++--- arch/arm/boot/dts/arm/arm-realview-pb1176.dts | 4 ++-- arch/arm/boot/dts/arm/arm-realview-pb11mp.dts | 6 +++--- arch/arm/boot/dts/arm/arm-realview-pbx.dtsi | 6 +++--- arch/arm/boot/dts/arm/integratorap-im-pd1.dts | 4 ++-- arch/arm/boot/dts/arm/integratorap.dts | 4 ++-- arch/arm/boot/dts/arm/integratorcp.dts | 14 +++++++------- arch/arm/boot/dts/arm/mps2.dtsi | 14 +++++++------- arch/arm/boot/dts/arm/versatile-ab.dts | 8 ++++---- arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi | 8 ++++---- arch/arm/boot/dts/arm/vexpress-v2m.dtsi | 16 ++++++++-------- arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts | 14 +++++++------- arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts | 22 +++++++++++----------- arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts | 12 ++++++------ arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts | 18 +++++++++--------- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 2 +- arch/arm64/boot/dts/arm/corstone1000.dtsi | 6 +++--- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 6 +++--- arch/arm64/boot/dts/arm/juno-clocks.dtsi | 10 +++++----- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 10 +++++----- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 10 +++++----- .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 6 +++--- 23 files changed, 104 insertions(+), 104 deletions(-) diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi index a79e1d1d30a7..7f62aef9ca8a 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi @@ -22,7 +22,7 @@ / { /* Introduce a fixed regulator for the new ethernet controller */ - veth: fixedregulator@0 { + veth: regulator-veth { compatible = "regulator-fixed"; regulator-name = "veth"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi index ed3ed5a4f0f7..16f784da5a55 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -45,7 +45,7 @@ }; /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { + vmmc: regulator-vmmc { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; @@ -59,7 +59,7 @@ clock-frequency = <24000000>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -68,7 +68,7 @@ }; /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index ab2c9b71da69..b9b10cbd65aa 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -69,7 +69,7 @@ clock-frequency = <24000000>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -78,7 +78,7 @@ }; /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts index a4c2d96aa5c8..ce35748f3d25 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -169,13 +169,13 @@ clock-frequency = <24000000>; }; - refclk32khz: refclk32khz { + refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -184,7 +184,7 @@ }; /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi index 61dbe041c69b..e625403a9456 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -68,13 +68,13 @@ clock-frequency = <24000000>; }; - refclk32khz: refclk32khz { + refclk32khz: clock-32768 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -83,7 +83,7 @@ }; /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts index 367850ea0912..db13e09f2fab 100644 --- a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts @@ -54,7 +54,7 @@ }; /* Also used for the Smart Card Interface SCI */ - impd1_uartclk: clock@1_4 { + impd1_uartclk: clock-uart { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <4>; @@ -64,7 +64,7 @@ }; /* For the SSP the clock is divided by 64 */ - impd1_sspclk: clock@1_64 { + impd1_sspclk: clock-ssp { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <64>; diff --git a/arch/arm/boot/dts/arm/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts index 27498e0f93f6..9b6a1dbaf265 100644 --- a/arch/arm/boot/dts/arm/integratorap.dts +++ b/arch/arm/boot/dts/arm/integratorap.dts @@ -64,7 +64,7 @@ }; /* The UART clock is 14.74 MHz divided by an ICS525 */ - uartclk: uartclk@14.74M { + uartclk: clock-14745600 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; @@ -73,7 +73,7 @@ core-module@10000000 { /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { + cm24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; diff --git a/arch/arm/boot/dts/arm/integratorcp.dts b/arch/arm/boot/dts/arm/integratorcp.dts index c011333eb165..8ad1a8957ace 100644 --- a/arch/arm/boot/dts/arm/integratorcp.dts +++ b/arch/arm/boot/dts/arm/integratorcp.dts @@ -47,14 +47,14 @@ */ /* The codec chrystal operates at 24.576 MHz */ - xtal_codec: xtal24.576@24.576M { + xtal_codec: clock-24576000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24576000>; }; /* The chrystal is divided by 2 by the codec for the AACI bit clock */ - aaci_bitclk: aaci_bitclk@12.288M { + aaci_bitclk: clock-12288000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <2>; @@ -63,21 +63,21 @@ }; /* This is a 25MHz chrystal on the base board */ - xtal25mhz: xtal25mhz@25M { + xtal25mhz: clock-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; }; /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ - uartclk: uartclk@14.74M { + uartclk: clock-14745600 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; }; /* Actually sysclk I think */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; @@ -85,7 +85,7 @@ core-module@10000000 { /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { + cm24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -131,7 +131,7 @@ }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi index d930168fbd91..e240bc8aa605 100644 --- a/arch/arm/boot/dts/arm/mps2.dtsi +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -48,31 +48,31 @@ #address-cells = <1>; #size-cells = <1>; - oscclk0: clk-osc0 { + oscclk0: clock-50000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; - oscclk1: clk-osc1 { + oscclk1: clock-24576000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; }; - oscclk2: clk-osc2 { + oscclk2: clock-25000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - cfgclk: clk-cfg { + cfgclk: clock-5000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <5000000>; }; - spicfgclk: clk-spicfg { + spicfgclk: clock-75000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <75000000>; @@ -86,7 +86,7 @@ clock-mult = <1>; }; - audmclk: clk-audm { + audmclk: clk-12388000 { compatible = "fixed-factor-clock"; clocks = <&oscclk1>; #clock-cells = <0>; @@ -94,7 +94,7 @@ clock-mult = <1>; }; - audsclk: clk-auds { + audsclk: clk-3072000 { compatible = "fixed-factor-clock"; clocks = <&oscclk1>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts index de45aa99e260..6fe6b49f5d8e 100644 --- a/arch/arm/boot/dts/arm/versatile-ab.dts +++ b/arch/arm/boot/dts/arm/versatile-ab.dts @@ -24,7 +24,7 @@ reg = <0x0 0x08000000>; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -142,14 +142,14 @@ }; /* OSC1 on AB, OSC4 on PB */ - osc1: cm_aux_osc@24M { + osc1: clock-osc { #clock-cells = <0>; compatible = "arm,versatile-cm-auxosc"; clocks = <&xtal24mhz>; }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -157,7 +157,7 @@ clocks = <&xtal24mhz>; }; - pclk: pclk@24M { + pclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi index 8af4b77fe655..158b3923eae3 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -20,7 +20,7 @@ #include / { - v2m_fixed_3v3: fixed-regulator-0 { + v2m_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -28,21 +28,21 @@ regulator-always-on; }; - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi index c5e92f6d2fcd..be03f2a8a57a 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi @@ -351,7 +351,7 @@ }; }; - v2m_fixed_3v3: fixed-regulator-0 { + v2m_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -359,21 +359,21 @@ regulator-always-on; }; - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -436,7 +436,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -445,7 +445,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: oscclk1 { + v2m_oscclk1: clock-controller-1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -454,7 +454,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: oscclk2 { + v2m_oscclk2: clock-controller-2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -463,7 +463,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt-vio { + regulator-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts index 679537e17ff5..5a91e936edef 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts @@ -142,7 +142,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* CPU PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -151,7 +151,7 @@ clock-output-names = "oscclk0"; }; - oscclk4 { + clock-controller-4 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -160,7 +160,7 @@ clock-output-names = "oscclk4"; }; - hdlcd_clk: oscclk5 { + hdlcd_clk: clock-controller-5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -169,7 +169,7 @@ clock-output-names = "oscclk5"; }; - smbclk: oscclk6 { + smbclk: clock-controller-6 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -178,7 +178,7 @@ clock-output-names = "oscclk6"; }; - sys_pll: oscclk7 { + sys_pll: clock-controller-7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -187,7 +187,7 @@ clock-output-names = "oscclk7"; }; - oscclk8 { + clock-controller-8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -196,7 +196,7 @@ clock-output-names = "oscclk8"; }; - volt-cores { + regulator-cores { /* CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts index 511e87cc2bc5..6ef23c53d2d8 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts @@ -253,7 +253,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* A15 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -262,7 +262,7 @@ clock-output-names = "oscclk0"; }; - oscclk1 { + clock-controller-1 { /* A15 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -271,7 +271,7 @@ clock-output-names = "oscclk1"; }; - oscclk2 { + clock-controller-2 { /* A7 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -280,7 +280,7 @@ clock-output-names = "oscclk2"; }; - oscclk3 { + clock-controller-3 { /* A7 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -289,7 +289,7 @@ clock-output-names = "oscclk3"; }; - oscclk4 { + clock-controller-4 { /* External AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -298,7 +298,7 @@ clock-output-names = "oscclk4"; }; - hdlcd_clk: oscclk5 { + hdlcd_clk: clock-controller-5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -307,7 +307,7 @@ clock-output-names = "oscclk5"; }; - smbclk: oscclk6 { + smbclk: clock-controller-6 { /* Static memory controller clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -316,7 +316,7 @@ clock-output-names = "oscclk6"; }; - oscclk7 { + clock-controller-7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -325,7 +325,7 @@ clock-output-names = "oscclk7"; }; - oscclk8 { + clock-controller-8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -334,7 +334,7 @@ clock-output-names = "oscclk8"; }; - volt-a15 { + regulator-a15 { /* A15 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -345,7 +345,7 @@ label = "A15 Vcore"; }; - volt-a7 { + regulator-a7 { /* A7 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts index ff1f9a1bcfcf..e3896253f33e 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts @@ -145,7 +145,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - cpu_clk: oscclk0 { + cpu_clk: clock-controller-0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -154,7 +154,7 @@ clock-output-names = "oscclk0"; }; - axi_clk: oscclk1 { + axi_clk: clock-controller-1 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -163,7 +163,7 @@ clock-output-names = "oscclk1"; }; - oscclk2 { + clock-controller-2 { /* DDR2 */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -172,7 +172,7 @@ clock-output-names = "oscclk2"; }; - hdlcd_clk: oscclk3 { + hdlcd_clk: clock-controller-3 { /* HDLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -181,7 +181,7 @@ clock-output-names = "oscclk3"; }; - oscclk4 { + clock-controller-4 { /* Test chip gate configuration */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -190,7 +190,7 @@ clock-output-names = "oscclk4"; }; - smbclk: oscclk5 { + smbclk: clock-controller-5 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts index 8bf35666412b..43a5a4ab6ff0 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts @@ -187,7 +187,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0: extsaxiclk { + oscclk0: clock-controller-0 { /* ACLK clock to the AXI master port on the test chip */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -196,7 +196,7 @@ clock-output-names = "extsaxiclk"; }; - oscclk1: clcdclk { + oscclk1: clock-controller-1 { /* Reference clock for the CLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -205,7 +205,7 @@ clock-output-names = "clcdclk"; }; - smbclk: oscclk2: tcrefclk { + smbclk: oscclk2: clock-controller-2 { /* Reference clock for the test chip internal PLLs */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -214,7 +214,7 @@ clock-output-names = "tcrefclk"; }; - volt-vd10 { + regulator-vd10 { /* Test Chip internal logic voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -223,7 +223,7 @@ label = "VD10"; }; - volt-vd10-s2 { + regulator-vd10-s2 { /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; @@ -232,7 +232,7 @@ label = "VD10_S2"; }; - volt-vd10-s3 { + regulator-vd10-s3 { /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 2>; @@ -241,7 +241,7 @@ label = "VD10_S3"; }; - volt-vcc1v8 { + regulator-vcc1v8 { /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 3>; @@ -250,7 +250,7 @@ label = "VCC1V8"; }; - volt-ddr2vtt { + regulator-ddr2vtt { /* DDR2 SDRAM VTT termination voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 4>; @@ -259,7 +259,7 @@ label = "DDR2VTT"; }; - volt-vcc3v3 { + regulator-vcc3v3 { /* Local board supply for miscellaneous logic external to the Test Chip */ arm,vexpress-sysreg,func = <2 5>; compatible = "arm,vexpress-volt"; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index 901a7fc83307..abd013562995 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -21,7 +21,7 @@ reg-io-width = <2>; }; - vmmc_v3_3d: fixed_v3_3d { + vmmc_v3_3d: regulator-vmmc { compatible = "regulator-fixed"; regulator-name = "vmmc_supply"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 6ad7829f9e28..bb9b96fb5314 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -60,14 +60,14 @@ cache-sets = <1024>; }; - refclk100mhz: refclk100mhz { + refclk100mhz: clock-100000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "apb_pclk"; }; - smbclk: refclk24mhzx2 { + smbclk: clock-48000000 { /* Reference 24MHz clock x 2 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -83,7 +83,7 @@ ; }; - uartclk: uartclk { + uartclk: clock-50000000 { /* UART clock - 50MHz */ compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 7b41537731a6..93f1e7c026b8 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -99,21 +99,21 @@ timeout-sec = <30>; }; - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi index 2870b5eeb198..6d7d88e9591a 100644 --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi +++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi @@ -8,35 +8,35 @@ */ / { /* SoC fixed clocks */ - soc_uartclk: refclk7372800hz { + soc_uartclk: clock-7372800 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <7372800>; clock-output-names = "juno:uartclk"; }; - soc_usb48mhz: clk48mhz { + soc_usb48mhz: clock-48000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; clock-output-names = "clk48mhz"; }; - soc_smc50mhz: clk50mhz { + soc_smc50mhz: clock-50000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; clock-output-names = "smc_clk"; }; - soc_refclk100mhz: refclk100mhz { + soc_refclk100mhz: clock-100000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "apb_pclk"; }; - soc_faxiclk: refclk400mhz { + soc_faxiclk: clock-400000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <400000000>; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 6ca73f41408d..ffa4ba4f1fbc 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -8,35 +8,35 @@ */ / { - mb_clk24mhz: clk24mhz { + mb_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "juno_mb:clk24mhz"; }; - mb_clk25mhz: clk25mhz { + mb_clk25mhz: clock-25000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; clock-output-names = "juno_mb:clk25mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "juno_mb:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "juno_mb:refclk32khz"; }; - mb_fixed_3v3: mcc-sb-3v3 { + mb_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "MCC_SB_3V3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index ba8beef3fe99..66b1b74d27dc 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -8,28 +8,28 @@ * VEMotherBoard.lisa */ / { - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; - v2m_fixed_3v3: v2m-3v3 { + v2m_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -41,7 +41,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - v2m_oscclk1: oscclk1 { + v2m_oscclk1: clock-controller { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 9115c99d0dc0..a0e1fa83eafa 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -111,7 +111,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - smbclk: smclk { + smbclk: clock-controller { /* SMC clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -120,7 +120,7 @@ clock-output-names = "smclk"; }; - volt-vio { + regulator-vio { /* VIO to expansion board above */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -130,7 +130,7 @@ regulator-always-on; }; - volt-12v { + regulator-12v { /* 12V from power connector J6 */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; -- cgit v1.2.3-58-ga151 From ddabb3ce3f908a40d0f154defcf5ed327537d0ff Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Mon, 17 Jun 2024 10:12:29 +0200 Subject: arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314 This adds support for TQMa8MPQL module on MBa8MP-RAS314 board. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 906 +++++++++++++++++++++ 2 files changed, 907 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 06d47aa49813..f04c22b7de72 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -178,6 +178,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts new file mode 100644 index 000000000000..d7fd9d36f824 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2023-2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx8mp-tqma8mpql.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314"; + compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + chassis-type = "embedded"; + + chosen { + stdout-path = &uart4; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + /* X8 */ + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_vcc_12v0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + /* X7 + X8 */ + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvdsdisplay>; + power-supply = <®_vcc_3v3>; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "X9"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x40000000 0 0xB0000000>; + linux,cma-default; + }; + }; + + rfkill { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rfkill>; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tq-mba8mp-ras314"; + audio-cpu = <&sai5>; + audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "", + "", "", "GPIO8", "", + "", "", "", "", + "", "", "GPIO12", "GPIO13", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + wifi-pmic-en-hog { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "WIFI_PMIC_EN"; + }; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25", + "GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2", + "", "", "GPIO1", "GPIO0", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "TEMP_EVENT#", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "HDMI_OC#", "GPIO14", "GPIO15", "GPIO16", + "GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20", + "PCIE_PERST#", "", "", ""; + + pewake-hog { + gpio-hog; + gpios = <25 0>; + input; + line-name = "PCIE_WAKE#"; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>, + <&pinctrl_gpt2_gpio>, <&pinctrl_gpt3_gpio>; + + gpio-line-names = "", "GPIO18", "", "GPIO3", + "GPIO2", "GPIO21", "", "", + "", "", "", "", + "", "", "", "", + "", "", "GPIO5", "GPIO6", + "", "", "GPIO11", "GPIO10", + "GPIO9", "GPIO7", "", "GPIO4", + "", "", "", ""; +}; + +&gpt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpt1>; + status = "disabled"; +}; + +&gpt2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpt2>; + status = "disabled"; +}; + +&gpt3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpt3>; + status = "disabled"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +/* X5 + X6 Camera & Display interface */ +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* X1 ID_I2C */ +&i2c3 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320aic3x04>; + reg = <0x18>; + clock-names = "mclk"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; +}; + +/* X1 I2C */ +&i2c5 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* X1 I2C on GPIO24/GPIO25 */ +&i2c6 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# is connected on MBa8MP-RAS314 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* X1 UART1 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart4 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_vcc_5v0>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_vcc_5v0>; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; +}; + +/* X1 SD card on GPIO22-GPIO27 */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + disable-wp; + bus-width = <4>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = ; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_ecspi3_gpio: ecspi3gpiogrp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = , + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = , + ; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = , + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = ; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = , + /* PCIE_WAKE# */ + , + , + ; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = , + ; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_gpt1: gpt1grp { + fsl,pins = ; + }; + + pinctrl_gpt1_gpio: gpt1gpiogrp { + fsl,pins = ; + }; + + pinctrl_gpt2: gpt2grp { + fsl,pins = ; + }; + + pinctrl_gpt2_gpio: gpt2gpiogrp { + fsl,pins = ; + }; + + pinctrl_gpt3: gpt3grp { + fsl,pins = ; + }; + + pinctrl_gpt3_gpio: gpt3gpiogrp { + fsl,pins = ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = , + ; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = , + ; + }; + + pinctrl_i2c5_gpio: i2c5-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = , + ; + }; + + pinctrl_i2c6_gpio: i2c6-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = , + ; + }; + + pinctrl_lvdsdisplay: lvdsdisplaygrp { + fsl,pins = ; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_pwm3_gpio: pwm3grpiogrp { + fsl,pins = ; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = ; + }; + + pinctrl_pwm4_gpio: pwm4grpiogrp { + fsl,pins = ; + }; + + pinctrl_rfkill: rfkillgrp { + fsl,pins = ; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_tlv320aic3x04: tlv320aic3x04grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart1_gpio: uart1gpiogrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = ; + }; +}; -- cgit v1.2.3-58-ga151 From ee39dbd9a6cbd07a9297693f599e22eb0d34c30c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 17 Jun 2024 14:47:07 -0400 Subject: arm64: dts: imx8dxl-evk: add imx8dxl_cm4, lsio mu5, related memory region Add imx8dxl_cm4, lsio mu5 and related memory region. Reviewed-by: Peng Fan Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 4ac96a058629..1a74ac3ee4ee 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -24,6 +24,19 @@ stdout-path = &lpuart0; }; + imx8dxl-cm4 { + compatible = "fsl,imx8qxp-cm4"; + clocks = <&clk_dummy>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; + fsl,resource-id = ; + fsl,entry-address = <0x34fe0000>; + }; + + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x40000000>; @@ -51,6 +64,37 @@ alloc-ranges = <0 0x98000000 0 0x14000000>; linux,cma-default; }; + + vdev0vring0: memory0@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table: memory-rsc-table@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory-vdevbuffer@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; }; m2_uart1_sel: regulator-m2uart1sel { @@ -505,6 +549,10 @@ status = "okay"; }; +&lsio_mu5 { + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; -- cgit v1.2.3-58-ga151 From 106f68fc9da3d4835070b55a2229d2c54ef5cba1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 17 Jun 2024 17:39:51 -0500 Subject: arm64: dts: imx8mp: Fix pgc_mlmix location The pgc_mlmix shows a power-domain@24, but the reg value is IMX8MP_POWER_DOMAIN_MLMIX which is set to 4. The stuff after the @ symbol should match the stuff referenced by 'reg' so reorder the pgc_mlmix so it to appear as power-domain@4. Fixes: 834464c8504c ("arm64: dts: imx8mp: add mlmix power domain") Fixes: 4bedc468b725 ("arm64: dts: imx8mp: Add NPU Node") Signed-off-by: Adam Ford Reviewed-by: Peng Fan Reviewed-by: Marek Vasut Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 34 +++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f25fc7a8358f..8928a84689a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -789,6 +789,23 @@ reg = ; }; + pgc_mlmix: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, + <800000000>, + <300000000>; + }; + pgc_audio: power-domain@5 { #power-domain-cells = <0>; reg = ; @@ -900,23 +917,6 @@ reg = ; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; - - pgc_mlmix: power-domain@24 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>, - <&clk IMX8MP_CLK_NPU_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, - <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, - <800000000>, - <300000000>; - }; }; }; }; -- cgit v1.2.3-58-ga151 From 3343ab4cc698e8f32b360fed610da5d3c0dbeb50 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 18 Jun 2024 10:21:51 -0700 Subject: arm64: dts: freescale: imx8m*-venice-*: fix gw,gsc dt-schema warnings Fix the dt-schema warnings due to #address-cells/#size-cells being unnecessary when there are no children with reg cells. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 2 -- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 2 -- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 2 -- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 2 -- arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 2 -- 5 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 35ae0faa815b..136cb30df03a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -364,8 +364,6 @@ interrupts = <16 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; adc { compatible = "gw,gsc-adc"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index c11260c26d0b..1d56f2a6c06a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -314,8 +314,6 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; adc { compatible = "gw,gsc-adc"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index db1737bf637d..45470160f98f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -280,8 +280,6 @@ interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; adc { compatible = "gw,gsc-adc"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 05489a31e7fd..ef951bc9f0dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -330,8 +330,6 @@ interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; adc { compatible = "gw,gsc-adc"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 0b1fa04f1d67..72004ab6bda5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -312,8 +312,6 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; adc { compatible = "gw,gsc-adc"; -- cgit v1.2.3-58-ga151 From 2a93ce597484a927b14bcb611ffc6b0b47af2683 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 18 Jun 2024 13:02:54 -0700 Subject: arm64: dts: imx8mm-venice-gw700x: add support for PHY LED's The GW700x SoM has an onboard DP83867 RGMII GbE PHY that drives two LED's (LED1 and LED2, skipping LED0). Add the appropriate dt bindings to allow these PHY LED's to be controlled via a netdev trigger. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index de7f67a4ff2a..36803b038cd5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include / { @@ -113,6 +114,25 @@ ti,tx-internal-delay = ; tx-fifo-depth = ; rx-fifo-depth = ; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From fdf7a55d3f499adfb7b66f644fc1ddca83ffeaca Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 18 Jun 2024 13:05:52 -0700 Subject: arm64: dts: imx8mp-venice-gw702x: add support for PHY LED's The GW702x SoM has an onboard DP83867 RGMII GbE PHY that drives two LED's (LED1 and LED2, skipping LED0). Add the appropriate dt bindings to allow these PHY LED's to be controlled via a netdev trigger. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi index 560c68e4da6d..6c75a5ecf56b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include / { @@ -102,6 +103,25 @@ ti,tx-internal-delay = ; tx-fifo-depth = ; rx-fifo-depth = ; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 9f05b20ceedee5df991db1681d9806935b1fd099 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 18 Jun 2024 13:09:01 -0700 Subject: arm64: dts: imx8mp-venice-gw74xx: add DP83867 configuration The GW7400 has an onboard DP83867 RGMII GbE PHY: - add RGMII delay and FIFO configuration - add LED configuration required to use them via netdev trigger: two LED's (LED1 and LED2, skipping LED0). Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-venice-gw74xx.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index a77e9a44d9fa..d765b7972841 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "imx8mp.dtsi" @@ -225,6 +226,29 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; }; -- cgit v1.2.3-58-ga151 From 2f8405fb077bcb8e98c8cd87c2a0a238b15d8da8 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 19 Jun 2024 05:10:44 -0500 Subject: arm64: dts: imx8mp: Fix pgc vpu locations The various pgv_vpu nodes have a mismatch between the value after the @ symbol and what is referenced by 'reg' so reorder the nodes to align. Fixes: df680992dd62 ("arm64: dts: imx8mp: add vpu pgc nodes") Suggested-by: Alexander Stein Signed-off-by: Adam Ford Reviewd-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 55 ++++++++++++++++--------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8928a84689a8..5e7360218d20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -838,6 +838,12 @@ assigned-clock-rates = <800000000>, <400000000>; }; + pgc_vpumix: power-domain@8 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; + }; + pgc_gpu3d: power-domain@9 { #power-domain-cells = <0>; reg = ; @@ -853,6 +859,28 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_vpu_g1: power-domain@11 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + pgc_vpu_g2: power-domain@12 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + + }; + + pgc_vpu_vc8000e: power-domain@13 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = ; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + pgc_hdmimix: power-domain@14 { #power-domain-cells = <0>; reg = ; @@ -890,33 +918,6 @@ reg = ; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; }; - - pgc_vpumix: power-domain@19 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MP_CLK_VPU_ROOT>; - }; - - pgc_vpu_g1: power-domain@20 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = ; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; - }; - - pgc_vpu_g2: power-domain@21 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = ; - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; - }; - - pgc_vpu_vc8000e: power-domain@22 { - #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = ; - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; - }; }; }; }; -- cgit v1.2.3-58-ga151 From 9684ba497754383c47e342b8bc05538f7b57de44 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 20 Jun 2024 10:26:36 +0800 Subject: arm64: dts: imx93-11x11-evk: fix duplicated lpi2c3 labels Move node "rtc@53" to existed "&lpi2c3" and remove redundant "&lpi2c3" label. Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index bd98eff4d685..095bbcb3b3ee 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -178,6 +178,13 @@ }; }; }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; }; &eqos { @@ -401,20 +408,6 @@ }; }; -&lpi2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c3>; - status = "okay"; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupt-parent = <&pcal6524>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; -}; - &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < -- cgit v1.2.3-58-ga151 From 16d41d987f32a41b6fa2d47ae4b0239e8abbaabc Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 20 Jun 2024 10:26:37 +0800 Subject: arm64: dts: imx93-11x11-evk: reorder lpi2c2, lpi2c3, mu1 and mu2 label Reorder lpi2c2, lpi2c3, mu1 and mu2 label in alphabetical order. Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 296 +++++++++++----------- 1 file changed, 148 insertions(+), 148 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 095bbcb3b3ee..a15987f49e8d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -97,12 +97,150 @@ status = "okay"; }; -&mu1 { +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + eee-broken-1000t; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; }; -&mu2 { +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &lpi2c3 { @@ -187,54 +325,6 @@ }; }; -&eqos { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - eee-broken-1000t; - reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - }; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - }; - }; -}; - &lpuart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -247,6 +337,14 @@ status = "okay"; }; +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -310,104 +408,6 @@ status = "okay"; }; -&lpi2c2 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-1 = <&pinctrl_lpi2c2>; - status = "okay"; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6524>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <670000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <840000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < -- cgit v1.2.3-58-ga151 From 227b474081d35da895948d79758c89aeef7d6beb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 24 Jun 2024 14:55:29 -0400 Subject: arm64: dts: fsl-ls1043a-rdb: use common spi-cs-setup(hold)-delay-ns Use SPI common properties 'spi-cs-setup-delay-ns' and 'spi-cs-hold-delay-ns', mark private properties 'fsl,spi-cs-sck-delay' and 'fsl,spi-sck-cs-delay' as deprecated. Signed-off-by: Frank Li Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index 26f8540cb101..de23f5ebaafd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -104,6 +104,12 @@ compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + /* + * Standard CS timing properties replace the deprecated vendor + * variants below. + */ + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <100>; fsl,spi-cs-sck-delay = <100>; fsl,spi-sck-cs-delay = <100>; }; @@ -112,6 +118,12 @@ compatible = "maxim,ds26522"; reg = <2>; spi-max-frequency = <2000000>; + /* + * Standard CS timing properties replace the deprecated vendor + * variants below. + */ + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <50>; fsl,spi-cs-sck-delay = <100>; fsl,spi-sck-cs-delay = <50>; }; @@ -120,6 +132,12 @@ compatible = "maxim,ds26522"; reg = <3>; spi-max-frequency = <2000000>; + /* + * Standard CS timing properties replace the deprecated vendor + * variants below. + */ + spi-cs-setup-delay-ns = <100>; + spi-cs-hold-delay-ns = <50>; fsl,spi-cs-sck-delay = <100>; fsl,spi-sck-cs-delay = <50>; }; -- cgit v1.2.3-58-ga151 From d9c34491268880775334032aa48c3157eef7ed1b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Jun 2024 12:16:19 -0400 Subject: arm64: dts: imx95: add '#address-cells' and '#size-cells' for all i2c Add '#address-cells' and '#size-cells' for all I2C to avoid duplicate these at every board files. Reviewed-by: Peng Fan Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index f98cec944eee..cc5e829e76cc 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -462,6 +462,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C3>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -472,6 +474,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C4>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -566,6 +570,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C5>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -576,6 +582,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C6>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -586,6 +594,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C7>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -596,6 +606,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C8>, <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -816,6 +828,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C1>, <&scmi_clk IMX95_CLK_BUSAON>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -826,6 +840,8 @@ clocks = <&scmi_clk IMX95_CLK_LPI2C2>, <&scmi_clk IMX95_CLK_BUSAON>; clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 3b1d5deb29ffdc2f4fa7db1e25f7ca3af9d375a2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Jun 2024 12:16:20 -0400 Subject: arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support Add pcie[0,1] and pcie-ep[0,1] support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 134 +++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index cc5e829e76cc..1bbf9a0468f6 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1054,5 +1054,139 @@ status = "disabled"; }; }; + + pcie0: pcie@4c300000 { + compatible = "fsl,imx95-pcie"; + reg = <0 0x4c300000 0 0x10000>, + <0 0x60100000 0 0xfe00000>, + <0 0x4c360000 0 0x10000>, + <0 0x4c340000 0 0x2000>; + reg-names = "dbi", "config", "atu", "app"; + ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, + <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + fsl,max-link-speed = <3>; + status = "disabled"; + }; + + pcie0_ep: pcie-ep@4c300000 { + compatible = "fsl,imx95-pcie-ep"; + reg = <0 0x4c300000 0 0x10000>, + <0 0x4c360000 0 0x1000>, + <0 0x4c320000 0 0x1000>, + <0 0x4c340000 0 0x2000>, + <0 0x4c370000 0 0x10000>, + <0x9 0 1 0>; + reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + status = "disabled"; + }; + + pcie1: pcie@4c380000 { + compatible = "fsl,imx95-pcie"; + reg = <0 0x4c380000 0 0x10000>, + <8 0x80100000 0 0xfe00000>, + <0 0x4c3e0000 0 0x10000>, + <0 0x4c3c0000 0 0x2000>; + reg-names = "dbi", "config", "atu", "app"; + ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, + <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + fsl,max-link-speed = <3>; + status = "disabled"; + }; + + pcie1_ep: pcie-ep@4c380000 { + compatible = "fsl,imx95-pcie-ep"; + reg = <0 0x4c380000 0 0x10000>, + <0 0x4c3e0000 0 0x1000>, + <0 0x4c3a0000 0 0x1000>, + <0 0x4c3c0000 0 0x2000>, + <0 0x4c3f0000 0 0x10000>, + <0xa 0 1 0>; + reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-58-ga151 From 9ceb5cb24d36613edb0165686dfd6ea465b81f28 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Jun 2024 12:16:21 -0400 Subject: arm64: dts: imx95-19x19-evk: add lpi2c7 and expander gpio pcal6524 Add lpi2c7 and expander gpio pcal6524. Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 675abb70aa18..750a5255b57c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -53,6 +53,26 @@ }; }; +&lpi2c7 { + clock-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + i2c7_pcal6524: i2c7-gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &lpuart1 { /* console */ pinctrl-names = "default"; @@ -95,6 +115,19 @@ }; &scmi_iomuxc { + pinctrl_i2c7_pcal6524: i2c7pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e + IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e -- cgit v1.2.3-58-ga151 From 418ecfca8b115935696121efa0fa018bec496f68 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Jun 2024 12:16:22 -0400 Subject: arm64: dts: imx95-19x19-evk: add PCIe[0,1] support Add PCIe[0,1] and all dependent nodes. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 750a5255b57c..d14a54ab4fd4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -40,6 +40,34 @@ }; }; + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "PCIE_WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_slot_pwr: regulator-slot-pwr { + compatible = "regulator-fixed"; + regulator-name = "PCIe slot-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -84,6 +112,22 @@ status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_slot_pwr>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -128,6 +172,18 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e -- cgit v1.2.3-58-ga151 From 14949fe3f79945957e33dee6de75e3f475ac3308 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 26 Jun 2024 11:05:32 -0300 Subject: arm64: dts: imx8qxp-mek: Pass memory-region to the DSP node According to fsl,dsp.yaml, 'memory-region' is a required property. Pass 'memory-region' to fix the following dt-schema warning: imx8qxp-mek.dtb: dsp@596e8000: 'memory-region' is a required property Signed-off-by: Fabio Estevam Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index cee13e58762c..936ba5ecdcac 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -63,6 +63,7 @@ }; &dsp { + memory-region = <&dsp_reserved>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 45c5e504b34d36b05ced8a4aefa6532e838b0c6a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:21 -0400 Subject: arm64: dts: layerscape: rename node 'timer' as 'rtc' ftm_alarm is rtc. Correct the name as 'rtc' to fix DTB_CHECK warning. timer@29d0000: $nodename:0: 'timer@29d0000' does not match '^rtc(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/rtc/fsl,ls-ftm-alarm.yaml Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index b2658fb759df..ff74addde399 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -563,7 +563,7 @@ #fsl,rcpm-wakeup-cells = <1>; }; - ftm_alarm0: timer@29d0000 { + ftm_alarm0: rtc@29d0000 { compatible = "fsl,ls1012a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 96e7fd0c30c8..3f6526510c85 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1325,7 +1325,7 @@ little-endian; }; - ftm_alarm0: timer@2800000 { + ftm_alarm0: rtc@2800000 { compatible = "fsl,ls1028a-ftm-alarm"; reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; @@ -1333,7 +1333,7 @@ status = "disabled"; }; - ftm_alarm1: timer@2810000 { + ftm_alarm1: rtc@2810000 { compatible = "fsl,ls1028a-ftm-alarm"; reg = <0x0 0x2810000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 2b9d77fe541b..b2c5f45d9ef4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -989,7 +989,7 @@ #fsl,rcpm-wakeup-cells = <1>; }; - ftm_alarm0: timer@29d0000 { + ftm_alarm0: rtc@29d0000 { compatible = "fsl,ls1043a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 30061c80f1cc..f8c9489507e7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -940,7 +940,7 @@ #fsl,rcpm-wakeup-cells = <1>; }; - ftm_alarm0: timer@29d0000 { + ftm_alarm0: rtc@29d0000 { compatible = "fsl,ls1046a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 336a6142d666..d8680ebef137 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -1040,7 +1040,7 @@ little-endian; }; - ftm_alarm0: timer@2800000 { + ftm_alarm0: rtc@2800000 { compatible = "fsl,ls1088a-ftm-alarm"; reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index cfdc3e71aed1..5695b43fba58 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1225,7 +1225,7 @@ little-endian; }; - ftm_alarm0: timer@2800000 { + ftm_alarm0: rtc@2800000 { compatible = "fsl,ls208xa-ftm-alarm"; reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index e60fbe3e51dc..0fd1ae2a73e0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1085,7 +1085,7 @@ little-endian; }; - ftm_alarm0: timer@2800000 { + ftm_alarm0: rtc@2800000 { compatible = "fsl,lx2160a-ftm-alarm"; reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; -- cgit v1.2.3-58-ga151 From b26f63cf5b088253a0baac744fe2f222f8a9c01e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:22 -0400 Subject: arm64: dts: layerscape: add platform special compatible string for gpio Add platform special compatible string for all gpio controller to fix below warning. gpio@2300000: compatible: 'oneOf' conditional failed, one must be fixed: ['fsl,qoriq-gpio'] is too short 'fsl,qoriq-gpio' is not one of ['fsl,mpc5121-gpio', 'fsl,mpc5125-gpio', 'fsl,mpc8349-gpio', 'fsl,mpc8572-gpio', 'fsl,mpc8610-gpio', 'fsl,pq3-gpio'] 'fsl,qoriq-gpio' is not one of ['fsl,ls1021a-gpio', 'fsl,ls1028a-gpio', 'fsl,ls1043a-gpio', 'fsl,ls1088a-gpio', 'fsl,ls2080a-gpio'] Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ff74addde399..1331858add94 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -407,7 +407,7 @@ }; gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -417,7 +417,7 @@ }; gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; gpio-controller; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index f8c9489507e7..524b44f42427 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -589,7 +589,7 @@ }; gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -599,7 +599,7 @@ }; gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -609,7 +609,7 @@ }; gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -619,7 +619,7 @@ }; gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; interrupts = ; gpio-controller; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 0fd1ae2a73e0..83431dd5d287 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1027,7 +1027,7 @@ }; gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -1038,7 +1038,7 @@ }; gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -1049,7 +1049,7 @@ }; gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = ; gpio-controller; @@ -1060,7 +1060,7 @@ }; gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; interrupts = ; gpio-controller; -- cgit v1.2.3-58-ga151 From 9ba8e6c55f1c45b8814b3a449260d9798dd6b4d0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:23 -0400 Subject: arm64: dts: fsl-lx2160a: fix #address-cells for pinctrl-single Change #addres-cells to 1 and #size-cells to 0 to align binding doc requiremement. Fix below warning: arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dtb: pinmux@70010012c: #address-cells:0:0: 1 was expected from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 83431dd5d287..26c7ca31e22e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1702,8 +1702,8 @@ pinmux_i2crv: pinmux@70010012c { compatible = "pinctrl-single"; reg = <0x00000007 0x0010012c 0x0 0xc>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; -- cgit v1.2.3-58-ga151 From b4ce7305f804b3ced9e70960cd7b8db47a7a6fd4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:24 -0400 Subject: arm64: dts: fsl-ls1012a: remove property 'snps,host-vbus-glitches' Workaround already applied unconditional at commit a6ba1e453174 ("usb: dwc3: apply snps,host-vbus-glitches workaround unconditionally") Remove it to fix CHECK_DTBS warning: usb@2f00000: Unevaluated properties are not allowed ('snps,host-vbus-glitches' was unexpected) Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 1331858add94..031a5fece5aa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -501,7 +501,6 @@ snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - snps,host-vbus-glitches; }; sata: sata@3200000 { -- cgit v1.2.3-58-ga151 From 6fc79a90a7498330eb4f10ccb1122a7b9762fcc1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:25 -0400 Subject: arm64: dts: layerscape: replace node name 'nor' with 'flash' Replace node name 'nor' with 'flash' to fix below CHECK_DTBS warning. nor@0,0: $nodename:0: 'nor@0,0' does not match '^(flash|.*sram|nand)(@.*)?$' Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index dda27ed7aaf2..11b1356e95d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -64,7 +64,7 @@ 0x2 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; big-endian; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index de23f5ebaafd..c4532c809f0a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -71,7 +71,7 @@ 0x1 0x0 0x0 0x7e800000 0x00010000 0x2 0x0 0x0 0x7fb00000 0x00000100>; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index 3b0ed9305f2b..e5296e51f656 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -151,7 +151,7 @@ 0x2 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; big-endian; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts index aa52ff73ff9e..d238a8440a81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts @@ -113,7 +113,7 @@ 3 0 0x5 0x20000000 0x00010000>; status = "okay"; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index e2c94da6d6e8..9178cd61c786 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -43,7 +43,7 @@ 0x2 0x0 0x5 0x30000000 0x00010000 0x3 0x0 0x5 0x20000000 0x00010000>; - nor@0,0 { + flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 537cecb13dd0..69cd05a30b85 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -21,7 +21,7 @@ 0x2 0x0 0x5 0x30000000 0x00010000 0x3 0x0 0x5 0x20000000 0x00010000>; - nor@0,0 { + flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; -- cgit v1.2.3-58-ga151 From 04b22497dfafde06bf007cbd226ce27ab187b4a2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:26 -0400 Subject: arm64: dts: layerscape: remove compatible string 'fsl,fman-xmdio' for fman3 Fman3 should use 'fsl,fman-memac-mdio'. 'fsl,fman-xmdio' is for fman2. Fix below CHECK_DTBS warning. fman@1a00000: mdio@eb000:compatible: ['fsl,fman-memac-mdio', 'fsl,fman-xmdio'] is too long Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 2 +- arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 4 ++-- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi index dbd2fc3ba790..65f7b5a50eb5 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi @@ -32,7 +32,7 @@ fman@1a00000 { mdio@f1000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xf1000 0x1000>; pcsphy6: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi index 6fc5d2560057..3f70482c98c3 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi @@ -32,7 +32,7 @@ fman@1a00000 { mdio@f3000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xf3000 0x1000>; pcsphy7: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi index 4e02276fcf99..78841c1f3252 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@e1000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xe1000 0x1000>; pcsphy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi index 0312fa43fa77..1f43fa666222 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@e3000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xe3000 0x1000>; pcsphy1: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi index af2df07971dd..de0aa017701d 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@e5000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xe5000 0x1000>; pcsphy2: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi index 4ac98dc8b227..6904aa5d8e54 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@e7000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xe7000 0x1000>; pcsphy3: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi index bd932d8b0160..a3d29d470297 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@e9000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xe9000 0x1000>; pcsphy4: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi index 7de1c5203f3e..01b78c0463a7 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi @@ -31,7 +31,7 @@ fman@1a00000 { mdio@eb000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xeb000 0x1000>; pcsphy5: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi index ae1c2abaaf36..b0390b711fef 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi @@ -67,14 +67,14 @@ fman0: fman@1a00000 { mdio0: mdio@fc000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xfc000 0x1000>; }; xmdio0: mdio@fd000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + compatible = "fsl,fman-memac-mdio"; reg = <0xfd000 0x1000>; }; }; -- cgit v1.2.3-58-ga151 From 327d71aa59bdf8400f909e35183f74f2c7cfa660 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:27 -0400 Subject: arm64: dts: layerscape: add #dma-cells for qdma Add #dma-cells for qdma to fix below warning. dma-controller@8380000: '#dma-cells' is a required property Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 3f6526510c85..6b6e3ee950e5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -828,6 +828,7 @@ ; interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1", "qdma-queue2", "qdma-queue3"; + #dma-cells = <1>; dma-channels = <8>; block-number = <1>; block-offset = <0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index b2c5f45d9ef4..b9303145bc2c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -974,6 +974,7 @@ ; interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1", "qdma-queue2", "qdma-queue3"; + #dma-cells = <1>; dma-channels = <8>; block-number = <1>; block-offset = <0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 524b44f42427..801c5b77d608 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -925,6 +925,7 @@ ; interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1", "qdma-queue2", "qdma-queue3"; + #dma-cells = <1>; dma-channels = <8>; block-number = <1>; block-offset = <0x10000>; -- cgit v1.2.3-58-ga151 From cfd95678a6fc814f16c16e6dd62934d5c3528ab5 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:28 -0400 Subject: arm64: dts: layerscape: rename node name "wdt" to "watchdog" Rename node name "wdt" to "watchdog" to fix below warning: arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dtb: wdt@c000000: $nodename:0: 'wdt@c000000' does not match '^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$ Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index d8680ebef137..8ce4b6aae79d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -880,7 +880,7 @@ }; }; - cluster1_core0_watchdog: wdt@c000000 { + cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -890,7 +890,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core1_watchdog: wdt@c010000 { + cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -900,7 +900,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core2_watchdog: wdt@c020000 { + cluster1_core2_watchdog: watchdog@c020000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -910,7 +910,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core3_watchdog: wdt@c030000 { + cluster1_core3_watchdog: watchdog@c030000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -920,7 +920,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core0_watchdog: wdt@c100000 { + cluster2_core0_watchdog: watchdog@c100000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -930,7 +930,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core1_watchdog: wdt@c110000 { + cluster2_core1_watchdog: watchdog@c110000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -940,7 +940,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core2_watchdog: wdt@c120000 { + cluster2_core2_watchdog: watchdog@c120000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -950,7 +950,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core3_watchdog: wdt@c130000 { + cluster2_core3_watchdog: watchdog@c130000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 5695b43fba58..bde89de2576e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -389,7 +389,7 @@ interrupts = ; }; - cluster1_core0_watchdog: wdt@c000000 { + cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -399,7 +399,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core1_watchdog: wdt@c010000 { + cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -409,7 +409,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core0_watchdog: wdt@c100000 { + cluster2_core0_watchdog: watchdog@c100000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -419,7 +419,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core1_watchdog: wdt@c110000 { + cluster2_core1_watchdog: watchdog@c110000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -429,7 +429,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster3_core0_watchdog: wdt@c200000 { + cluster3_core0_watchdog: watchdog@c200000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -439,7 +439,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster3_core1_watchdog: wdt@c210000 { + cluster3_core1_watchdog: watchdog@c210000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -449,7 +449,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster4_core0_watchdog: wdt@c300000 { + cluster4_core0_watchdog: watchdog@c300000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -459,7 +459,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster4_core1_watchdog: wdt@c310000 { + cluster4_core1_watchdog: watchdog@c310000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL -- cgit v1.2.3-58-ga151 From 7dcd914ba1e3caff3ddf2ac1123fd2651a676a17 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:29 -0400 Subject: arm64: dts: layerscape: change pcie interrupt order Change pcie interrupt order to fix below warning. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: pcie@3400000: interrupt-names:0: 'pme' was expected from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dtb: pcie@3400000: interrupt-names:1: 'aer' was expected from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 18 +++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 031a5fece5aa..e61ea7e0737e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -535,9 +535,9 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; + interrupts = , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 801c5b77d608..8ce73a076e77 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -801,9 +801,9 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; + interrupts = , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -840,9 +840,9 @@ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; + interrupts = , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -879,9 +879,9 @@ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; + interrupts = , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; -- cgit v1.2.3-58-ga151 From 8cd751f27ade9edb099a58d4fea4f9c15ca483ba Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:30 -0400 Subject: arm64: dts: layerscape: rename aux_bus to aux-bus Rename aux_bus to aux-bus to fix below CHECK_DTBS warning. arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: aux_bus: $nodename:0: 'aux_bus' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yam Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index b9303145bc2c..5521b89e1d35 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -805,7 +805,7 @@ QORIQ_CLK_PLL_DIV(1)>; }; - aux_bus: aux_bus { + aux_bus: aux-bus { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 8ce73a076e77..f2fd8f984dc3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -715,7 +715,7 @@ QORIQ_CLK_PLL_DIV(2)>; }; - aux_bus: aux_bus { + aux_bus: aux-bus { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; -- cgit v1.2.3-58-ga151 From dcb38239320fd19432b70679a9b0c52af6da6782 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:31 -0400 Subject: arm64: dts: fsl-ls1043a: remove unused clk-name at watchdog node clk-name is undocument property and never used in watchdog driver. Remove it and fix below CHECK_DTB warning. arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: watchdog@2ad0000: Unevaluated properties are not allowed ('big-endian', 'clock-names' were unexpected) Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 5521b89e1d35..31950cc4c6ba 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -783,7 +783,6 @@ interrupts = ; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; - clock-names = "wdog"; big-endian; }; -- cgit v1.2.3-58-ga151 From a1107e7c8823b88b17c8d71e36e325cca66ccd1b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:32 -0400 Subject: arm64: dts: fsl-ls1046a: rename thermal node name Add thermal subfix for thermal node to fix below CHECK_DTB warnings. thermal-zones: '...' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$' Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index f2fd8f984dc3..060b74d3ca58 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -122,7 +122,7 @@ }; thermal-zones { - ddr-controller { + ddr-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; @@ -142,7 +142,7 @@ }; }; - serdes { + serdes-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; @@ -162,7 +162,7 @@ }; }; - fman { + fman-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 2>; @@ -182,7 +182,7 @@ }; }; - core-cluster { + core-cluster-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 3>; @@ -213,7 +213,7 @@ }; }; - sec { + sec-thermal { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 4>; -- cgit v1.2.3-58-ga151 From 8b898acb51da6e13e8b42a269f72097e07ca1cdf Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 26 Jun 2024 16:25:33 -0400 Subject: arm64: dts: layerscape: rename b(q)man-portals to b(q)man-portals-bus Rename b(q)man-portals to b(q)man-portals-bus to fix below CHECK_DTB warnings. arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: bman-portals@508000000: $nodename:0: 'bman-portals@508000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 31950cc4c6ba..17f4e3171120 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -505,11 +505,11 @@ memory-region = <&bman_fbpr>; }; - bportals: bman-portals@508000000 { + bportals: bman-portals-bus@508000000 { ranges = <0x0 0x5 0x08000000 0x8000000>; }; - qportals: qman-portals@500000000 { + qportals: qman-portals-bus@500000000 { ranges = <0x0 0x5 0x00000000 0x8000000>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 060b74d3ca58..200e52622f99 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -409,11 +409,11 @@ }; - qportals: qman-portals@500000000 { + qportals: qman-portals-bus@500000000 { ranges = <0x0 0x5 0x00000000 0x8000000>; }; - bportals: bman-portals@508000000 { + bportals: bman-portals-bus@508000000 { ranges = <0x0 0x5 0x08000000 0x8000000>; }; -- cgit v1.2.3-58-ga151 From 037ee58e0ae5bc48e770c2256dc06d6a82ade428 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 25 Jun 2024 14:11:09 +0200 Subject: arm64: dts: imx8mp: Do not reconfigure Audio PLL2 on DH i.MX8M Plus DHCOM SoM The DH i.MX8M Plus DHCOM SoM uses Audio PLL2 to supply clock to CLKOUT2 output. Those clock are used to supply on-SoM TC9595 DSI-to-(e)DP bridge with RefClk and must not be reconfigured, otherwise the bridge cannot work correctly. Stop reconfiguring Audio PLL2 on this SoM. Fixes: f560da940e32 ("arm64: dts: imx8mp: Initialize audio PLLs from audiomix subsystem") Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index f5115f9e8c47..a1b77d57a906 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -78,6 +78,11 @@ cpu-supply = <&buck2>; }; +&audio_blk_ctrl { + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>; + assigned-clock-rates = <393216000>; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; -- cgit v1.2.3-58-ga151 From a38d101e46080fd32135b139d8eafb778a214f68 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Jun 2024 01:30:09 +0200 Subject: arm64: dts: imx8mp: Update Fast ethernet PHY MDIO addresses to match DH i.MX8MP DHCOM rev.200 The production DH i.MX8MP DHCOM SoM rev.200 uses updated PHY MDIO addresses for the Fast ethernet PHYs. Update the base SoM DT to cater for this change. Prototype rev.100 SoM was never publicly available and was manufactured in limited series, anything currently available is rev.200 or newer, so it is safe to update the DT this way. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index a1b77d57a906..a90e28c07e3f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -110,14 +110,14 @@ #size-cells = <0>; /* Up to one of these two PHYs may be populated. */ - ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio3>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; - reg = <0>; + reg = <1>; reset-assert-us = <1000>; reset-deassert-us = <1000>; reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; @@ -156,14 +156,14 @@ #size-cells = <0>; /* Up to one PHY may be populated. */ - ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio4>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy1>; pinctrl-names = "default"; - reg = <1>; + reg = <2>; reset-assert-us = <1000>; reset-deassert-us = <1000>; reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; -- cgit v1.2.3-58-ga151 From 29c4d4c54cdd7aeb9dceb4274dbbfb9b687f442a Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 27 Jun 2024 17:53:00 +0800 Subject: arm64: dts: imx8mp: Add audio XCVR device node XCVR (Audio Transceiver) is a on-chip functional module found on i.MX8MP. It supports HDMI2.1 eARC, HDMI1.4 ARC and SPDIF. The reset controller is provided by the audio block control driver. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5e7360218d20..603dfe80216f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1541,6 +1541,31 @@ dma-names = "tx"; status = "disabled"; }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + , + /* XCVR IRQ 1 */ + , + /* XCVR PHY - SPDIF wakeup IRQ */ + ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audio_blk_ctrl 0>; + status = "disabled"; + }; }; sdma3: dma-controller@30e00000 { @@ -1569,6 +1594,7 @@ compatible = "fsl,imx8mp-audio-blk-ctrl"; reg = <0x30e20000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_SAI1>, <&clk IMX8MP_CLK_SAI2>, -- cgit v1.2.3-58-ga151 From 710bdbee25893a838c22a217a6be98c78d241ff5 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 27 Jun 2024 17:53:01 +0800 Subject: arm64: dts: imx8mp-evk: Add audio XCVR sound card Add audio XCVR sound card, which supports SPDIF TX & RX, eARC RX, ARC RX functions. HDMI_HPD is shared with the HDMI module so use pinctrl_hog. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c2c708c492c0..a64e8a6c830d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -209,6 +209,19 @@ }; }; + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -748,7 +761,15 @@ status = "okay"; }; +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + pinctrl_audio_pwr_reg: audiopwrreggrp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 @@ -838,6 +859,12 @@ >; }; + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 -- cgit v1.2.3-58-ga151 From 9db27bc55bd8363570c5a259ff4dc77bd6a0b2cd Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 28 Jun 2024 10:07:51 +0100 Subject: arm64: dts: imx8mm-verdin: add TPM device Add TPM device found on Verdin iMX8M Mini PID4 0090 variant. While adding the node, rename `pinctrl_pmic_tpm_ena` to `pinctrl_tpm_spi_cs`. Signed-off-by: Vitor Soares Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index eaf254e44825..5fa395914191 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -228,15 +228,16 @@ pinctrl-0 = <&pinctrl_ecspi2>; }; -/* Verdin CAN_1 (On-module) */ +/* On-module SPI */ &ecspi3 { #address-cells = <1>; #size-cells = <0>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>; status = "okay"; + /* Verdin CAN_1 */ can1: can@0 { compatible = "microchip,mcp251xfd"; clocks = <&clk40m>; @@ -246,6 +247,12 @@ reg = <0>; spi-max-frequency = <8500000>; }; + + verdin_som_tpm: tpm@1 { + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; /* Verdin ETH_1 (On-module PHY) */ @@ -808,8 +815,7 @@ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, - <&pinctrl_pmic_tpm_ena>; + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; pinctrl_can1_int: can1intgrp { fsl,pins = @@ -1111,7 +1117,7 @@ }; /* control signal for optional ATTPM20P or SE050 */ - pinctrl_pmic_tpm_ena: pmictpmenagrp { + pinctrl_tpm_spi_cs: tpmspicsgrp { fsl,pins = ; /* PMIC_TPM_ENA */ }; -- cgit v1.2.3-58-ga151 From feebfe95a6654e991befca7dee45788979fd7f72 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Thu, 18 Apr 2024 12:57:30 +0200 Subject: arm64: dts: k3-am625-verdin: enable nau8822 pll In current configuration, nau8822 codec on development carrier board provides distorted audio output. This happens due to reference clock is fixed to 25MHz and no PLL is enabled. Following is the calculation of deviation error for different frequencies: 44100Hz: fs = 256 (fixed) prescaler = 2 target frequency = 44100 * 256 * 2 = 22579200 deviation = 22579200 vs 25000000 = 9.6832% 48000Hz: fs = 256 (fixed) prescaler = 2 target frequency = 48000 * 256 * 2 = 24576000 deviation = 24576000 vs 25000000 = 1.696% Enabling nau822 PLL via providing mclk-fs property to simple-audio-card configures clocks properly, but also adjusts audio reference clock (mclk), which in case of TI AM62 should be avoided, as it only supports 25MHz output [1][2]. This change enables PLL on nau8822 by providing mclk-fs, and moves away audio reference clock from DAI configuration, which prevents simple-audio-card to adjust it before every playback [3]. [1]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1175479/processor-sdk-am62x-output-audio_ext_refclk0-as-mclk-for-codec-and-mcbsp/4444986#4444986 [2]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188051/am625-audio_ext_refclk1-clock-output---dts-support/4476322#4476322 [3]: sound/soc/generic/simple-card-utils.c#L441 Signed-off-by: Andrejs Cainikovs Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240418105730.120913-1-andrejs.cainikovs@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index 74eec1a1abca..5c1284b802ad 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -14,6 +14,7 @@ simple-audio-card,bitclock-master = <&codec_dai>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "verdin-nau8822"; simple-audio-card,routing = "Headphones", "LHP", @@ -34,7 +35,6 @@ "Line", "Line In"; codec_dai: simple-audio-card,codec { - clocks = <&audio_refclk1>; sound-dai = <&nau8822_1a>; }; @@ -107,6 +107,8 @@ reg = <0x1a>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2s1_mclk>; + clock-names = "mclk"; + clocks = <&audio_refclk1>; #sound-dai-cells = <0>; }; -- cgit v1.2.3-58-ga151 From 60c2f9784d0ea1fad07a28c03a0576274beabdc3 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 25 Jun 2024 13:02:44 +0200 Subject: arm64: dts: ti: k3-am64-tqma64xxl: relicense to GPL-2.0-only OR MIT MIT license was added to the AM64x SoC DTSIs in commit 6248b20e3203 ("arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0"). Apply the same license change to the TQMa64xxL SoM and MBaX4XxL baseboard Device Trees. The copyright year is updated to indicate the license change. Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/20240625110244.9881-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso | 4 ++-- arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso | 4 ++-- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso index 79ed19c6c0e9..c4525024ba5d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Copyright (c) 2022-2024 TQ-Systems GmbH , D-82229 Seefeld, Germany. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso index 32596a84b7ba..82f8a21b6cbf 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Copyright (c) 2022-2024 TQ-Systems GmbH , D-82229 Seefeld, Germany. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 1f4dc5ad1696..c40ad67cee01 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Copyright (c) 2022-2024 TQ-Systems GmbH , D-82229 Seefeld, Germany. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 6c785eff7d2f..828d815d6bdf 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (c) 2022-2023 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Copyright (c) 2022-2024 TQ-Systems GmbH , D-82229 Seefeld, Germany. */ #include "k3-am642.dtsi" -- cgit v1.2.3-58-ga151 From 45a792b5131a02cfa9771b8e1ad9df797b01263a Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Fri, 21 Jun 2024 16:31:43 -0700 Subject: arm64: dts: ti: k3-am6xx-phycore-qspi-nor: Add overlay to enable QSPI NOR Add an overlay to change from the default OSPI NOR to QSPI NOR for all am6xx-phycore-som boards. The EEPROM on am6xx-phycore-soms contains information about the configuration of the SOM. The standard configuration of the SOM has an ospi nor, but if qspi nor is populated, the EEPROM will indicate that change and we can use this overlay to cleanly change to qspi nor. Signed-off-by: Nathan Morrisson Link: https://lore.kernel.org/r/20240621233143.2077941-1-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 +++++ arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso | 15 +++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 1e6fcd1ff7ba..cebc7bade968 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-spi-nor.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-qspi-nor.dtbo # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ @@ -131,6 +132,8 @@ k3-am625-phyboard-lyra-disable-spi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-spi-nor.dtbo k3-am625-phyboard-lyra-gpio-fan-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am62x-phyboard-lyra-gpio-fan.dtbo +k3-am625-phyboard-lyra-qspi-nor-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ + k3-am6xx-phycore-qspi-nor.dtbo k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \ k3-am62x-sk-csi2-imx219.dtbo k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \ @@ -162,6 +165,8 @@ k3-am642-phyboard-electra-disable-rtc-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-rtc.dtbo k3-am642-phyboard-electra-disable-spi-nor-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-disable-spi-nor.dtbo +k3-am642-phyboard-electra-qspi-nor-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am6xx-phycore-qspi-nor.dtbo k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso new file mode 100644 index 000000000000..969dfebcd637 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-qspi-nor.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&serial_flash { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; +}; -- cgit v1.2.3-58-ga151 From 73f1f26e2e4cda4e105476708961f0c3aff4515e Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Sat, 22 Jun 2024 21:48:35 +0530 Subject: arm64: dts: ti: k3-am68-sk-som: Add support for OSPI flash AM68 SK has an OSPI NOR flash on its SOM connected to OSPI0 instance. Enable support for the same. Also, describe the OSPI flash partition information through the device tree, according to the offsets in the bootloader. Signed-off-by: Sinthu Raja Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20240622161835.3610348-1-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 81 ++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 2ebb7daa822f..5c66e0ec6e82 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -131,6 +131,25 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins { + bootph-all; + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + >; + }; +}; + &wkup_pmx2 { wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < @@ -153,6 +172,68 @@ }; }; +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>; -- cgit v1.2.3-58-ga151 From a5cd7067e45c33907afe20c0d1ab5e75b09a1ee2 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 25 Jun 2024 17:03:00 +0530 Subject: arm64: dts: ti: k3-j722s-main: Add audio_refclk node On J722S SoC, the AUDIO_REFCLK1 can be used as input to external peripherals when configured through CTRL_MMR. Add audio_refclk1 node which would be used as system clock for the audio codec TLV320AIC3106. Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20240625113301.217369-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 228c6c89245c..a6b7817d35bc 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -163,6 +163,15 @@ mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ <0x10 0x3>; /* SERDES1 lane0 select */ }; + + audio_refclk1: clock@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 18>; + assigned-clocks = <&k3_clks 157 18>; + assigned-clock-parents = <&k3_clks 157 33>; + #clock-cells = <0>; + }; }; &wkup_conf { -- cgit v1.2.3-58-ga151 From 3a36c535dfd279ff093cc9271f474a99531bea21 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 25 Jun 2024 17:03:01 +0530 Subject: arm64: dts: ti: k3-j722s-evm: Enable analog audio support The audio support on J722S-EVM is using TLV320AIC3106[0] codec connected to McASP1 serializers. - Add the nodes for sound-card, audio codec and McASP1. - Add hog for TRC_MUX_SEL to select between McASP and TRACE signals - Add hogs for GPIO_AUD_RSTn and MCASP1_FET_SEL which is used to switch between HDMI audio and codec audio. - Add pinmux for MCASP1 and AUDIO_EXT_REFCLK1. [0]: Signed-off-by: Jayesh Choudhary Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20240625113301.217369-3-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 109 ++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 253b02f0437d..dd3b5f7039d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -107,6 +107,15 @@ <3300000 0x1>; }; + vsys_io_3v3: regulator-vsys-io-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + vsys_io_1v8: regulator-vsys-io-1v8 { compatible = "regulator-fixed"; regulator-name = "vsys_io_1v8"; @@ -124,6 +133,35 @@ regulator-always-on; regulator-boot-on; }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "J722S-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&audio_refclk1>; + }; + }; }; &main_pmx0 { @@ -210,6 +248,21 @@ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ >; }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */ + J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */ + J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; }; &cpsw3g { @@ -285,6 +338,12 @@ bootph-all; }; +&k3_clks { + /* Configure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -316,6 +375,41 @@ gpios = <5 GPIO_ACTIVE_HIGH>; output-high; }; + + p01_hog: p01-hog { + /* P01 - TRC_MUX_SEL */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "TRC_MUX_SEL"; + }; + + p02_hog: p02-hog { + /* P02 - MCASP1_FET_SEL */ + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MCASP1_FET_SEL"; + }; + + p13_hog: p13-hog { + /* P13 - GPIO_AUD_RSTn */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "GPIO_AUD_RSTn"; + }; + }; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + AVDD-supply = <&vsys_io_3v3>; + IOVDD-supply = <&vsys_io_3v3>; + DRVDD-supply = <&vsys_io_3v3>; + DVDD-supply = <&vsys_io_1v8>; }; }; @@ -457,3 +551,18 @@ phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; -- cgit v1.2.3-58-ga151 From a0286c7bf091ac6bf542a00a305b3ae510242127 Mon Sep 17 00:00:00 2001 From: Nitin Yadav Date: Sat, 22 Jun 2024 14:59:56 +0300 Subject: arm64: dts: ti: k3-am62: Add GPMC and ELM nodes Add GPMC and ELM device tree nodes for AM62 SoC family. Signed-off-by: Nitin Yadav Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-1-caee496eaf42@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 00776a9987c1..e7e7cdc24e3d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -1053,4 +1053,33 @@ status = "disabled"; }; + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x03b000000 0x00 0x400>, + <0x00 0x050000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + elm0: ecc@25010000 { + compatible = "ti,am64-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = ; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 54 0>; + clock-names = "fck"; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index f0781f2bea29..bfb55ca11323 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -68,11 +68,13 @@ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ -- cgit v1.2.3-58-ga151 From e569152274fec9ffdd3cf40d865d2b21ce46f75b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Sat, 22 Jun 2024 14:59:57 +0300 Subject: arm64: dts: ti: am62-lp-sk: Add overlay for NAND expansion card The NAND expansion card (PROC143E1) connects over the User/MCU/PRU Expansion port on the am62-lp-sk EVM. The following pins are shared between McASP1 and GPMC-NAND so both cannot work simultaneously. Pin name McASP1 function GPMC function ======== =============== ============= J17 MCASP1_AXR0 GPMC0_WEN P21 MCASP1_AFSX GPMC0_WAIT0 K17 MCASP1_ACLKX GPMC0_BE0N_CLE K20 MCASP1_AXR2 GPMC0_ADVN_ALE The factory default sets the pins for McASP1 use. (i.e. Resistor Array RA1 installed, RA4 not installed). For NAND use, RA1 has to be removed and RA4 must be installed. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-2-caee496eaf42@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso | 116 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 + 3 files changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index cebc7bade968..c11b0acd2134 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso b/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso new file mode 100644 index 000000000000..173ac60723b6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include +#include +#include "k3-pinctrl.h" + +&mcasp1 { + status = "disabled"; +}; + +&main_pmx0 { + gpmc0_pins_default: gpmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */ + AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */ + AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */ + AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */ + AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */ + AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */ + AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */ + AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */ + AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */ + AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */ + AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */ + AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */ + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */ + >; + }; +}; + +&elm0 { + status = "okay"; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + #address-cells = <2>; + #size-cells = <1>; + + nand@0,0 { + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00200000>; /* 2M */ + }; + partition@200000 { + label = "NAND.tispl"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 2M */ + reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ + }; + partition@600000 { + label = "NAND.u-boot"; + reg = <0x00600000 0x00400000>; /* 4M */ + }; + partition@a00000 { + label = "NAND.u-boot-env"; + reg = <0x00a00000 0x00040000>; /* 256K */ + }; + partition@a40000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00a40000 0x00040000>; /* 256K */ + }; + partition@a80000 { + label = "NAND.file-system"; + reg = <0x00a80000 0x3f580000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 9a17bd3e59c9..8e9fc00a6b3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -228,3 +228,7 @@ &tlv320aic3106 { DVDD-supply = <&buck2_reg>; }; + +&gpmc0 { + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ +}; -- cgit v1.2.3-58-ga151 From 5095ec4aa1ea3d253c09486eaab42fa1a8b48c9a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 26 Jun 2024 15:46:43 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add McASP nodes Add McASP 0-4 instances and keep them disabled because several required properties are missing as they are board specific. Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20240626101645.36764-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 90 ++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index a3e91ff87b4a..7e10be314684 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -2683,4 +2683,94 @@ */ }; }; + + mcasp0: mcasp@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 265 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 265 0>; + assigned-clock-parents = <&k3_clks 265 1>; + power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: mcasp@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 266 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 266 0>; + assigned-clock-parents = <&k3_clks 266 1>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: mcasp@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 267 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 267 0>; + assigned-clock-parents = <&k3_clks 267 1>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp3: mcasp@2b30000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b30000 0x00 0x2000>, + <0x00 0x02b38000 0x00 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 268 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 268 0>; + assigned-clock-parents = <&k3_clks 268 1>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp4: mcasp@2b40000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b40000 0x00 0x2000>, + <0x00 0x02b48000 0x00 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; + dma-names = "tx", "rx"; + clocks = <&k3_clks 269 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 269 0>; + assigned-clock-parents = <&k3_clks 269 1>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; }; -- cgit v1.2.3-58-ga151 From 3ea5142a97346653ed797438495503025062ec02 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 26 Jun 2024 15:46:44 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Add audio_refclk node On J784S4 SoC, the AUDIO_REFCLK1 can be used as input to external peripherals when configured through CTRL_MMR. Add audio_refclk1 node which would be used as system clock for audio codec PCM3168A. Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20240626101645.36764-3-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 7e10be314684..f170f80f00c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -121,6 +121,15 @@ reg = <0x4140 0x18>; #clock-cells = <1>; }; + + audio_refclk1: clock@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 34>; + assigned-clocks = <&k3_clks 157 34>; + assigned-clock-parents = <&k3_clks 157 63>; + #clock-cells = <0>; + }; }; main_ehrpwm0: pwm@3000000 { -- cgit v1.2.3-58-ga151 From 479112c9f5315604b5a96e10efddcd375a0e56a3 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 26 Jun 2024 15:46:45 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Enable analog audio support The audio support on J784S4-EVM is using PCM3168A[0] codec connected to McASP0 serializers. - Add the nodes for sound-card, audio codec, MAIN_I2C3 and McASP0. - Add pinmux for I2C3, McASP0 and AUDIO_EXT_REFCLK1. - Add necessary GPIO hogs to route the MAIN_I2C3 lines and McASP serializer. - Add idle-state as 1 in mux1 to route McASP clock signals. [0]: Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20240626101645.36764-4-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 111 +++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index a4a6efcce362..9338d987180d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -312,6 +312,20 @@ compatible = "gpio-mux"; #mux-state-cells = <1>; mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; + idle-state = <1>; + }; + + codec_audio: sound { + compatible = "ti,j7200-cpb-audio"; + model = "j784s4-cpb"; + + ti,cpb-mcasp = <&mcasp0>; + ti,cpb-codec = <&pcm3168a_1>; + + clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, + <&k3_clks 157 34>, <&k3_clks 157 63>; + clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", + "cpb-codec-scki", "cpb-codec-scki-48000"; }; }; @@ -422,6 +436,28 @@ J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ >; }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ + J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ + >; + }; + + main_mcasp0_pins_default: main-mcasp0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ + J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ + J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ + J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ + >; + }; + + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ + >; + }; }; &wkup_pmx2 { @@ -881,6 +917,14 @@ "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; + + p12-hog { + /* P12 - AUDIO_MUX_SEL */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUDIO_MUX_SEL"; + }; }; exp2: gpio@22 { @@ -896,6 +940,22 @@ "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; + + p13-hog { + /* P13 - CANUART_MUX_SEL0 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CANUART_MUX_SEL0"; + }; + + p15-hog { + /* P15 - CANUART_MUX1_SEL1 */ + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CANUART_MUX1_SEL1"; + }; }; }; @@ -1373,3 +1433,54 @@ phys = <&serdes1_pcie0_link>; phy-names = "pcie-phy"; }; + +&k3_clks { + /* Confiure AUDIO_EXT_REFCLK1 pin as output */ + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcm3168a_1: audio-codec@44 { + compatible = "ti,pcm3168a"; + reg = <0x44>; + #sound-dai-cells = <1>; + reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; + clocks = <&audio_refclk1>; + clock-names = "scki"; + VDD1-supply = <&vsys_3v3>; + VDD2-supply = <&vsys_3v3>; + VCCAD1-supply = <&vsys_5v0>; + VCCAD2-supply = <&vsys_5v0>; + VCCDA1-supply = <&vsys_5v0>; + VCCDA2-supply = <&vsys_5v0>; + }; +}; + +&mcasp0 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp0_pins_default>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + auxclk-fs-ratio = <256>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 1 + 2 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; +}; -- cgit v1.2.3-58-ga151 From fe6a73eee30173695d3a56e30033d7bb1f4c79eb Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Wed, 26 Jun 2024 08:52:41 -0700 Subject: arm64: dts: ti: k3-am62a: Enable AUDIO_REFCLKx On AM62a SoCs the AUDIO_REFCLKx clocks can be used as an input to external peripherals when configured through CTRL_MMR, so add the clock nodes. Based on: Link: https://lore.kernel.org/lkml/20230807202159.13095-2-francesco@dolcini.it/ Signed-off-by: Garrett Giordano Link: https://lore.kernel.org/r/20240626155244.3311436-1-ggiordano@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 08b3aea1d30f..ae9560632fbe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -59,6 +59,24 @@ reg = <0x4130 0x4>; #clock-cells = <1>; }; + + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; + + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 10>; + assigned-clocks = <&k3_clks 157 10>; + assigned-clock-parents = <&k3_clks 157 18>; + #clock-cells = <0>; + }; }; dmss: bus@48000000 { -- cgit v1.2.3-58-ga151 From f1b3adade0459a9a2d9fb0964f975e9541fb1ac9 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Wed, 26 Jun 2024 08:52:42 -0700 Subject: arm64: dts: ti: Add am62x-phyboard-lyra carrier board PHYTECs phyBOARD-Lyra carrier board is able to accomidate multiple SoMs. Refactor k3-am625-phyboard-lyra-rdk.dts into an include file so it can be reused in combination with our phyCORE-AM62Ax SoM. Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240626155244.3311436-2-ggiordano@phytec.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 465 +------------------- arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 475 +++++++++++++++++++++ 2 files changed, 476 insertions(+), 464 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index 6c24e4d39ee8..4fa5efdffcd7 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -7,475 +7,12 @@ * https://www.phytec.com/product/phyboard-am62x */ -#include -#include -#include -#include #include "k3-am625.dtsi" #include "k3-am62-phycore-som.dtsi" +#include "k3-am62x-phyboard-lyra.dtsi" / { compatible = "phytec,am625-phyboard-lyra-rdk", "phytec,am62-phycore-som", "ti,am625"; model = "PHYTEC phyBOARD-Lyra AM625"; - - aliases { - serial2 = &main_uart0; - serial3 = &main_uart1; - mmc1 = &sdhci1; - usb0 = &usb0; - usb1 = &usb1; - ethernet1 = &cpsw_port2; - }; - - can_tc1: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <8000000>; - standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&sii9022_out>; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins_default>; - - key-home { - label = "home"; - linux,code = ; - gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - key-menu { - label = "menu"; - linux,code = ; - gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "phyBOARD-Lyra"; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "External Speaker", "SPOP", - "External Speaker", "SPOM"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp2>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&audio_codec>; - clocks = <&audio_refclk1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; - - led-1 { - gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - led-2 { - gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - }; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_mmc: regulator-vcc-3v3-mmc { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3_MMC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sw: regulator-vcc-3v3-sw { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&main_pmx0 { - audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ - >; - }; - - gpio_keys_pins_default: gpio-keys-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ - >; - }; - - gpio_exp_int_pins_default: gpio-exp-int-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ - >; - }; - - hdmi_int_pins_default: hdmi-int-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ - >; - }; - - main_dss0_pins_default: main-dss0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ - AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ - AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ - AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ - AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ - AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ - AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ - AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ - AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ - AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ - AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ - AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ - AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ - AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ - AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ - AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ - AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ - AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ - AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ - AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - main_mcan0_pins_default: main-mcan0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ - AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ - >; - }; - - main_mcasp2_pins_default: main-mcasp2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */ - AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */ - AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */ - AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ - AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ - AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ - AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ - AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ - AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ - AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ - >; - }; - - main_rgmii2_pins_default: main-rgmii2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ - AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ - AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ - AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ - >; - }; - - main_usb1_pins_default: main-usb1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ - >; - }; - - user_leds_pins_default: user-leds-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ - >; - }; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy3>; -}; - -&cpsw3g_mdio { - cpsw3g_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; - reg = <3>; - ti,clk-output-sel = ; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&main_dss0_pins_default>; - status = "okay"; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* VP2: DPI/HDMI Output */ - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&sii9022_in>; - }; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <100000>; - status = "okay"; - - audio_codec: audio-codec@18 { - pinctrl-names = "default"; - pinctrl-0 = <&audio_ext_refclk1_pins_default>; - - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - ai3x-micbias-vg = <2>; - - AVDD-supply = <&vcc_3v3_sw>; - IOVDD-supply = <&vcc_3v3_sw>; - DRVDD-supply = <&vcc_3v3_sw>; - DVDD-supply = <&vcc_1v8>; - }; - - gpio_exp: gpio-expander@21 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_exp_int_pins_default>; - compatible = "nxp,pcf8574"; - reg = <0x21>; - interrupt-parent = <&main_gpio1>; - interrupts = <49 0>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - gpio-line-names = "", "GPIO1_CAN0_nEN", - "GPIO2_LED2", "GPIO3_LVDS_GPIO", - "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", - "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; - }; - - usb-pd@22 { - compatible = "ti,tps6598x"; - reg = <0x22>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - self-powered; - data-role = "dual"; - power-role = "sink"; - port { - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - }; - }; - - sii9022: bridge-hdmi@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - - interrupt-parent = <&main_gpio0>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_int_pins_default>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sii9022_in: endpoint { - remote-endpoint = <&dpi1_out>; - }; - }; - - port@1 { - reg = <1>; - - sii9022_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x51>; - }; -}; - -&main_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan0_pins_default>; - phys = <&can_tc1>; - status = "okay"; -}; - -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - status = "okay"; -}; - -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; - /* Main UART1 may be used by TIFS firmware */ - status = "okay"; -}; - -&mcasp2 { - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_mcasp2_pins_default>; - - /* MCASP_IIS_MODE */ - op-mode = <0>; - tdm-slots = <2>; - - /* 0: INACTIVE, 1: TX, 2: RX */ - serial-dir = < - 0 0 1 2 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - status = "okay"; -}; - -&sdhci1 { - vmmc-supply = <&vcc_3v3_mmc>; - vqmmc-supply = <&vddshv5_sdio>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - disable-wp; - no-1-8-v; - status = "okay"; -}; - -&usbss0 { - ti,vbus-divider; - status = "okay"; -}; - -&usbss1 { - ti,vbus-divider; - status = "okay"; -}; - -&usb0 { - usb-role-switch; - - port { - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb1_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi new file mode 100644 index 000000000000..e4633af87eb9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + */ + +#include +#include +#include +#include + +/ { + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + ethernet1 = &cpsw_port2; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <8000000>; + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = ; + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = ; + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Lyra"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "External Speaker", "SPOP", + "External Speaker", "SPOM"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp2>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&audio_refclk1>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; + + led-1 { + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_mmc: regulator-vcc-3v3-mmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sw: regulator-vcc-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + + gpio_keys_pins_default: gpio-keys-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; + + gpio_exp_int_pins_default: gpio-exp-int-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + hdmi_int_pins_default: hdmi-int-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ + >; + }; + + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + main_mcasp2_pins_default: main-mcasp2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */ + AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */ + AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + user_leds_pins_default: user-leds-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP2: DPI/HDMI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + audio_codec: audio-codec@18 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; + + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + ai3x-micbias-vg = <2>; + + AVDD-supply = <&vcc_3v3_sw>; + IOVDD-supply = <&vcc_3v3_sw>; + DRVDD-supply = <&vcc_3v3_sw>; + DVDD-supply = <&vcc_1v8>; + }; + + gpio_exp: gpio-expander@21 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_exp_int_pins_default>; + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "", "GPIO1_CAN0_nEN", + "GPIO2_LED2", "GPIO3_LVDS_GPIO", + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; + }; + + usb-pd@22 { + compatible = "ti,tps6598x"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + sii9022: bridge-hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + + interrupt-parent = <&main_gpio0>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_int_pins_default>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 may be used by TIFS firmware */ + status = "okay"; +}; + +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp2_pins_default>; + + /* MCASP_IIS_MODE */ + op-mode = <0>; + tdm-slots = <2>; + + /* 0: INACTIVE, 1: TX, 2: RX */ + serial-dir = < + 0 0 1 2 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + +&sdhci1 { + vmmc-supply = <&vcc_3v3_mmc>; + vqmmc-supply = <&vddshv5_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; + no-1-8-v; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + usb-role-switch; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; -- cgit v1.2.3-58-ga151 From 567c373f441b29414157c00cfff09f1c60e83bf6 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Wed, 26 Jun 2024 08:52:43 -0700 Subject: dt-bindings: arm: ti: Add bindings for PHYTEC AM62Ax based hardware Add devicetree bindings for AM62Ax based phyCORE-AM62A7 SoM and phyBOARD-Lyra RDK. Signed-off-by: Garrett Giordano Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240626155244.3311436-3-ggiordano@phytec.com Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 52b51fd7044e..4d9c5fbb4c26 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra + items: + - const: phytec,am62a7-phyboard-lyra-rdk + - const: phytec,am62a-phycore-som + - const: ti,am62a7 + - description: K3 AM62P5 SoC and Boards items: - enum: -- cgit v1.2.3-58-ga151 From d69383885576954033b537c29c7d259f18e75293 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Wed, 26 Jun 2024 08:52:44 -0700 Subject: arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM62Ax The phyCORE-AM62Ax [1] is a SoM (System on Module) featuring TI's AM62Ax SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62Ax family. A development Kit, called phyBOARD-Lyra [2] is used as a carrier board reference design with a mapper board being used to allow the phyCORE-AM62Ax to fit the phyBOARD-Lyra. Supported features: * Debug UART * SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * GPIO Expander * LEDs * USB * HDMI * USB-C * Audio For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am62a [2] Product page CB: https://www.phytec.com/product/phyboard-am62a Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240626155244.3311436-4-ggiordano@phytec.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 330 +++++++++++++++++++++ .../boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts | 18 ++ 3 files changed, 350 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c11b0acd2134..e20b27ddf901 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb @@ -224,6 +225,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@ +DTC_FLAGS_k3-am62a7-phyboard-lyra-rdk += -@ DTC_FLAGS_k3-am625-sk += -@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi new file mode 100644 index 000000000000..a5aceaa39670 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023 - 2024 PHYTEC America LLC + * Author: Garrett Giordano + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62a + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-AM62Ax"; + compatible = "phytec,am62a-phycore-som", "ti,am62a7"; + + aliases { + ethernet0 = &cpsw_port1; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + spi0 = &ospi0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = ; + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + leds_pins_default: leds-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x034, PIN_OUTPUT, 7) /* (K20) OSPI0_CSN2.GPIO0_13 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ + AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB7) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ + AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ + AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ + AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ + AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ + AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ + AM62AX_IOPAD(0x134, PIN_OUTPUT, 0) /* (Y17) RGMII1_TD0 */ + AM62AX_IOPAD(0x138, PIN_OUTPUT, 0) /* (V16) RGMII1_TD1 */ + AM62AX_IOPAD(0x13c, PIN_OUTPUT, 0) /* (Y16) RGMII1_TD2 */ + AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */ + AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ + AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ + AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ + AM62AX_IOPAD(0x038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */ + AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ + AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ + AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ + AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ + AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ + AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ + AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ + AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&fss { + status = "okay"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_5v0_som>; + buck2-supply = <&vcc_5v0_som>; + buck3-supply = <&vcc_5v0_som>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&vdd_1v8>; + ldo3-supply = <&vcc_5v0_som>; + ldo4-supply = <&vcc_5v0_som>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,power-button; + system-power-controller; + + regulators { + vdd_3v3: buck1 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_1v8: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_lpddr4: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vddshv5_sdio: ldo1 { + regulator-name = "VDDSHV5_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + vddr_core: ldo2 { + regulator-name = "VDDR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdda_1v8: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_2v5: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_gpio_intr { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts new file mode 100644 index 000000000000..3b93409b23e7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a7-phyboard-lyra-rdk.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023 - 2024 PHYTEC America LLC + * Author: Garrett Giordano + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am62a + */ + +#include "k3-am62a7.dtsi" +#include "k3-am62a-phycore-som.dtsi" +#include "k3-am62x-phyboard-lyra.dtsi" + +/ { + compatible = "phytec,am62a7-phyboard-lyra-rdk", + "phytec,am62a-phycore-som", "ti,am62a7"; + model = "PHYTEC phyBOARD-Lyra AM62A7"; +}; -- cgit v1.2.3-58-ga151 From 447f85b70f6553218e0aa7889e8615e4b31c8a2f Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 28 Jun 2024 13:30:38 +0300 Subject: arm: dts: k3-am642-evm-nand: Add bootph-all to NAND related nodes NAND boot would require these nodes to be present at early stage. Ensure that by adding "bootph-all" to relevant nodes. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20240628-am642-evm-nand-bootph-v2-1-387bfa1533a6@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso index dc70b6fbc3d7..f08c0e272b53 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-nand.dtso @@ -13,6 +13,7 @@ &main_pmx0 { gpmc0_pins_default: gpmc0-pins-default { + bootph-all; pinctrl-single,pins = < AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */ AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */ @@ -50,6 +51,7 @@ &main_gpio0 { gpio0-36 { + bootph-all; gpio-hog; gpios = <36 0>; input; @@ -58,6 +60,7 @@ }; &elm0 { + bootph-all; status = "okay"; }; @@ -106,30 +109,37 @@ #size-cells = <1>; partition@0 { + bootph-all; label = "NAND.tiboot3"; reg = <0x00000000 0x00200000>; /* 2M */ }; partition@200000 { + bootph-all; label = "NAND.tispl"; reg = <0x00200000 0x00200000>; /* 2M */ }; partition@400000 { + bootph-all; label = "NAND.tiboot3.backup"; /* 2M */ reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ }; partition@600000 { + bootph-all; label = "NAND.u-boot"; reg = <0x00600000 0x00400000>; /* 4M */ }; partition@a00000 { + bootph-all; label = "NAND.u-boot-env"; reg = <0x00a00000 0x00040000>; /* 256K */ }; partition@a40000 { + bootph-all; label = "NAND.u-boot-env.backup"; reg = <0x00a40000 0x00040000>; /* 256K */ }; partition@a80000 { + bootph-all; label = "NAND.file-system"; reg = <0x00a80000 0x3f580000>; }; -- cgit v1.2.3-58-ga151 From 0ab18cecc806586144ea8f245d15a8da71c332eb Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:12 -0500 Subject: arm64: dts: ti: k3-am65: Add cpsw-mac-efuse node to mcu_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-2-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 8feab9317644..43c6118d2bf0 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -6,13 +6,17 @@ */ &cbass_mcu { - mcu_conf: scm-conf@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; @@ -358,7 +362,7 @@ reg = <1>; ti,mac-only; label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; }; }; -- cgit v1.2.3-58-ga151 From 3128edb3c4a8ad8f7c53d11fc5a21da5d6b597ba Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:13 -0500 Subject: arm64: dts: ti: k3-j7200: Add cpsw-mac-efuse node to mcu_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-3-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fccaabfb1348..5097d192c2b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -164,12 +164,16 @@ ti,timer-pwm; }; - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; + mcu_conf: bus@40f00000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; @@ -420,7 +424,7 @@ reg = <1>; ti,mac-only; label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; }; }; -- cgit v1.2.3-58-ga151 From 1147fa465a82db96f9883477c3351b77a48e457c Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:14 -0500 Subject: arm64: dts: ti: k3-j721e: Add cpsw-mac-efuse node to mcu_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-4-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 9349ae07c046..6b6ef6a30614 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -34,13 +34,17 @@ }; }; - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; @@ -546,7 +550,7 @@ reg = <1>; ti,mac-only; label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; }; }; -- cgit v1.2.3-58-ga151 From 418291e705a9824b09f76858c374b04cf4e7a1d3 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:15 -0500 Subject: arm64: dts: ti: k3-j721s2: Add cpsw-mac-efuse node to mcu_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-5-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5ccb04c7c462..8feb42c89e47 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -139,13 +139,17 @@ ti,interrupt-ranges = <16 960 16>; }; - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; @@ -544,7 +548,7 @@ reg = <1>; ti,mac-only; label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; }; }; -- cgit v1.2.3-58-ga151 From 74e074d22a4161c86b3acc12d6fc1dbd60b177f9 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:16 -0500 Subject: arm64: dts: ti: k3-j784s4: Add cpsw-mac-efuse node to mcu_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-6-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 2e18d91ae92f..f3a6ed1c979d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -145,12 +145,16 @@ status = "reserved"; }; - mcu_conf: syscon@40f00000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; + mcu_conf: bus@40f00000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; @@ -553,7 +557,7 @@ reg = <1>; ti,mac-only; label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; phys = <&phy_gmii_sel 1>; }; }; -- cgit v1.2.3-58-ga151 From 00d20114b515b4697af228cf3c01120ca1335270 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:17 -0500 Subject: arm64: dts: ti: k3-am62a: Add cpsw-mac-efuse node to wkup_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The WKUP system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-7-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index ae9560632fbe..916fcf3cc57d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -739,7 +739,7 @@ label = "port1"; phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&wkup_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; }; cpsw_port2: port@2 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 5c5aca4bb925..f5ac101a04df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -6,9 +6,8 @@ */ &cbass_wakeup { - wkup_conf: syscon@43000000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; + wkup_conf: bus@43000000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x43000000 0x20000>; @@ -18,6 +17,11 @@ reg = <0x14 0x4>; }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; -- cgit v1.2.3-58-ga151 From c870321e4317ea28443e12445f070b35089fd45e Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Fri, 28 Jun 2024 10:15:18 -0500 Subject: arm64: dts: ti: k3-am62: Add cpsw-mac-efuse node to wkup_conf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The WKUP system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property “ti,syscon-efuse” contains a phandle to a syscon region and an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240628151518.40100-8-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index e7e7cdc24e3d..328929c740dc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -735,7 +735,7 @@ label = "port1"; phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&wkup_conf 0x200>; + ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; }; cpsw_port2: port@2 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 66ddf2dc51af..e0afafd532a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -22,6 +22,11 @@ reg = <0x14 0x4>; }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x200 0x8>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; -- cgit v1.2.3-58-ga151 From 50d9981fa12212cdc0110c42db0411209bb5d765 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 27 Jun 2024 11:25:37 -0500 Subject: arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode Introduce a GPIO mux mode macro for easier readability. All K3 devices use mux mode 7 to switch to GPIO mux and this allows the gpio-ranges to be defined for pinctrl-single clearly. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20240627162539.691223-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 4cd2df467d0b..22b8d73cfd32 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -38,6 +38,9 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +/* Default mux configuration for gpio-ranges to use with pinctrl */ +#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -- cgit v1.2.3-58-ga151 From d72d73a44c3c98109764bfb56c329cd628c518cc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 27 Jun 2024 11:25:38 -0500 Subject: arm64: dts: ti: k3-am62p: Add gpio-ranges properties On the AM62P platform we have no single 1:1 relation regarding index of GPIO and pin controller. The GPIOs and pin controller registers have mapping and holes in the map. These have been extracted from the AM62P data sheet. MCU pinctrl definition is shared as it is common between AM62P and J722S, but that is not the case for main domain. Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20240627162539.691223-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index 1d4e5fc8b4e0..e65db6ce02bf 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -12,7 +12,15 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; + pinctrl-single,gpio-range = + <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, + <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, + <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; + + mcu_pmx_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; }; mcu_esm: esm@4100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index f8a7f0cbd327..57383bd2eaeb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -42,10 +42,27 @@ ti,interrupt-ranges = <5 69 35>; }; +&main_pmx0 { + pinctrl-single,gpio-range = + <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 92 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; + + main_pmx0_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + &main_gpio0 { + gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, + <&main_pmx0 70 72 22>; ti,ngpio = <92>; }; &main_gpio1 { + gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>, + <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; ti,ngpio = <52>; }; -- cgit v1.2.3-58-ga151 From 5e5c50964e2e524a7537c97303e9266b11f372d8 Mon Sep 17 00:00:00 2001 From: Jared McArthur Date: Thu, 27 Jun 2024 11:25:39 -0500 Subject: arm64: dts: ti: k3-j722s: Add gpio-ranges properties The AM67A/J722S/TDA4AEN platform is a derivative of AM62P platform and we have no single 1:1 relation regarding index of GPIO and pin controller. The GPIOs and pin controller registers have mapping and holes in the map. These have been extracted from the J722S data sheet. The MCU mapping is carried forward as is with J722S, however the main GPIO block has differences that needs to be accounted for. Mux mode input is selected as it is bi-directional. In case a specific pull type or a specific pin level drive setting is desired, the board device tree files will have to explicitly mux those pins for the GPIO with the desired setting. Ref: J722S Data sheet https://www.ti.com/lit/gpn/tda4aen-q1 Signed-off-by: Jared McArthur Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20240627162539.691223-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index a6b7817d35bc..c797980528ec 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -190,10 +190,28 @@ ti,interrupt-ranges = <7 71 21>; }; +&main_pmx0 { + pinctrl-single,gpio-range = + <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 33 55 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, + <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; + + main_pmx0_range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + &main_gpio0 { + gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, + <&main_pmx0 70 72 17>; ti,ngpio = <87>; }; &main_gpio1 { + gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>, + <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>; ti,ngpio = <73>; }; -- cgit v1.2.3-58-ga151 From 28a950c404679aba602e3311c733a19b7c945ab4 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Wed, 26 Jun 2024 15:45:19 +0530 Subject: arm64: dts: ti: k3-am62p5-sk: fix graph_child_address warnings Fix the following warnings that are thrown when building dtbs with W=1: ../arch/arm64/boot/dts/ti/k3-am62p5-sk.dts:367.10-376.6: Warning (graph_child_address): /bus@f0000/i2c@20000000/usb-power-controller@3f/connector/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary ../arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi:647.22-657.5: Warning (graph_child_address): /bus@f0000/usb@f900000/usb@31000000: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary also defined at ../arch/arm64/boot/dts/ti/k3-am62p5-sk.dts:517.7-528.3 Cc: Roger Quadros Signed-off-by: Dhruva Gole Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20240626101520.1782320-2-d-gole@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index fb980d46e304..ff65955551a3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -364,14 +364,9 @@ self-powered; data-role = "dual"; power-role = "sink"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - usb_con_hs: endpoint { - remote-endpoint = <&usb0_hs_ep>; - }; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; }; }; }; @@ -516,11 +511,8 @@ &usb0 { usb-role-switch; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; + port { usb0_hs_ep: endpoint { remote-endpoint = <&usb_con_hs>; }; -- cgit v1.2.3-58-ga151 From cf645197f045147cd0232c7a205cdfed49590756 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Wed, 26 Jun 2024 15:45:20 +0530 Subject: arm64: dts: ti: k3-am62x-sk-common: Fix graph_child_address warns Fix the following warnings when compiling dtbs with W=1: ../arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi:343.10-353.6: Warning (graph_child_address): /bus@f0000/i2c@20000000/tps6598x@3f/connector/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary ../arch/arm64/boot/dts/ti/k3-am62-main.dtsi:633.22-643.5: Warning (graph_child_address): /bus@f0000/dwc3-usb@f900000/usb@31000000: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary Cc: Roger Quadros Signed-off-by: Dhruva Gole Tested-by: Roger Quadros Link: https://lore.kernel.org/r/20240626101520.1782320-3-d-gole@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index ce7ab338f468..465743d6cc21 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -340,15 +340,9 @@ self-powered; data-role = "dual"; power-role = "sink"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb_con_hs: endpoint { - remote-endpoint = <&usb0_hs_ep>; - }; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; }; }; }; @@ -475,12 +469,9 @@ &usb0 { bootph-all; - #address-cells = <1>; - #size-cells = <0>; usb-role-switch; - port@0 { - reg = <0>; + port { usb0_hs_ep: endpoint { remote-endpoint = <&usb_con_hs>; }; -- cgit v1.2.3-58-ga151 From 9c99c33a904c86d95ecf4e2690de6a826b88671c Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Sat, 29 Jun 2024 09:29:43 +0300 Subject: arm64: dts: qcom: x1e80100: Fix USB HS PHY 0.8V supply According to the power grid documentation, the 0.8v HS PHY shared regulator is actually LDO3 from PM8550ve id J. Fix both CRD and QCP boards. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240629-x1e80100-dts-fix-hsphy-0-8v-supplies-v1-1-de99ee030b27@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 6 +++--- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index d0f28d8547b1..96f51850644b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -990,7 +990,7 @@ }; &usb_1_ss0_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -1022,7 +1022,7 @@ }; &usb_1_ss1_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -1054,7 +1054,7 @@ }; &usb_1_ss2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 4edec3212dde..72a4f4138616 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -842,7 +842,7 @@ }; &usb_1_ss0_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -874,7 +874,7 @@ }; &usb_1_ss1_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -906,7 +906,7 @@ }; &usb_1_ss2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; + vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; -- cgit v1.2.3-58-ga151 From 721e38301b79a6ee8375cb0ebd586699a7f353e3 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 29 Jun 2024 07:19:38 +0530 Subject: arm64: dts: qcom: x1e80100: Add gpu support Add the necessary dt nodes for gpu support in X1E80100. Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240629015111.264564-6-quic_akhilpo@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 195 +++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 72abfab0f1f7..7bca5fcd7d52 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -3131,6 +3132,200 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050c01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/gen70500_zap.mbn"; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-level = ; + opp-peak-kBps = <14398438>; + }; + + opp-925000000 { + opp-hz = /bits/ 64 <925000000>; + opp-level = ; + opp-peak-kBps = <14398438>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + }; + + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + }; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + opp-peak-kBps = <6074219>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = ; + opp-peak-kBps = <3000000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = ; + opp-peak-kBps = <2136719>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,x1e80100-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; -- cgit v1.2.3-58-ga151 From ac3eb41a283adf861aa49408bd4a6ce1e9563f84 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 1 Jul 2024 21:11:16 +0300 Subject: arm64: dts: qcom: pm8916: correct thermal zone name Correct the name for the thermal zone on PM8916 PMIC. I ended up with c&p mistake, which wasn't noticed until the patch got merged. Reported-by: Konrad Dybcio Fixes: b7a28d8a7b80 ("arm64: dts: qcom: pm8916: add temp-alarm thermal zone") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240701-fix-pm8916-tz-v1-1-02f8a713f577@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 2def48f2d101..f8e4829ff7f7 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -6,7 +6,7 @@ / { thermal-zones { - pm8150-thermal { + pm8916-thermal { polling-delay-passive = <100>; thermal-sensors = <&pm8916_temp>; -- cgit v1.2.3-58-ga151 From 2a89f2b7e4b98ff684eff2950cbe62d8dd47da72 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 08:22:53 +0200 Subject: ARM: dts: qcom: apq8064: drop incorrect ranges from QFPROM There is no direct mapping between QFPROM children and parent/SoC MMIO bus, so 'ranges' property is not correct. Pointed by dtbs_check: qcom-apq8064-cm-qs600.dtb: efuse@700000: Unevaluated properties are not allowed ('ranges' was unexpected) Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406292139.yqPYyUfi-lkp@intel.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240701062253.18149-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index d73ea1434b36..769e151747c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -671,7 +671,7 @@ reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; - ranges; + tsens_calib: calib@404 { reg = <0x404 0x10>; }; -- cgit v1.2.3-58-ga151 From d870196e3383b92179dfc051fe6f038df9a94ea9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 27 Jun 2024 15:15:54 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240627-fp4-regulator-name-v1-1-66931111a006@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index a74f3ac09a5e..4e67bb80a026 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -150,124 +150,145 @@ qcom,pmic-id = "a"; vreg_s1a: smps1 { + regulator-name = "vreg_s1a"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; vreg_s2a: smps2 { + regulator-name = "vreg_s2a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <2048000>; }; vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; regulator-min-microvolt = <352000>; regulator-max-microvolt = <801000>; regulator-initial-mode = ; }; vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; regulator-min-microvolt = <1710000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-initial-mode = ; }; vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = ; }; vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; regulator-min-microvolt = <570000>; regulator-max-microvolt = <650000>; regulator-initial-mode = ; }; vreg_l14a: ldo14 { + regulator-name = "vreg_l14a"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = ; }; vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; regulator-min-microvolt = <830000>; regulator-max-microvolt = <921000>; regulator-initial-mode = ; }; vreg_l18a: ldo18 { + regulator-name = "vreg_l18a"; regulator-min-microvolt = <788000>; regulator-max-microvolt = <1049000>; regulator-initial-mode = ; }; vreg_l19a: ldo19 { + regulator-name = "vreg_l19a"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = ; }; vreg_l20a: ldo20 { + regulator-name = "vreg_l20a"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <801000>; regulator-initial-mode = ; }; vreg_l21a: ldo21 { + regulator-name = "vreg_l21a"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <825000>; regulator-initial-mode = ; }; vreg_l22a: ldo22 { + regulator-name = "vreg_l22a"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = ; @@ -279,41 +300,48 @@ qcom,pmic-id = "e"; vreg_s8e: smps8 { + regulator-name = "vreg_s8e"; regulator-min-microvolt = <313000>; regulator-max-microvolt = <1395000>; }; vreg_l1e: ldo1 { + regulator-name = "vreg_l1e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2e: ldo2 { + regulator-name = "vreg_l2e"; regulator-min-microvolt = <1170000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = ; }; vreg_l3e: ldo3 { + regulator-name = "vreg_l3e"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1299000>; regulator-initial-mode = ; }; vreg_l4e: ldo4 { + regulator-name = "vreg_l4e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5e: ldo5 { + regulator-name = "vreg_l5e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2950000>; regulator-initial-mode = ; @@ -323,18 +351,21 @@ }; vreg_l7e: ldo7 { + regulator-name = "vreg_l7e"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9e: ldo9 { + regulator-name = "vreg_l9e"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = ; @@ -344,18 +375,21 @@ }; vreg_l10e: ldo10 { + regulator-name = "vreg_l10e"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = ; }; vreg_l11e: ldo11 { + regulator-name = "vreg_l11e"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = ; }; vreg_bob: bob { + regulator-name = "vreg_bob"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <5492000>; regulator-initial-mode = ; -- cgit v1.2.3-58-ga151 From 1cda6acb8fbd9c1050737d50a60c0b91b8c64dfb Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Jun 2024 14:57:14 +0200 Subject: arm64: dts: qcom: sm8650-hdk: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker to correctly map the Speaker ports to the WSA macro ports. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240627-topic-sm8650-upstream-was-port-mapping-v1-1-4700bcc2489a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index eb2f910b4f58..591e6ab9bf5b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1137,6 +1137,16 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker South */ @@ -1150,6 +1160,16 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From f3b84707c41fe1c2ca41588278ac1845d15a5006 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Jun 2024 14:57:15 +0200 Subject: arm64: dts: qcom: sm8650-mtp: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker to correctly map the Speaker ports to the WSA macro ports. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240627-topic-sm8650-upstream-was-port-mapping-v1-2-4700bcc2489a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index fa6c3b397f2d..c63822f5b127 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -751,6 +751,16 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker Right */ @@ -764,6 +774,16 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From 519df670e8921d0f9bea2be1049ad601742d749d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Jun 2024 14:57:16 +0200 Subject: arm64: dts: qcom: sm8650-qrd: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker to correctly map the Speaker ports to the WSA macro ports. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240627-topic-sm8650-upstream-was-port-mapping-v1-3-4700bcc2489a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 6e3c4d8dcc19..b0d7927b708f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1089,6 +1089,16 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker Right */ @@ -1102,6 +1112,16 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From 21663c69b3f75ae52d9f1f6b844aa2bb314a6a3f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 27 Jun 2024 14:20:13 +0200 Subject: arm64: dts: qcom: sm8550-hdk: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker. This solves second (south) speaker sound distortions when playing audio. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240627122015.30945-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index e0dc03a97771..2e12219006c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1106,6 +1106,7 @@ #sound-dai-cells = <0>; sound-name-prefix = "SpkrLeft"; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker South */ @@ -1123,6 +1124,7 @@ #sound-dai-cells = <0>; sound-name-prefix = "SpkrRight"; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From 5ba3ba4d4439709c68b96aef3b0e71c63fd9d665 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 27 Jun 2024 14:20:14 +0200 Subject: arm64: dts: qcom: sm8550-mtp: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker. This solves second (right) speaker sound distortions when playing audio. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240627122015.30945-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 26dfca0c3e05..ab447fc252f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -842,6 +842,7 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845 */ @@ -855,6 +856,7 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From 6bf99fdb4c93b165e77b879606f2e9c2571399da Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 27 Jun 2024 14:20:15 +0200 Subject: arm64: dts: qcom: sm8550-qrd: add port mapping to speakers Add appropriate mappings of Soundwire ports of WSA8845 speaker. This solves second (south) speaker sound distortions when playing audio. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240627122015.30945-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 361b0792db4f..774bdfcffec3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1025,6 +1025,7 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker South */ @@ -1038,6 +1039,7 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; -- cgit v1.2.3-58-ga151 From 9ca49bb26ef64ffd0edd1a037e0b00b8e32617dc Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 27 Jun 2024 13:42:10 +0200 Subject: dt-bindings: arm: qcom: add sa8775p-ride Rev 3 Document the compatible for revision 3 of the sa8775p-ride board. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240627114212.25400-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ec1c10a12470..000037f4a712 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -895,6 +895,7 @@ properties: - items: - enum: - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 - const: qcom,sa8775p - items: -- cgit v1.2.3-58-ga151 From fe15631117f8d85b1bc4e0c3b434c78be483a43d Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 27 Jun 2024 13:42:11 +0200 Subject: arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsi In order to support multiple revisions of the sa8775p-ride board, create a .dtsi containing the common parts and split out the ethernet bits into the actual board file as they will change in revision 3. Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20240627114212.25400-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 834 +---------------------------- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 814 ++++++++++++++++++++++++++++ 2 files changed, 835 insertions(+), 813 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 26ad05bd3b3f..2e87fd760dbd 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,835 +5,43 @@ /dts-v1/; -#include -#include - -#include "sa8775p.dtsi" -#include "sa8775p-pmics.dtsi" +#include "sa8775p-ride.dtsi" / { model = "Qualcomm SA8775P Ride"; compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; - - aliases { - ethernet0 = ðernet0; - ethernet1 = ðernet1; - i2c11 = &i2c11; - i2c18 = &i2c18; - serial0 = &uart10; - serial1 = &uart12; - serial2 = &uart17; - spi16 = &spi16; - ufshc1 = &ufs_mem_hc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_s4a: smps4 { - regulator-name = "vreg_s4a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1816000>; - regulator-initial-mode = ; - }; - - vreg_s5a: smps5 { - regulator-name = "vreg_s5a"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1996000>; - regulator-initial-mode = ; - }; - - vreg_s9a: smps9 { - regulator-name = "vreg_s9a"; - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - regulator-initial-mode = ; - }; - - vreg_l4a: ldo4 { - regulator-name = "vreg_l4a"; - regulator-min-microvolt = <788000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l5a: ldo5 { - regulator-name = "vreg_l5a"; - regulator-min-microvolt = <870000>; - regulator-max-microvolt = <950000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l6a: ldo6 { - regulator-name = "vreg_l6a"; - regulator-min-microvolt = <870000>; - regulator-max-microvolt = <970000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l7a: ldo7 { - regulator-name = "vreg_l7a"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <950000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l8a: ldo8 { - regulator-name = "vreg_l8a"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l9a: ldo9 { - regulator-name = "vreg_l9a"; - regulator-min-microvolt = <2970000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - }; - - regulators-1 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_l1c: ldo1 { - regulator-name = "vreg_l1c"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1260000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l2c: ldo2 { - regulator-name = "vreg_l2c"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l3c: ldo3 { - regulator-name = "vreg_l3c"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l4c: ldo4 { - regulator-name = "vreg_l4c"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - /* - * FIXME: This should have regulator-allow-set-load but - * we're getting an over-current fault from the PMIC - * when switching to LPM. - */ - }; - - vreg_l5c: ldo5 { - regulator-name = "vreg_l5c"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l6c: ldo6 { - regulator-name = "vreg_l6c"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l7c: ldo7 { - regulator-name = "vreg_l7c"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l8c: ldo8 { - regulator-name = "vreg_l8c"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l9c: ldo9 { - regulator-name = "vreg_l9c"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2700000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "e"; - - vreg_s4e: smps4 { - regulator-name = "vreg_s4e"; - regulator-min-microvolt = <970000>; - regulator-max-microvolt = <1520000>; - regulator-initial-mode = ; - }; - - vreg_s7e: smps7 { - regulator-name = "vreg_s7e"; - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - regulator-initial-mode = ; - }; - - vreg_s9e: smps9 { - regulator-name = "vreg_s9e"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <570000>; - regulator-initial-mode = ; - }; - - vreg_l6e: ldo6 { - regulator-name = "vreg_l6e"; - regulator-min-microvolt = <1280000>; - regulator-max-microvolt = <1450000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - - vreg_l8e: ldo8 { - regulator-name = "vreg_l8e"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1950000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; - }; - }; }; ðernet0 { phy-mode = "sgmii"; - phy-handle = <&sgmii_phy0>; - - pinctrl-0 = <ðernet0_default>; - pinctrl-names = "default"; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,ps-speed = <1000>; - - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@a { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0xa>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; }; ðernet1 { phy-mode = "sgmii"; - phy-handle = <&sgmii_phy1>; - - snps,mtl-rx-config = <&mtl_rx_setup1>; - snps,mtl-tx-config = <&mtl_tx_setup1>; - snps,ps-speed = <1000>; - - status = "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - -&i2c11 { - clock-frequency = <400000>; - pinctrl-0 = <&qup_i2c11_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c18 { - clock-frequency = <400000>; - pinctrl-0 = <&qup_i2c18_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pmm8654au_0_gpios { - gpio-line-names = "DS_EN", - "POFF_COMPLETE", - "UFS0_VER_ID", - "FAST_POFF", - "DBU1_PON_DONE", - "AOSS_SLEEP", - "CAM_DES0_EN", - "CAM_DES1_EN", - "CAM_DES2_EN", - "CAM_DES3_EN", - "UEFI", - "ANALOG_PON_OPT"; -}; - -&pmm8654au_0_pon_resin { - linux,code = ; - status = "okay"; -}; - -&pmm8654au_1_gpios { - gpio-line-names = "PMIC_C_ID0", - "PMIC_C_ID1", - "UFS1_VER_ID", - "IPA_PWR", - "", - "WLAN_DBU4_EN", - "WLAN_EN", - "BT_EN", - "USB2_PWR_EN", - "USB2_FAULT"; - - usb2_en_state: usb2-en-state { - pins = "gpio9"; - function = "normal"; - output-high; - power-source = <0>; - }; -}; - -&pmm8654au_2_gpios { - gpio-line-names = "PMIC_E_ID0", - "PMIC_E_ID1", - "USB0_PWR_EN", - "USB0_FAULT", - "SENSOR_IRQ_1", - "SENSOR_IRQ_2", - "SENSOR_RST", - "SGMIIO0_RST", - "SGMIIO1_RST", - "USB1_PWR_ENABLE", - "USB1_FAULT", - "VMON_SPX8"; - - usb0_en_state: usb0-en-state { - pins = "gpio3"; - function = "normal"; - output-high; - power-source = <0>; - }; - - usb1_en_state: usb1-en-state { - pins = "gpio10"; - function = "normal"; - output-high; - power-source = <0>; - }; -}; - -&pmm8654au_3_gpios { - gpio-line-names = "PMIC_G_ID0", - "PMIC_G_ID1", - "GNSS_RST", - "GNSS_EN", - "GNSS_BOOT_MODE"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -&serdes0 { - phy-supply = <&vreg_l5a>; - status = "okay"; -}; - -&serdes1 { - phy-supply = <&vreg_l5a>; - status = "okay"; -}; - -&sleep_clk { - clock-frequency = <32764>; -}; - -&spi16 { - pinctrl-0 = <&qup_spi16_default>; - pinctrl-names = "default"; - status = "okay"; }; -&tlmm { - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins = "gpio8"; - function = "emac0_mdc"; - drive-strength = <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins = "gpio9"; - function = "emac0_mdio"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - qup_uart10_default: qup-uart10-state { - pins = "gpio46", "gpio47"; - function = "qup1_se3"; - }; - - qup_spi16_default: qup-spi16-state { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - function = "qup2_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-state { - pins = "gpio48", "gpio49"; - function = "qup1_se4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c18_default: qup-i2c18-state { - pins = "gpio95", "gpio96"; - function = "qup2_se4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart12_default: qup-uart12-state { - qup_uart12_cts: qup-uart12-cts-pins { - pins = "gpio52"; - function = "qup1_se5"; - bias-disable; - }; - - qup_uart12_rts: qup-uart12-rts-pins { - pins = "gpio53"; - function = "qup1_se5"; - bias-pull-down; - }; - - qup_uart12_tx: qup-uart12-tx-pins { - pins = "gpio54"; - function = "qup1_se5"; - bias-pull-up; - }; - - qup_uart12_rx: qup-uart12-rx-pins { - pins = "gpio55"; - function = "qup1_se5"; - bias-pull-down; - }; - }; - - qup_uart17_default: qup-uart17-state { - qup_uart17_cts: qup-uart17-cts-pins { - pins = "gpio91"; - function = "qup2_se3"; - bias-disable; - }; - - qup_uart17_rts: qup0-uart17-rts-pins { - pins = "gpio92"; - function = "qup2_se3"; - bias-pull-down; - }; - - qup_uart17_tx: qup0-uart17-tx-pins { - pins = "gpio93"; - function = "qup2_se3"; - bias-pull-up; - }; - - qup_uart17_rx: qup0-uart17-rx-pins { - pins = "gpio94"; - function = "qup2_se3"; - bias-pull-down; - }; - }; +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; - pcie0_default_state: pcie0-default-state { - perst-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio1"; - function = "pcie0_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio0"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; }; - pcie1_default_state: pcie1-default-state { - perst-pins { - pins = "gpio4"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio3"; - function = "pcie1_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio5"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; }; }; - -&pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - status = "okay"; -}; - -&pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - status = "okay"; -}; - -&pcie0_phy { - vdda-phy-supply = <&vreg_l5a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&pcie1_phy { - vdda-phy-supply = <&vreg_l5a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&uart10 { - compatible = "qcom,geni-debug-uart"; - pinctrl-0 = <&qup_uart10_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart12 { - pinctrl-0 = <&qup_uart12_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart17 { - pinctrl-0 = <&qup_uart17_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ufs_mem_hc { - reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - vcc-supply = <&vreg_l8a>; - vcc-max-microamp = <1100000>; - vccq-supply = <&vreg_l4c>; - vccq-max-microamp = <1200000>; - - status = "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply = <&vreg_l4a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&usb_0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_state>; - - status = "okay"; -}; - -&usb_0_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_0_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; - - status = "okay"; -}; - -&usb_1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_state>; - - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; - - status = "okay"; -}; - -&usb_2 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_en_state>; - - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&xo_board_clk { - clock-frequency = <38400000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi new file mode 100644 index 000000000000..2a6170623ea9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include + +#include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + i2c11 = &i2c11; + i2c18 = &i2c18; + serial0 = &uart10; + serial1 = &uart12; + serial2 = &uart17; + spi16 = &spi16; + ufshc1 = &ufs_mem_hc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = ; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = ; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = ; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +ðernet0 { + phy-handle = <&sgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&sgmii_phy1>; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c11 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c18 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_0_pon_resin { + linux,code = ; + status = "okay"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; + + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; + + usb0_en_state: usb0-en-state { + pins = "gpio3"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb1_en_state: usb1-en-state { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + +&serdes1 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; + }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins = "gpio94"; + function = "qup2_se3"; + bias-pull-down; + }; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart12 { + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart17 { + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_state>; + + status = "okay"; +}; + +&usb_0_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_state>; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; -- cgit v1.2.3-58-ga151 From 818c2676e5816dad5a77df5a1c0d99d0e160d0b1 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 27 Jun 2024 13:42:12 +0200 Subject: arm64: dts: qcom: sa8775p-ride-r3: add new board file Revision 3 of the sa8775p-ride board uses a different PHY for the two ethernet ports and supports 2.5G speed. Create a new file for the board reflecting the changes. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240627114212.25400-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 47 ++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5576c7d6ea06..8b7a81b82213 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts new file mode 100644 index 000000000000..ae065ae92478 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p-ride.dtsi" + +/ { + model = "Qualcomm SA8775P Ride Rev3"; + compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; +}; + +ðernet0 { + phy-mode = "2500base-x"; +}; + +ðernet1 { + phy-mode = "2500base-x"; +}; + +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@0 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x0>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; +}; -- cgit v1.2.3-58-ga151 From e796887c06d177155b7bb6e6b876bb3683e23fda Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 1 Jul 2024 17:54:58 -0300 Subject: arm64: dts: imx8mp: Remove 'snps,rx-sched-sp' According to nxp,dwmac-imx.yaml, 'snps,rx-sched-sp' is not a valid property. Remove it from the imx8mp board devicetree files to avoid dt-schema warnings: ... 'snps,tx-sched-sp' does not match any of the regexes Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 2 -- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 - arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 8be251b69378..15f7ab58db36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -71,7 +71,6 @@ mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; queue0 { snps,dcb-algorithm; @@ -106,7 +105,6 @@ mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a64e8a6c830d..938347704136 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -307,7 +307,6 @@ mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index c96e74684e03..d23a3942174d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -241,7 +241,6 @@ mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; queue0 { snps,dcb-algorithm; @@ -276,7 +275,6 @@ mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; -- cgit v1.2.3-58-ga151 From 1c6285e10d76b0cfb5b0384dc9c02e266a2ffd0a Mon Sep 17 00:00:00 2001 From: Pierre-Hugues Husson Date: Tue, 4 Jun 2024 18:44:24 +0200 Subject: arm64: dts: qcom: msm8998: add venus node Now that the venus clocks are fixed, we can add the DT node. Signed-off-by: Pierre-Hugues Husson Signed-off-by: Marc Gonzalez Reviewed-by: Bryan O'Donoghue Acked-by: Vikash Garodia Link: https://lore.kernel.org/r/6d86a6a3-4d99-4fda-9a38-7688587237e6@freebox.fr Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 48 +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3c94d823a514..99f811a57ac5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3000,6 +3000,54 @@ }; }; + venus: video-codec@cc00000 { + compatible = "qcom,msm8998-venus"; + reg = <0x0cc00000 0xff000>; + interrupts = ; + power-domains = <&mmcc VIDEO_TOP_GDSC>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc VIDEO_MAXI_CLK>; + clock-names = "core", "iface", "bus", "mbus"; + iommus = <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + memory-region = <&venus_mem>; + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; -- cgit v1.2.3-58-ga151 From c6050d45cd372e4a34f9f501b30243caf2e810c6 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 2 Jul 2024 13:01:19 +0700 Subject: arm64: dts: qcom: qrb4210-rb2: Correct max current draw for VBUS According to downstream sources, maximum current for PMI632 VBUS is 1A. Taken from msm-4.19 (631561973a034e46ccacd0e53ef65d13a40d87a4) Line 685-687 in drivers/power/supply/qcom/qpnp-smb5.c Fixes: a06a2f12f9e2 ("arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling") Reviewed-by: Luca Weiss Signed-off-by: Dang Huynh Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240702-qrd4210rb2-vbus-volt-v3-1-fbd24661eec4@riseup.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 1c7de7f2db79..1888d99d398b 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -305,7 +305,7 @@ &pmi632_vbus { regulator-min-microamp = <500000>; - regulator-max-microamp = <3000000>; + regulator-max-microamp = <1000000>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From ef7025079a9de1ed06a049a0c69afe822d0b7fb0 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Mon, 1 Jul 2024 11:05:17 +0800 Subject: dt-bindings: arm: qcom: Add ASUS Vivobook S 15 Add the compatible for this device. Signed-off-by: Xilin Wu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240701-asus-vivobook-s15-v4-1-ce7933b4d4e5@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 000037f4a712..599e8930cda8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1037,6 +1037,7 @@ properties: - items: - enum: + - asus,vivobook-s15 - qcom,x1e80100-crd - qcom,x1e80100-qcp - const: qcom,x1e80100 -- cgit v1.2.3-58-ga151 From d0e2f8f62dff11ce399937fa51d09c24b46049be Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Mon, 1 Jul 2024 11:05:18 +0800 Subject: arm64: dts: qcom: Add device tree for ASUS Vivobook S 15 ASUS Vivobook S 15 is a laptop based on the Qualcomm Snapdragon X Elite SoC (X1E78100). Add the device tree for the laptop with support for the following features: - CPU frequency scaling up to 3.4GHz - NVMe storage on PCIe 6a (capable of Gen4x4, currently limited to Gen4x2) - Keyboard and touchpad - WCN7850 Wi-Fi - Two Type-C ports on the left side (USB3 only in one orientation) - internal eDP display - ADSP and CDSP remoteprocs Further details could be found in the cover letter. Signed-off-by: Xilin Wu Link: https://lore.kernel.org/r/20240701-asus-vivobook-s15-v4-2-ce7933b4d4e5@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 616 +++++++++++++++++++++ 2 files changed, 617 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8b7a81b82213..e0babd642fa8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -259,5 +259,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts new file mode 100644 index 000000000000..7fb980fcb307 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +/dts-v1/; + +#include +#include + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model = "ASUS Vivobook S 15"; + compatible = "asus,vivobook-s15", "qcom,x1e80100"; + chassis-type = "laptop"; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + /* EC? @ 0x5b, 0x76 */ +}; + +&i2c7 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcadsp8380.mbn", + "qcom/x1e80100/ASUSTeK/vivobook-s15/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qccdsp8380.mbn", + "qcom/x1e80100/ASUSTeK/vivobook-s15/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "disabled"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; -- cgit v1.2.3-58-ga151 From 968178e35e78e566f75dbb7fbfc4dd1436ce8309 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sun, 30 Jun 2024 13:29:26 +0000 Subject: dt-bindings: arm: qcom: Document samsung,ms013g Document samsung,ms013g for Galaxy Grand 2. Signed-off-by: Raymond Hackley Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240630132859.2885-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 599e8930cda8..1c8643eeb2d1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -141,6 +141,7 @@ properties: - microsoft,makepeace - microsoft,moneypenny - motorola,falcon + - samsung,ms013g - samsung,s3ve3g - const: qcom,msm8226 -- cgit v1.2.3-58-ga151 From 2a5454d0fe5684855581f8ad958afbcdc476fd64 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sun, 30 Jun 2024 13:29:41 +0000 Subject: ARM: dts: qcom: qcom-msm8226-samsung-ms013g: Add initial device tree Samsung Galaxy Grand 2 is a phone based on MSM8226. It's similar to the other Samsung devices based on MSM8226 with only a few minor differences. The device trees contain initial support with: - GPIO keys - Regulator haptic - SDHCI (internal and external storage) - UART (on USB connector via the TI TSU6721 MUIC) - Regulators - Touchscreen - Accelerometer Signed-off-by: Raymond Hackley Reviewed-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240630132859.2885-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts | 386 +++++++++++++++++++++ 2 files changed, 387 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index ccd4ce6353df..f06c6d425e91 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8226-microsoft-dempsey.dtb \ qcom-msm8226-microsoft-makepeace.dtb \ qcom-msm8226-microsoft-moneypenny.dtb \ + qcom-msm8226-samsung-ms013g.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8916-samsung-e5.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts new file mode 100644 index 000000000000..2ecc5983d365 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &smem_region; + +/ { + model = "Samsung Galaxy Grand 2"; + compatible = "samsung,ms013g", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-home { + label = "Home Key"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; + + reserved-memory { + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + }; + + vibrator { + compatible = "regulator-haptic"; + haptic-supply = <®_motor_vdd>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma255"; + reg = <0x18>; + interrupts-extended = <&tlmm 64 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + + reg = <0x20>; + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8226_lvs1>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdhc2_default_state &sdhc2_cd_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio50"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio106", "gpio107", "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdhc2_cd_default: sdhc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-58-ga151 From 9e8560556f9c41da28118af3385b4e9dc832ae2b Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Thu, 13 Jun 2024 20:39:00 +0530 Subject: arm64: dts: ti: k3-am62x-sk-common: Reserve 128MiB of global CMA Reserve 128MiB of global CMA which is also marked as re-usable so that OS can also use the same if peripheral drivers are not using the same. AM62x supports multimedia components such as GPU, dual Display and Camera. Assuming the worst-case scenario where all 3 are run in parallel below is the calculation : 1) OV5640 camera sensor supports 1920x1080 resolution -> 1920 width x 1080 height x 2 bytesperpixel x 8 buffers (default in yavta) : 32MiB 2) 1920x1200 Microtips LVDS panel supported -> 1920 width x 1080 height x 4 bytesperpixel x 2 buffers : 16 MiB 3) 1920x1080 HDMI display supported -> 1920 width x 1080 height x 4 bytesperpixel x 2 buffers : 15.82 MiB which is ~16 MiB 4) IMG GPU shares with display allocated buffers while rendering but in case some dedicated operation viz color conversion, keeping same window of ~16 MiB for GPU too. Total is 80 MiB and adding 32 MiB for other peripherals and extra 16 MiB to keep as buffer for fragmentation thus rounding total to 128 MiB. Signed-off-by: Devarsh Thakkar Reviewed-by: Randolph Sapp Link: https://lore.kernel.org/r/20240613150902.2173582-2-devarsht@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 465743d6cc21..44ff67b6bf1e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -48,6 +48,14 @@ pmsg-size = <0x8000>; }; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; -- cgit v1.2.3-58-ga151 From 6406c5d5512c0814b8c155df7f833a98d9069a72 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Thu, 13 Jun 2024 20:39:01 +0530 Subject: arm64: dts: ti: k3-am62a7-sk: Reserve 576MiB of global CMA Reserve 576MiB of CMA as global CMA pool starting after initial 1GiB of DDR. AM62ax has different multimedia components such as Camera, Display, H.264 VPU and JPEG Encoder which use CMA for buffer allocations. The 12x 720x480 realtime VPU decode use-case requires 544MiB of CMA, additional 32MiB is kept as buffer in case some other peripheral also require it while VPU is running. The reason to choose latter 1GiB is to not overlap with existing memory map which is utilizing initial 1GiB for remoteproc firmwares as shared here [1]. Also some drivers such as JPEG require 32bit addressing so not allocating from higher DDR address. Link: https://lore.kernel.org/all/20240605124859.3034-5-hnagalla@ti.com [1] Signed-off-by: Devarsh Thakkar Tested-by: Brandon Brnich Reviewed-by: Randolph Sapp Link: https://lore.kernel.org/r/20240613150902.2173582-3-devarsht@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index e026f65738b3..67faf46d7a35 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -40,6 +40,15 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; -- cgit v1.2.3-58-ga151 From 9c29e5d7a2d1d91c29976c0c8aa7f42780e4a254 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 30 Jun 2024 05:48:41 +0200 Subject: ARM: dts: rockchip: Drop ethernet-phy-ieee802.3-c22 from PHY compatible string on edgeble-neu2 The rtl82xx DT bindings do not require ethernet-phy-ieee802.3-c22 as the fallback compatible string. There are fewer users of the Realtek PHY compatible string with fallback compatible string than there are users without fallback compatible string, so drop the fallback compatible string from the few remaining users: $ git grep -ho ethernet-phy-id001c....... | sort | uniq -c 1 ethernet-phy-id001c.c816", 2 ethernet-phy-id001c.c915", 2 ethernet-phy-id001c.c915"; 5 ethernet-phy-id001c.c916", 13 ethernet-phy-id001c.c916"; Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406290316.YvZdvLxu-lkp@intel.com/ Signed-off-by: Marek Vasut Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20240630034910.173552-1-marex@denx.de Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 0c2396b8f8db..7707d1b01440 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -69,8 +69,7 @@ &mdio { phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x0>; pinctrl-names = "default"; pinctrl-0 = <ð_phy_rst>; -- cgit v1.2.3-58-ga151 From 9d42c3ee3ce37cdad6f98c9e77bfbd0d791ac7da Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 2 Jul 2024 04:12:52 +0300 Subject: arm64: dts: rockchip: Add missing power-domains for rk356x vop_mmu The iommu@fe043e00 on RK356x SoC shares the VOP power domain, but the power-domains property was not provided when the node has been added. The consequence is that an attempt to reload the rockchipdrm module will freeze the entire system. That is because on probe time, pm_runtime_get_suppliers() gets called for vop@fe040000, which blocks when pm_runtime_get_sync() is being invoked for iommu@fe043e00. Fix the issue by adding the missing property. Fixes: 9d6c6d978f97 ("arm64: dts: rockchip: rk356x: Add VOP2 nodes") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20240702-rk356x-fix-vop-mmu-v1-1-a66d1a0c45ea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index d8543b5557ee..3e2a8bfcafea 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -790,6 +790,7 @@ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3568_PD_VO>; status = "disabled"; }; -- cgit v1.2.3-58-ga151 From 3573653dcf29a254a274b50f699af14e987b1925 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 30 Jun 2024 05:48:42 +0200 Subject: arm64: dts: rockchip: Drop ethernet-phy-ieee802.3-c22 from PHY compatible string on all RK3588 boards The rtl82xx DT bindings do not require ethernet-phy-ieee802.3-c22 as the fallback compatible string. There are fewer users of the Realtek PHY compatible string with fallback compatible string than there are users without fallback compatible string, so drop the fallback compatible string from the few remaining users: $ git grep -ho ethernet-phy-id001c....... | sort | uniq -c 1 ethernet-phy-id001c.c816", 2 ethernet-phy-id001c.c915", 2 ethernet-phy-id001c.c915"; 5 ethernet-phy-id001c.c916", 13 ethernet-phy-id001c.c916"; Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406290316.YvZdvLxu-lkp@intel.com/ Signed-off-by: Marek Vasut Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20240630034910.173552-2-marex@denx.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 6 ++---- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 3 +-- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 230e630820b4..c2a08bdf09e8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -261,8 +261,7 @@ &mdio0 { rgmii_phy0: ethernet-phy@1 { /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; pinctrl-names = "default"; pinctrl-0 = <&rtl8211f_0_rst>; @@ -275,8 +274,7 @@ &mdio1 { rgmii_phy1: ethernet-phy@2 { /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x2>; pinctrl-names = "default"; pinctrl-0 = <&rtl8211f_1_rst>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 77bcf0f6b028..dbaa94ca69f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -198,8 +198,7 @@ &mdio1 { rgmii_phy: ethernet-phy@1 { /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; pinctrl-names = "default"; pinctrl-0 = <&rtl8211f_rst>; -- cgit v1.2.3-58-ga151 From 2e1fae80023a38ea03dfca3eab65b3b46617ef3b Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 30 Jun 2024 18:00:40 +0200 Subject: arm64: dts: rockchip: Add GPU OPP voltage ranges to RK356x SoC dtsi Add support for voltage ranges to the GPU OPPs defined in the SoC dtsi for Rockchip RK356x. This is, for example, useful for RK356x-based boards that are designed to use the same power supply for the GPU and NPU portions of the SoC, which is described further in the following documents: - Rockchip RK3566 Hardware Design Guide, version 1.1.0, page 37 - Rockchip RK3568 Hardware Design Guide, version 1.2, page 78 The values for the exact GPU OPP voltages and the lower limits for the GPU OPP voltage ranges differ from the values found in the vendor kernel source (cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support adjust opp-table by otp")), [1][2] and present the exact GPU OPP voltage values that have served us well so far. [1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be7092ab93f564598daa9 [2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Suggested-by: Diederik de Haas Helped-by: Jonas Karlman Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/7e9ba70fd54a21d6f1f267df11e0acabff8d24e0.1719763100.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 3e2a8bfcafea..710291940856 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,32 +195,32 @@ opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1000000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1000000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1000000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; + opp-microvolt = <825000 825000 1000000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1000000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1000000>; }; }; -- cgit v1.2.3-58-ga151 From eb665b1c06bcaf16df10018550d8f467ed4b2887 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 30 Jun 2024 18:00:41 +0200 Subject: arm64: dts: rockchip: Update GPU OPP voltages in RK356x SoC dtsi Update the values for the exact Rockchip RK356x GPU OPP voltages and the lower limits for the GPU OPP voltage ranges, using the most conservative values (i.e. the highest per-OPP voltages) found in the vendor kernel source (cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support adjust opp-table by otp")). [1][2] Using the most conservative per-OPP voltages ensures reliable GPU operation regardless of the actual GPU binning, with the downside of possibly using a bit more power than absolutely needed. [1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be7092ab93f564598daa9 [2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed561650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Suggested-by: Diederik de Haas Helped-by: Jonas Karlman Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/80301764e8983c8410c806ed2256403823709897.1719763100.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 710291940856..4690be841a1c 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,27 +195,27 @@ opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000 825000 1000000>; + opp-microvolt = <850000 850000 1000000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <825000 825000 1000000>; + opp-microvolt = <850000 850000 1000000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000 825000 1000000>; + opp-microvolt = <850000 850000 1000000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000 825000 1000000>; + opp-microvolt = <900000 900000 1000000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000 900000 1000000>; + opp-microvolt = <950000 950000 1000000>; }; opp-800000000 { -- cgit v1.2.3-58-ga151 From bf6f26deb0e84089700c1b864f643442e262e16b Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 28 Jun 2024 14:00:43 +0200 Subject: arm64: dts: rockchip: Add dma-names to uart1 on quartz64-b There have been several attempts to set the dma-names property on the SoC level (in rk356x.dtsi), but that appears to cause problems when set on channels without flow control. Quoting part of a previous attempt for clarification: > Nah, enabling it for bluetooth is fine because you have flow control. > My issues have been on channels without flow control. Without DMA it > simply drops messages or the channel hangs until you close and reopen > it. With DMA, when an overflow locks up the channel it is usually > unavailable until the board is rebooted. Setting it on the board level for the bluetooth connection was deemed safe, so do so for the Quartz64 Model B. This fixes the following error/warning: of_dma_request_slave_channel: dma-names property of node '/serial@fe650000' missing or empty dw-apb-uart fe650000.serial: failed to request DMA Signed-off-by: Diederik de Haas Link: https://libera.irclog.whitequark.org/armlinux/2024-02-29 Link: https://lore.kernel.org/linux-rockchip/18284546.sWSEgdgrri@diego/ Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20240628120130.24076-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 26322a358d91..a9dd60464b3f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -652,6 +652,7 @@ }; &uart1 { + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; status = "okay"; -- cgit v1.2.3-58-ga151 From 2dad31528de9ea8b05245ce6ac4f76ebf8dae947 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 30 Jun 2024 23:00:02 +0800 Subject: arm64: dts: rockchip: fix regulator name for Lunzn Fastrhino R6xS Make the regulator name the same as those marked by schematics. Fixes: c79dab407afd ("arm64: dts: rockchip: Add Lunzn Fastrhino R66S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240630150010.55729-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi index 89e84e3a9262..93987c8740f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -39,9 +39,9 @@ }; }; - dc_12v: dc-12v-regulator { + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; - regulator-name = "dc_12v"; + regulator-name = "vcc12v_dcin"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <12000000>; @@ -65,7 +65,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; + vin-supply = <&vcc12v_dcin>; }; vcc5v0_sys: vcc5v0-sys-regulator { @@ -75,7 +75,7 @@ regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; + vin-supply = <&vcc12v_dcin>; }; vcc5v0_usb_host: vcc5v0-usb-host-regulator { -- cgit v1.2.3-58-ga151 From 9e823ba92118510c0d1c050b67bb000f9b9a73d7 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Jul 2024 22:30:26 +0800 Subject: arm64: dts: rockchip: fix usb regulator for Lunzn Fastrhino R6xS Remove the non-existent usb_host regulator and fix the supply according to the schematic. Also remove the unnecessary always-on and boot-on for the usb_otg regulator. Fixes: c79dab407afd ("arm64: dts: rockchip: Add Lunzn Fastrhino R66S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240701143028.1203997-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi index 93987c8740f7..8f587978fa3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -78,15 +78,6 @@ vin-supply = <&vcc12v_dcin>; }; - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -94,8 +85,9 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_usb_otg_en>; regulator-name = "vcc5v0_usb_otg"; - regulator-always-on; - regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; }; }; @@ -460,7 +452,7 @@ }; &usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; + phy-supply = <&vcc5v0_sys>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From cfeac8e5d05815521f5c5568680735a92ee91fe4 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 30 Jun 2024 23:00:04 +0800 Subject: arm64: dts: rockchip: fix pmu_io supply for Lunzn Fastrhino R6xS Fixes pmu_io_domains supply according to the schematic. Among them, the vccio3 is responsible for the io voltage of sdcard. There is no sdcard slot on the R68S, and it's connected to vcc_3v3, so describe the supply of vccio3 separately. Fixes: c79dab407afd ("arm64: dts: rockchip: Add Lunzn Fastrhino R66S") Fixes: b9f8ca655d80 ("arm64: dts: rockchip: Add Lunzn Fastrhino R68S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240630150010.55729-4-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts | 4 ++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts index 58ab7e9971db..b5e67990dd0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts @@ -11,6 +11,10 @@ }; }; +&pmu_io_domains { + vccio3-supply = <&vccio_sd>; +}; + &sdmmc0 { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi index 8f587978fa3b..82577eba31eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -397,8 +397,8 @@ &pmu_io_domains { pmuio1-supply = <&vcc3v3_pmu>; pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; vccio4-supply = <&vcc_1v8>; vccio5-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts index e1fe5e442689..a3339186e89c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts @@ -102,6 +102,10 @@ }; }; +&pmu_io_domains { + vccio3-supply = <&vcc_3v3>; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>; -- cgit v1.2.3-58-ga151 From cd77139a307fbabe75e6b5cb8a3753e3c700f394 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 30 Jun 2024 23:00:05 +0800 Subject: arm64: dts: rockchip: remove unused usb2 nodes for Lunzn Fastrhino R6xS Fix the following error when booting: [ 15.851853] platform fd800000.usb: deferred probe pending [ 15.852384] platform fd840000.usb: deferred probe pending [ 15.852881] platform fd880000.usb: deferred probe pending This is due to usb2phy1 is not enabled. There is no USB 2.0 port on the board, just remove it. Fixes: c79dab407afd ("arm64: dts: rockchip: Add Lunzn Fastrhino R66S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240630150010.55729-5-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi index 82577eba31eb..e08c9eab6f17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -421,28 +421,12 @@ status = "okay"; }; -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; extcon = <&usb2phy0>; status = "okay"; }; -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - &usb_host1_xhci { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 2bf5d445df2ec89689d15ea259a916260c936959 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Jul 2024 22:30:27 +0800 Subject: arm64: dts: rockchip: disable display subsystem for Lunzn Fastrhino R6xS The R66S and R68S boards do not have HDMI output, so disable the display subsystem. Fixes: c79dab407afd ("arm64: dts: rockchip: Add Lunzn Fastrhino R66S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240701143028.1203997-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi index e08c9eab6f17..25c49bdbadbc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -115,6 +115,10 @@ cpu-supply = <&vdd_cpu>; }; +&display_subsystem { + status = "disabled"; +}; + &gpu { mali-supply = <&vdd_gpu>; status = "okay"; -- cgit v1.2.3-58-ga151 From e261bd74000ca80e5483ba8a8bda509de8cbe7fd Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 30 Jun 2024 23:00:07 +0800 Subject: arm64: dts: rockchip: fixes PHY reset for Lunzn Fastrhino R68S Fixed the PHY address and reset GPIOs (does not match the corresponding pinctrl) for gmac0 and gmac1. Fixes: b9f8ca655d80 ("arm64: dts: rockchip: Add Lunzn Fastrhino R68S") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240630150010.55729-7-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts index a3339186e89c..ce2a5e1ccefc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts @@ -39,7 +39,7 @@ &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; snps,reset-active-low; /* Reset time is 15ms, 50ms for rtl8211f */ snps,reset-delays-us = <0 15000 50000>; @@ -61,7 +61,7 @@ &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; snps,reset-active-low; /* Reset time is 15ms, 50ms for rtl8211f */ snps,reset-delays-us = <0 15000 50000>; @@ -71,18 +71,18 @@ }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; + reg = <0x1>; pinctrl-0 = <ð_phy0_reset_pin>; pinctrl-names = "default"; }; }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; + reg = <0x1>; pinctrl-0 = <ð_phy1_reset_pin>; pinctrl-names = "default"; }; -- cgit v1.2.3-58-ga151 From 690c66656e99ebc962451afbc1f15d074646773a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:11 +0200 Subject: ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board. The following pinmux nodes are added: - ADC pins - ADC CC pins - ETH1 pins - ETH2 pins - I2C5 pins - MCAN1 pins - MCAN2 pins - PWM13 pins - PWM5 pins - QSPI pins - SAI1 pins - SDMMC2 D4..D7 pins - SPI2 pins - SPI3 pins - UART4 pins - UART7 pins - USART1 pins - USART2 pins Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 483 ++++++++++++++++++++++++++++ 1 file changed, 483 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 66efef93251f..22cd07196499 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -6,6 +6,12 @@ #include &pinctrl { + adc1_pins_a: adc1-pins-0 { + pins { + pinmux = ; /* ADC1 in12 */ + }; + }; + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = , /* ADC1 in6 */ @@ -68,6 +74,104 @@ }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = , /* ADC1_INP2 */ + ; /* ADC1_INP11 */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -102,6 +206,23 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ @@ -159,6 +280,46 @@ }; }; + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ + }; + }; + mcp23017_pins_a: mcp23017-0 { pins { pinmux = ; @@ -196,6 +357,21 @@ }; }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = ; /* TIM5_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = ; /* TIM5_CH3 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH3 */ @@ -211,6 +387,21 @@ }; }; + pwm13_pins_a: pwm13-0 { + pins { + pinmux = ; /* TIM13_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm13_sleep_pins_a: pwm13-sleep-0 { + pins { + pinmux = ; /* TIM13_CH1 */ + }; + }; + pwm14_pins_a: pwm14-0 { pins { pinmux = ; /* TIM14_CH1 */ @@ -226,6 +417,89 @@ }; }; + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = ; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = ; /* QSPI_CLK */ + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + }; + }; + + sai1a_pins_a: sai1a-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + }; + }; + + sai1b_pins_a: sai1b-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + bias-disable; + }; + }; + + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -328,6 +602,73 @@ }; }; + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + spi2_pins_a: spi2-0 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_sleep_pins_a: spi2-sleep-0 { + pins { + pinmux = , /* SPI2_SCK */ + , /* SPI2_MISO */ + ; /* SPI2_MOSI */ + }; + }; + + spi3_pins_a: spi3-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + ; /* SPI3_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins { + pinmux = , /* SPI3_SCK */ + , /* SPI3_MISO */ + ; /* SPI3_MOSI */ + }; + }; + spi5_pins_a: spi5-0 { pins1 { pinmux = , /* SPI5_SCK */ @@ -388,6 +729,77 @@ }; }; + uart4_pins_b: uart4-1 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_idle_pins_b: uart4-idle-1 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_sleep_pins_b: uart4-sleep-1 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART7_RX */ + ; /* UART7_CTS_NSS */ + bias-disable; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_CTS_NSS */ + }; + pins2 { + pinmux = ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = , /* UART7_TX */ + , /* UART7_RTS */ + , /* UART7_RX */ + ; /* UART7_CTS_NSS */ + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -459,6 +871,36 @@ }; }; + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -499,4 +941,45 @@ ; /* USART2_CTS_NSS */ }; }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_b: usart2-idle-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; -- cgit v1.2.3-58-ga151 From 6331bddce649829afb2c2e462df812f8e8657a61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:12 +0200 Subject: ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC carrier board. The SoM contains the following peripherals: - STPMIC (power delivery) - 512MB DDR3L memory - eMMC and SDIO WiFi module The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - USB-A Host port, USB-C peripheral port, USB-C power supply plug - Expansion connector Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 321 +++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 308 ++++++++++++++++++++++ 3 files changed, 630 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts create mode 100644 arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 9fedd6776208..015903d09323 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts new file mode 100644 index 000000000000..5f4f6b6e427a --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + * + * DHCOR STM32MP13 variant: + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG + * DHCOR PCB number: 718-100 or newer + * DHSBC PCB number: 719-100 or newer + */ + +/dts-v1/; + +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP135F DHCOR DHSBC"; + compatible = "dh,stm32mp135f-dhcor-dhsbc", + "dh,stm32mp135f-dhcor-som", + "st,stm32mp135"; + + aliases { + serial2 = &usart1; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + * + * The pinmux pins must be set as ANALOG, use datasheet + * DS13483 Table 7. STM32MP135C/F ball definitions to + * find out which 'pin name' maps to which 'additional + * functions', which lists the mapping between pin and + * ADC channel. In this case, PA5 maps to ADC1_INP2 and + * PF13 maps to ADC1_INP11 . + */ + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + + channel@11 { + reg = <11>; + st,min-sample-time-ns = <5000>; + }; + + /* Expansion connector: INP12:pin29 */ + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "DHSBC_USB_PWR_CC1", "", "", + "", "", "", "DHSBC_nETH1_RST", + "", "DHCOR_HW-CODING_0", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOR_BT_HOST_WAKE", + "", "", "", "", + "", "DHSBC_nTPM_CS", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "DHCOR_RAM-CODING_0", "", "", + "", "DHCOR_RAM-CODING_1", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "DHSBC_nTPM_RST", "", "", + "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", ""; +}; + +&gpiof { + gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "", + "", "", "", "", + "", "", "", "", + "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "", + "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; +}; + +&gpioi { + gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", + "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", + "DHSBC_BOOT0", "DHSBC_BOOT1", + "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS"; +}; + +&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + status = "okay"; +}; + +&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */ + clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>; + pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>; +}; + +&scmi_voltd { + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_sleep_pins_a>; + cs-gpios = <&gpiob 13 0>; + status = "okay"; + + st33htph: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + cs-gpios = <&gpiof 3 0>; + status = "disabled"; +}; + +&timers5 { /* Expansion connector: CH3:pin31 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers13 { /* Expansion connector: CH1:pin32 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm13_pins_a>; + pinctrl-1 = <&pwm13_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@12 { + status = "okay"; + }; +}; + +&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b>; + pinctrl-1 = <&usart1_sleep_pins_b>; + pinctrl-2 = <&usart1_idle_pins_b>; + status = "okay"; +}; + +&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + pinctrl-2 = <&usart2_idle_pins_b>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb33d-supply = <&usb33>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + self-powered; + type = "micro"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi new file mode 100644 index 000000000000..ddad6497775b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "DH electronics STM32MP13xx DHCOR SoM"; + compatible = "dh,stm32mp131a-dhcor-som", + "st,stm32mp131"; + + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + rtc0 = &rv3032; + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&vin>; + ldo2-supply = <&vin>; + ldo3-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcpu: buck1 { /* VDD_CPU_1V2 */ + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { /* VDD_DDR_1V35 */ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { /* VDD_3V3_1V8 */ + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vddcore: buck4 { /* VDD_CORE_1V2 */ + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { /* VDD_ADC_1V8 */ + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */ + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_ldo3: ldo3 { /* LDO3_OUT */ + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_usb: ldo4 { /* VDD_USB_3V3 */ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */ + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */ + regulator-name = "vdd_sd2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { /* VREF_DDR_0V675 */ + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { /* BST_OUT_5V2 */ + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; /* ST M24256 */ + reg = <0x50>; + pagesize = <64>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Console UART */ +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_b>; + pinctrl-1 = <&uart4_sleep_pins_b>; + pinctrl-2 = <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed = <3000000>; + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SDIO WiFi */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 1YN */ + reg = <1>; + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + interrupt-parent = <&gpioe>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + bus-width = <8>; + mmc-ddr-3_3v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 0fc78aa67b3f9a7cc6b67ddbc511e4a5022cfd01 Mon Sep 17 00:00:00 2001 From: Yanjun Yang Date: Fri, 14 Jun 2024 09:00:12 +0800 Subject: ARM: dts: stm32: Missing clocks for stm32f429's syscfg. Without clock definition, SYSCFG will not work, EXTI interrupt for port other than GPIOA will fail to operate. Signed-off-by: Yanjun Yang Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f429.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi index 8efcda9ef8ae..ad91b74ddd0d 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -579,6 +579,7 @@ syscfg: syscon@40013800 { compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; }; exti: interrupt-controller@40013c00 { -- cgit v1.2.3-58-ga151 From 7852134db3c6fca65e6cbdf081e40113e9222997 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 31 May 2024 11:16:08 +1200 Subject: ARM: dts: marvell: Add 7-segment LED display on x530 The Allied Telesis x530 products have a 7-segment LED display which is used for node identification when the devices are stacked. Represent this as a gpio-7-segment device. Signed-off-by: Chris Packham Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-385-atl-x530.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts index 5a9ab8410b7b..2fb7304039be 100644 --- a/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts @@ -43,6 +43,17 @@ }; }; }; + + led-7seg { + compatible = "gpio-7-segment"; + segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 1 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 2 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 3 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 4 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 5 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 6 GPIO_ACTIVE_LOW>; + }; }; &pciec { @@ -149,7 +160,7 @@ #size-cells = <0>; reg = <3>; - gpio@20 { + led_7seg_gpio: gpio@20 { compatible = "nxp,pca9554"; gpio-controller; #gpio-cells = <2>; -- cgit v1.2.3-58-ga151 From e62f7f6b48e3473278edc18e439cd60b87ae2644 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 24 Jun 2024 16:53:54 +0200 Subject: ARM: dts: armada-{370-xp,375,38x,39x}: Drop #size-cells from mpic node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The marvell,mpic interrupt controller has no children nodes. Drop the Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-370-xp.dtsi | 1 - arch/arm/boot/dts/marvell/armada-375.dtsi | 1 - arch/arm/boot/dts/marvell/armada-38x.dtsi | 1 - arch/arm/boot/dts/marvell/armada-39x.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi index 0b8c2a64b36f..954c891e5aee 100644 --- a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi @@ -168,7 +168,6 @@ mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; }; diff --git a/arch/arm/boot/dts/marvell/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi index ddc49547d786..99778b4b7e7b 100644 --- a/arch/arm/boot/dts/marvell/armada-375.dtsi +++ b/arch/arm/boot/dts/marvell/armada-375.dtsi @@ -376,7 +376,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 446861b6b17b..1181b13deabc 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -408,7 +408,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; diff --git a/arch/arm/boot/dts/marvell/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi index 9d1cac49c022..6d05835efb42 100644 --- a/arch/arm/boot/dts/marvell/armada-39x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-39x.dtsi @@ -268,7 +268,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = ; -- cgit v1.2.3-58-ga151 From b98a91911d24babe20600ad19697570ea335356f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:34 +0200 Subject: ARM: dts: marvell: kirkwood: align GPIO keys node name with bindings Bindings expect the GPIO key node names to follow certain pattern, see dtbs_check warnings: kirkwood-laplug.dtb: gpio_keys: 'power' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)... Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts | 8 ++++---- arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-dir665.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-iconnect.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-l-50.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-laplug.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi | 2 +- arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi | 6 +++--- arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-t5325.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts | 4 ++-- arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi | 4 ++-- 23 files changed, 47 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts index 07fbfca444d5..f34c3897ff48 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts @@ -35,13 +35,13 @@ gpio_keys { compatible = "gpio-keys"; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - button { + button-power { label = "Power"; linux,code = ; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts index f59ff7578dfc..7e3ee64d4bdf 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts @@ -29,25 +29,25 @@ pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = ; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; - reset { + button-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; - usb1 { + button-usb1 { label = "USB1 Button"; linux,code = ; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - usb2 { + button-usb2 { label = "USB2 Button"; linux,code = ; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts index 448b0cd23b5f..2582b84d8415 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <0>; - power { + key-power { label = "Power push button"; linux,code = ; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts index 0c0851cd9bec..e8eff0ba1c99 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -179,12 +179,12 @@ #address-cells = <1>; #size-cells = <0>; - reset { + button-reset { label = "reset"; linux,code = ; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi index 0738eb679fcd..baea14c68520 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi @@ -14,17 +14,17 @@ &pmx_button_reset>; pinctrl-names = "default"; - power { + button-power { label = "Power button"; linux,code = ; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB unmount button"; linux,code = ; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset button"; linux,code = ; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts index 962a910a6f5c..d76dbbce16f1 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts @@ -63,12 +63,12 @@ pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = ; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts index aed20185fd7a..ea98ff13700e 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts @@ -127,13 +127,13 @@ pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; pinctrl-names = "default"; - otb { + button-otb { label = "OTB Button"; linux,code = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts index 2338f495d517..fa7ace071de8 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts @@ -154,17 +154,17 @@ pinctrl-names = "default"; - Power { + button-power { label = "Power Button"; linux,code = ; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; }; - Reset { + button-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; }; - OTB { + button-otb { label = "OTB Button"; linux,code = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts index c841eb8e7fb1..094854743dde 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -193,7 +193,7 @@ keys { compatible = "gpio-keys"; - factory_defaults { + button-factory-defaults { label = "factory_defaults"; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts index 8c2b540eaf4f..8296486a5931 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts @@ -51,7 +51,7 @@ gpio_keys { compatible = "gpio-keys"; - power { + button-power { label = "Power push button"; linux,code = ; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts index 27fd6e2337d5..3f97240fda74 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts @@ -38,13 +38,13 @@ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; pinctrl-names = "default"; - wps { + button-wps { label = "WPS Button"; linux,code = ; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi index f80af24b9e90..a86dbc490600 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi @@ -113,18 +113,18 @@ &pmx_power_auto_switch>; pinctrl-names = "default"; - option { + button-option { label = "Function Button"; linux,code = ; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; - reserved { + button-reserved { label = "Power-on Switch"; linux,code = ; linux,input-type = <5>; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - power { + button-power { label = "Power-auto Switch"; linux,code = ; linux,input-type = <5>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts index 5a77286136c7..0d5d85c873b5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -96,12 +96,12 @@ pinctrl-0 = <&pmx_keys>; pinctrl-names = "default"; - restart { + button-restart { label = "SWR Button"; linux,code = ; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS Button"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi index b5737026e244..d0f85893aeca 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi @@ -60,19 +60,19 @@ * esc and power represent a three position rocker * switch. Thus the conventional KEY_POWER does not fit */ - exc { + button-exc { label = "Back power switch (on|auto)"; linux,code = ; linux,input-type = <5>; gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; - power { + button-power { label = "Back power switch (auto|off)"; linux,code = ; linux,input-type = <5>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - option { + button-option { label = "Function button"; linux,code = ; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi index 51530ea86622..6cc068a05673 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -58,7 +58,7 @@ #address-cells = <1>; #size-cells = <0>; - power { + button-power { label = "Power push button"; linux,code = ; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts index 49da633a1bc0..767f34ab434e 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts @@ -40,19 +40,19 @@ pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = ; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; }; - copy { + button-copy { label = "Copy Button"; linux,code = ; gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi index ea3d36512e9f..bdce8a86ce51 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi @@ -68,17 +68,17 @@ pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; - copy { + button-copy { label = "Copy Button"; linux,code = ; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts index 8ea430168ea5..ef6d6d7a4008 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts @@ -118,7 +118,7 @@ #address-cells = <1>; #size-cells = <0>; - power { + button-power { label = "Init Button"; linux,code = ; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts index 5aa4669ae254..601760041c99 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts @@ -34,7 +34,7 @@ pinctrl-0 = <&pmx_button_eject>; pinctrl-names = "default"; - eject { + button-eject { debounce-interval = <50>; wakeup-source; linux,code = ; diff --git a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts index ad093324e075..6703e412c8e2 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts @@ -161,7 +161,7 @@ pinctrl-0 = <&pmx_button_power>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = ; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts index 30892c19aceb..859521b5b84e 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts @@ -40,12 +40,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = ; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts index aba1205981f1..3b0a4ed588e8 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts @@ -40,12 +40,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = ; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi index 717236853e45..126db753c8fe 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi @@ -41,12 +41,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = ; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = ; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; -- cgit v1.2.3-58-ga151 From 28be5af95a79c841e8dee5ec2cde990519c8df73 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:35 +0200 Subject: ARM: dts: marvell: kirkwood: drop incorrect address/size-cells in GPIO keys Bindings do not allow address/size-cells in GPIO keys and the GPIO keys is not a bus, see dtbs_check warnings: kirkwood-openblocks_a7.dtb: gpio_keys: '#address-cells', '#size-cells' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)... Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-dir665.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-iconnect.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi | 2 -- arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-t5325.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts | 2 -- arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi | 2 -- 21 files changed, 42 deletions(-) diff --git a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts index 2582b84d8415..92897f8b637b 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts @@ -58,8 +58,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; key-power { label = "Power push button"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts index e8eff0ba1c99..1d1f4cdedab2 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -176,8 +176,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; button-reset { label = "reset"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi index baea14c68520..20bcd031f3f5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi @@ -8,8 +8,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power &pmx_button_unmount &pmx_button_reset>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts index d76dbbce16f1..0f50eb2d5931 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts @@ -58,8 +58,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts index ea98ff13700e..a2782fe3d379 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts @@ -122,8 +122,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts index fa7ace071de8..91409ae949c4 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts @@ -147,8 +147,6 @@ }; gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_reset &pmx_button_power &pmx_button_otb>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi index b54c9980f636..8a11d2b9d449 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi @@ -88,8 +88,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_function &pmx_power_switch &pmx_power_auto_switch>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts index 3f97240fda74..ddefaf628501 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts @@ -33,8 +33,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi index a86dbc490600..c0f80146706d 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi @@ -107,8 +107,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_function &pmx_power_switch &pmx_power_auto_switch>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts index 0d5d85c873b5..fd3813ace0c1 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -91,8 +91,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_keys>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi index d0f85893aeca..d4edf2727388 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi @@ -53,8 +53,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; /* * esc and power represent a three position rocker diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi index 6cc068a05673..28f09f71b24d 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -55,8 +55,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; button-power { label = "Power push button"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts index 767f34ab434e..47deb93c90a5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts @@ -35,8 +35,6 @@ keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi index bdce8a86ce51..e9bd9c551af5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi @@ -63,8 +63,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts index ef6d6d7a4008..20c6290d2037 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts @@ -115,8 +115,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_gpio_init>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; button-power { label = "Init Button"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts index 946f0f453dd1..9c438f10f737 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts @@ -136,8 +136,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_gpio_init>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; button { label = "Init Button"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts index 601760041c99..b66fc4d57410 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts @@ -29,8 +29,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_eject>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts index 6703e412c8e2..a6e77a487d00 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts @@ -156,8 +156,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts index 859521b5b84e..a2e0ad4b84d8 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts @@ -35,8 +35,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts index 3b0a4ed588e8..35be6bce1dba 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts @@ -35,8 +35,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi index 126db753c8fe..f136059607b7 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi @@ -36,8 +36,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; -- cgit v1.2.3-58-ga151 From 9d0120b72b972fb564940a252d994864fb9d6524 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:36 +0200 Subject: ARM: dts: marvell: kirkwood: align LED node name with bindings Bindings expect the LED node names to follow certain pattern, see dtbs_check warnings: kirkwood-ds409slim.dtb: gpio-leds-alarm-12: 'hdd1-green' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- .../dts/marvell/kirkwood-blackarmor-nas220.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts | 4 +- arch/arm/boot/dts/marvell/kirkwood-d2net.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-dir665.dts | 16 +++--- arch/arm/boot/dts/marvell/kirkwood-dns320.dts | 10 ++-- arch/arm/boot/dts/marvell/kirkwood-dns325.dts | 10 ++-- arch/arm/boot/dts/marvell/kirkwood-dockstar.dts | 4 +- arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts | 6 +-- arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts | 20 ++++---- .../dts/marvell/kirkwood-guruplug-server-plus.dts | 8 +-- arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts | 6 +-- arch/arm/boot/dts/marvell/kirkwood-iconnect.dts | 14 +++--- .../boot/dts/marvell/kirkwood-iomega_ix2_200.dts | 8 +-- arch/arm/boot/dts/marvell/kirkwood-l-50.dts | 18 +++---- arch/arm/boot/dts/marvell/kirkwood-laplug.dts | 4 +- .../boot/dts/marvell/kirkwood-linksys-viper.dts | 4 +- arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi | 10 ++-- arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts | 12 ++--- .../boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts | 6 +-- arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi | 2 +- arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-nsa310.dts | 20 ++++---- arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts | 18 +++---- arch/arm/boot/dts/marvell/kirkwood-nsa320.dts | 18 +++---- arch/arm/boot/dts/marvell/kirkwood-nsa325.dts | 18 +++---- arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts | 4 +- .../dts/marvell/kirkwood-pogoplug-series-4.dts | 4 +- .../boot/dts/marvell/kirkwood-sheevaplug-esata.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts | 4 +- arch/arm/boot/dts/marvell/kirkwood-synology.dtsi | 58 +++++++++++----------- 30 files changed, 157 insertions(+), 157 deletions(-) diff --git a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts index f34c3897ff48..36b90c632fd6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts @@ -51,7 +51,7 @@ gpio-leds { compatible = "gpio-leds"; - blue-power { + led-blue-power { label = "nas220:blue:power"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts index 92897f8b637b..151edcd140a0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts @@ -69,11 +69,11 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "cloudbox:red:fail"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; - blue-sata { + led-blue-sata { label = "cloudbox:blue:sata"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-d2net.dts b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts index bd3b266dd766..fcce8730d3e3 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-d2net.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts @@ -37,7 +37,7 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "d2net_v2:red:fail"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts index 1d1f4cdedab2..2f6793f794cd 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -137,38 +137,38 @@ gpio-leds { compatible = "gpio-leds"; - blue-usb { + led-blue-usb { label = "dir665:blue:usb"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - blue-internet { + led-blue-internet { /* Can only be turned on if the Internet * Ethernet port has Link */ label = "dir665:blue:internet"; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - amber-internet { + led-amber-internet { label = "dir665:amber:internet"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - blue-wifi5g { + led-blue-wifi5g { label = "dir665:blue:5g"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; }; - blue-status { + led-blue-status { label = "dir665:blue:status"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - blue-wps { + led-blue-wps { label = "dir665:blue:wps"; gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; - amber-status { + led-amber-status { label = "dir665:amber:status"; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; - blue-24g { + led-blue-24g { label = "dir665:blue:24g"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns320.dts b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts index d6b0f418fd01..d8279e0c4c4f 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts @@ -24,24 +24,24 @@ &pmx_led_white_usb>; pinctrl-names = "default"; - blue-power { + led-blue-power { label = "dns320:blue:power"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - blue-usb { + led-blue-usb { label = "dns320:blue:usb"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - orange-l_hdd { + led-orange-l_hdd { label = "dns320:orange:l_hdd"; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - orange-r_hdd { + led-orange-r_hdd { label = "dns320:orange:r_hdd"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; - orange-usb { + led-orange-usb { label = "dns320:orange:usb"; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns325.dts b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts index 94d9c06cbbf5..7f396195e977 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts @@ -24,24 +24,24 @@ &pmx_led_white_usb>; pinctrl-names = "default"; - white-power { + led-white-power { label = "dns325:white:power"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - white-usb { + led-white-usb { label = "dns325:white:usb"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ }; - red-l_hdd { + led-red-l_hdd { label = "dns325:red:l_hdd"; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - red-r_hdd { + led-red-r_hdd { label = "dns325:red:r_hdd"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; - red-usb { + led-red-usb { label = "dns325:red:usb"; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts index 264938dfa4d9..090f1e2e5bb6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts @@ -42,12 +42,12 @@ pinctrl-0 = <&pmx_led_green &pmx_led_orange>; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "status:orange:fault"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts index 328516351e84..590bee3c561c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts @@ -85,15 +85,15 @@ &pmx_led_wifi_ap >; pinctrl-names = "default"; - bluetooth { + led-bluetooth { label = "dreamplug:blue:bluetooth"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wifi { + led-wifi { label = "dreamplug:green:wifi"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; - wifi-ap { + led-wifi-ap { label = "dreamplug:green:wifi_ap"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts index d4cb3cd3e2a2..d5ac4e3974da 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts @@ -85,44 +85,44 @@ >; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "status:orange:fault"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - left0 { + led-left0 { label = "status:white:left0"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - left1 { + led-left1 { label = "status:white:left1"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - left2 { + led-left2 { label = "status:white:left2"; gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - left3 { + led-left3 { label = "status:white:left3"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - right0 { + led-right0 { label = "status:white:right0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; - right1 { + led-right1 { label = "status:white:right1"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - right2 { + led-right2 { label = "status:white:right2"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; - right3 { + led-right3 { label = "status:white:right3"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts index dfb41393941d..d5aa8b505cc0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts @@ -59,19 +59,19 @@ &pmx_led_wmode_r &pmx_led_wmode_g >; pinctrl-names = "default"; - health-r { + led-health-r { label = "guruplug:red:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; - health-g { + led-health-g { label = "guruplug:green:health"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wmode-r { + led-wmode-r { label = "guruplug:red:wmode"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; - wmode-g { + led-wmode-g { label = "guruplug:green:wmode"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts index 0f50eb2d5931..018c6b8f3e8a 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts @@ -79,16 +79,16 @@ &pmx_led_usb_transfer>; pinctrl-names = "default"; - green-os { + led-green-os { label = "ib62x0:green:os"; gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - red-os { + led-red-os { label = "ib62x0:red:os"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; }; - usb-copy { + led-usb-copy { label = "ib62x0:red:usb_copy"; gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts index a2782fe3d379..91b46e77e0b6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts @@ -89,32 +89,32 @@ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - power-blue { + led-power-blue { label = "power:blue"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - power-red { + led-power-red { label = "power:red"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - usb1 { + led-usb1 { label = "usb1:blue"; gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - usb2 { + led-usb2 { label = "usb2:blue"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - usb3 { + led-usb3 { label = "usb3:blue"; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; - usb4 { + led-usb4 { label = "usb4:blue"; gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; - otb { + led-otb { label = "otb:blue"; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts index 91409ae949c4..039362152650 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts @@ -127,20 +127,20 @@ &pmx_led_rebuild &pmx_led_health >; pinctrl-names = "default"; - power_led { + led-power-led { label = "status:white:power_led"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - rebuild_led { + led-rebuild-led { label = "status:white:rebuild_led"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; - health_led { + led-health-led { label = "status:red:health_led"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; - backup_led { + led-backup-led { label = "status:blue:backup_led"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts index 094854743dde..974bc9de4702 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -97,52 +97,52 @@ leds { compatible = "gpio-leds"; - status_green { + led-status-green { label = "l-50:green:status"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - status_red { + led-status-red { label = "l-50:red:status"; gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; }; - wifi { + led-wifi { label = "l-50:green:wifi"; gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy0tpt"; }; - internet_green { + led-internet-green { label = "l-50:green:internet"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; }; - internet_red { + led-internet-red { label = "l-50:red:internet"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; }; - usb1_green { + led-usb1-green { label = "l-50:green:usb1"; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; trigger-sources = <&hub_port3>; }; - usb1_red { + led-usb1-red { label = "l-50:red:usb1"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; }; - usb2_green { + led-usb2-green { label = "l-50:green:usb2"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; trigger-sources = <&hub_port1>; }; - usb2_red { + led-usb2-red { label = "l-50:red:usb2"; gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts index 8296486a5931..90ea6cdee8e0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts @@ -61,11 +61,11 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "laplug_v2:red:power"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - blue-power { + led-blue-power { label = "laplug_v2:blue:power"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts index ddefaf628501..8a1c38ab6111 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts @@ -54,12 +54,12 @@ pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; pinctrl-names = "default"; - white-health { + led-white-health { label = "viper:white:health"; gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; }; - white-pulse { + led-white-pulse { label = "viper:white:pulse"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi index c0f80146706d..5e0b139dd4fb 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi @@ -137,28 +137,28 @@ &pmx_led_function_blue>; pinctrl-names = "default"; - func_blue { + led-func-blue { label = "lsxl:blue:func"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - alarm { + led-alarm { label = "lsxl:red:alarm"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - info { + led-info { label = "lsxl:amber:info"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "lsxl:blue:power"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - func_red { + led-func-red { label = "lsxl:red:func"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts index e87ea7146546..6533b49a15b2 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts @@ -114,36 +114,36 @@ >; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; }; - user1o { + led-user1o { label = "user1:orange"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user1g { + led-user1g { label = "user1:green"; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user0o { + led-user0o { label = "user0:orange"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user0g { + led-user0g { label = "user0:green"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; default-state = "on"; }; - misc { + led-misc { label = "status:orange:misc"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts index fd3813ace0c1..e3b41784c876 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -73,17 +73,17 @@ pinctrl-0 = <&pmx_leds &pmx_usb_led>; pinctrl-names = "default"; - green-status { + led-green-status { label = "gtw:green:Status"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; }; - red-status { + led-red-status { label = "gtw:red:Status"; gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "gtw:green:USB"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi index 28f09f71b24d..d6b615cf6390 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -66,7 +66,7 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "ns2:red:fail"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts index b0cb5907ed63..686bcd6f0f3c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts @@ -24,7 +24,7 @@ gpio-leds { compatible = "gpio-leds"; - blue-sata { + led-blue-sata { label = "ns2:blue:sata"; gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; linux,default-trigger = "disk-activity"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts index c1799a07816e..3555ac1c3b15 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts @@ -87,43 +87,43 @@ &pmx_led_hdd_green &pmx_led_hdd_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa310:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - red-sys { + led-red-sys { label = "nsa310:red:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd { + led-green-hdd { label = "nsa310:green:hdd"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd { + led-red-hdd { label = "nsa310:red:hdd"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-esata { + led-green-esata { label = "nsa310:green:esata"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-esata { + led-red-esata { label = "nsa310:red:esata"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa310:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - red-usb { + led-red-usb { label = "nsa310:red:usb"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa310:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa310:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts index b85e314f045a..ddf84092aade 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts @@ -75,39 +75,39 @@ gpio-leds { compatible = "gpio-leds"; - green-sys { + led-green-sys { label = "nsa310:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - red-sys { + led-red-sys { label = "nsa310:red:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd { + led-green-hdd { label = "nsa310:green:hdd"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd { + led-red-hdd { label = "nsa310:red:hdd"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-esata { + led-green-esata { label = "nsa310:green:esata"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-esata { + led-red-esata { label = "nsa310:red:esata"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa310:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa310:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa310:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts index 652405e65006..dd5c8ffc8781 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts @@ -142,39 +142,39 @@ &pmx_led_hdd1_green &pmx_led_hdd1_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa320:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - orange-sys { + led-orange-sys { label = "nsa320:orange:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd1 { + led-green-hdd1 { label = "nsa320:green:hdd1"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd1 { + led-red-hdd1 { label = "nsa320:red:hdd1"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-hdd2 { + led-green-hdd2 { label = "nsa320:green:hdd2"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-hdd2 { + led-red-hdd2 { label = "nsa320:red:hdd2"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa320:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa320:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa320:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts index 371456de34b2..f0786a5f2ce6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts @@ -162,39 +162,39 @@ &pmx_led_hdd1_green &pmx_led_hdd1_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa325:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - orange-sys { + led-orange-sys { label = "nsa325:orange:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd1 { + led-green-hdd1 { label = "nsa325:green:hdd1"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd1 { + led-red-hdd1 { label = "nsa325:red:hdd1"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-hdd2 { + led-green-hdd2 { label = "nsa325:green:hdd2"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-hdd2 { + led-red-hdd2 { label = "nsa325:red:hdd2"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa325:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa325:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa325:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts index f9e95e55f36d..39a5345332da 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts @@ -33,12 +33,12 @@ gpio-leds { compatible = "gpio-leds"; - health { + led-health { label = "pogo_e02:green:health"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "pogo_e02:orange:fault"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts index b66fc4d57410..0e9c4cf79822 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts @@ -46,12 +46,12 @@ pinctrl-0 = <&pmx_led_green &pmx_led_red>; pinctrl-names = "default"; - health { + led-health { label = "pogoplugv4:green:health"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; default-state = "on"; }; - fault { + led-fault { label = "pogoplugv4:red:fault"; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts index ae8f493c9a0f..eb185273376e 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts @@ -33,7 +33,7 @@ pinctrl-0 = <&pmx_led_blue>; pinctrl-names = "default"; - health { + led-health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts index c73cc904e5c4..ce73fcf2255f 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts @@ -28,13 +28,13 @@ pinctrl-0 = <&pmx_led_blue &pmx_led_red>; pinctrl-names = "default"; - health { + led-health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - misc { + led-misc { label = "sheevaplug:red:misc"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi index 20964eb48fd7..6b7c5218b1fb 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi @@ -410,7 +410,7 @@ pinctrl-0 = <&pmx_alarmled_12>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:alarm"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; @@ -424,42 +424,42 @@ &pmx_hddled_26 &pmx_hddled_27>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; - hdd3-green { + led-hdd3-green { label = "synology:green:hdd3"; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; - hdd3-amber { + led-hdd3-amber { label = "synology:amber:hdd3"; gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; - hdd4-green { + led-hdd4-green { label = "synology:green:hdd4"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; }; - hdd4-amber { + led-hdd4-amber { label = "synology:amber:hdd4"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; @@ -471,12 +471,12 @@ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; @@ -488,22 +488,22 @@ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; @@ -518,52 +518,52 @@ &pmx_hddled_45>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; - hdd3-green { + led-hdd3-green { label = "synology:green:hdd3"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; - hdd3-amber { + led-hdd3-amber { label = "synology:amber:hdd3"; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; - hdd4-green { + led-hdd4-green { label = "synology:green:hdd4"; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - hdd4-amber { + led-hdd4-amber { label = "synology:amber:hdd4"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - hdd5-green { + led-hdd5-green { label = "synology:green:hdd5"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; }; - hdd5-amber { + led-hdd5-amber { label = "synology:amber:hdd5"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; @@ -575,22 +575,22 @@ pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3-58-ga151 From 85860863a4b2c216f399896d4fb1ec75b2dea64f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:37 +0200 Subject: ARM: dts: marvell: orion: align GPIO keys node name with bindings Bindings expect the GPIO key node names to follow certain pattern, see dtbs_check warnings: orion5x-lacie-d2-network.dtb: gpio-keys: 'front_button', 'power_rocker_sw_off', 'power_rocker_sw_on' do not match any of the regexes: '^(button|event|key|switch| ... Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts | 7 ++++--- arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts | 2 +- arch/arm/boot/dts/marvell/orion5x-lswsgl.dts | 7 ++++--- arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts | 5 +++-- arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts | 2 +- 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts index 03471d30bfd9..3d6c5af0e843 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts @@ -37,20 +37,21 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - front_button { + + button-front { label = "Front Push Button"; linux,code = ; gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; }; - power_rocker_sw_on { + switch-power-rocker-sw-on { label = "Power rocker switch (on|auto)"; linux,input-type = <5>; /* EV_SW */ linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; }; - power_rocker_sw_off { + switch-power-rocker-sw-off { label = "Power rocker switch (auto|off)"; linux,input-type = <5>; /* EV_SW */ linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts index ee751995c8d0..624b737a8be4 100644 --- a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts @@ -61,7 +61,7 @@ }; gpio_keys { - func { + func-button { label = "Function Button"; linux,code = ; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts index 2fbc17d6dfa4..e2829fb0c8b2 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -76,20 +76,21 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - func { + + key-func { label = "Function Button"; linux,code = ; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - power { + key-power { label = "Power-on Switch"; linux,input-type = <5>; /* EV_SW */ linux,code = ; /* LSMINI_SW_POWER */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; }; - autopower { + key-autopower { label = "Power-auto Switch"; linux,input-type = <5>; /* EV_SW */ linux,code = ; /* LSMINI_SW_AUTOPOWER */ diff --git a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts index d57859998350..90ce5fa883a4 100644 --- a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts @@ -37,13 +37,14 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - power { + + key-power { label = "Power"; linux,code = ; gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; }; - reset { + key-reset { label = "Reset"; linux,code = ; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts index fb203e7d37f5..d63ea15539aa 100644 --- a/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts @@ -35,7 +35,7 @@ pinctrl-0 = <&pmx_reset_button>; pinctrl-names = "default"; - reset { + key-reset { label = "Reset Button"; linux,code = ; gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; -- cgit v1.2.3-58-ga151 From 7d751583a086123768be06ef8acdec7a516ffcbc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:38 +0200 Subject: ARM: dts: marvell: orion: drop incorrect address/size-cells in GPIO keys Bindings do not allow address/size-cells in GPIO keys and the GPIO keys is not a bus, see dtbs_check warnings: orion5x-lacie-ethernet-disk-mini-v2.dtb: gpio-keys: '#address-cells', '#size-cells' do not match any of the regexes: '^(button|event|key|switch|... Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi | 2 -- arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts | 2 -- arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts | 5 ++--- arch/arm/boot/dts/marvell/orion5x-lswsgl.dts | 2 -- arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts | 2 -- 5 files changed, 2 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi index c2d87ba6190a..055ac754c5fd 100644 --- a/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi +++ b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi @@ -48,8 +48,6 @@ / { gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_power_switch>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts index 3d6c5af0e843..12a4aac2633e 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts @@ -35,8 +35,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; button-front { label = "Front Push Button"; diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts index f17e25ac98dd..a7586370b1d5 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -39,9 +39,8 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_power_button>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { + + button-1 { label = "Power-on Switch"; linux,code = ; gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts index e2829fb0c8b2..35dffb24b8b5 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -74,8 +74,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; key-func { label = "Function Button"; diff --git a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts index 90ce5fa883a4..cb1bd24b7ae3 100644 --- a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts @@ -35,8 +35,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; key-power { label = "Power"; -- cgit v1.2.3-58-ga151 From d8fff5ef3ef5345cc68b470e59832339890d2fd3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:39 +0200 Subject: ARM: dts: marvell: orion5x-lswsgl: use 'gpios' property for LEDs The 'gpio' property in GPIO LEDs is deprecated, as reported by dtbs_check: orion5x-lswsgl.dtb: gpio-leds: led-alarm: Unevaluated properties are not allowed ('gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/orion5x-lswsgl.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts index 35dffb24b8b5..802cd6ff6169 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -104,22 +104,22 @@ alarm { label = "lswsgl:alarm:red"; - gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; }; info { label = "lswsgl:info:amber"; - gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; func { label = "lswsgl:func:blue:top"; - gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; }; power { label = "lswsgl:power:blue:bottom"; - gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; }; -- cgit v1.2.3-58-ga151 From 5b3566a75f2d749fbfef5fb4f5acfd1754333252 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 16:56:40 +0200 Subject: ARM: dts: marvell: orion: align LED node name with bindings Bindings expect the LED node names to follow certain pattern, see dtbs_check warnings: orion5x-lswsgl.dtb: gpio-leds: led-alarm: Unevaluated properties are not allowed ('gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts | 2 +- arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts | 2 +- arch/arm/boot/dts/marvell/orion5x-lswsgl.dts | 8 ++++---- arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts index a7586370b1d5..f81acb9b7223 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -52,7 +52,7 @@ pinctrl-0 = <&pmx_power_led>; pinctrl-names = "default"; - led@1 { + led-1 { label = "power:blue"; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts index 624b737a8be4..79fee048c900 100644 --- a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts @@ -90,7 +90,7 @@ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; - func { + func-led { label = "lschl:func:blue:top"; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts index 802cd6ff6169..e0da406c430f 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -102,22 +102,22 @@ &pmx_led_power>; pinctrl-names = "default"; - alarm { + led-alarm { label = "lswsgl:alarm:red"; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; }; - info { + led-info { label = "lswsgl:info:amber"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; - func { + led-func { label = "lswsgl:func:blue:top"; gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "lswsgl:power:blue:bottom"; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; diff --git a/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts index fd78aa02a3c5..75ab913b21e5 100644 --- a/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts +++ b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts @@ -32,7 +32,7 @@ pinctrl-0 = <&pmx_debug_led>; pinctrl-names = "default"; - led@0 { + led-0 { label = "rd88f5182:cpu"; linux,default-trigger = "heartbeat"; gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3-58-ga151 From 3333d21af6fade5215bf0803fd8ef3c4c9d46fd4 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 17 Jun 2024 11:14:18 +0200 Subject: ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards Define the GIC interrupt (PPI 15) to be used on ST STM32MP15x boards for OP-TEE async notif. Signed-off-by: Etienne Carriere Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index 306e1bc2a514..847b360f02fc 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -62,6 +62,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 956da5f26c1c..43280289759d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -68,6 +68,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 8e4b0db198c2..6f27d794d270 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -67,6 +67,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 72b9cab2d990..6ae391bffee5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -72,6 +72,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; -- cgit v1.2.3-58-ga151 From 710d4f79bd430aec8c2b1edbd54b4370ac0b5f1b Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 13 Jun 2024 10:02:28 +0200 Subject: ARM: dts: stm32: Document output pins for PWMs on stm32mp135f-dk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To simplify identifying the pins where the PWM output is routed to, add a comment to each PWM device about the respective pin on the expansion connector. Signed-off-by: Uwe Kleine-König Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 970de441fbaa..faccdda588e5 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -374,6 +374,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */ pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -389,6 +390,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */ pinctrl-0 = <&pwm4_pins_a>; pinctrl-1 = <&pwm4_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -404,6 +406,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */ pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -417,6 +420,7 @@ &timers14 { status = "disabled"; pwm { + /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */ pinctrl-0 = <&pwm14_pins_a>; pinctrl-1 = <&pwm14_sleep_pins_a>; pinctrl-names = "default", "sleep"; -- cgit v1.2.3-58-ga151 From 0872f840edc9a163a9be46760f81631a8c7efa0f Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:07 +0200 Subject: ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13 Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d..e1a764d269d2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -979,6 +979,12 @@ ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1505,6 +1511,38 @@ status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 3e394c8e58b9..73e470019ce4 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -68,4 +68,35 @@ }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + access-controllers = <&etzpc 49>; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; -- cgit v1.2.3-58-ga151 From fbbfbdfe03522c72f22cb79b7bd920b99bc7c674 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:08 +0200 Subject: ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 22cd07196499..fc56be60cfcd 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -172,6 +172,77 @@ }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ -- cgit v1.2.3-58-ga151 From e9442f1fa4d2545dd6c0aaf7cb7a125cb04f8f2f Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:09 +0200 Subject: ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board Ethernet1: RMII with crystal Ethernet2: RMII with no cristal, need "phy-supply" property to work, today this property was managed by Ethernet glue, but should be present and managed in PHY node. So I will push second Ethernet in next step. PHYs used are SMSC (LAN8742A) Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index faccdda588e5..1af335a39993 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,7 @@ compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -172,6 +173,28 @@ }; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reg = <0>; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; -- cgit v1.2.3-58-ga151 From bf016e1db918ae5574b1f0e6d1fe844f9f125498 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 27 Jun 2024 14:27:49 +0200 Subject: ARM: dts: stm32: order stm32mp13-pinctrl nodes Keep alphabetic order for pins definition nodes for a better read. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 130 ++++++++++++++-------------- 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index fc56be60cfcd..0f3b752620bb 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -19,6 +19,13 @@ }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = , /* ADC1_INP2 */ + ; /* ADC1_INP11 */ + }; + }; + dcmipp_pins_a: dcmi-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -52,35 +59,6 @@ }; }; - goodix_pins_a: goodix-0 { - /* - * touchscreen reset needs to be configured - * via the pinctrl not the driver (a pull-down resistor - * has been soldered onto the reset line which forces - * the touchscreen to reset state). - */ - pins1 { - pinmux = ; - output-high; - bias-pull-up; - }; - /* - * Interrupt line must have a pull-down resistor - * in order to freeze the i2c address at 0x5D - */ - pins2 { - pinmux = ; - bias-pull-down; - }; - }; - - adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { - pins { - pinmux = , /* ADC1_INP2 */ - ; /* ADC1_INP11 */ - }; - }; - eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -127,6 +105,42 @@ }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -172,42 +186,6 @@ }; }; - eth1_rmii_pins_a: eth1-rmii-0 { - pins1 { - pinmux = , /* ETH_RMII_TXD0 */ - , /* ETH_RMII_TXD1 */ - , /* ETH_RMII_TX_EN */ - , /* ETH_RMII_REF_CLK */ - , /* ETH_MDIO */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = , /* ETH_RMII_RXD0 */ - , /* ETH_RMII_RXD1 */ - ; /* ETH_RMII_CRS_DV */ - bias-disable; - }; - - }; - - eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { - pins1 { - pinmux = , /* ETH_RMII_TXD0 */ - , /* ETH_RMII_TXD1 */ - , /* ETH_RMII_TX_EN */ - , /* ETH_RMII_REF_CLK */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RMII_RXD0 */ - , /* ETH_RMII_RXD1 */ - ; /* ETH_RMII_CRS_DV */ - }; - }; - eth2_rmii_pins_a: eth2-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -243,6 +221,28 @@ }; }; + goodix_pins_a: goodix-0 { + /* + * touchscreen reset needs to be configured + * via the pinctrl not the driver (a pull-down resistor + * has been soldered onto the reset line which forces + * the touchscreen to reset state). + */ + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + /* + * Interrupt line must have a pull-down resistor + * in order to freeze the i2c address at 0x5D + */ + pins2 { + pinmux = ; + bias-pull-down; + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ -- cgit v1.2.3-58-ga151 From 1b02383c385b16b4b275e30a3dd5860c0fd95c4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Jun 2024 21:51:56 +0200 Subject: ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board. This carrier board is populated with two gigabit ethernet ports and two Realtek RTL8211F PHYs, both are described in this DT patch. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 5f4f6b6e427a..bacb70b4256b 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -22,6 +22,8 @@ "st,stm32mp135"; aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; serial2 = &usart1; serial3 = &usart2; }; @@ -72,6 +74,60 @@ }; }; +ðernet1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð1_rgmii_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðernet2 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy2: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + &gpioa { gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", -- cgit v1.2.3-58-ga151 From 7253ddc6a38d39951d3f06cbf80bbfe236dae3e8 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 31 May 2024 17:07:12 +0200 Subject: arm64: dts: st: add HPDMA nodes on stm32mp251 The High Performance Direct Memory Access (HPDMA) controller is used to perform programmable data transfers between memory-mapped peripherals and memories (or between memories) via linked-lists. There are 3 instances of HPDMA on stm32mp251, using stm32-dma3 driver, with 16 channels per instance and with one interrupt per channel. Channels 0 to 7 are implemented with a FIFO of 8 bytes. Channels 8 to 11 are implemented with a FIFO of 32 bytes. Channels 12 to 15 are implemented with a FIFO of 128 bytes. Thanks to stm32-dma3 bindings, the user can ask for a channel with specific FIFO size. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 69 ++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 96d6de29c14c..2fe1c2bc2c2e 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -125,6 +125,75 @@ interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + rifsc: bus@42080000 { compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; -- cgit v1.2.3-58-ga151 From ed4dd5b795738a14ceb58299b6456c84b0ad6c5e Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:13 +0200 Subject: arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25 Both instances ethernet based on GMAC SNPS IP on stm32mp25. GMAC IP version is SNPS 5.3 Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 49 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 51 ++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 2fe1c2bc2c2e..16e95f76bd95 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -497,6 +497,55 @@ access-controllers = <&rifsc 76>; status = "disabled"; }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; bsec: efuse@44000000 { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 652e41facb35..eeceb086252b 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -41,3 +41,54 @@ &optee { interrupts = ; }; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; -- cgit v1.2.3-58-ga151 From b4c354b1b226af0855b43cdae8fbb0361995e407 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:14 +0200 Subject: arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsi Add pinctrl entry related to ETH2 in stm32mp25-pinctrl.dtsi ethernet2: RGMII with crystal. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 4e677e64c406..8fdd5f020425 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,65 @@ #include &pinctrl { + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins5 { + pinmux = ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ -- cgit v1.2.3-58-ga151 From e0fc47d897fbf89bd556a898624490e7171f3adb Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:15 +0200 Subject: arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 board ETHERNET2 instance is connected to Realtek PHY in RGMII mode Ethernet is SNSP IP with GMAC5 version. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 18c6266532b2..68c8cb25d5a1 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -17,6 +17,7 @@ compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; aliases { + ethernet0 = ðernet2; serial0 = &usart2; serial1 = &usart6; }; @@ -56,6 +57,29 @@ status = "okay"; }; +ðernet2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + max-speed = <1000>; + phy-handle = <&phy0_eth2>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; -- cgit v1.2.3-58-ga151 From 81e7b432f144155d791ae4ed8cb0ef78ddb532cf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 5 Jul 2024 11:36:35 +0200 Subject: ARM: dts: stm32: omit unused pinctrl groups from stm32mp13 dtb files stm32mp13-pinctrl.dtsi contains nearly all pinctrl groups collected from all boards. Most of them end up unused by a board and only waste binary space. Add /omit-if-no-ref/ to the groups to scrub the unused groups from the dtbs. Use the following regex to update the file and drop two useless newlines too: s@^\t[^:]\+: [^ ]\+ {$@\t/omit-if-no-ref/\r&@ Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 92 ++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 0f3b752620bb..c9f588a65094 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -6,12 +6,14 @@ #include &pinctrl { + /omit-if-no-ref/ adc1_pins_a: adc1-pins-0 { pins { pinmux = ; /* ADC1 in12 */ }; }; + /omit-if-no-ref/ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = , /* ADC1 in6 */ @@ -19,6 +21,7 @@ }; }; + /omit-if-no-ref/ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { pins { pinmux = , /* ADC1_INP2 */ @@ -26,6 +29,7 @@ }; }; + /omit-if-no-ref/ dcmipp_pins_a: dcmi-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -43,6 +47,7 @@ }; }; + /omit-if-no-ref/ dcmipp_sleep_pins_a: dcmi-sleep-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -59,6 +64,7 @@ }; }; + /omit-if-no-ref/ eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -83,9 +89,9 @@ ; /* ETH_RGMII_RX_CLK */ bias-disable; }; - }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -105,6 +111,7 @@ }; }; + /omit-if-no-ref/ eth1_rmii_pins_a: eth1-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -124,9 +131,9 @@ ; /* ETH_RMII_CRS_DV */ bias-disable; }; - }; + /omit-if-no-ref/ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -141,6 +148,7 @@ }; }; + /omit-if-no-ref/ eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -167,6 +175,7 @@ }; }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -186,6 +195,7 @@ }; }; + /omit-if-no-ref/ eth2_rmii_pins_a: eth2-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -207,6 +217,7 @@ }; }; + /omit-if-no-ref/ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -221,6 +232,7 @@ }; }; + /omit-if-no-ref/ goodix_pins_a: goodix-0 { /* * touchscreen reset needs to be configured @@ -243,6 +255,7 @@ }; }; + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -253,6 +266,7 @@ }; }; + /omit-if-no-ref/ i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = , /* I2C1_SCL */ @@ -260,6 +274,7 @@ }; }; + /omit-if-no-ref/ i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -270,6 +285,7 @@ }; }; + /omit-if-no-ref/ i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = , /* I2C5_SCL */ @@ -277,6 +293,7 @@ }; }; + /omit-if-no-ref/ i2c5_pins_b: i2c5-1 { pins { pinmux = , /* I2C5_SCL */ @@ -287,6 +304,7 @@ }; }; + /omit-if-no-ref/ i2c5_sleep_pins_b: i2c5-sleep-1 { pins { pinmux = , /* I2C5_SCL */ @@ -294,6 +312,7 @@ }; }; + /omit-if-no-ref/ ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ @@ -324,6 +343,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = , /* LCD_CLK */ @@ -351,6 +371,7 @@ }; }; + /omit-if-no-ref/ m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -364,6 +385,7 @@ }; }; + /omit-if-no-ref/ m_can1_sleep_pins_a: m_can1-sleep-0 { pins { pinmux = , /* CAN1_TX */ @@ -371,6 +393,7 @@ }; }; + /omit-if-no-ref/ m_can2_pins_a: m-can2-0 { pins1 { pinmux = ; /* CAN2_TX */ @@ -384,6 +407,7 @@ }; }; + /omit-if-no-ref/ m_can2_sleep_pins_a: m_can2-sleep-0 { pins { pinmux = , /* CAN2_TX */ @@ -391,6 +415,7 @@ }; }; + /omit-if-no-ref/ mcp23017_pins_a: mcp23017-0 { pins { pinmux = ; @@ -398,6 +423,7 @@ }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH4 */ @@ -407,12 +433,14 @@ }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = ; /* TIM3_CH4 */ }; }; + /omit-if-no-ref/ pwm4_pins_a: pwm4-0 { pins { pinmux = ; /* TIM4_CH2 */ @@ -422,12 +450,14 @@ }; }; + /omit-if-no-ref/ pwm4_sleep_pins_a: pwm4-sleep-0 { pins { pinmux = ; /* TIM4_CH2 */ }; }; + /omit-if-no-ref/ pwm5_pins_a: pwm5-0 { pins { pinmux = ; /* TIM5_CH3 */ @@ -437,12 +467,14 @@ }; }; + /omit-if-no-ref/ pwm5_sleep_pins_a: pwm5-sleep-0 { pins { pinmux = ; /* TIM5_CH3 */ }; }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH3 */ @@ -452,12 +484,14 @@ }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = ; /* TIM8_CH3 */ }; }; + /omit-if-no-ref/ pwm13_pins_a: pwm13-0 { pins { pinmux = ; /* TIM13_CH1 */ @@ -467,12 +501,14 @@ }; }; + /omit-if-no-ref/ pwm13_sleep_pins_a: pwm13-sleep-0 { pins { pinmux = ; /* TIM13_CH1 */ }; }; + /omit-if-no-ref/ pwm14_pins_a: pwm14-0 { pins { pinmux = ; /* TIM14_CH1 */ @@ -482,12 +518,14 @@ }; }; + /omit-if-no-ref/ pwm14_sleep_pins_a: pwm14-sleep-0 { pins { pinmux = ; /* TIM14_CH1 */ }; }; + /omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 { pins { pinmux = ; /* QSPI_CLK */ @@ -497,12 +535,14 @@ }; }; + /omit-if-no-ref/ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { pins { pinmux = ; /* QSPI_CLK */ }; }; + /omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 { pins { pinmux = , /* QSPI_BK1_IO0 */ @@ -515,6 +555,7 @@ }; }; + /omit-if-no-ref/ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { pins { pinmux = , /* QSPI_BK1_IO0 */ @@ -524,6 +565,7 @@ }; }; + /omit-if-no-ref/ qspi_cs1_pins_a: qspi-cs1-0 { pins { pinmux = ; /* QSPI_BK1_NCS */ @@ -533,12 +575,14 @@ }; }; + /omit-if-no-ref/ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { pins { pinmux = ; /* QSPI_BK1_NCS */ }; }; + /omit-if-no-ref/ sai1a_pins_a: sai1a-0 { pins { pinmux = , /* SAI1_SCK_A */ @@ -550,6 +594,7 @@ }; }; + /omit-if-no-ref/ sai1a_sleep_pins_a: sai1a-sleep-0 { pins { pinmux = , /* SAI1_SCK_A */ @@ -558,6 +603,7 @@ }; }; + /omit-if-no-ref/ sai1b_pins_a: sai1b-0 { pins { pinmux = ; /* SAI1_SD_B */ @@ -565,12 +611,14 @@ }; }; + /omit-if-no-ref/ sai1b_sleep_pins_a: sai1b-sleep-0 { pins { pinmux = ; /* SAI1_SD_B */ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -584,6 +632,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -602,6 +651,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -613,6 +663,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 { pins { pinmux = ; /* SDMMC1_CK */ @@ -622,6 +673,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = , /* SDMMC2_D0 */ @@ -635,6 +687,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { pins1 { pinmux = , /* SDMMC2_D0 */ @@ -653,6 +706,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pins { pinmux = , /* SDMMC2_D0 */ @@ -664,6 +718,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 { pins { pinmux = ; /* SDMMC2_CK */ @@ -673,6 +728,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = , /* SDMMC2_D4 */ @@ -685,6 +741,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { pins { pinmux = , /* SDMMC2_D4 */ @@ -694,6 +751,7 @@ }; }; + /omit-if-no-ref/ spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -709,6 +767,7 @@ }; }; + /omit-if-no-ref/ spi2_sleep_pins_a: spi2-sleep-0 { pins { pinmux = , /* SPI2_SCK */ @@ -717,6 +776,7 @@ }; }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -732,6 +792,7 @@ }; }; + /omit-if-no-ref/ spi3_sleep_pins_a: spi3-sleep-0 { pins { pinmux = , /* SPI3_SCK */ @@ -740,6 +801,7 @@ }; }; + /omit-if-no-ref/ spi5_pins_a: spi5-0 { pins1 { pinmux = , /* SPI5_SCK */ @@ -755,6 +817,7 @@ }; }; + /omit-if-no-ref/ spi5_sleep_pins_a: spi5-sleep-0 { pins { pinmux = , /* SPI5_SCK */ @@ -763,6 +826,7 @@ }; }; + /omit-if-no-ref/ stm32g0_intn_pins_a: stm32g0-intn-0 { pins { pinmux = ; @@ -770,6 +834,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -783,6 +848,7 @@ }; }; + /omit-if-no-ref/ uart4_idle_pins_a: uart4-idle-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -793,6 +859,7 @@ }; }; + /omit-if-no-ref/ uart4_sleep_pins_a: uart4-sleep-0 { pins { pinmux = , /* UART4_TX */ @@ -800,6 +867,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_b: uart4-1 { pins1 { pinmux = ; /* UART4_TX */ @@ -813,6 +881,7 @@ }; }; + /omit-if-no-ref/ uart4_idle_pins_b: uart4-idle-1 { pins1 { pinmux = ; /* UART4_TX */ @@ -823,6 +892,7 @@ }; }; + /omit-if-no-ref/ uart4_sleep_pins_b: uart4-sleep-1 { pins { pinmux = , /* UART4_TX */ @@ -830,6 +900,7 @@ }; }; + /omit-if-no-ref/ uart7_pins_a: uart7-0 { pins1 { pinmux = , /* UART7_TX */ @@ -845,6 +916,7 @@ }; }; + /omit-if-no-ref/ uart7_idle_pins_a: uart7-idle-0 { pins1 { pinmux = , /* UART7_TX */ @@ -862,6 +934,7 @@ }; }; + /omit-if-no-ref/ uart7_sleep_pins_a: uart7-sleep-0 { pins { pinmux = , /* UART7_TX */ @@ -871,6 +944,7 @@ }; }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -884,6 +958,7 @@ }; }; + /omit-if-no-ref/ uart8_idle_pins_a: uart8-idle-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -894,6 +969,7 @@ }; }; + /omit-if-no-ref/ uart8_sleep_pins_a: uart8-sleep-0 { pins { pinmux = , /* UART8_TX */ @@ -901,6 +977,7 @@ }; }; + /omit-if-no-ref/ usart1_pins_a: usart1-0 { pins1 { pinmux = , /* USART1_TX */ @@ -916,6 +993,7 @@ }; }; + /omit-if-no-ref/ usart1_idle_pins_a: usart1-idle-0 { pins1 { pinmux = , /* USART1_TX */ @@ -933,6 +1011,7 @@ }; }; + /omit-if-no-ref/ usart1_sleep_pins_a: usart1-sleep-0 { pins { pinmux = , /* USART1_TX */ @@ -942,6 +1021,7 @@ }; }; + /omit-if-no-ref/ usart1_pins_b: usart1-1 { pins1 { pinmux = ; /* USART1_TX */ @@ -955,6 +1035,7 @@ }; }; + /omit-if-no-ref/ usart1_idle_pins_b: usart1-idle-1 { pins1 { pinmux = ; /* USART1_TX */ @@ -965,6 +1046,7 @@ }; }; + /omit-if-no-ref/ usart1_sleep_pins_b: usart1-sleep-1 { pins { pinmux = , /* USART1_TX */ @@ -972,6 +1054,7 @@ }; }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -987,6 +1070,7 @@ }; }; + /omit-if-no-ref/ usart2_idle_pins_a: usart2-idle-0 { pins1 { pinmux = , /* USART2_TX */ @@ -1004,6 +1088,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = , /* USART2_TX */ @@ -1013,6 +1098,7 @@ }; }; + /omit-if-no-ref/ usart2_pins_b: usart2-1 { pins1 { pinmux = , /* USART2_TX */ @@ -1028,6 +1114,7 @@ }; }; + /omit-if-no-ref/ usart2_idle_pins_b: usart2-idle-1 { pins1 { pinmux = , /* USART2_TX */ @@ -1045,6 +1132,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_b: usart2-sleep-1 { pins { pinmux = , /* USART2_TX */ -- cgit v1.2.3-58-ga151 From 87b6426ab92efd91a17aed1f5b1d94f36938e28f Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:11 +0200 Subject: regulator: Add STM32MP25 regulator bindings These bindings will be used for the SCMI voltage domain. Signed-off-by: Pascal Paillet Acked-by: Krzysztof Kozlowski Acked-by: Mark Brown Signed-off-by: Alexandre Torgue --- .../dt-bindings/regulator/st,stm32mp25-regulator.h | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp25-regulator.h diff --git a/include/dt-bindings/regulator/st,stm32mp25-regulator.h b/include/dt-bindings/regulator/st,stm32mp25-regulator.h new file mode 100644 index 000000000000..3c3d30911dd0 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp25-regulator.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_VDDIO1 0 +#define VOLTD_SCMI_VDDIO2 1 +#define VOLTD_SCMI_VDDIO3 2 +#define VOLTD_SCMI_VDDIO4 3 +#define VOLTD_SCMI_VDDIO 4 +#define VOLTD_SCMI_UCPD 5 +#define VOLTD_SCMI_USB33 6 +#define VOLTD_SCMI_ADC 7 +#define VOLTD_SCMI_GPU 8 +#define VOLTD_SCMI_VREFBUF 9 + +/* STPMIC2 regulators */ +#define VOLTD_SCMI_STPMIC2_BUCK1 10 +#define VOLTD_SCMI_STPMIC2_BUCK2 11 +#define VOLTD_SCMI_STPMIC2_BUCK3 12 +#define VOLTD_SCMI_STPMIC2_BUCK4 13 +#define VOLTD_SCMI_STPMIC2_BUCK5 14 +#define VOLTD_SCMI_STPMIC2_BUCK6 15 +#define VOLTD_SCMI_STPMIC2_BUCK7 16 +#define VOLTD_SCMI_STPMIC2_LDO1 17 +#define VOLTD_SCMI_STPMIC2_LDO2 18 +#define VOLTD_SCMI_STPMIC2_LDO3 19 +#define VOLTD_SCMI_STPMIC2_LDO4 20 +#define VOLTD_SCMI_STPMIC2_LDO5 21 +#define VOLTD_SCMI_STPMIC2_LDO6 22 +#define VOLTD_SCMI_STPMIC2_LDO7 23 +#define VOLTD_SCMI_STPMIC2_LDO8 24 +#define VOLTD_SCMI_STPMIC2_REFDDR 25 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 26 +#define VOLTD_SCMI_REGU1 27 +#define VOLTD_SCMI_REGU2 28 +#define VOLTD_SCMI_REGU3 29 +#define VOLTD_SCMI_REGU4 30 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H */ -- cgit v1.2.3-58-ga151 From 387abbb94535a74dbbd37fcfb33094daa0c56129 Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:12 +0200 Subject: arm64: dts: st: add scmi regulators on stm32mp25 Add SCMI regulators description on STM32MP25. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 16e95f76bd95..1167cf63d7e8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -75,6 +76,40 @@ reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = ; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = ; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = ; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = ; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = ; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = ; + regulator-name = "vdda18adc"; + }; + }; + }; }; }; -- cgit v1.2.3-58-ga151 From 419ed754a3b6279f748909dd552fe425c7fce4a2 Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:13 +0200 Subject: arm64: dts: st: describe power supplies for stm32mp257f-ev1 board Describe power supplies for stm32mp257f-ev1 board. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 43 +++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 68c8cb25d5a1..214191a8322b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "stm32mp257.dtsi" #include "stm32mp25xf.dtsi" #include "stm32mp25-pinctrl.dtsi" @@ -42,14 +43,6 @@ no-map; }; }; - - vdd_sdcard: vdd-sdcard { - compatible = "regulator-fixed"; - regulator-name = "vdd_sdcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; &arm_wdt { @@ -100,6 +93,37 @@ status = "disabled"; }; +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -109,7 +133,8 @@ disable-wp; st,neg-edge; bus-width = <4>; - vmmc-supply = <&vdd_sdcard>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From cfa65ef7c84adafcbd1f9c7ba349812e1692d0a2 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 1 Jul 2024 13:30:09 +0200 Subject: ARM: dts: turris-omnia: Add MCU system-controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turris Omnia's MCU provides various features that can be configured over I2C at address 0x2a. Add device-tree node. This does not carry a Fixes tag - we do not want this to get backported to stable kernels for the following reason: U-Boot since v2022.10 inserts a phy-reset-gpio property into the WAN ethernet node pointing to the MCU node if it finds the MCU node with a cznic,turris-omnia-mcu compatible. Thus if this change got backported to a stable kernel, the WAN interface driver would defer probe indefinitely (since it would wait for the turris-omnia-mcu driver which would not be present). Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-385-turris-omnia.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 7b755bb4e4e7..59079d63fe27 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -218,7 +218,22 @@ #size-cells = <0>; reg = <0>; - /* STM32F0 command interface at address 0x2a */ + mcu: system-controller@2a { + compatible = "cznic,turris-omnia-mcu"; + reg = <0x2a>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcu_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_NONE>; + + gpio-controller; + #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + }; led-controller@2b { compatible = "cznic,turris-omnia-leds"; @@ -501,6 +516,11 @@ }; &pinctrl { + mcu_pins: mcu-pins { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pcawan_pins: pcawan-pins { marvell,pins = "mpp46"; marvell,function = "gpio"; -- cgit v1.2.3-58-ga151 From 731daaa5093d5c93c3b46dfbe46970cc52e15335 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 1 Jul 2024 13:30:10 +0200 Subject: ARM: dts: turris-omnia: Add GPIO key node for front button MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we have the MCU device-tree node, which acts as a GPIO controller, add GPIO key node for the front button. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 59079d63fe27..43202890c959 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -112,6 +112,19 @@ status = "disabled"; }; + gpio-keys { + compatible = "gpio-keys"; + + front-button { + label = "Front Button"; + linux,code = ; + linux,can-disable; + gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>; + /* debouncing is done by the microcontroller */ + debounce-interval = <0>; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; -- cgit v1.2.3-58-ga151 From a0342414431101629aece5d43f3cc83da71ff8cc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 17:03:39 +0200 Subject: arm64: dts: armada-3720: align GPIO keys node name with bindings Bindings expect the GPIO key node names to follow certain pattern, see dtbs_check warnings: armada-3720-gl-mv1000.dtb: keys: 'reset' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)... Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 63fbc8352161..07c14bf04b83 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -41,7 +41,7 @@ keys { compatible = "gpio-keys"; - reset { + button-reset { label = "reset"; linux,code = ; gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; -- cgit v1.2.3-58-ga151 From cf8b7454ec916449210f3e9670c871e525006d52 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Jul 2024 17:03:40 +0200 Subject: arm64: dts: armada-3720: align LED node name with bindings Bindings expect the LED node names to follow certain pattern, see dtbs_check warnings: armada-3720-gl-mv1000.dtb: leds: 'power', 'vpn', 'wan' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 07c14bf04b83..56930f2ce481 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -57,17 +57,17 @@ leds { compatible = "gpio-leds"; - vpn { + led-vpn { label = "green:vpn"; gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; }; - wan { + led-wan { label = "green:wan"; gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; }; - led_power: power { + led_power: led-power { label = "green:power"; gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; default-state = "on"; -- cgit v1.2.3-58-ga151 From 5f5eb24090bec383b32e39b9c61e45da82dd6812 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jul 2024 17:03:19 +0200 Subject: dt-bindings: arm64: marvell: add solidrun cn9130 som based boards Add bindings for SolidRun boards based on CN9130 SoM. Three boards are added in total: - Clearfog Base - Clearfog Pro - SolidWAN The Clearfog boards are identical to the older Armada 388 based boards, upgraded with a new SoM and SoC. However the feature set and performance characteristics are different, therefore compatible strings from armada 388 versions are not included. SolidWAN uses the same SoM adding a southbridge on the carrier. Since 2019 there are bindings in-tree for two boards based on cn9130 and 9131. These are extremely verbose by listing cn9132, cn9131, cn9130, ap807-quad, ap807 for the SoC alone. CN9130 SoC combines an application processor (ap807) and a communication processor (cp115) in a single package. The communication processor (short CP) is also available separately as a southbridge. It only functions in combination with the CN9130 SoC. Complete systems adding one or two southbridges are by convention called CN9131 and CN9132 respectively. Despite different naming all systems are built around the same SoC. Therefore marvell,cn9131 and marvell,cn9132 can be omitted. The number of CPs is part of a board's BoM and can be reflected in the board compatible string instead. Existing bindings also describe cn9130 as a specialisation of ap807-quad. Usually board-level compatibles stop at the SoC without going into silicon versions or individual dies. There is no programming model at this layer, and in particular not for parts of an SoC. Therefore the ap compatibles can also be omitted. Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/arm/marvell/armada-7k-8k.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 16d2e132d3d1..74d935ea279c 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -82,4 +82,14 @@ properties: - const: marvell,armada-ap807-quad - const: marvell,armada-ap807 + - description: + SolidRun CN9130 SoM based single-board computers + items: + - enum: + - solidrun,cn9130-clearfog-base + - solidrun,cn9130-clearfog-pro + - solidrun,cn9131-solidwan + - const: solidrun,cn9130-sr-som + - const: marvell,cn9130 + additionalProperties: true -- cgit v1.2.3-58-ga151 From 099e1d034f009ead74137c191f687f0a617520f8 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jul 2024 17:03:20 +0200 Subject: dt-bindings: arm64: marvell: add solidrun cn9132 CEX-7 evaluation board Add bindings for the SolidRun CN9132 COM-Express Type 7 evaluation board. The CEX is based on CN9130 SoC and includes two southbridges. Because CN9132 and 9131 are just names for different designs around the same SoC, no soc compatibles beside marvell,cn9130 are needed. Signed-off-by: Josua Mayer Acked-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 74d935ea279c..538d91be8857 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -92,4 +92,12 @@ properties: - const: solidrun,cn9130-sr-som - const: marvell,cn9130 + - description: + SolidRun CN9132 COM-Express Type 7 based single-board computers + items: + - enum: + - solidrun,cn9132-clearfog + - const: solidrun,cn9132-sr-cex7 + - const: marvell,cn9130 + additionalProperties: true -- cgit v1.2.3-58-ga151 From 1c510c7d82e52142953255896288eaac716efd72 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jul 2024 17:03:21 +0200 Subject: arm64: dts: add description for solidrun cn9130 som and clearfog boards Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro reference boards. The SoM has been designed as a pin-compatible replacement for the older Armada 388 based SoM. Therefore it supports the same boards and a similar feature set. Most notable upgrades: - 4x Cortex-A72 - 10Gbps SFP - Both eMMC and SD supported at the same time The developer first supporting this product at SolidRun decided to use different filenames for the DTBs: Armada 388 uses the full "clearfog" string while cn9130 uses the abbreviation "cf". This name is already hard-coded in pre-installed vendor u-boot and can not be changed easily. NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE: CN9130 SoM has a different footprint from Armada 388 SoM. Components on the carrier board below the SoM may collide causing damage, such as on Clearfog Base. Signed-off-by: Josua Mayer Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 2 + arch/arm64/boot/dts/marvell/cn9130-cf-base.dts | 178 ++++++++++++ arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts | 375 +++++++++++++++++++++++++ arch/arm64/boot/dts/marvell/cn9130-cf.dtsi | 197 +++++++++++++ arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 160 +++++++++++ 5 files changed, 912 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/cn9130-cf-base.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-cf.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 99b8cb3c49e1..019f2251d696 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -28,3 +28,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts new file mode 100644 index 000000000000..788a5c302b17 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9130 Clearfog Base. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9130-sr-som.dtsi" +#include "cn9130-cf.dtsi" + +/ { + model = "SolidRun CN9130 Clearfog Base"; + compatible = "solidrun,cn9130-clearfog-base", + "solidrun,cn9130-sr-som", "marvell,cn9130"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button-0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&cp0_gpio1 31 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; + + rfkill-m2-gnss { + compatible = "rfkill-gpio"; + label = "m.2 GNSS"; + radio-type = "gps"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>; + }; + + /* M.2 is B-keyed, so w-disable is for WWAN */ + rfkill-m2-wwan { + compatible = "rfkill-gpio"; + label = "m.2 WWAN"; + radio-type = "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SRDS #3 - SGMII 1GE */ +&cp0_eth1 { + phy = <&phy1>; + phys = <&cp0_comphy3 1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&cp0_eth2_phy { + /* + * Configure LEDs default behaviour: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (yellow) + * - LED[2]: high impedance (floating) + */ + marvell,reg-init = <3 16 0xf000 0x0a61>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; +}; + +&cp0_gpio1 { + sim-select-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sim-select"; + }; +}; + +&cp0_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + /* + * Configure LEDs default behaviour: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (yellow) + * - LED[2]: high impedance (floating) + * + * Configure LEDs electrical polarity + * - on-state: low + * - off-state: high (not hi-z, to avoid residual glow) + */ + marvell,reg-init = <3 16 0xf000 0x0a61>, + <3 17 0x003f 0x000a>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&cp0_pinctrl { + pinctrl-0 = <&sim_select_pins>; + pintrl-names = "default"; + + rear_button_pins: cp0-rear-button-pins { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sim_select_pins: cp0-sim-select-pins { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; +}; + +/* + * SRDS #4 - USB 3.0 host on M.2 connector + * USB-2.0 Host on Type-A connector + */ +&cp0_usb3_1 { + phys = <&cp0_comphy4 1>, <&cp0_utmi1>; + phy-names = "comphy", "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&expander0 { + m2-full-card-power-off-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-full-card-power-off"; + }; + + m2-reset-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-reset"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts new file mode 100644 index 000000000000..a27fe0042867 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9130 Clearfog Pro. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9130-sr-som.dtsi" +#include "cn9130-cf.dtsi" + +/ { + model = "SolidRun CN9130 Clearfog Pro"; + compatible = "solidrun,cn9130-clearfog-pro", + "solidrun,cn9130-sr-som", "marvell,cn9130"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&rear_button_pins>; + pinctrl-names = "default"; + + button-0 { + /* The rear SW3 button */ + label = "Rear Button"; + gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; +}; + +/* SRDS #3 - SGMII 1GE to L2 switch */ +&cp0_eth1 { + phys = <&cp0_comphy3 1>; + phy-mode = "sgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&cp0_eth2_phy { + /* + * Configure LEDs default behaviour similar to switch ports: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (red) + * - LED[2]: high impedance (floating) + * + * Switch port defaults: + * - LED0: link/activity: On/blink (green) + * - LED1: link is 1000Mbps: On (red) + * + * Identical configuration is impossible with hardware offload. + */ + marvell,reg-init = <3 16 0xf000 0x0a61>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + label = "LED2"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + label = "LED1"; + default-state = "keep"; + }; + }; +}; + +&cp0_mdio { + ethernet-switch@4 { + compatible = "marvell,mv88e6085"; + reg = <4>; + pinctrl-0 = <&dsa_clk_pins &dsa_pins>; + pinctrl-names = "default"; + reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; + interrupt-parent = <&cp0_gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan5"; + phy = <&switch0phy0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED12"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED11"; + default-state = "keep"; + }; + }; + }; + + ethernet-port@1 { + reg = <1>; + label = "lan4"; + phy = <&switch0phy1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED10"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED9"; + default-state = "keep"; + }; + }; + }; + + ethernet-port@2 { + reg = <2>; + label = "lan3"; + phy = <&switch0phy2>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED8"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED7"; + default-state = "keep"; + }; + }; + }; + + ethernet-port@3 { + reg = <3>; + label = "lan2"; + phy = <&switch0phy3>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED6"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED5"; + default-state = "keep"; + }; + }; + }; + + ethernet-port@4 { + reg = <4>; + label = "lan1"; + phy = <&switch0phy4>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED4"; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + label = "LED3"; + default-state = "keep"; + }; + }; + }; + + ethernet-port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp0_eth1>; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet-port@6 { + reg = <6>; + label = "lan6"; + phy-mode = "rgmii"; + + /* + * Because of mdio address conflict the + * external phy is not readable. + * Force a fixed link instead. + */ + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + switch0phy1: ethernet-phy@1 { + reg = <0x1>; + /* + * Indirectly configure default behaviour + * for port lan6 leds behind external phy. + * Internal PHYs are not using page 3, + * therefore writing to it is safe. + */ + marvell,reg-init = <3 16 0xf000 0x0a61>; + }; + + switch0phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + switch0phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + switch0phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + /* + * There is an external phy on the switch mdio bus. + * Because its mdio address collides with internal phys, + * it is not readable. + * + * mdio-external { + * compatible = "marvell,mv88e6xxx-mdio-external"; + * #address-cells = <1>; + * #size-cells = <0>; + * + * ethernet-phy@1 { + * reg = <0x1>; + * }; + * }; + */ + }; +}; + +/* SRDS #4 - miniPCIe (CON2) */ +&cp0_pcie1 { + num-lanes = <1>; + phys = <&cp0_comphy4 1>; + /* dw-pcie inverts internally */ + reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cp0_pinctrl { + dsa_clk_pins: cp0-dsa-clk-pins { + marvell,pins = "mpp40"; + marvell,function = "synce1"; + }; + + dsa_pins: cp0-dsa-pins { + marvell,pins = "mpp27", "mpp29"; + marvell,function = "gpio"; + }; + + rear_button_pins: cp0-rear-button-pins { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { + marvell,pins = "mpp12"; + marvell,function = "spi1"; + }; +}; + +&cp0_spi1 { + /* add pin for chip-select 1 on mikrobus */ + pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>; +}; + +/* USB-2.0 Host on Type-A connector */ +&cp0_usb3_1 { + phys = <&cp0_utmi1>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&expander0 { + /* CON2 */ + pcie1-0-clkreq-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie1.0-clkreq"; + }; + + /* CON2 */ + pcie1-0-w-disable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie1.0-w-disable"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi new file mode 100644 index 000000000000..ad0ab34b6602 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for common base of SolidRun CN9130 Clearfog Base and Pro. + * + */ + +/ { + aliases { + /* label nics same order as armada 388 clearfog */ + ethernet0 = &cp0_eth2; + ethernet1 = &cp0_eth1; + ethernet2 = &cp0_eth0; + i2c1 = &cp0_i2c1; + mmc1 = &cp0_sdhci0; + }; + + reg_usb3_vbus0: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; + regulator-name = "vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&cp0_i2c1>; + los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +/* SRDS #2 - SFP+ 10GE */ +&cp0_eth0 { + managed = "in-band-status"; + phys = <&cp0_comphy2 0>; + phy-mode = "10gbase-r"; + sfp = <&sfp>; + status = "okay"; +}; + +&cp0_i2c0 { + expander0: gpio-expander@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&expander0_pins>; + pinctrl-names = "default"; + interrupt-parent = <&cp0_gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + /* CON3 */ + pcie2-0-clkreq-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "pcie2.0-clkreq"; + }; + + /* CON3 */ + pcie2-0-w-disable-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie2.0-w-disable"; + }; + + usb3-ilimit-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + input; + line-name = "usb3-current-limit"; + }; + + m2-devslp-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "m.2 devslp"; + }; + }; + + /* The MCP3021 supports standard and fast modes */ + adc@4c { + compatible = "microchip,mcp3021"; + reg = <0x4c>; + }; + + carrier_eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <8>; + }; +}; + +&cp0_i2c1 { + /* + * Routed to SFP, M.2, mikrobus, and miniPCIe + * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with + * address pins tied low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C bus being present. + * PCIe uses ARP to assign addresses, or 0x63-0x64. + */ + clock-frequency = <100000>; + pinctrl-0 = <&cp0_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* SRDS #5 - miniPCIe (CON3) */ +&cp0_pcie2 { + num-lanes = <1>; + phys = <&cp0_comphy5 2>; + /* dw-pcie inverts internally */ + reset-gpios = <&expander0 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&cp0_pinctrl { + cp0_i2c1_pins: cp0-i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + + cp0_mmc0_pins: cp0-mmc0-pins { + marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + + mikro_spi_pins: cp0-spi1-cs1-pins { + marvell,pins = "mpp12"; + marvell,function = "spi1"; + }; + + mikro_uart_pins: cp0-uart-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "uart1"; + }; + + expander0_pins: cp0-expander0-pins { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; +}; + +/* SRDS #0 - SATA on M.2 connector */ +&cp0_sata0 { + phys = <&cp0_comphy0 1>; + status = "okay"; + + /* only port 1 is available */ + /delete-node/ sata-port@0; +}; + +/* microSD */ +&cp0_sdhci0 { + pinctrl-0 = <&cp0_mmc0_pins>; + pinctrl-names = "default"; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&cp0_spi1 { + /* CS1 for mikrobus */ + pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>; +}; + +/* + * SRDS #1 - USB-3.0 Host on Type-A connector + * USB-2.0 Host on mPCI-e connector (CON3) + */ +&cp0_usb3_0 { + phys = <&cp0_comphy1 0>, <&cp0_utmi0>; + phy-names = "comphy", "utmi"; + vbus-supply = <®_usb3_vbus0>; + dr_mode = "host"; + status = "okay"; +}; + +&cp0_utmi { + status = "okay"; +}; + +/* mikrobus uart */ +&cp0_uart0 { + pinctrl-0 = <&mikro_uart_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi new file mode 100644 index 000000000000..4676e3488f54 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Josua Mayer + * + */ + +#include + +/ { + model = "SolidRun CN9130 SoM"; + compatible = "solidrun,cn9130-sr-som", "marvell,cn9130"; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth1; + ethernet2 = &cp0_eth2; + i2c0 = &cp0_i2c0; + mmc0 = &ap_sdhci0; + rtc0 = &cp0_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* requires assembly of R9307 */ + vhv: regulator-vhv-1-8 { + compatible = "regulator-fixed"; + regulator-name = "vhv-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-0 = <&cp0_reg_vhv_pins>; + pinctrl-names = "default"; + gpios = <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ap_pinctrl { + ap_mmc0_pins: ap-mmc0-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12"; + marvell,function = "sdio"; + /* + * mpp12 is emmc reset, function should be sdio (hw_rst), + * but pinctrl-mvebu does not support this. + * + * From pinctrl-mvebu.h: + * "The name will be used to switch to this setting in DT description, e.g. + * marvell,function = "uart2". subname is only for debugging purposes." + */ + }; +}; + +&ap_sdhci0 { + bus-width = <8>; + pinctrl-0 = <&ap_mmc0_pins>; + pinctrl-names = "default"; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&cp0_ethernet { + status = "okay"; +}; + +/* for assembly with phy */ +&cp0_eth2 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_eth2_pins>; + phy-mode = "rgmii-id"; + phy = <&cp0_eth2_phy>; + status = "okay"; +}; + +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + som_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <8>; + }; +}; + +&cp0_mdio { + pinctrl-0 = <&cp0_mdio_pins>; + status = "okay"; + + /* assembly option */ + cp0_eth2_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi1_pins>; + /* max speed limited by a mux */ + spi-max-frequency = <1800000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + /* read command supports max. 50MHz */ + spi-max-frequency = <50000000>; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_eth2_pins: cp0-ge2-rgmii-pins { + marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", + "mpp48", "mpp49", "mpp50", "mpp51", + "mpp52", "mpp53", "mpp54", "mpp55"; + /* docs call it "ge2", but cp110-pinctrl "ge1" */ + marvell,function = "ge1"; + }; + + cp0_i2c0_pins: cp0-i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + + cp0_mdio_pins: cp0-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + + cp0_spi1_pins: cp0-spi1-pins { + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + + cp0_reg_vhv_pins: cp0-reg-vhv-pins { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + }; +}; + +/* AP default console */ +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 1280840d20305e01901fa4361d792c4a69704ac5 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jul 2024 17:03:22 +0200 Subject: arm64: dts: add description for solidrun cn9131 solidwan board Add description for the SolidRun CN9131 SolidWAN, based on CN9130 SoM with an extra communication processor on the carrier board. This board differentiates itself from CN9130 Clearfog by providing additional SoC native network interfaces and pci buses: 2x 10Gbps SFP+ 4x 1Gbps RJ45 1x miniPCI-E 1x m.2 b-key with sata, usb-2.0 and usb-3.0 1x m.2 m-key with pcie and usb-2.0 1x m.2 b-key with pcie, usb-2.0, usb-3.0 and 2x sim slots 1x mpcie with pcie only 2x type-a usb-2.0/3.0 Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 637 +++++++++++++++++++++ 2 files changed, 638 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 019f2251d696..16f9d7156d9f 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -30,3 +30,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts new file mode 100644 index 000000000000..b1ea7dcaed17 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9130 Clearfog Base. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9130-sr-som.dtsi" + +/* + * Instantiate the external CP115 + */ + +#define CP11X_NAME cp1 +#define CP11X_BASE f4000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f4600000 +#define CP11X_PCIE1_BASE f4620000 +#define CP11X_PCIE2_BASE f4640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE + +/ { + model = "SolidRun CN9131 SolidWAN"; + compatible = "solidrun,cn9131-solidwan", + "solidrun,cn9130-sr-som", "marvell,cn9130"; + + aliases { + ethernet0 = &cp1_eth1; + ethernet1 = &cp1_eth2; + ethernet2 = &cp0_eth1; + ethernet3 = &cp0_eth2; + ethernet4 = &cp0_eth0; + ethernet5 = &cp1_eth0; + gpio0 = &ap_gpio; + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + gpio3 = &cp1_gpio1; + gpio4 = &cp1_gpio2; + gpio5 = &expander0; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + i2c2 = &cp1_i2c1; + mmc0 = &ap_sdhci0; + mmc1 = &cp0_sdhci0; + rtc0 = &cp0_rtc; + rtc1 = &carrier_rtc; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_led_pins &cp1_led_pins>; + + /* for sfp-1 (J42) */ + led-sfp1-activity { + label = "sfp1:green"; + gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + /* for sfp-1 (J42) */ + led-sfp1-link { + label = "sfp1:yellow"; + gpios = <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + + /* (J28) */ + led-sfp0-activity { + label = "sfp0:green"; + gpios = <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>; + }; + + /* (J28) */ + led-sfp0-link { + label = "sfp0:yellow"; + gpios = <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>; + }; + }; + + /* Type-A port on J53 */ + reg_usb_a_vbus0: regulator-usb-a-vbus0 { + compatible = "regulator-fixed"; + pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>; + pinctrl-names = "default"; + regulator-name = "vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_a_vbus1: regulator-usb-a-vbus1 { + compatible = "regulator-fixed"; + pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>; + pinctrl-names = "default"; + regulator-name = "vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sfp0: sfp-0 { + compatible = "sff,sfp"; + pinctrl-0 = <&cp0_sfp0_pins>; + pinctrl-names = "default"; + i2c-bus = <&cp0_i2c1>; + los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; + + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cp1_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&cp1_i2c1>; + los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +/* SRDS #2 - SFP+ 10GE */ +&cp0_eth0 { + managed = "in-band-status"; + phy-mode = "10gbase-r"; + phys = <&cp0_comphy2 0>; + sfp = <&sfp0>; + status = "okay"; +}; + +/* SRDS #3 - SGMII 1GE */ +&cp0_eth1 { + managed = "in-band-status"; + phy-mode = "sgmii"; + /* Without mdio phy access rely on sgmii auto-negotiation. */ + phys = <&cp0_comphy3 1>; + status = "okay"; +}; + +/* SRDS #1 - SGMII */ +&cp0_eth2 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + managed = "in-band-status"; + phy-mode = "sgmii"; + phy = <&cp0_phy1>; + phys = <&cp0_comphy1 2>; +}; + +&cp0_gpio1 { + pcie0-0-w-disable-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "pcie0.0-w-disable"; + }; + + /* J34 */ + m2-full-card-power-off-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-full-card-power-off"; + }; +}; + +&cp0_i2c0 { + /* assembly option */ + fan-controller@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + expander0: gpio@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + + usb-a-vbus0-ilimit-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "vbus0-ilimit"; + }; + + /* duplicate connection, controlled by soc gpio */ + usb-vbus0-enable-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + line-name = "vbus0-enable"; + }; + + usb-a-vbus1-ilimit-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + input; + line-name = "vbus1-ilimit"; + }; + + /* duplicate connection, controlled by soc gpio */ + usb-vbus1-enable-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "vbus1-enable"; + }; + }; + + carrier_eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <8>; + }; + + /* usb-hub@60 */ + + /* assembly option */ + carrier_rtc: rtc@68 { + compatible = "st,m41t83"; + reg = <0x68>; + pinctrl-0 = <&cp1_rtc_pins>; + pinctrl-names = "default"; + interrupt-parent = <&cp1_gpio1>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>; + }; +}; + +&cp0_i2c1 { + /* + * Routed to SFP. + * Limit to 100kHz for compatibility with SFP modules, + * featuring AT24C01A/02/04 at addresses 0x50/0x51. + */ + clock-frequency = <100000>; + pinctrl-0 = <&cp0_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cp0_mdio { + /* + * SoM + Carrier each have a PHY at address 0. + * Remove the SoM phy node, and skip adding the carrier node. + * SGMII Auto-Negotation is enabled by bootloader for + * autonomous operation without mdio control. + */ + /delete-node/ ethernet-phy@0; + + /* U17016 */ + cp0_phy1: ethernet-phy@1 { + reg = <1>; + /* + * Configure LEDs default behaviour: + * - LED[0]: link is 1000Mbps: On (yellow) + * - LED[1]: link/activity: On/blink (green) + * - LED[2]: high impedance (floating) + */ + marvell,reg-init = <3 16 0xf000 0x0a17>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +/* SRDS #0 - miniPCIe */ +&cp0_pcie0 { + num-lanes = <1>; + phys = <&cp0_comphy0 0>; + status = "okay"; +}; + +/* SRDS #5 - M.2 B-Key (J34) */ +&cp0_pcie2 { + num-lanes = <1>; + phys = <&cp0_comphy5 2>; + status = "okay"; +}; + +&cp0_pinctrl { + pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>; + pinctrl-names = "default"; + + cp0_i2c1_pins: cp0-i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + + cp0_led_pins: cp0-led-pins { + marvell,pins = "mpp4", "mpp7"; + marvell,function = "gpio"; + }; + + cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + cp0_mmc0_pins: cp0-mmc0-pins { + marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + + cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + cp0_sfp0_pins: cp0-sfp0-pins { + marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34"; + marvell,function = "gpio"; + }; + + cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { + marvell,pins = "mpp12"; + marvell,function = "spi1"; + }; +}; + +/* microSD */ +&cp0_sdhci0 { + pinctrl-0 = <&cp0_mmc0_pins>; + pinctrl-names = "default"; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&cp0_spi1 { + /* add pin for chip-select 1 */ + pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>; + + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + /* read command supports max. 50MHz */ + spi-max-frequency = <50000000>; + }; +}; + +/* USB-2.0 Host to USB-Hub */ +&cp0_usb3_0 { + phys = <&cp0_utmi0>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +/* SRDS #4 - USB-3.0 Host to USB-Hub */ +&cp0_usb3_1 { + phys = <&cp0_comphy4 1>, <&cp0_utmi1>; + phy-names = "comphy", "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&cp0_utmi { + status = "okay"; +}; + +&cp0_utmi1 { + status = "disabled"; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* SRDS #4 - SFP+ 10GE */ +&cp1_eth0 { + managed = "in-band-status"; + phy-mode = "10gbase-r"; + phys = <&cp1_comphy4 0>; + sfp = <&sfp1>; + status = "okay"; +}; + +/* SRDS #3 - SGMII 1GE */ +&cp1_eth1 { + managed = "in-band-status"; + phy-mode = "sgmii"; + phy = <&cp1_phy0>; + phys = <&cp0_comphy3 1>; + status = "okay"; +}; + +/* SRDS #5 - SGMII 1GE */ +&cp1_eth2 { + managed = "in-band-status"; + phy-mode = "sgmii"; + phy = <&cp1_phy1>; + phys = <&cp0_comphy5 2>; + status = "okay"; +}; + +&cp1_gpio1 { + status = "okay"; + + /* J30 */ + m2-full-card-power-off-hog-0 { + gpio-hog; + gpios = <29 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-full-card-power-off"; + }; + + /* J44 */ + m2-full-card-power-off-hog-1 { + gpio-hog; + gpios = <30 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-full-card-power-off"; + }; +}; + +&cp1_gpio2 { + status = "okay"; +}; + +&cp1_i2c1 { + /* + * Routed to SFP. + * Limit to 100kHz for compatibility with SFP modules, + * featuring AT24C01A/02/04 at addresses 0x50/0x51. + */ + clock-frequency = <100000>; + pinctrl-0 = <&cp1_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cp1_mdio { + pinctrl-0 = <&cp1_mdio_pins>; + pinctrl-names = "default"; + status = "okay"; + + cp1_phy0: ethernet-phy@0 { + reg = <0>; + /* + * Configure LEDs default behaviour: + * - LED[0]: link is 1000Mbps: On (yellow) + * - LED[1]: link/activity: On/blink (green) + * - LED[2]: high impedance (floating) + */ + marvell,reg-init = <3 16 0xf000 0x0a17>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + cp1_phy1: ethernet-phy@1 { + reg = <1>; + /* + * Configure LEDs default behaviour: + * - LED[0]: link is 1000Mbps: On (yellow) + * - LED[1]: link/activity: On/blink (green) + * - LED[2]: high impedance (floating) + */ + marvell,reg-init = <3 16 0xf000 0x0a17>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +/* SRDS #0 - M.2 (J30) */ +&cp1_pcie0 { + num-lanes = <1>; + phys = <&cp1_comphy0 0>; + status = "okay"; +}; + +&cp1_rtc { + status = "disabled"; +}; + +/* SRDS #1 - SATA on M.2 (J44) */ +&cp1_sata0 { + phys = <&cp1_comphy1 0>; + status = "okay"; + + /* only port 0 is available */ + /delete-node/ sata-port@1; +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>; + pinctrl-names = "default"; + + cp1_i2c1_pins: cp0-i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + + cp1_led_pins: cp1-led-pins { + marvell,pins = "mpp54", "mpp55"; + marvell,function = "gpio"; + }; + + cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + + cp1_mdio_pins: cp1-mdio-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "ge"; + }; + + cp1_rtc_pins: cp1-rtc-pins { + marvell,pins = "mpp12", "mpp13"; + marvell,function = "gpio"; + }; + + cp1_sfp1_pins: cp1-sfp1-pins { + marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50"; + marvell,function = "gpio"; + }; + }; +}; + +/* + * SRDS #2 - USB-3.0 Host to M.2 (J44) + * USB-2.0 Host to M.2 (J30) + */ +&cp1_usb3_0 { + phys = <&cp1_comphy2 0>, <&cp1_utmi0>; + phy-names = "comphy", "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +/* USB-2.0 Host to M.2 (J44) */ +&cp1_usb3_1 { + phys = <&cp1_utmi1>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&cp1_utmi { + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From e9ff907f40768351a3a86f5aa9b819436ee0ef19 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 4 Jul 2024 17:03:23 +0200 Subject: arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board Add description for the SolidRun CN9132 COM-Express Type 7 module, and the Clearfog evaluation board. The COM-Express module includes: - CN9130 SoC - 2x 88F8215 Southbridges - eMMC - SPI Flash - DDR-4 SODIMM connector - 1GBase-T Ethernet PHY The Clearfog Evaluation board provides: - 1x 10Gbps SFP+ - 2x 5GBase-T RJ45 - 4x 1GBase-T RJ45 on DSA switch with 2.5Gbps cpu link - 1x full-size PCI-E x4 - 2x M.2 with PCI-E x1 - 1x M.2 with PCI-E x2 - 2x M.2 with PCI-E x1 and USB-2.0 - 1x M.2 with USB-2.0, USB-3.0 and 2x SIM slots - 1x mini-PCI-E x1 - 2x SATA (Laptop-Style connector with data and power) - 3x USB-3.0 Type-A - microSD slot Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 673 ++++++++++++++++++++++ arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi | 712 ++++++++++++++++++++++++ 3 files changed, 1386 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/cn9132-clearfog.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 16f9d7156d9f..ce751b5028e2 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -31,3 +31,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts new file mode 100644 index 000000000000..0f53745a6fa0 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9132 Clearfog. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9132-sr-cex7.dtsi" + +/ { + model = "SolidRun CN9132 Clearfog"; + compatible = "solidrun,cn9132-clearfog", + "solidrun,cn9132-sr-cex7", "marvell,cn9130"; + + aliases { + ethernet1 = &cp0_eth2; + ethernet2 = &cp0_eth0; + ethernet3 = &cp2_eth0; + ethernet4 = &cp1_eth0; + i2c7 = &carrier_mpcie_i2c; + i2c8 = &carrier_ptp_i2c; + mmc1 = &cp0_sdhci0; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_wake0_pins>; + + button-0 { + label = "SW2"; + gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>; + + /* LED11 */ + led-io-0 { + color = ; + function = LED_FUNCTION_DISK; + function-enumerator = <0>; + default-state = "off"; + gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + /* LED12 */ + led-io-1 { + color = ; + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + default-state = "off"; + gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + }; + + /* CON4 W_DISABLE1/W_DISABLE2 */ + rfkill-m2-wlan { + compatible = "rfkill-gpio"; + label = "m.2 wlan (CON4)"; + radio-type = "wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_10g_phy_rst_01_pins>; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>; + }; + + /* CON5 W_DISABLE1/W_DISABLE2 */ + rfkill-m2-wlan { + compatible = "rfkill-gpio"; + label = "m.2 wlan (CON5)"; + radio-type = "wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_10g_phy_rst_23_pins>; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + /* J21 W_DISABLE1 */ + rfkill-m2-wwan { + compatible = "rfkill-gpio"; + label = "m.2 wwan (J21)"; + radio-type = "wwan"; + pinctrl-names = "default"; + pinctrl-0 = <&cp2_rsvd3_pins>; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + /* J21 W_DISABLE1 */ + rfkill-m2-gnss { + compatible = "rfkill-gpio"; + label = "m.2 gnss (J21)"; + radio-type = "gps"; + pinctrl-names = "default"; + pinctrl-0 = <&cp2_rsvd8_pins>; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + /* J14 W_DISABLE */ + rfkill-mpcie-wlan { + compatible = "rfkill-gpio"; + label = "mpcie wlan (J14)"; + radio-type = "wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&cp2_rsvd2_pins>; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&com_10g_sfp_i2c0>; + pinctrl-names = "default"; + pinctrl-0 = <&com_10g_int0_pins>; + mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2000>; + }; +}; + +&com_smbus { + /* This bus is also routed to STM32 BMC Microcontroller (U2) */ + + power-sensor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + #io-channel-cells = <1>; + label = "vdd_12v0"; + shunt-resistor = <2000>; + }; + + adc@48 { + compatible = "ti,tla2021"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + /* supplied by chaoskey hardware noise generator circuit */ + channel@0 { + reg = <0>; + }; + }; +}; + +&cp0_eth_phy0 { + /* + * Configure LEDs default behaviour: + * - LED[0]: link is 1000Mbps: On (yellow): 0111 + * - LED[1]: link/activity: On/Blink (green): 0001 + * - LED[2]: Off (green): 1000 + */ + marvell,reg-init = <3 16 0xf000 0x0817>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + /* link */ + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + /* act */ + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + /* 1000 */ + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; + +/* SRDS #4 - 10GE */ +&cp0_eth0 { + phys = <&cp0_comphy4 0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp>; + status = "okay"; +}; + +&cp0_eth2 { + phy-mode = "2500base-x"; + phys = <&cp0_comphy5 2>; + status = "okay"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&cp0_i2c1 { + /* + * Both COM and Carrier Board have a PCA9547 i2c mux at 0x77. + * Describe them as a single device merging each child bus. + */ + + i2c-mux@77 { + i2c@0 { + /* Routed to Full PCIe (J4) */ + }; + + i2c@1 { + /* Routed to USB Hub (U29) */ + }; + + i2c@2 { + /* Routed to M.2 (CON4) */ + }; + + i2c@3 { + /* Routed to M.2 (CON5) */ + }; + + i2c@4 { + /* Routed to M.2 (J21) */ + }; + + carrier_mpcie_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + /* Routed to mini-PCIe (J14) */ + }; + + carrier_ptp_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + /* Routed to various optional PTP related components */ + }; + }; +}; + +&cp0_mdio { + ethernet-switch@4 { + compatible = "marvell,mv88e6085"; + reg = <4>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + sw_phy1: ethernet-phy@1 { + reg = <0x11>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x12>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x13>; + }; + + sw_phy4: ethernet-phy@4 { + reg = <0x14>; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&sw_phy1>; + phy-mode = "internal"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&sw_phy2>; + phy-mode = "internal"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&sw_phy3>; + phy-mode = "internal"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&sw_phy4>; + phy-mode = "internal"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&cp0_eth2>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +/* SRDS #0,#1,#2,#3 - PCIe */ +&cp0_pcie0 { + num-lanes = <4>; + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; + status = "okay"; +}; + +&cp0_pinctrl { + /* + * configure unused gpios exposed via pin headers: + * - J7-10: PWRBTN + */ + pinctrl-names = "default"; + pinctrl-0 = <&cp0_pwrbtn_pins>; +}; + +/* microSD */ +&cp0_sdhci0 { + pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>; + pinctrl-names = "default"; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&cp0_spi1 { + /* add CS1 */ + pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>; + + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + /* read command supports max. 50MHz */ + spi-max-frequency = <50000000>; + }; +}; + +/* J38 */ +&cp0_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_uart2_pins>; + status = "okay"; +}; + +&cp0_utmi { + /* M.2 "CON5" swaps D+/D- */ + swap-dx-lanes = <1>; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* SRDS #2 - 5GE */ +&cp1_eth0 { + phys = <&cp1_comphy2 0>; + phy-mode = "5gbase-r"; + phy = <&cp1_eth_phy0>; + managed = "in-band-status"; + status = "okay"; +}; + +/* SRDS #0,#1 - PCIe */ +&cp1_pcie0 { + num-lanes = <2>; + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; + status = "okay"; +}; + +/* SRDS #4 - PCIe */ +&cp1_pcie1 { + num-lanes = <1>; + phys = <&cp1_comphy4 1>; + status = "okay"; +}; + +/* SRDS #5 - PCIe */ +&cp1_pcie2 { + num-lanes = <1>; + phys = <&cp1_comphy5 2>; + status = "okay"; +}; + +&cp1_pinctrl { + /* + * configure unused gpios exposed via pin headers: + * - J7-8: RSVD16 + * - J7-10: THRM + * - J10-1: WAKE1 + * - J10-2: SATA_ACT + * - J10-8: THERMTRIP + */ + pinctrl-names = "default"; + pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>, + <&cp1_thrm_trip_pins &cp1_wake1_pins>; +}; + +/* SRDS #3 - SATA */ +&cp1_sata0 { + status = "okay"; + + /* only port 1 is available */ + /delete-node/ sata-port@0; + + sata-port@1 { + phys = <&cp1_comphy3 1>; + }; +}; + +&cp1_utmi { + /* M.2 "CON4" swaps D+/D- */ + swap-dx-lanes = <0>; +}; + +&cp1_xmdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_xmdio_pins>; + status = "okay"; + + cp1_eth_phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&com_10g_int1_pins>; + interrupt-parent = <&cp1_gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&cp2_ethernet { + status = "okay"; +}; + +/* SRDS #2 - 5GE */ +&cp2_eth0 { + phys = <&cp2_comphy2 0>; + phy-mode = "5gbase-r"; + phy = <&cp2_eth_phy0>; + managed = "in-band-status"; + status = "okay"; +}; + +&cp2_gpio1 { + pinctrl-names= "default"; + pinctrl-0 = <&cp2_rsvd9_pins>; + + /* J21 */ + m2-wwan-reset-hog { + gpio-hog; + gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + output-low; + line-name = "m2-wwan-reset"; + }; +}; + +/* SRDS #0 - PCIe */ +&cp2_pcie0 { + num-lanes = <1>; + phys = <&cp2_comphy0 0>; + status = "okay"; +}; + +/* SRDS #4 - PCIe */ +&cp2_pcie1 { + num-lanes = <1>; + phys = <&cp2_comphy4 1>; + status = "okay"; +}; + +/* SRDS #5 - PCIe */ +&cp2_pcie2 { + num-lanes = <1>; + phys = <&cp2_comphy5 2>; + status = "okay"; +}; + +&cp2_pinctrl { + /* + * configure unused gpios exposed via pin headers: + * - J7-1: RSVD10 + * - J7-3: RSVD11 + * - J7-5: RSVD56 + * - J7-6: RSVD7 + * - J7-7: RSVD27 + * - J10-3: RSVD31 + * - J10-5: RSVD5 + * - J10-6: RSVD32 + * - J10-7: RSVD0 + * - J10-9: RSVD1 + */ + pinctrl-names = "default"; + pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>, + <&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>, + <&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>, + <&cp2_rsvd56_pins>; +}; + +/* SRDS #3 - SATA */ +&cp2_sata0 { + status = "okay"; + + /* only port 1 is available */ + /delete-node/ sata-port@0; + + sata-port@1 { + phys = <&cp2_comphy3 1>; + }; +}; + +&cp2_xmdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp2_xmdio_pins>; + status = "okay"; + + cp2_eth_phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&com_10g_int2_pins>; + interrupt-parent = <&cp2_gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi new file mode 100644 index 000000000000..afc041c1c448 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Josua Mayer + * + */ + +#include + +/* + * Instantiate the first external CP115 + */ + +#define CP11X_NAME cp1 +#define CP11X_BASE f4000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f4600000 +#define CP11X_PCIE1_BASE f4620000 +#define CP11X_PCIE2_BASE f4640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE + +/* + * Instantiate the second external CP115 + */ + +#define CP11X_NAME cp2 +#define CP11X_BASE f6000000 +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 +#define CP11X_PCIE0_BASE f6600000 +#define CP11X_PCIE1_BASE f6620000 +#define CP11X_PCIE2_BASE f6640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE + +/ { + model = "SolidRun CN9132 COM Express Type 7 Module"; + compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130"; + + aliases { + ethernet0 = &cp0_eth1; + gpio3 = &cp1_gpio1; + gpio4 = &cp1_gpio2; + gpio5 = &cp2_gpio1; + gpio6 = &cp2_gpio2; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + i2c2 = &com_clkgen_i2c; + i2c3 = &com_10g_led_i2c; + i2c4 = &com_10g_sfp_i2c0; + i2c5 = &com_smbus; + i2c6 = &com_fanctrl_i2c; + mmc0 = &ap_sdhci0; + rtc0 = &cp0_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 51 102 153 204 255>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>; + pwms = <&cp0_gpio2 7 40000>; + interrupt-parent = <&cp0_gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ap_vhv: regulator-ap-vhv-1-8 { + compatible = "regulator-fixed"; + regulator-name = "ap-vhv-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-0 = <&cp0_reg_ap_vhv_pins>; + pinctrl-names = "default"; + gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cp_vhv: regulator-cp-vhv-1-8 { + compatible = "regulator-fixed"; + regulator-name = "cp-vhv-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-0 = <&cp0_reg_cp_vhv_pins>; + pinctrl-names = "default"; + gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ap_pinctrl { + ap_mmc0_pins: ap-mmc0-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12"; + marvell,function = "sdio"; + /* + * mpp12 is emmc reset, function should be sdio (hw_rst), + * but pinctrl-mvebu does not support this. + * + * From pinctrl-mvebu.h: + * "The name will be used to switch to this setting in DT description, e.g. + * marvell,function = "uart2". subname is only for debugging purposes." + */ + }; +}; + +&ap_sdhci0 { + bus-width = <8>; + pinctrl-0 = <&ap_mmc0_pins>; + pinctrl-names = "default"; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&ap_thermal_ic { + polling-delay = <1000>; + + trips { + ap_active: trip-active { + temperature = <40000>; + hysteresis = <4000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&ap_active>; + cooling-device = <&fan THERMAL_NO_LIMIT 4>; + }; + + map1 { + trip = <&ap_crit>; + cooling-device = <&fan 4 5>; + }; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_eth1_pins>; + phy-mode = "rgmii-id"; + phy = <&cp0_eth_phy0>; + status = "okay"; +}; + +&cp0_gpio1 { + status = "okay"; + + /* + * Tacho signal used as interrupt source by pwm-fan driver. + * Hog IO as input to ensure mvebu-gpio irq driver`s + * irq_set_type can succeed. + */ + pwm-tacho-irq-hog { + gpio-hog; + gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + input; + line-name = "fan-tacho"; + }; +}; + +&cp0_gpio2 { + status = "okay"; +}; + +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + com_eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + }; + + eeprom@53 { + compatible = "atmel,spd"; + reg = <0x53>; + }; +}; + +&cp0_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + i2c-mux-idle-disconnect; + #address-cells = <1>; + #size-cells = <0>; + + com_clkgen_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* clock-controller@6b */ + }; + + com_10g_led_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */ + }; + + com_10g_sfp_i2c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */ + }; + + com_smbus: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + /* Routed to B2B Connector as SBM_CLK/DAT */ + }; + + com_fanctrl_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + /* fan-controller@2f (assembly option) */ + }; + }; +}; + +&cp0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_mdio_pins>; + status = "okay"; + + cp0_eth_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi1_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + /* read command supports max. 50MHz */ + spi-max-frequency = <50000000>; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + com_10g_int0_pins: cp0-10g-int-pins { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + cp0_eth1_pins: cp0-eth1-pins { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + /* docs call it "ge1", but cp110-pinctrl "ge0" */ + marvell,function = "ge0"; + }; + + cp0_fan_pwm_pins: cp0-fan-pwm-pins { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + cp0_fan_tacho_pins: cp0-fan-tacho-pins { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + cp0_i2c0_pins: cp0-i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + + cp0_i2c1_pins: cp0-i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + + cp0_mdio_pins: cp0-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + + cp0_mmc0_pins: cp0-mmc0-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + + cp0_mmc0_cd_pins: cp0-mmc0-cd-pins { + marvell,pins = "mpp55"; + marvell,function = "sdio_cd"; + }; + + cp0_pwrbtn_pins: cp0-pwrbtn-pins { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins { + marvell,pins = "mpp53"; + marvell,function = "gpio"; + }; + + cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + + cp0_spi1_pins: cp0-spi1-pins { + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + + cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { + marvell,pins = "mpp12"; + marvell,function = "spi1"; + }; + + cp0_uart2_pins: cp0-uart2-pins { + marvell,pins = "mpp50", "mpp51"; + marvell,function = "uart2"; + }; + }; +}; + +&cp0_thermal_ic { + polling-delay = <1000>; + + trips { + cp0_active: trip-active { + temperature = <40000>; + hysteresis = <4000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&cp0_active>; + cooling-device = <&fan THERMAL_NO_LIMIT 4>; + }; + + map1 { + trip = <&cp0_crit>; + cooling-device = <&fan 4 5>; + }; + }; +}; + +/* USB-2.0 Host */ +&cp0_usb3_0 { + phys = <&cp0_utmi0>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +/* USB-2.0 Host */ +&cp0_usb3_1 { + phys = <&cp0_utmi1>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&cp0_utmi { + status = "okay"; +}; + +&cp1_gpio1 { + status = "okay"; +}; + +&cp1_gpio2 { + status = "okay"; +}; + +&cp1_rtc { + status = "disabled"; +}; + +&cp1_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_spi1_pins>; + status = "okay"; + + tpm@0 { + reg = <0>; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <10000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_tpm_irq_pins>; + interrupt-parent = <&cp1_gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&cp1_syscon0 { + cp1_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + com_10g_int1_pins: cp1-10g-int-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; + + cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + cp1_batlow_pins: cp1-batlow-pins { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + cp1_rsvd16_pins: cp1-rsvd16-pins { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + cp1_sata_act_pins: cp1-sata-act-pins { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + cp1_spi1_pins: cp1-spi1-pins { + marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + + cp1_thrm_irq_pins: cp1-thrm-irq-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cp1_thrm_trip_pins: cp1-thrm-trip-pins { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + cp1_tpm_irq_pins: cp1-tpm-irq-pins { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + cp1_wake0_pins: cp1-wake0-pins { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + cp1_wake1_pins: cp1-wake1-pins { + marvell,pins = "mpp51"; + marvell,function = "gpio"; + }; + + cp1_xmdio_pins: cp1-xmdio-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "xg"; + }; + }; +}; + +&cp1_thermal_ic { + polling-delay = <1000>; + + trips { + cp1_active: trip-active { + temperature = <40000>; + hysteresis = <4000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&cp1_active>; + cooling-device = <&fan THERMAL_NO_LIMIT 4>; + }; + + map1 { + trip = <&cp1_crit>; + cooling-device = <&fan 4 5>; + }; + }; +}; + +/* USB-2.0 Host */ +&cp1_usb3_0 { + phys = <&cp1_utmi0>; + phy-names = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&cp1_utmi { + status = "okay"; +}; + +&cp2_ethernet { + status = "okay"; +}; + +&cp2_gpio1 { + status = "okay"; +}; + +&cp2_gpio2 { + status = "okay"; +}; + +&cp2_rtc { + status = "disabled"; +}; + +&cp2_syscon0 { + cp2_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + com_10g_int2_pins: cp2-10g-int-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; + + cp2_rsvd0_pins: cp2-rsvd0-pins { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + cp2_rsvd1_pins: cp2-rsvd1-pins { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + cp2_rsvd2_pins: cp2-rsvd2-pins { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + cp2_rsvd3_pins: cp2-rsvd3-pins { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + cp2_rsvd4_pins: cp2-rsvd4-pins { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + cp2_rsvd5_pins: cp2-rsvd5-pins { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + cp2_rsvd7_pins: cp2-rsvd7-pins { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + cp2_rsvd8_pins: cp2-rsvd8-pins { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + cp2_rsvd9_pins: cp2-rsvd9-pins { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + cp2_rsvd10_pins: cp2-rsvd10-pins { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + cp2_rsvd11_pins: cp2-rsvd11-pins { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + cp2_rsvd27_pins: cp2-rsvd27-pins { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + cp2_rsvd31_pins: cp2-rsvd31-pins { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + cp2_rsvd32_pins: cp2-rsvd32-pins { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + cp2_rsvd55_pins: cp2-rsvd55-pins { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + cp2_rsvd56_pins: cp2-rsvd56-pins { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + cp2_xmdio_pins: cp2-xmdio-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "xg"; + }; + }; +}; + +&cp2_thermal_ic { + polling-delay = <1000>; + + trips { + cp2_active: trip-active { + temperature = <40000>; + hysteresis = <4000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&cp2_active>; + cooling-device = <&fan THERMAL_NO_LIMIT 4>; + }; + + map1 { + trip = <&cp2_crit>; + cooling-device = <&fan 4 5>; + }; + }; +}; + +/* USB-2.0/3.0 Host */ +&cp2_usb3_0 { + phys = <&cp2_utmi0>, <&cp2_comphy1 0>; + phy-names = "utmi", "comphy"; + dr_mode = "host"; + status = "okay"; +}; + +&cp2_utmi { + status = "okay"; +}; + +/* AP default console */ +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From c46a239a24908dda57031589f0db944a5d2e9246 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 3 Jul 2024 20:45:05 +0100 Subject: dt-bindings: arm: qcom: Add Lenovo Yoga Slim 7x Document the x1e80100 based Lenovo Yoga Slim 7x laptop. Signed-off-by: Srinivas Kandagatla Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240703-yoga-slim7x-v2-1-3b297dab8db1@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1c8643eeb2d1..626e48703bea 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1039,6 +1039,7 @@ properties: - items: - enum: - asus,vivobook-s15 + - lenovo,yoga-slim7x - qcom,x1e80100-crd - qcom,x1e80100-qcp - const: qcom,x1e80100 -- cgit v1.2.3-58-ga151 From 45247fe17db25594bec804f9db751635c7b6e473 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 3 Jul 2024 20:45:06 +0100 Subject: arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree Add an initial devicetree for the Lenovo Yoga slim 7x with support for Display, usb, keyboard, touchpad, touchscreen, PMICs, speaker audio, gpu, NVMe and remoteprocs. Signed-off-by: Srinivas Kandagatla Tested-by: Rob Clark Link: https://lore.kernel.org/r/20240703-yoga-slim7x-v2-2-3b297dab8db1@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 929 +++++++++++++++++++++ 2 files changed, 930 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e0babd642fa8..d7de2aea4748 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -261,4 +261,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts new file mode 100644 index 000000000000..fbff558f5b07 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -0,0 +1,929 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model = "Lenovo Yoga Slim 7x"; + compatible = "lenovo,yoga-slim7x", "qcom,x1e80100"; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Right-side port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Yoga-Slim7x"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@14 { + compatible = "hid-over-i2c"; + reg = <0x14>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcadsp8380.mbn", + "qcom/x1e80100/LENOVO/83ED/adsp_dtbs.elf"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qccdsp8380.mbn", + "qcom/x1e80100/LENOVO/83ED/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; +}; -- cgit v1.2.3-58-ga151 From 4ae4837871ee8c8b055cf8131f65d31ee4208fa0 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:41 +0530 Subject: arm64: dts: qcom: ipq6018: Disable SS instance in Parkmode for USB For Gen-1 targets like IPQ6018, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for IPQ6018 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 20bb9e3dd2e4 ("arm64: dts: qcom: ipq6018: add usb3 DT description") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index b3b98f050cfd..e1e45da7f787 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -704,6 +704,7 @@ clocks = <&xo>; clock-names = "ref"; tx-fifo-resize; + snps,parkmode-disable-ss-quirk; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; -- cgit v1.2.3-58-ga151 From dc6ba95c6c4400a84cca5b419b34ae852a08cfb5 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:42 +0530 Subject: arm64: dts: qcom: ipq8074: Disable SS instance in Parkmode for USB For Gen-1 targets like IPQ8074, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for IPQ8074 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 5e09bc51d07b ("arm64: dts: ipq8074: enable USB support") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 92682d3c9478..284a4553070f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -666,6 +666,7 @@ interrupts = ; phys = <&qusb_phy_0>, <&ssphy_0>; phy-names = "usb2-phy", "usb3-phy"; + snps,parkmode-disable-ss-quirk; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; @@ -715,6 +716,7 @@ interrupts = ; phys = <&qusb_phy_1>, <&ssphy_1>; phy-names = "usb2-phy", "usb3-phy"; + snps,parkmode-disable-ss-quirk; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; -- cgit v1.2.3-58-ga151 From 0046325ae52079b46da13a7f84dd7b2a6f7c38f8 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:43 +0530 Subject: arm64: dts: qcom: msm8998: Disable SS instance in Parkmode for USB For Gen-1 targets like MSM8998, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for MSM8998 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 026dad8f5873 ("arm64: dts: qcom: msm8998: Add USB-related nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-4-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 99f811a57ac5..7f44807b1b97 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2144,6 +2144,7 @@ interrupts = ; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&qusb2phy>, <&usb3phy>; phy-names = "usb2-phy", "usb3-phy"; snps,has-lpm-erratum; -- cgit v1.2.3-58-ga151 From fad58a41b84667cb6c9232371fc3af77d4443889 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:44 +0530 Subject: arm64: dts: qcom: sdm630: Disable SS instance in Parkmode for USB For Gen-1 targets like SDM630, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for SDM630 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-5-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 94057ebf767f..c7e3764a8cf3 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1302,6 +1302,7 @@ interrupts = ; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&qusb2phy0>, <&usb3_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; -- cgit v1.2.3-58-ga151 From 074992a1163295d717faa21d1818c4c19ef6e676 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:45 +0530 Subject: arm64: dts: qcom: sm6115: Disable SS instance in Parkmode for USB For Gen-1 targets like SM6115, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for SM6115 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-6-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index ac5f071a8db3..aec6ca5941c2 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1659,6 +1659,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + snps,parkmode-disable-ss-quirk; usb-role-switch; -- cgit v1.2.3-58-ga151 From c5d57eb7d06df16c07037cea5dacfd74d49d1833 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:46 +0530 Subject: arm64: dts: qcom: sm6350: Disable SS instance in Parkmode for USB For Gen-1 targets like SM6350, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for SM6350 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-7-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 46e122c4421c..84009b74aee7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1921,6 +1921,7 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; usb-role-switch; -- cgit v1.2.3-58-ga151 From 44ea1ae3cf95db97e10d6ce17527948121f1dd4b Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:47 +0530 Subject: arm64: dts: qcom: msm8996: Disable SS instance in Parkmode for USB For Gen-1 targets like MSM8996, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for MSM8996 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: 1e39255ed29d ("arm64: dts: msm8996: Add device node for qcom,dwc3") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-8-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2b20cedfe26c..0fd2b1b944a5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3101,6 +3101,7 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; tx-fifo-resize; }; }; -- cgit v1.2.3-58-ga151 From cf4d6d54eadb60d2ee4d31c9d92299f5e8dcb55c Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 4 Jul 2024 20:58:48 +0530 Subject: arm64: dts: qcom: sdm845: Disable SS instance in Parkmode for USB For Gen-1 targets like SDM845, it is seen that stressing out the controller in host mode results in HC died error: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up And at this instant only restarting the host mode fixes it. Disable SuperSpeed instance in park mode for SDM845 to mitigate this issue. Cc: stable@vger.kernel.org Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240704152848.3380602-9-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 23b101bb3842..54077549b9da 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4138,6 +4138,7 @@ iommus = <&apps_smmu 0x740 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; @@ -4213,6 +4214,7 @@ iommus = <&apps_smmu 0x760 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; -- cgit v1.2.3-58-ga151 From 81008068ee4f2c4c26e97a0404405bb4b450241b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 5 Jul 2024 09:43:11 +0200 Subject: arm64: dts: qcom: sm6350: Add missing qcom,non-secure-domain property By default the DSP domains are secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: efc33c969f23 ("arm64: dts: qcom: sm6350: Add ADSP nodes") Fixes: 8eb5287e8a42 ("arm64: dts: qcom: sm6350: Add CDSP nodes") Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240705-sm6350-fastrpc-fix-v2-1-89a43166c9bb@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 84009b74aee7..7986ddb30f6e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1323,6 +1323,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -1582,6 +1583,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-58-ga151 From 4d37847187b3fd7ff1fac23248a8ec11d89b3e55 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 5 Jul 2024 14:40:09 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Add PMK8003 thermals Configure the thermals for the XO_THERM thermistor connected to the PMK8003 (which is called PMK8350 in software). The ADC configuration for PMK8350_ADC7_AMUX_THM1_100K_PU has already been added in the past. The trip points can really only be considered as placeholders, more configuration with cooling etc. can be added later. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240705-fp4-thermals-v2-1-a4870a8d084f@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 4e67bb80a026..e263010c348c 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -136,6 +136,18 @@ }; }; }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; }; @@ -712,6 +724,17 @@ status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,hw-settle-time-us = <200>; + qcom,ratiometric; + }; +}; + &pmk8350_rtc { status = "okay"; }; -- cgit v1.2.3-58-ga151 From 8cf636a03260352853ff1c949f30c418600e7b2b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 5 Jul 2024 14:40:10 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Add PM6150L thermals Configure the thermals for the PA_THERM1, MSM_THERM, PA_THERM0, RFC_CAM_THERM, CAM_FLASH_THERM and QUIET_THERM thermistors connected to PM6150L. Due to hardware constraints we can only register 4 zones with pm6150l_adc_tm, the other 2 we can register via generic-adc-thermal. The trip points can really only be considered as placeholders, more configuration with cooling etc. can be added later. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240705-fp4-thermals-v2-2-a4870a8d084f@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 189 ++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index e263010c348c..2ee2561b57b1 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -93,6 +93,20 @@ }; }; + msm_therm_sensor: thermal-sensor-msm { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&pm6150l_adc ADC5_AMUX_THM2_100K_PU>; + io-channel-names = "sensor-channel"; + }; + + rear_cam_sensor: thermal-sensor-rear-cam { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&pm6150l_adc ADC5_GPIO2_100K_PU>; + io-channel-names = "sensor-channel"; + }; + thermal-zones { chg-skin-thermal { thermal-sensors = <&pm7250b_adc_tm 0>; @@ -118,6 +132,30 @@ }; }; + pa0-thermal { + thermal-sensors = <&pm6150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa1-thermal { + thermal-sensors = <&pm6150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + pm8008-thermal { polling-delay-passive = <100>; thermal-sensors = <&pm8008>; @@ -137,6 +175,64 @@ }; }; + quiet-thermal { + thermal-sensors = <&pm6150l_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-cam-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&rear_cam_sensor>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rfc-flash-thermal { + thermal-sensors = <&pm6150l_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&msm_therm_sensor>; + + trips { + trip0 { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <55000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + xo-thermal { thermal-sensors = <&pmk8350_adc_tm 0>; @@ -596,6 +692,91 @@ status = "okay"; }; +&pm6150l_adc { + pinctrl-0 = <&pm6150l_adc_default>; + pinctrl-names = "default"; + + channel@4d { + reg = ; + label = "pa_therm1"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@4e { + reg = ; + label = "msm_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@4f { + reg = ; + label = "pa_therm0"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@53 { + reg = ; + label = "rear_cam_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@54 { + reg = ; + label = "rear_cam_flash_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@55 { + reg = ; + label = "quiet_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; +}; + +&pm6150l_adc_tm { + status = "okay"; + + pa-therm1@0 { + reg = <0>; + io-channels = <&pm6150l_adc ADC5_AMUX_THM1_100K_PU>; + qcom,hw-settle-time-us = <200>; + qcom,ratiometric; + }; + + pa-therm0@1 { + reg = <1>; + io-channels = <&pm6150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,hw-settle-time-us = <200>; + qcom,ratiometric; + }; + + rear-cam-flash-therm@2 { + reg = <2>; + io-channels = <&pm6150l_adc ADC5_GPIO3_100K_PU>; + qcom,hw-settle-time-us = <200>; + qcom,ratiometric; + }; + + quiet-therm@3 { + reg = <3>; + io-channels = <&pm6150l_adc ADC5_GPIO4_100K_PU>; + qcom,hw-settle-time-us = <200>; + qcom,ratiometric; + }; +}; + &pm6150l_flash { status = "okay"; @@ -618,6 +799,14 @@ }; }; +&pm6150l_gpios { + pm6150l_adc_default: adc-default-state { + pins = "gpio6", "gpio7", "gpio10"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + &pm6150l_wled { qcom,switching-freq = <800>; qcom,current-limit-microamp = <20000>; -- cgit v1.2.3-58-ga151 From 134a4b2f3be287358542953c9540bee4296bf593 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 5 Jul 2024 20:04:43 +0530 Subject: arm64: dts: qcom: sc7280: Enable download mode register write Enable download mode setting for sc7280 which can help collect ramdump for this SoC. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240705143443.1491956-1-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 06d0e59e7125..3d8410683402 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -711,6 +711,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc7280", "qcom,scm"; + qcom,dload-mode = <&tcsr_2 0x13000>; }; }; -- cgit v1.2.3-58-ga151 From e3e169cd28d0ba80d25ad683e076b299a39e8526 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Thu, 6 Jun 2024 20:10:27 +0200 Subject: arm64: dts: qcom: pm6150: Add vibrator Add a node for the vibrator module found inside the PM6150. Signed-off-by: Jens Reidel Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240606181027.98537-3-adrian@travitia.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index b4f4d700800d..59524609fb1e 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -166,5 +166,11 @@ reg = <0x1 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm6150_vib: vibrator@5300 { + compatible = "qcom,pm6150-vib", "qcom,pmi632-vib"; + reg = <0x5300>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-58-ga151 From cfe9685473add0ae76952f0eb54489c3547db335 Mon Sep 17 00:00:00 2001 From: Satya Priya Kakitapalli Date: Thu, 9 May 2024 15:54:04 +0530 Subject: arm64: dts: qcom: sm8150: Add video clock controller node Add device node for video clock controller on Qualcomm SM8150 platform. Signed-off-by: Satya Priya Kakitapalli Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240509-videocc-sm8150-dt-node-v4-2-e9617f65e946@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p.dtsi b/arch/arm64/boot/dts/qcom/sa8155p.dtsi index ffb7ab695213..9e70effc72e1 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155p.dtsi @@ -38,3 +38,7 @@ */ compatible = "qcom,sa8155p-rpmhpd"; }; + +&videocc { + power-domains = <&rpmhpd SA8155P_CX>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2471b158c76e..3e236adb9397 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -3738,6 +3739,19 @@ }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sm8150-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + power-domains = <&rpmhpd SM8150_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + camnoc_virt: interconnect@ac00000 { compatible = "qcom,sm8150-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; -- cgit v1.2.3-58-ga151 From d1f1570f3d6db5d35642092a671812e62bfba79d Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 30 Apr 2024 12:12:10 +0530 Subject: dt-bindings: interconnect: Add Qualcomm IPQ9574 support Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework. Acked-by: Georgi Djakov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20240430064214.2030013-3-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++ include/dt-bindings/interconnect/qcom,ipq9574.h | 59 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h new file mode 100644 index 000000000000..42019335c7dd --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ9574_H +#define INTERCONNECT_QCOM_IPQ9574_H + +#define MASTER_ANOC_PCIE0 0 +#define SLAVE_ANOC_PCIE0 1 +#define MASTER_SNOC_PCIE0 2 +#define SLAVE_SNOC_PCIE0 3 +#define MASTER_ANOC_PCIE1 4 +#define SLAVE_ANOC_PCIE1 5 +#define MASTER_SNOC_PCIE1 6 +#define SLAVE_SNOC_PCIE1 7 +#define MASTER_ANOC_PCIE2 8 +#define SLAVE_ANOC_PCIE2 9 +#define MASTER_SNOC_PCIE2 10 +#define SLAVE_SNOC_PCIE2 11 +#define MASTER_ANOC_PCIE3 12 +#define SLAVE_ANOC_PCIE3 13 +#define MASTER_SNOC_PCIE3 14 +#define SLAVE_SNOC_PCIE3 15 +#define MASTER_USB 16 +#define SLAVE_USB 17 +#define MASTER_USB_AXI 18 +#define SLAVE_USB_AXI 19 +#define MASTER_NSSNOC_NSSCC 20 +#define SLAVE_NSSNOC_NSSCC 21 +#define MASTER_NSSNOC_SNOC_0 22 +#define SLAVE_NSSNOC_SNOC_0 23 +#define MASTER_NSSNOC_SNOC_1 24 +#define SLAVE_NSSNOC_SNOC_1 25 +#define MASTER_NSSNOC_PCNOC_1 26 +#define SLAVE_NSSNOC_PCNOC_1 27 +#define MASTER_NSSNOC_QOSGEN_REF 28 +#define SLAVE_NSSNOC_QOSGEN_REF 29 +#define MASTER_NSSNOC_TIMEOUT_REF 30 +#define SLAVE_NSSNOC_TIMEOUT_REF 31 +#define MASTER_NSSNOC_XO_DCD 32 +#define SLAVE_NSSNOC_XO_DCD 33 +#define MASTER_NSSNOC_ATB 34 +#define SLAVE_NSSNOC_ATB 35 +#define MASTER_MEM_NOC_NSSNOC 36 +#define SLAVE_MEM_NOC_NSSNOC 37 +#define MASTER_NSSNOC_MEMNOC 38 +#define SLAVE_NSSNOC_MEMNOC 39 +#define MASTER_NSSNOC_MEM_NOC_1 40 +#define SLAVE_NSSNOC_MEM_NOC_1 41 + +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_IMEM_QSB 6 +#define SLAVE_NSSNOC_IMEM_QSB 7 +#define MASTER_NSSNOC_IMEM_AHB 8 +#define SLAVE_NSSNOC_IMEM_AHB 9 + +#endif /* INTERCONNECT_QCOM_IPQ9574_H */ -- cgit v1.2.3-58-ga151 From 5d0ab61a700214366dfcca5893b87655261e8c94 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 30 Apr 2024 12:12:14 +0530 Subject: arm64: dts: qcom: ipq9574: Add icc provider ability to gcc IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20240430064214.2030013-7-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 04ba09a9156c..48dfafea46a7 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -315,6 +316,7 @@ <0>; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 { -- cgit v1.2.3-58-ga151 From c1842643a3df6004d1bc9df74e34d8b72997d886 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 6 Jul 2024 15:00:30 -0700 Subject: ARM: dts: qcom: msm8960: correct memory base DeviceTree validation requires a unit address on the memory node, adjust the base to match [Ref] and use this as unit address. The bootloader will update the information with the actual values during boot. Ref: https://github.com/msm8916-mainline/lk2nd/blob/main/target/msm8960/rules.mk Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20240706220041.241839-1-david@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index a9c6d2dbb460..ebc43c5c6e5f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -47,9 +47,9 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; - reg = <0x0 0x0>; + reg = <0x80000000 0>; }; cpu-pmu { -- cgit v1.2.3-58-ga151 From 2c69048c5dafb315e11c257f7100f7fb3cabfa8a Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sun, 23 Jun 2024 14:26:30 +0500 Subject: dt-bindings: arm: qcom: Add msm8916 based LG devices Add compatible values for the msm8916 based LG smartphones. Signed-off-by: Nikita Travkin Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240623-msm8916-lg-initial-v1-1-6fbcf714d69b@trvn.ru Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 626e48703bea..f08e13b61172 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -210,6 +210,8 @@ properties: - asus,z00l - gplus,fl8005a - huawei,g7 + - lg,c50 + - lg,m216 - longcheer,l8910 - longcheer,l8150 - motorola,harpia -- cgit v1.2.3-58-ga151 From 0655b447461607f93c55435b32a7783aa7d711ef Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Sun, 23 Jun 2024 14:26:31 +0500 Subject: arm64: dts: qcom: msm8916-lg-m216: Add initial device tree This commit adds initial support for the LG K10 smartphone. Support for the following features is included: - Serial - Keys - Battery and charger - Accelerometer, magnetometer - Touchscreen - Sound and modem - Haptic Signed-off-by: Cristian Cozzolino [Nikita: Minor cleanup] Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240623-msm8916-lg-initial-v1-2-6fbcf714d69b@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts | 251 +++++++++++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d7de2aea4748..66c46fe668ad 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-lg-m216.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts new file mode 100644 index 000000000000..07345e694f6f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include + +/ { + model = "LG K10 (K420n)"; + compatible = "lg,m216", "qcom,msm8916"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + battery: battery { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3300000>; + voltage-max-design-microvolt = <4350000>; + energy-full-design-microwatt-hours = <8800000>; + charge-full-design-microamp-hours = <2300000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = <4342000 100>, <4266000 95>, <4206000 90>, + <4148000 85>, <4094000 80>, <4046000 75>, <3994000 70>, + <3956000 65>, <3916000 60>, <3866000 55>, <3831000 50>, + <3808000 45>, <3789000 40>, <3776000 35>, <3769000 30>, + <3760000 25>, <3740000 20>, <3712000 16>, <3684000 13>, + <3676000 11>, <3674000 10>, <3672000 9>, <3669000 8>, + <3665000 7>, <3660000 6>, <3643000 5>, <3602000 4>, + <3542000 3>, <3458000 2>, <3326000 1>, <3000000 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down-button { + label = "Volume Down"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + accelerometer@11 { + compatible = "bosch,bmc150_accel"; + reg = <0x11>; + + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; + + magnetometer@13 { + compatible = "bosch,bmc150_magn"; + reg = <0x13>; + + interrupts-extended = <&tlmm 69 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&magn_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + ce-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x4a00000>; +}; + +&pm8916_bms { + monitored-battery = <&battery>; + power-supplies = <&pm8916_charger>; + + status = "okay"; +}; + +&pm8916_charger { + qcom,fast-charge-safe-current = <700000>; + qcom,fast-charge-safe-voltage = <4300000>; + + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm8916_codec { + qcom,micbias1-ext-cap; + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 100 120 180 500>; + qcom,mbhc-vthreshold-high = <75 100 120 180 500>; + qcom,hphl-jack-type-normally-open; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; +}; + +&usb { + dr_mode = "peripheral"; + extcon = <&pm8916_charger>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_charger>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + magn_int_default: magn-int-default-state { + pins = "gpio69"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_default: touchscreen-default-state { + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ce-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; -- cgit v1.2.3-58-ga151 From 88bf3be9c327f2d78c65e7e4c10c677d4b36128a Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 23 Jun 2024 14:26:32 +0500 Subject: arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE Add initial device-tree for LG Leon LTE (lg-c50), currently supported features: - eMMC; - MicroSD; - usb in peripheral mode; - WiFi/BT; - vibration; - keys. Signed-off-by: Anton Bambura Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240623-msm8916-lg-initial-v1-3-6fbcf714d69b@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts | 140 ++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 66c46fe668ad..0e5c810304fb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-lg-c50.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-lg-m216.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts new file mode 100644 index 000000000000..a823a1c40208 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" + +#include + +/ { + model = "LG Leon LTE"; + compatible = "lg,c50", "qcom,msm8916"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down-button { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reg_sd_vmmc: regulator-sdcard-vmmc { + compatible = "regulator-fixed"; + regulator-name = "sdcard-vmmc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; + enable-active-high; + + startup-delay-us = <5000>; + + pinctrl-0 = <&sd_vmmc_en_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&pm8916_usbin { + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <®_sd_vmmc>; + + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&usb { + dr_mode = "peripheral"; + extcon = <&pm8916_usbin>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_vmmc_en_default: sd-vmmc-en-default-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; -- cgit v1.2.3-58-ga151 From dbdadc14b94e1c0326a430c1f84592a9b5c6b6d2 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Thu, 4 Jul 2024 21:18:33 +0200 Subject: arm64: dts: rockchip: Add avdd supplies to hdmi on rock64 Pine64's Rock64 was missing the avdd supply properties on the hdmi node, causing the following warnings: dwhdmi-rockchip ff3c0000.hdmi: supply avdd-0v9 not found, using dummy regulator dwhdmi-rockchip ff3c0000.hdmi: supply avdd-1v8 not found, using dummy regulator In the Rock64 Schematic document version 2.0 those supplies are marked as DVIDEO_AVDD_1V0 and DVIDEO_AVDD_1V8 respectively, but in version 3.0 those are named HDMI_AVDD_1V0 and HDMI_AVDD_1V8, which is a bit clearer. In both versions those are connected to LDO3 and LDO1 respectively. While the DeviceTree property is named 'avdd-0v9-supply' the 'rockchip,dw-hdmi.yaml' binding document notes the following: A 0.9V supply that powers up the SoC internal circuitry. The actual pin name varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes HDMI_AVDD_1V0. So the 'vdd_10' reference is not an error. Signed-off-by: Diederik de Haas Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20240704191919.38856-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 229fe9da9c2d..90fef766f3ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -154,6 +154,8 @@ }; &hdmi { + avdd-0v9-supply = <&vdd_10>; + avdd-1v8-supply = <&vcc_18>; status = "okay"; }; -- cgit v1.2.3-58-ga151 From 3087576e1c706bcd3623b48478ea8c9b23173107 Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Fri, 5 Jul 2024 18:22:14 +0200 Subject: arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices Similar to bf6f26deb0e8 ("arm64: dts: rockchip: Add dma-names to uart1 on quartz64-b") also add the dma-names property to the other rk3566 devices from Pine64 with bluetooth functionality. Signed-off-by: Diederik de Haas Tested-by: Riley Trautman Link: https://lore.kernel.org/r/20240705163004.29678-4-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 + arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index d899087bf0b5..ae2536c65a83 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -674,6 +674,7 @@ }; &uart1 { + dma-names = "tx", "rx"; pinctrl-0 = <&uart1m0_ctsn>, <&uart1m0_rtsn>, <&uart1m0_xfer>; pinctrl-names = "default"; uart-has-rtscts; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 0b191d8462ad..37a1303d9a34 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -738,6 +738,7 @@ }; &uart1 { + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index dd4e9c1893c6..e42c474ef4ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -614,6 +614,7 @@ }; &uart1 { + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; -- cgit v1.2.3-58-ga151 From 8687469a51af609ad4180c3ac2624b836fd55ff8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 4 Jul 2024 17:38:14 +0200 Subject: dt-bindings: arm: rockchip: Add ROCK 5 ITX board Add devicetree binding for the ROCK 5 ITX board, built around the rk3588. Acked-by: Krzysztof Kozlowski Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20240704153815.837392-2-heiko@sntech.de --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d2e887415d5d..bd5c1ae2487c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -816,6 +816,11 @@ properties: - const: radxa,rock-3c - const: rockchip,rk3566 + - description: Radxa ROCK 5 ITX + items: + - const: radxa,rock-5-itx + - const: rockchip,rk3588 + - description: Radxa ROCK 5A items: - const: radxa,rock-5a -- cgit v1.2.3-58-ga151 From 31390eb8ffbf2b6be7d789708ec08b635d7a3eb8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 4 Jul 2024 17:38:15 +0200 Subject: arm64: dts: rockchip: add ROCK 5 ITX board The ROCK 5 ITX as the name suggests is made in the ITX form factor and actually built in a form to be used in a regular case even providing connectors for regular front-panel io. It can be powered either by 12V, ATX power-supply or PoE. Notable peripherals are the 4 SATA ports, M.2 M-Key slot, M.2 E-key slot, 2*2.5Gb PCIe-connected Ethernet NICs. As of yet unsupported display options consist of 2*HDMI, DP via USB-c, eDP + 2*DSI via PCB connectors. USB ports are 4*USB3 + 2*USB2 on the back panel and 2-port front-panel connector. Schematics for the board can be found on - https://dl.radxa.com/rock5/5itx/radxa_rock_5_itx_X1100_schematic.pdf - https://dl.radxa.com/rock5/5itx/v1110/radxa_rock_5itx_v1110_schematic.pdf Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20240704153815.837392-3-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 1177 ++++++++++++++++++++ 2 files changed, 1178 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index adfb168759dd..92b210b171de 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts new file mode 100644 index 000000000000..d0b922b8d67e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -0,0 +1,1177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Limited + * Copyright (c) 2024 Heiko Stuebner + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" + +/ { + model = "Radxa ROCK 5 ITX"; + compatible = "radxa,rock-5-itx", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Mask Rom"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + power-led1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + hdd-led2 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm14 0 10000 0>; + }; + + /* M.2 E-KEY */ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + typec_vin: regulator-typec-vin { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + regulator-name = "typec_vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc33_io64: regulator-vcc33-io64 { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io64"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_ekey: regulator-vcc3v3-ekey { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ekey_en>; + regulator-name = "vcc3v3_ekey"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_mkey: regulator-vcc3v3-mkey { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_pwren_h>; + regulator-name = "vcc3v3_mkey"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20: vcc5v0_usb12: vcc5v0_usb34: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* CAM0 connector */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +/* M.2 E-key */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; +}; + +/* RTC and LCD0 connector */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "wifi_32kout"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; +}; + +/* Audio codec and CAM1 connector */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +/* FUSB302 and LCD1 connector */ +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m4_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&typec_vin>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c8m4_xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_up_drv_level_6>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_up_drv_level_6>; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + hysteresis = <2000>; + temperature = <50000>; + type = "active"; + }; + + package_fan1: package-fan1 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; + trip = <&package_fan0>; + }; + map1 { + cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; + trip = <&package_fan1>; + }; + }; +}; + +/* M.2 E-key */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_0_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ekey>; + status = "okay"; +}; + +/* RTL8125B_1 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_1_perstn>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_lan>; + status = "okay"; +}; + +/* RTL8125B_2 */ +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_lan_phy2>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 1 2 2>; + /* separate clock lines from the clock generator to phy and devices */ + rockchip,rx-common-refclk-mode = <0 0 0 0>; + status = "okay"; +}; + +/* ASMedia ASM1164 Sata controller */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc33_io64>; + status = "okay"; +}; + +/* M.2 M.key */ +&pcie3x4 { + num-lanes = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mkey>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20x1_2_perstn: pcie20x1-2-perstn { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_0_perstn_m1_l: pcie30x1-0-perstn-m1-l { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_1_perstn: pcie30x1-1-perstn { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ekey_en: ekey-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pcie30x4_pwren_h: pcie30x4-pwren-h { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gl3523_reset: rl3523-reset { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +/* M.2 E-KEY */ +&sdio { + broken-cd; + bus-width = <4>; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_ekey>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + spi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* Connected to M.2 E-key */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + /* connected to USB3 hub, which is powered by vcc5v0_usb12 */ + phy-supply = <&vcc5v0_usb12>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB2 hub, which is powered by vcc5v0_usb20 */ + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_xhci { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + peer-hub = <&hub_3_0>; + vdd-supply = <&vcc_3v3_s3>; + }; + + /* 3.0 hub on port 4 */ + hub_3_0: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + peer-hub = <&hub_2_0>; + pinctrl-names = "default"; + pinctrl-0 = <&gl3523_reset>; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_3v3_s3>; + }; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; -- cgit v1.2.3-58-ga151 From 8b5d415c4f9cc5a147c791d0300ee0b0cd8deae0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 3 Jul 2024 15:23:41 +0200 Subject: ARM: dts: ixp4xx: nslu2: beeper uses PWM The beeper in the NSLU2 is just a GPIO connected to a speaker, so we need to use PWM on the GPIO to get any kind of sound out. Tested with some random beeps by enabling INPUT_EVDEV and running beep.c with e.g. beep 400 for a 400 Hz tone. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20240627-ixp4xx-dts-v1-1-cdbbe1150873@linaro.org Link: https://lore.kernel.org/r/20240703-ixp4xx-dts-v1-1-e5149da36f6e@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts index 2eec5f63d399..2f7c34c649ea 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts @@ -90,11 +90,18 @@ timeout-ms = <5000>; }; - gpio-beeper { - compatible = "gpio-beeper"; + gpio_pwm: pwm { + #pwm-cells = <3>; + compatible = "pwm-gpio"; gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; }; + beeper { + compatible = "pwm-beeper"; + pwms = <&gpio_pwm 0 1 0>; + beeper-hz = <1000>; + }; + soc { bus@c4000000 { /* The first 16MB region at CS0 on the expansion bus */ -- cgit v1.2.3-58-ga151 From 2881fcfc8f32c536a4bf708066d6fea9ba762e86 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 28 Jun 2024 19:40:55 +0200 Subject: mailmap: Update Luca Weiss's email address I'm slowly migrating my mail to a new domain, add an entry to map the mail address. Just for clarity, my work-related @fairphone.com email stays unchanged. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240628-mailmap-v1-1-a0d12ffd1cd9@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 43cd2995dbc2..17d632f49881 100644 --- a/.mailmap +++ b/.mailmap @@ -381,6 +381,7 @@ Li Yang Lior David Lorenzo Pieralisi Luca Ceresoli +Luca Weiss Lukasz Luba Luo Jie Maciej W. Rozycki -- cgit v1.2.3-58-ga151 From 056abbd100ce9ce6dae3e5e64ffee92b56439c0c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 27 Jun 2024 21:17:30 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa ROCK 3B Add devicetree binding documentation for the Radxa ROCK 3B board. The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community version based on the RK3568 SoC and an industrial version based on the RK3568J SoC. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240627211737.1985549-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index bd5c1ae2487c..8afd31a2bc5e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -811,6 +811,11 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 + - description: Radxa ROCK 3B + items: + - const: radxa,rock-3b + - const: rockchip,rk3568 + - description: Radxa ROCK 3C items: - const: radxa,rock-3c -- cgit v1.2.3-58-ga151 From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 27 Jun 2024 21:17:31 +0000 Subject: arm64: dts: rockchip: Add Radxa ROCK 3B The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community version based on the RK3568 SoC and an industrial version based on the RK3568J SoC. Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++++++++ 2 files changed, 782 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 92b210b171de..16570b487816 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts new file mode 100644 index 000000000000..3d0c1ccfaa79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Radxa ROCK 3B"; + compatible = "radxa,rock-3b", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_ir>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <10000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys2: regulator-3v3-vcc-sys2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&rtcic_int_l>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20m1_pins>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir-receiver { + pwm3_ir: pwm3-ir { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led: led { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie20 { + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + <2 RK_PD0 4 &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + <2 RK_PD4 4 &pcfg_pull_none>, + <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + rtcic_int_l: rtcic-int-l { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys2>; + vqmmc-supply = <&vcc_1v8>; + status = "disabled"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- cgit v1.2.3-58-ga151 From 6d48d5045d99a938b42ee875ae6be80b832e6d77 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 26 Jun 2024 23:03:11 +0000 Subject: dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B Add devicetree binding for the Xunlong Orange Pi 3B board. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240626230319.1425316-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 8afd31a2bc5e..1ef09fbfdfaf 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -993,6 +993,14 @@ properties: - const: wolfvision,rk3568-pf5 - const: rockchip,rk3568 + - description: Xunlong Orange Pi 3B + items: + - enum: + - xunlong,orangepi-3b-v1.1 + - xunlong,orangepi-3b-v2.1 + - const: xunlong,orangepi-3b + - const: rockchip,rk3566 + - description: Xunlong Orange Pi 5 Plus items: - const: xunlong,orangepi-5-plus -- cgit v1.2.3-58-ga151 From d79d713d602e8b32cf935ddfdf61769cb74ba1dc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 26 Jun 2024 23:03:12 +0000 Subject: arm64: dts: rockchip: Add Xunlong Orange Pi 3B The Xunlong Orange Pi 3B is a single-board computer based on the Rockchip RK3566 SoC. Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20240626230319.1425316-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + .../boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 +++ .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 +++++++++++++++++++++ 4 files changed, 779 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 16570b487816..fda1b980eb4b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinetab2-v0.1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 000000000000..074e93bd4b85 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v1.1"; + compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio5-supply = <&vcc_3v3>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 000000000000..d894bff41e61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v2.1"; + compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566"; + + vccio_phy1: regulator-1v8-vccio-phy { + compatible = "regulator-fixed"; + regulator-name = "vccio_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; +}; + +&pmu_io_domains { + vccio5-supply = <&vccio_phy1>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&uart1 { + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi new file mode 100644 index 000000000000..d539570f531e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Xunlong Orange Pi 3B"; + compatible = "xunlong,orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc3v3_pcie30: regulator-3v3-vcc-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pins>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led: work-led { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_pins: pcie20-pins { + rockchip,pins = + <1 RK_PB0 4 &pcfg_pull_none>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie20_pwren: pcie20-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- cgit v1.2.3-58-ga151 From b1240a39511b9206293b82ac372c5114d6e15821 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 24 Nov 2023 14:26:02 +0800 Subject: riscv: dts: add clock generator for Sophgo SG2042 SoC Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang Reviewed-by: Guo Ren --- .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 +++++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 49b4b9c2c101..80cb017974d8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -14,6 +14,18 @@ }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 81fda312f988..34c802bd3f9b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -4,8 +4,10 @@ */ /dts-v1/; +#include +#include +#include #include - #include #include "sg2042-cpus.dtsi" @@ -20,12 +22,60 @@ serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + pllclk: clock-controller@70300100c0 { + compatible = "sophgo,sg2042-pll"; + reg = <0x70 0x300100c0 0x0 0x40>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; + #clock-cells = <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x70 0x30010368 0x0 0x98>; + clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; + clock-names = "rpgate"; + #clock-cells = <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + clocks = <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + clock-names = "mpll", + "fpll", + "dpll0", + "dpll1"; + #clock-cells = <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; @@ -341,6 +391,9 @@ interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rstgen RST_UART0>; -- cgit v1.2.3-58-ga151 From 6ed9a85f1c44d7049cf2d488bfe71252ce467dc2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 25 Jun 2024 00:21:10 +0100 Subject: arm64: dts: allwinner: h616: add crypto engine node The Allwinner H616 SoC contains a crypto engine very similar to the H6 version, but with all base addresses in the DMA descriptors shifted by two bits. This requires a new compatible string. Also the H616 CE relies on the internal osciallator for the TRNG operation, so we need to reference this clock. Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20240624232110.9817-5-andre.przywara@arm.com [wens@csie.org: fix up register range size] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index bf4d41ecbfdc..b29ce7321317 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -150,6 +150,16 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + crypto: crypto@1904000 { + compatible = "allwinner,sun50i-h616-crypto"; + reg = <0x01904000 0x800>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + syscon: syscon@3000000 { compatible = "allwinner,sun50i-h616-system-control"; reg = <0x03000000 0x1000>; -- cgit v1.2.3-58-ga151