From 920cda3870557a50105f0c5eb783059b3aced86e Mon Sep 17 00:00:00 2001 From: Chad Reese Date: Thu, 15 Jan 2015 16:11:16 +0300 Subject: MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. CN38XX pass 1 required icache prefetching to be turned off. This chip never reached production and is long dead. Other processor specific icache settings are done by the bootloader. Remove these bits from the kernel. Signed-off-by: Chad Reese Signed-off-by: Aleksey Makarov Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/8944/ Signed-off-by: Ralf Baechle --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index c7ce0811657d..4bef539e1f07 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -37,26 +37,6 @@ # Needed for octeon specific memcpy or v0, v0, 0x5001 xor v0, v0, 0x1001 - # Read the processor ID register - mfc0 v1, CP0_PRID_REG - # Disable instruction prefetching (Octeon Pass1 errata) - or v0, v0, 0x2000 - # Skip reenable of prefetching for Octeon Pass1 - beq v1, CP0_PRID_OCTEON_PASS1, skip - nop - # Reenable instruction prefetching, not on Pass1 - xor v0, v0, 0x2000 - # Strip off pass number off of processor id - srl v1, 8 - sll v1, 8 - # CN30XX needs some extra stuff turned off for better performance - bne v1, CP0_PRID_OCTEON_CN30XX, skip - nop - # CN30XX Use random Icache replacement - or v0, v0, 0x400 - # CN30XX Disable instruction prefetching - or v0, v0, 0x2000 -skip: # First clear off CvmCtl[IPPCI] bit and move the performance # counters interrupt to IRQ 6 dli v1, ~(7 << 7) -- cgit v1.2.3-58-ga151