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path: root/drivers/pinctrl/intel/pinctrl-intel.c
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2024-02-19pwm: lpss-*: Make use of devm_pwmchip_alloc() functionUwe Kleine-König
This prepares the pwm-lpss drivers to further changes of the pwm core outlined in the commit introducing devm_pwmchip_alloc(). There is no intended semantical change and the driver should behave as before. Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/b567ab5dd992e361eb884fa6c2cac11be9c7dde3.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2023-11-22pinctrl: intel: use the correct _PM_OPS() export macroRaag Jadav
Since we don't have runtime PM handles here, we should be using EXPORT_NS_GPL_DEV_SLEEP_PM_OPS() macro, so that the compiler can discard it in case CONFIG_PM_SLEEP=n. Fixes: b10a74b5c0c1 ("pinctrl: intel: Provide Intel pin control wide PM ops structure") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-14pinctrl: intel: Revert "Unexport intel_pinctrl_probe()"Andy Shevchenko
In order to prepare for a new coming driver export the original intel_pinctrl_probe() again. This reverts commit 0dd519e3784b13befa1cdfeff847a0885b06650f. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Refactor intel_pinctrl_get_soc_data()Andy Shevchenko
Refactor intel_pinctrl_get_soc_data() to drop initial assignment of the data variable. It's only used in ACPI case and instead we may always assign it there as the ACPI ID table has the terminator entry that has driver data set to NULL. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Move default strength assignment to a switch-caseAndy Shevchenko
iWhen ->pin_config_set() is called from the GPIO library (assumed GpioIo() ACPI resource), the argument can be 1, when, for example, PullDefault is provided. In such case we supply sane default in the driver. Move that default assingment to a switch-case, so it will be consolidated in one place. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Make PM ops functions staticAndy Shevchenko
No more users outside of the main module. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231030120734.2831419-18-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-13pinctrl: intel: Provide Intel pin control wide PM ops structureAndy Shevchenko
With the help of EXPORT_NS_GPL_DEV_PM_OPS() and NOIRQ_SYSTEM_SLEEP_PM_OPS() we may convert PM ops functions to become static. This also takes into account the PM configuration options such as CONFIG_PM and CONFIG_PM_SLEEP. Hence the first step is to provide a generic PM ops structure that can be used by drivers directly. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231030120734.2831419-2-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-11-04treewide: rename pinctrl_gpio_direction_output_new()Bartosz Golaszewski
Now that pinctrl_gpio_direction_output() is no longer used, let's drop the '_new' suffix from its improved variant. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-04treewide: rename pinctrl_gpio_direction_input_new()Bartosz Golaszewski
Now that pinctrl_gpio_direction_input() is no longer used, let's drop the '_new' suffix from its improved variant. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-04pinctrl: intel: use new pinctrl GPIO helpersBartosz Golaszewski
Replace the pinctrl helpers taking the global GPIO number as argument with the improved variants that instead take a pointer to the GPIO chip and the controller-relative offset. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-11-03Merge tag 'pinctrl-v6.7-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No pin control core changes this time. New drivers: - Realtek RTD family pin control driver and RTD1619B, RTD1319D and RTD1315E subdrivers - Nuvoton NPCM8xx combined pin control and GPIO driver - Amlogic T7 pin control driver - Renesas RZ/G3S pin control driver Improvements: - A number of additional UART groups added to the Mediatek MT7981 driver - MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660 - Extra GPIO banks for the Sunxi H616 - MLSP I2C6 function support in Qualcomm MSM8226 - Some __counted_by() annotations for dynamic arrays - Ongoing work to make remove() return void - LSBC groups and functions in the Renesas R8A7778" * tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: Use device_get_match_data() dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes dt-bindings: pinctrl: brcm: Ensure all child node properties are documented pinctrl: renesas: rzn1: Convert to platform remove callback returning void pinctrl: renesas: rzg2l: Add RZ/G3S support dt-bindings: pinctrl: renesas: Document RZ/G3S SoC pinctrl: renesas: rzg2l: Add support for different DS values on different groups pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets pinctrl: renesas: rzg2l: Index all registers based on port offset pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions pinctrl: intel: fetch community only when we need it pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case pinctrl: cherryview: Convert to platform remove callback returning void pinctrl: sprd-sc9860: Convert to platform remove callback returning void pinctrl: qcom/msm: Convert to platform remove callback returning void pinctrl: qcom/lpi: Convert to platform remove callback returning void ...
2023-10-24pinctrl: intel: use acpi_dev_uid_match() for matching _UIDRaag Jadav
Convert manual _UID references to use the standard ACPI helper. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-10-11pinctrl: intel: fetch community only when we need itRaag Jadav
We check community features only in case PIN_CONFIG_BIAS_PULL_DOWN while setting/getting pad termination. No need to fetch the community otherwise. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-10-03pinctrl: intel: refine intel_config_set_pull() functionRaag Jadav
Improve intel_config_set_pull() implementation in Intel pinctrl driver by: - Reducing scope of spinlock by moving unneeded operations out of it. - Utilizing temporary variables for common operations. - Limiting IO operations to positive cases. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-09-26pinctrl: intel: Simplify code with cleanup helpersAndy Shevchenko
Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. While at it, unify the variables and approach in intel_gpio_irq_*(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15pinctrl: intel: Switch to use exported namespaceAndy Shevchenko
We already have a few symbols exported in the namespace. Let's do the same for others (except PM for now). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: intel: export common pinctrl functionsRaag Jadav
Export common pinctrl functions that are used across Intel specific platform drivers, so that they can be reused. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-15pinctrl: intel: refine ->irq_set_type() hookRaag Jadav
Refine ->irq_set_type() hook and improve its readability by: - Reducing scope of spinlock by moving unneeded operations out of it. - Dropping redundant PADCFG0_RXEVCFG_SHIFT and including it directly into PADCFG0_RXEVCFG_* definitions. - Utilizing temporary variables for common operations. - Simplifying if-else-if chain. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-14pinctrl: intel: refine ->set_mux() hookRaag Jadav
Utilize a temporary variable for common shift operation in ->set_mux() hook and improve readability while saving a few bytes. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3) Function old new delta intel_pinmux_set_mux 245 242 -3 Total: Before=10472, After=10469, chg -0.03% Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230613085054.10976-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-02-22Merge tag 'pinctrl-v6.3-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Nothing special, notably a lot of new Qualcomm hardware is supported, a RISC-V reference SoC and then some cleanups both in code and device tree bindings. Core changes: - Add PINCTRL_PINFUNCTION() macro and use it in several drivers New drivers: - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on) pin controllers. (RISC-V.) - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin controllers - New subdriver for the Qualcomm SA8775P SoC pin controller - New subdriver for the Qualcomm IPQ5332 SoC pin controller - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin control - New subdriver for the Mediatek MT7981 SoC pin controller Improvements: - Several cleanups and refactorings to the Intel drivers - Add 4KOhm bias support to the Intel driver - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver - Support general purpose clocks in the Qualcomm MSM8226 SoC - Several conversions to use the new I2C .probe_new() call - Massive clean-up of the Qualcomm Device Tree YAML schemas - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC driver" * tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits) pinctrl: qcom: Add support for i2c specific pull feature pinctrl: starfive: Add StarFive JH7110 aon controller driver pinctrl: starfive: Add StarFive JH7110 sys controller driver dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl pinctrl: add mt7981 pinctrl driver dt-bindings: pinctrl: add bindings for MT7981 SoC dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated pinctrl: qcom: Introduce IPQ5332 TLMM driver dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS pinctrl: at91: use devm_kasprintf() to avoid potential leaks dt-bindings: pinctrl: qcom: correct gpio-ranges in examples dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example ...
2023-02-07pinctrl: intel: Restore the pins that used to be in Direct IRQ modeAndy Shevchenko
If the firmware mangled the register contents too much, check the saved value for the Direct IRQ mode. If it matches, we will restore the pin state. Reported-by: Jim Minter <jimminter@microsoft.com> Fixes: 6989ea4881c8 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode") Tested-by: Jim Minter <jimminter@microsoft.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-30pinctrl: intel: Make use of struct pinfunction and PINCTRL_PINFUNCTION()Andy Shevchenko
Since pin control provides a generic data type and a macro for the pin function definition, use them in the Intel driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Define maximum pad number in the groupAndy Shevchenko
Instead of using hard coded magic number here and there, define maximum pad number in the group in newly added INTEL_PINCTRL_MAX_GPP_SIZE. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Use same order of bit fields for PADCFG2Andy Shevchenko
PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Add ~4k bias supportAndy Shevchenko
All versions that have 20k and 5k resistance, i.e. all that the driver supports, may support ~4k when the above mentioned are connected in parallel. Add such a support. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Add definitions to all possible biasesAndy Shevchenko
Add definitions to all possible biases, i.e. add ~800 Ohms, ~952 Ohms, ~4 kOhms. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Deduplicate some code in intel_config_set_pull()Andy Shevchenko
First part is to assign default argument for all cases, since bias disablement doesn't use it anyway. Second part is to clear all bits in the bias setting and depending on the argument and parameter set them as asked. While at it, add break statement to the default cases. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-27pinctrl: intel: Add default case to intel_config_set_pull()Andy Shevchenko
For the sake of symmetry with intel_config_get_pull(), add a default case to the outer switch. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-27pinctrl: intel: Convert to generic_handle_domain_irq()Andy Shevchenko
Replace construct that matches generic_handle_irq(irq_find_mapping()) to a single call to generic_handle_domain_irq(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-27pinctrl: intel: Always use gpp_num_padown_regs in the main driverAndy Shevchenko
For the size-based communities, always use gpp_num_padown_regs, which is now provided explicitly via INTEL_COMMUNITY_SIZE() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-13Merge tag 'pinctrl-v6.2-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ...
2022-11-28pinctrl: intel: Save and restore pins in "direct IRQ" modeAndy Shevchenko
The firmware on some systems may configure GPIO pins to be an interrupt source in so called "direct IRQ" mode. In such cases the GPIO controller driver has no idea if those pins are being used or not. At the same time, there is a known bug in the firmwares that don't restore the pin settings correctly after suspend, i.e. by an unknown reason the Rx value becomes inverted. Hence, let's save and restore the pins that are configured as GPIOs in the input mode with GPIROUTIOXAPIC bit set. Cc: stable@vger.kernel.org Reported-and-tested-by: Dale Smith <dalepsmith@gmail.com> Reported-and-tested-by: John Harris <jmharris@gmail.com> BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214749 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221124222926.72326-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-28Merge tag 'intel-pinctrl-v6.2-2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-2 * Enable PWM feature on Intel pin control IPs The following is an automated git shortlog grouped by driver: intel: - Enumerate PWM device when community has a capability pwm: - lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() - lpss: Allow other drivers to enable PWM LPSS - lpss: Include headers we are the direct user of - lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS - Add a stub for devm_pwmchip_add()
2022-11-22pinctrl: intel: Enumerate PWM device when community has a capabilityAndy Shevchenko
Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2022-11-03pinctrl: intel: Use temporary variable for struct deviceAndy Shevchenko
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: intel: Use str_enable_disable() helperAndy Shevchenko
Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2022-10-24pinctrl: intel: Add missing header(s)Andy Shevchenko
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-08-10Merge tag 'pinctrl-v6.0-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ...
2022-07-14pinctrl: intel: Check against matching data instead of ACPI companionAndy Shevchenko
In some cases we may get a platform device that has ACPI companion which is different to the pin control described in the ACPI tables. This is primarily happens when device is instantiated by board file. In order to allow this device being enumerated, refactor intel_pinctrl_get_soc_data() to check the matching data instead of ACPI companion. Reported-by: Henning Schild <henning.schild@siemens.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
2022-06-20pinctrl: intel: Switch to to embedded struct pingroupAndy Shevchenko
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-20pinctrl: intel: Fix kernel doc format, i.e. add return sectionsAndy Shevchenko
Kernel doc validator is not happy: pinctrl-intel.c:865: warning: No description found for return value of 'intel_gpio_to_pin' pinctrl-intel.c:904: warning: No description found for return value of 'intel_pin_to_gpio' 2 warnings Add return sections to the kernel documentation of the above mentioned functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-18pinctrl: intel: make irq_chip immutableAndy Shevchenko
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-01-24pinctrl: intel: Fix a glitch when updating IRQ flags on a preconfigured lineAndy Shevchenko
The commit af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") hadn't taken into account an update of the IRQ flags scenario. When updating the IRQ flags on the preconfigured line the ->irq_set_type() is called again. In such case the sequential Rx buffer configuration changes may trigger a falling or rising edge interrupt that may lead, on some platforms, to an undesired event. This may happen because each of intel_gpio_set_gpio_mode() and __intel_gpio_set_direction() updates the pad configuration with a different value of the GPIORXDIS bit. Notable, that the intel_gpio_set_gpio_mode() is called only for the pads that are configured as an input. Due to this fact, integrate the logic of __intel_gpio_set_direction() call into the intel_gpio_set_gpio_mode() so that the Rx buffer won't be disabled and immediately re-enabled. Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") Reported-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Grace Kao <grace.kao@intel.com>
2022-01-24pinctrl: intel: fix unexpected interruptŁukasz Bartosik
ASUS Chromebook C223 with Celeron N3350 crashes sometimes during cold booot. Inspection of the kernel log showed that it gets into an inifite loop logging the following message: ->handle_irq(): 000000009cdb51e8, handle_bad_irq+0x0/0x251 ->irq_data.chip(): 000000005ec212a7, 0xffffa043009d8e7 ->action(): 00000 IRQ_NOPROBE set unexpected IRQ trap at vector 7c The issue happens during cold boot but only if cold boot happens at most several dozen seconds after Chromebook is powered off. For longer intervals between power off and power on (cold boot) the issue does not reproduce. The unexpected interrupt is sourced from INT3452 GPIO pin which is used for SD card detect. Investigation relevealed that when the interval between power off and power on (cold boot) is less than several dozen seconds then values of INT3452 GPIO interrupt enable and interrupt pending registers survive power off and power on sequence and interrupt for SD card detect pin is enabled and pending during probe of SD controller which causes the unexpected IRQ message. "Intel Pentium and Celeron Processor N- and J- Series" volume 3 doc mentions that GPIO interrupt enable and status registers default value is 0x0. The fix clears INT3452 GPIO interrupt enabled and interrupt pending registers in its probe function. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Signed-off-by: Łukasz Bartosik <lb@semihalf.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-04-30Merge tag 'pinctrl-v5.13-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is a lot going on! Core changes: - A semantic change to handle pinmux and pinconf in explicit order while up until now we depended on the semantic order in the device tree. The device tree is a functional programming language and does not imply any order, so the right thing is for the pin control core to provide these semantics. - Add a new pinmux-select debugfs file which makes it possible to go in and select functions for a pin manually (iteratively, at the prompt) for debugging purposes. - Fixes to gpio regmap handling for a new pin control driver making use of regmap-gpio. - Use octal permissions on debugfs files. New drivers: - A massive rewrite of the former custom pin control driver for MIPS Broadcom devices to instead use the pin control subsystem. New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368, BCM63268 and BCM6318 SoC variants are implemented. - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are supported. - Support for the Rockchip RK3568/RK3566 pin controller. - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000. - Support for Mediatek MTK8195. - Add a new Xilinx ZynqMP pin control driver. Driver improvements and non-urgent fixes: - Modularization and improvements of the Rockchip drivers. - Some new pins added to the description of new Renesas SoCs. - Clarifications of the GPIO base calculation in the Intel driver. - Fix the function names for the MPP54 and MPP55 pins in the Armada CP110 pin controller. - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350. - Support for ACPI probing of the Qualcomm SC8180x. - Fix interrupt clear status on rockchip - Fix some missing pins on the Ingenic JZ4770, some semantic fixes for the behaviour of the Ingenic pin controller. Add DMIC pins for JZ4780, X1000, X1500 and X1830. - A slew of janitorial like of_node_put() calls" * tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: Add Xilinx ZynqMP pinctrl driver support firmware: xilinx: Add pinctrl support pinctrl: rockchip: do coding style for mux route struct pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param pinctrl: Introduce MODE group in enum pin_config_param pinctrl: Keep enum pin_config_param ordered by name dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver pinctrl: core: Fix kernel doc string for pin_get_name() pinctrl: mediatek: use spin lock in mtk_rmw pinctrl: add drive for I2C related pins on MT8195 pinctrl: add pinctrl driver on mt8195 dt-bindings: pinctrl: mt8195: add pinctrl file and binding document pinctrl: Ingenic: Add pinctrl driver for X2000. pinctrl: Ingenic: Add pinctrl driver for JZ4775. pinctrl: Ingenic: Add pinctrl driver for JZ4755. pinctrl: Ingenic: Add pinctrl driver for JZ4750. pinctrl: Ingenic: Add pinctrl driver for JZ4730. dt-bindings: pinctrl: Add bindings for new Ingenic SoCs. pinctrl: Ingenic: Reformat the code. pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs. ...
2021-03-25pinctrl: intel: check REVID register value for device presenceRoger Pau Monne
Use the value read from the REVID register in order to check for the presence of the device. A read of all ones is treated as if the device is not present, and hence probing is ended. This fixes an issue when running as a Xen PVH dom0, where the ACPI DSDT table is provided unmodified to dom0 and hence contains the pinctrl devices, but the MMIO region(s) containing the device registers might not be mapped in the guest physical memory map if such region(s) are not exposed on a PCI device BAR or marked as reserved in the host memory map. Fixes: 91d898e51e60 ("pinctrl: intel: Convert capability list to features") Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-03-25pinctrl: intel: No need to disable IRQs in the handlerAndy Shevchenko
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-03-08pinctrl: intel: Show the GPIO base calculation explicitlyAndy Shevchenko
During the split of intel_pinctrl_add_padgroups(), the _by_size() variant missed the GPIO base calculations and hence made unable to retrieve proper GPIO number. Assign the gpio_base explicitly in _by_size() variant. While at it, differentiate NOMAP case with the rest in _by_gpps() variant. Fixes: 036e126c72eb ("pinctrl: intel: Split intel_pinctrl_add_padgroups() for better maintenance") Reported-and-tested-by: Maximilian Luz <luzmaximilian@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08pinctrl: intel: Convert capability list to featuresAndy Shevchenko
Communities can have features provided in the capability list. Traverse the list and convert to respective features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08pinctrl: intel: Drop unnecessary check for predefined featuresAndy Shevchenko
None of the drivers is overriding features. Remove unnecessary check. While here, rename rev to value to make easier further development. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
generated by cgit v1.2.3-58-ga151 (git 2.39.0) at 2024-11-28 19:44:12 +0000