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2019-10-23phy: renesas: rcar-gen3-usb2: Use platform_get_irq_optional() for optional irqGeert Uytterhoeven
As platform_get_irq() now prints an error when the interrupt does not exist, a scary warning may be printed for an optional interrupt: phy_rcar_gen3_usb2 ee0a0200.usb-phy: IRQ index 0 not found Fix this by calling platform_get_irq_optional() instead. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-23phy-mvebu-a3700-utmi: Use devm_platform_ioremap_resource() in ↵Markus Elfring
mvebu_a3700_utmi_phy_probe() Simplify this function implementation by using a known wrapper function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-23phy: tegra: xusb: remove unused variableChunfeng Yun
The local variable @priv is set but not used, can be removed Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-23phy: xgene: make array serdes_reg static const, makes object smallerColin Ian King
Don't populate the array serdes_reg on the stack but instead make it static const. Makes the object code smaller by 228 bytes. Before: text data bss dec hex filename 23875 6232 64 30171 75db drivers/phy/phy-xgene.o After: text data bss dec hex filename 23551 6328 64 29943 74f7 drivers/phy/phy-xgene.o (gcc version 9.2.1, amd64) Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-09-23Merge tag 'pci-v5.4-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Consolidate _HPP/_HPX stuff in pci-acpi.c and simplify it (Krzysztof Wilczynski) - Fix incorrect PCIe device types and remove dev->has_secondary_link to simplify code that deals with upstream/downstream ports (Mika Westerberg) - After suspend, restore Resizable BAR size bits correctly for 1MB BARs (Sumit Saxena) - Enable PCI_MSI_IRQ_DOMAIN support for RISC-V (Wesley Terpstra) Virtualization: - Add ACS quirks for iProc PAXB (Abhinav Ratna), Amazon Annapurna Labs (Ali Saidi) - Move sysfs SR-IOV functions to iov.c (Kelsey Skunberg) - Remove group write permissions from sysfs sriov_numvfs, sriov_drivers_autoprobe (Kelsey Skunberg) Hotplug: - Simplify pciehp indicator control (Denis Efremov) Peer-to-peer DMA: - Allow P2P DMA between root ports for whitelisted bridges (Logan Gunthorpe) - Whitelist some Intel host bridges for P2P DMA (Logan Gunthorpe) - DMA map P2P DMA requests that traverse host bridge (Logan Gunthorpe) Amazon Annapurna Labs host bridge driver: - Add DT binding and controller driver (Jonathan Chocron) Hyper-V host bridge driver: - Fix hv_pci_dev->pci_slot use-after-free (Dexuan Cui) - Fix PCI domain number collisions (Haiyang Zhang) - Use instance ID bytes 4 & 5 as PCI domain numbers (Haiyang Zhang) - Fix build errors on non-SYSFS config (Randy Dunlap) i.MX6 host bridge driver: - Limit DBI register length (Stefan Agner) Intel VMD host bridge driver: - Fix config addressing issues (Jon Derrick) Layerscape host bridge driver: - Add bar_fixed_64bit property to endpoint driver (Xiaowei Bao) - Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC drivers separately (Xiaowei Bao) Mediatek host bridge driver: - Add MT7629 controller support (Jianjun Wang) Mobiveil host bridge driver: - Fix CPU base address setup (Hou Zhiqiang) - Make "num-lanes" property optional (Hou Zhiqiang) Tegra host bridge driver: - Fix OF node reference leak (Nishka Dasgupta) - Disable MSI for root ports to work around design problem (Vidya Sagar) - Add Tegra194 DT binding and controller support (Vidya Sagar) - Add support for sideband pins and slot regulators (Vidya Sagar) - Add PIPE2UPHY support (Vidya Sagar) Misc: - Remove unused pci_block_cfg_access() et al (Kelsey Skunberg) - Unexport pci_bus_get(), etc (Kelsey Skunberg) - Hide PM, VC, link speed, ATS, ECRC, PTM constants and interfaces in the PCI core (Kelsey Skunberg) - Clean up sysfs DEVICE_ATTR() usage (Kelsey Skunberg) - Mark expected switch fall-through (Gustavo A. R. Silva) - Propagate errors for optional regulators and PHYs (Thierry Reding) - Fix kernel command line resource_alignment parameter issues (Logan Gunthorpe)" * tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (112 commits) PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCI arm64: tegra: Add PCIe slot supply information in p2972-0000 platform arm64: tegra: Add configuration for PCIe C5 sideband signals PCI: tegra: Add support to enable slot regulators PCI: tegra: Add support to configure sideband pins PCI: vmd: Fix shadow offsets to reflect spec changes PCI: vmd: Fix config addressing when using bus offsets PCI: dwc: Add validation that PCIe core is set to correct mode PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port PCI: Add ACS quirk for Amazon Annapurna Labs root ports PCI: Add Amazon's Annapurna Labs vendor ID MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer PCI: hv: Use bytes 4 and 5 from instance ID as the PCI domain numbers dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries dt-bindings: PCI: tegra: Add sideband pins configuration entries PCI: tegra: Add Tegra194 PCIe support PCI: Get rid of dev->has_secondary_link flag ...
2019-09-22Merge tag 'for-v5.4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply Pull power supply and reset updates from Sebastian Reichel: "Core: - Ensure HWMON devices are registered with valid names - Fix device wakeup code Drivers: - bq25890_charger: Add BQ25895 support - axp288_fuel_gauge: Add Minix Neo Z83-4 to blacklist - sc27xx: improve battery calibration - misc small fixes all over drivers" * tag 'for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (24 commits) power: supply: cpcap-charger: Enable vbus boost voltage power: supply: sc27xx: Add POWER_SUPPLY_PROP_CALIBRATE attribute power: supply: sc27xx: Optimize the battery capacity calibration power: supply: sc27xx: Make sure the alarm capacity is larger than 0 power: supply: sc27xx: Fix the the accuracy issue of coulomb calculation power: supply: sc27xx: Fix conditon to enable the FGU interrupt power: supply: sc27xx: Add POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN attribute power: supply: max77650: add MODULE_ALIAS() power: supply: isp1704: remove redundant assignment to variable ret power: supply: bq25890_charger: Add the BQ25895 part power: supply: sc27xx: Replace devm_add_action() followed by failure action with devm_add_action_or_reset() power: supply: sc27xx: Introduce local variable 'struct device *dev' power: reset: reboot-mode: Fix author email format power: supply: ab8500: remove set but not used variables 'vbup33_vrtcn' and 'bup_vch_range' power: supply: max17042_battery: Fix a typo in function names power: reset: gpio-restart: Fix typo when gpio reset is not found power: supply: Init device wakeup after device_add() power: supply: ab8500_charger: Mark expected switch fall-through power: supply: sbs-battery: only return health when battery present MAINTAINERS: N900: Remove isp1704_charger.h record ...
2019-09-20Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have a small collection of core framework updates this time, mostly around clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: Drop !clk checks in debugfs dumping clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: sprd: add missing kfree clk: at91: allow 24 Mhz clock as input for PLL clk: Make clk_bulk_get_all() return a valid "id" clk: actions: Fix factor clk struct member access clk: qcom: rcg: Return failure for RCG update clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h ...
2019-09-02power: supply: cpcap-charger: Enable vbus boost voltageTony Lindgren
We are currently not enabling VBUS boost for cpcap when in host mode. This means the VBUS is fed at the battery voltage level, which can cause flakeyness enumerating devices. Looks like the boost control for VBUS is CPCAP_BIT_VBUS_SWITCH that we must enable in the charger for nice 4.92 V VBUS output. And looks like we must not use the STBY pin enabling but must instead use manual VBUS control in phy-cpcap-usb. We want to do this in cpcap_charger_vbus_work() and also set a flag for feeding_vbus to avoid races between USB detection and charger detection, and disable charging if feeding_vbus is set. Cc: Jacopo Mondi <jacopo@jmondi.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Marcel Partap <mpartap@gmx.net> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Scott <hashcode0f@gmail.com> Cc: NeKit <nekit1000@gmail.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2019-08-27phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLTMatt Pelland
The documentation for Marvell's cp110 phy refers to these registers/register regions as DTL control, DTL frequency loop enable, etc. This patch aligns the relevant code for these accordingly. Signed-off-by: Matt Pelland <mpelland@starry.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI supportMatt Pelland
Marvell's cp110 phy supports RXAUI on lanes 2, 3, 4, and 5 when connected to port zero. When used in this mode, lanes operate in pairs of two (2 and 3, 4 and 5). Signed-off-by: Matt Pelland <mpelland@starry.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Update comment about powering off all lanes at bootMiquel Raynal
Now that all COMPHY modes are supported by the driver, update the comment stating that mvebu_comphy_power_off() should be called for each lane. This is still wrong because for compatibility reasons, it might break users running an old firmware (the driver only uses SMC calls for SATA, USB and PCIe configuration, there is no code in Linux to fallback on in these cases. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add PCIe supportGrzegorz Jaszczyk
Add PCIe support by filling the COMPHY modes table. Also add a new macro to generate the right value for the firmware depending on the width (PCI x1, x2, x4, etc). The width will be passed by the core as the "submode" argument of the ->set_mode() callback. If this argument is zero, default to x1 mode. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Cosmetic change in a helperMiquel Raynal
Before adding more logic, simplify a bit the writing of the mvebu_comphy_get_mode() helper by using a pointer instead of referencing a configuration with the entire table name. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add SATA supportGrzegorz Jaszczyk
Add the corresponding entries in the COMPHY modes table. SATA support does not need any additional care. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add USB3 host/device supportGrzegorz Jaszczyk
Add USB3 host/device support by adding the right entries in the COMPHY modes table. A new macro is created to instantiate a "generic" mode ie. not an Ethernet one. This macro will be re-used when adding SATA support. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configuredMiquel Raynal
The COMPHY can configure the SERDES lanes in several non-Ethernet modes: SATA, USB3, PCIe. Drop the condition limiting the driver to Ethernet modes only before adding support for more. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modesMiquel Raynal
Before adding support for other PHY modes (not Ethernet ones), let's rename the MVEBU_COMPHY_CONF macro to a more specific (and shorter) appellation. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add RXAUI supportGrzegorz Jaszczyk
Add support for RXAUI mode by adding an entry in the COMPHY modes list. There is no user for this mode yet so we can enforce an up-to-date firmware and return an error otherwise without breaking anywone. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: List already supported Ethernet modesMiquel Raynal
Currently, the driver supports setting lanes to 1000BASEX, 2500BASEX, 10GKR. Complete the COMPHY modes list by adding two (already supported) cases for lane 4. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add SMC call supportGrzegorz Jaszczyk
Keep the exact same list of supported configurations but first try to use the firmware's implementation. If it fails, try the legacy method: Linux implementation. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Explicitly initialize the lane submodeMiquel Raynal
Explicitly set the lane submode (enum) to a known invalid value. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy: mvebu-cp110-comphy: Add clocks supportMiquel Raynal
There is no public clock tree that implies such dependencies between the MG/MG-core/AXI clocks and the COMPHY IP but accessing the COMPHY registers while one of the three clocks are disabled stalls the CPU. This happens if, for instance, the COMPHY driver probe is deferred (eg. the USB Vbus regulator driver is not yet visible). The MVPP2 driver which also needs these clocks (among others) will prepare/enable the clocks, then be deferred, and disable/unprepare them. Next COMPHY lane to be configured would produce an infinite stall. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-27phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third valueNathan Chancellor
After commit "linux/bits.h: Add compile time sanity check of GENMASK inputs" [1], arm64 defconfig builds started failing: In file included from ../include/linux/bits.h:22, from ../include/linux/bitops.h:5, from ../include/linux/kernel.h:12, from ../include/linux/clk.h:13, from ../drivers/phy/rockchip/phy-rockchip-inno-hdmi.c:9: ../drivers/phy/rockchip/phy-rockchip-inno-hdmi.c: In function 'inno_hdmi_phy_rk3328_power_on': ../include/linux/build_bug.h:16:45: error: negative width in bit-field '<anonymous>' 16 | #define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); })) | ^ ../include/linux/bits.h:24:18: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 24 | ((unsigned long)BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ | ^~~~~~~~~~~~~~~~~ ../include/linux/bits.h:39:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 39 | (GENMASK_INPUT_CHECK(high, low) + __GENMASK(high, low)) | ^~~~~~~~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-inno-hdmi.c:24:42: note: in expansion of macro 'GENMASK' 24 | #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) | ^~~~~~~ ../drivers/phy/rockchip/phy-rockchip-inno-hdmi.c:201:50: note: in expansion of macro 'UPDATE' 201 | #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 9) | ^~~~~~ ../drivers/phy/rockchip/phy-rockchip-inno-hdmi.c:1046:26: note: in expansion of macro 'RK3328_TERM_RESISTOR_CALIB_SPEED_7_0' 1046 | inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ As pointed out by Robin and Guenter, inno_write's val argument is an 8-bit value so having a mask larger than that doesn't make sense. This also matches the rest of the *_7_0 macros in this driver. [1]: https://lore.kernel.org/lkml/20190801230358.4193-2-rikard.falkeborn@gmail.com/ Reported-by: Andrzej Hajda <a.hajda@samsung.com> Reported-by: Guenter Roeck <linux@roeck-us.net> Reported-by: kernelci.org bot <bot@kernelci.org> Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Suggested-by: Guenter Roeck <linux@roeck-us.net> Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de>
2019-08-26phy: qcom-qmp: Correct ready status, againBjorn Andersson
Despite extensive testing of commit 885bd765963b ("phy: qcom-qmp: Correct READY_STATUS poll break condition") I failed to conclude that the PHYSTATUS bit of the PCS_STATUS register used in PCIe and USB3 falls as the PHY gets ready. Similar to the prior bug with UFS the code will generally get past the check before the transition and thereby "succeed". Correct the name of the register used PCIe and USB3 PHYs, replace mask_pcs_ready with a constant expression depending on the type of the PHY and check for the appropriate ready state. Cc: stable@vger.kernel.org Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Evan Green <evgreen@chromium.org> Cc: Niklas Cassel <niklas.cassel@linaro.org> Reported-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Fixes: 885bd765963b ("phy: qcom-qmp: Correct READY_STATUS poll break condition") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-26phy: qualcomm: phy-qcom-qmp: Add of_node_put() before returnNishka Dasgupta
Each iteration of for_each_available_child_of_node() puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence create a new label, err_node_put, that puts the previous node (child) before returning the required value. Also include the statement pm_runtime_disable() under this label in order to avoid repetition among mid-loop return conditions. Edit the mid-loop return statements to instead go to this new label err_node_put. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-26phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-currentYoshihiro Shimoda
The hardware manual should be revised, but the initial value of VBCTRL.OCCLREN is set to 1 actually. If the bit is set, the hardware clears VBCTRL.VBOUT and ADPCTRL.DRVVBUS registers automatically when the hardware detects over-current signal from a USB power switch. However, since the hardware doesn't have any registers which indicates over-current, the driver cannot handle it at all. So, if "is_otg_channel" hardware detects over-current, since ADPCTRL.DRVVBUS register is cleared automatically, the channel cannot be used after that. To resolve this behavior, this patch sets the VBCTRL.OCCLREN to 0 to keep ADPCTRL.DRVVBUS even if the "is_otg_channel" hardware detects over-current. (We assume a USB power switch itself protects over-current and turns the VBUS off.) This patch is inspired by a BSP patch from Kazuya Mizuguchi. Fixes: 1114e2d31731 ("phy: rcar-gen3-usb2: change the mode to OTG on the combined channel") Cc: <stable@vger.kernel.org> # v4.5+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-26phy: ti: am654-serdes: fix an use-after-free in serdes_am654_clk_register()Wen Yang
The regmap_node variable is still being used in the syscon_node_to_regmap() call after the of_node_put() call, which may result in use-after-free. Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC") Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Roger Quadros <rogerq@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: mvebu-a3700-comphy: Inform users if their firmware is too oldMiquel Raynal
PHY configuration has been implemented in the firmware and accessed through SMC calls. In the past, it worked magically if the bootloader was correctly doing the initializations. With up-to-date bindings, the kernel will need a recent firmware in order to do the initializations himself (we assume people must update their firmware along with their kernel). People might not understand why IPs that were working correctly before stopped to be probed suddendly. In this case, let's advise the users to update their firmware with a visual warning. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: samsung: disable bind/unbind platform driver featureMarek Szyprowski
Samsung PHY drivers control the power to the SoC core components needed by their client devices (USB HCDs, SATA, camera ISP bridge, DP encoder) to properly operate. Disabling PHYs in runtime usually causes the client device to crash with external abort exception or similar issue due to lack of API to notify clients about PHY removal. This patch removes the possiblity to unbind Samsung Exynos PHY drivers in runtime. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: core: document phy_calibrate()Marek Szyprowski
Commit 36914111e682 ("drivers: phy: add calibrate method") added support for generic phy_calibrate() method, but it didn't explain in detail when such method is supposed to be called. Add some more documentation directly to the phy.h to make it clean that it is intended to be called after every host controller reset. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: marvell: phy-mvebu-a3700-comphy: Add of_node_put() before returnNishka Dasgupta
Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return in two places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: marvell: phy-mvebu-cp110-comphy: Add of_node_put() before returnNishka Dasgupta
Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return in two places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: marvell: phy-armada38x-comphy: Add of_node_put() before returnNishka Dasgupta
Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: enable compile-testing for the Lantiq PHY driversMartin Blumenstingl
Unconditionally include the lantiq subdirectory in the phy Makefile. All drivers in there have their dependencies maintained. One of these (optional) dependencies is COMPILE_TEST, however this can only be evaluated when Kconfig scans the lantiq subdirectory. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-23phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHYMartin Blumenstingl
The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most other IP blocks on this SoC the register values are only 16-bit wide. Like other IP blocks on this SoC the register values are in big endian. The PHY embeds a PLL which can be configured in various modes. Only the 36MHz mode is supported for now, the other modes can be implemented when there's a board which actually needs them. OpenWrt uses the out-of-tree vendor driver and all supported boards there only need the 36MHz mode. There are two input clocks: - the "pdi" clock enables the register access - the "phy" clock is the clock input and enables the internal PLL There are two reset lines: - "phy" resets the PHY itself - the "pcie" reset line is shared between the PHY and the PCIe controller While the VRX200 SoC has only one PCIe controller and PHY the ARX300 uses two identical PCIe controllers and PHYs which are compatible with the PCIe controller and PHY on VRX200. Add a driver for this PHY so PCIe support can be enabled on these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-16phy: ti: am654-serdes: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Roger Quadros <rogerq@ti.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-9-sboyd@kernel.org Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-08-13phy: tegra: Add PCIe PIPE2UPHY supportVidya Sagar
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-07-01Merge tag 'phy-for-5.3' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next phy: for 5.3 *) Add a new PHY driver for Qualcomm PCIe2 PHY *) Add a new PHY driver for Mixel DPHY present in i.MX8 *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that PHY enable failed *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to calling a sleeping function from invalid context *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to imbalance powered flag *) Fix .cocci and sparse warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay phy: meson-g12a-usb3-pcie: disable locking for cr_regmap phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs dt-bindings: phy: Add documentation for mixel dphy dt-bindings: phy-pxa-usb: add bindings phy: renesas: rcar-gen3-usb2: fix imbalance powered flag phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting phy: qcom-qmp: Correct READY_STATUS poll break condition phy: ti: am654-serdes: Make serdes_am654_xlate() static phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings phy: samsung: Use struct_size() in devm_kzalloc() phy: qcom: Add Qualcomm PCIe2 PHY driver dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
2019-07-01Merge tag 'phy-for-5.2-rc_v2' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.2-rc *) Move Tegra124 PLL power supplies to be enabled by xusb-tegra124 *) Move Tegra210 PLL power supplies to be enabled by xusb-tegra210 *) Minor fixes: fix memory leaks at error path and addresses coverity. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.2-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: tegra: xusb: Add Tegra210 PLL power supplies phy: tegra: xusb: Add Tegra124 PLL power supplies dt-bindings: phy: tegra-xusb: List PLL power supplies phy: usb: phy-brcm-usb: Remove sysfs attributes upon driver removal phy: renesas: rcar-gen2: Fix memory leak at error paths phy: qcom-qusb2: fix missing assignment of ret when calling clk_prepare_enable
2019-06-25phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delayMarc Gonzalez
readl_poll_timeout() calls usleep_range() to sleep between reads. usleep_range() doesn't work efficiently for tiny values. Raise the polling delay in qcom_qmp_phy_enable() to bring it in line with the delay in qcom_qmp_phy_com_init(). Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-25phy: meson-g12a-usb3-pcie: disable locking for cr_regmapNeil Armstrong
Locking is not needed for the phy_g12a_usb3_pcie_cr_bus_read/write() and currently it causes the following BUG because of the usage of the regmap_read_poll_timeout() running in spinlock_irq, configured by regmap fast_io. Simply disable locking in the cr_regmap config since it's only used from the PHY init callback function. BUG: sleeping function called from invalid context at drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c:85 in_atomic(): 1, irqs_disabled(): 128, pid: 60, name: kworker/3:1 [snip] Workqueue: events deferred_probe_work_func Call trace: dump_backtrace+0x0/0x190 show_stack+0x14/0x20 dump_stack+0x90/0xb4 ___might_sleep+0xec/0x110 __might_sleep+0x50/0x88 phy_g12a_usb3_pcie_cr_bus_addr.isra.0+0x80/0x1a8 phy_g12a_usb3_pcie_cr_bus_read+0x34/0x1d8 _regmap_read+0x60/0xe0 _regmap_update_bits+0xc4/0x110 regmap_update_bits_base+0x60/0x90 phy_g12a_usb3_pcie_init+0xdc/0x210 phy_init+0x74/0xd0 dwc3_meson_g12a_probe+0x2cc/0x4d0 platform_drv_probe+0x50/0xa0 really_probe+0x20c/0x3b8 driver_probe_device+0x68/0x150 __device_attach_driver+0xa8/0x170 bus_for_each_drv+0x64/0xc8 __device_attach+0xd8/0x158 device_initial_probe+0x10/0x18 bus_probe_device+0x90/0x98 deferred_probe_work_func+0x94/0xe8 process_one_work+0x1e0/0x338 worker_thread+0x230/0x458 kthread+0x134/0x138 ret_from_fork+0x10/0x1c Fixes: 36077e16c050 ("phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-21phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCsGuido Günther
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since this is an IP core it will likely be found on others in the future. So instead of adding this to the nwl host driver make it a generic PHY driver. The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be added once the necessary system controller bits are in via mixel_dphy_devdata. Signed-off-by: Guido Günther <agx@sigxcpu.org> Co-developed-by: Robert Chiras <robert.chiras@nxp.com> Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-21phy: renesas: rcar-gen3-usb2: fix imbalance powered flagYoshihiro Shimoda
The powered flag should be set for any other phys anyway. Also the flag should be locked by the channel. Otherwise, after we have revised the device tree for the usb phy, the following warning happened during a second system suspend. And if the driver doesn't lock the flag, an imbalance is possible when enabling the regulator during system resume. So, this patch fixes the issues. < The warning > [ 56.026531] unbalanced disables for USB20_VBUS0 [ 56.031108] WARNING: CPU: 3 PID: 513 at drivers/regulator/core.c:2593 _regula tor_disable+0xe0/0x1c0 [ 56.040146] Modules linked in: rcar_du_drm rcar_lvds drm_kms_helper drm drm_p anel_orientation_quirks vsp1 videobuf2_vmalloc videobuf2_dma_contig videobuf2_me mops videobuf2_v4l2 videobuf2_common videodev snd_soc_rcar renesas_usbhs snd_soc _audio_graph_card media snd_soc_simple_card_utils crct10dif_ce renesas_usb3 snd_ soc_ak4613 rcar_fcp pwm_rcar usb_dmac phy_rcar_gen3_usb3 pwm_bl ipv6 [ 56.074047] CPU: 3 PID: 513 Comm: kworker/u16:19 Not tainted 5.2.0-rc3-00001- g5f20a19 #6 [ 56.082129] Hardware name: Renesas Salvator-X board based on r8a7795 ES2.0+ ( DT) [ 56.089524] Workqueue: events_unbound async_run_entry_fn [ 56.094832] pstate: 40000005 (nZcv daif -PAN -UAO) [ 56.099617] pc : _regulator_disable+0xe0/0x1c0 [ 56.104054] lr : _regulator_disable+0xe0/0x1c0 [ 56.108489] sp : ffff0000121c3ae0 [ 56.111796] x29: ffff0000121c3ae0 x28: 0000000000000000 [ 56.117102] x27: 0000000000000000 x26: ffff000010fe0e60 [ 56.122407] x25: 0000000000000002 x24: 0000000000000001 [ 56.127712] x23: 0000000000000002 x22: ffff8006f99d4000 [ 56.133017] x21: ffff8006f99cc000 x20: ffff8006f9846800 [ 56.138322] x19: ffff8006f9846800 x18: ffffffffffffffff [ 56.143626] x17: 0000000000000000 x16: 0000000000000000 [ 56.148931] x15: ffff0000112f96c8 x14: ffff0000921c37f7 [ 56.154235] x13: ffff0000121c3805 x12: ffff000011312000 [ 56.159540] x11: 0000000005f5e0ff x10: ffff0000112f9f20 [ 56.164844] x9 : ffff0000112d3018 x8 : 00000000000001ad [ 56.170149] x7 : 00000000ffffffcc x6 : ffff8006ff768180 [ 56.175453] x5 : ffff8006ff768180 x4 : 0000000000000000 [ 56.180758] x3 : ffff8006ff76ef10 x2 : ffff8006ff768180 [ 56.186062] x1 : 3d2eccbaead8fb00 x0 : 0000000000000000 [ 56.191367] Call trace: [ 56.193808] _regulator_disable+0xe0/0x1c0 [ 56.197899] regulator_disable+0x40/0x78 [ 56.201820] rcar_gen3_phy_usb2_power_off+0x3c/0x50 [ 56.206692] phy_power_off+0x48/0xd8 [ 56.210263] usb_phy_roothub_power_off+0x30/0x50 [ 56.214873] usb_phy_roothub_suspend+0x1c/0x50 [ 56.219311] hcd_bus_suspend+0x13c/0x168 [ 56.223226] generic_suspend+0x4c/0x58 [ 56.226969] usb_suspend_both+0x1ac/0x238 [ 56.230972] usb_suspend+0xcc/0x170 [ 56.234455] usb_dev_suspend+0x10/0x18 [ 56.238199] dpm_run_callback.isra.6+0x20/0x68 [ 56.242635] __device_suspend+0x110/0x308 [ 56.246637] async_suspend+0x24/0xa8 [ 56.250205] async_run_entry_fn+0x40/0xf8 [ 56.254210] process_one_work+0x1e0/0x320 [ 56.258211] worker_thread+0x40/0x450 [ 56.261867] kthread+0x124/0x128 [ 56.265094] ret_from_fork+0x10/0x18 [ 56.268661] ---[ end trace 86d7ec5de5c517af ]--- [ 56.273290] phy phy-ee080200.usb-phy.10: phy poweroff failed --> -5 Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 549b6b55b005 ("phy: renesas: rcar-gen3-usb2: enable/disable independent irqs") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-21phy: qcom-qmp: Drop useless msm8998_pciephy_cfg settingMarc Gonzalez
'mask_com_pcs_ready' is only useful if 'has_phy_com_ctrl' is true. Since msm8998_pciephy_cfg.has_phy_com_ctrl is false, let's drop msm8998_pciephy_cfg.mask_com_pcs_ready altogether. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-21phy: qcom-qmp: Correct READY_STATUS poll break conditionBjorn Andersson
After issuing a PHY_START request to the QMP, the hardware documentation states that the software should wait for the PCS_READY_STATUS to become 1. With the introduction of commit c9b589791fc1 ("phy: qcom: Utilize UFS reset controller") an additional 1ms delay was introduced between the start request and the check of the status bit. This greatly increases the chances for the hardware to actually becoming ready before the status bit is read. The result can be seen in that UFS PHY enabling is now reported as a failure in 10% of the boots on SDM845, which is a clear regression from the previous rare/occasional failure. This patch fixes the "break condition" of the poll to check for the correct state of the status bit. Unfortunately PCIe on 8996 and 8998 does not specify the mask_pcs_ready register, which means that the code checks a bit that's always 0. So the patch also fixes these, in order to not regress these targets. Fixes: 73d7ec899bd8 ("phy: qcom-qmp: Add msm8998 PCIe QMP PHY support") Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: stable@vger.kernel.org Cc: Evan Green <evgreen@chromium.org> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-21phy: ti: am654-serdes: Make serdes_am654_xlate() staticYueHaibing
Fix sparse warning: drivers/phy/ti/phy-am654-serdes.c:250:12: warning: symbol 'serdes_am654_xlate' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-20phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warningsYueHaibing
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-20phy: samsung: Use struct_size() in devm_kzalloc()Gustavo A. R. Silva
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct samsung_usb2_phy_driver { ... struct samsung_usb2_phy_instance instances[0]; }; instance = devm_kzalloc(dev, sizeof(struct samsung_usb2_phy_driver) + count * sizeof(struct samsung_usb2_phy_instance), GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = devm_kzalloc(dev, struct_size(instance, instances, count), GFP_KERNEL); This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 235Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 53 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.904365654@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>