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path: root/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
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2020-08-07drm/amd/powerplay: update swSMU VCN/JPEG PG logicsEvan Quan
Add lock protections and avoid unnecessary actions if the PG state is already the same as required. Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Matt Coffin <mcoffin13@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: tag swSMU code layersEvan Quan
Per designs, the swSMU code is separated into four layers. And the typical calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> smu_cmn.c. Compile errors will come out for any violations. This can help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c -> amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: move SMC message issuing APIs to smu_cmn.cEvan Quan
Considering they can be shared by all ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: update the tables init relatedEvan Quan
To avoid cross calling and maintain clear code layer. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: move table setting common code to smu_cmn.cEvan Quan
As they are shared by all ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: maximum code sharing around watermarks settingEvan Quan
Maximum code sharing. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: move more APIs to smu_cmn.cEvan Quan
Considering they are shared by all ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: common API for disabling all features with exceptionEvan Quan
We are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: move ppfeature mask setting to smu_cmn.cEvan Quan
Considering they are shared by all ASICs. And we are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: implement smu_cmn_get_enabled_mask() for all ASICsEvan Quan
Instead of having each for smu v11 and v12. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.cEvan Quan
Considering it is shared by all ASICs and smu_cmn.c should be the right place. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: drop unused codeEvan Quan
Those code were obsoleted by new common API smu_cmn_to_asic_specific_index(). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amd/powerplay: unify swSMU index to asic specific index mappingEvan Quan
By this we can drop redundant code. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-21drm/amdgpu: add read amdgpu_gfxoff status in debugfsJinzhou.Su
Add interface for SMU12 device, used by UMR. v2: fix code style Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/powerplay: drop unused APIs and parametersEvan Quan
Leftover of previous performance level setting cleanups. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2Evan Quan
By moving the implemention to renoir_ppt.c considering it's really ASIC specific. V2: fix compile warnings below drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); ^~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/powerplay: drop unnecessary wrappersEvan Quan
By calling the target APIs directly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14drm/amdgpu/powerplay: Modify SMC message name for setting power profile modechen gong
I consulted Cai Land(Chuntian.Cai@amd.com), he told me corresponding smc message name to fSMC_MSG_SetWorkloadMask() is "PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir. Strange though it may seem, but it's a fact. Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14drm/amdgpu/powerplay: Target power profile mode should be the second ↵chen gong
parameter of renoir_set_power_profile_mode A small mistake Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-10drm/amd/powerplay: revise calling chain on retrieving frequency rangeEvan Quan
This helps to maintain clear code layers and drop unnecessary parameter. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-10drm/amd/powerplay: revise calling chain on setting soft limitEvan Quan
This helps to maintain clear code layers and drop unnecessary parameter. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-10drm/amd/powerplay: drop unused code and wrapper around clock retrievingEvan Quan
Clean code by dropping unnecessary ones. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-10drm/amd/powerplay: unshare the code for retrieving current clock frequencyEvan Quan
By moving them into asic specific file. Since they are really ASIC specific. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-10drm/amd/powerplay: drop unnecessary wrappers around clock retrievingEvan Quan
By calling the target APIs directly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unnecessary wrapper .populate_smc_tablesEvan Quan
Since .populate_smc_tables is just a wrapper of .set_default_dpm_table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: correct the APIs' namingEvan Quan
'UVD' is a HW engine name for Vega20 and before ASICs. For newer ASICs, the similar engine is named as 'VCN'. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: forbid to use pr_err/warn/info/debugEvan Quan
Use dev_err/warn/info/dbg instead. They are more MGPU friendly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: use MGPU friendly err/warn/info/dbg messagesEvan Quan
Use dev_err/warn/info/dbg instead of pr_err/warn/info/debug. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: use existed smu_dpm_set* interfaces to implement ↵Huang Rui
powergate functions Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amdgpu/powerplay:avoid to show invalid DPM table infoYuxian Dai
for different ASIC support different the number of DPM levels, we should avoid to show the invalid level value. v1 -> v2: follow the suggestion,clarifiy the description for this change Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/powerplay: fix resume failed as smu table initialize early exitPrike Liang
When the amdgpu in the suspend/resume loop need notify the dpm disabled, otherwise the smu table will be uninitialize and result in resume failed. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Tested-by: Mengbing Wang <Mengbing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amdgpu: cache smu fw version infoJohn Clements
reduce cmd submission to smu by caching version info Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/powerplay: properly set the dpm_enabled stateEvan Quan
On the ASIC powered down(in baco or system suspend), the dpm_enabled will be set as false. Then all access (e.g. df state setting issued on RAS error event) to SMU will be blocked. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amd/powerplay: fix a typoNirmoy Das
Util -> Until Fixes: 567c8fc4a0d28b63f ("drm/amd/powerplay: implement the is_dpm_running()") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amd/powerplay: implement the is_dpm_running()Prike Liang
As the pmfw hasn't exported the interface of SMU feature mask to APU SKU so just force on all the features to driver inquired interface at early initial stage. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-03drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLKYuxian Dai
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-13drm/amdgpu/swsmu: clean up unused header in swsmuKevin Wang
clean up unused header in swsmu driver stack: 1. pp_debug.h 2. amd_pcie.h 3. soc15_common.h Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS casePrike Liang
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export fclk frequency to user usage. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05drm/amdgpu: add lock option for smu_set_soft_freq_range()Chengming Gui
Add lock_needed param for smu_set_soft_freq_range() Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-28drm/amdgpu/powerplay: Remove deprecated smc_read_argMatt Coffin
The new interface reads the argument in the call to send the message, so this is no longer needed, and shouldn't be used for concurrency safety reasons. Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-28drm/amdgpu/powerplay: Refactor SMU message handling for safetyMatt Coffin
Move the responsibility for reading argument registers into the smu_send_smc_msg* implementations, so that adding a message-sending lock to protect the SMU registers will result in the lock still being held when the argument is read. v2: transition smu_v12_0, it's asics, and vega20 Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-28drm/amdgpu/powerplay: nv1x, renior copy dcn clock settings of watermark to ↵Hersen Wu
smu during boot up dc to pplib interface is changed for navi1x, renoir. display_config_changed is not called by dc anymore. smu_write_watermarks_table is not executed for navi1x, renoir during boot up. solution: call smu_write_watermarks_table just after dc pass watermark clock settings to pplib Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/powerplay: suppress nonsupport profile mode overrun messagePrike Liang
SMU12 not support WORKLOAD_DEFAULT_BIT and WORKLOAD_PPLIB_POWER_SAVING_BIT. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2Evan Quan
By this, we can avoid to pass in the VRAM address on every table transferring. That puts extra unnecessary traffics on SMU on some cases(e.g. polling the amdgpu_pm_info sysfs interface). V2: document what the driver table is for and how it works Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/powerplay: cache the watermark settings on system memoryEvan Quan
So that we do not need to allocate a piece of VRAM for it. This is a preparation for coming change which unifies the VRAM address for all driver tables interaction with SMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu/smu: make the set_performance_level logic easier to followAlex Deucher
Have every asic provide a callback for this rather than a mix of generic and asic specific code. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amdgpu/smu: add metrics table lock for renoir (v2)Alex Deucher
To protect access to the metrics table. v2: unlock on error Bug: https://gitlab.freedesktop.org/drm/amd/issues/900 Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-18drm/amd/powerplay: Add SMU WMTABLE Validity Check for RenoirZhan Liu
[Why] SMU watermark table (WMTABLE) validity check is missing on Renoir. This validity check is very useful for checking whether WMTABLE is updated successfully. [How] Add SMU watermark validity check. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-11drm/amd/powerplay: correct the value retrieved through GPU_LOAD sensor interfaceXiaomeng Hou
the unit of variable AverageGfxActivity defined in smu12 metrics struct is centi, so the retrieved value should be divided by 100 before return. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-11drm/amd/powerplay: implement the get_enabled_mask callback for smu12Xiaomeng Hou
implement sensor interface of feature mask for debugfs. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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