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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2022-07-05clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_configAndi Kleen
2022-07-05clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar
2022-06-17clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang
2022-06-17clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda
2022-06-17clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven
2022-06-13clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven
2022-06-13clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven
2022-06-13clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven
2022-06-13clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven
2022-06-13clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven
2022-06-13clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven
2022-06-13clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang
2022-06-13clk: renesas: r8a779f0: Add thermal clockWolfram Sang
2022-06-07clk: renesas: rzg2l: Fix reset status functionBiju Das
2022-06-06clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen
2022-06-06clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen
2022-06-06clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy
2022-06-06clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy
2022-06-06clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das
2022-06-06clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das
2022-05-29Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds
2022-05-19clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal
2022-05-19clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das