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path: root/arch/mips/mm/c-tx39.c
AgeCommit message (Expand)Author
2015-06-21MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'Maciej W. Rozycki
2013-07-14MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle
2012-03-28Disintegrate asm/system.h for MIPSDavid Howells
2011-10-20MIPS: cache: Provide cache flush operations for XFSRalf Baechle
2011-04-06update David Miller's old email addressJustin P. Mattock
2009-06-24MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle
2008-09-05[MIPS] TX39xx: Add missing local_flush_icache_range initializationAtsushi Nemoto
2008-09-05[MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer
2008-04-07[MIPS] Handle aliases in vmalloc correctly.Ralf Baechle
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle
2007-03-07[MIPS] TX39: Remove redundant tx39_blast_icache() callsAtsushi Nemoto
2006-10-01[MIPS] Remove __flush_icache_pageAtsushi Nemoto
2006-09-27[MIPS] Retire flush_icache_page from mm use.Ralf Baechle
2006-04-19[MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle
2006-03-18[MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto
2006-02-14[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds
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