diff options
Diffstat (limited to 'sound/soc/fsl/imx-ssi.c')
| -rw-r--r-- | sound/soc/fsl/imx-ssi.c | 57 |
1 files changed, 25 insertions, 32 deletions
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c index 06790615e04e..9038b61317be 100644 --- a/sound/soc/fsl/imx-ssi.c +++ b/sound/soc/fsl/imx-ssi.c @@ -1,35 +1,28 @@ -/* - * imx-ssi.c -- ALSA Soc Audio Layer - * - * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de> - * - * This code is based on code copyrighted by Freescale, - * Liam Girdwood, Javier Martin and probably others. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * The i.MX SSI core has some nasty limitations in AC97 mode. While most - * sane processor vendors have a FIFO per AC97 slot, the i.MX has only - * one FIFO which combines all valid receive slots. We cannot even select - * which slots we want to receive. The WM9712 with which this driver - * was developed with always sends GPIO status data in slot 12 which - * we receive in our (PCM-) data stream. The only chance we have is to - * manually skip this data in the FIQ handler. With sampling rates different - * from 48000Hz not every frame has valid receive data, so the ratio - * between pcm data and GPIO status data changes. Our FIQ handler is not - * able to handle this, hence this driver only works with 48000Hz sampling - * rate. - * Reading and writing AC97 registers is another challenge. The core - * provides us status bits when the read register is updated with *another* - * value. When we read the same register two times (and the register still - * contains the same value) these status bits are not set. We work - * around this by not polling these bits but only wait a fixed delay. - * - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// imx-ssi.c -- ALSA Soc Audio Layer +// +// Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de> +// +// This code is based on code copyrighted by Freescale, +// Liam Girdwood, Javier Martin and probably others. +// +// The i.MX SSI core has some nasty limitations in AC97 mode. While most +// sane processor vendors have a FIFO per AC97 slot, the i.MX has only +// one FIFO which combines all valid receive slots. We cannot even select +// which slots we want to receive. The WM9712 with which this driver +// was developed with always sends GPIO status data in slot 12 which +// we receive in our (PCM-) data stream. The only chance we have is to +// manually skip this data in the FIQ handler. With sampling rates different +// from 48000Hz not every frame has valid receive data, so the ratio +// between pcm data and GPIO status data changes. Our FIQ handler is not +// able to handle this, hence this driver only works with 48000Hz sampling +// rate. +// Reading and writing AC97 registers is another challenge. The core +// provides us status bits when the read register is updated with *another* +// value. When we read the same register two times (and the register still +// contains the same value) these status bits are not set. We work +// around this by not polling these bits but only wait a fixed delay. #include <linux/clk.h> #include <linux/delay.h> |