diff options
Diffstat (limited to 'drivers/net/can/ctucanfd/ctucanfd_kregs.h')
| -rw-r--r-- | drivers/net/can/ctucanfd/ctucanfd_kregs.h | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/drivers/net/can/ctucanfd/ctucanfd_kregs.h b/drivers/net/can/ctucanfd/ctucanfd_kregs.h index edc1c1a24348..0c181ab51bf8 100644 --- a/drivers/net/can/ctucanfd/ctucanfd_kregs.h +++ b/drivers/net/can/ctucanfd/ctucanfd_kregs.h @@ -4,9 +4,9 @@ * CTU CAN FD IP Core * * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU - * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded + * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU - * Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded + * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded * * Project advisors: * Jiri Novak <jnovak@fel.cvut.cz> @@ -64,9 +64,12 @@ enum ctu_can_fd_can_registers { CTUCANFD_RX_DATA = 0x6c, CTUCANFD_TX_STATUS = 0x70, CTUCANFD_TX_COMMAND = 0x74, + CTUCANFD_TXTB_INFO = 0x76, CTUCANFD_TX_PRIORITY = 0x78, CTUCANFD_ERR_CAPT = 0x7c, + CTUCANFD_RETR_CTR = 0x7d, CTUCANFD_ALC = 0x7e, + CTUCANFD_TS_INFO = 0x7f, CTUCANFD_TRV_DELAY = 0x80, CTUCANFD_SSP_CFG = 0x82, CTUCANFD_RX_FR_CTR = 0x84, @@ -102,8 +105,12 @@ enum ctu_can_fd_can_registers { #define REG_MODE_STM BIT(2) #define REG_MODE_AFM BIT(3) #define REG_MODE_FDE BIT(4) +#define REG_MODE_TTTM BIT(5) +#define REG_MODE_ROM BIT(6) #define REG_MODE_ACF BIT(7) #define REG_MODE_TSTM BIT(8) +#define REG_MODE_RXBAM BIT(9) +#define REG_MODE_SAM BIT(11) #define REG_MODE_RTRLE BIT(16) #define REG_MODE_RTRTH GENMASK(20, 17) #define REG_MODE_ILBP BIT(21) @@ -123,8 +130,10 @@ enum ctu_can_fd_can_registers { #define REG_STATUS_EWL BIT(6) #define REG_STATUS_IDLE BIT(7) #define REG_STATUS_PEXS BIT(8) +#define REG_STATUS_STCNT BIT(16) /* COMMAND registers */ +#define REG_COMMAND_RXRPMV BIT(1) #define REG_COMMAND_RRB BIT(2) #define REG_COMMAND_CDO BIT(3) #define REG_COMMAND_ERCRST BIT(4) @@ -263,8 +272,12 @@ enum ctu_can_fd_can_registers { #define REG_TX_STATUS_TX2S GENMASK(7, 4) #define REG_TX_STATUS_TX3S GENMASK(11, 8) #define REG_TX_STATUS_TX4S GENMASK(15, 12) +#define REG_TX_STATUS_TX5S GENMASK(19, 16) +#define REG_TX_STATUS_TX6S GENMASK(23, 20) +#define REG_TX_STATUS_TX7S GENMASK(27, 24) +#define REG_TX_STATUS_TX8S GENMASK(31, 28) -/* TX_COMMAND registers */ +/* TX_COMMAND TXTB_INFO registers */ #define REG_TX_COMMAND_TXCE BIT(0) #define REG_TX_COMMAND_TXCR BIT(1) #define REG_TX_COMMAND_TXCA BIT(2) @@ -272,18 +285,29 @@ enum ctu_can_fd_can_registers { #define REG_TX_COMMAND_TXB2 BIT(9) #define REG_TX_COMMAND_TXB3 BIT(10) #define REG_TX_COMMAND_TXB4 BIT(11) +#define REG_TX_COMMAND_TXB5 BIT(12) +#define REG_TX_COMMAND_TXB6 BIT(13) +#define REG_TX_COMMAND_TXB7 BIT(14) +#define REG_TX_COMMAND_TXB8 BIT(15) +#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16) /* TX_PRIORITY registers */ #define REG_TX_PRIORITY_TXT1P GENMASK(2, 0) #define REG_TX_PRIORITY_TXT2P GENMASK(6, 4) #define REG_TX_PRIORITY_TXT3P GENMASK(10, 8) #define REG_TX_PRIORITY_TXT4P GENMASK(14, 12) +#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16) +#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20) +#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24) +#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28) -/* ERR_CAPT ALC registers */ +/* ERR_CAPT RETR_CTR ALC TS_INFO registers */ #define REG_ERR_CAPT_ERR_POS GENMASK(4, 0) #define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5) +#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8) #define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16) #define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21) +#define REG_ERR_CAPT_TS_BITS GENMASK(29, 24) /* TRV_DELAY SSP_CFG registers */ #define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0) |