diff options
Diffstat (limited to 'drivers/gpu/drm/msm')
14 files changed, 99 insertions, 86 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 8e6650aaa8a2..e5a42ebda4d7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = { .vbif = msm8998_vbif, .reg_dma_count = 0, .perf = &msm8998_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 3e3b9967dd12..46b0e9e50ced 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sdm845_regdma, .perf = &sdm845_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 29bcbc88cd5a..0d9c627b467b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -223,7 +223,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8150_regdma, .perf = &sm8150_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index fb8cdcd6bfe9..b01dfd47ed2f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -201,7 +201,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8150_regdma, .perf = &sc8180x_perf_data, - .mdss_irqs = IRQ_SC8180X_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR) | \ + BIT(MDP_INTF5_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 233ea66155bd..857f8aab4e0d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8250_regdma, .perf = &sm8250_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 433f7b259f7b..19dbc72aa137 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -146,7 +146,11 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sdm845_regdma, .perf = &sc7180_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index e741cb3e7888..8b276e0b5b71 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -119,7 +119,11 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6115_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index c0f95473611d..9c4ad9795c1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -109,7 +109,11 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &qcm2290_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index a5818878ee0a..7846c2f3a1fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -214,7 +214,13 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8350_regdma, .perf = &sm8350_perf_data, - .mdss_irqs = IRQ_SM8350_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 0b10e2060591..11ef3b8f1fa4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -147,7 +147,12 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sc7280_perf_data, - .mdss_irqs = IRQ_SC7280_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 0d100f7b3c03..e83df053838d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -205,7 +205,18 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sc8280xp_regdma, .perf = &sc8280xp_perf_data, - .mdss_irqs = IRQ_SC8280XP_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + BIT(MDP_INTF4_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR) | \ + BIT(MDP_INTF6_7xxx_INTR) | \ + BIT(MDP_INTF7_7xxx_INTR) | \ + BIT(MDP_INTF8_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index fa603034ffab..8205b5076bd3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -222,7 +222,13 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8450_regdma, .perf = &sm8450_perf_data, - .mdss_irqs = IRQ_SM8450_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 9acd9fcf39a1..aafb1680c9a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -227,7 +227,13 @@ static const struct dpu_mdss_cfg sm8550_dpu_cfg = { .reg_dma_count = 1, .dma_cfg = &sm8450_regdma, .perf = &sm8550_perf_data, - .mdss_irqs = IRQ_SM8450_MASK, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 547546d85474..0fcde3757b72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -102,79 +102,6 @@ #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) -#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR)) - -#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR)) - -#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR)) - -#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR)) - -#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR)) - -#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR) | \ - BIT(MDP_INTF5_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR)) - -#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR) | \ - BIT(MDP_INTF4_7xxx_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR) | \ - BIT(MDP_INTF6_7xxx_INTR) | \ - BIT(MDP_INTF7_7xxx_INTR) | \ - BIT(MDP_INTF8_7xxx_INTR)) - -#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR)) - #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ |