diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/at91/clk-pll.c | 3 | ||||
| -rw-r--r-- | drivers/clk/hisilicon/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/clk/hisilicon/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3670.c | 1016 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.c | 6 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 2 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos-audss.c | 1 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos3250.c | 1 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 226 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 42 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 76 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 33 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-s3c2410.c | 43 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-s3c2412.c | 43 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-s3c2443.c | 43 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-s3c64xx.c | 66 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-s5pv210.c | 41 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk.c | 23 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk.h | 18 |
19 files changed, 1130 insertions, 561 deletions
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 72b6091eb7b9..dc7fbc796cb6 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, { struct clk_pll *pll = to_clk_pll(hw); + if (!pll->div || !pll->mul) + return 0; + return (parent_rate / pll->div) * (pll->mul + 1); } diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index becdb1dd21b5..30fad7ab0d88 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -21,6 +21,13 @@ config COMMON_CLK_HI3660 help Build the clock driver for hi3660. +config COMMON_CLK_HI3670 + bool "Hi3670 Clock Driver" + depends on ARCH_HISI || COMPILE_TEST + default ARCH_HISI + help + Build the clock driver for hi3670. + config COMMON_CLK_HI3798CV200 tristate "Hi3798CV200 Clock Driver" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 2a714c0f9657..b2441b99f3d5 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o +obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c new file mode 100644 index 000000000000..fd8c837a6ea3 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -0,0 +1,1016 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. + * Author: chenjun <chenjun14@huawei.com> + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +#include <dt-bindings/clock/hi3670-clock.h> +#include <linux/clk-provider.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "clk.h" + +static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = { + { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, }, + { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, }, + { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, }, + { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, }, + { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, }, + { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, }, + { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, }, + { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, }, + { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, }, + { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, }, + { HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, }, + { HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, }, + { HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, }, + { HI3670_PCLK, "pclk", NULL, 0, 20000000, }, + { HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, }, + { HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, }, + { HI3670_OSC32K, "osc32k", NULL, 0, 32764, }, + { HI3670_OSC19M, "osc19m", NULL, 0, 19200000, }, + { HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, }, + { HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, }, +}; + +/* crgctrl */ +static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = { + { HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", + 1, 7, 0, }, + { HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", + 1, 6, 0, }, + { HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt", + 1, 6, 0, }, + { HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt", + 1, 6, 0, }, + { HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt", + 1, 4, 0, }, + { HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", + 1, 5, 0, }, + { HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl", + 1, 1, 0, }, + { HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0", + 1, 1, 0, }, + { HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0", + 1, 60, 0, }, + { HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en", + 1, 1, 0, }, + { HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys", + 1, 1, 0, }, + { HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold", + 1, 1, 0, }, + { HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle", + 1, 1, 0, }, + { HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", + 1, 1, 0, }, + { HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold", + 1, 1, 0, }, + { HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold", + 1, 1, 0, }, + { HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt", + 1, 10, 0, }, + { HI3670_CLK_FACTOR_RXDPHY, "clk_factor_rxdphy", "clk_andgt_rxdphy", + 1, 6, 0, }, +}; + +static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = { + { HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1", + CLK_SET_RATE_PARENT, 0x0, 0, 0, }, + { HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2", + CLK_SET_RATE_PARENT, 0x0, 3, 0, }, + { HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3", + CLK_SET_RATE_PARENT, 0x0, 27, 0, }, + { HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1", + CLK_SET_RATE_PARENT, 0x460, 16, 0, }, + { HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2", + CLK_SET_RATE_PARENT, 0x460, 18, 0, }, + { HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3", + CLK_SET_RATE_PARENT, 0x460, 20, 0, }, + { HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2", + CLK_SET_RATE_PARENT, 0x410, 27, 0, }, + { HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3", + CLK_SET_RATE_PARENT, 0x410, 28, 0, }, + { HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4", + CLK_SET_RATE_PARENT, 0x410, 26, 0, }, + { HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6", + CLK_SET_RATE_PARENT, 0x410, 30, 0, }, + { HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7", + CLK_SET_RATE_PARENT, 0x410, 29, 0, }, + { HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 0, 0, }, + { HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 1, 0, }, + { HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 2, 0, }, + { HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 3, 0, }, + { HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 4, 0, }, + { HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 5, 0, }, + { HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 6, 0, }, + { HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 7, 0, }, + { HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 8, 0, }, + { HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 9, 0, }, + { HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 10, 0, }, + { HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 11, 0, }, + { HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 12, 0, }, + { HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 13, 0, }, + { HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 14, 0, }, + { HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 15, 0, }, + { HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 16, 0, }, + { HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 17, 0, }, + { HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 20, 0, }, + { HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x10, 21, 0, }, + { HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x50, 28, 0, }, + { HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus", + CLK_SET_RATE_PARENT, 0x50, 29, 0, }, + { HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x0, 25, 0, }, + { HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus", + CLK_SET_RATE_PARENT, 0x40, 1, 0, }, + { HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x0, 21, 0, }, + { HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus", + CLK_SET_RATE_PARENT, 0x420, 7, 0, }, + { HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie", + CLK_SET_RATE_PARENT, 0x420, 9, 0, }, + { HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie", + CLK_SET_RATE_PARENT, 0x30, 12, 0, }, + { HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus", + CLK_SET_RATE_PARENT, 0x40, 13, 0, }, + { HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus", + CLK_SET_RATE_PARENT, 0x420, 21, 0, }, + { HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x30, 1, 0, }, + { HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus", + CLK_SET_RATE_PARENT, 0x0, 5, 0, }, + { HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq", + CLK_SET_RATE_PARENT, 0x22C, 28, 0, }, + { HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq", + CLK_SET_RATE_PARENT, 0x50, 14, 0, }, + { HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys", + CLK_SET_RATE_PARENT, 0x40, 17, 0, }, + { HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x0, 30, 0, }, + { HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys", + CLK_SET_RATE_PARENT, 0x40, 19, 0, }, + { HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x050, 9, 0, }, + { HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x050, 13, 0, }, + { HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x480, 10, 0, }, + { HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x480, 9, 0, }, + { HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x480, 15, 0, }, + { HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x050, 15, 0, }, + { HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x050, 12, 0, }, + { HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x050, 11, 0, }, + { HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth", + CLK_SET_RATE_PARENT, 0x20, 11, 0, }, + { HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth", + CLK_SET_RATE_PARENT, 0x20, 14, 0, }, + { HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth", + CLK_SET_RATE_PARENT, 0x20, 11, 0, }, + { HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth", + CLK_SET_RATE_PARENT, 0x20, 14, 0, }, + { HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl", + CLK_SET_RATE_PARENT, 0x20, 12, 0, }, + { HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl", + CLK_SET_RATE_PARENT, 0x20, 15, 0, }, + { HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl", + CLK_SET_RATE_PARENT, 0x20, 12, 0, }, + { HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl", + CLK_SET_RATE_PARENT, 0x20, 15, 0, }, + { HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0", + CLK_SET_RATE_PARENT, 0x20, 10, 0, }, + { HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x20, 7, 0, }, + { HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x20, 27, 0, }, + { HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x10, 31, 0, }, + { HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x20, 7, 0, }, + { HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x20, 27, 0, }, + { HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c", + CLK_SET_RATE_PARENT, 0x10, 31, 0, }, + { HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi", + CLK_SET_RATE_PARENT, 0x20, 9, 0, }, + { HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi", + CLK_SET_RATE_PARENT, 0x40, 4, 0, }, + { HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi", + CLK_SET_RATE_PARENT, 0x20, 9, 0, }, + { HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi", + CLK_SET_RATE_PARENT, 0x40, 4, 0, }, + { HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys", + CLK_SET_RATE_PARENT, 0x40, 0, 0, }, + { HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys", + CLK_SET_RATE_PARENT, 0x410, 19, 0, }, + { HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys", + CLK_SET_RATE_PARENT, 0x420, 8, 0, }, + { HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi", + CLK_SET_RATE_PARENT, 0x420, 5, 0, }, + { HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi", + CLK_SET_RATE_PARENT, 0x050, 4, 0, }, + { HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie", + CLK_SET_RATE_PARENT, 0x470, 14, 0, }, + { HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie", + CLK_SET_RATE_PARENT, 0x470, 12, 0, }, + { HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie", + CLK_SET_RATE_PARENT, 0x470, 13, 0, }, + { HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie", + CLK_SET_RATE_PARENT, 0x470, 15, 0, }, + { HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp", + CLK_SET_RATE_PARENT, 0x0, 26, 0, }, + { HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp", + CLK_SET_RATE_PARENT, 0x20, 31, 0, }, + { HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans", + CLK_SET_RATE_PARENT, 0x30, 24, 0, }, + { HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans", + CLK_SET_RATE_PARENT, 0x30, 25, 0, }, + { HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp", + CLK_SET_RATE_PARENT, 0x20, 0, 0, }, + { HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192", + CLK_SET_RATE_PARENT, 0x30, 8, 0, }, + { HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192", + CLK_SET_RATE_PARENT, 0x30, 9, 0, }, + { HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0", + CLK_SET_RATE_PARENT, 0x30, 19, 0, }, + { HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1", + CLK_SET_RATE_PARENT, 0x40, 20, 0, }, + { HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao", + CLK_SET_RATE_PARENT, 0x00, 13, 0, }, + { HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys", + CLK_SET_RATE_PARENT, 0, 1, 0, }, + { HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys", + CLK_SET_RATE_PARENT, 0, 1, 0, }, + { HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0", + CLK_SET_RATE_PARENT, 0x50, 16, 0, }, + { HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1", + CLK_SET_RATE_PARENT, 0x50, 17, 0, }, + { HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2", + CLK_SET_RATE_PARENT, 0x50, 18, 0, }, + { HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg", + CLK_SET_RATE_PARENT, 0x030, 20, 0, }, + { HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg", + CLK_SET_RATE_PARENT, 0x030, 21, 0, }, + { HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg", + CLK_SET_RATE_PARENT, 0x030, 22, 0, }, + { HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys", + CLK_SET_RATE_PARENT, 0x030, 28, 0, }, + { HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys", + CLK_SET_RATE_PARENT, 0x030, 29, 0, }, + { HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys", + CLK_SET_RATE_PARENT, 0x030, 30, 0, }, + { HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys", + CLK_SET_RATE_PARENT, 0x030, 31, 0, }, + { HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys", + CLK_SET_RATE_PARENT, 0x40, 6, 0, }, +}; + +static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = { + { HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus", + CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus", + CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll", + CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys", + CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll", + CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys", + CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm", + CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m", + CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi", + CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp", + CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2", + CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2", + CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0", + CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0", + CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6", + CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec", + CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc", + CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm", + CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics", + CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus", + CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, 0, }, +}; + +static const char *const +clk_mux_sysbus_p[] = { "clk_ppll1", "clk_ppll0", }; +static const char *const +clk_mux_vcodecbus_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", + "clk_invalid", "clk_ppll2", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_ppll3", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", }; +static const char *const +clk_mux_sd_sys_p[] = { "clk_sd_sys", "clk_div_sd", }; +static const char *const +clk_mux_sd_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", }; +static const char *const +clk_mux_sdio_sys_p[] = { "clk_sdio_sys", "clk_div_sdio", }; +static const char *const +clk_mux_sdio_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", }; +static const char *const +clk_mux_a53hpm_p[] = { "clk_ppll0", "clk_ppll2", }; +static const char *const +clk_mux_320m_p[] = { "clk_ppll2", "clk_ppll0", }; +static const char *const +clk_mux_uarth_p[] = { "clkin_sys", "clk_div_uarth", }; +static const char *const +clk_mux_uartl_p[] = { "clkin_sys", "clk_div_uartl", }; +static const char *const +clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", }; +static const char *const +clk_mux_i2c_p[] = { "clkin_sys", "clk_div_i2c", }; +static const char *const +clk_mux_spi_p[] = { "clkin_sys", "clk_div_spi", }; +static const char *const +clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", }; +static const char *const +clk_mux_ao_asp_p[] = { "clk_ppll2", "clk_ppll3", }; +static const char *const +clk_mux_vdec_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", }; +static const char *const +clk_mux_venc_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", }; +static const char *const +clk_isp_snclk_mux0_p[] = { "clkin_sys", "clk_isp_snclk_div0", }; +static const char *const +clk_isp_snclk_mux1_p[] = { "clkin_sys", "clk_isp_snclk_div1", }; +static const char *const +clk_isp_snclk_mux2_p[] = { "clkin_sys", "clk_isp_snclk_div2", }; +static const char *const +clk_mux_rxdphy_cfg_p[] = { "clk_factor_rxdphy", "clkin_sys", }; +static const char *const +clk_mux_ics_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid", + "clk_ppll2", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_ppll3", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", }; + +static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = { + { HI3670_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, + ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, + 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_VCODECBUS, "clk_mux_vcodecbus", clk_mux_vcodecbus_p, + ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT, + 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p, + ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, + 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_sd_pll_p, + ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT, + 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p, + ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, + 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_sdio_pll_p, + ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT, + 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_a53hpm_p, + ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT, + 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_320M, "clk_mux_320m", clk_mux_320m_p, + ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT, + 0x100, 0, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p, + ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, + 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_UARTL, "clk_mux_uartl", clk_mux_uartl_p, + ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT, + 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p, + ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, + 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p, + ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, + 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p, + ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, + 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p, + ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT, + 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_AO_ASP, "clk_mux_ao_asp", clk_mux_ao_asp_p, + ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT, + 0x100, 6, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_vdec_p, + ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT, + 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p, + ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, + 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_ISP_SNCLK_MUX0, "clk_isp_snclk_mux0", clk_isp_snclk_mux0_p, + ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT, + 0x108, 3, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_ISP_SNCLK_MUX1, "clk_isp_snclk_mux1", clk_isp_snclk_mux1_p, + ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT, + 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_ISP_SNCLK_MUX2, "clk_isp_snclk_mux2", clk_isp_snclk_mux2_p, + ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT, + 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_RXDPHY_CFG, "clk_mux_rxdphy_cfg", clk_mux_rxdphy_cfg_p, + ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT, + 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_ICS, "clk_mux_ics", clk_mux_ics_p, + ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT, + 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, }, +}; + +static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = { + { HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus", + CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie", + CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt", + CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd", + CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio", + CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth", + CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl", + CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0", + CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m", + CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi", + CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi", + CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt", + CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans", + CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans", + CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp", + CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0", + CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1", + CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao", + CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec", + CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc", + CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac", + CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac", + CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac", + CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics", + CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, +}; + +/* clk_pmuctrl */ +static const struct hisi_gate_clock hi3670_pmu_gate_clks[] = { + { HI3670_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys", + CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, }, +}; + +/* clk_pctrl */ +static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = { + { HI3670_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en", "clk_gate_abb_192", + CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, }, + { HI3670_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192", + CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, }, +}; + +/* clk_sctrl */ +static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = { + { HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x190, 26, 0, }, + { HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x190, 15, 0, }, + { HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x1b0, 6, 0, }, + { HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x1B0, 9, 0, }, + { HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x1B0, 8, 0, }, + { HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi", + CLK_SET_RATE_PARENT, 0x1B0, 10, 0, }, + { HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi", + CLK_SET_RATE_PARENT, 0x1B0, 10, 0, }, + { HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys", + CLK_SET_RATE_PARENT, 0x1B0, 14, 0, }, + { HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys", + CLK_SET_RATE_PARENT, 0x1b0, 12, 0, }, + { HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 11, 0, }, + { HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 12, 0, }, + { HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 13, 0, }, + { HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 14, 0, }, + { HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 21, 0, }, + { HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 22, 0, }, + { HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 25, 0, }, + { HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0", + CLK_SET_RATE_PARENT, 0x160, 16, 0, }, + { HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1", + CLK_SET_RATE_PARENT, 0x160, 17, 0, }, + { HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus", + CLK_SET_RATE_PARENT, 0x160, 19, 0, }, + { HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys", + CLK_SET_RATE_PARENT, 0x160, 20, 0, }, + { HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri", + "clk_mux_asp_subsys_peri", + CLK_SET_RATE_PARENT, 0x170, 6, 0, }, + { HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll", + CLK_SET_RATE_PARENT, 0x170, 4, 0, }, + { HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys", + CLK_SET_RATE_PARENT, 0x160, 27, 0, }, + { HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll", + "clk_gate_dp_audio_pll_ao", + CLK_SET_RATE_PARENT, 0x1B0, 7, 0, }, +}; + +static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = { + { HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri", + "clk_ppll0", + CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, 0, }, +}; + +static const char *const +clk_mux_ufs_subsys_p[] = { "clkin_sys", "clk_ppll0", }; +static const char *const +clk_mux_clkout0_p[] = { "clkin_ref", "clk_div_clkout0_tcxo", + "clk_div_clkout0_pll", "clk_div_clkout0_pll", }; +static const char *const +clk_mux_clkout1_p[] = { "clkin_ref", "clk_div_clkout1_tcxo", + "clk_div_clkout1_pll", "clk_div_clkout1_pll", }; +static const char *const +clk_mux_asp_subsys_peri_p[] = { "clk_ppll0", "clk_fll_src", }; +static const char *const +clk_mux_asp_pll_p[] = { "clk_ppll0", "clk_fll_src", "clk_gate_ao_asp", + "clk_pciepll_rev", }; + +static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = { + { HI3670_CLK_MUX_UFS_SUBSYS, "clk_mux_ufs_subsys", clk_mux_ufs_subsys_p, + ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT, + 0x274, 8, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_CLKOUT0, "clk_mux_clkout0", clk_mux_clkout0_p, + ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT, + 0x254, 12, 2, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_CLKOUT1, "clk_mux_clkout1", clk_mux_clkout1_p, + ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT, + 0x254, 14, 2, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_ASP_SUBSYS_PERI, "clk_mux_asp_subsys_peri", + clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p), + CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_ASP_PLL, "clk_mux_asp_pll", clk_mux_asp_pll_p, + ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT, + 0x268, 9, 2, CLK_MUX_HIWORD_MASK, }, +}; + +static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = { + { HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys", + CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi", + CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys", + CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys", + CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri", + CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys", + CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, +}; + +/* clk_iomcu */ +static const struct hisi_fixed_factor_clock hi3670_iomcu_fixed_factor_clks[] = { + { HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, }, + { HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, }, + { HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, }, + { HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, }, + { HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, }, + { HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, }, +}; + +static const struct hisi_gate_clock hi3670_iomcu_gate_sep_clks[] = { + { HI3670_CLK_I2C0_GATE_IOMCU, "clk_i2c0_gate_iomcu", "clk_fll_src", + CLK_SET_RATE_PARENT, 0x10, 3, 0, }, + { HI3670_CLK_I2C1_GATE_IOMCU, "clk_i2c1_gate_iomcu", "clk_fll_src", + CLK_SET_RATE_PARENT, 0x10, 4, 0, }, + { HI3670_CLK_I2C2_GATE_IOMCU, "clk_i2c2_gate_iomcu", "clk_fll_src", + CLK_SET_RATE_PARENT, 0x10, 5, 0, }, + { HI3670_CLK_SPI0_GATE_IOMCU, "clk_spi0_gate_iomcu", "clk_fll_src", + CLK_SET_RATE_PARENT, 0x10, 10, 0, }, + { HI3670_CLK_SPI2_GATE_IOMCU, "clk_spi2_gate_iomcu", "clk_fll_src", + CLK_SET_RATE_PARENT, 0x10, 30, 0, }, + { HI3670_CLK_UART3_GATE_IOMCU, "clk_uart3_gate_iomcu", "clk_gate_iomcu_peri0", + CLK_SET_RATE_PARENT, 0x10, 11, 0, }, + { HI3670_CLK_GATE_PERI0_IOMCU, "clk_gate_iomcu_peri0", "clk_ppll0", + CLK_SET_RATE_PARENT, 0x90, 0, 0, }, +}; + +/* clk_media1 */ +static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = { + { HI3670_ACLK_GATE_NOC_DSS, "aclk_gate_noc_dss", "aclk_gate_disp_noc_subsys", + CLK_SET_RATE_PARENT, 0x10, 21, 0, }, + { HI3670_PCLK_GATE_NOC_DSS_CFG, "pclk_gate_noc_dss_cfg", "pclk_gate_disp_noc_subsys", + CLK_SET_RATE_PARENT, 0x10, 22, 0, }, + { HI3670_PCLK_GATE_MMBUF_CFG, "pclk_gate_mmbuf_cfg", "pclk_gate_disp_noc_subsys", + CLK_SET_RATE_PARENT, 0x20, 5, 0, }, + { HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus", + CLK_SET_RATE_PARENT, 0x10, 18, 0, }, + { HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq", + CLK_SET_RATE_PARENT, 0x10, 17, 0, }, + { HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys", + CLK_SET_RATE_PARENT, 0x00, 14, 0, }, + { HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys", + CLK_SET_RATE_PARENT, 0x00, 19, 0, }, + { HI3670_CLK_GATE_VIVOBUSFREQ, "clk_gate_vivobusfreq", "clk_div_vivobus", + CLK_SET_RATE_PARENT, 0x00, 18, 0, }, + { HI3670_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0", + CLK_SET_RATE_PARENT, 0x00, 15, 0, }, + { HI3670_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0", + CLK_SET_RATE_PARENT, 0x00, 16, 0, }, + { HI3670_CLK_GATE_LDI1FREQ, "clk_gate_ldi1freq", "clk_div_ldi1", + CLK_SET_RATE_PARENT, 0x00, 17, 0, }, + { HI3670_CLK_GATE_BRG, "clk_gate_brg", "clk_media_common_div", + CLK_SET_RATE_PARENT, 0x00, 29, 0, }, + { HI3670_ACLK_GATE_ASC, "aclk_gate_asc", "clk_gate_mmbuf", + CLK_SET_RATE_PARENT, 0x20, 3, 0, }, + { HI3670_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "clk_gate_mmbuf", + CLK_SET_RATE_PARENT, 0x20, 4, 0, }, + { HI3670_CLK_GATE_MMBUF, "clk_gate_mmbuf", "aclk_div_mmbuf", + CLK_SET_RATE_PARENT, 0x20, 0, 0, }, + { HI3670_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf", + CLK_SET_RATE_PARENT, 0x20, 1, 0, }, + { HI3670_CLK_GATE_ATDIV_VIVO, "clk_gate_atdiv_vivo", "clk_div_vivobus", + CLK_SET_RATE_PARENT, 0x010, 1, 0, }, +}; + +static const struct hisi_gate_clock hi3670_media1_gate_clks[] = { + { HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus", + CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0", + CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0", + CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1", + CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf", + CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, 0, }, + { HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf", + CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, 0, }, +}; + +static const char *const +clk_mux_vivobus_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media", + "clk_invalid", "clk_gate_ppll2_media", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_gate_ppll3_media", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", }; +static const char *const +clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media", + "clk_invalid", "clk_gate_ppll2_media", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_gate_ppll3_media", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", }; +static const char *const +clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media", + "clk_gate_ppll0_media", "clk_invalid", + "clk_gate_ppll2_media", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_gate_ppll3_media", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", }; +static const char *const +clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media", + "clk_gate_ppll0_media", "clk_invalid", + "clk_gate_ppll2_media", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_gate_ppll3_media", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", }; +static const char *const +clk_sw_mmbuf_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media", + "clk_invalid", "clk_gate_ppll2_media", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_gate_ppll3_media", + "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid", + "clk_invalid", "clk_invalid", "clk_invalid", }; + +static const struct hisi_mux_clock hi3670_media1_mux_clks[] = { + { HI3670_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_vivobus_p, + ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT, + 0x74, 6, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p, + ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, + 0x68, 6, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p, + ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, + 0x60, 6, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p, + ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT, + 0x64, 6, 4, CLK_MUX_HIWORD_MASK, }, + { HI3670_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p, + ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, + 0x88, 0, 4, CLK_MUX_HIWORD_MASK, }, +}; + +static const struct hisi_divider_clock hi3670_media1_divider_clks[] = { + { HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt", + CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0", + CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0", + CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1", + CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt", + CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt", + CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, +}; + +/* clk_media2 */ +static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = { + { HI3670_CLK_GATE_VDECFREQ, "clk_gate_vdecfreq", "clk_div_vdec", + CLK_SET_RATE_PARENT, 0x00, 8, 0, }, + { HI3670_CLK_GATE_VENCFREQ, "clk_gate_vencfreq", "clk_div_venc", + CLK_SET_RATE_PARENT, 0x00, 5, 0, }, + { HI3670_CLK_GATE_ICSFREQ, "clk_gate_icsfreq", "clk_div_ics", + CLK_SET_RATE_PARENT, 0x00, 2, 0, }, +}; + +static void hi3670_clk_crgctrl_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + + int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) + + ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) + + ARRAY_SIZE(hi3670_crgctrl_gate_clks) + + ARRAY_SIZE(hi3670_crgctrl_mux_clks) + + ARRAY_SIZE(hi3670_crg_fixed_factor_clks) + + ARRAY_SIZE(hi3670_crgctrl_divider_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks, + ARRAY_SIZE(hi3670_fixed_rate_clks), + clk_data); + hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks, + ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), + clk_data); + hisi_clk_register_gate(hi3670_crgctrl_gate_clks, + ARRAY_SIZE(hi3670_crgctrl_gate_clks), + clk_data); + hisi_clk_register_mux(hi3670_crgctrl_mux_clks, + ARRAY_SIZE(hi3670_crgctrl_mux_clks), + clk_data); + hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks, + ARRAY_SIZE(hi3670_crg_fixed_factor_clks), + clk_data); + hisi_clk_register_divider(hi3670_crgctrl_divider_clks, + ARRAY_SIZE(hi3670_crgctrl_divider_clks), + clk_data); +} + +static void hi3670_clk_pctrl_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + hisi_clk_register_gate(hi3670_pctrl_gate_clks, + ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data); +} + +static void hi3670_clk_pmuctrl_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi3670_pmu_gate_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate(hi3670_pmu_gate_clks, + ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data); +} + +static void hi3670_clk_sctrl_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) + + ARRAY_SIZE(hi3670_sctrl_gate_clks) + + ARRAY_SIZE(hi3670_sctrl_mux_clks) + + ARRAY_SIZE(hi3670_sctrl_divider_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks, + ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), + clk_data); + hisi_clk_register_gate(hi3670_sctrl_gate_clks, + ARRAY_SIZE(hi3670_sctrl_gate_clks), + clk_data); + hisi_clk_register_mux(hi3670_sctrl_mux_clks, + ARRAY_SIZE(hi3670_sctrl_mux_clks), + clk_data); + hisi_clk_register_divider(hi3670_sctrl_divider_clks, + ARRAY_SIZE(hi3670_sctrl_divider_clks), + clk_data); +} + +static void hi3670_clk_iomcu_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) + + ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks, + ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data); + + hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks, + ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), + clk_data); +} + +static void hi3670_clk_media1_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + + int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) + + ARRAY_SIZE(hi3670_media1_gate_clks) + + ARRAY_SIZE(hi3670_media1_mux_clks) + + ARRAY_SIZE(hi3670_media1_divider_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks, + ARRAY_SIZE(hi3670_media1_gate_sep_clks), + clk_data); + hisi_clk_register_gate(hi3670_media1_gate_clks, + ARRAY_SIZE(hi3670_media1_gate_clks), + clk_data); + hisi_clk_register_mux(hi3670_media1_mux_clks, + ARRAY_SIZE(hi3670_media1_mux_clks), + clk_data); + hisi_clk_register_divider(hi3670_media1_divider_clks, + ARRAY_SIZE(hi3670_media1_divider_clks), + clk_data); +} + +static void hi3670_clk_media2_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + + int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks, + ARRAY_SIZE(hi3670_media2_gate_sep_clks), + clk_data); +} + +static const struct of_device_id hi3670_clk_match_table[] = { + { .compatible = "hisilicon,hi3670-crgctrl", + .data = hi3670_clk_crgctrl_init }, + { .compatible = "hisilicon,hi3670-pctrl", + .data = hi3670_clk_pctrl_init }, + { .compatible = "hisilicon,hi3670-pmuctrl", + .data = hi3670_clk_pmuctrl_init }, + { .compatible = "hisilicon,hi3670-sctrl", + .data = hi3670_clk_sctrl_init }, + { .compatible = "hisilicon,hi3670-iomcu", + .data = hi3670_clk_iomcu_init }, + { .compatible = "hisilicon,hi3670-media1-crg", + .data = hi3670_clk_media1_init }, + { .compatible = "hisilicon,hi3670-media2-crg", + .data = hi3670_clk_media2_init }, + { } +}; + +static int hi3670_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + void (*init_func)(struct device_node *np); + + init_func = of_device_get_match_data(dev); + if (!init_func) + return -ENODEV; + + init_func(np); + + return 0; +} + +static struct platform_driver hi3670_clk_driver = { + .probe = hi3670_clk_probe, + .driver = { + .name = "hi3670-clk", + .of_match_table = hi3670_clk_match_table, + }, +}; + +static int __init hi3670_clk_init(void) +{ + return platform_driver_register(&hi3670_clk_driver); +} +core_initcall(hi3670_clk_init); diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index d2c99d8916b8..a5fddebbe530 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -152,7 +152,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) { const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; - unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); + unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); unsigned long alt_div = 0, alt_div_mask = DIV_MASK; unsigned long div0, div1 = 0, mux_reg; unsigned long flags; @@ -280,7 +280,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) { const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; - unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); + unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); unsigned long alt_div = 0, alt_div_mask = DIV_MASK; unsigned long div0, div1 = 0, mux_reg; unsigned long flags; @@ -432,7 +432,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, else cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; - cpuclk->alt_parent = __clk_lookup(alt_parent); + cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent)); if (!cpuclk->alt_parent) { pr_err("%s: could not lookup alternate parent %s\n", __func__, alt_parent); diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index d4b6b517fe1b..bd38c6aa3897 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -49,7 +49,7 @@ struct exynos_cpuclk_cfg_data { */ struct exynos_cpuclk { struct clk_hw hw; - struct clk *alt_parent; + struct clk_hw *alt_parent; void __iomem *ctrl_base; spinlock_t *lock; const struct exynos_cpuclk_cfg_data *cfg; diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index f659c5cbf1d5..8f8a0f9fc842 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -15,7 +15,6 @@ #include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/of_device.h> -#include <linux/syscore_ops.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 27c9d23657b3..0e9a41a4cac8 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -12,7 +12,6 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> -#include <linux/syscore_ops.h> #include <dt-bindings/clock/exynos3250.h> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 0421960eb963..59d4d46667ce 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -16,7 +16,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include "clk.h" #include "clk-cpu.h" @@ -123,10 +122,6 @@ #define CLKOUT_CMU_CPU 0x14a00 #define PWR_CTRL1 0x15020 #define E4X12_PWR_CTRL2 0x15024 -#define E4X12_DIV_ISP0 0x18300 -#define E4X12_DIV_ISP1 0x18304 -#define E4X12_GATE_ISP0 0x18800 -#define E4X12_GATE_ISP1 0x18804 /* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) @@ -158,14 +153,6 @@ static void __iomem *reg_base; static enum exynos4_soc exynos4_soc; /* - * Support for CMU save/restore across system suspends - */ -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *exynos4_save_common; -static struct samsung_clk_reg_dump *exynos4_save_soc; -static struct samsung_clk_reg_dump *exynos4_save_pll; - -/* * list of controller registers to be saved and restored during a * suspend/resume cycle. */ @@ -192,7 +179,7 @@ static const unsigned long exynos4x12_clk_save[] __initconst = { E4X12_PWR_CTRL2, }; -static const unsigned long exynos4_clk_pll_regs[] __initconst = { +static const unsigned long exynos4_clk_regs[] __initconst = { EPLL_LOCK, VPLL_LOCK, EPLL_CON0, @@ -201,9 +188,6 @@ static const unsigned long exynos4_clk_pll_regs[] __initconst = { VPLL_CON0, VPLL_CON1, VPLL_CON2, -}; - -static const unsigned long exynos4_clk_regs[] __initconst = { SRC_LEFTBUS, DIV_LEFTBUS, GATE_IP_LEFTBUS, @@ -276,6 +260,8 @@ static const unsigned long exynos4_clk_regs[] __initconst = { }; static const struct samsung_clk_reg_dump src_mask_suspend[] = { + { .offset = VPLL_CON0, .value = 0x80600302, }, + { .offset = EPLL_CON0, .value = 0x806F0302, }, { .offset = SRC_MASK_TOP, .value = 0x00000001, }, { .offset = SRC_MASK_CAM, .value = 0x11111111, }, { .offset = SRC_MASK_TV, .value = 0x00000111, }, @@ -291,123 +277,6 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, }; -#define PLL_ENABLED (1 << 31) -#define PLL_LOCKED (1 << 29) - -static void exynos4_clk_enable_pll(u32 reg) -{ - u32 pll_con = readl(reg_base + reg); - pll_con |= PLL_ENABLED; - writel(pll_con, reg_base + reg); - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static void exynos4_clk_wait_for_pll(u32 reg) -{ - u32 pll_con; - - pll_con = readl(reg_base + reg); - if (!(pll_con & PLL_ENABLED)) - return; - - while (!(pll_con & PLL_LOCKED)) { - cpu_relax(); - pll_con = readl(reg_base + reg); - } -} - -static int exynos4_clk_suspend(void) -{ - samsung_clk_save(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - samsung_clk_save(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_enable_pll(EPLL_CON0); - exynos4_clk_enable_pll(VPLL_CON0); - - if (exynos4_soc == EXYNOS4210) { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - samsung_clk_restore(reg_base, src_mask_suspend_e4210, - ARRAY_SIZE(src_mask_suspend_e4210)); - } else { - samsung_clk_save(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); - } - - samsung_clk_restore(reg_base, src_mask_suspend, - ARRAY_SIZE(src_mask_suspend)); - - return 0; -} - -static void exynos4_clk_resume(void) -{ - samsung_clk_restore(reg_base, exynos4_save_pll, - ARRAY_SIZE(exynos4_clk_pll_regs)); - - exynos4_clk_wait_for_pll(EPLL_CON0); - exynos4_clk_wait_for_pll(VPLL_CON0); - - samsung_clk_restore(reg_base, exynos4_save_common, - ARRAY_SIZE(exynos4_clk_regs)); - - if (exynos4_soc == EXYNOS4210) - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4210_clk_save)); - else - samsung_clk_restore(reg_base, exynos4_save_soc, - ARRAY_SIZE(exynos4x12_clk_save)); -} - -static struct syscore_ops exynos4_clk_syscore_ops = { - .suspend = exynos4_clk_suspend, - .resume = exynos4_clk_resume, -}; - -static void __init exynos4_clk_sleep_init(void) -{ - exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, - ARRAY_SIZE(exynos4_clk_regs)); - if (!exynos4_save_common) - goto err_warn; - - if (exynos4_soc == EXYNOS4210) - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4210_clk_save, - ARRAY_SIZE(exynos4210_clk_save)); - else - exynos4_save_soc = samsung_clk_alloc_reg_dump( - exynos4x12_clk_save, - ARRAY_SIZE(exynos4x12_clk_save)); - if (!exynos4_save_soc) - goto err_common; - - exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, - ARRAY_SIZE(exynos4_clk_pll_regs)); - if (!exynos4_save_pll) - goto err_soc; - - register_syscore_ops(&exynos4_clk_syscore_ops); - return; - -err_soc: - kfree(exynos4_save_soc); -err_common: - kfree(exynos4_save_common); -err_warn: - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); -} -#else -static void __init exynos4_clk_sleep_init(void) {} -#endif - /* list of all parent clock list */ PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; @@ -841,18 +710,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; -static struct samsung_div_clock exynos4x12_isp_div_clks[] = { - DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, - CLK_GET_RATE_NOCACHE, 0), - DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), - DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, - 4, 3, CLK_GET_RATE_NOCACHE, 0), - DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, - 8, 3, CLK_GET_RATE_NOCACHE, 0), -}; - /* list of gate clocks supported in all exynos4 soc's */ static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), @@ -1150,61 +1007,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0), }; -static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { - GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, - CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), -}; - /* * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit * resides in chipid register space, outside of the clock controller memory @@ -1504,8 +1306,6 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { - struct resource res; - samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1516,14 +1316,6 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); - of_address_to_resource(np, 0, &res); - if (resource_size(&res) > 0x18000) { - samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, - ARRAY_SIZE(exynos4x12_isp_div_clks)); - samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, - ARRAY_SIZE(exynos4x12_isp_gate_clks)); - } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), @@ -1532,7 +1324,17 @@ static void __init exynos4_clk_init(struct device_node *np, if (soc == EXYNOS4X12) exynos4x12_core_down_clock(); - exynos4_clk_sleep_init(); + + samsung_clk_extended_sleep_init(reg_base, + exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), + src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); + if (exynos4_soc == EXYNOS4210) + samsung_clk_extended_sleep_init(reg_base, + exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), + src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); + else + samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, + ARRAY_SIZE(exynos4x12_clk_save)); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 347fd80c351b..f14139bcb0c1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -14,7 +14,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include "clk.h" #include "clk-cpu.h" @@ -111,9 +110,6 @@ enum exynos5250_plls { static void __iomem *reg_base; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *exynos5250_save; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -172,41 +168,6 @@ static const unsigned long exynos5250_clk_regs[] __initconst = { GATE_IP_ISP1, }; -static int exynos5250_clk_suspend(void) -{ - samsung_clk_save(reg_base, exynos5250_save, - ARRAY_SIZE(exynos5250_clk_regs)); - - return 0; -} - -static void exynos5250_clk_resume(void) -{ - samsung_clk_restore(reg_base, exynos5250_save, - ARRAY_SIZE(exynos5250_clk_regs)); -} - -static struct syscore_ops exynos5250_clk_syscore_ops = { - .suspend = exynos5250_clk_suspend, - .resume = exynos5250_clk_resume, -}; - -static void __init exynos5250_clk_sleep_init(void) -{ - exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, - ARRAY_SIZE(exynos5250_clk_regs)); - if (!exynos5250_save) { - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; - } - - register_syscore_ops(&exynos5250_clk_syscore_ops); -} -#else -static void __init exynos5250_clk_sleep_init(void) {} -#endif - /* list of all parent clock list */ PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; @@ -882,7 +843,8 @@ static void __init exynos5250_clk_init(struct device_node *np) PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); __raw_writel(tmp, reg_base + PWR_CTRL2); - exynos5250_clk_sleep_init(); + samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, + ARRAY_SIZE(exynos5250_clk_regs)); exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 95e1bf69449b..34cce3c5898f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -15,7 +15,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include "clk.h" #include "clk-cpu.h" @@ -156,10 +155,6 @@ enum exynos5x_plls { static void __iomem *reg_base; static enum exynos5x_soc exynos5x_soc; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *exynos5x_save; -static struct samsung_clk_reg_dump *exynos5800_save; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -281,68 +276,9 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, + { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, }; -static int exynos5420_clk_suspend(void) -{ - samsung_clk_save(reg_base, exynos5x_save, - ARRAY_SIZE(exynos5x_clk_regs)); - - if (exynos5x_soc == EXYNOS5800) - samsung_clk_save(reg_base, exynos5800_save, - ARRAY_SIZE(exynos5800_clk_regs)); - - samsung_clk_restore(reg_base, exynos5420_set_clksrc, - ARRAY_SIZE(exynos5420_set_clksrc)); - - return 0; -} - -static void exynos5420_clk_resume(void) -{ - samsung_clk_restore(reg_base, exynos5x_save, - ARRAY_SIZE(exynos5x_clk_regs)); - - if (exynos5x_soc == EXYNOS5800) - samsung_clk_restore(reg_base, exynos5800_save, - ARRAY_SIZE(exynos5800_clk_regs)); -} - -static struct syscore_ops exynos5420_clk_syscore_ops = { - .suspend = exynos5420_clk_suspend, - .resume = exynos5420_clk_resume, -}; - -static void __init exynos5420_clk_sleep_init(void) -{ - exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, - ARRAY_SIZE(exynos5x_clk_regs)); - if (!exynos5x_save) { - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; - } - - if (exynos5x_soc == EXYNOS5800) { - exynos5800_save = - samsung_clk_alloc_reg_dump(exynos5800_clk_regs, - ARRAY_SIZE(exynos5800_clk_regs)); - if (!exynos5800_save) - goto err_soc; - } - - register_syscore_ops(&exynos5420_clk_syscore_ops); - return; -err_soc: - kfree(exynos5x_save); - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; -} -#else -static void __init exynos5420_clk_sleep_init(void) {} -#endif - /* list of all parent clocks */ PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll"}; @@ -633,6 +569,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { }; static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { + GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), }; @@ -1162,8 +1099,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), - GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), - /* GEN Block */ GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), @@ -1540,7 +1475,12 @@ static void __init exynos5x_clk_init(struct device_node *np, mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); - exynos5420_clk_sleep_init(); + samsung_clk_extended_sleep_init(reg_base, + exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), + exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); + if (soc == EXYNOS5800) + samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, + ARRAY_SIZE(exynos5800_clk_regs)); exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), exynos5x_subcmus); diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 162de44df099..751e2c4fb65b 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -177,6 +177,17 @@ static const unsigned long top_clk_regs[] __initconst = { ENABLE_CMU_TOP_DIV_STAT, }; +static const struct samsung_clk_reg_dump top_suspend_regs[] = { + /* force all aclk clocks enabled */ + { ENABLE_ACLK_TOP, 0x67ecffed }, + /* force all sclk_uart clocks enabled */ + { ENABLE_SCLK_TOP_PERIC, 0x38 }, + /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ + { ISP_PLL_CON0, 0x85cc0502 }, + /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ + { AUD_PLL_CON0, 0x84830202 }, +}; + /* list of all parent clock list */ PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; @@ -792,6 +803,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_clk_ids = TOP_NR_CLK, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), + .suspend_regs = top_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), }; static void __init exynos5433_cmu_top_init(struct device_node *np) @@ -822,6 +835,13 @@ static const unsigned long cpif_clk_regs[] __initconst = { ENABLE_SCLK_CPIF, }; +static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { + /* force all sclk clocks enabled */ + { ENABLE_SCLK_CPIF, 0x3ff }, + /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ + { MPHY_PLL_CON0, 0x81c70601 }, +}; + /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; @@ -862,6 +882,8 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = { .nr_clk_ids = CPIF_NR_CLK, .clk_regs = cpif_clk_regs, .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), + .suspend_regs = cpif_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), }; static void __init exynos5433_cmu_cpif_init(struct device_node *np) @@ -1547,6 +1569,13 @@ static const unsigned long peric_clk_regs[] __initconst = { ENABLE_IP_PERIC2, }; +static const struct samsung_clk_reg_dump peric_suspend_regs[] = { + /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ + { ENABLE_PCLK_PERIC0, 0xe00ff000 }, + /* sclk: uart2-0 */ + { ENABLE_SCLK_PERIC, 0x7 }, +}; + static const struct samsung_div_clock peric_div_clks[] __initconst = { /* DIV_PERIC */ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), @@ -1705,6 +1734,8 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .nr_clk_ids = PERIC_NR_CLK, .clk_regs = peric_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .suspend_regs = peric_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), }; static void __init exynos5433_cmu_peric_init(struct device_node *np) @@ -5630,7 +5661,7 @@ static const struct of_device_id exynos5433_cmu_of_match[] = { static const struct dev_pm_ops exynos5433_cmu_pm_ops = { SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume, NULL) - SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) }; diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c index a9c887475054..8cb868f06257 100644 --- a/drivers/clk/samsung/clk-s3c2410.c +++ b/drivers/clk/samsung/clk-s3c2410.c @@ -11,7 +11,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include <dt-bindings/clock/s3c2410.h> @@ -40,9 +39,6 @@ enum s3c2410_plls { static void __iomem *reg_base; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *s3c2410_save; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -57,42 +53,6 @@ static unsigned long s3c2410_clk_regs[] __initdata = { CAMDIVN, }; -static int s3c2410_clk_suspend(void) -{ - samsung_clk_save(reg_base, s3c2410_save, - ARRAY_SIZE(s3c2410_clk_regs)); - - return 0; -} - -static void s3c2410_clk_resume(void) -{ - samsung_clk_restore(reg_base, s3c2410_save, - ARRAY_SIZE(s3c2410_clk_regs)); -} - -static struct syscore_ops s3c2410_clk_syscore_ops = { - .suspend = s3c2410_clk_suspend, - .resume = s3c2410_clk_resume, -}; - -static void __init s3c2410_clk_sleep_init(void) -{ - s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs, - ARRAY_SIZE(s3c2410_clk_regs)); - if (!s3c2410_save) { - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; - } - - register_syscore_ops(&s3c2410_clk_syscore_ops); - return; -} -#else -static void __init s3c2410_clk_sleep_init(void) {} -#endif - PNAME(fclk_p) = { "mpll", "div_slow" }; static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = { @@ -461,7 +421,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, ARRAY_SIZE(s3c244x_common_aliases)); } - s3c2410_clk_sleep_init(); + samsung_clk_sleep_init(reg_base, s3c2410_clk_regs, + ARRAY_SIZE(s3c2410_clk_regs)); samsung_clk_of_add_provider(np, ctx); } diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c index 6bc94d3aff78..dd1159050a5a 100644 --- a/drivers/clk/samsung/clk-s3c2412.c +++ b/drivers/clk/samsung/clk-s3c2412.c @@ -11,7 +11,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include <linux/reboot.h> #include <dt-bindings/clock/s3c2412.h> @@ -29,9 +28,6 @@ static void __iomem *reg_base; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *s3c2412_save; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -45,42 +41,6 @@ static unsigned long s3c2412_clk_regs[] __initdata = { CLKSRC, }; -static int s3c2412_clk_suspend(void) -{ - samsung_clk_save(reg_base, s3c2412_save, - ARRAY_SIZE(s3c2412_clk_regs)); - - return 0; -} - -static void s3c2412_clk_resume(void) -{ - samsung_clk_restore(reg_base, s3c2412_save, - ARRAY_SIZE(s3c2412_clk_regs)); -} - -static struct syscore_ops s3c2412_clk_syscore_ops = { - .suspend = s3c2412_clk_suspend, - .resume = s3c2412_clk_resume, -}; - -static void __init s3c2412_clk_sleep_init(void) -{ - s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs, - ARRAY_SIZE(s3c2412_clk_regs)); - if (!s3c2412_save) { - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; - } - - register_syscore_ops(&s3c2412_clk_syscore_ops); - return; -} -#else -static void __init s3c2412_clk_sleep_init(void) {} -#endif - static struct clk_div_table divxti_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, @@ -278,7 +238,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, samsung_clk_register_alias(ctx, s3c2412_aliases, ARRAY_SIZE(s3c2412_aliases)); - s3c2412_clk_sleep_init(); + samsung_clk_sleep_init(reg_base, s3c2412_clk_regs, + ARRAY_SIZE(s3c2412_clk_regs)); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c index c46e6d5bc9bc..884067e4f1a1 100644 --- a/drivers/clk/samsung/clk-s3c2443.c +++ b/drivers/clk/samsung/clk-s3c2443.c @@ -11,7 +11,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include <linux/reboot.h> #include <dt-bindings/clock/s3c2443.h> @@ -43,9 +42,6 @@ enum supported_socs { static void __iomem *reg_base; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *s3c2443_save; - /* * list of controller registers to be saved and restored during a * suspend/resume cycle. @@ -65,42 +61,6 @@ static unsigned long s3c2443_clk_regs[] __initdata = { SCLKCON, }; -static int s3c2443_clk_suspend(void) -{ - samsung_clk_save(reg_base, s3c2443_save, - ARRAY_SIZE(s3c2443_clk_regs)); - - return 0; -} - -static void s3c2443_clk_resume(void) -{ - samsung_clk_restore(reg_base, s3c2443_save, - ARRAY_SIZE(s3c2443_clk_regs)); -} - -static struct syscore_ops s3c2443_clk_syscore_ops = { - .suspend = s3c2443_clk_suspend, - .resume = s3c2443_clk_resume, -}; - -static void __init s3c2443_clk_sleep_init(void) -{ - s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs, - ARRAY_SIZE(s3c2443_clk_regs)); - if (!s3c2443_save) { - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); - return; - } - - register_syscore_ops(&s3c2443_clk_syscore_ops); - return; -} -#else -static void __init s3c2443_clk_sleep_init(void) {} -#endif - PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; PNAME(esysclk_p) = { "epllref", "epll" }; PNAME(mpllref_p) = { "xti", "mdivclk" }; @@ -450,7 +410,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, break; } - s3c2443_clk_sleep_init(); + samsung_clk_sleep_init(reg_base, s3c2443_clk_regs, + ARRAY_SIZE(s3c2443_clk_regs)); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index 6db01cf5ab83..54916c7bdb06 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -12,7 +12,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include <dt-bindings/clock/samsung,s3c64xx-clock.h> @@ -59,10 +58,6 @@ static void __iomem *reg_base; static bool is_s3c6400; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *s3c64xx_save_common; -static struct samsung_clk_reg_dump *s3c64xx_save_soc; - /* * List of controller registers to be saved and restored during * a suspend/resume cycle. @@ -89,60 +84,6 @@ static unsigned long s3c6410_clk_regs[] __initdata = { MEM0_GATE, }; -static int s3c64xx_clk_suspend(void) -{ - samsung_clk_save(reg_base, s3c64xx_save_common, - ARRAY_SIZE(s3c64xx_clk_regs)); - - if (!is_s3c6400) - samsung_clk_save(reg_base, s3c64xx_save_soc, - ARRAY_SIZE(s3c6410_clk_regs)); - - return 0; -} - -static void s3c64xx_clk_resume(void) -{ - samsung_clk_restore(reg_base, s3c64xx_save_common, - ARRAY_SIZE(s3c64xx_clk_regs)); - - if (!is_s3c6400) - samsung_clk_restore(reg_base, s3c64xx_save_soc, - ARRAY_SIZE(s3c6410_clk_regs)); -} - -static struct syscore_ops s3c64xx_clk_syscore_ops = { - .suspend = s3c64xx_clk_suspend, - .resume = s3c64xx_clk_resume, -}; - -static void __init s3c64xx_clk_sleep_init(void) -{ - s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs, - ARRAY_SIZE(s3c64xx_clk_regs)); - if (!s3c64xx_save_common) - goto err_warn; - - if (!is_s3c6400) { - s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs, - ARRAY_SIZE(s3c6410_clk_regs)); - if (!s3c64xx_save_soc) - goto err_soc; - } - - register_syscore_ops(&s3c64xx_clk_syscore_ops); - return; - -err_soc: - kfree(s3c64xx_save_common); -err_warn: - pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", - __func__); -} -#else -static void __init s3c64xx_clk_sleep_init(void) {} -#endif - /* List of parent clocks common for all S3C64xx SoCs. */ PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" }; PNAME(uart_p) = { "mout_epll", "dout_mpll" }; @@ -508,7 +449,12 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, ARRAY_SIZE(s3c64xx_clock_aliases)); - s3c64xx_clk_sleep_init(); + + samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs, + ARRAY_SIZE(s3c64xx_clk_regs)); + if (!is_s3c6400) + samsung_clk_sleep_init(reg_base, s3c6410_clk_regs, + ARRAY_SIZE(s3c6410_clk_regs)); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c index fd2725710a6f..41d2337fe030 100644 --- a/drivers/clk/samsung/clk-s5pv210.c +++ b/drivers/clk/samsung/clk-s5pv210.c @@ -14,7 +14,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/syscore_ops.h> #include "clk.h" #include "clk-pll.h" @@ -83,9 +82,6 @@ enum { static void __iomem *reg_base; -#ifdef CONFIG_PM_SLEEP -static struct samsung_clk_reg_dump *s5pv210_clk_dump; - /* List of registers that need to be preserved across suspend/resume. */ static unsigned long s5pv210_clk_regs[] __initdata = { CLK_SRC0, @@ -132,40 +128,6 @@ static unsigned long s5pv210_clk_regs[] __initdata = { CLK_OUT, }; -static int s5pv210_clk_suspend(void) -{ - samsung_clk_save(reg_base, s5pv210_clk_dump, - ARRAY_SIZE(s5pv210_clk_regs)); - return 0; -} - -static void s5pv210_clk_resume(void) -{ - samsung_clk_restore(reg_base, s5pv210_clk_dump, - ARRAY_SIZE(s5pv210_clk_regs)); -} - -static struct syscore_ops s5pv210_clk_syscore_ops = { - .suspend = s5pv210_clk_suspend, - .resume = s5pv210_clk_resume, -}; - -static void s5pv210_clk_sleep_init(void) -{ - s5pv210_clk_dump = - samsung_clk_alloc_reg_dump(s5pv210_clk_regs, - ARRAY_SIZE(s5pv210_clk_regs)); - if (!s5pv210_clk_dump) { - pr_warn("%s: Failed to allocate sleep save data\n", __func__); - return; - } - - register_syscore_ops(&s5pv210_clk_syscore_ops); -} -#else -static inline void s5pv210_clk_sleep_init(void) { } -#endif - /* Mux parent lists. */ static const char *const fin_pll_p[] __initconst = { "xxti", @@ -822,7 +784,8 @@ static void __init __s5pv210_clk_init(struct device_node *np, samsung_clk_register_alias(ctx, s5pv210_aliases, ARRAY_SIZE(s5pv210_aliases)); - s5pv210_clk_sleep_init(); + samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, + ARRAY_SIZE(s5pv210_clk_regs)); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 8634884aa11c..1f6e47cd327d 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -290,9 +290,12 @@ static int samsung_clk_suspend(void) { struct samsung_clock_reg_cache *reg_cache; - list_for_each_entry(reg_cache, &clock_reg_cache_list, node) + list_for_each_entry(reg_cache, &clock_reg_cache_list, node) { samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, reg_cache->rd_num); + samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend, + reg_cache->rsuspend_num); + } return 0; } @@ -310,9 +313,11 @@ static struct syscore_ops samsung_clk_syscore_ops = { .resume = samsung_clk_resume, }; -void samsung_clk_sleep_init(void __iomem *reg_base, +void samsung_clk_extended_sleep_init(void __iomem *reg_base, const unsigned long *rdump, - unsigned long nr_rdump) + unsigned long nr_rdump, + const struct samsung_clk_reg_dump *rsuspend, + unsigned long nr_rsuspend) { struct samsung_clock_reg_cache *reg_cache; @@ -330,13 +335,10 @@ void samsung_clk_sleep_init(void __iomem *reg_base, reg_cache->reg_base = reg_base; reg_cache->rd_num = nr_rdump; + reg_cache->rsuspend = rsuspend; + reg_cache->rsuspend_num = nr_rsuspend; list_add_tail(®_cache->node, &clock_reg_cache_list); } - -#else -void samsung_clk_sleep_init(void __iomem *reg_base, - const unsigned long *rdump, - unsigned long nr_rdump) {} #endif /* @@ -380,8 +382,9 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks, cmu->nr_fixed_factor_clks); if (cmu->clk_regs) - samsung_clk_sleep_init(reg_base, cmu->clk_regs, - cmu->nr_clk_regs); + samsung_clk_extended_sleep_init(reg_base, + cmu->clk_regs, cmu->nr_clk_regs, + cmu->suspend_regs, cmu->nr_suspend_regs); samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 3880d2f9d582..c3f309d7100d 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -279,6 +279,8 @@ struct samsung_clock_reg_cache { void __iomem *reg_base; struct samsung_clk_reg_dump *rdump; unsigned int rd_num; + const struct samsung_clk_reg_dump *rsuspend; + unsigned int rsuspend_num; }; struct samsung_cmu_info { @@ -358,9 +360,21 @@ extern struct samsung_clk_provider __init *samsung_cmu_register_one( extern unsigned long _get_rate(const char *clk_name); -extern void samsung_clk_sleep_init(void __iomem *reg_base, +#ifdef CONFIG_PM_SLEEP +extern void samsung_clk_extended_sleep_init(void __iomem *reg_base, const unsigned long *rdump, - unsigned long nr_rdump); + unsigned long nr_rdump, + const struct samsung_clk_reg_dump *rsuspend, + unsigned long nr_rsuspend); +#else +static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump, + const struct samsung_clk_reg_dump *rsuspend, + unsigned long nr_rsuspend) {} +#endif +#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \ + samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0) extern void samsung_clk_save(void __iomem *base, struct samsung_clk_reg_dump *rd, |