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Diffstat (limited to 'arch/blackfin/mach-bf561/smp.c')
-rw-r--r--arch/blackfin/mach-bf561/smp.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index ab1c617b9cfc..11789beca75a 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -48,7 +48,7 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
return -EINVAL;
}
-void __cpuinit platform_secondary_init(unsigned int cpu)
+void platform_secondary_init(unsigned int cpu)
{
/* Clone setup for peripheral interrupt sources from CoreA. */
bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
@@ -69,12 +69,11 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
SSYNC();
/* We are done with local CPU inits, unblock the boot CPU. */
- set_cpu_online(cpu, true);
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
-int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
+int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
@@ -91,7 +90,9 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
SSYNC();
}
- timeout = jiffies + 1 * HZ;
+ timeout = jiffies + HZ;
+ /* release the lock and let coreb run */
+ spin_unlock(&boot_lock);
while (time_before(jiffies, timeout)) {
if (cpu_online(cpu))
break;
@@ -100,8 +101,6 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
}
if (cpu_online(cpu)) {
- /* release the lock and let coreb run */
- spin_unlock(&boot_lock);
return 0;
} else
panic("CPU%u: processor failed to boot\n", cpu);
@@ -155,7 +154,7 @@ void platform_clear_ipi(unsigned int cpu, int irq)
* Setup core B's local core timer.
* In SMP, core timer is used for clock event device.
*/
-void __cpuinit bfin_local_timer_setup(void)
+void bfin_local_timer_setup(void)
{
#if defined(CONFIG_TICKSOURCE_CORETMR)
struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);