diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt7981b.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 78 |
1 files changed, 73 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4feff3d1c5f4..64aeeb24efac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/clock/mediatek,mt7981-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/mt7986-resets.h> / { compatible = "mediatek,mt7981b"; @@ -62,12 +63,19 @@ #clock-cells = <1>; }; - clock-controller@1001b000 { + topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7981-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; @@ -78,20 +86,80 @@ compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; #pwm-cells = <2>; }; + i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + gpio-ranges = <&pio 0 0 56>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + + wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + }; }; timer { |