diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 473 |
1 files changed, 473 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi new file mode 100644 index 000000000000..3036af49fc85 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0 { + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>; + clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk"; +}; + +&asrc1 { + clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>, + <&asrc1_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>; + clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk"; +}; + +&audio_subsys { + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59810000 0x10000>; + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&esai1_lpcg IMX_LPCG_CLK_0>, + <&esai1_lpcg IMX_LPCG_CLK_4>, + <&esai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai6_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai6_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai7_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai7_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; + + acm: acm@59e00000 { + compatible = "fsl,imx8qm-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_mlb_clk>, + <&clk_hdmi_rx_mclk>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_esai1_rx_clk>, + <&clk_esai1_rx_hf_clk>, + <&clk_esai1_tx_clk>, + <&clk_esai1_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>, + <&clk_sai5_rx_bclk>, + <&clk_sai6_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "mlb_clk", + "hdmi_rx_mclk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "esai1_rx_clk", + "esai1_rx_hf_clk", + "esai1_tx_clk", + "esai1_tx_hf_clk", + "spdif0_rx", + "spdif1_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk", + "sai5_tx_bclk", + "sai6_rx_bclk"; + }; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x591f0000 0x150000>; + dma-channels = <20>; + dma-channel-mask = <0>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */ + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x599f0000 0xc0000>; + dma-channels = <11>; + dma-channel-mask = <0xc0>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; +}; + +&esai0 { + clocks = <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&esai0_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk"; +}; + +&mqs0_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk"; +}; + +&sai0 { + clocks = <&sai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai0_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk"; +}; + +&sai1 { + clocks = <&sai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai1_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai1_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk"; +}; + +&sai2 { + clocks = <&sai2_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai2_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai2_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk"; +}; + +&sai3 { + clocks = <&sai3_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai3_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&sai3_lpcg { + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; + clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk"; +}; + +&spdif0 { + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&spdif0_lpcg { + clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>; + clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw"; +}; |