diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso new file mode 100644 index 000000000000..bf3e04651ba0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Jens Lang <j.lang@phytec.de> + * + * Tauri-L 2 x RS232: + * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive) + */ + +#include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "phytec,imx8mm-phygate-tauri-l"; + +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrcl-0 = <&pinctrl_gpio3_hog>; + + uart4_rs485_en { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "uart4_rs485_en"; + }; +}; + +/* UART2 - RS232 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +/* UART4 - RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio3_hog: gpio3hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 + >; + }; +}; |