diff options
Diffstat (limited to 'arch/arm/plat-omap/include')
32 files changed, 1171 insertions, 579 deletions
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 35b36caf5f91..bb937f3fabed 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -25,17 +25,25 @@ struct omap_clk { }, \ } - +/* Platform flags for the clkdev-OMAP integration code */ #define CK_310 (1 << 0) -#define CK_7XX (1 << 1) +#define CK_7XX (1 << 1) /* 7xx, 850 */ #define CK_1510 (1 << 2) -#define CK_16XX (1 << 3) -#define CK_243X (1 << 4) -#define CK_242X (1 << 5) -#define CK_343X (1 << 6) -#define CK_3430ES1 (1 << 7) -#define CK_3430ES2 (1 << 8) -#define CK_443X (1 << 9) +#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ +#define CK_242X (1 << 4) +#define CK_243X (1 << 5) +#define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/ +#define CK_343X (1 << 7) /* OMAP34xx common clocks */ +#define CK_3430ES1 (1 << 8) /* 34xxES1 only */ +#define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */ +#define CK_3505 (1 << 10) +#define CK_3517 (1 << 11) +#define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */ +#define CK_443X (1 << 13) + +#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ + + #endif diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 94fe2a0ce40a..34f7fa9ad4c0 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -1,9 +1,9 @@ /* - * arch/arm/plat-omap/include/mach/clock.h + * OMAP clock: data structure definitions, function prototypes, shared macros * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc + * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,12 +22,13 @@ struct clockdomain; struct clkops { int (*enable)(struct clk *); void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, u8 *); - void (*find_companion)(struct clk *, void __iomem **, u8 *); + void (*find_idlest)(struct clk *, void __iomem **, + u8 *, u8 *); + void (*find_companion)(struct clk *, void __iomem **, + u8 *); }; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS struct clksel_rate { u32 val; @@ -40,6 +41,50 @@ struct clksel { const struct clksel_rate *rates; }; +/** + * struct dpll_data - DPLL registers and integration data + * @mult_div1_reg: register containing the DPLL M and N bitfields + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg + * @clk_bypass: struct clk pointer to the clock's bypass clock input + * @clk_ref: struct clk pointer to the clock's reference clock input + * @control_reg: register containing the DPLL mode bitfield + * @enable_mask: mask of the DPLL mode bitfield in @control_reg + * @rate_tolerance: maximum variance allowed from target rate (in Hz) + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() + * @max_multiplier: maximum valid non-bypass multiplier value (actual) + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() + * @min_divider: minimum valid non-bypass divider value (actual) + * @max_divider: maximum valid non-bypass divider value (actual) + * @modes: possible values of @enable_mask + * @autoidle_reg: register containing the DPLL autoidle mode bitfield + * @idlest_reg: register containing the DPLL idle status bitfield + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs + * @flags: DPLL type/features (see below) + * + * Possible values for @flags: + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) + * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs) + + * @freqsel_mask is only used on the OMAP34xx family and AM35xx. + * + * XXX Some DPLLs have multiple bypass inputs, so it's not technically + * correct to only have one @clk_bypass pointer. + * + * XXX @rate_tolerance should probably be deprecated - currently there + * don't seem to be any usecases for DPLL rounding that is not exact. + * + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, + * @last_rounded_n) should be separated from the runtime-fixed fields + * and placed into a differenct structure, so that the runtime-fixed data + * can be placed into read-only space. + */ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; @@ -51,13 +96,12 @@ struct dpll_data { unsigned int rate_tolerance; unsigned long last_rounded_rate; u16 last_rounded_m; + u16 max_multiplier; u8 last_rounded_n; u8 min_divider; u8 max_divider; - u32 max_tolerance; - u16 max_multiplier; -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) u8 modes; +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) void __iomem *autoidle_reg; void __iomem *idlest_reg; u32 autoidle_mask; @@ -66,6 +110,7 @@ struct dpll_data { u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; + u8 flags; # endif }; @@ -75,12 +120,10 @@ struct clk { struct list_head node; const struct clkops *ops; const char *name; - int id; struct clk *parent; struct list_head children; struct list_head sibling; /* node for children */ unsigned long rate; - __u32 flags; void __iomem *enable_reg; unsigned long (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); @@ -88,9 +131,9 @@ struct clk { void (*init)(struct clk *); __u8 enable_bit; __s8 usecount; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) u8 fixed_div; + u8 flags; +#ifdef CONFIG_ARCH_OMAP2PLUS void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; @@ -123,7 +166,7 @@ struct clk_functions { #endif }; -extern unsigned int mpurate; +extern int mpurate; extern int clk_init(struct clk_functions *custom_clocks); extern void clk_preinit(struct clk *clk); @@ -134,27 +177,23 @@ extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); +unsigned long omap_fixed_divisor_recalc(struct clk *clk); #ifdef CONFIG_CPU_FREQ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); #endif +extern struct clk *omap_clk_get_by_name(const char *name); extern const struct clkops clkops_null; +extern struct clk dummy_ck; + /* Clock flags */ -/* bit 0 is free */ -#define RATE_FIXED (1 << 1) /* Fixed clock rate */ -/* bits 2-4 are free */ -#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 7) -#define CLOCK_NO_IDLE_PARENT (1 << 8) -#define DELAYED_APP (1 << 9) /* Delay application of clock */ -#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ -#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -#define CLOCK_IN_OMAP4430 (1 << 13) -#define ALWAYS_ENABLED (1 << 14) -/* bits 13-31 are currently free */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ /* Clksel_rate flags */ #define DEFAULT_RATE (1 << 0) @@ -162,7 +201,8 @@ extern const struct clkops clkops_null; #define RATE_IN_243X (1 << 2) #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ -#define RATE_IN_4430 (1 << 5) +#define RATE_IN_36XX (1 << 5) +#define RATE_IN_4430 (1 << 6) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index eb734826e64e..ba0a6c07c0fe 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h @@ -4,7 +4,7 @@ * OMAP2/3 clockdomain framework functions * * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008 Nokia Corporation + * Copyright (C) 2008-2009 Nokia Corporation * * Written by Paul Walmsley * @@ -40,65 +40,95 @@ #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 -/* - * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps - * and sleepdeps added when a powerdomain should stay active in hwsup mode; - * and conversely, removed when the powerdomain should be allowed to go - * inactive in hwsup mode. +/** + * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode + * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only + * @omap_chip: OMAP chip types that this autodep is valid on + * + * A clockdomain that should have wkdeps and sleepdeps added when a + * clockdomain should stay active in hwsup mode; and conversely, + * removed when the clockdomain should be allowed to go inactive in + * hwsup mode. + * + * Autodeps are deprecated and should be removed after + * omap_hwmod-based fine-grained module idle control is added. */ -struct clkdm_pwrdm_autodep { - +struct clkdm_autodep { union { - /* Name of the powerdomain to add a wkdep/sleepdep on */ const char *name; - - /* Powerdomain pointer (looked up at clkdm_init() time) */ - struct powerdomain *ptr; - } pwrdm; - - /* OMAP chip types that this clockdomain dep is valid on */ + struct clockdomain *ptr; + } clkdm; const struct omap_chip_id omap_chip; +}; +/** + * struct clkdm_dep - encode dependencies between clockdomains + * @clkdm_name: clockdomain name + * @clkdm: pointer to the struct clockdomain of @clkdm_name + * @omap_chip: OMAP chip types that this dependency is valid on + * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake + * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle + * + * Statically defined. @clkdm is resolved from @clkdm_name at runtime and + * should not be pre-initialized. + * + * XXX Should also include hardware (fixed) dependencies. + */ +struct clkdm_dep { + const char *clkdm_name; + struct clockdomain *clkdm; + atomic_t wkdep_usecount; + atomic_t sleepdep_usecount; + const struct omap_chip_id omap_chip; }; +/** + * struct clockdomain - OMAP clockdomain + * @name: clockdomain name + * @pwrdm: powerdomain containing this clockdomain + * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain + * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg + * @flags: Clockdomain capability flags + * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit + * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up + * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact + * @omap_chip: OMAP chip types that this clockdomain is valid on + * @usecount: Usecount tracking + * @node: list_head to link all clockdomains together + */ struct clockdomain { - - /* Clockdomain name */ const char *name; - union { - /* Powerdomain enclosing this clockdomain */ const char *name; - - /* Powerdomain pointer assigned at clkdm_register() */ struct powerdomain *ptr; } pwrdm; - - /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ + void __iomem *clkstctrl_reg; const u16 clktrctrl_mask; - - /* Clockdomain capability flags */ const u8 flags; - - /* OMAP chip types that this clockdomain is valid on */ + const u8 dep_bit; + struct clkdm_dep *wkdep_srcs; + struct clkdm_dep *sleepdep_srcs; const struct omap_chip_id omap_chip; - - /* Usecount tracking */ atomic_t usecount; - struct list_head node; - }; -void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps); -int clkdm_register(struct clockdomain *clkdm); -int clkdm_unregister(struct clockdomain *clkdm); +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); struct clockdomain *clkdm_lookup(const char *name); int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), void *user); struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); + void omap2_clkdm_allow_idle(struct clockdomain *clkdm); void omap2_clkdm_deny_idle(struct clockdomain *clkdm); diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 32c22272425d..7556e271942e 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -37,21 +37,30 @@ extern void __iomem *gic_cpu_base_addr; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; -/* IO bases for various OMAP processors */ +/* + * IO bases for various OMAP processors + * Except the tap base, rest all the io bases + * listed are physical addresses. + */ struct omap_globals { u32 class; /* OMAP class to detect */ void __iomem *tap; /* Control module ID code */ - void __iomem *sdrc; /* SDRAM Controller */ - void __iomem *sms; /* SDRAM Memory Scheduler */ - void __iomem *ctrl; /* System Control Module */ - void __iomem *prm; /* Power and Reset Management */ - void __iomem *cm; /* Clock Management */ - void __iomem *cm2; + unsigned long sdrc; /* SDRAM Controller */ + unsigned long sms; /* SDRAM Memory Scheduler */ + unsigned long ctrl; /* System Control Module */ + unsigned long prm; /* Power and Reset Management */ + unsigned long cm; /* Clock Management */ + unsigned long cm2; + unsigned long uart1_phys; + unsigned long uart2_phys; + unsigned long uart3_phys; + unsigned long uart4_phys; }; void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +void omap2_set_globals_36xx(void); void omap2_set_globals_443x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ @@ -59,6 +68,7 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); +void omap2_set_globals_uart(struct omap_globals *); /** * omap_test_timeout - busy-loop, testing a condition diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a745d62fad0d..a56deee97676 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -160,6 +160,14 @@ #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) +/* AM35XX only CONTROL_GENERAL register offsets */ +#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) +#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) +#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) +#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) +#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) +#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) +#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) /* 34xx PADCONF register offsets */ #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ @@ -196,6 +204,9 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* 44xx control status register offset */ +#define OMAP44XX_CONTROL_STATUS 0x2c4 + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -257,6 +268,32 @@ #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C +/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ +#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 +#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 +#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 +#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 +#define AM35XX_USBOTG_FCLK_SHIFT 8 +#define AM35XX_CPGMAC_FCLK_SHIFT 9 +#define AM35XX_VPFE_FCLK_SHIFT 10 + +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) +#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) +#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) +#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) +#define AM35XX_USBOTGSS_INT_CLR BIT(4) +#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) +#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) +#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) + +/*AM35XX CONTROL_IP_SW_RESET bits*/ +#define AM35XX_USBOTGSS_SW_RST BIT(0) +#define AM35XX_CPGMACSS_SW_RST BIT(1) +#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) +#define AM35XX_HECC_SW_RST BIT(3) +#define AM35XX_VPFE_PCLK_SW_RST BIT(4) + /* * CONTROL OMAP STATUS register to identify OMAP3 features */ @@ -292,8 +329,7 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index a162f585b1e3..ed8786c41df2 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -31,6 +31,7 @@ #define __ASM_ARCH_OMAP_CPU_H #include <linux/bitops.h> +#include <plat/multi.h> /* * Omap device type i.e. EMU/HS/TST/GP/BAD @@ -44,7 +45,7 @@ int omap_type(void); struct omap_chip_id { - u8 oc; + u16 oc; u8 type; }; @@ -76,75 +77,6 @@ unsigned int omap_rev(void); #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) /* - * Test if multicore OMAP support is needed - */ -#undef MULTI_OMAP1 -#undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP15XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap1510 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP16XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap16xx -# endif -#endif -#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) -# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) -# error "OMAP1 and OMAP2 can't be selected at the same time" -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3430 -# endif -#endif - -/* * Macros to group OMAP into cpu classes. * These can be used in most places. * cpu_is_omap7xx(): True for OMAP730, OMAP850 @@ -154,6 +86,7 @@ unsigned int omap_rev(void); * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 * cpu_is_omap243x(): True for OMAP2430 * cpu_is_omap343x(): True for OMAP3430 + * cpu_is_omap443x(): True for OMAP4430 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) @@ -232,7 +165,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) #endif #if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP24XX) +# if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap24xx # undef cpu_is_omap242x # undef cpu_is_omap243x @@ -240,14 +173,14 @@ IS_OMAP_SUBCLASS(443x, 0x443) # define cpu_is_omap242x() is_omap242x() # define cpu_is_omap243x() is_omap243x() # endif -# if defined(CONFIG_ARCH_OMAP34XX) +# if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap34xx # undef cpu_is_omap343x # define cpu_is_omap34xx() is_omap34xx() # define cpu_is_omap343x() is_omap343x() # endif #else -# if defined(CONFIG_ARCH_OMAP24XX) +# if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap24xx # define cpu_is_omap24xx() 1 # endif @@ -259,7 +192,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) # undef cpu_is_omap243x # define cpu_is_omap243x() 1 # endif -# if defined(CONFIG_ARCH_OMAP34XX) +# if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap34xx # define cpu_is_omap34xx() 1 # endif @@ -286,6 +219,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) * cpu_is_omap2423(): True for OMAP2423 * cpu_is_omap2430(): True for OMAP2430 * cpu_is_omap3430(): True for OMAP3430 + * cpu_is_omap4430(): True for OMAP4430 * cpu_is_omap3505(): True for OMAP3505 * cpu_is_omap3517(): True for OMAP3517 */ @@ -334,6 +268,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define cpu_is_omap3505() 0 #define cpu_is_omap3517() 0 #define cpu_is_omap3430() 0 +#define cpu_is_omap4430() 0 #define cpu_is_omap3630() 0 /* @@ -371,7 +306,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap1710() is_omap1710() #endif -#if defined(CONFIG_ARCH_OMAP24XX) +#if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap2420 # undef cpu_is_omap2422 # undef cpu_is_omap2423 @@ -382,7 +317,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap2430() is_omap2430() #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap3430 # undef cpu_is_omap3503 # undef cpu_is_omap3515 @@ -471,9 +406,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_0 (1 << 5) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) +#define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) + /* * "GE" here represents "greater than or equal to" in terms of ES * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 @@ -501,6 +439,7 @@ extern u32 omap3_features; #define OMAP3_HAS_SGX BIT(2) #define OMAP3_HAS_NEON BIT(3) #define OMAP3_HAS_ISP BIT(4) +#define OMAP3_HAS_192MHZ_CLK BIT(5) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -513,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX) OMAP3_HAS_FEATURE(iva, IVA) OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) #endif diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h new file mode 100644 index 000000000000..1f767cb2f38a --- /dev/null +++ b/arch/arm/plat-omap/include/plat/dma-44xx.h @@ -0,0 +1,147 @@ +/* + * OMAP4 SDMA channel definitions + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H +#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H + +#define OMAP44XX_DMA_SYS_REQ0 2 +#define OMAP44XX_DMA_SYS_REQ1 3 +#define OMAP44XX_DMA_GPMC 4 +#define OMAP44XX_DMA_DSS_DISPC_REQ 6 +#define OMAP44XX_DMA_SYS_REQ2 7 +#define OMAP44XX_DMA_MCASP1_AXEVT 8 +#define OMAP44XX_DMA_ISS_REQ1 9 +#define OMAP44XX_DMA_ISS_REQ2 10 +#define OMAP44XX_DMA_MCASP1_AREVT 11 +#define OMAP44XX_DMA_ISS_REQ3 12 +#define OMAP44XX_DMA_ISS_REQ4 13 +#define OMAP44XX_DMA_DSS_RFBI_REQ 14 +#define OMAP44XX_DMA_SPI3_TX0 15 +#define OMAP44XX_DMA_SPI3_RX0 16 +#define OMAP44XX_DMA_MCBSP2_TX 17 +#define OMAP44XX_DMA_MCBSP2_RX 18 +#define OMAP44XX_DMA_MCBSP3_TX 19 +#define OMAP44XX_DMA_MCBSP3_RX 20 +#define OMAP44XX_DMA_C2C_SSCM_GPO0 21 +#define OMAP44XX_DMA_C2C_SSCM_GPO1 22 +#define OMAP44XX_DMA_SPI3_TX1 23 +#define OMAP44XX_DMA_SPI3_RX1 24 +#define OMAP44XX_DMA_I2C3_TX 25 +#define OMAP44XX_DMA_I2C3_RX 26 +#define OMAP44XX_DMA_I2C1_TX 27 +#define OMAP44XX_DMA_I2C1_RX 28 +#define OMAP44XX_DMA_I2C2_TX 29 +#define OMAP44XX_DMA_I2C2_RX 30 +#define OMAP44XX_DMA_MCBSP4_TX 31 +#define OMAP44XX_DMA_MCBSP4_RX 32 +#define OMAP44XX_DMA_MCBSP1_TX 33 +#define OMAP44XX_DMA_MCBSP1_RX 34 +#define OMAP44XX_DMA_SPI1_TX0 35 +#define OMAP44XX_DMA_SPI1_RX0 36 +#define OMAP44XX_DMA_SPI1_TX1 37 +#define OMAP44XX_DMA_SPI1_RX1 38 +#define OMAP44XX_DMA_SPI1_TX2 39 +#define OMAP44XX_DMA_SPI1_RX2 40 +#define OMAP44XX_DMA_SPI1_TX3 41 +#define OMAP44XX_DMA_SPI1_RX3 42 +#define OMAP44XX_DMA_SPI2_TX0 43 +#define OMAP44XX_DMA_SPI2_RX0 44 +#define OMAP44XX_DMA_SPI2_TX1 45 +#define OMAP44XX_DMA_SPI2_RX1 46 +#define OMAP44XX_DMA_MMC2_TX 47 +#define OMAP44XX_DMA_MMC2_RX 48 +#define OMAP44XX_DMA_UART1_TX 49 +#define OMAP44XX_DMA_UART1_RX 50 +#define OMAP44XX_DMA_UART2_TX 51 +#define OMAP44XX_DMA_UART2_RX 52 +#define OMAP44XX_DMA_UART3_TX 53 +#define OMAP44XX_DMA_UART3_RX 54 +#define OMAP44XX_DMA_UART4_TX 55 +#define OMAP44XX_DMA_UART4_RX 56 +#define OMAP44XX_DMA_MMC4_TX 57 +#define OMAP44XX_DMA_MMC4_RX 58 +#define OMAP44XX_DMA_MMC5_TX 59 +#define OMAP44XX_DMA_MMC5_RX 60 +#define OMAP44XX_DMA_MMC1_TX 61 +#define OMAP44XX_DMA_MMC1_RX 62 +#define OMAP44XX_DMA_SYS_REQ3 64 +#define OMAP44XX_DMA_MCPDM_UP 65 +#define OMAP44XX_DMA_MCPDM_DL 66 +#define OMAP44XX_DMA_DMIC_REQ 67 +#define OMAP44XX_DMA_C2C_SSCM_GPO2 68 +#define OMAP44XX_DMA_C2C_SSCM_GPO3 69 +#define OMAP44XX_DMA_SPI4_TX0 70 +#define OMAP44XX_DMA_SPI4_RX0 71 +#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 +#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 +#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 +#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 +#define OMAP44XX_DMA_DSS_HDMI_REQ 76 +#define OMAP44XX_DMA_MMC3_TX 77 +#define OMAP44XX_DMA_MMC3_RX 78 +#define OMAP44XX_DMA_USIM_TX 79 +#define OMAP44XX_DMA_USIM_RX 80 +#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 +#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 +#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 +#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 +#define OMAP44XX_DMA_SLIMBUS1_TX0 85 +#define OMAP44XX_DMA_SLIMBUS1_TX1 86 +#define OMAP44XX_DMA_SLIMBUS1_TX2 87 +#define OMAP44XX_DMA_SLIMBUS1_TX3 88 +#define OMAP44XX_DMA_SLIMBUS1_RX0 89 +#define OMAP44XX_DMA_SLIMBUS1_RX1 90 +#define OMAP44XX_DMA_SLIMBUS1_RX2 91 +#define OMAP44XX_DMA_SLIMBUS1_RX3 92 +#define OMAP44XX_DMA_SLIMBUS2_TX0 93 +#define OMAP44XX_DMA_SLIMBUS2_TX1 94 +#define OMAP44XX_DMA_SLIMBUS2_TX2 95 +#define OMAP44XX_DMA_SLIMBUS2_TX3 96 +#define OMAP44XX_DMA_SLIMBUS2_RX0 97 +#define OMAP44XX_DMA_SLIMBUS2_RX1 98 +#define OMAP44XX_DMA_SLIMBUS2_RX2 99 +#define OMAP44XX_DMA_SLIMBUS2_RX3 100 +#define OMAP44XX_DMA_ABE_REQ_0 101 +#define OMAP44XX_DMA_ABE_REQ_1 102 +#define OMAP44XX_DMA_ABE_REQ_2 103 +#define OMAP44XX_DMA_ABE_REQ_3 104 +#define OMAP44XX_DMA_ABE_REQ_4 105 +#define OMAP44XX_DMA_ABE_REQ_5 106 +#define OMAP44XX_DMA_ABE_REQ_6 107 +#define OMAP44XX_DMA_ABE_REQ_7 108 +#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ 109 +#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ 110 +#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ 111 +#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ 112 +#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ 113 +#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ 114 +#define OMAP44XX_DMA_DES_P_CTX_IN_REQ 115 +#define OMAP44XX_DMA_DES_P_DATA_IN_REQ 116 +#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ 117 +#define OMAP44XX_DMA_SHA2_CTXIN_P 118 +#define OMAP44XX_DMA_SHA2_DIN_P 119 +#define OMAP44XX_DMA_SHA2_CTXOUT_P 120 +#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ 121 +#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ 122 +#define OMAP44XX_DMA_I2C4_TX 124 +#define OMAP44XX_DMA_I2C4_RX 125 + +#endif diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 4ede9e17a0be..02232ca2c37f 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -21,6 +21,9 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H +/* Move omap4 specific defines to dma-44xx.h */ +#include "dma-44xx.h" + /* Hardware registers for omap1 */ #define OMAP1_DMA_BASE (0xfffed800) @@ -316,89 +319,6 @@ #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ -/* DMA request lines for 44xx */ -#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */ -#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */ -#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */ -#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */ -#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */ -#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */ -#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */ -#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ -#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ -#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */ -#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */ -#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */ -#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */ -#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ -#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ -#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */ -#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */ -#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */ -#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */ -#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */ -#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */ -#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */ -#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */ -#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */ -#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ -#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ -#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ -#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ -#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ -#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ -#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ -#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ -#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ -#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ -#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ -#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ -#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */ -#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */ -#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */ -#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */ -#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */ -#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */ -#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */ -#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */ -#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */ -#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */ -#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */ -#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */ -#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */ -#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */ -#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */ -#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */ -#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */ -#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ -#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */ -#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */ -#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */ -#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */ -#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */ -#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */ -#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */ -#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */ -#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */ -#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */ -#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */ -#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */ -#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */ -#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */ -#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */ -#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */ -#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */ -#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */ - /*----------------------------------------------------------------------------*/ #define OMAP1_DMA_TOUT_IRQ (1 << 0) diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h new file mode 100644 index 000000000000..3e6327016b40 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/flash.h @@ -0,0 +1,16 @@ +/* + * Flash support for OMAP1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_FLASH_H +#define __OMAP_FLASH_H + +#include <linux/mtd/map.h> + +extern void omap1_set_vpp(struct map_info *map, int enable); + +#endif diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index e081338e0b23..145838a81ef6 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -27,6 +27,8 @@ #define GPMC_CONFIG 0x50 #define GPMC_STATUS 0x54 +#define GPMC_CS0_BASE 0x60 +#define GPMC_CS_SIZE 0x30 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) @@ -110,6 +112,6 @@ extern void gpmc_prefetch_reset(void); extern int gpmc_prefetch_status(void); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern void __init gpmc_init(void); +extern void gpmc_init(void); #endif diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 585d9ca68b97..87f6bf2ea4fa 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h @@ -34,6 +34,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, } #endif -int omap_plat_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len); +void __init omap1_i2c_mux_pins(int bus_id); +void __init omap2_i2c_mux_pins(int bus_id); diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index a3e7b471bcba..128b549c2796 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -158,10 +158,6 @@ * VPOM3430 was not working for Int controller */ -#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */ -#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_WK_34XX_SIZE SZ_1M - #define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 --> 0xfb000000 */ #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) @@ -204,11 +200,6 @@ #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_44XX_SIZE SZ_4M - -#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */ -#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_WK_44XX_SIZE SZ_1M - #define L4_PER_44XX_PHYS L4_PER_44XX_BASE /* 0x48000000 --> 0xfa000000 */ #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) @@ -268,7 +259,38 @@ struct omap_sdrc_params; extern void omap1_map_common_io(void); extern void omap1_init_common_hw(void); -extern void omap2_map_common_io(void); +#ifdef CONFIG_ARCH_OMAP2420 +extern void omap242x_map_common_io(void); +#else +static inline void omap242x_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +extern void omap243x_map_common_io(void); +#else +static inline void omap243x_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP3 +extern void omap34xx_map_common_io(void); +#else +static inline void omap34xx_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP4 +extern void omap44xx_map_common_io(void); +#else +static inline void omap44xx_map_common_io(void) +{ +} +#endif + extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h new file mode 100644 index 000000000000..518322c80116 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/irqs-44xx.h @@ -0,0 +1,144 @@ +/* + * OMAP4 Interrupt lines definitions + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H +#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H + +/* OMAP44XX IRQs numbers definitions */ +#define OMAP44XX_IRQ_LOCALTIMER 29 +#define OMAP44XX_IRQ_LOCALWDT 30 + +#define OMAP44XX_IRQ_GIC_START 32 + +#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START) +#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START) + +#endif diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c0ab7c80f72e..b65088a869e9 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -28,6 +28,9 @@ #ifndef __ASM_ARCH_OMAP15XX_IRQS_H #define __ASM_ARCH_OMAP15XX_IRQS_H +/* All OMAP4 specific defines are moved to irqs-44xx.h */ +#include "irqs-44xx.h" + /* * IRQ numbers for interrupt handler 1 * @@ -344,95 +347,16 @@ #define INT_34XX_BENCH_MPU_EMUL 3 - -#define IRQ_GIC_START 32 -#define INT_44XX_LOCALTIMER_IRQ 29 -#define INT_44XX_LOCALWDT_IRQ 30 - -#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) -#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) -#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) -#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) -#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) -#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) -#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) -#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) -#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) -#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) -#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) -#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) -#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) -#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) -#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) -#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) -#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) -#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) -#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) -#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) -#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) -#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) -#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) -#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) -#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) -#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) -#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) -#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) -#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) -#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) -#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) -#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) -#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) -#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) -#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) -#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) -#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) -#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) -#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) -#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) - -#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) -#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) -#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) -#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) -#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) -#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) -#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) - -#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) -#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) -#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) -#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) -#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) -#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) -#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) -#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) -#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) -#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START) -#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) -#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) -#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) -#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) -#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) -#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) -#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) -#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) -#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) - +#define INT_35XX_HECC0_IRQ 24 +#define INT_35XX_HECC1_IRQ 28 +#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 +#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68 +#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 +#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 +#define INT_35XX_USBOTG_IRQ 71 +#define INT_35XX_CCDC_VD0_IRQ 88 +#define INT_35XX_CCDC_VD1_IRQ 92 +#define INT_35XX_CCDC_VD2_IRQ 93 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 4f22e5bb7ff7..39748354ce45 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -49,6 +49,9 @@ #define OMAP34XX_MCBSP1_BASE 0x48074000 #define OMAP34XX_MCBSP2_BASE 0x49022000 +#define OMAP34XX_MCBSP2_ST_BASE 0x49028000 +#define OMAP34XX_MCBSP3_BASE 0x49024000 +#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000 #define OMAP34XX_MCBSP3_BASE 0x49024000 #define OMAP34XX_MCBSP4_BASE 0x49026000 #define OMAP34XX_MCBSP5_BASE 0x48096000 @@ -103,8 +106,7 @@ #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX -#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#else #define OMAP_MCBSP_REG_DRR2 0x00 #define OMAP_MCBSP_REG_DRR1 0x04 @@ -147,6 +149,15 @@ #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 #define OMAP_MCBSP_REG_XCCR 0xAC #define OMAP_MCBSP_REG_RCCR 0xB0 +#define OMAP_MCBSP_REG_SSELCR 0xBC + +#define OMAP_ST_REG_REV 0x00 +#define OMAP_ST_REG_SYSCONFIG 0x10 +#define OMAP_ST_REG_IRQSTATUS 0x18 +#define OMAP_ST_REG_IRQENABLE 0x1C +#define OMAP_ST_REG_SGAINCR 0x24 +#define OMAP_ST_REG_SFIRCR 0x28 +#define OMAP_ST_REG_SSELCR 0x2C #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) @@ -265,6 +276,24 @@ #define ENAWAKEUP 0x0004 #define SOFTRST 0x0002 +/********************** McBSP SSELCR bit definitions ***********************/ +#define SIDETONEEN 0x0400 + +/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ +#define ST_AUTOIDLE 0x0001 + +/********************** McBSP Sidetone SGAINCR bit definitions *************/ +#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */ +#define ST_CH0GAIN(value) (value) /* Bits 0:15 */ + +/********************** McBSP Sidetone SFIRCR bit definitions **************/ +#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */ + +/********************** McBSP Sidetone SSELCR bit definitions **************/ +#define ST_COEFFWRDONE 0x0004 +#define ST_COEFFWREN 0x0002 +#define ST_SIDETONEEN 0x0001 + /********************** McBSP DMA operating modes **************************/ #define MCBSP_DMA_MODE_ELEMENT 0 #define MCBSP_DMA_MODE_THRESHOLD 1 @@ -374,11 +403,23 @@ struct omap_mcbsp_platform_data { u8 dma_rx_sync, dma_tx_sync; u16 rx_irq, tx_irq; struct omap_mcbsp_ops *ops; -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 + /* Sidetone block for McBSP 2 and 3 */ + unsigned long phys_base_st; u16 buffer_size; #endif }; +struct omap_mcbsp_st_data { + void __iomem *io_base_st; + bool running; + bool enabled; + s16 taps[128]; /* Sidetone filter coefficients */ + int nr_taps; /* Number of filter coefficients in use */ + s16 ch0gain; + s16 ch1gain; +}; + struct omap_mcbsp { struct device *dev; unsigned long phys_base; @@ -410,20 +451,22 @@ struct omap_mcbsp { struct omap_mcbsp_platform_data *pdata; struct clk *iclk; struct clk *fclk; -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 + struct omap_mcbsp_st_data *st_data; int dma_op_mode; u16 max_tx_thres; u16 max_rx_thres; #endif + void *reg_cache; }; extern struct omap_mcbsp **mcbsp_ptr; -extern int omap_mcbsp_count; +extern int omap_mcbsp_count, omap_mcbsp_cache_size; int omap_mcbsp_init(void); void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); @@ -459,4 +502,21 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf); int omap_mcbsp_pollwrite(unsigned int id, u16 buf); int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); +#ifdef CONFIG_ARCH_OMAP3 +/* Sidetone specific API */ +int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); +int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); +int omap_st_enable(unsigned int id); +int omap_st_disable(unsigned int id); +int omap_st_is_enabled(unsigned int id); +#else +static inline int omap_st_set_chgain(unsigned int id, int channel, + s16 chgain) { return 0; } +static inline int omap_st_get_chgain(unsigned int id, int channel, + s16 *chgain) { return 0; } +static inline int omap_st_enable(unsigned int id) { return 0; } +static inline int omap_st_disable(unsigned int id) { return 0; } +static inline int omap_st_is_enabled(unsigned int id) { return 0; } +#endif + #endif diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index 3325f7b49eaa..d5306bee44b2 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h @@ -38,8 +38,7 @@ */ #if defined(CONFIG_ARCH_OMAP1) #define PHYS_OFFSET UL(0x10000000) -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#else #define PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h index 3122bf68c7ce..4a970ec62dd1 100644 --- a/arch/arm/plat-omap/include/plat/menelaus.h +++ b/arch/arm/plat-omap/include/plat/menelaus.h @@ -40,7 +40,7 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); extern int menelaus_set_regulator_sleep(int enable, u32 val); -#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS) #define omap_has_menelaus() 1 #else #define omap_has_menelaus() 0 diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 29937137bf3e..a1bac07c89eb 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -55,12 +55,12 @@ struct omap_mmc_platform_data { unsigned int max_freq; /* switch the bus to a new slot */ - int (* switch_slot)(struct device *dev, int slot); + int (*switch_slot)(struct device *dev, int slot); /* initialize board-specific MMC functionality, can be NULL if * not supported */ - int (* init)(struct device *dev); - void (* cleanup)(struct device *dev); - void (* shutdown)(struct device *dev); + int (*init)(struct device *dev); + void (*cleanup)(struct device *dev); + void (*shutdown)(struct device *dev); /* To handle board related suspend/resume functionality for MMC */ int (*suspend)(struct device *dev, int slot); @@ -96,14 +96,28 @@ struct omap_mmc_platform_data { /* Try to sleep or power off when possible */ unsigned power_saving:1; + /* If using power_saving and the MMC power is not to go off */ + unsigned no_off:1; + + /* Regulator off remapped to sleep */ + unsigned vcc_aux_disable_is_sleep:1; + int switch_pin; /* gpio (card detect) */ int gpio_wp; /* gpio (write protect) */ - int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); - int (* set_power)(struct device *dev, int slot, int power_on, int vdd); - int (* get_ro)(struct device *dev, int slot); + int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); + int (*set_power)(struct device *dev, int slot, + int power_on, int vdd); + int (*get_ro)(struct device *dev, int slot); int (*set_sleep)(struct device *dev, int slot, int sleep, int vdd, int cardsleep); + void (*remux)(struct device *dev, int slot, int power_on); + /* Call back before enabling / disabling regulators */ + void (*before_set_reg)(struct device *dev, int slot, + int power_on, int vdd); + /* Call back after enabling / disabling regulators */ + void (*after_set_reg)(struct device *dev, int slot, + int power_on, int vdd); /* return MMC cover switch state, can be NULL if not supported. * @@ -111,14 +125,14 @@ struct omap_mmc_platform_data { * 0 - closed * 1 - open */ - int (* get_cover_state)(struct device *dev, int slot); + int (*get_cover_state)(struct device *dev, int slot); const char *name; u32 ocr_mask; /* Card detection IRQs */ int card_detect_irq; - int (* card_detect)(int irq); + int (*card_detect)(struct device *dev, int slot); unsigned int ban_openended:1; @@ -126,7 +140,8 @@ struct omap_mmc_platform_data { }; /* called from board-specific card detection service routine */ -extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, + int is_closed); #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h new file mode 100644 index 000000000000..f235d32cd942 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -0,0 +1,94 @@ +/* + * Support for compiling in multiple OMAP processors + * + * Copyright (C) 2010 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __PLAT_OMAP_MULTI_H +#define __PLAT_OMAP_MULTI_H + +/* + * Test if multicore OMAP support is needed + */ +#undef MULTI_OMAP1 +#undef MULTI_OMAP2 +#undef OMAP_NAME + +#ifdef CONFIG_ARCH_OMAP730 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap730 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP850 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap850 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP15XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap1510 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP16XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap16xx +# endif +#endif +#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) +# error "OMAP1 and OMAP2 can't be selected at the same time" +# endif +#endif +#ifdef CONFIG_ARCH_OMAP2420 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2420 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP2430 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2430 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP3430 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap3430 +# endif +#endif + +#endif /* __PLAT_OMAP_MULTI_H */ diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index 692c90e89ac3..c7472a28ce24 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h @@ -135,7 +135,7 @@ struct pin_config { const unsigned int mux_reg; unsigned char debug; -#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) const unsigned char mask_offset; const unsigned char mask; diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 631a7bed1eef..6ba88d2630d9 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -15,10 +15,18 @@ struct omap_nand_platform_data { int cs; int gpio_irq; struct mtd_partition *parts; + struct gpmc_timings *gpmc_t; int nr_parts; - int (*nand_setup)(void __iomem *); + int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + unsigned long phys_base; void __iomem *gpmc_cs_baseaddr; void __iomem *gpmc_baseaddr; + int devsize; }; + +/* size (4 KiB) for IO mapping */ +#define NAND_IO_SIZE SZ_4K + +extern int gpmc_nand_init(struct omap_nand_platform_data *d); diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h index 7560b4d583a3..e69e1d857b45 100644 --- a/arch/arm/plat-omap/include/plat/omap16xx.h +++ b/arch/arm/plat-omap/include/plat/omap16xx.h @@ -125,43 +125,43 @@ #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) /* UART3 Registers Mapping through MPU bus */ -#define UART3_RHR (OMAP_UART3_BASE + 0) -#define UART3_THR (OMAP_UART3_BASE + 0) -#define UART3_DLL (OMAP_UART3_BASE + 0) -#define UART3_IER (OMAP_UART3_BASE + 4) -#define UART3_DLH (OMAP_UART3_BASE + 4) -#define UART3_IIR (OMAP_UART3_BASE + 8) -#define UART3_FCR (OMAP_UART3_BASE + 8) -#define UART3_EFR (OMAP_UART3_BASE + 8) -#define UART3_LCR (OMAP_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_UART3_BASE + 0x50) +#define UART3_RHR (OMAP1_UART3_BASE + 0) +#define UART3_THR (OMAP1_UART3_BASE + 0) +#define UART3_DLL (OMAP1_UART3_BASE + 0) +#define UART3_IER (OMAP1_UART3_BASE + 4) +#define UART3_DLH (OMAP1_UART3_BASE + 4) +#define UART3_IIR (OMAP1_UART3_BASE + 8) +#define UART3_FCR (OMAP1_UART3_BASE + 8) +#define UART3_EFR (OMAP1_UART3_BASE + 8) +#define UART3_LCR (OMAP1_UART3_BASE + 0x0C) +#define UART3_MCR (OMAP1_UART3_BASE + 0x10) +#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) +#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) +#define UART3_LSR (OMAP1_UART3_BASE + 0x14) +#define UART3_TCR (OMAP1_UART3_BASE + 0x18) +#define UART3_MSR (OMAP1_UART3_BASE + 0x18) +#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) +#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) +#define UART3_SPR (OMAP1_UART3_BASE + 0x1C) +#define UART3_TLR (OMAP1_UART3_BASE + 0x1C) +#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) +#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) +#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) +#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) +#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) +#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) +#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) +#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) +#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) +#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) +#define UART3_BLR (OMAP1_UART3_BASE + 0x38) +#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) +#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) +#define UART3_SCR (OMAP1_UART3_BASE + 0x40) +#define UART3_SSR (OMAP1_UART3_BASE + 0x44) +#define UART3_EBLR (OMAP1_UART3_BASE + 0x48) +#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) +#define UART3_MVR (OMAP1_UART3_BASE + 0x50) /* * --------------------------------------------------------------------------- diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 696edfc145a6..7055672a8c68 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h @@ -23,8 +23,8 @@ * */ -#ifndef __ASM_ARCH_OMAP24XX_H -#define __ASM_ARCH_OMAP24XX_H +#ifndef __ASM_ARCH_OMAP2_H +#define __ASM_ARCH_OMAP2_H /* * Please place only base defines here and put the rest in device @@ -85,5 +85,5 @@ #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) -#endif /* __ASM_ARCH_OMAP24XX_H */ +#endif /* __ASM_ARCH_OMAP2_H */ diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 077f05979f86..2845fdc658b0 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -21,8 +21,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_OMAP34XX_H -#define __ASM_ARCH_OMAP34XX_H +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H /* * Please place only base defines here and put the rest in device @@ -82,5 +82,5 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) -#endif /* __ASM_ARCH_OMAP34XX_H */ +#endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index c7d628ecb467..2302474a3748 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -42,8 +42,11 @@ #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 #define OMAP44XX_L2CACHE_BASE 0x48242000 #define OMAP44XX_WKUPGEN_BASE 0x48281000 +#define OMAP44XX_MCPDM_BASE 0x40132000 +#define OMAP44XX_MCPDM_L3_BASE 0x49032000 #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) +#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) #endif /* __ASM_ARCH_OMAP44XX_H */ diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index dc1fac1d805c..3694b622c4ac 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -62,6 +62,7 @@ * */ struct omap_device { + u32 magic; struct platform_device pdev; struct omap_hwmod **hwmods; struct omap_device_pm_latency *pm_lats; @@ -81,6 +82,7 @@ int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ +bool omap_device_is_valid(struct omap_device *od); int omap_device_count_resources(struct omap_device *od); int omap_device_fill_resources(struct omap_device *od, struct resource *res); @@ -88,15 +90,16 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, struct omap_hwmod *oh, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt); + int pm_lats_cnt, int is_early_device); struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, struct omap_hwmod **oh, int oh_cnt, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt); + int pm_lats_cnt, int is_early_device); int omap_device_register(struct omap_device *od); +int omap_early_device_register(struct omap_device *od); /* OMAP PM interface */ int omap_device_align_pm_lat(struct platform_device *pdev, @@ -131,11 +134,15 @@ int omap_device_enable_clocks(struct omap_device *od); */ struct omap_device_pm_latency { u32 deactivate_lat; + u32 deactivate_lat_worst; int (*deactivate_func)(struct omap_device *od); u32 activate_lat; + u32 activate_lat_worst; int (*activate_func)(struct omap_device *od); + u32 flags; }; +#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) /* Get omap_device pointer from platform_device pointer */ #define to_omap_device(x) container_of((x), struct omap_device, pdev) diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 33933256a226..440b4164f2f6 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -4,7 +4,7 @@ * Copyright (C) 2009 Nokia Corporation * Paul Walmsley * - * Created in collaboration with (alphabetical order): Benoit Cousson, + * Created in collaboration with (alphabetical order): Benoît Cousson, * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff * @@ -33,25 +33,42 @@ #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H #include <linux/kernel.h> +#include <linux/list.h> #include <linux/ioport.h> - #include <plat/cpu.h> struct omap_device; -/* OCP SYSCONFIG bit shifts/masks */ -#define SYSC_MIDLEMODE_SHIFT 12 -#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) -#define SYSC_CLOCKACTIVITY_SHIFT 8 -#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) -#define SYSC_SIDLEMODE_SHIFT 3 -#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) -#define SYSC_ENAWAKEUP_SHIFT 2 -#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) -#define SYSC_SOFTRESET_SHIFT 1 -#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) -#define SYSC_AUTOIDLE_SHIFT 0 -#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; + +/* + * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant + * with the original PRCM protocol defined for OMAP2420 + */ +#define SYSC_TYPE1_MIDLEMODE_SHIFT 12 +#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) +#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 +#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) +#define SYSC_TYPE1_SIDLEMODE_SHIFT 3 +#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) +#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 +#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) +#define SYSC_TYPE1_SOFTRESET_SHIFT 1 +#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) +#define SYSC_TYPE1_AUTOIDLE_SHIFT 0 +#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) + +/* + * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant + * with the new PRCM protocol defined for new OMAP4 IPs. + */ +#define SYSC_TYPE2_SOFTRESET_SHIFT 0 +#define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) +#define SYSC_TYPE2_SIDLEMODE_SHIFT 2 +#define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) +#define SYSC_TYPE2_MIDLEMODE_SHIFT 4 +#define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 @@ -62,7 +79,6 @@ struct omap_device; #define HWMOD_IDLEMODE_NO (1 << 1) #define HWMOD_IDLEMODE_SMART (1 << 2) - /** * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod * @name: name of the IRQ channel (module local name) @@ -94,8 +110,7 @@ struct omap_hwmod_dma_info { /** * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() - * @clkdev_dev_id: opt clock: clkdev dev_id string - * @clkdev_con_id: opt clock: clkdev con_id string + * @clk: opt clock: OMAP clock name * @_clk: pointer to the struct clk (filled in at runtime) * * The module's interface clock and main functional clock should not @@ -103,8 +118,7 @@ struct omap_hwmod_dma_info { */ struct omap_hwmod_opt_clk { const char *role; - const char *clkdev_dev_id; - const char *clkdev_con_id; + const char *clk; struct clk *_clk; }; @@ -171,8 +185,7 @@ struct omap_hwmod_addr_space { * @master: struct omap_hwmod that initiates OCP transactions on this link * @slave: struct omap_hwmod that responds to OCP transactions on this link * @addr: address space associated with this link - * @clkdev_dev_id: interface clock: clkdev dev_id string - * @clkdev_con_id: interface clock: clkdev con_id string + * @clk: interface clock: OMAP clock name * @_clk: pointer to the interface struct clk (filled in at runtime) * @fw: interface firewall data * @addr_cnt: ARRAY_SIZE(@addr) @@ -191,8 +204,7 @@ struct omap_hwmod_ocp_if { struct omap_hwmod *master; struct omap_hwmod *slave; struct omap_hwmod_addr_space *addr; - const char *clkdev_dev_id; - const char *clkdev_con_id; + const char *clk; struct clk *_clk; union { struct omap_hwmod_omap2_firewall omap2; @@ -236,7 +248,25 @@ struct omap_hwmod_ocp_if { #define CLOCKACT_TEST_NONE 0x3 /** - * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data + * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. + * @midle_shift: Offset of the midle bit + * @clkact_shift: Offset of the clockactivity bit + * @sidle_shift: Offset of the sidle bit + * @enwkup_shift: Offset of the enawakeup bit + * @srst_shift: Offset of the softreset bit + * @autoidle_shift: Offset of the autoidle bit + */ +struct omap_hwmod_sysc_fields { + u8 midle_shift; + u8 clkact_shift; + u8 sidle_shift; + u8 enwkup_shift; + u8 srst_shift; + u8 autoidle_shift; +}; + +/** + * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) @@ -252,14 +282,22 @@ struct omap_hwmod_ocp_if { * been associated with the clocks marked in @clockact. This field is * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) * + * @sysc_fields: structure containing the offset positions of various bits in + * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or + * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on + * whether the device ip is compliant with the original PRCM protocol + * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. + * If the device follows a different scheme for the sysconfig register , + * then this field has to be populated with the correct offset structure. */ -struct omap_hwmod_sysconfig { +struct omap_hwmod_class_sysconfig { u16 rev_offs; u16 sysc_offs; u16 syss_offs; u8 idlemodes; u8 sysc_flags; u8 clockact; + struct omap_hwmod_sysc_fields *sysc_fields; }; /** @@ -352,19 +390,33 @@ struct omap_hwmod_omap4_prcm { #define _HWMOD_STATE_DISABLED 6 /** + * struct omap_hwmod_class - the type of an IP block + * @name: name of the hwmod_class + * @sysc: device SYSCONFIG/SYSSTATUS register data + * @rev: revision of the IP class + * + * Represent the class of a OMAP hardware "modules" (e.g. timer, + * smartreflex, gpio, uart...) + */ +struct omap_hwmod_class { + const char *name; + struct omap_hwmod_class_sysconfig *sysc; + u32 rev; +}; + +/** * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) * @name: name of the hwmod + * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) * @prcm: PRCM data pertaining to this hwmod - * @clkdev_dev_id: main clock: clkdev dev_id string - * @clkdev_con_id: main clock: clkdev con_id string + * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @masters: ptr to array of OCP ifs that this hwmod can initiate on * @slaves: ptr to array of OCP ifs that this hwmod can respond on - * @sysconfig: device SYSCONFIG/SYSSTATUS register data * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags * @_rt_va: cached register target start address (internal use) @@ -383,16 +435,17 @@ struct omap_hwmod_omap4_prcm { * @omap_chip: OMAP chips this hwmod is present on * @node: list node for hwmod list (internal use) * - * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main - * clock," which for our purposes is defined as "the functional clock needed - * for register accesses to complete." Modules may not have a main clock if - * the interface clock also serves as a main clock. + * @main_clk refers to this module's "main clock," which for our + * purposes is defined as "the functional clock needed for register + * accesses to complete." Modules may not have a main clock if the + * interface clock also serves as a main clock. * * Parameter names beginning with an underscore are managed internally by * the omap_hwmod code and should not be set during initialization. */ struct omap_hwmod { const char *name; + struct omap_hwmod_class *class; struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; struct omap_hwmod_dma_info *sdma_chs; @@ -400,13 +453,11 @@ struct omap_hwmod { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; } prcm; - const char *clkdev_dev_id; - const char *clkdev_con_id; + const char *main_clk; struct clk *_clk; struct omap_hwmod_opt_clk *opt_clks; struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ - struct omap_hwmod_sysconfig *sysconfig; void *dev_attr; u32 _sysc_cache; void __iomem *_rt_va; @@ -441,6 +492,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); +int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); + int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); @@ -465,4 +518,17 @@ int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); +int omap_hwmod_for_each_by_class(const char *classname, + int (*fn)(struct omap_hwmod *oh, + void *user), + void *user); + +/* + * Chip variant-specific hwmod init routines - XXX should be converted + * to use initcalls once the initial boot ordering is straightened out + */ +extern int omap2420_hwmod_init(void); +extern int omap2430_hwmod_init(void); +extern int omap3xxx_hwmod_init(void); + #endif diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 0b960051eaed..d82b2c00d4f1 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -1,8 +1,8 @@ /* * OMAP2/3 powerdomain control * - * Copyright (C) 2007-8 Texas Instruments, Inc. - * Copyright (C) 2007-8 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * @@ -37,6 +37,9 @@ #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_RET)) +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) @@ -48,16 +51,16 @@ */ /* - * Number of memory banks that are power-controllable. On OMAP3430, the - * maximum is 4. + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. */ -#define PWRDM_MAX_MEM_BANKS 4 +#define PWRDM_MAX_MEM_BANKS 5 /* * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP3 is the worst case + * CORE powerdomain on OMAP4 is the worst case */ -#define PWRDM_MAX_CLKDMS 4 +#define PWRDM_MAX_CLKDMS 9 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 @@ -65,65 +68,40 @@ struct clockdomain; struct powerdomain; -/* Encodes dependencies between powerdomains - statically defined */ -struct pwrdm_dep { - - /* Powerdomain name */ - const char *pwrdm_name; - - /* Powerdomain pointer - resolved by the powerdomain code */ - struct powerdomain *pwrdm; - - /* Flags to mark OMAP chip restrictions, etc. */ - const struct omap_chip_id omap_chip; - -}; - +/** + * struct powerdomain - OMAP powerdomain + * @name: Powerdomain name + * @omap_chip: represents the OMAP chip types containing this pwrdm + * @prcm_offs: the address offset from CM_BASE/PRM_BASE + * @pwrsts: Possible powerdomain power states + * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION + * @flags: Powerdomain flags + * @banks: Number of software-controllable memory banks in this powerdomain + * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION + * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON + * @pwrdm_clkdms: Clockdomains in this powerdomain + * @node: list_head linking all powerdomains + * @state: + * @state_counter: + * @timer: + * @state_timer: + */ struct powerdomain { - - /* Powerdomain name */ const char *name; - - /* the address offset from CM_BASE/PRM_BASE */ - const s16 prcm_offs; - - /* Used to represent the OMAP chip types containing this pwrdm */ const struct omap_chip_id omap_chip; - - /* Powerdomains that can be told to wake this powerdomain up */ - struct pwrdm_dep *wkdep_srcs; - - /* Powerdomains that can be told to keep this pwrdm from inactivity */ - struct pwrdm_dep *sleepdep_srcs; - - /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ - const u8 dep_bit; - - /* Possible powerdomain power states */ + const s16 prcm_offs; const u8 pwrsts; - - /* Possible logic power states when pwrdm in RETENTION */ const u8 pwrsts_logic_ret; - - /* Powerdomain flags */ const u8 flags; - - /* Number of software-controllable memory banks in this powerdomain */ const u8 banks; - - /* Possible memory bank pwrstates when pwrdm in RETENTION */ const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; - - /* Possible memory bank pwrstates when pwrdm is ON */ const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; - - /* Clockdomains in this powerdomain */ struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; - struct list_head node; - int state; unsigned state_counter[PWRDM_MAX_PWRSTS]; + unsigned ret_logic_off_counter; + unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; #ifdef CONFIG_PM_DEBUG s64 timer; @@ -134,8 +112,6 @@ struct powerdomain { void pwrdm_init(struct powerdomain **pwrdm_list); -int pwrdm_register(struct powerdomain *pwrdm); -int pwrdm_unregister(struct powerdomain *pwrdm); struct powerdomain *pwrdm_lookup(const char *name); int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), @@ -149,13 +125,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, int (*fn)(struct powerdomain *pwrdm, struct clockdomain *clkdm)); -int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); - int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); @@ -170,8 +139,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_logic_retst(struct powerdomain *pwrdm); int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index e63e94e18975..d6a0e27d5a7f 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -25,7 +25,8 @@ u32 omap_prcm_get_reset_sources(void); void omap_prcm_arch_reset(char mode); -int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, + const char *name); #define START_PADCONF_SAVE 0x2 #define PADCONF_SAVE_DONE 0x1 @@ -33,6 +34,14 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); void omap3_prcm_save_context(void); void omap3_prcm_restore_context(void); +u32 prm_read_mod_reg(s16 module, u16 idx); +void prm_write_mod_reg(u32 val, s16 module, u16 idx); +u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +u32 cm_read_mod_reg(s16 module, u16 idx); +void cm_write_mod_reg(u32 val, s16 module, u16 idx); +u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); + #endif diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index f5a4a92393ef..83dce4c4f7e6 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -15,37 +15,65 @@ #include <linux/init.h> -#if defined(CONFIG_ARCH_OMAP1) /* OMAP1 serial ports */ -#define OMAP_UART1_BASE 0xfffb0000 -#define OMAP_UART2_BASE 0xfffb0800 -#define OMAP_UART3_BASE 0xfffb9800 -#elif defined(CONFIG_ARCH_OMAP2) +#define OMAP1_UART1_BASE 0xfffb0000 +#define OMAP1_UART2_BASE 0xfffb0800 +#define OMAP1_UART3_BASE 0xfffb9800 + /* OMAP2 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x4806e000 -#elif defined(CONFIG_ARCH_OMAP3) +#define OMAP2_UART1_BASE 0x4806a000 +#define OMAP2_UART2_BASE 0x4806c000 +#define OMAP2_UART3_BASE 0x4806e000 + /* OMAP3 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x49020000 -#elif defined(CONFIG_ARCH_OMAP4) +#define OMAP3_UART1_BASE OMAP2_UART1_BASE +#define OMAP3_UART2_BASE OMAP2_UART2_BASE +#define OMAP3_UART3_BASE 0x49020000 +#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ + /* OMAP4 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x48020000 -#define OMAP_UART4_BASE 0x4806e000 -#endif +#define OMAP4_UART1_BASE OMAP2_UART1_BASE +#define OMAP4_UART2_BASE OMAP2_UART2_BASE +#define OMAP4_UART3_BASE 0x48020000 +#define OMAP4_UART4_BASE 0x4806e000 + +/* External port on Zoom2/3 */ +#define ZOOM_UART_BASE 0x10000000 +#define ZOOM_UART_VIRT 0xfb000000 + +#define OMAP_PORT_SHIFT 2 +#define OMAP7XX_PORT_SHIFT 0 +#define ZOOM_PORT_SHIFT 1 #define OMAP1510_BASE_BAUD (12000000/16) #define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16) +/* + * DEBUG_LL port encoding stored into the UART1 scratchpad register by + * decomp_setup in uncompress.h + */ +#define OMAP1UART1 11 +#define OMAP1UART2 12 +#define OMAP1UART3 13 +#define OMAP2UART1 21 +#define OMAP2UART2 22 +#define OMAP2UART3 23 +#define OMAP3UART1 OMAP2UART1 +#define OMAP3UART2 OMAP2UART2 +#define OMAP3UART3 33 +#define OMAP3UART4 34 /* Only on 36xx */ +#define OMAP4UART1 OMAP2UART1 +#define OMAP4UART2 OMAP2UART2 +#define OMAP4UART3 43 +#define OMAP4UART4 44 +#define ZOOM_UART 95 /* Only on zoom2/3 */ + +/* This is only used by 8250.c for omap1510 */ #define is_omap_port(pt) ({int __ret = 0; \ - if ((pt)->port.mapbase == OMAP_UART1_BASE || \ - (pt)->port.mapbase == OMAP_UART2_BASE || \ - (pt)->port.mapbase == OMAP_UART3_BASE) \ + if ((pt)->port.mapbase == OMAP1_UART1_BASE || \ + (pt)->port.mapbase == OMAP1_UART2_BASE || \ + (pt)->port.mapbase == OMAP1_UART3_BASE) \ __ret = 1; \ __ret; \ }) diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 13c305d62127..81d9ec540fcf 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -19,62 +19,38 @@ #include <linux/types.h> #include <linux/serial_reg.h> + +#include <asm/mach-types.h> + #include <plat/serial.h> -unsigned int system_rev; +static volatile u8 *uart1_base; +static int uart1_shift; -#define UART_OMAP_MDR1 0x08 /* mode definition register */ -#define OMAP_ID_730 0x355F -#define OMAP_ID_850 0x362C -#define ID_MASK 0x7fff -#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) -#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK +static volatile u8 *uart_base; +static int uart_shift; -static void putc(int c) +/* + * Store the DEBUG_LL uart number into UART1 scratchpad register. + * See also debug-macro.S, and serial.c for related code. + * + * Please note that we currently assume that: + * - UART1 clocks are enabled for register access + * - UART1 scratchpad register can be used + */ +static void set_uart1_scratchpad(unsigned char port) { - volatile u8 * uart = 0; - int shift = 2; - -#ifdef CONFIG_MACH_OMAP_PALMTE - return; -#endif - -#ifdef CONFIG_ARCH_OMAP -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - uart = (volatile u8 *)(OMAP_UART3_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) - uart = (volatile u8 *)(OMAP_UART2_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_UART1) - uart = (volatile u8 *)(OMAP_UART1_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_NONE) - return; -#else - return; -#endif - -#ifdef CONFIG_ARCH_OMAP1 - /* Determine which serial port to use */ - do { - /* MMU is not on, so cpu_is_omapXXXX() won't work here */ - unsigned int omap_id = omap_get_id(); - - if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) - shift = 0; + uart1_base[UART_SCR << uart1_shift] = port; +} - if (check_port(uart, shift)) - break; - /* Silent boot if no serial ports are enabled. */ +static void putc(int c) +{ + if (!uart_base) return; - } while (0); -#endif /* CONFIG_ARCH_OMAP1 */ -#endif - /* - * Now, xmit each character - */ - while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) barrier(); - uart[UART_TX << shift] = c; + uart_base[UART_TX << uart_shift] = c; } static inline void flush(void) @@ -82,7 +58,116 @@ static inline void flush(void) } /* + * Macros to configure UART1 and debug UART + */ +#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ + dbg_uart, dbg_shft, dbg_id) \ + if (machine_is_##mach()) { \ + uart1_base = (volatile u8 *)(uart1_phys); \ + uart1_shift = (uart1_shft); \ + uart_base = (volatile u8 *)(dbg_uart); \ + uart_shift = (dbg_shft); \ + port = (dbg_id); \ + set_uart1_scratchpad(port); \ + break; \ + } + +#define DEBUG_LL_OMAP7XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ + OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) + +#define DEBUG_LL_OMAP1(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) + +#define DEBUG_LL_OMAP2(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) + +#define DEBUG_LL_OMAP3(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) + +#define DEBUG_LL_OMAP4(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) + +/* Zoom2/3 shift is different for UART1 and external port */ +#define DEBUG_LL_ZOOM(mach) \ + _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ + ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + int port = 0; + + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* omap7xx/8xx based boards using UART1 with shift 0 */ + DEBUG_LL_OMAP7XX(1, herald); + DEBUG_LL_OMAP7XX(1, omap_perseus2); + + /* omap15xx/16xx based boards using UART1 */ + DEBUG_LL_OMAP1(1, ams_delta); + DEBUG_LL_OMAP1(1, nokia770); + DEBUG_LL_OMAP1(1, omap_h2); + DEBUG_LL_OMAP1(1, omap_h3); + DEBUG_LL_OMAP1(1, omap_innovator); + DEBUG_LL_OMAP1(1, omap_osk); + DEBUG_LL_OMAP1(1, omap_palmte); + DEBUG_LL_OMAP1(1, omap_palmz71); + + /* omap15xx/16xx based boards using UART2 */ + DEBUG_LL_OMAP1(2, omap_palmtt); + + /* omap15xx/16xx based boards using UART3 */ + DEBUG_LL_OMAP1(3, sx1); + + /* omap2 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap2evm); + DEBUG_LL_OMAP2(1, omap_2430sdp); + DEBUG_LL_OMAP2(1, omap_apollon); + DEBUG_LL_OMAP2(1, omap_h4); + + /* omap2 based boards using UART3 */ + DEBUG_LL_OMAP2(3, nokia_n800); + DEBUG_LL_OMAP2(3, nokia_n810); + DEBUG_LL_OMAP2(3, nokia_n810_wimax); + + /* omap3 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap3evm); + DEBUG_LL_OMAP3(1, omap_3430sdp); + DEBUG_LL_OMAP3(1, omap_3630sdp); + + /* omap3 based boards using UART3 */ + DEBUG_LL_OMAP3(3, cm_t35); + DEBUG_LL_OMAP3(3, igep0020); + DEBUG_LL_OMAP3(3, nokia_rx51); + DEBUG_LL_OMAP3(3, omap3517evm); + DEBUG_LL_OMAP3(3, omap3_beagle); + DEBUG_LL_OMAP3(3, omap3_pandora); + DEBUG_LL_OMAP3(3, omap_ldp); + DEBUG_LL_OMAP3(3, overo); + DEBUG_LL_OMAP3(3, touchbook); + + /* omap4 based boards using UART3 */ + DEBUG_LL_OMAP4(3, omap_4430sdp); + + /* zoom2/3 external uart */ + DEBUG_LL_ZOOM(omap_zoom2); + DEBUG_LL_ZOOM(omap_zoom3); + + } while (0); +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) + +/* * nothing to do */ -#define arch_decomp_setup() #define arch_decomp_wdog() diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 33a500eb2f93..288e29e1c06f 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -3,6 +3,7 @@ #ifndef __ASM_ARCH_OMAP_USB_H #define __ASM_ARCH_OMAP_USB_H +#include <linux/usb/musb.h> #include <plat/board.h> #define OMAP3_HS_USB_PORTS 3 @@ -42,7 +43,15 @@ struct ehci_hcd_omap_platform_data { #define UDC_BASE OMAP2_UDC_BASE #define OMAP_OHCI_BASE OMAP2_OHCI_BASE -extern void usb_musb_init(void); +struct omap_musb_board_data { + u8 interface_type; + u8 mode; + u8 power; +}; + +enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; + +extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata); |