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Diffstat (limited to 'arch/arm/boot/dts/stih410-clock.dtsi')
-rw-r--r--arch/arm/boot/dts/stih410-clock.dtsi138
1 files changed, 12 insertions, 126 deletions
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,25 +72,18 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen", "st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
- "clk-ic-lmi1";
- clock-critical = <CLK_IC_LMI0>;
};
};
@@ -102,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -116,26 +101,21 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen", "st,flexgen-stih410-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -145,52 +125,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
- "clk-fdma",
- "clk-nand",
- "clk-hva",
- "clk-proc-stfe",
- "clk-proc-tp",
- "clk-rx-icn-dmu",
- "clk-rx-icn-hva",
- "clk-icn-cpu",
- "clk-tx-icn-dmu",
- "clk-mmc-0",
- "clk-mmc-1",
- "clk-jpegdec",
- "clk-ext2fa9",
- "clk-ic-bdisp-0",
- "clk-ic-bdisp-1",
- "clk-pp-dmu",
- "clk-vid-dmu",
- "clk-dss-lpc",
- "clk-st231-aud-0",
- "clk-st231-gp-1",
- "clk-st231-dmu",
- "clk-icn-lmi",
- "clk-tx-icn-disp-1",
- "clk-icn-sbc",
- "clk-stfe-frc2",
- "clk-eth-phy",
- "clk-eth-ref-phyclk",
- "clk-flash-promip",
- "clk-main-disp",
- "clk-aux-disp",
- "clk-compo-dvp",
- "clk-tx-icn-hades",
- "clk-rx-icn-hades",
- "clk-icn-reg-16",
- "clk-pp-hades",
- "clk-clust-hades",
- "clk-hwpe-hades",
- "clk-fc-hades";
- clock-critical = <CLK_PROC_STFE>,
- <CLK_ICN_CPU>,
- <CLK_TX_ICN_DMU>,
- <CLK_EXT2F_A9>,
- <CLK_ICN_LMI>,
- <CLK_ICN_SBC>;
-
/*
* ARM Peripheral clock for timers
*/
@@ -210,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -227,34 +156,22 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen-audio", "st,flexgen";
+ compatible = "st,flexgen", "st,flexgen-stih410-d0";
clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>,
<&clk_s_d0_quadfs 2>,
<&clk_s_d0_quadfs 3>,
<&clk_sysin>;
-
- clock-output-names = "clk-pcm-0",
- "clk-pcm-1",
- "clk-pcm-2",
- "clk-spdiff",
- "clk-pcmr10-master",
- "clk-usb2-phy";
};
};
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -263,7 +180,7 @@
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen-video", "st,flexgen";
+ compatible = "st,flexgen", "st,flexgen-stih407-d2";
clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
@@ -272,37 +189,15 @@
<&clk_sysin>,
<&clk_sysin>,
<&clk_tmdsout_hdmi>;
-
- clock-output-names = "clk-pix-main-disp",
- "clk-pix-pip",
- "clk-pix-gdp1",
- "clk-pix-gdp2",
- "clk-pix-gdp3",
- "clk-pix-gdp4",
- "clk-pix-aux-disp",
- "clk-denc",
- "clk-pix-hddac",
- "clk-hddac",
- "clk-sddac",
- "clk-pix-dvo",
- "clk-dvo",
- "clk-pix-hdmi",
- "clk-tmds-hdmi",
- "clk-ref-hdmiphy";
- };
+ };
};
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
@@ -311,22 +206,13 @@
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen", "st,flexgen-stih407-d3";
clocks = <&clk_s_d3_quadfs 0>,
<&clk_s_d3_quadfs 1>,
<&clk_s_d3_quadfs 2>,
<&clk_s_d3_quadfs 3>,
<&clk_sysin>;
-
- clock-output-names = "clk-stfe-frc1",
- "clk-tsout-0",
- "clk-tsout-1",
- "clk-mchi",
- "clk-vsens-compo",
- "clk-frc1-remote",
- "clk-lpc-0",
- "clk-lpc-1";
};
};
};
generated by cgit v1.2.3-58-ga151 (git 2.39.0) at 2024-12-23 13:11:20 +0000