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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-08-06 12:45:42 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-08-06 12:45:42 +0200 |
| commit | 9e90c7985229430428dc9ba0ec7fe422901b456d (patch) | |
| tree | cae2072feba8cc433a32d96568bbcf36070bd6e5 /virt/kvm/arm/mmu.c | |
| parent | 4f7799d96e6621ce584df60739e1480a6fd89f0a (diff) | |
| parent | a8db74564b0c634667e1722264bde303d296f566 (diff) | |
Merge tag 'irqchip-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- GICv3 ITS LPI allocation revamp
- GICv3 support for hypervisor-enforced LPI range
- GICv3 ITS conversion to raw spinlock
Diffstat (limited to 'virt/kvm/arm/mmu.c')
| -rw-r--r-- | virt/kvm/arm/mmu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 8d90de213ce9..1d90d79706bd 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -297,6 +297,8 @@ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) phys_addr_t next; assert_spin_locked(&kvm->mmu_lock); + WARN_ON(size & ~PAGE_MASK); + pgd = kvm->arch.pgd + stage2_pgd_index(addr); do { /* |