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authorDave Jiang <dave.jiang@intel.com>2024-04-03 08:47:16 -0700
committerDave Jiang <dave.jiang@intel.com>2024-04-08 08:25:21 -0700
commit7bcf809b1e7889ab7e75fe1fcf8f1a98332f36d2 (patch)
tree24fa46c5562555f14233d3b892e70b671bebf4a5 /tools
parent001c5d19341a39cb683ab0a18ce4b662a09d96a0 (diff)
cxl: Add checks to access_coordinate calculation to fail missing data
Jonathan noted that when the coordinates for host bridge and switches can be 0s if no actual data are retrieved and the calculation continues. The resulting number would be inaccurate. Add checks to ensure that the calculation would complete only if the numbers are valid. While not seen in the wild, issue may show up with a BIOS that reported CXL root ports via Generic Ports (via a PCI handle in the SRAT entry). Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20240403154844.3403859-6-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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