diff options
author | Axel Lin <axel.lin@ingics.com> | 2015-08-12 11:09:39 +0800 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-08-14 17:30:52 +0100 |
commit | 7f325bfc933d140337e55507821d6bb021321059 (patch) | |
tree | 6bf7286c6e906e878dabe3509717b67ba8a86b0b /sound | |
parent | bc0195aad0daa2ad5b0d76cce22b167bc3435590 (diff) |
ASoC: cs42l56: Use case range at appropriate place
The readable registers are in continuous range: 0x01 ~ 0x2e.
Use case range syntax makes the code shorter with better readability when
we have a large number of continuous switch cases.
No functional change with this patch.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/codecs/cs42l56.c | 47 |
1 files changed, 1 insertions, 46 deletions
diff --git a/sound/soc/codecs/cs42l56.c b/sound/soc/codecs/cs42l56.c index 1e11ba45a79f..98a68c66cf71 100644 --- a/sound/soc/codecs/cs42l56.c +++ b/sound/soc/codecs/cs42l56.c @@ -115,52 +115,7 @@ static const struct reg_default cs42l56_reg_defaults[] = { static bool cs42l56_readable_register(struct device *dev, unsigned int reg) { switch (reg) { - case CS42L56_CHIP_ID_1: - case CS42L56_CHIP_ID_2: - case CS42L56_PWRCTL_1: - case CS42L56_PWRCTL_2: - case CS42L56_CLKCTL_1: - case CS42L56_CLKCTL_2: - case CS42L56_SERIAL_FMT: - case CS42L56_CLASSH_CTL: - case CS42L56_MISC_CTL: - case CS42L56_INT_STATUS: - case CS42L56_PLAYBACK_CTL: - case CS42L56_DSP_MUTE_CTL: - case CS42L56_ADCA_MIX_VOLUME: - case CS42L56_ADCB_MIX_VOLUME: - case CS42L56_PCMA_MIX_VOLUME: - case CS42L56_PCMB_MIX_VOLUME: - case CS42L56_ANAINPUT_ADV_VOLUME: - case CS42L56_DIGINPUT_ADV_VOLUME: - case CS42L56_MASTER_A_VOLUME: - case CS42L56_MASTER_B_VOLUME: - case CS42L56_BEEP_FREQ_ONTIME: - case CS42L56_BEEP_FREQ_OFFTIME: - case CS42L56_BEEP_TONE_CFG: - case CS42L56_TONE_CTL: - case CS42L56_CHAN_MIX_SWAP: - case CS42L56_AIN_REFCFG_ADC_MUX: - case CS42L56_HPF_CTL: - case CS42L56_MISC_ADC_CTL: - case CS42L56_GAIN_BIAS_CTL: - case CS42L56_PGAA_MUX_VOLUME: - case CS42L56_PGAB_MUX_VOLUME: - case CS42L56_ADCA_ATTENUATOR: - case CS42L56_ADCB_ATTENUATOR: - case CS42L56_ALC_EN_ATTACK_RATE: - case CS42L56_ALC_RELEASE_RATE: - case CS42L56_ALC_THRESHOLD: - case CS42L56_NOISE_GATE_CTL: - case CS42L56_ALC_LIM_SFT_ZC: - case CS42L56_AMUTE_HPLO_MUX: - case CS42L56_HPA_VOLUME: - case CS42L56_HPB_VOLUME: - case CS42L56_LOA_VOLUME: - case CS42L56_LOB_VOLUME: - case CS42L56_LIM_THRESHOLD_CTL: - case CS42L56_LIM_CTL_RELEASE_RATE: - case CS42L56_LIM_ATTACK_RATE: + case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE: return true; default: return false; |