diff options
author | Paweł Anikiel <pan@semihalf.com> | 2023-04-14 16:02:00 +0200 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2023-04-17 12:55:55 +0100 |
commit | 8076c586bbc1c62e075e58f41dafdd8b5022b24d (patch) | |
tree | bb0da1ad3bb43e64e3ef7ea916dee227d6f2de58 /sound | |
parent | fc0b096c92918c2ba4d76411ea763fdeb2ef6b0d (diff) |
ASoC: ssm2602: Add support for CLKDIV2
The SSM260x chips have an internal MCLK /2 divider (bit D7 in register
R8). Add logic that allows for more MCLK values using this divider.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Link: https://lore.kernel.org/r/20230414140203.707729-7-pan@semihalf.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/codecs/ssm2602.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index cbbe83b85ada..00b60369b029 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -280,9 +280,12 @@ static inline int ssm2602_get_coeff(int mclk, int rate) int i; for (i = 0; i < ARRAY_SIZE(ssm2602_coeff_table); i++) { - if (ssm2602_coeff_table[i].rate == rate && - ssm2602_coeff_table[i].mclk == mclk) - return ssm2602_coeff_table[i].srate; + if (ssm2602_coeff_table[i].rate == rate) { + if (ssm2602_coeff_table[i].mclk == mclk) + return ssm2602_coeff_table[i].srate; + if (ssm2602_coeff_table[i].mclk == mclk / 2) + return ssm2602_coeff_table[i].srate | SRATE_CORECLK_DIV2; + } } return -EINVAL; } @@ -365,18 +368,24 @@ static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai, switch (freq) { case 12288000: case 18432000: + case 24576000: + case 36864000: ssm2602->sysclk_constraints = &ssm2602_constraints_12288000; break; case 11289600: case 16934400: + case 22579200: + case 33868800: ssm2602->sysclk_constraints = &ssm2602_constraints_11289600; break; case 12000000: + case 24000000: ssm2602->sysclk_constraints = NULL; break; default: return -EINVAL; } + ssm2602->sysclk = freq; } else { unsigned int mask; |