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authorRichard Fitzgerald <rf@opensource.cirrus.com>2021-08-05 17:11:08 +0100
committerMark Brown <broonie@kernel.org>2021-08-05 23:33:43 +0100
commitb962bae81fa40fcce7662edcb1e426fa37d32abb (patch)
tree56e50452af6891fd9f60599ba2a400f4d89a0162 /sound/soc/codecs
parente5ada3f6787a4d6234adc6f2f3ae35c6d5b71ba0 (diff)
ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit
44.1kHz 16-bit standard I2S gives a SCLK of 1.4112 MHz. Add a PLL configuration for this. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210805161111.10410-5-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/cs42l42.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 99c022be94a6..6895f2fe9eb0 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -586,6 +586,7 @@ struct cs42l42_pll_params {
* Table 4-5 from the Datasheet
*/
static const struct cs42l42_pll_params pll_ratio_table[] = {
+ { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
{ 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
{ 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
{ 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},