diff options
author | Len Brown <len.brown@intel.com> | 2016-04-06 17:00:47 -0400 |
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committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-04-09 02:17:43 +0200 |
commit | 5dcef694860100fd16885f052591b1268b764d21 (patch) | |
tree | 7c083237a14697091466b2506f039e8d45363daa /security | |
parent | c998c07836f985b24361629dc98506ec7893e7a0 (diff) |
intel_idle: add BXT support
Broxton has all the HSW C-states, except C3.
BXT C-state timing is slightly different.
Here we trust the IRTL MSRs as authority
on maximum C-state latency, and override the driver's tables
with the values found in the associated IRTL MSRs.
Further we set the target_residency to 1x maximum latency,
trusting the hardware demotion logic.
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions