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authorMengdong Lin <mengdong.lin@intel.com>2015-04-20 17:33:57 +0800
committerTakashi Iwai <tiwai@suse.de>2015-04-20 17:27:55 +0200
commitf4c1a311d8dc55c90c39e9cf7b003254a769574d (patch)
treebb09e34b0fb05c7280b151a3528a13feebd1af6d /samples/seccomp
parent9476d369d7b39348945c297da5f2935904229813 (diff)
ALSA: hda - only sync BCLK to the display clock for Haswell & Broadwell
Only Intel Haswell and Broadwell have a separate HD-A controller (PCI device 3) for display audio, which needs to get 24MHz HD-A link BCLK from the variable display core clock through vendor specific registers EM4 & EM5. Other platforms (Baytrail, Braswell and Skylake) don't have this feature. So this patch checks the PCI device ID of the controller in haswell_set_bclk() and only sync BCLK for HSW and BDW. Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'samples/seccomp')
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