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author | Dinh Nguyen <dinguyen@kernel.org> | 2019-06-05 10:05:50 -0500 |
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committer | David S. Miller <davem@davemloft.net> | 2019-06-06 14:21:06 -0700 |
commit | b637e0856a6248230e53b5465ab0751f27fdf320 (patch) | |
tree | 82b71cb2e5e623c99f7c627654b5b207fc812890 /net/ipv6/reassembly.c | |
parent | 020aa5c7d42bf9cba171d1e6b4a0196226e4e03d (diff) |
dt-bindings: socfpga-dwmac: add "altr, socfpga-stmmac-a10-s10" binding
Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10
implementation of the stmmac ethernet controller.
On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Because of these differences, the dwmac-socfpga glue logic driver will
use this new binding to set the appropriate bits for PHY, PTP reference
clock, and signal from FPGA.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/ipv6/reassembly.c')
0 files changed, 0 insertions, 0 deletions