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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-29 09:57:13 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-29 09:57:13 -0800 |
| commit | d5ff835f88c7c346ba748f389bd4ef5eae619ebc (patch) | |
| tree | 8feddb009e4479fbdad95284d72e4aa3c629038f /ipc | |
| parent | 033dbbdec3ab178e5fe063a992b8c90ad08fd18c (diff) | |
| parent | 3676f9ef5481d614f8c5c857f5319755be248268 (diff) | |
Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64
Pull ARM64 fixes from Catalin Marinas:
- Remove preempt_count modifications in the arm64 IRQ handling code
since that's already dealt with in generic irq_enter/irq_exit
- PTE_PROT_NONE bit moved higher up to avoid overlapping with the
hardware bits (for PROT_NONE mappings which are pte_present)
- Big-endian fixes for ptrace support
- Asynchronous aborts unmasking while in the kernel
- pgprot_writecombine() change to create Normal NonCacheable memory
rather than Device GRE
* tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
arm64: Move PTE_PROT_NONE higher up
arm64: Use Normal NonCacheable memory for writecombine
arm64: debug: make aarch32 bkpt checking endian clean
arm64: ptrace: fix compat registes get/set to be endian clean
arm64: Unmask asynchronous aborts when in kernel mode
arm64: dts: Reserve the memory used for secondary CPU release address
arm64: let the core code deal with preempt_count
Diffstat (limited to 'ipc')
0 files changed, 0 insertions, 0 deletions