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authorMarc Zyngier <maz@kernel.org>2022-04-05 19:23:26 +0100
committerMarc Zyngier <maz@kernel.org>2022-05-04 14:09:53 +0100
commit4645d11f4a5538ec1221f36e397cfb0115718ffe (patch)
tree6ad52be9cbdd181135c5a4b2baa5af4bbd7425d6 /include
parent94828468a6085e6ae148986d300b634b87f86516 (diff)
KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
Since GICv4.1, it has become legal for an implementation to advertise GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more efficient invalidation scheme (no guest command queue contention when multiple CPUs are generating invalidations). Provide the invalidation registers as a primitive to their ITS counterpart. Note that we don't advertise them to the guest yet (the architecture allows an implementation to do this). Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Oliver Upton <oupton@google.com> Link: https://lore.kernel.org/r/20220405182327.205520-4-maz@kernel.org
Diffstat (limited to 'include')
-rw-r--r--include/kvm/arm_vgic.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index fdf1c2c322e5..401236f97cf2 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -344,6 +344,7 @@ struct vgic_cpu {
struct vgic_io_device rd_iodev;
struct vgic_redist_region *rdreg;
u32 rdreg_index;
+ atomic_t syncr_busy;
/* Contains the attributes and gpa of the LPI pending tables. */
u64 pendbaser;