diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2007-10-12 21:27:47 -0400 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2007-10-12 21:27:47 -0400 |
| commit | b981d8b3f5e008ff10d993be633ad00564fc22cd (patch) | |
| tree | e292dc07b22308912cf6a58354a608b9e5e8e1fd /include | |
| parent | b11d2127c4893a7315d1e16273bc8560049fa3ca (diff) | |
| parent | 2b9e0aae1d50e880c58d46788e5e3ebd89d75d62 (diff) | |
Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
drivers/macintosh/adbhid.c
Diffstat (limited to 'include')
1644 files changed, 31971 insertions, 28003 deletions
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index 8948a6461834..45662f6dbdb6 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -486,6 +486,8 @@ #define ACPI_FUNCTION_NAME(name) #endif +#ifdef DEBUG_FUNC_TRACE + #define ACPI_FUNCTION_TRACE(a) ACPI_FUNCTION_NAME(a) \ acpi_ut_trace(ACPI_DEBUG_PARAMETERS) #define ACPI_FUNCTION_TRACE_PTR(a,b) ACPI_FUNCTION_NAME(a) \ @@ -563,6 +565,27 @@ #endif /* ACPI_SIMPLE_RETURN_MACROS */ +#else /* !DEBUG_FUNC_TRACE */ + +#define ACPI_FUNCTION_TRACE(a) +#define ACPI_FUNCTION_TRACE_PTR(a,b) +#define ACPI_FUNCTION_TRACE_U32(a,b) +#define ACPI_FUNCTION_TRACE_STR(a,b) +#define ACPI_FUNCTION_EXIT +#define ACPI_FUNCTION_STATUS_EXIT(s) +#define ACPI_FUNCTION_VALUE_EXIT(s) +#define ACPI_FUNCTION_TRACE(a) +#define ACPI_FUNCTION_ENTRY() + +#define return_VOID return +#define return_ACPI_STATUS(s) return(s) +#define return_VALUE(s) return(s) +#define return_UINT8(s) return(s) +#define return_UINT32(s) return(s) +#define return_PTR(s) return(s) + +#endif /* DEBUG_FUNC_TRACE */ + /* Conditional execution */ #define ACPI_DEBUG_EXEC(a) a @@ -599,26 +622,26 @@ #define ACPI_DEBUG_EXEC(a) #define ACPI_NORMAL_EXEC(a) a; -#define ACPI_DEBUG_DEFINE(a) -#define ACPI_DEBUG_ONLY_MEMBERS(a) -#define ACPI_FUNCTION_NAME(a) -#define ACPI_FUNCTION_TRACE(a) -#define ACPI_FUNCTION_TRACE_PTR(a,b) -#define ACPI_FUNCTION_TRACE_U32(a,b) -#define ACPI_FUNCTION_TRACE_STR(a,b) -#define ACPI_FUNCTION_EXIT -#define ACPI_FUNCTION_STATUS_EXIT(s) -#define ACPI_FUNCTION_VALUE_EXIT(s) -#define ACPI_FUNCTION_ENTRY() -#define ACPI_DUMP_STACK_ENTRY(a) -#define ACPI_DUMP_OPERANDS(a,b,c,d,e) -#define ACPI_DUMP_ENTRY(a,b) -#define ACPI_DUMP_TABLES(a,b) -#define ACPI_DUMP_PATHNAME(a,b,c,d) -#define ACPI_DUMP_RESOURCE_LIST(a) -#define ACPI_DUMP_BUFFER(a,b) -#define ACPI_DEBUG_PRINT(pl) -#define ACPI_DEBUG_PRINT_RAW(pl) +#define ACPI_DEBUG_DEFINE(a) do { } while(0) +#define ACPI_DEBUG_ONLY_MEMBERS(a) do { } while(0) +#define ACPI_FUNCTION_NAME(a) do { } while(0) +#define ACPI_FUNCTION_TRACE(a) do { } while(0) +#define ACPI_FUNCTION_TRACE_PTR(a,b) do { } while(0) +#define ACPI_FUNCTION_TRACE_U32(a,b) do { } while(0) +#define ACPI_FUNCTION_TRACE_STR(a,b) do { } while(0) +#define ACPI_FUNCTION_EXIT do { } while(0) +#define ACPI_FUNCTION_STATUS_EXIT(s) do { } while(0) +#define ACPI_FUNCTION_VALUE_EXIT(s) do { } while(0) +#define ACPI_FUNCTION_ENTRY() do { } while(0) +#define ACPI_DUMP_STACK_ENTRY(a) do { } while(0) +#define ACPI_DUMP_OPERANDS(a,b,c,d,e) do { } while(0) +#define ACPI_DUMP_ENTRY(a,b) do { } while(0) +#define ACPI_DUMP_TABLES(a,b) do { } while(0) +#define ACPI_DUMP_PATHNAME(a,b,c,d) do { } while(0) +#define ACPI_DUMP_RESOURCE_LIST(a) do { } while(0) +#define ACPI_DUMP_BUFFER(a,b) do { } while(0) +#define ACPI_DEBUG_PRINT(pl) do { } while(0) +#define ACPI_DEBUG_PRINT_RAW(pl) do { } while(0) #define return_VOID return #define return_ACPI_STATUS(s) return(s) diff --git a/include/acpi/acoutput.h b/include/acpi/acoutput.h index 7812267b577f..c090a8b0bc99 100644 --- a/include/acpi/acoutput.h +++ b/include/acpi/acoutput.h @@ -178,8 +178,8 @@ /* Defaults for debug_level, debug and normal */ -#define ACPI_DEBUG_DEFAULT (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR | ACPI_LV_DEBUG_OBJECT) -#define ACPI_NORMAL_DEFAULT (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR | ACPI_LV_DEBUG_OBJECT) +#define ACPI_DEBUG_DEFAULT (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR) +#define ACPI_NORMAL_DEFAULT (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR) #define ACPI_DEBUG_ALL (ACPI_LV_AML_DISASSEMBLE | ACPI_LV_ALL_EXCEPTIONS | ACPI_LV_ALL) #endif /* __ACOUTPUT_H__ */ diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index c6fa5e023bc7..86aea44ce6d4 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -131,7 +131,7 @@ struct acpi_device_ops { struct acpi_driver { char name[80]; char class[80]; - char *ids; /* Supported Hardware IDs */ + const struct acpi_device_id *ids; /* Supported Hardware IDs */ struct acpi_device_ops ops; struct device_driver drv; struct module *owner; @@ -321,7 +321,7 @@ struct acpi_bus_event { }; extern struct kset acpi_subsys; - +extern int acpi_bus_generate_netlink_event(const char*, const char*, u8, int); /* * External Functions */ @@ -331,8 +331,13 @@ void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context); int acpi_bus_get_status(struct acpi_device *device); int acpi_bus_get_power(acpi_handle handle, int *state); int acpi_bus_set_power(acpi_handle handle, int state); -int acpi_bus_generate_event(struct acpi_device *device, u8 type, int data); +#ifdef CONFIG_ACPI_PROC_EVENT +int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data); int acpi_bus_receive_event(struct acpi_bus_event *event); +#else +static inline int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data) + { return 0; } +#endif int acpi_bus_register_driver(struct acpi_driver *driver); void acpi_bus_unregister_driver(struct acpi_driver *driver); int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent, @@ -340,7 +345,8 @@ int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent, int acpi_bus_trim(struct acpi_device *start, int rmdevice); int acpi_bus_start(struct acpi_device *device); acpi_status acpi_bus_get_ejd(acpi_handle handle, acpi_handle * ejd); -int acpi_match_ids(struct acpi_device *device, char *ids); +int acpi_match_device_ids(struct acpi_device *device, + const struct acpi_device_id *ids); int acpi_create_dir(struct acpi_device *); void acpi_remove_dir(struct acpi_device *); @@ -364,6 +370,17 @@ acpi_handle acpi_get_child(acpi_handle, acpi_integer); acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle)) +#ifdef CONFIG_PM_SLEEP +int acpi_pm_device_sleep_state(struct device *, int, int *); +#else /* !CONFIG_PM_SLEEP */ +static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p) +{ + if (p) + *p = ACPI_STATE_D0; + return ACPI_STATE_D3; +} +#endif /* !CONFIG_PM_SLEEP */ + #endif /* CONFIG_ACPI */ #endif /*__ACPI_BUS_H__*/ diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index 553515912c0b..f85f77a538aa 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -34,16 +34,21 @@ #define ACPI_BUS_COMPONENT 0x00010000 #define ACPI_SYSTEM_COMPONENT 0x02000000 -/* _HID definitions */ +/* + * _HID definitions + * HIDs must conform to ACPI spec(6.1.4) + * Linux specific HIDs do not apply to this and begin with LNX: + */ -#define ACPI_POWER_HID "power_resource" +#define ACPI_POWER_HID "LNXPOWER" #define ACPI_PROCESSOR_HID "ACPI0007" -#define ACPI_SYSTEM_HID "acpi_system" -#define ACPI_THERMAL_HID "thermal" -#define ACPI_BUTTON_HID_POWERF "button_power" -#define ACPI_BUTTON_HID_SLEEPF "button_sleep" -#define ACPI_VIDEO_HID "video" -#define ACPI_BAY_HID "bay" +#define ACPI_SYSTEM_HID "LNXSYSTM" +#define ACPI_THERMAL_HID "LNXTHERM" +#define ACPI_BUTTON_HID_POWERF "LNXPWRBN" +#define ACPI_BUTTON_HID_SLEEPF "LNXSLPBN" +#define ACPI_VIDEO_HID "LNXVIDEO" +#define ACPI_BAY_HID "LNXIOBAY" + /* -------------------------------------------------------------------------- PCI -------------------------------------------------------------------------- */ @@ -142,10 +147,6 @@ static inline void unregister_hotplug_dock_device(acpi_handle handle) /*-------------------------------------------------------------------------- Suspend/Resume -------------------------------------------------------------------------- */ -#ifdef CONFIG_ACPI_SLEEP extern int acpi_sleep_init(void); -#else -#define acpi_sleep_init() do {} while (0) -#endif #endif /*__ACPI_DRIVERS_H__*/ diff --git a/include/acpi/acpi_numa.h b/include/acpi/acpi_numa.h index e2fcee2b340d..62c5ee4311da 100644 --- a/include/acpi/acpi_numa.h +++ b/include/acpi/acpi_numa.h @@ -13,6 +13,7 @@ extern int pxm_to_node(int); extern int node_to_pxm(int); +extern void __acpi_map_pxm_to_node(int, int); extern int acpi_map_pxm_to_node(int); extern void __cpuinit acpi_unmap_pxm_to_node(int); diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index b5cca5daa348..3d7ab9e0c9fe 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -130,7 +130,7 @@ acpi_walk_namespace(acpi_object_type type, void *context, void **return_value); acpi_status -acpi_get_devices(char *HID, +acpi_get_devices(const char *HID, acpi_walk_callback user_function, void *context, void **return_value); diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index aeb4498e5e06..88482655407f 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -146,7 +146,7 @@ struct acpi_init_walk_info { struct acpi_get_devices_info { acpi_walk_callback user_function; void *context; - char *hid; + const char *hid; }; union acpi_aml_operands { diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index fe8abc276437..e73a38939120 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -809,7 +809,7 @@ acpi_status(*acpi_walk_callback) (acpi_handle obj_handle, /* Common string version of device HIDs and UIDs */ -struct acpi_device_id { +struct acpica_device_id { char value[ACPI_DEVICE_ID_LENGTH]; }; @@ -859,8 +859,8 @@ struct acpi_device_info { u32 valid; /* Indicates which fields below are valid */ u32 current_status; /* _STA value */ acpi_integer address; /* _ADR value if any */ - struct acpi_device_id hardware_id; /* _HID value if any */ - struct acpi_device_id unique_id; /* _UID value if any */ + struct acpica_device_id hardware_id; /* _HID value if any */ + struct acpica_device_id unique_id; /* _UID value if any */ u8 highest_dstates[4]; /* _sx_d values: 0xFF indicates not valid */ struct acpi_compatible_id_list compatibility_id; /* List of _CIDs if any */ }; diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index a87ef1c8d46b..a2918547c73f 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -354,7 +354,7 @@ acpi_ut_evaluate_numeric_object(char *object_name, acpi_status acpi_ut_execute_HID(struct acpi_namespace_node *device_node, - struct acpi_device_id *hid); + struct acpica_device_id *hid); acpi_status acpi_ut_execute_CID(struct acpi_namespace_node *device_node, @@ -366,7 +366,7 @@ acpi_ut_execute_STA(struct acpi_namespace_node *device_node, acpi_status acpi_ut_execute_UID(struct acpi_namespace_node *device_node, - struct acpi_device_id *uid); + struct acpica_device_id *uid); acpi_status acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest); diff --git a/include/acpi/platform/acenv.h b/include/acpi/platform/acenv.h index dab2ec59a3b0..c785485e62a6 100644 --- a/include/acpi/platform/acenv.h +++ b/include/acpi/platform/acenv.h @@ -136,7 +136,7 @@ /*! [Begin] no source code translation */ -#if defined(__linux__) +#if defined(_LINUX) || defined(__linux__) #include "aclinux.h" #elif defined(_AED_EFI) diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h index a568717f98c6..6ed15a0978eb 100644 --- a/include/acpi/platform/aclinux.h +++ b/include/acpi/platform/aclinux.h @@ -91,7 +91,10 @@ #define ACPI_USE_NATIVE_DIVIDE #endif +#ifndef __cdecl #define __cdecl +#endif + #define ACPI_FLUSH_CPU_CACHE() #endif /* __KERNEL__ */ diff --git a/include/acpi/processor.h b/include/acpi/processor.h index b4b0ffdab098..99934a999e66 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -21,6 +21,8 @@ #define ACPI_PSD_REV0_REVISION 0 /* Support for _PSD as in ACPI 3.0 */ #define ACPI_PSD_REV0_ENTRIES 5 +#define ACPI_TSD_REV0_REVISION 0 /* Support for _PSD as in ACPI 3.0 */ +#define ACPI_TSD_REV0_ENTRIES 5 /* * Types of coordination defined in ACPI 3.0. Same macros can be used across * P, C and T states @@ -125,17 +127,53 @@ struct acpi_processor_performance { /* Throttling Control */ +struct acpi_tsd_package { + acpi_integer num_entries; + acpi_integer revision; + acpi_integer domain; + acpi_integer coord_type; + acpi_integer num_processors; +} __attribute__ ((packed)); + +struct acpi_ptc_register { + u8 descriptor; + u16 length; + u8 space_id; + u8 bit_width; + u8 bit_offset; + u8 reserved; + u64 address; +} __attribute__ ((packed)); + +struct acpi_processor_tx_tss { + acpi_integer freqpercentage; /* */ + acpi_integer power; /* milliWatts */ + acpi_integer transition_latency; /* microseconds */ + acpi_integer control; /* control value */ + acpi_integer status; /* success indicator */ +}; struct acpi_processor_tx { u16 power; u16 performance; }; +struct acpi_processor; struct acpi_processor_throttling { - int state; + unsigned int state; + unsigned int platform_limit; + struct acpi_pct_register control_register; + struct acpi_pct_register status_register; + unsigned int state_count; + struct acpi_processor_tx_tss *states_tss; + struct acpi_tsd_package domain_info; + cpumask_t shared_cpu_map; + int (*acpi_processor_get_throttling) (struct acpi_processor * pr); + int (*acpi_processor_set_throttling) (struct acpi_processor * pr, + int state); + u32 address; u8 duty_offset; u8 duty_width; - int state_count; struct acpi_processor_tx states[ACPI_PROCESSOR_MAX_THROTTLING]; }; @@ -169,6 +207,9 @@ struct acpi_processor { u32 id; u32 pblk; int performance_platform_limit; + int throttling_platform_limit; + /* 0 - states 0..n-th state available */ + struct acpi_processor_flags flags; struct acpi_processor_power power; struct acpi_processor_performance *performance; @@ -191,7 +232,7 @@ struct acpi_processor_errata { extern int acpi_processor_preregister_performance(struct acpi_processor_performance - **performance); + *performance); extern int acpi_processor_register_performance(struct acpi_processor_performance *performance, unsigned int cpu); @@ -270,7 +311,7 @@ static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr) /* in processor_throttling.c */ int acpi_processor_get_throttling_info(struct acpi_processor *pr); -int acpi_processor_set_throttling(struct acpi_processor *pr, int state); +extern int acpi_processor_set_throttling(struct acpi_processor *pr, int state); extern struct file_operations acpi_processor_throttling_fops; /* in processor_idle.c */ @@ -279,6 +320,8 @@ int acpi_processor_power_init(struct acpi_processor *pr, int acpi_processor_cst_has_changed(struct acpi_processor *pr); int acpi_processor_power_exit(struct acpi_processor *pr, struct acpi_device *device); +int acpi_processor_suspend(struct acpi_device * device, pm_message_t state); +int acpi_processor_resume(struct acpi_device * device); /* in processor_thermal.c */ int acpi_processor_get_limit_info(struct acpi_processor *pr); diff --git a/include/asm-alpha/a.out.h b/include/asm-alpha/a.out.h index d97daf42753d..e43cf61649a9 100644 --- a/include/asm-alpha/a.out.h +++ b/include/asm-alpha/a.out.h @@ -101,6 +101,8 @@ struct exec #define STACK_TOP \ (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL) +#define STACK_TOP_MAX 0x00120000000UL + #endif #endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-alpha/bitops.h b/include/asm-alpha/bitops.h index 3a0cbeb03fa1..9e71201000d5 100644 --- a/include/asm-alpha/bitops.h +++ b/include/asm-alpha/bitops.h @@ -324,7 +324,7 @@ static inline int fls64(unsigned long x) { unsigned long t, a, r; - t = __kernel_cmpbge (x, 0x0101010101010101); + t = __kernel_cmpbge (x, 0x0101010101010101UL); a = __flsm1_tab[t]; t = __kernel_extbl (x, a); r = a*8 + __flsm1_tab[t] + (x != 0); diff --git a/include/asm-alpha/fcntl.h b/include/asm-alpha/fcntl.h index 87f2cf459e26..25da0017ec87 100644 --- a/include/asm-alpha/fcntl.h +++ b/include/asm-alpha/fcntl.h @@ -16,6 +16,7 @@ #define O_LARGEFILE 0400000 /* will be set by the kernel on every open */ #define O_DIRECT 02000000 /* direct disk access - should check with OSF/1 */ #define O_NOATIME 04000000 +#define O_CLOEXEC 010000000 /* set close_on_exec */ #define F_GETLK 7 #define F_SETLK 8 diff --git a/include/asm-alpha/irq.h b/include/asm-alpha/irq.h index 917b9fe372cf..06377400dc09 100644 --- a/include/asm-alpha/irq.h +++ b/include/asm-alpha/irq.h @@ -85,10 +85,6 @@ static __inline__ int irq_canonicalize(int irq) return ((irq == 2) ? 9 : irq); } -extern void disable_irq(unsigned int); -extern void disable_irq_nosync(unsigned int); -extern void enable_irq(unsigned int); - struct pt_regs; extern void (*perf_irq)(unsigned long, struct pt_regs *); diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h index cf1021a97b2e..620c4d86cbf4 100644 --- a/include/asm-alpha/system.h +++ b/include/asm-alpha/system.h @@ -139,16 +139,6 @@ extern void halt(void) __attribute__((noreturn)); struct task_struct; extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*); -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - #define imb() \ __asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory") diff --git a/include/asm-alpha/thread_info.h b/include/asm-alpha/thread_info.h index 48a22e3e6f32..fb3185196298 100644 --- a/include/asm-alpha/thread_info.h +++ b/include/asm-alpha/thread_info.h @@ -67,28 +67,24 @@ register struct thread_info *__current_thread_info __asm__("$8"); * TIF_SYSCALL_TRACE is known to be 0 via blbs. */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* poll_idle is polling NEED_RESCHED */ -#define TIF_DIE_IF_KERNEL 5 /* dik recursion lock */ -#define TIF_UAC_NOPRINT 6 /* see sysinfo.h */ -#define TIF_UAC_NOFIX 7 -#define TIF_UAC_SIGBUS 8 -#define TIF_MEMDIE 9 -#define TIF_RESTORE_SIGMASK 10 /* restore signal mask in do_signal */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* poll_idle is polling NEED_RESCHED */ +#define TIF_DIE_IF_KERNEL 4 /* dik recursion lock */ +#define TIF_UAC_NOPRINT 5 /* see sysinfo.h */ +#define TIF_UAC_NOFIX 6 +#define TIF_UAC_SIGBUS 7 +#define TIF_MEMDIE 8 +#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) /* Work to do on interrupt/exception return. */ -#define _TIF_WORK_MASK (_TIF_NOTIFY_RESUME \ - | _TIF_SIGPENDING \ - | _TIF_NEED_RESCHED) +#define _TIF_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED) /* Work to do on any return to userspace. */ #define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \ diff --git a/include/asm-arm/a.out.h b/include/asm-arm/a.out.h index 3e5fe64c4394..d7165e86df25 100644 --- a/include/asm-arm/a.out.h +++ b/include/asm-arm/a.out.h @@ -30,6 +30,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ TASK_SIZE : TASK_SIZE_26) +#define STACK_TOP_MAX TASK_SIZE #endif #ifndef LIBRARY_START_TEXT diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h index 40a9876b661a..c2e11cc374ba 100644 --- a/include/asm-arm/arch-at91/at91_mci.h +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -26,6 +26,9 @@ #define AT91_MCI_MR 0x04 /* Mode Register */ #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1127a3b5e928..70b1216dce5d 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -42,4 +42,7 @@ */ #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) +/* FIQ is AIC source 0. */ +#define FIQ_START AT91_ID_FIQ + #endif diff --git a/include/asm-arm/arch-imx/mmc.h b/include/asm-arm/arch-imx/mmc.h index 84c726934ace..4712f354dcca 100644 --- a/include/asm-arm/arch-imx/mmc.h +++ b/include/asm-arm/arch-imx/mmc.h @@ -3,8 +3,11 @@ #include <linux/mmc/host.h> +struct device; + struct imxmmc_platform_data { - int (*card_present)(void); + int (*card_present)(struct device *); + int (*get_ro)(struct device *); }; extern void imx_set_mmc_info(struct imxmmc_platform_data *info); diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index d4e4f828577c..52b7fab7ef60 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void) return id; } +/* WDTCR CP6 R7 Page 9 */ +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); +} + +/* WDTSR CP6 R8 Page 9 */ +static inline u32 read_wdtsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtsr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); +} + +/* RCSR - Reset Cause Status Register */ +static inline u32 read_rcsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); + return val; +} + +extern unsigned long get_iop_tick_rate(void); #endif /* @@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) + +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f +#define IOP_WDTCR_DIS 0xf1f1f1f1 +#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ +#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ +#define IOP13XX_WDTCR_IB_RESET (1 << 0) + #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h index 127827058e1f..8575af8db78c 100644 --- a/include/asm-arm/arch-iop13xx/system.h +++ b/include/asm-arm/arch-iop13xx/system.h @@ -13,43 +13,13 @@ static inline void arch_idle(void) cpu_do_idle(); } -/* WDTCR CP6 R7 Page 9 */ -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); -} - -/* WDTSR CP6 R8 Page 9 */ -static inline u32 read_wdtsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtsr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); -} - -#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP13XX_WDTCR_EN 0xe1e1e1e1 -#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f -#define IOP13XX_WDTCR_DIS 0xf1f1f1f1 -#define IOP13XX_WDTSR_WRITE_EN (1 << 31) -#define IOP13XX_WDTCR_IB_RESET (1 << 0) static inline void arch_reset(char mode) { /* * Reset the internal bus (warning both cores are reset) */ - write_wdtcr(IOP13XX_WDTCR_EN_ARM); - write_wdtcr(IOP13XX_WDTCR_EN); + write_wdtcr(IOP_WDTCR_EN_ARM); + write_wdtcr(IOP_WDTCR_EN); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtcr(0x1000); diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h index b9525d59b7ad..dd9c2934190e 100644 --- a/include/asm-arm/arch-iop13xx/uncompress.h +++ b/include/asm-arm/arch-iop13xx/uncompress.h @@ -1,7 +1,6 @@ #include <asm/types.h> #include <linux/serial_reg.h> #include <asm/hardware.h> -#include <asm/processor.h> #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) @@ -9,7 +8,7 @@ static inline void putc(char c) { while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) - cpu_relax(); + barrier(); UART_BASE[UART_TX] = c; } diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h index e64f52bf2bce..070f15818fe7 100644 --- a/include/asm-arm/arch-iop32x/uncompress.h +++ b/include/asm-arm/arch-iop32x/uncompress.h @@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) { if (machine_is_iq80321()) uart_base = (volatile u8 *)IQ80321_UART; - else if (machine_is_iq31244()) + else if (machine_is_iq31244() || machine_is_em7210()) uart_base = (volatile u8 *)IQ31244_UART; else uart_base = (volatile u8 *)0xfe800000; diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h new file mode 100644 index 000000000000..be29b83ad4ae --- /dev/null +++ b/include/asm-arm/arch-mxc/board-mx31ads.h @@ -0,0 +1,142 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ + +/*! + * @name PBC Controller parameters + */ +/*! @{ */ +/*! + * Base address of PBC controller + */ +#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) +/* Offsets for the PBC Controller register */ +/*! + * PBC Board status register offset + */ +#define PBC_BSTAT 0x000002 +/*! + * PBC Board control register 1 set address. + */ +#define PBC_BCTRL1_SET 0x000004 +/*! + * PBC Board control register 1 clear address. + */ +#define PBC_BCTRL1_CLEAR 0x000006 +/*! + * PBC Board control register 2 set address. + */ +#define PBC_BCTRL2_SET 0x000008 +/*! + * PBC Board control register 2 clear address. + */ +#define PBC_BCTRL2_CLEAR 0x00000A +/*! + * PBC Board control register 3 set address. + */ +#define PBC_BCTRL3_SET 0x00000C +/*! + * PBC Board control register 3 clear address. + */ +#define PBC_BCTRL3_CLEAR 0x00000E +/*! + * PBC Board control register 4 set address. + */ +#define PBC_BCTRL4_SET 0x000010 +/*! + * PBC Board control register 4 clear address. + */ +#define PBC_BCTRL4_CLEAR 0x000012 +/*! + * PBC Board status register 1. + */ +#define PBC_BSTAT1 0x000014 +/*! + * PBC Board interrupt status register. + */ +#define PBC_INTSTATUS 0x000016 +/*! + * PBC Board interrupt current status register. + */ +#define PBC_INTCURR_STATUS 0x000018 +/*! + * PBC Interrupt mask register set address. + */ +#define PBC_INTMASK_SET 0x00001A +/*! + * PBC Interrupt mask register clear address. + */ +#define PBC_INTMASK_CLEAR 0x00001C + +/*! + * External UART A. + */ +#define PBC_SC16C652_UARTA 0x010000 +/*! + * External UART B. + */ +#define PBC_SC16C652_UARTB 0x010010 +/*! + * Ethernet Controller IO base address. + */ +#define PBC_CS8900A_IOBASE 0x020000 +/*! + * Ethernet Controller Memory base address. + */ +#define PBC_CS8900A_MEMBASE 0x021000 +/*! + * Ethernet Controller DMA base address. + */ +#define PBC_CS8900A_DMABASE 0x022000 +/*! + * External chip select 0. + */ +#define PBC_XCS0 0x040000 +/*! + * LCD Display enable. + */ +#define PBC_LCD_EN_B 0x060000 +/*! + * Code test debug enable. + */ +#define PBC_CODE_B 0x070000 +/*! + * PSRAM memory select. + */ +#define PBC_PSRAM_B 0x5000000 + +#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) +#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) +#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) +#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) + +#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) +#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) +#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) +#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) +#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) +#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) +#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) +#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) +#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) +#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) +#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) +#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) + +#define MXC_MAX_EXP_IO_LINES 16 + +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h new file mode 100644 index 000000000000..23b4350edbd6 --- /dev/null +++ b/include/asm-arm/arch-mxc/common.h @@ -0,0 +1,20 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_COMMON_H__ +#define __ASM_ARCH_MXC_COMMON_H__ + +struct sys_timer; + +extern void mxc_map_io(void); +extern void mxc_init_irq(void); +extern struct sys_timer mxc_timer; + +#endif diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h new file mode 100644 index 000000000000..65e639d51d2b --- /dev/null +++ b/include/asm-arm/arch-mxc/dma.h @@ -0,0 +1,21 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +/*! + * @file dma.h + * @brief This file contains Unified DMA API for all MXC platforms. + * The API is platform independent. + * + * @ingroup SDMA + */ +#endif diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S new file mode 100644 index 000000000000..b542433afb1b --- /dev/null +++ b/include/asm-arm/arch-mxc/entry-macro.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + @ this macro disables fast irq (not implemented) + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + @ this macro checks which interrupt occured + @ and returns its number in irqnr + @ and returns if an interrupt occured in irqstat + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) + @ Load offset & priority of the highest priority + @ interrupt pending from AVIC_NIVECSR + ldr \irqstat, [\base, #0x40] + @ Shift to get the decoded IRQ number, using ASR so + @ 'no interrupt pending' becomes 0xffffffff + mov \irqnr, \irqstat, asr #16 + @ set zero flag if IRQ + 1 == 0 + adds \tmp, \irqnr, #1 + .endm + + @ irq priority table (not used) + .macro irq_prio_table + .endm diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h new file mode 100644 index 000000000000..3c09b92fef0d --- /dev/null +++ b/include/asm-arm/arch-mxc/hardware.h @@ -0,0 +1,52 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/*! + * @file hardware.h + * @brief This file contains the hardware definitions of the board. + * + * @ingroup System + */ +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#define __ASM_ARCH_MXC_HARDWARE_H__ + +#include <asm/sizes.h> + +#include <asm/arch/mx31.h> + +#include <asm/arch/mxc.h> + +#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) + +/* + * --------------------------------------------------------------------------- + * Board specific defines + * --------------------------------------------------------------------------- + */ +#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES) + +#include <asm/arch/board-mx31ads.h> + +#ifndef MXC_MAX_EXP_IO_LINES +#define MXC_MAX_EXP_IO_LINES 0 +#endif + +#define MXC_MAX_VIRTUAL_INTS 16 +#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) +#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE +#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) +#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) + +#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \ + MXC_MAX_GPIO_LINES + \ + MXC_MAX_EXP_IO_LINES + \ + MXC_MAX_VIRTUAL_INTS) + +#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h new file mode 100644 index 000000000000..cf6c83a4b9f7 --- /dev/null +++ b/include/asm-arm/arch-mxc/io.h @@ -0,0 +1,33 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/*! + * @file io.h + * @brief This file contains some memory mapping macros. + * @note There is no real ISA or PCI buses. But have to define these macros + * for some drivers to compile. + * + * @ingroup System + */ + +#ifndef __ASM_ARCH_MXC_IO_H__ +#define __ASM_ARCH_MXC_IO_H__ + +/*! Allow IO space to be anywhere in the memory */ +#define IO_SPACE_LIMIT 0xffffffff + +/*! + * io address mapping macro + */ +#define __io(a) ((void __iomem *)(a)) + +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h new file mode 100644 index 000000000000..e4686c6bc4bf --- /dev/null +++ b/include/asm-arm/arch-mxc/irqs.h @@ -0,0 +1,38 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_IRQS_H__ +#define __ASM_ARCH_MXC_IRQS_H__ + +#include <asm/hardware.h> + +/*! + * @file irqs.h + * @brief This file defines the number of normal interrupts and fast interrupts + * + * @ingroup Interrupt + */ + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) +#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) + +/*! + * Number of normal interrupts + */ +#define NR_IRQS MXC_MAX_INTS + +/*! + * Number of fast interrupts + */ +#define NR_FIQS MXC_MAX_INTS + +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h new file mode 100644 index 000000000000..c89aac83a407 --- /dev/null +++ b/include/asm-arm/arch-mxc/memory.h @@ -0,0 +1,36 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_MEMORY_H__ +#define __ASM_ARCH_MXC_MEMORY_H__ + +#include <asm/hardware.h> + +/*! + * @file memory.h + * @brief This file contains macros needed by the Linux kernel and drivers. + * + * @ingroup Memory + */ + +/*! + * Virtual view <-> DMA view memory address translations + * This macro is used to translate the virtual address to an address + * suitable to be passed to set_dma_addr() + */ +#define __virt_to_bus(a) __virt_to_phys(a) + +/*! + * Used to convert an address for DMA operations to an address that the + * kernel can use. + */ +#define __bus_to_virt(a) __phys_to_virt(a) + +#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h new file mode 100644 index 000000000000..85c49c9e5d15 --- /dev/null +++ b/include/asm-arm/arch-mxc/mx31.h @@ -0,0 +1,335 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_MX31_H__ +#define __ASM_ARCH_MXC_MX31_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/*! + * defines the hardware clock tick rate + */ +#define CLOCK_TICK_RATE 16625000 + +/* + * MX31 memory map: + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * F8000000 1FFC0000 16K IRAM + * F9000000 30000000 256M L2CC + * FC000000 43F00000 1M AIPS 1 + * FC100000 50000000 1M SPBA + * FC200000 53F00000 1M AIPS 2 + * FC500000 60000000 128M ROMPATCH + * FC400000 68000000 128M AVIC + * 70000000 256M IPU (MAX M2) + * 80000000 256M CSD0 SDRAM/DDR + * 90000000 256M CSD1 SDRAM/DDR + * A0000000 128M CS0 Flash + * A8000000 128M CS1 Flash + * B0000000 32M CS2 + * B2000000 32M CS3 + * F4000000 B4000000 32M CS4 + * B6000000 32M CS5 + * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers + * C0000000 64M PCMCIA/CF + */ + +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 + +#define CS4_BASE_ADDR 0xB4000000 +#define CS4_BASE_ADDR_VIRT 0xF4000000 +#define CS4_SIZE SZ_32M + +#define CS5_BASE_ADDR 0xB6000000 +#define PCMCIA_MEM_BASE_ADDR 0xBC000000 + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ +#define IRAM_BASE_ADDR_VIRT 0xF8000000 +#define IRAM_SIZE SZ_16K + +/* + * L2CC + */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2CC_BASE_ADDR_VIRT 0xF9000000 +#define L2CC_SIZE SZ_1M + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_BASE_ADDR_VIRT 0xFC000000 +#define AIPS1_SIZE SZ_1M + +#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) +#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) +#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) +#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) +#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) +#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) +#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x50000000 +#define SPBA0_BASE_ADDR_VIRT 0xFC100000 +#define SPBA0_SIZE SZ_1M + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) +#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR_VIRT 0xFC200000 +#define AIPS2_SIZE SZ_1M +#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) +#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) +#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) +#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) + +/* + * ROMP and AVIC + */ +#define ROMP_BASE_ADDR 0x60000000 +#define ROMP_BASE_ADDR_VIRT 0xFC500000 +#define ROMP_SIZE SZ_1M + +#define AVIC_BASE_ADDR 0x68000000 +#define AVIC_BASE_ADDR_VIRT 0xFC400000 +#define AVIC_SIZE SZ_1M + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define X_MEMC_BASE_ADDR 0xB8000000 +#define X_MEMC_BASE_ADDR_VIRT 0xFC320000 +#define X_MEMC_SIZE SZ_64K + +#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) +#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) +#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) +#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) +#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) +#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 + +#define CS4_BASE_ADDR 0xB4000000 +#define CS4_BASE_ADDR_VIRT 0xF4000000 +#define CS4_SIZE SZ_32M + +#define CS5_BASE_ADDR 0xB6000000 +#define PCMCIA_MEM_BASE_ADDR 0xBC000000 + +/*! + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ +#define IO_ADDRESS(x) \ + (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ + ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ + ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ + ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ + ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ + ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ + ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ + ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ + ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ + +#define IRAM_IO_ADDRESS(x) \ + (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT) + +#define L2CC_IO_ADDRESS(x) \ + (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) + +#define AIPS1_IO_ADDRESS(x) \ + (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) + +#define SPBA0_IO_ADDRESS(x) \ + (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) + +#define AIPS2_IO_ADDRESS(x) \ + (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) + +#define ROMP_IO_ADDRESS(x) \ + (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) + +#define AVIC_IO_ADDRESS(x) \ + (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) + +#define CS4_IO_ADDRESS(x) \ + (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) + +#define X_MEMC_IO_ADDRESS(x) \ + (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) + +#define PCMCIA_IO_ADDRESS(x) \ + (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) + +/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */ +#define PHYS_OFFSET CSD0_BASE_ADDR + +/* + * Interrupt numbers + */ +#define MXC_INT_PEN_ADS7843 0 +#define MXC_INT_RESV1 1 +#define MXC_INT_CS8900A 2 +#define MXC_INT_I2C3 3 +#define MXC_INT_I2C2 4 +#define MXC_INT_MPEG4_ENCODER 5 +#define MXC_INT_RTIC 6 +#define MXC_INT_FIRI 7 +#define MXC_INT_MMC_SDHC2 8 +#define MXC_INT_MMC_SDHC1 9 +#define MXC_INT_I2C 10 +#define MXC_INT_SSI2 11 +#define MXC_INT_SSI1 12 +#define MXC_INT_CSPI2 13 +#define MXC_INT_CSPI1 14 +#define MXC_INT_ATA 15 +#define MXC_INT_MBX 16 +#define MXC_INT_CSPI3 17 +#define MXC_INT_UART3 18 +#define MXC_INT_IIM 19 +#define MXC_INT_SIM2 20 +#define MXC_INT_SIM1 21 +#define MXC_INT_RNGA 22 +#define MXC_INT_EVTMON 23 +#define MXC_INT_KPP 24 +#define MXC_INT_RTC 25 +#define MXC_INT_PWM 26 +#define MXC_INT_EPIT2 27 +#define MXC_INT_EPIT1 28 +#define MXC_INT_GPT 29 +#define MXC_INT_RESV30 30 +#define MXC_INT_RESV31 31 +#define MXC_INT_UART2 32 +#define MXC_INT_NANDFC 33 +#define MXC_INT_SDMA 34 +#define MXC_INT_USB1 35 +#define MXC_INT_USB2 36 +#define MXC_INT_USB3 37 +#define MXC_INT_USB4 38 +#define MXC_INT_MSHC1 39 +#define MXC_INT_MSHC2 40 +#define MXC_INT_IPU_ERR 41 +#define MXC_INT_IPU_SYN 42 +#define MXC_INT_RESV43 43 +#define MXC_INT_RESV44 44 +#define MXC_INT_UART1 45 +#define MXC_INT_UART4 46 +#define MXC_INT_UART5 47 +#define MXC_INT_ECT 48 +#define MXC_INT_SCC_SCM 49 +#define MXC_INT_SCC_SMN 50 +#define MXC_INT_GPIO2 51 +#define MXC_INT_GPIO1 52 +#define MXC_INT_CCM 53 +#define MXC_INT_PCMCIA 54 +#define MXC_INT_WDOG 55 +#define MXC_INT_GPIO3 56 +#define MXC_INT_RESV57 57 +#define MXC_INT_EXT_POWER 58 +#define MXC_INT_EXT_TEMPER 59 +#define MXC_INT_EXT_SENSOR60 60 +#define MXC_INT_EXT_SENSOR61 61 +#define MXC_INT_EXT_WDOG 62 +#define MXC_INT_EXT_TV 63 + +#define MXC_MAX_INT_LINES 64 + +#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES + +/*! + * Number of GPIO port as defined in the IC Spec + */ +#define GPIO_PORT_NUM 3 +/*! + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define PROD_SIGNATURE 0x1 /* For MX31 */ + +#define SYSTEM_REV_MIN CHIP_REV_1_0 +#define SYSTEM_REV_NUM 3 + +#endif /* __ASM_ARCH_MXC_MX31_H__ */ diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h new file mode 100644 index 000000000000..0837f1f9ca31 --- /dev/null +++ b/include/asm-arm/arch-mxc/mxc.h @@ -0,0 +1,149 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_H__ +#define __ASM_ARCH_MXC_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/* + ***************************************** + * GPT Register definitions * + ***************************************** + */ +#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00) +#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04) +#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08) +#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C) +#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10) +#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14) +#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18) +#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C) +#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) +#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) + +/*! + * GPT Control register bit definitions + */ +#define GPTCR_FO3 (1 << 31) +#define GPTCR_FO2 (1 << 30) +#define GPTCR_FO1 (1 << 29) + +#define GPTCR_OM3_SHIFT 26 +#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT) +#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT) +#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT) +#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT) +#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT) +#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT) + +#define GPTCR_OM2_SHIFT 23 +#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT) +#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT) +#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT) +#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT) +#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT) +#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT) + +#define GPTCR_OM1_SHIFT 20 +#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT) +#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT) +#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT) +#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT) +#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT) +#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT) + +#define GPTCR_IM2_SHIFT 18 +#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT) +#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT) +#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT) +#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT) +#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT) + +#define GPTCR_IM1_SHIFT 16 +#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT) +#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT) +#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT) +#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT) +#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT) + +#define GPTCR_SWR (1 << 15) +#define GPTCR_FRR (1 << 9) + +#define GPTCR_CLKSRC_SHIFT 6 +#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT) +#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT) + +#define GPTCR_STOPEN (1 << 5) +#define GPTCR_DOZEN (1 << 4) +#define GPTCR_WAITEN (1 << 3) +#define GPTCR_DBGEN (1 << 2) + +#define GPTCR_ENMOD (1 << 1) +#define GPTCR_ENABLE (1 << 0) + +#define GPTSR_OF1 (1 << 0) +#define GPTSR_OF2 (1 << 1) +#define GPTSR_OF3 (1 << 2) +#define GPTSR_IF1 (1 << 3) +#define GPTSR_IF2 (1 << 4) +#define GPTSR_ROV (1 << 5) + +#define GPTIR_OF1IE GPTSR_OF1 +#define GPTIR_OF2IE GPTSR_OF2 +#define GPTIR_OF3IE GPTSR_OF3 +#define GPTIR_IF1IE GPTSR_IF1 +#define GPTIR_IF2IE GPTSR_IF2 +#define GPTIR_ROVIE GPTSR_ROV + +/* + ***************************************** + * AVIC Registers * + ***************************************** + */ +#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) +#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ +#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */ +#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */ +#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */ +#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */ +#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ +#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ +#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ +#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ +#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */ +#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */ +#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */ +#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */ +#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */ +#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */ +#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */ +#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ +#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ +#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ +#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */ +#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */ +#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */ +#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */ +#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */ +#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */ +#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */ + +#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20) +#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24) +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 + +#endif /* __ASM_ARCH_MXC_H__ */ diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h new file mode 100644 index 000000000000..109956b41aca --- /dev/null +++ b/include/asm-arm/arch-mxc/system.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_SYSTEM_H__ +#define __ASM_ARCH_MXC_SYSTEM_H__ + +/*! + * @file system.h + * @brief This file contains idle and reset functions. + * + * @ingroup System + */ + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h new file mode 100644 index 000000000000..59019fa58f82 --- /dev/null +++ b/include/asm-arm/arch-mxc/timex.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_TIMEX_H__ +#define __ASM_ARCH_MXC_TIMEX_H__ + +#include <asm/hardware.h> /* for CLOCK_TICK_RATE */ + +#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h new file mode 100644 index 000000000000..42cc0cb3fefd --- /dev/null +++ b/include/asm-arm/arch-mxc/uncompress.h @@ -0,0 +1,78 @@ +/* + * include/asm-arm/arch-mxc/uncompress.h + * + * + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ +#define __ASM_ARCH_MXC_UNCOMPRESS_H__ + +#define __MXC_BOOT_UNCOMPRESS + +#include <asm/hardware.h> + +#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) + +#define USR2 0x98 +#define USR2_TXFE (1<<14) +#define TXR 0x40 +#define UCR1 0x80 +#define UCR1_UARTEN 1 + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. We search for the first enabled + * port in the most probable order. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ + +static void putc(int ch) +{ + static unsigned long serial_port = 0; + + if (unlikely(serial_port == 0)) { + do { + serial_port = UART1_BASE_ADDR; + if (UART(UCR1) & UCR1_UARTEN) + break; + serial_port = UART2_BASE_ADDR; + if (UART(UCR1) & UCR1_UARTEN) + break; + return; + } while (0); + } + + while (!(UART(USR2) & USR2_TXFE)) + barrier(); + + UART(TXR) = ch; +} + +#define flush() do { } while (0) + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h new file mode 100644 index 000000000000..83a73da895eb --- /dev/null +++ b/include/asm-arm/arch-mxc/vmalloc.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2000 Russell King. + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_VMALLOC_H__ +#define __ASM_ARCH_MXC_VMALLOC_H__ + +/*! + * @file vmalloc.h + * + * @brief This file contains platform specific macros for vmalloc. + * + * @ingroup System + */ + +/*! + * vmalloc ending address + */ +#define VMALLOC_END 0xF4000000 + +#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h index e26269546240..7ee194dc6354 100644 --- a/include/asm-arm/arch-ns9xxx/regs-bbu.h +++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h @@ -15,7 +15,31 @@ /* BBus Utility */ -/* GPIO Configuration Register */ -#define BBU_GC(x) __REG2(0x9060000c, (x)) +/* GPIO Configuration Registers block 1 */ +/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is + * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register + * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ +#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) +#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) + +#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) +#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) +#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) +#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) +#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) +#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) +#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) +#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) +#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) +#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) +#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) + +#define BBU_GCTRL1 __REG(0x90600030) +#define BBU_GCTRL2 __REG(0x90600034) +#define BBU_GCTRL3 __REG(0x90600120) + +#define BBU_GSTAT1 __REG(0x90600040) +#define BBU_GSTAT2 __REG(0x90600044) +#define BBU_GSTAT3 __REG(0x90600130) #endif /* ifndef __ASM_ARCH_REGSBBU_H */ diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h index 8ed8448767b9..fb455a0ed845 100644 --- a/include/asm-arm/arch-ns9xxx/regs-mem.h +++ b/include/asm-arm/arch-ns9xxx/regs-mem.h @@ -79,9 +79,9 @@ #define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) /* Static Memory Configuration Register x: Write protect */ -#define MEM_SMC_WSMC __REGBIT(20) -#define MEM_SMC_WSMC_OFF __REGVAL(MEM_SMC_WSMC, 0) -#define MEM_SMC_WSMC_ON __REGVAL(MEM_SMC_WSMC, 1) +#define MEM_SMC_PSMC __REGBIT(20) +#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0) +#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1) /* Static Memory Configuration Register x: Buffer enable */ #define MEM_SMC_BSMC __REGBIT(19) diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h index a42546aeb92a..749262f86204 100644 --- a/include/asm-arm/arch-ns9xxx/regs-sys.h +++ b/include/asm-arm/arch-ns9xxx/regs-sys.h @@ -64,7 +64,7 @@ /* Timer x Control register: Timer enable */ #define SYS_TCx_TEN __REGBIT(15) -#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 1) +#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0) #define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) /* Timer x Control register: CPU debug mode */ diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h index 345a649ec838..96bb12fab438 100644 --- a/include/asm-arm/arch-omap/irda.h +++ b/include/asm-arm/arch-omap/irda.h @@ -31,6 +31,7 @@ struct omap_irda_config { unsigned long src_start; int tx_trigger; int rx_trigger; + int mode; }; #endif diff --git a/include/asm-arm/arch-omap/mailbox.h b/include/asm-arm/arch-omap/mailbox.h index 4bf0909461f2..7cbed9332e16 100644 --- a/include/asm-arm/arch-omap/mailbox.h +++ b/include/asm-arm/arch-omap/mailbox.h @@ -37,7 +37,7 @@ struct omap_mbox_ops { struct omap_mbox_queue { spinlock_t lock; - request_queue_t *queue; + struct request_queue *queue; struct work_struct work; int (*callback)(void *); struct omap_mbox *mbox; diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h index 52243a62c4e7..6903db7fae15 100644 --- a/include/asm-arm/arch-pxa/pm.h +++ b/include/asm-arm/arch-pxa/pm.h @@ -7,5 +7,19 @@ * */ -extern int pxa_pm_prepare(suspend_state_t state); +struct pxa_cpu_pm_fns { + int save_size; + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); +}; + +extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; + +/* sleep.S */ +extern void pxa25x_cpu_suspend(unsigned int); +extern void pxa27x_cpu_suspend(unsigned int); +extern void pxa_cpu_resume(void); + extern int pxa_pm_enter(suspend_state_t state); diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h index 94cb4982af82..2b0fe773213a 100644 --- a/include/asm-arm/arch-pxa/sharpsl.h +++ b/include/asm-arm/arch-pxa/sharpsl.h @@ -25,12 +25,6 @@ struct corgits_machinfo { /* * SharpSL Backlight */ -struct corgibl_machinfo { - int max_intensity; - int default_intensity; - int limit_mask; - void (*set_bl_intensity)(int intensity); -}; extern void corgibl_limit_intensity(int limit); diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h new file mode 100644 index 000000000000..1184d907b31e --- /dev/null +++ b/include/asm-arm/arch-s3c2400/map.h @@ -0,0 +1,66 @@ +/* linux/include/asm-arm/arch-s3c2400/map.h + * + * Copyright 2003,2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * Copyright 2003, Lucas Correia Villa Real + * + * S3C2400 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C2400_PA_MEMCTRL (0x14000000) +#define S3C2400_PA_USBHOST (0x14200000) +#define S3C2400_PA_IRQ (0x14400000) +#define S3C2400_PA_DMA (0x14600000) +#define S3C2400_PA_CLKPWR (0x14800000) +#define S3C2400_PA_LCD (0x14A00000) +#define S3C2400_PA_UART (0x15000000) +#define S3C2400_PA_TIMER (0x15100000) +#define S3C2400_PA_USBDEV (0x15200140) +#define S3C2400_PA_WATCHDOG (0x15300000) +#define S3C2400_PA_IIC (0x15400000) +#define S3C2400_PA_IIS (0x15508000) +#define S3C2400_PA_GPIO (0x15600000) +#define S3C2400_PA_RTC (0x15700040) +#define S3C2400_PA_ADC (0x15800000) +#define S3C2400_PA_SPI (0x15900000) + +#define S3C2400_PA_MMC (0x15A00000) +#define S3C2400_SZ_MMC SZ_1M + +/* physical addresses of all the chip-select areas */ + +#define S3C2400_CS0 (0x00000000) +#define S3C2400_CS1 (0x02000000) +#define S3C2400_CS2 (0x04000000) +#define S3C2400_CS3 (0x06000000) +#define S3C2400_CS4 (0x08000000) +#define S3C2400_CS5 (0x0A000000) +#define S3C2400_CS6 (0x0C000000) +#define S3C2400_CS7 (0x0E000000) + +#define S3C2400_SDRAM_PA (S3C2400_CS6) + +/* Use a single interface for common resources between S3C24XX cpus */ + +#define S3C24XX_PA_IRQ S3C2400_PA_IRQ +#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL +#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST +#define S3C24XX_PA_DMA S3C2400_PA_DMA +#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR +#define S3C24XX_PA_LCD S3C2400_PA_LCD +#define S3C24XX_PA_UART S3C2400_PA_UART +#define S3C24XX_PA_TIMER S3C2400_PA_TIMER +#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV +#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG +#define S3C24XX_PA_IIC S3C2400_PA_IIC +#define S3C24XX_PA_IIS S3C2400_PA_IIS +#define S3C24XX_PA_GPIO S3C2400_PA_GPIO +#define S3C24XX_PA_RTC S3C2400_PA_RTC +#define S3C24XX_PA_ADC S3C2400_PA_ADC +#define S3C24XX_PA_SPI S3C2400_PA_SPI diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h new file mode 100644 index 000000000000..fb0381dde704 --- /dev/null +++ b/include/asm-arm/arch-s3c2400/memory.h @@ -0,0 +1,23 @@ +/* linux/include/asm-arm/arch-s3c2400/memory.h + * from linux/include/asm-arm/arch-rpc/memory.h + * + * Copyright 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * Copyright (C) 1996,1997,1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x0C000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S index 93064860e0e5..9c8cd9abb82b 100644 --- a/include/asm-arm/arch-s3c2410/debug-macro.S +++ b/include/asm-arm/arch-s3c2410/debug-macro.S @@ -13,32 +13,23 @@ */ #include <asm/arch/map.h> -#include <asm/arch/regs-serial.h> #include <asm/arch/regs-gpio.h> +#include <asm/plat-s3c/regs-serial.h> #define S3C2410_UART1_OFF (0x4000) #define SHIFT_2440TXF (14-9) - .macro addruart, rx + .macro addruart, rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C24XX_PA_UART ldrne \rx, = S3C24XX_VA_UART -#if CONFIG_DEBUG_S3C2410_UART != 0 - add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART) +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) #endif - .endm + .endm - .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH ] - .endm - - .macro busyuart, rd, rx - ldr \rd, [ \rx, # S3C2410_UFCON ] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: + .macro fifo_full_s3c24xx rd, rx @ check for arm920 vs arm926. currently assume all arm926 @ devices have an 64 byte FIFO identical to the s3c2440 mrc p15, 0, \rd, c0, c0 @@ -57,25 +48,22 @@ ldr \rd, [ \rx, # S3C2410_UFSTAT ] moveq \rd, \rd, lsr #SHIFT_2440TXF tst \rd, #S3C2410_UFSTAT_TXFULL - bne 1003b - b 1002f - -1001: - @ busy waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b + .endm -1002: @ exit busyuart - .endm + .macro fifo_full_s3c2410 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + tst \rd, #S3C2410_UFSTAT_TXFULL + .endm - .macro waituart,rd,rx +/* fifo level reading */ - ldr \rd, [ \rx, # S3C2410_UFCON ] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: + .macro fifo_level_s3c24xx rd, rx + @ check for arm920 vs arm926. currently assume all arm926 + @ devices have an 64 byte FIFO identical to the s3c2440 + mrc p15, 0, \rd, c0, c0 + and \rd, \rd, #0xff0 + teq \rd, #0x260 + beq 10000f mrc p15, 0, \rd, c1, c0 tst \rd, #1 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) @@ -85,18 +73,32 @@ and \rd, \rd, #0x00ff0000 teq \rd, #0x00440000 @ is it 2440? +10000: ldr \rd, [ \rx, # S3C2410_UFSTAT ] andne \rd, \rd, #S3C2410_UFSTAT_TXMASK andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK - teq \rd, #0 - bne 1003b - b 1002f + .endm + + .macro fifo_level_s3c2410 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + and \rd, \rd, #S3C2410_UFSTAT_TXMASK + .endm + +/* Select the correct implementation depending on the configuration. The + * S3C2440 will get selected by default, as these are the most widely + * used variants of these +*/ + +#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) +#define fifo_full fifo_full_s3c2410 +#define fifo_level fifo_level_s3c2410 +#warning 2410only +#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) +#define fifo_full fifo_full_s3c24xx +#define fifo_level fifo_level_s3c24xx +#warning generic +#endif -1001: - @ idle waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b +/* include the reset of the code which will do the work */ -1002: @ exit busyuart - .endm +#include <asm/plat-s3c/debug-macro.S> diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h index 19e77f038042..b33ed3b05ef5 100644 --- a/include/asm-arm/arch-s3c2410/map.h +++ b/include/asm-arm/arch-s3c2410/map.h @@ -13,58 +13,36 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H -/* we have a bit of a tight squeeze to fit all our registers from - * 0xF00000000 upwards, since we use all of the nGCS space in some - * capacity, and also need to fit the S3C2410 registers in as well... - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - * - * Note, we are trying to remove some of these from the implementation - * as they are only useful to certain drivers... - */ - -#ifndef __ASSEMBLY__ -#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x)) -#else -#define S3C2410_ADDR(x) (0xF0000000 + (x)) -#endif +#include <asm/plat-s3c/map.h> -#define S3C2400_ADDR(x) S3C2410_ADDR(x) +#define S3C2410_ADDR(x) S3C_ADDR(x) /* interrupt controller is the first thing we put in, to make * the assembly code for the irq detection easier */ -#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) -#define S3C2400_PA_IRQ (0x14400000) +#define S3C24XX_VA_IRQ S3C_VA_IRQ #define S3C2410_PA_IRQ (0x4A000000) #define S3C24XX_SZ_IRQ SZ_1M /* memory controller registers */ -#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) -#define S3C2400_PA_MEMCTRL (0x14000000) +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM #define S3C2410_PA_MEMCTRL (0x48000000) #define S3C24XX_SZ_MEMCTRL SZ_1M /* USB host controller */ -#define S3C2400_PA_USBHOST (0x14200000) #define S3C2410_PA_USBHOST (0x49000000) #define S3C24XX_SZ_USBHOST SZ_1M /* DMA controller */ -#define S3C2400_PA_DMA (0x14600000) #define S3C2410_PA_DMA (0x4B000000) #define S3C24XX_SZ_DMA SZ_1M /* Clock and Power management */ -#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) -#define S3C2400_PA_CLKPWR (0x14800000) +#define S3C24XX_VA_CLKPWR S3C_VA_SYS #define S3C2410_PA_CLKPWR (0x4C000000) #define S3C24XX_SZ_CLKPWR SZ_1M /* LCD controller */ -#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000) -#define S3C2400_PA_LCD (0x14A00000) #define S3C2410_PA_LCD (0x4D000000) #define S3C24XX_SZ_LCD SZ_1M @@ -72,41 +50,30 @@ #define S3C2410_PA_NAND (0x4E000000) #define S3C24XX_SZ_NAND SZ_1M -/* MMC controller - available on the S3C2400 */ -#define S3C2400_PA_MMC (0x15A00000) -#define S3C2400_SZ_MMC SZ_1M - /* UARTs */ -#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) -#define S3C2400_PA_UART (0x15000000) +#define S3C24XX_VA_UART S3C_VA_UART #define S3C2410_PA_UART (0x50000000) #define S3C24XX_SZ_UART SZ_1M /* Timers */ -#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) -#define S3C2400_PA_TIMER (0x15100000) +#define S3C24XX_VA_TIMER S3C_VA_TIMER #define S3C2410_PA_TIMER (0x51000000) #define S3C24XX_SZ_TIMER SZ_1M /* USB Device port */ -#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000) -#define S3C2400_PA_USBDEV (0x15200140) #define S3C2410_PA_USBDEV (0x52000000) #define S3C24XX_SZ_USBDEV SZ_1M /* Watchdog */ -#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) -#define S3C2400_PA_WATCHDOG (0x15300000) +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG #define S3C2410_PA_WATCHDOG (0x53000000) #define S3C24XX_SZ_WATCHDOG SZ_1M /* IIC hardware controller */ -#define S3C2400_PA_IIC (0x15400000) #define S3C2410_PA_IIC (0x54000000) #define S3C24XX_SZ_IIC SZ_1M /* IIS controller */ -#define S3C2400_PA_IIS (0x15508000) #define S3C2410_PA_IIS (0x55000000) #define S3C24XX_SZ_IIS SZ_1M @@ -116,27 +83,23 @@ * it is the same distance apart from the UART in the * phsyical address space, as the initial mapping for the IO * is done as a 1:1 maping. This puts it (currently) at - * 0xF6800000, which is not in the way of any current mapping + * 0xFA800000, which is not in the way of any current mapping * by the base system. */ -#define S3C2400_PA_GPIO (0x15600000) #define S3C2410_PA_GPIO (0x56000000) #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) #define S3C24XX_SZ_GPIO SZ_1M /* RTC */ -#define S3C2400_PA_RTC (0x15700040) #define S3C2410_PA_RTC (0x57000000) #define S3C24XX_SZ_RTC SZ_1M /* ADC */ -#define S3C2400_PA_ADC (0x15800000) #define S3C2410_PA_ADC (0x58000000) #define S3C24XX_SZ_ADC SZ_1M /* SPI */ -#define S3C2400_PA_SPI (0x15900000) #define S3C2410_PA_SPI (0x59000000) #define S3C24XX_SZ_SPI SZ_1M @@ -177,37 +140,8 @@ #define S3C2410_SDRAM_PA (S3C2410_CS6) -#define S3C2400_CS0 (0x00000000) -#define S3C2400_CS1 (0x02000000) -#define S3C2400_CS2 (0x04000000) -#define S3C2400_CS3 (0x06000000) -#define S3C2400_CS4 (0x08000000) -#define S3C2400_CS5 (0x0A000000) -#define S3C2400_CS6 (0x0C000000) -#define S3C2400_CS7 (0x0E000000) - -#define S3C2400_SDRAM_PA (S3C2400_CS6) - /* Use a single interface for common resources between S3C24XX cpus */ -#ifdef CONFIG_CPU_S3C2400 -#define S3C24XX_PA_IRQ S3C2400_PA_IRQ -#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL -#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST -#define S3C24XX_PA_DMA S3C2400_PA_DMA -#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR -#define S3C24XX_PA_LCD S3C2400_PA_LCD -#define S3C24XX_PA_UART S3C2400_PA_UART -#define S3C24XX_PA_TIMER S3C2400_PA_TIMER -#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV -#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG -#define S3C24XX_PA_IIC S3C2400_PA_IIC -#define S3C24XX_PA_IIS S3C2400_PA_IIS -#define S3C24XX_PA_GPIO S3C2400_PA_GPIO -#define S3C24XX_PA_RTC S3C2400_PA_RTC -#define S3C24XX_PA_ADC S3C2400_PA_ADC -#define S3C24XX_PA_SPI S3C2400_PA_SPI -#else #define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST @@ -224,7 +158,6 @@ #define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_SPI S3C2410_PA_SPI -#endif /* deal with the registers that move under the 2412/2413 */ diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h index 4be6a74c4303..533e2436e707 100644 --- a/include/asm-arm/arch-s3c2410/memory.h +++ b/include/asm-arm/arch-s3c2410/memory.h @@ -11,20 +11,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -/* - * DRAM starts at 0x30000000 for S3C2410/S3C2440 - * and at 0x0C000000 for S3C2400 - */ -#ifdef CONFIG_CPU_S3C2400 -#define PHYS_OFFSET UL(0x0C000000) -#else #define PHYS_OFFSET UL(0x30000000) -#endif - -/* - * These are exactly the same on the S3C2410 as the - * physical memory view. -*/ #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h index b7faeb04c0ff..76fe5f693426 100644 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/include/asm-arm/arch-s3c2410/regs-lcd.h @@ -12,7 +12,7 @@ #ifndef ___ASM_ARCH_REGS_LCD_H #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" -#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD) +#define S3C2410_LCDREG(x) (x) /* LCD control registers */ #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 1c74ef17da33..63891786dfa0 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h @@ -17,7 +17,7 @@ #include <asm/arch/idle.h> #include <asm/arch/reset.h> -#include <asm/arch/regs-watchdog.h> +#include <asm/plat-s3c/regs-watchdog.h> #include <asm/arch/regs-clock.h> void (*s3c24xx_idle)(void); diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index dcb2cef38f50..48a5731ee988 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -1,6 +1,7 @@ /* linux/include/asm-arm/arch-s3c2410/uncompress.h * - * Copyright (c) 2003 Simtec Electronics + * Copyright (c) 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * * S3C2410 - uncompress code @@ -13,153 +14,39 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ - -/* defines for UART registers */ -#include "asm/arch/regs-serial.h" -#include "asm/arch/regs-gpio.h" -#include "asm/arch/regs-watchdog.h" - +#include <asm/arch/regs-gpio.h> #include <asm/arch/map.h> /* working in physical space... */ #undef S3C2410_GPIOREG -#undef S3C2410_WDOGREG - #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) -/* how many bytes we allow into the FIFO at a time in FIFO mode */ -#define FIFO_MAX (14) +#include <asm/plat-s3c/uncompress.h> -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT) - -static __inline__ void -uart_wr(unsigned int reg, unsigned int val) +static inline int is_arm926(void) { - volatile unsigned int *ptr; - - ptr = (volatile unsigned int *)(reg + uart_base); - *ptr = val; -} + unsigned int cpuid; -static __inline__ unsigned int -uart_rd(unsigned int reg) -{ - volatile unsigned int *ptr; + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); - ptr = (volatile unsigned int *)(reg + uart_base); - return *ptr; + return ((cpuid & 0xff0) == 0x260); } - -/* we can deal with the case the UARTs are being run - * in FIFO mode, so that we don't hold up our execution - * waiting for tx to happen... -*/ - -static void putc(int ch) +static void arch_detect_cpu(void) { - int cpuid = S3C2410_GSTATUS1_2410; + unsigned int cpuid; -#ifndef CONFIG_CPU_S3C2400 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); cpuid &= S3C2410_GSTATUS1_IDMASK; -#endif - - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { - int level; - - while (1) { - level = uart_rd(S3C2410_UFSTAT); - - if (cpuid == S3C2410_GSTATUS1_2440 || - cpuid == S3C2410_GSTATUS1_2442) { - level &= S3C2440_UFSTAT_TXMASK; - level >>= S3C2440_UFSTAT_TXSHIFT; - } else { - level &= S3C2410_UFSTAT_TXMASK; - level >>= S3C2410_UFSTAT_TXSHIFT; - } - - if (level < FIFO_MAX) - break; - } + if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || + cpuid == S3C2410_GSTATUS1_2442) { + fifo_mask = S3C2440_UFSTAT_TXMASK; + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; } else { - /* not using fifos */ - - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) - barrier(); + fifo_mask = S3C2410_UFSTAT_TXMASK; + fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; } - - /* write byte to transmission register */ - uart_wr(S3C2410_UTXH, ch); } -static inline void flush(void) -{ -} - -#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) - -/* CONFIG_S3C2410_BOOT_WATCHDOG - * - * Simple boot-time watchdog setup, to reboot the system if there is - * any problem with the boot process -*/ - -#ifdef CONFIG_S3C2410_BOOT_WATCHDOG - -#define WDOG_COUNT (0xff00) - -static inline void arch_decomp_wdog(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); -} - -static void arch_decomp_wdog_start(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTDAT); - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); -} - -#else -#define arch_decomp_wdog_start() -#define arch_decomp_wdog() -#endif - -#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET - -static void arch_decomp_error(const char *x) -{ - putstr("\n\n"); - putstr(x); - putstr("\n\n -- System resetting\n"); - - __raw_writel(0x4000, S3C2410_WTDAT); - __raw_writel(0x4000, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); - - while(1); -} - -#define arch_error arch_decomp_error -#endif - -static void error(char *err); - -static void -arch_decomp_setup(void) -{ - /* we may need to setup the uart(s) here if we are not running - * on an BAST... the BAST will have left the uarts configured - * after calling linux. - */ - - arch_decomp_wdog_start(); -} - - #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h new file mode 100644 index 000000000000..45d2bb59f9d0 --- /dev/null +++ b/include/asm-arm/arch-sa1100/jornada720.h @@ -0,0 +1,27 @@ +/* + * include/asm-arm/arch-sa1100/jornada720.h + * + * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728 + * + * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> + * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + /* HP Jornada 7xx microprocessor commands */ +#define GETBATTERYDATA 0xc0 +#define GETSCANKEYCODE 0x90 +#define GETTOUCHSAMPLES 0xa0 +#define GETCONTRAST 0xD0 +#define SETCONTRAST 0xD1 +#define GETBRIGHTNESS 0xD2 +#define SETBRIGHTNESS 0xD3 +#define CONTRASTOFF 0xD8 +#define BRIGHTNESSOFF 0xD9 +#define PWMOFF 0xDF +#define TXDUMMY 0x11 +#define ERRORCODE 0x00 diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index d1294a46c70c..6c1c968b2987 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -426,6 +426,13 @@ static inline void flush_anon_page(struct vm_area_struct *vma, */ #define flush_icache_page(vma,page) do { } while (0) +static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, + unsigned offset, size_t size) +{ + const void *start = (void __force *)virt + offset; + dmac_inv_range(start, start + size); +} + #define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) #define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29)) diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index d7a777f05088..ec1c685562ce 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -1,13 +1,14 @@ #ifndef __ASMARM_ELF_H #define __ASMARM_ELF_H +#include <asm/hwcap.h> + #ifndef __ASSEMBLY__ /* * ELF register definitions.. */ #include <asm/ptrace.h> #include <asm/user.h> -#include <asm/hwcap.h> typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h index 54b5ae44ed94..d595c15166a4 100644 --- a/include/asm-arm/floppy.h +++ b/include/asm-arm/floppy.h @@ -30,15 +30,21 @@ #define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) #define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) +static inline int fd_dma_setup(void *data, unsigned int length, + unsigned int mode, unsigned long addr) +{ + set_dma_mode(DMA_FLOPPY, mode); + __set_dma_addr(DMA_FLOPPY, data); + set_dma_count(DMA_FLOPPY, length); + virtual_dma_port = addr; + enable_dma(DMA_FLOPPY); + return 0; +} +#define fd_dma_setup fd_dma_setup + #define fd_request_dma() request_dma(DMA_FLOPPY,"floppy") #define fd_free_dma() free_dma(DMA_FLOPPY) #define fd_disable_dma() disable_dma(DMA_FLOPPY) -#define fd_enable_dma() enable_dma(DMA_FLOPPY) -#define fd_clear_dma_ff() clear_dma_ff(DMA_FLOPPY) -#define fd_set_dma_mode(mode) set_dma_mode(DMA_FLOPPY, (mode)) -#define fd_set_dma_addr(addr) set_dma_addr(DMA_FLOPPY, virt_to_bus((addr))) -#define fd_set_dma_count(len) set_dma_count(DMA_FLOPPY, (len)) -#define fd_cacheflush(addr,sz) /* need to clean up dma.h */ #define DMA_FLOPPYDISK DMA_FLOPPY diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 81ca5d3e2bff..fb90b421f31c 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -194,6 +194,13 @@ extern int init_atu; #define IOP_TMR_PRIVILEGED 0x08 #define IOP_TMR_RATIO_1_1 0x00 +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +/* iop3xx does not support stopping the watchdog, so we just re-arm */ +#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM) +#define IOP_WDTCR_DIS (IOP_WDTCR_EN) + /* Application accelerator unit */ #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) @@ -274,6 +281,32 @@ static inline void write_tisr(u32 val) asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); } +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); +} + +extern unsigned long get_iop_tick_rate(void); + +/* only iop13xx has these registers, we define these to present a + * common register interface for the iop_wdt driver. + */ +#define IOP_RCSR_WDT (0) +static inline u32 read_rcsr(void) +{ + return 0; +} +static inline void write_wdtsr(u32 val) +{ + do { } while (0); +} + extern struct platform_device iop3xx_dma_0_channel; extern struct platform_device iop3xx_dma_1_channel; extern struct platform_device iop3xx_aau_channel; diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h index 0c8be19fd66b..33c83dd87965 100644 --- a/include/asm-arm/pgtable-nommu.h +++ b/include/asm-arm/pgtable-nommu.h @@ -74,7 +74,6 @@ static inline int pte_file(pte_t pte) { return 0; } * These would be in other places but having them here reduces the diffs. */ extern unsigned int kobjsize(const void *objp); -extern int is_in_rom(unsigned long); /* * No page table caches to initialise. @@ -102,7 +101,8 @@ extern int is_in_rom(unsigned long); #define v4_tlb_fns (0) #define v4wb_tlb_fns (0) #define v4wbi_tlb_fns (0) -#define v6_tlb_fns (0) +#define v6wbi_tlb_fns (0) +#define v7wbi_tlb_fns (0) #define v3_user_fns (0) #define v4_user_fns (0) diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S new file mode 100644 index 000000000000..84c40b847da8 --- /dev/null +++ b/include/asm-arm/plat-s3c/debug-macro.S @@ -0,0 +1,75 @@ +/* linux/include/asm-arm/plat-s3c/debug-macro.S + * + * Copyright 2005, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <asm/plat-s3c/regs-serial.h> + +/* The S3C2440 implementations are used by default as they are the + * most widely re-used */ + + .macro fifo_level_s3c2440 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + and \rd, \rd, #S3C2440_UFSTAT_TXMASK + .endm + +#ifndef fifo_level +#define fifo_level fifo_level_s3c2410 +#endif + + .macro fifo_full_s3c2440 rd, rx + ldr \rd, [ \rx, # S3C2410_UFSTAT ] + tst \rd, #S3C2440_UFSTAT_TXFULL + .endm + +#ifndef fifo_full +#define fifo_full fifo_full_s3c2440 +#endif + + .macro senduart,rd,rx + strb \rd, [\rx, # S3C2410_UTXH ] + .endm + + .macro busyuart, rd, rx + ldr \rd, [ \rx, # S3C2410_UFCON ] + tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? + beq 1001f @ + @ FIFO enabled... +1003: + fifo_full \rd, \rx + bne 1003b + b 1002f + +1001: + @ busy waiting for non fifo + ldr \rd, [ \rx, # S3C2410_UTRSTAT ] + tst \rd, #S3C2410_UTRSTAT_TXFE + beq 1001b + +1002: @ exit busyuart + .endm + + .macro waituart,rd,rx + ldr \rd, [ \rx, # S3C2410_UFCON ] + tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? + beq 1001f @ + @ FIFO enabled... +1003: + fifo_level \rd, \rx + teq \rd, #0 + bne 1003b + b 1002f +1001: + @ idle waiting for non fifo + ldr \rd, [ \rx, # S3C2410_UTRSTAT ] + tst \rd, #S3C2410_UTRSTAT_TXFE + beq 1001b + +1002: @ exit busyuart + .endm diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/plat-s3c/iic.h index 71211c8b5384..71211c8b5384 100644 --- a/include/asm-arm/arch-s3c2410/iic.h +++ b/include/asm-arm/plat-s3c/iic.h diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h new file mode 100644 index 000000000000..b84289d32a54 --- /dev/null +++ b/include/asm-arm/plat-s3c/map.h @@ -0,0 +1,40 @@ +/* linux/include/asm-arm/plat-s3c/map.h + * + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - Memory map definitions (virtual addresses) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_MAP_H +#define __ASM_PLAT_MAP_H __FILE__ + +/* Fit all our registers in at 0xF4000000 upwards, trying to use as + * little of the VA space as possible so vmalloc and friends have a + * better chance of getting memory. + * + * we try to ensure stuff like the IRQ registers are available for + * an single MOVS instruction (ie, only 8 bits of set data) + */ + +#define S3C_ADDR_BASE (0xF4000000) + +#ifndef __ASSEMBLY__ +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#else +#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) +#endif + +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ + +#endif /* __ASM_PLAT_MAP_H */ diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/plat-s3c/nand.h index 8816f7f9cee1..8816f7f9cee1 100644 --- a/include/asm-arm/arch-s3c2410/nand.h +++ b/include/asm-arm/plat-s3c/nand.h diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h index b004dee6bcaf..b004dee6bcaf 100644 --- a/include/asm-arm/arch-s3c2410/regs-ac97.h +++ b/include/asm-arm/plat-s3c/regs-ac97.h diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h index c7f231963e76..c7f231963e76 100644 --- a/include/asm-arm/arch-s3c2410/regs-adc.h +++ b/include/asm-arm/plat-s3c/regs-adc.h diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h index 2ae29522f253..2ae29522f253 100644 --- a/include/asm-arm/arch-s3c2410/regs-iic.h +++ b/include/asm-arm/plat-s3c/regs-iic.h diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h index b824d371ae0b..b824d371ae0b 100644 --- a/include/asm-arm/arch-s3c2410/regs-nand.h +++ b/include/asm-arm/plat-s3c/regs-nand.h diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h index 93b03c49710a..93b03c49710a 100644 --- a/include/asm-arm/arch-s3c2410/regs-rtc.h +++ b/include/asm-arm/plat-s3c/regs-rtc.h diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h index 8946702a87f5..923e114db663 100644 --- a/include/asm-arm/arch-s3c2410/regs-serial.h +++ b/include/asm-arm/plat-s3c/regs-serial.h @@ -32,10 +32,10 @@ #ifndef __ASM_ARM_REGS_SERIAL_H #define __ASM_ARM_REGS_SERIAL_H -#define S3C24XX_VA_UART0 (S3C24XX_VA_UART) -#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) -#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) -#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 ) +#define S3C24XX_VA_UART0 (S3C_VA_UART) +#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) +#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) +#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) #define S3C2410_PA_UART0 (S3C24XX_PA_UART) #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h index 6f8fe432fe3a..8b0d594397b1 100644 --- a/include/asm-arm/arch-s3c2410/regs-timer.h +++ b/include/asm-arm/plat-s3c/regs-timer.h @@ -14,12 +14,12 @@ #ifndef __ASM_ARCH_REGS_TIMER_H #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $" -#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x)) -#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c)) +#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) +#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) -#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00) -#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04) -#define S3C2410_TCON S3C2410_TIMERREG(0x08) +#define S3C2410_TCFG0 S3C_TIMERREG(0x00) +#define S3C2410_TCFG1 S3C_TIMERREG(0x04) +#define S3C2410_TCON S3C_TIMERREG(0x08) #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) @@ -71,9 +71,9 @@ /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ -#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00) -#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04) -#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) +#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) +#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) +#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) #define S3C2410_TCON_T4RELOAD (1<<22) #define S3C2410_TCON_T4MANUALUPD (1<<21) diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h index a9c5d491bdb6..56c4193b7a46 100644 --- a/include/asm-arm/arch-s3c2410/regs-watchdog.h +++ b/include/asm-arm/plat-s3c/regs-watchdog.h @@ -14,11 +14,11 @@ #ifndef __ASM_ARCH_REGS_WATCHDOG_H #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" -#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG) +#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) -#define S3C2410_WTCON S3C2410_WDOGREG(0x00) -#define S3C2410_WTDAT S3C2410_WDOGREG(0x04) -#define S3C2410_WTCNT S3C2410_WDOGREG(0x08) +#define S3C2410_WTCON S3C_WDOGREG(0x00) +#define S3C2410_WTDAT S3C_WDOGREG(0x04) +#define S3C2410_WTCNT S3C_WDOGREG(0x08) /* the watchdog can either generate a reset pulse, or an * interrupt. diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h new file mode 100644 index 000000000000..b5e6208175d1 --- /dev/null +++ b/include/asm-arm/plat-s3c/uncompress.h @@ -0,0 +1,155 @@ +/* linux/include/asm-arm/plat-s3c/uncompress.h + * + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_UNCOMPRESS_H +#define __ASM_PLAT_UNCOMPRESS_H + +typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ + +/* uart setup */ + +static unsigned int fifo_mask; +static unsigned int fifo_max; + +/* forward declerations */ + +static void arch_detect_cpu(void); + +/* defines for UART registers */ + +#include "asm/plat-s3c/regs-serial.h" +#include "asm/plat-s3c/regs-watchdog.h" + +/* working in physical space... */ +#undef S3C2410_WDOGREG +#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) + +/* how many bytes we allow into the FIFO at a time in FIFO mode */ +#define FIFO_MAX (14) + +#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT) + +static __inline__ void +uart_wr(unsigned int reg, unsigned int val) +{ + volatile unsigned int *ptr; + + ptr = (volatile unsigned int *)(reg + uart_base); + *ptr = val; +} + +static __inline__ unsigned int +uart_rd(unsigned int reg) +{ + volatile unsigned int *ptr; + + ptr = (volatile unsigned int *)(reg + uart_base); + return *ptr; +} + +/* we can deal with the case the UARTs are being run + * in FIFO mode, so that we don't hold up our execution + * waiting for tx to happen... +*/ + +static void putc(int ch) +{ + if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { + int level; + + while (1) { + level = uart_rd(S3C2410_UFSTAT); + level &= fifo_mask; + + if (level < fifo_max) + break; + } + + } else { + /* not using fifos */ + + while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) + barrier(); + } + + /* write byte to transmission register */ + uart_wr(S3C2410_UTXH, ch); +} + +static inline void flush(void) +{ +} + +#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) + +/* CONFIG_S3C_BOOT_WATCHDOG + * + * Simple boot-time watchdog setup, to reboot the system if there is + * any problem with the boot process +*/ + +#ifdef CONFIG_S3C_BOOT_WATCHDOG + +#define WDOG_COUNT (0xff00) + +static inline void arch_decomp_wdog(void) +{ + __raw_writel(WDOG_COUNT, S3C2410_WTCNT); +} + +static void arch_decomp_wdog_start(void) +{ + __raw_writel(WDOG_COUNT, S3C2410_WTDAT); + __raw_writel(WDOG_COUNT, S3C2410_WTCNT); + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); +} + +#else +#define arch_decomp_wdog_start() +#define arch_decomp_wdog() +#endif + +#ifdef CONFIG_S3C_BOOT_ERROR_RESET + +static void arch_decomp_error(const char *x) +{ + putstr("\n\n"); + putstr(x); + putstr("\n\n -- System resetting\n"); + + __raw_writel(0x4000, S3C2410_WTDAT); + __raw_writel(0x4000, S3C2410_WTCNT); + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); + + while(1); +} + +#define arch_error arch_decomp_error +#endif + +static void error(char *err); + +static void +arch_decomp_setup(void) +{ + /* we may need to setup the uart(s) here if we are not running + * on an BAST... the BAST will have left the uarts configured + * after calling linux. + */ + + arch_detect_cpu(); + arch_decomp_wdog_start(); +} + + +#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h index eaf77916a602..eaf77916a602 100644 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ b/include/asm-arm/plat-s3c24xx/regs-iis.h diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h index 4a499a138256..4a499a138256 100644 --- a/include/asm-arm/arch-s3c2410/regs-spi.h +++ b/include/asm-arm/plat-s3c24xx/regs-spi.h diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h index e1e9805d2d9a..e1e9805d2d9a 100644 --- a/include/asm-arm/arch-s3c2410/regs-udc.h +++ b/include/asm-arm/plat-s3c24xx/regs-udc.h diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/plat-s3c24xx/udc.h index b8aa6cb69b58..b8aa6cb69b58 100644 --- a/include/asm-arm/arch-s3c2410/udc.h +++ b/include/asm-arm/plat-s3c24xx/udc.h diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 6f8e6a69dc5f..94ea8c6dc1a4 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -254,16 +254,6 @@ do { \ last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ } while (0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) /* * On the StrongARM, "swp" is terminally broken since it bypasses the diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index eae85b09db2e..41784357a204 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -24,7 +24,6 @@ struct task_struct; struct exec_domain; -#include <asm/ptrace.h> #include <asm/types.h> #include <asm/domain.h> @@ -135,22 +134,19 @@ extern void iwmmxt_task_switch(struct thread_info *); /* * thread information flags: * TIF_SYSCALL_TRACE - syscall trace active - * TIF_NOTIFY_RESUME - resumption notification requested * TIF_SIGPENDING - signal pending * TIF_NEED_RESCHED - rescheduling necessary * TIF_USEDFPU - FPU was used by this task this quantum (SMP) * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_NOTIFY_RESUME 0 -#define TIF_SIGPENDING 1 -#define TIF_NEED_RESCHED 2 +#define TIF_SIGPENDING 0 +#define TIF_NEED_RESCHED 1 #define TIF_SYSCALL_TRACE 8 #define TIF_POLLING_NRFLAG 16 #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 #define TIF_FREEZE 19 -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h index 795b9e5b9e6a..8431f6eed5c6 100644 --- a/include/asm-arm/unaligned.h +++ b/include/asm-arm/unaligned.h @@ -60,24 +60,24 @@ extern int __bug_unaligned_x(const void *ptr); __get_unaligned_4_be((__p+4))) #define __get_unaligned_le(ptr) \ - ({ \ + ((__force typeof(*(ptr)))({ \ const __u8 *__p = (const __u8 *)(ptr); \ __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \ __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_le(__p), \ __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_le(__p), \ __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_le(__p), \ (void)__bug_unaligned_x(__p))))); \ - }) + })) #define __get_unaligned_be(ptr) \ - ({ \ + ((__force typeof(*(ptr)))({ \ const __u8 *__p = (const __u8 *)(ptr); \ __builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \ __builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_be(__p), \ __builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_be(__p), \ __builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_be(__p), \ (void)__bug_unaligned_x(__p))))); \ - }) + })) static inline void __put_unaligned_2_le(__u32 __v, register __u8 *__p) @@ -131,15 +131,16 @@ static inline void __put_unaligned_8_be(const unsigned long long __v, register _ */ #define __put_unaligned_le(val,ptr) \ ({ \ + (void)sizeof(*(ptr) = (val)); \ switch (sizeof(*(ptr))) { \ case 1: \ *(ptr) = (val); \ break; \ - case 2: __put_unaligned_2_le((val),(__u8 *)(ptr)); \ + case 2: __put_unaligned_2_le((__force u16)(val),(__u8 *)(ptr)); \ break; \ - case 4: __put_unaligned_4_le((val),(__u8 *)(ptr)); \ + case 4: __put_unaligned_4_le((__force u32)(val),(__u8 *)(ptr)); \ break; \ - case 8: __put_unaligned_8_le((val),(__u8 *)(ptr)); \ + case 8: __put_unaligned_8_le((__force u64)(val),(__u8 *)(ptr)); \ break; \ default: __bug_unaligned_x(ptr); \ break; \ @@ -149,15 +150,16 @@ static inline void __put_unaligned_8_be(const unsigned long long __v, register _ #define __put_unaligned_be(val,ptr) \ ({ \ + (void)sizeof(*(ptr) = (val)); \ switch (sizeof(*(ptr))) { \ case 1: \ *(ptr) = (val); \ break; \ - case 2: __put_unaligned_2_be((val),(__u8 *)(ptr)); \ + case 2: __put_unaligned_2_be((__force u16)(val),(__u8 *)(ptr)); \ break; \ - case 4: __put_unaligned_4_be((val),(__u8 *)(ptr)); \ + case 4: __put_unaligned_4_be((__force u32)(val),(__u8 *)(ptr)); \ break; \ - case 8: __put_unaligned_8_be((val),(__u8 *)(ptr)); \ + case 8: __put_unaligned_8_be((__force u64)(val),(__u8 *)(ptr)); \ break; \ default: __bug_unaligned_x(ptr); \ break; \ diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index bfdbebebdc1b..d327b25c986c 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -441,7 +441,6 @@ /* * Unimplemented (or alternatively implemented) syscalls */ -#define __IGNORE_sync_file_range 1 #define __IGNORE_fadvise64_64 1 #endif /* __KERNEL__ */ diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h index 14c5e0946c47..bd6be9d7f772 100644 --- a/include/asm-arm/vfp.h +++ b/include/asm-arm/vfp.h @@ -26,8 +26,8 @@ #define FPSID_REV_MASK (0xF << FPSID_REV_BIT) /* FPEXC bits */ -#define FPEXC_EXCEPTION (1<<31) -#define FPEXC_ENABLE (1<<30) +#define FPEXC_EX (1 << 31) +#define FPEXC_EN (1 << 30) /* FPSCR bits */ #define FPSCR_DEFAULT_NAN (1<<25) diff --git a/include/asm-arm26/a.out.h b/include/asm-arm26/a.out.h deleted file mode 100644 index 9b2702c42c87..000000000000 --- a/include/asm-arm26/a.out.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __ARM_A_OUT_H__ -#define __ARM_A_OUT_H__ - -#include <linux/personality.h> -#include <asm/types.h> - -struct exec -{ - __u32 a_info; /* Use macros N_MAGIC, etc for access */ - __u32 a_text; /* length of text, in bytes */ - __u32 a_data; /* length of data, in bytes */ - __u32 a_bss; /* length of uninitialized data area for file, in bytes */ - __u32 a_syms; /* length of symbol table data in file, in bytes */ - __u32 a_entry; /* start address */ - __u32 a_trsize; /* length of relocation info for text, in bytes */ - __u32 a_drsize; /* length of relocation info for data, in bytes */ -}; - -/* - * This is always the same - */ -#define N_TXTADDR(a) (0x00008000) - -#define N_TRSIZE(a) ((a).a_trsize) -#define N_DRSIZE(a) ((a).a_drsize) -#define N_SYMSIZE(a) ((a).a_syms) - -#define M_ARM 103 - -#ifdef __KERNEL__ -#define STACK_TOP TASK_SIZE -#endif - -#ifndef LIBRARY_START_TEXT -#define LIBRARY_START_TEXT (0x00c00000) -#endif - -#endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-arm26/assembler.h b/include/asm-arm26/assembler.h deleted file mode 100644 index bb507a9a4a55..000000000000 --- a/include/asm-arm26/assembler.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * linux/include/asm-arm26/assembler.h - * - * This file contains arm architecture specific defines - * for the different processors. - * - * Do not include any C declarations in this file - it is included by - * assembler source. - */ -#ifndef __ASSEMBLY__ -#error "Only include this from assembly code" -#endif - -/* - * Endian independent macros for shifting bytes within registers. - */ -#define pull lsr -#define push lsl -#define byte(x) (x*8) - -#ifdef __STDC__ -#define LOADREGS(cond, base, reglist...)\ - ldm##cond base,reglist^ - -#define RETINSTR(instr, regs...)\ - instr##s regs -#else -#define LOADREGS(cond, base, reglist...)\ - ldm/**/cond base,reglist^ - -#define RETINSTR(instr, regs...)\ - instr/**/s regs -#endif - -#define MODENOP\ - mov r0, r0 - -#define MODE(savereg,tmpreg,mode) \ - mov savereg, pc; \ - bic tmpreg, savereg, $0x0c000003; \ - orr tmpreg, tmpreg, $mode; \ - teqp tmpreg, $0 - -#define RESTOREMODE(savereg) \ - teqp savereg, $0 - -#define SAVEIRQS(tmpreg) - -#define RESTOREIRQS(tmpreg) - -#define DISABLEIRQS(tmpreg)\ - teqp pc, $0x08000003 - -#define ENABLEIRQS(tmpreg)\ - teqp pc, $0x00000003 - -#define USERMODE(tmpreg)\ - teqp pc, $0x00000000;\ - mov r0, r0 - -#define SVCMODE(tmpreg)\ - teqp pc, $0x00000003;\ - mov r0, r0 - - -/* - * Save the current IRQ state and disable IRQs - * Note that this macro assumes FIQs are enabled, and - * that the processor is in SVC mode. - */ - .macro save_and_disable_irqs, oldcpsr, temp - mov \oldcpsr, pc - orr \temp, \oldcpsr, #0x08000000 - teqp \temp, #0 - .endm - -/* - * Restore interrupt state previously stored in - * a register - * ** Actually do nothing on Arc - hope that the caller uses a MOVS PC soon - * after! - */ - .macro restore_irqs, oldcpsr - @ This be restore_irqs - .endm - -/* - * These two are used to save LR/restore PC over a user-based access. - * The old 26-bit architecture requires that we save lr (R14) - */ - .macro save_lr - str lr, [sp, #-4]! - .endm - - .macro restore_pc - ldmfd sp!, {pc}^ - .endm - -#define USER(x...) \ -9999: x; \ - .section __ex_table,"a"; \ - .align 3; \ - .long 9999b,9001f; \ - .previous - - diff --git a/include/asm-arm26/atomic.h b/include/asm-arm26/atomic.h deleted file mode 100644 index d6dd42374cf3..000000000000 --- a/include/asm-arm26/atomic.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * linux/include/asm-arm26/atomic.h - * - * Copyright (c) 1996 Russell King. - * Modified for arm26 by Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 25-11-2004 IM Updated for 2.6.9 - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - * - * FIXME - its probably worth seeing what these compile into... - */ -#ifndef __ASM_ARM_ATOMIC_H -#define __ASM_ARM_ATOMIC_H - -#ifdef CONFIG_SMP -#error SMP is NOT supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ -#include <asm/system.h> - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline int atomic_add_return(int i, atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val; -} - -static inline int atomic_sub_return(int i, atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= i; - local_irq_restore(flags); - - return val; -} - -static inline int atomic_cmpxchg(atomic_t *v, int old, int new) -{ - int ret; - unsigned long flags; - - local_irq_save(flags); - ret = v->counter; - if (likely(ret == old)) - v->counter = new; - local_irq_restore(flags); - - return ret; -} - -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -static inline int atomic_add_unless(atomic_t *v, int a, int u) -{ - int ret; - unsigned long flags; - - local_irq_save(flags); - ret = v->counter; - if (ret != u) - v->counter += a; - local_irq_restore(flags); - - return ret != u; -} -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -#define atomic_add(i, v) (void) atomic_add_return(i, v) -#define atomic_inc(v) (void) atomic_add_return(1, v) -#define atomic_sub(i, v) (void) atomic_sub_return(i, v) -#define atomic_dec(v) (void) atomic_sub_return(1, v) - -#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) -#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) -#define atomic_inc_return(v) (atomic_add_return(1, v)) -#define atomic_dec_return(v) (atomic_sub_return(1, v)) - -#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) - -/* Atomic operations are already serializing on ARM26 */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#include <asm-generic/atomic.h> -#endif -#endif diff --git a/include/asm-arm26/auxvec.h b/include/asm-arm26/auxvec.h deleted file mode 100644 index c0536f6b29a7..000000000000 --- a/include/asm-arm26/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMARM_AUXVEC_H -#define __ASMARM_AUXVEC_H - -#endif diff --git a/include/asm-arm26/bitops.h b/include/asm-arm26/bitops.h deleted file mode 100644 index 19a69573a654..000000000000 --- a/include/asm-arm26/bitops.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright 1995, Russell King. - * - * Based on the arm32 version by RMK (and others). Their copyrights apply to - * Those parts. - * Modified for arm26 by Ian Molton on 25/11/04 - * - * bit 0 is the LSB of an "unsigned long" quantity. - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require privileged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_ARM_BITOPS_H -#define __ASM_ARM_BITOPS_H - -#ifdef __KERNEL__ - -#include <linux/compiler.h> -#include <asm/system.h> - -#define smp_mb__before_clear_bit() do { } while (0) -#define smp_mb__after_clear_bit() do { } while (0) - -/* - * These functions are the basis of our bit ops. - * - * First, the atomic bitops. These use native endian. - */ -static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - *p |= mask; - local_irq_restore(flags); -} - -static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - *p &= ~mask; - local_irq_restore(flags); -} - -static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - *p ^= mask; - local_irq_restore(flags); -} - -static inline int -____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned int res; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - res = *p; - *p = res | mask; - local_irq_restore(flags); - - return res & mask; -} - -static inline int -____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned int res; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - res = *p; - *p = res & ~mask; - local_irq_restore(flags); - - return res & mask; -} - -static inline int -____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) -{ - unsigned long flags; - unsigned int res; - unsigned long mask = 1UL << (bit & 31); - - p += bit >> 5; - - local_irq_save(flags); - res = *p; - *p = res ^ mask; - local_irq_restore(flags); - - return res & mask; -} - -#include <asm-generic/bitops/non-atomic.h> - -/* - * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. - */ -extern void _set_bit_le(int nr, volatile unsigned long * p); -extern void _clear_bit_le(int nr, volatile unsigned long * p); -extern void _change_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_set_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p); -extern int _test_and_change_bit_le(int nr, volatile unsigned long * p); -extern int _find_first_zero_bit_le(const unsigned long * p, unsigned size); -extern int _find_next_zero_bit_le(void * p, int size, int offset); -extern int _find_first_bit_le(const unsigned long *p, unsigned size); -extern int _find_next_bit_le(const unsigned long *p, int size, int offset); - -/* - * The __* form of bitops are non-atomic and may be reordered. - */ -#define ATOMIC_BITOP_LE(name,nr,p) \ - (__builtin_constant_p(nr) ? \ - ____atomic_##name(nr, p) : \ - _##name##_le(nr,p)) - -#define NONATOMIC_BITOP(name,nr,p) \ - (____nonatomic_##name(nr, p)) - -/* - * These are the little endian, atomic definitions. - */ -#define set_bit(nr,p) ATOMIC_BITOP_LE(set_bit,nr,p) -#define clear_bit(nr,p) ATOMIC_BITOP_LE(clear_bit,nr,p) -#define change_bit(nr,p) ATOMIC_BITOP_LE(change_bit,nr,p) -#define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p) -#define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p) -#define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p) -#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) -#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) -#define find_first_bit(p,sz) _find_first_bit_le(p,sz) -#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) - -#define WORD_BITOFF_TO_LE(x) ((x)) - -#include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/hweight.h> - -/* - * Ext2 is defined to use little-endian byte ordering. - * These do not need to be atomic. - */ -#define ext2_set_bit(nr,p) \ - __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_set_bit_atomic(lock,nr,p) \ - test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_clear_bit(nr,p) \ - __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_clear_bit_atomic(lock,nr,p) \ - test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_test_bit(nr,p) \ - test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define ext2_find_first_zero_bit(p,sz) \ - _find_first_zero_bit_le(p,sz) -#define ext2_find_next_zero_bit(p,sz,off) \ - _find_next_zero_bit_le(p,sz,off) - -/* - * Minix is defined to use little-endian byte ordering. - * These do not need to be atomic. - */ -#define minix_set_bit(nr,p) \ - __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_bit(nr,p) \ - test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_and_set_bit(nr,p) \ - __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_test_and_clear_bit(nr,p) \ - __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p)) -#define minix_find_first_zero_bit(p,sz) \ - _find_first_zero_bit_le((unsigned long *)(p),sz) - -#endif /* __KERNEL__ */ - -#endif /* _ARM_BITOPS_H */ diff --git a/include/asm-arm26/bug.h b/include/asm-arm26/bug.h deleted file mode 100644 index 8545d58b0475..000000000000 --- a/include/asm-arm26/bug.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASMARM_BUG_H -#define _ASMARM_BUG_H - - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -extern volatile void __bug(const char *file, int line, void *data); -/* give file/line information */ -#define BUG() __bug(__FILE__, __LINE__, NULL) -#else -#define BUG() (*(int *)0 = 0) -#endif - -#define HAVE_ARCH_BUG -#endif - -#include <asm-generic/bug.h> - -#endif diff --git a/include/asm-arm26/bugs.h b/include/asm-arm26/bugs.h deleted file mode 100644 index e99ac2e46d7f..000000000000 --- a/include/asm-arm26/bugs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * linux/include/asm-arm26/bugs.h - * - * Copyright (C) 1995 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_BUGS_H -#define __ASM_BUGS_H - -#define check_bugs() cpu_check_bugs() - -#endif diff --git a/include/asm-arm26/byteorder.h b/include/asm-arm26/byteorder.h deleted file mode 100644 index 0b4af9ac76e9..000000000000 --- a/include/asm-arm26/byteorder.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include <linux/byteorder/little_endian.h> - -#endif - diff --git a/include/asm-arm26/cache.h b/include/asm-arm26/cache.h deleted file mode 100644 index 8c3abcf728fe..000000000000 --- a/include/asm-arm26/cache.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * linux/include/asm-arm26/cache.h - */ -#ifndef __ASMARM_CACHE_H -#define __ASMARM_CACHE_H - -#define L1_CACHE_SHIFT 5 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#endif diff --git a/include/asm-arm26/cacheflush.h b/include/asm-arm26/cacheflush.h deleted file mode 100644 index 14ae15b6faab..000000000000 --- a/include/asm-arm26/cacheflush.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * linux/include/asm-arm/cacheflush.h - * - * Copyright (C) 2000-2002 Russell King - * Copyright (C) 2003 Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ARM26 cache 'functions' - * - */ - -#ifndef _ASMARM_CACHEFLUSH_H -#define _ASMARM_CACHEFLUSH_H - -#if 1 //FIXME - BAD INCLUDES!!! -#include <linux/sched.h> -#include <linux/mm.h> -#endif - -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma,start,end) do { } while (0) -#define flush_cache_page(vma,vmaddr,pfn) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define invalidate_dcache_range(start,end) do { } while (0) -#define clean_dcache_range(start,end) do { } while (0) -#define flush_dcache_range(start,end) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define clean_dcache_entry(_s) do { } while (0) -#define clean_cache_entry(_start) do { } while (0) - -#define flush_icache_user_range(start,end, bob, fred) do { } while (0) -#define flush_icache_range(start,end) do { } while (0) -#define flush_icache_page(vma,page) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -/* DAG: ARM3 will flush cache on MEMC updates anyway? so don't bother */ -/* IM : Yes, it will, but only if setup to do so (we do this). */ -#define clean_cache_area(_start,_size) do { } while (0) - -#endif diff --git a/include/asm-arm26/checksum.h b/include/asm-arm26/checksum.h deleted file mode 100644 index f2b4b0a403bd..000000000000 --- a/include/asm-arm26/checksum.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * linux/include/asm-arm/checksum.h - * - * IP checksum routines - * - * Copyright (C) Original authors of ../asm-i386/checksum.h - * Copyright (C) 1996-1999 Russell King - */ -#ifndef __ASM_ARM_CHECKSUM_H -#define __ASM_ARM_CHECKSUM_H - -#include <linux/in6.h> - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -/* - * the same as csum_partial, but copies from src while it - * checksums, and handles user-space pointer exceptions correctly, when needed. - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -__wsum -csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum); - -__wsum -csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *err_ptr); - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - */ -static inline __sum16 -ip_fast_csum(const void *iph, unsigned int ihl) -{ - unsigned int sum, tmp1; - - __asm__ __volatile__( - "ldr %0, [%1], #4 @ ip_fast_csum \n\ - ldr %3, [%1], #4 \n\ - sub %2, %2, #5 \n\ - adds %0, %0, %3 \n\ - ldr %3, [%1], #4 \n\ - adcs %0, %0, %3 \n\ - ldr %3, [%1], #4 \n\ -1: adcs %0, %0, %3 \n\ - ldr %3, [%1], #4 \n\ - tst %2, #15 @ do this carefully \n\ - subne %2, %2, #1 @ without destroying \n\ - bne 1b @ the carry flag \n\ - adcs %0, %0, %3 \n\ - adc %0, %0, #0 \n\ - adds %0, %0, %0, lsl #16 \n\ - addcs %0, %0, #0x10000 \n\ - mvn %0, %0 \n\ - mov %0, %0, lsr #16" - : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1) - : "1" (iph), "2" (ihl) - : "cc"); - return (__force __sum16)sum; -} - -/* - * Fold a partial checksum without adding pseudo headers - */ -static inline __sum16 csum_fold(__wsum sum) -{ - __asm__( - "adds %0, %1, %1, lsl #16 @ csum_fold \n\ - addcs %0, %0, #0x10000" - : "=r" (sum) - : "r" (sum) - : "cc"); - return (__force __sum16)(~(__force u32)sum >> 16); -} - -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - __asm__( - "adds %0, %1, %2 @ csum_tcpudp_nofold \n\ - adcs %0, %0, %3 \n\ - adcs %0, %0, %4 \n\ - adcs %0, %0, %5 \n\ - adc %0, %0, #0" - : "=&r"(sum) - : "r" (sum), "r" (daddr), "r" (saddr), "r" (htons(len)), "Ir" (htons(proto)) - : "cc"); - return sum; -} -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ -static inline __sum16 -csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - __asm__( - "adds %0, %1, %2 @ csum_tcpudp_magic \n\ - adcs %0, %0, %3 \n\ - adcs %0, %0, %4 \n\ - adcs %0, %0, %5 \n\ - adc %0, %0, #0 \n\ - adds %0, %0, %0, lsl #16 \n\ - addcs %0, %0, #0x10000 \n\ - mvn %0, %0" - : "=&r"(sum) - : "r" (sum), "r" (daddr), "r" (saddr), "r" (htons(len)), "Ir" (htons(proto)) - : "cc"); - return (__force __sum16)((__force u32)sum >> 16); -} - - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ -static inline __sum16 -ip_compute_csum(const void *buff, int len) -{ - return csum_fold(csum_partial(buff, len, 0)); -} - -#define _HAVE_ARCH_IPV6_CSUM -extern __wsum -__csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __be32 len, - __be32 proto, __wsum sum); - -static inline __sum16 -csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __u32 len, - unsigned short proto, __wsum sum) -{ - return csum_fold(__csum_ipv6_magic(saddr, daddr, htonl(len), - htonl(proto), sum)); -} -#endif diff --git a/include/asm-arm26/constants.h b/include/asm-arm26/constants.h deleted file mode 100644 index 0d0b14415563..000000000000 --- a/include/asm-arm26/constants.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/arm26/Makefile - * - */ - -#define TSK_ACTIVE_MM 96 /* offsetof(struct task_struct, active_mm) */ - -#define VMA_VM_MM 0 /* offsetof(struct vm_area_struct, vm_mm) */ -#define VMA_VM_FLAGS 20 /* offsetof(struct vm_area_struct, vm_flags) */ - -#define VM_EXEC 4 /* VM_EXEC */ - - -#define PAGE_PRESENT 1 /* L_PTE_PRESENT */ -#define PAGE_READONLY 95 /* PAGE_READONLY */ -#define PAGE_NOT_USER 3 /* PAGE_NONE */ -#define PAGE_OLD 3 /* PAGE_NONE */ -#define PAGE_CLEAN 128 /* L_PTE_DIRTY */ - -#define PAGE_SZ 32768 /* PAGE_SIZE */ - -#define SYS_ERROR0 10420224 /* 0x9f0000 */ - -#endif diff --git a/include/asm-arm26/cputime.h b/include/asm-arm26/cputime.h deleted file mode 100644 index d2783a9e47b3..000000000000 --- a/include/asm-arm26/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARM26_CPUTIME_H -#define __ARM26_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __ARM26_CPUTIME_H */ diff --git a/include/asm-arm26/current.h b/include/asm-arm26/current.h deleted file mode 100644 index 75d21e2a3ff7..000000000000 --- a/include/asm-arm26/current.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASMARM_CURRENT_H -#define _ASMARM_CURRENT_H - -#include <linux/thread_info.h> - -static inline struct task_struct *get_current(void) __attribute_const__; - -static inline struct task_struct *get_current(void) -{ - return current_thread_info()->task; -} - -#define current (get_current()) - -#endif /* _ASMARM_CURRENT_H */ diff --git a/include/asm-arm26/delay.h b/include/asm-arm26/delay.h deleted file mode 100644 index 40fbf7bbe6c2..000000000000 --- a/include/asm-arm26/delay.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __ASM_ARM_DELAY_H -#define __ASM_ARM_DELAY_H - -/* - * Copyright (C) 1995 Russell King - * - * Delay routines, using a pre-computed "loops_per_second" value. - */ - -extern void __delay(int loops); - -/* - * division by multiplication: you don't have to worry about - * loss of precision. - * - * Use only for very small delays ( < 1 msec). Should probably use a - * lookup table, really, as the multiplications take much too long with - * short delays. This is a "reasonable" implementation, though (and the - * first constant multiplications gets optimized away if the delay is - * a constant) - * - * FIXME - lets improve it then... - */ -extern void udelay(unsigned long usecs); - -static inline unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c) -{ - return a * b / c; -} - - - -#endif /* defined(_ARM_DELAY_H) */ - diff --git a/include/asm-arm26/device.h b/include/asm-arm26/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-arm26/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include <asm-generic/device.h> - diff --git a/include/asm-arm26/dma.h b/include/asm-arm26/dma.h deleted file mode 100644 index 4326ba85eb72..000000000000 --- a/include/asm-arm26/dma.h +++ /dev/null @@ -1,183 +0,0 @@ -#ifndef __ASM_ARM_DMA_H -#define __ASM_ARM_DMA_H - -typedef unsigned int dmach_t; - -#include <linux/spinlock.h> -#include <asm/system.h> -#include <asm/memory.h> -#include <asm/scatterlist.h> - -// FIXME - do we really need this? arm26 cant do 'proper' DMA - -typedef struct dma_struct dma_t; -typedef unsigned int dmamode_t; - -struct dma_ops { - int (*request)(dmach_t, dma_t *); /* optional */ - void (*free)(dmach_t, dma_t *); /* optional */ - void (*enable)(dmach_t, dma_t *); /* mandatory */ - void (*disable)(dmach_t, dma_t *); /* mandatory */ - int (*residue)(dmach_t, dma_t *); /* optional */ - int (*setspeed)(dmach_t, dma_t *, int); /* optional */ - char *type; -}; - -struct dma_struct { - struct scatterlist buf; /* single DMA */ - int sgcount; /* number of DMA SG */ - struct scatterlist *sg; /* DMA Scatter-Gather List */ - - unsigned int active:1; /* Transfer active */ - unsigned int invalid:1; /* Address/Count changed */ - unsigned int using_sg:1; /* using scatter list? */ - dmamode_t dma_mode; /* DMA mode */ - int speed; /* DMA speed */ - - unsigned int lock; /* Device is allocated */ - const char *device_id; /* Device name */ - - unsigned int dma_base; /* Controller base address */ - int dma_irq; /* Controller IRQ */ - int state; /* Controller state */ - struct scatterlist cur_sg; /* Current controller buffer */ - - struct dma_ops *d_ops; -}; - -/* Prototype: void arch_dma_init(dma) - * Purpose : Initialise architecture specific DMA - * Params : dma - pointer to array of DMA structures - */ -extern void arch_dma_init(dma_t *dma); - -extern void isa_init_dma(dma_t *dma); - - -#define MAX_DMA_ADDRESS 0x03000000 -#define MAX_DMA_CHANNELS 3 - -/* ARC */ -#define DMA_VIRTUAL_FLOPPY0 0 -#define DMA_VIRTUAL_FLOPPY1 1 -#define DMA_VIRTUAL_SOUND 2 - -/* A5K */ -#define DMA_FLOPPY 0 - -/* - * DMA modes - */ -#define DMA_MODE_MASK 3 - -#define DMA_MODE_READ 0 -#define DMA_MODE_WRITE 1 -#define DMA_MODE_CASCADE 2 -#define DMA_AUTOINIT 4 - -extern spinlock_t dma_spin_lock; - -static inline unsigned long claim_dma_lock(void) -{ - unsigned long flags; - spin_lock_irqsave(&dma_spin_lock, flags); - return flags; -} - -static inline void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&dma_spin_lock, flags); -} - -/* Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - */ -#define clear_dma_ff(channel) - -/* Set only the page register bits of the transfer address. - * - * NOTE: This is an architecture specific function, and should - * be hidden from the drivers - */ -extern void set_dma_page(dmach_t channel, char pagenr); - -/* Request a DMA channel - * - * Some architectures may need to do allocate an interrupt - */ -extern int request_dma(dmach_t channel, const char * device_id); - -/* Free a DMA channel - * - * Some architectures may need to do free an interrupt - */ -extern void free_dma(dmach_t channel); - -/* Enable DMA for this channel - * - * On some architectures, this may have other side effects like - * enabling an interrupt and setting the DMA registers. - */ -extern void enable_dma(dmach_t channel); - -/* Disable DMA for this channel - * - * On some architectures, this may have other side effects like - * disabling an interrupt or whatever. - */ -extern void disable_dma(dmach_t channel); - -/* Test whether the specified channel has an active DMA transfer - */ -extern int dma_channel_active(dmach_t channel); - -/* Set the DMA scatter gather list for this channel - * - * This should not be called if a DMA channel is enabled, - * especially since some DMA architectures don't update the - * DMA address immediately, but defer it to the enable_dma(). - */ -extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); - -/* Set the DMA address for this channel - * - * This should not be called if a DMA channel is enabled, - * especially since some DMA architectures don't update the - * DMA address immediately, but defer it to the enable_dma(). - */ -extern void set_dma_addr(dmach_t channel, unsigned long physaddr); - -/* Set the DMA byte count for this channel - * - * This should not be called if a DMA channel is enabled, - * especially since some DMA architectures don't update the - * DMA count immediately, but defer it to the enable_dma(). - */ -extern void set_dma_count(dmach_t channel, unsigned long count); - -/* Set the transfer direction for this channel - * - * This should not be called if a DMA channel is enabled, - * especially since some DMA architectures don't update the - * DMA transfer direction immediately, but defer it to the - * enable_dma(). - */ -extern void set_dma_mode(dmach_t channel, dmamode_t mode); - -/* Set the transfer speed for this channel - */ -extern void set_dma_speed(dmach_t channel, int cycle_ns); - -/* Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * If called before the channel has been used, it may return 1. - * Otherwise, it returns the number of _bytes_ left to transfer. - */ -extern int get_dma_residue(dmach_t channel); - -#ifndef NO_DMA -#define NO_DMA 255 -#endif - -#endif /* _ARM_DMA_H */ diff --git a/include/asm-arm26/ecard.h b/include/asm-arm26/ecard.h deleted file mode 100644 index 66691939c3c1..000000000000 --- a/include/asm-arm26/ecard.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * linux/include/asm-arm26/ecard.h - * - * definitions for expansion cards - * - * This is a new system as from Linux 1.2.3 - * - * Changelog: - * 11-12-1996 RMK Further minor improvements - * 12-09-1997 RMK Added interrupt enable/disable for card level - * 18-05-2003 IM Adjusted for ARM26 - * - * Reference: Acorns Risc OS 3 Programmers Reference Manuals. - */ - -#ifndef __ASM_ECARD_H -#define __ASM_ECARD_H - -/* - * Currently understood cards (but not necessarily - * supported): - * Manufacturer Product ID - */ -#define MANU_ACORN 0x0000 -#define PROD_ACORN_SCSI 0x0002 -#define PROD_ACORN_ETHER1 0x0003 -#define PROD_ACORN_MFM 0x000b - -#define MANU_CCONCEPTS 0x0009 -#define PROD_CCONCEPTS_COLOURCARD 0x0050 - -#define MANU_ANT2 0x0011 -#define PROD_ANT_ETHER3 0x00a4 - -#define MANU_ATOMWIDE 0x0017 -#define PROD_ATOMWIDE_3PSERIAL 0x0090 - -#define MANU_IRLAM_INSTRUMENTS 0x001f -#define MANU_IRLAM_INSTRUMENTS_ETHERN 0x5678 - -#define MANU_OAK 0x0021 -#define PROD_OAK_SCSI 0x0058 - -#define MANU_MORLEY 0x002b -#define PROD_MORLEY_SCSI_UNCACHED 0x0067 - -#define MANU_CUMANA 0x003a -#define PROD_CUMANA_SCSI_2 0x003a -#define PROD_CUMANA_SCSI_1 0x00a0 - -#define MANU_ICS 0x003c -#define PROD_ICS_IDE 0x00ae - -#define MANU_ICS2 0x003d -#define PROD_ICS2_IDE 0x00ae - -#define MANU_SERPORT 0x003f -#define PROD_SERPORT_DSPORT 0x00b9 - -#define MANU_ARXE 0x0041 -#define PROD_ARXE_SCSI 0x00be - -#define MANU_I3 0x0046 -#define PROD_I3_ETHERLAN500 0x00d4 -#define PROD_I3_ETHERLAN600 0x00ec -#define PROD_I3_ETHERLAN600A 0x011e - -#define MANU_ANT 0x0053 -#define PROD_ANT_ETHERM 0x00d8 -#define PROD_ANT_ETHERB 0x00e4 - -#define MANU_ALSYSTEMS 0x005b -#define PROD_ALSYS_SCSIATAPI 0x0107 - -#define MANU_MCS 0x0063 -#define PROD_MCS_CONNECT32 0x0125 - -#define MANU_EESOX 0x0064 -#define PROD_EESOX_SCSI2 0x008c - -#define MANU_YELLOWSTONE 0x0096 -#define PROD_YELLOWSTONE_RAPIDE32 0x0120 - -#define MANU_SIMTEC 0x005f -#define PROD_SIMTEC_IDE8 0x0130 -#define PROD_SIMTEC_IDE16 0x0131 - - -#ifdef ECARD_C -#define CONST -#else -#define CONST const -#endif - -#define MAX_ECARDS 4 - -typedef enum { /* Cards address space */ - ECARD_IOC, - ECARD_MEMC, - ECARD_EASI -} card_type_t; - -typedef enum { /* Speed for ECARD_IOC space */ - ECARD_SLOW = 0, - ECARD_MEDIUM = 1, - ECARD_FAST = 2, - ECARD_SYNC = 3 -} card_speed_t; - -struct ecard_id { /* Card ID structure */ - unsigned short manufacturer; - unsigned short product; - void *data; -}; - -struct in_ecid { /* Packed card ID information */ - unsigned short product; /* Product code */ - unsigned short manufacturer; /* Manufacturer code */ - unsigned char id:4; /* Simple ID */ - unsigned char cd:1; /* Chunk dir present */ - unsigned char is:1; /* Interrupt status pointers */ - unsigned char w:2; /* Width */ - unsigned char country; /* Country */ - unsigned char irqmask; /* IRQ mask */ - unsigned char fiqmask; /* FIQ mask */ - unsigned long irqoff; /* IRQ offset */ - unsigned long fiqoff; /* FIQ offset */ -}; - -typedef struct expansion_card ecard_t; -typedef unsigned long *loader_t; - -typedef struct { /* Card handler routines */ - void (*irqenable)(ecard_t *ec, int irqnr); - void (*irqdisable)(ecard_t *ec, int irqnr); - int (*irqpending)(ecard_t *ec); - void (*fiqenable)(ecard_t *ec, int fiqnr); - void (*fiqdisable)(ecard_t *ec, int fiqnr); - int (*fiqpending)(ecard_t *ec); -} expansioncard_ops_t; - -#define ECARD_NUM_RESOURCES (6) - -#define ECARD_RES_IOCSLOW (0) -#define ECARD_RES_IOCMEDIUM (1) -#define ECARD_RES_IOCFAST (2) -#define ECARD_RES_IOCSYNC (3) -#define ECARD_RES_MEMC (4) -#define ECARD_RES_EASI (5) - -#define ecard_resource_start(ec,nr) ((ec)->resource[nr].start) -#define ecard_resource_end(ec,nr) ((ec)->resource[nr].end) -#define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \ - (ec)->resource[nr].start + 1) - -/* - * This contains all the info needed on an expansion card - */ -struct expansion_card { - struct expansion_card *next; - - struct device dev; - struct resource resource[ECARD_NUM_RESOURCES]; - - /* Public data */ - volatile unsigned char *irqaddr; /* address of IRQ register */ - volatile unsigned char *fiqaddr; /* address of FIQ register */ - unsigned char irqmask; /* IRQ mask */ - unsigned char fiqmask; /* FIQ mask */ - unsigned char claimed; /* Card claimed? */ - - void *irq_data; /* Data for use for IRQ by card */ - void *fiq_data; /* Data for use for FIQ by card */ - const expansioncard_ops_t *ops; /* Enable/Disable Ops for card */ - - CONST unsigned int slot_no; /* Slot number */ - CONST unsigned int dma; /* DMA number (for request_dma) */ - CONST unsigned int irq; /* IRQ number (for request_irq) */ - CONST unsigned int fiq; /* FIQ number (for request_irq) */ - CONST card_type_t type; /* Type of card */ - CONST struct in_ecid cid; /* Card Identification */ - - /* Private internal data */ - const char *card_desc; /* Card description */ - CONST unsigned int podaddr; /* Base Linux address for card */ - CONST loader_t loader; /* loader program */ - u64 dma_mask; -}; - -struct in_chunk_dir { - unsigned int start_offset; - union { - unsigned char string[256]; - unsigned char data[1]; - } d; -}; - -/* - * ecard_claim: claim an expansion card entry - * FIXME - are these atomic / called with interrupts off ? - */ -#define ecard_claim(ec) ((ec)->claimed = 1) - -/* - * ecard_release: release an expansion card entry - */ -#define ecard_release(ec) ((ec)->claimed = 0) - -/* - * Read a chunk from an expansion card - * cd : where to put read data - * ec : expansion card info struct - * id : id number to find - * num: (n+1)'th id to find. - */ -extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); - -/* - * Obtain the address of a card - */ -extern unsigned int ecard_address (struct expansion_card *ec, card_type_t card_type, card_speed_t speed); - -#ifdef ECARD_C -/* Definitions internal to ecard.c - for it's use only!! - * - * External expansion card header as read from the card - */ -struct ex_ecid { - unsigned char r_irq:1; - unsigned char r_zero:1; - unsigned char r_fiq:1; - unsigned char r_id:4; - unsigned char r_a:1; - - unsigned char r_cd:1; - unsigned char r_is:1; - unsigned char r_w:2; - unsigned char r_r1:4; - - unsigned char r_r2:8; - - unsigned char r_prod[2]; - - unsigned char r_manu[2]; - - unsigned char r_country; - - unsigned char r_irqmask; - unsigned char r_irqoff[3]; - - unsigned char r_fiqmask; - unsigned char r_fiqoff[3]; -}; - -/* - * Chunk directory entry as read from the card - */ -struct ex_chunk_dir { - unsigned char r_id; - unsigned char r_len[3]; - unsigned long r_start; - union { - char string[256]; - char data[1]; - } d; -#define c_id(x) ((x)->r_id) -#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16)) -#define c_start(x) ((x)->r_start) -}; - -#endif - -extern struct bus_type ecard_bus_type; - -#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) - -struct ecard_driver { - int (*probe)(struct expansion_card *, const struct ecard_id *id); - void (*remove)(struct expansion_card *); - void (*shutdown)(struct expansion_card *); - const struct ecard_id *id_table; - unsigned int id; - struct device_driver drv; -}; - -#define ECARD_DRV(_d) container_of((_d), struct ecard_driver, drv) - -#define ecard_set_drvdata(ec,data) dev_set_drvdata(&(ec)->dev, (data)) -#define ecard_get_drvdata(ec) dev_get_drvdata(&(ec)->dev) - -int ecard_register_driver(struct ecard_driver *); -void ecard_remove_driver(struct ecard_driver *); - -#endif diff --git a/include/asm-arm26/elf.h b/include/asm-arm26/elf.h deleted file mode 100644 index 5a47fdb3015d..000000000000 --- a/include/asm-arm26/elf.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef __ASMARM_ELF_H -#define __ASMARM_ELF_H - -/* - * ELF register definitions.. - */ - -#include <asm/ptrace.h> -#include <asm/procinfo.h> - -//FIXME - is it always 32K ? - -#define ELF_EXEC_PAGESIZE 32768 -#define SET_PERSONALITY(ex,ibcs2) set_personality(PER_LINUX) - -typedef unsigned long elf_greg_t; -typedef unsigned long elf_freg_t[3]; - -#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct { void *null; } elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture. - * We can only execute 26-bit code. - */ - -#define EM_ARM 40 -#define EF_ARM_APCS26 0x08 - -//#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && ((x)->e_flags & EF_ARM_APCS26) ) FIXME!!!!! - this looks OK, but the flags seem to be wrong. -#define elf_check_arch(x) (1) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_ARM - -#define USE_ELF_CORE_DUMP - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* When the program starts, a1 contains a pointer to a function to be - registered with atexit, as per the SVR4 ABI. A value of 0 means we - have no such handler. */ -#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -extern unsigned int elf_hwcap; -#define ELF_HWCAP (elf_hwcap) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -/* For now we just provide a fairly general string that describes the - processor family. This could be made more specific later if someone - implemented optimisations that require it. 26-bit CPUs give you - "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't - supported). - */ - -#define ELF_PLATFORM_SIZE 8 -extern char elf_platform[]; -#define ELF_PLATFORM (elf_platform) - -#endif diff --git a/include/asm-arm26/emergency-restart.h b/include/asm-arm26/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/include/asm-arm26/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-arm26/errno.h b/include/asm-arm26/errno.h deleted file mode 100644 index 6e60f0612bb6..000000000000 --- a/include/asm-arm26/errno.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ARM_ERRNO_H -#define _ARM_ERRNO_H - -#include <asm-generic/errno.h> - -#endif diff --git a/include/asm-arm26/fb.h b/include/asm-arm26/fb.h deleted file mode 100644 index c7df38030992..000000000000 --- a/include/asm-arm26/fb.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include <linux/fb.h> - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/include/asm-arm26/fcntl.h b/include/asm-arm26/fcntl.h deleted file mode 100644 index d85995e7459e..000000000000 --- a/include/asm-arm26/fcntl.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ARM_FCNTL_H -#define _ARM_FCNTL_H - -/* open/fcntl - O_SYNC is only implemented on blocks devices and on files - located on an ext2 file system */ -#define O_DIRECTORY 040000 /* must be a directory */ -#define O_NOFOLLOW 0100000 /* don't follow links */ -#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ -#define O_LARGEFILE 0400000 - -#include <asm-generic/fcntl.h> - -#endif diff --git a/include/asm-arm26/fiq.h b/include/asm-arm26/fiq.h deleted file mode 100644 index a3bad09e825c..000000000000 --- a/include/asm-arm26/fiq.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/include/asm-arm/fiq.h - * - * Support for FIQ on ARM architectures. - * Written by Philip Blundell <philb@gnu.org>, 1998 - * Re-written by Russell King - */ - -#ifndef __ASM_FIQ_H -#define __ASM_FIQ_H - -#include <asm/ptrace.h> - -struct fiq_handler { - struct fiq_handler *next; - /* Name - */ - const char *name; - /* Called to ask driver to relinquish/ - * reacquire FIQ - * return zero to accept, or -<errno> - */ - int (*fiq_op)(void *, int relinquish); - /* data for the relinquish/reacquire functions - */ - void *dev_id; -}; - -extern int claim_fiq(struct fiq_handler *f); -extern void release_fiq(struct fiq_handler *f); -extern void set_fiq_handler(void *start, unsigned int length); -extern void set_fiq_regs(struct pt_regs *regs); -extern void get_fiq_regs(struct pt_regs *regs); -extern void enable_fiq(int fiq); -extern void disable_fiq(int fiq); - -#endif diff --git a/include/asm-arm26/floppy.h b/include/asm-arm26/floppy.h deleted file mode 100644 index efb732165a4f..000000000000 --- a/include/asm-arm26/floppy.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * linux/include/asm-arm/floppy.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note that we don't touch FLOPPY_DMA nor FLOPPY_IRQ here - */ -#ifndef __ASM_ARM_FLOPPY_H -#define __ASM_ARM_FLOPPY_H - -#define fd_outb(val,port) \ - do { \ - if ((port) == FD_DOR) \ - fd_setdor((val)); \ - else \ - outb((val),(port)); \ - } while(0) - -#define fd_inb(port) inb((port)) -#define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\ - IRQF_DISABLED,"floppy",NULL) -#define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL) -#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) -#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) - -#define fd_request_dma() request_dma(DMA_FLOPPY,"floppy") -#define fd_free_dma() free_dma(DMA_FLOPPY) -#define fd_disable_dma() disable_dma(DMA_FLOPPY) -#define fd_enable_dma() enable_dma(DMA_FLOPPY) -#define fd_clear_dma_ff() clear_dma_ff(DMA_FLOPPY) -#define fd_set_dma_mode(mode) set_dma_mode(DMA_FLOPPY, (mode)) -#define fd_set_dma_addr(addr) set_dma_addr(DMA_FLOPPY, virt_to_bus((addr))) -#define fd_set_dma_count(len) set_dma_count(DMA_FLOPPY, (len)) -#define fd_cacheflush(addr,sz) - -/* need to clean up dma.h */ -#define DMA_FLOPPYDISK DMA_FLOPPY - -/* Floppy_selects is the list of DOR's to select drive fd - * - * On initialisation, the floppy list is scanned, and the drives allocated - * in the order that they are found. This is done by seeking the drive - * to a non-zero track, and then restoring it to track 0. If an error occurs, - * then there is no floppy drive present. [to be put back in again] - */ -static unsigned char floppy_selects[2][4] = -{ - { 0x10, 0x21, 0x23, 0x33 }, - { 0x10, 0x21, 0x23, 0x33 } -}; - -#define fd_setdor(dor) \ -do { \ - int new_dor = (dor); \ - if (new_dor & 0xf0) \ - new_dor = (new_dor & 0x0c) | floppy_selects[fdc][new_dor & 3]; \ - else \ - new_dor &= 0x0c; \ - outb(new_dor, FD_DOR); \ -} while (0) - -/* - * Someday, we'll automatically detect which drives are present... - */ -static inline void fd_scandrives (void) -{ -#if 0 - int floppy, drive_count; - - fd_disable_irq(); - raw_cmd = &default_raw_cmd; - raw_cmd->flags = FD_RAW_SPIN | FD_RAW_NEED_SEEK; - raw_cmd->track = 0; - raw_cmd->rate = ?; - drive_count = 0; - for (floppy = 0; floppy < 4; floppy ++) { - current_drive = drive_count; - /* - * Turn on floppy motor - */ - if (start_motor(redo_fd_request)) - continue; - /* - * Set up FDC - */ - fdc_specify(); - /* - * Tell FDC to recalibrate - */ - output_byte(FD_RECALIBRATE); - LAST_OUT(UNIT(floppy)); - /* wait for command to complete */ - if (!successful) { - int i; - for (i = drive_count; i < 3; i--) - floppy_selects[fdc][i] = floppy_selects[fdc][i + 1]; - floppy_selects[fdc][3] = 0; - floppy -= 1; - } else - drive_count++; - } -#else - floppy_selects[0][0] = 0x10; - floppy_selects[0][1] = 0x21; - floppy_selects[0][2] = 0x23; - floppy_selects[0][3] = 0x33; -#endif -} - -#define FDC1 (0x3f0) - -#define FLOPPY0_TYPE 4 -#define FLOPPY1_TYPE 4 - -#define N_FDC 1 -#define N_DRIVE 4 - -#define FLOPPY_MOTOR_MASK 0xf0 - -#define CROSS_64KB(a,s) (0) - -/* - * This allows people to reverse the order of - * fd0 and fd1, in case their hardware is - * strangely connected (as some RiscPCs - * and A5000s seem to be). - */ -static void driveswap(int *ints, int dummy, int dummy2) -{ - floppy_selects[0][0] ^= floppy_selects[0][1]; - floppy_selects[0][1] ^= floppy_selects[0][0]; - floppy_selects[0][0] ^= floppy_selects[0][1]; -} - -#define EXTRA_FLOPPY_PARAMS ,{ "driveswap", &driveswap, NULL, 0, 0 } - -#endif diff --git a/include/asm-arm26/fpstate.h b/include/asm-arm26/fpstate.h deleted file mode 100644 index 785749b3c5ab..000000000000 --- a/include/asm-arm26/fpstate.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * linux/include/asm-arm/fpstate.h - * - * Copyright (C) 1995 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_FPSTATE_H -#define __ASM_ARM_FPSTATE_H - -#define FP_SIZE 35 - -struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ -}; - -struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ -}; - -union fp_state { - struct fp_hard_struct hard; - struct fp_soft_struct soft; -}; - -#endif diff --git a/include/asm-arm26/futex.h b/include/asm-arm26/futex.h deleted file mode 100644 index 6a332a9f099c..000000000000 --- a/include/asm-arm26/futex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - -#include <asm-generic/futex.h> - -#endif diff --git a/include/asm-arm26/hardirq.h b/include/asm-arm26/hardirq.h deleted file mode 100644 index e717742ffce0..000000000000 --- a/include/asm-arm26/hardirq.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __ASM_HARDIRQ_H -#define __ASM_HARDIRQ_H - -#include <linux/cache.h> -#include <linux/threads.h> -#include <asm/irq.h> - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - -#define HARDIRQ_BITS 8 - -/* - * The hardirq mask has to be large enough to have space - * for potentially all IRQ sources in the system nesting - * on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -#ifndef CONFIG_SMP - -extern asmlinkage void __do_softirq(void); - -#endif - - -#endif /* __ASM_HARDIRQ_H */ diff --git a/include/asm-arm26/hardware.h b/include/asm-arm26/hardware.h deleted file mode 100644 index 801df0bde8b7..000000000000 --- a/include/asm-arm26/hardware.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linux/include/asm-arm/arch-arc/hardware.h - * - * Copyright (C) 1996-1999 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains the hardware definitions of the - * Acorn Archimedes/A5000 machines. - * - * Modifications: - * 04-04-1998 PJB/RMK Merged arc and a5k versions - */ -#ifndef __ASM_HARDWARE_H -#define __ASM_HARDWARE_H - - - -/* - * What hardware must be present - these can be tested by the kernel - * source. - */ -#define HAS_IOC -#define HAS_MEMC -#define HAS_VIDC - -#define VDMA_ALIGNMENT PAGE_SIZE -#define VDMA_XFERSIZE 16 -#define VDMA_INIT 0 -#define VDMA_START 1 -#define VDMA_END 2 - -#ifndef __ASSEMBLY__ -extern void memc_write(unsigned int reg, unsigned long val); - -#define video_set_dma(start,end,offset) \ -do { \ - memc_write (VDMA_START, (start >> 2)); \ - memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \ - memc_write (VDMA_INIT, (offset >> 2)); \ -} while (0) -#endif - - -/* Hardware addresses of major areas. - * *_START is the physical address - * *_SIZE is the size of the region - * *_BASE is the virtual address - */ -#define IO_START 0x03000000 -#define IO_SIZE 0x01000000 -#define IO_BASE 0x03000000 - -/* - * Screen mapping information - */ -#define SCREEN_START 0x02000000 -#define SCREEN_END 0x02078000 -#define SCREEN_SIZE 0x00078000 -#define SCREEN_BASE 0x02000000 - - -#define EXPMASK_BASE 0x03360000 -#define IOEB_BASE 0x03350000 -#define VIDC_BASE 0x03400000 -#define LATCHA_BASE 0x03250040 -#define LATCHB_BASE 0x03250018 -#define IOC_BASE 0x03200000 -#define FLOPPYDMA_BASE 0x0302a000 -#define PCIO_BASE 0x03010000 - -// FIXME - are the below correct? -#define PODSLOT_IOC0_BASE 0x03240000 -#define PODSLOT_IOC_SIZE (1 << 14) -#define PODSLOT_MEMC_BASE 0x03000000 -#define PODSLOT_MEMC_SIZE (1 << 14) - -#define vidc_writel(val) __raw_writel(val, VIDC_BASE) - -#ifndef __ASSEMBLY__ - -/* - * for use with inb/outb - */ -#define IOEB_VID_CTL (IOEB_BASE + 0x48) -#define IOEB_PRESENT (IOEB_BASE + 0x50) -#define IOEB_PSCLR (IOEB_BASE + 0x58) -#define IOEB_MONTYPE (IOEB_BASE + 0x70) - -//FIXME - These adresses are weird - ISTR some weirdo address shifting stuff was going on here... -#define IO_EC_IOC_BASE 0x80090000 -#define IO_EC_MEMC_BASE 0x80000000 - -#ifdef CONFIG_ARCH_ARC -/* A680 hardware */ -#define WD1973_BASE 0x03290000 -#define WD1973_LATCH 0x03350000 -#define Z8530_BASE 0x032b0008 -#define SCSI_BASE 0x03100000 -#endif - -#endif - -#define EXPMASK_STATUS (EXPMASK_BASE + 0x00) -#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) - -#endif diff --git a/include/asm-arm26/ide.h b/include/asm-arm26/ide.h deleted file mode 100644 index db804d751df9..000000000000 --- a/include/asm-arm26/ide.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * linux/include/asm-arm/ide.h - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - */ - -/* - * This file contains the i386 architecture specific IDE code. - */ - -#ifndef __ASMARM_IDE_H -#define __ASMARM_IDE_H - -#ifdef __KERNEL__ - -#ifndef MAX_HWIFS -#define MAX_HWIFS 4 -#endif - -#include <asm/irq.h> -#include <asm/mach-types.h> - -/* JMA 18.05.03 these will never be needed, but the kernel needs them to compile */ -#define __ide_mm_insw(port,addr,len) readsw(port,addr,len) -#define __ide_mm_insl(port,addr,len) readsl(port,addr,len) -#define __ide_mm_outsw(port,addr,len) writesw(port,addr,len) -#define __ide_mm_outsl(port,addr,len) writesl(port,addr,len) - -#define IDE_ARCH_OBSOLETE_INIT -#define ide_default_io_ctl(base) (0) - -#endif /* __KERNEL__ */ - -#endif /* __ASMARM_IDE_H */ diff --git a/include/asm-arm26/io.h b/include/asm-arm26/io.h deleted file mode 100644 index a5a7a4d5e09c..000000000000 --- a/include/asm-arm26/io.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> -#include <asm/memory.h> -#include <asm/hardware.h> - -/* - * Generic IO read/write. These perform native-endian accesses. Note - * that some architectures will want to re-define __raw_{read,write}w. - */ -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - - -/* - * Bad read/write accesses... - */ -extern void __readwrite_bug(const char *fn); - -/* - * Now, pick up the machine-defined IO definitions - */ - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * GCC is totally crap at loading/storing data. We try to persuade it - * to do the right thing by using these whereever possible instead of - * the above. - */ -#define __arch_base_getb(b,o) \ - ({ \ - unsigned int v, r = (b); \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2]" \ - : "=r" (v) \ - : "r" (r), "Ir" (o)); \ - v; \ - }) - -#define __arch_base_getl(b,o) \ - ({ \ - unsigned int v, r = (b); \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2]" \ - : "=r" (v) \ - : "r" (r), "Ir" (o)); \ - v; \ - }) - -#define __arch_base_putb(v,b,o) \ - ({ \ - unsigned int r = (b); \ - __asm__ __volatile__( \ - "strb %0, [%1, %2]" \ - : \ - : "r" (v), "r" (r), "Ir" (o)); \ - }) - -#define __arch_base_putl(v,b,o) \ - ({ \ - unsigned int r = (b); \ - __asm__ __volatile__( \ - "str %0, [%1, %2]" \ - : \ - : "r" (v), "r" (r), "Ir" (o)); \ - }) - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ - * and are translated to the start of IO. Note that all addresses are - * shifted left! - */ -#define __PORT_PCIO(x) (!((x) & 0x80000000)) - -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ -static inline void __outb (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "strb %1, [%0, %2, lsl #2] @ outb" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outw (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outw" - : "=&r" (temp) - : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outl (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outl" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "tst %2, #0x80000000\n\t" \ - "mov %0, %4\n\t" \ - "addeq %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline unsigned int __ioaddr (unsigned int port) \ -{ \ - if (__PORT_PCIO(port)) \ - return (unsigned int)(PCIO_BASE + (port << 2)); \ - else \ - return (unsigned int)(IO_BASE + (port << 2)); \ -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result & 0xffff; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define __ioaddrc(port) \ -({ \ - unsigned long addr; \ - if (__PORT_PCIO((port))) \ - addr = PCIO_BASE + ((port) << 2); \ - else \ - addr = IO_BASE + ((port) << 2); \ - addr; \ -}) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) - -/* JMA 18.02.03 added sb,sl from arm/io.h, changing io to ioaddr */ - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) -#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) -#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) - -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) - -#define readb(c) (__readwrite_bug("readb"),0) -#define readw(c) (__readwrite_bug("readw"),0) -#define readl(c) (__readwrite_bug("readl"),0) -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define writeb(v,c) __readwrite_bug("writeb") -#define writew(v,c) __readwrite_bug("writew") -#define writel(v,c) __readwrite_bug("writel") - -#define readsw(p,d,l) (__readwrite_bug("readsw"),0) -#define readsl(p,d,l) (__readwrite_bug("readsl"),0) -#define writesw(p,d,l) __readwrite_bug("writesw") -#define writesl(p,d,l) __readwrite_bug("writesl") - -#define mmiowb() - -/* the following macro is deprecated */ -#define ioaddr(port) __ioaddr((port)) - -/* - * No ioremap support here. - */ -#define __arch_ioremap(c,s,f,a) ((void *)(c)) -#define __arch_iounmap(c) do { } while (0) - - -#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \ - defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl) -#warning machine class uses old __arch_putw or __arch_getw -#endif - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - */ -/* -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -*/ -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * Documentation/IO-mapping.txt. - */ -extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long); -extern void __iounmap(void *addr); - -#ifndef __arch_ioremap -#define ioremap(cookie,size) __ioremap(cookie,size,0,1) -#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1) -#define iounmap(cookie) __iounmap(cookie) -#else -#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1) -#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1) -#define iounmap(cookie) __arch_iounmap(cookie) -#endif - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * can the hardware map this into one segment or not, given no other - * constraints. - */ -#define BIOVEC_MERGEABLE(vec1, vec2) \ - ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/include/asm-arm26/ioc.h b/include/asm-arm26/ioc.h deleted file mode 100644 index b3b46ef65943..000000000000 --- a/include/asm-arm26/ioc.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * linux/include/asm-arm/hardware/ioc.h - * - * Copyright (C) Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Use these macros to read/write the IOC. All it does is perform the actual - * read/write. - */ -#ifndef __ASMARM_HARDWARE_IOC_H -#define __ASMARM_HARDWARE_IOC_H - -#ifndef __ASSEMBLY__ - -/* - * We use __raw_base variants here so that we give the compiler the - * chance to keep IOC_BASE in a register. - */ -#define ioc_readb(off) __raw_readb(IOC_BASE + (off)) -#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off)) - -#endif - -#define IOC_CONTROL (0x00) -#define IOC_KARTTX (0x04) -#define IOC_KARTRX (0x04) - -#define IOC_IRQSTATA (0x10) -#define IOC_IRQREQA (0x14) -#define IOC_IRQCLRA (0x14) -#define IOC_IRQMASKA (0x18) - -#define IOC_IRQSTATB (0x20) -#define IOC_IRQREQB (0x24) -#define IOC_IRQMASKB (0x28) - -#define IOC_FIQSTAT (0x30) -#define IOC_FIQREQ (0x34) -#define IOC_FIQMASK (0x38) - -#define IOC_T0CNTL (0x40) -#define IOC_T0LTCHL (0x40) -#define IOC_T0CNTH (0x44) -#define IOC_T0LTCHH (0x44) -#define IOC_T0GO (0x48) -#define IOC_T0LATCH (0x4c) - -#define IOC_T1CNTL (0x50) -#define IOC_T1LTCHL (0x50) -#define IOC_T1CNTH (0x54) -#define IOC_T1LTCHH (0x54) -#define IOC_T1GO (0x58) -#define IOC_T1LATCH (0x5c) - -#define IOC_T2CNTL (0x60) -#define IOC_T2LTCHL (0x60) -#define IOC_T2CNTH (0x64) -#define IOC_T2LTCHH (0x64) -#define IOC_T2GO (0x68) -#define IOC_T2LATCH (0x6c) - -#define IOC_T3CNTL (0x70) -#define IOC_T3LTCHL (0x70) -#define IOC_T3CNTH (0x74) -#define IOC_T3LTCHH (0x74) -#define IOC_T3GO (0x78) -#define IOC_T3LATCH (0x7c) - -#endif diff --git a/include/asm-arm26/ioctls.h b/include/asm-arm26/ioctls.h deleted file mode 100644 index 8a3296200be1..000000000000 --- a/include/asm-arm26/ioctls.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef __ASM_ARM_IOCTLS_H -#define __ASM_ARM_IOCTLS_H - -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x545E - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -#endif diff --git a/include/asm-arm26/ipcbuf.h b/include/asm-arm26/ipcbuf.h deleted file mode 100644 index 97683975f7df..000000000000 --- a/include/asm-arm26/ipcbuf.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __ASMARM_IPCBUF_H -#define __ASMARM_IPCBUF_H - -/* - * The ipc64_perm structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit mode_t and seq - * - 2 miscellaneous 32-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid32_t uid; - __kernel_gid32_t gid; - __kernel_uid32_t cuid; - __kernel_gid32_t cgid; - __kernel_mode_t mode; - unsigned short __pad1; - unsigned short seq; - unsigned short __pad2; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* __ASMARM_IPCBUF_H */ diff --git a/include/asm-arm26/irq.h b/include/asm-arm26/irq.h deleted file mode 100644 index 9aaac87efba9..000000000000 --- a/include/asm-arm26/irq.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef __ASM_ARM_IRQ_H -#define __ASM_ARM_IRQ_H - -#include <asm/sysirq.h> - -#ifndef NR_IRQS -#define NR_IRQS 128 -#endif - - -/* JMA 18.05.02 Copied off arch/arm/irq.h */ -#ifndef irq_canonicalize -#define irq_canonicalize(i) (i) -#endif - - -/* - * Use this value to indicate lack of interrupt - * capability - */ -#ifndef NO_IRQ -#define NO_IRQ ((unsigned int)(-1)) -#endif - -struct irqaction; - -#define disable_irq_nosync(i) disable_irq(i) - -extern void disable_irq(unsigned int); -extern void enable_irq(unsigned int); - -#define __IRQT_FALEDGE (1 << 0) -#define __IRQT_RISEDGE (1 << 1) -#define __IRQT_LOWLVL (1 << 2) -#define __IRQT_HIGHLVL (1 << 3) - -#define IRQT_NOEDGE (0) -#define IRQT_RISING (__IRQT_RISEDGE) -#define IRQT_FALLING (__IRQT_FALEDGE) -#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE) -#define IRQT_LOW (__IRQT_LOWLVL) -#define IRQT_HIGH (__IRQT_HIGHLVL) -#define IRQT_PROBE (1 << 4) - -int set_irq_type(unsigned int irq, unsigned int type); - -#endif - diff --git a/include/asm-arm26/irqchip.h b/include/asm-arm26/irqchip.h deleted file mode 100644 index 6a007a954098..000000000000 --- a/include/asm-arm26/irqchip.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linux/include/asm-arm/mach/irq.h - * - * Copyright (C) 1995-2000 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_MACH_IRQ_H -#define __ASM_ARM_MACH_IRQ_H - -struct irqdesc; -struct pt_regs; -struct seq_file; - -typedef void (*irq_handler_t)(unsigned int, struct irqdesc *, struct pt_regs *); -typedef void (*irq_control_t)(unsigned int); - -struct irqchip { - /* - * Acknowledge the IRQ. - * If this is a level-based IRQ, then it is expected to mask the IRQ - * as well. - */ - void (*ack)(unsigned int); - /* - * Mask the IRQ in hardware. - */ - void (*mask)(unsigned int); - /* - * Unmask the IRQ in hardware. - */ - void (*unmask)(unsigned int); - /* - * Re-run the IRQ - */ - void (*rerun)(unsigned int); - /* - * Set the type of the IRQ. - */ - int (*type)(unsigned int, unsigned int); -}; - -struct irqdesc { - irq_handler_t handle; - struct irqchip *chip; - struct irqaction *action; - - unsigned int enabled : 1; /* IRQ is currently enabled */ - unsigned int triggered: 1; /* IRQ has occurred */ - unsigned int running : 1; /* IRQ is running */ - unsigned int pending : 1; /* IRQ is pending */ - unsigned int probing : 1; /* IRQ in use for a probe */ - unsigned int probe_ok : 1; /* IRQ can be used for probe */ - unsigned int valid : 1; /* IRQ claimable */ - unsigned int noautoenable : 1; /* don't automatically enable IRQ */ - unsigned int unused :23; - unsigned int depth; /* disable depth */ - - /* - * IRQ lock detection - */ - unsigned int lck_cnt; - unsigned int lck_pc; - unsigned int lck_jif; -}; - -extern struct irqdesc irq_desc[]; - -/* - * This is internal. Do not use it. - */ -extern void (*init_arch_irq)(void); -extern void init_FIQ(void); -extern int show_fiq_list(struct seq_file *, void *); -void __set_irq_handler(unsigned int irq, irq_handler_t, int); - -/* - * External stuff. - */ -#define set_irq_handler(irq,handler) __set_irq_handler(irq,handler,0) -#define set_irq_chained_handler(irq,handler) __set_irq_handler(irq,handler,1) - -void set_irq_chip(unsigned int irq, struct irqchip *); -void set_irq_flags(unsigned int irq, unsigned int flags); - -#define IRQF_VALID (1 << 0) -#define IRQF_PROBE (1 << 1) -#define IRQF_NOAUTOEN (1 << 2) - -/* - * Built-in IRQ handlers. - */ -void do_level_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs); -void do_edge_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs); -void do_simple_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs); -void do_bad_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs); -void dummy_mask_unmask_irq(unsigned int irq); - -#endif diff --git a/include/asm-arm26/kdebug.h b/include/asm-arm26/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-arm26/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/kdebug.h> diff --git a/include/asm-arm26/kmap_types.h b/include/asm-arm26/kmap_types.h deleted file mode 100644 index d5da712b723c..000000000000 --- a/include/asm-arm26/kmap_types.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __ARM_KMAP_TYPES_H -#define __ARM_KMAP_TYPES_H - -/* - * This is the "bare minimum". AIO seems to require this. - */ -enum km_type { - KM_IRQ0, - KM_USER1 -}; - -#endif diff --git a/include/asm-arm26/leds.h b/include/asm-arm26/leds.h deleted file mode 100644 index 12290ea55801..000000000000 --- a/include/asm-arm26/leds.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/include/asm-arm/leds.h - * - * Copyright (C) 1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Event-driven interface for LEDs on machines - * Added led_start and led_stop- Alex Holden, 28th Dec 1998. - */ -#ifndef ASM_ARM_LEDS_H -#define ASM_ARM_LEDS_H - - -typedef enum { - led_idle_start, - led_idle_end, - led_timer, - led_start, - led_stop, - led_claim, /* override idle & timer leds */ - led_release, /* restore idle & timer leds */ - led_start_timer_mode, - led_stop_timer_mode, - led_green_on, - led_green_off, - led_amber_on, - led_amber_off, - led_red_on, - led_red_off, - led_blue_on, - led_blue_off, - /* - * I want this between led_timer and led_start, but - * someone has decided to export this to user space - */ - led_halted -} led_event_t; - -/* Use this routine to handle LEDs */ - -#ifdef CONFIG_LEDS -extern void (*leds_event)(led_event_t); -#else -#define leds_event(e) -#endif - -#endif diff --git a/include/asm-arm26/limits.h b/include/asm-arm26/limits.h deleted file mode 100644 index 08d8c6600804..000000000000 --- a/include/asm-arm26/limits.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_PIPE_H -#define __ASM_PIPE_H - -#ifndef PAGE_SIZE -#include <asm/page.h> -#endif - -#define PIPE_BUF PAGE_SIZE - -#endif - diff --git a/include/asm-arm26/linkage.h b/include/asm-arm26/linkage.h deleted file mode 100644 index dbe4b4e31a5b..000000000000 --- a/include/asm-arm26/linkage.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -#define __ALIGN .align 0 -#define __ALIGN_STR ".align 0" - -#endif diff --git a/include/asm-arm26/local.h b/include/asm-arm26/local.h deleted file mode 100644 index 6759e9183cef..000000000000 --- a/include/asm-arm26/local.h +++ /dev/null @@ -1,2 +0,0 @@ -//FIXME - nicked from arm32 - check it is correct... -#include <asm-generic/local.h> diff --git a/include/asm-arm26/locks.h b/include/asm-arm26/locks.h deleted file mode 100644 index 81b3bda2ed00..000000000000 --- a/include/asm-arm26/locks.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * linux/include/asm-arm/proc-armo/locks.h - * - * Copyright (C) 2000 Russell King - * Fixes for 26 bit machines, (C) 2000 Dave Gilbert - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Interrupt safe locking assembler. - */ -#ifndef __ASM_PROC_LOCKS_H -#define __ASM_PROC_LOCKS_H - -/* Decrements by 1, fails if value < 0 */ -#define __down_op(ptr,fail) \ - ({ \ - __asm__ __volatile__ ( \ - "@ atomic down operation\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -" ldr lr, [%0]\n" \ -" and ip, ip, #0x0c000003\n" \ -" subs lr, lr, #1\n" \ -" str lr, [%0]\n" \ -" orrmi ip, ip, #0x80000000 @ set N\n" \ -" teqp ip, #0\n" \ -" movmi ip, %0\n" \ -" blmi " #fail \ - : \ - : "r" (ptr) \ - : "ip", "lr", "cc"); \ - }) - -#define __down_op_ret(ptr,fail) \ - ({ \ - unsigned int result; \ - __asm__ __volatile__ ( \ -" @ down_op_ret\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -" ldr lr, [%1]\n" \ -" and ip, ip, #0x0c000003\n" \ -" subs lr, lr, #1\n" \ -" str lr, [%1]\n" \ -" orrmi ip, ip, #0x80000000 @ set N\n" \ -" teqp ip, #0\n" \ -" movmi ip, %1\n" \ -" movpl ip, #0\n" \ -" blmi " #fail "\n" \ -" mov %0, ip" \ - : "=&r" (result) \ - : "r" (ptr) \ - : "ip", "lr", "cc"); \ - result; \ - }) - -#define __up_op(ptr,wake) \ - ({ \ - __asm__ __volatile__ ( \ - "@ up_op\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -" ldr lr, [%0]\n" \ -" and ip, ip, #0x0c000003\n" \ -" adds lr, lr, #1\n" \ -" str lr, [%0]\n" \ -" orrle ip, ip, #0x80000000 @ set N - should this be mi ??? DAG ! \n" \ -" teqp ip, #0\n" \ -" movmi ip, %0\n" \ -" blmi " #wake \ - : \ - : "r" (ptr) \ - : "ip", "lr", "cc"); \ - }) - -/* - * The value 0x01000000 supports up to 128 processors and - * lots of processes. BIAS must be chosen such that sub'ing - * BIAS once per CPU will result in the long remaining - * negative. - */ -#define RW_LOCK_BIAS 0x01000000 -#define RW_LOCK_BIAS_STR "0x01000000" - -/* Decrements by RW_LOCK_BIAS rather than 1, fails if value != 0 */ -#define __down_op_write(ptr,fail) \ - ({ \ - __asm__ __volatile__( \ - "@ down_op_write\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -" and ip, ip, #0x0c000003\n" \ -\ -" ldr lr, [%0]\n" \ -" subs lr, lr, %1\n" \ -" str lr, [%0]\n" \ -\ -" orreq ip, ip, #0x40000000 @ set Z \n"\ -" teqp ip, #0\n" \ -" movne ip, %0\n" \ -" blne " #fail \ - : \ - : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc"); \ - }) - -/* Increments by RW_LOCK_BIAS, wakes if value >= 0 */ -#define __up_op_write(ptr,wake) \ - ({ \ - __asm__ __volatile__( \ - "@ up_op_read\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -\ -" ldr lr, [%0]\n" \ -" and ip, ip, #0x0c000003\n" \ -" adds lr, lr, %1\n" \ -" str lr, [%0]\n" \ -\ -" orrcs ip, ip, #0x20000000 @ set C\n" \ -" teqp ip, #0\n" \ -" movcs ip, %0\n" \ -" blcs " #wake \ - : \ - : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc"); \ - }) - -#define __down_op_read(ptr,fail) \ - __down_op(ptr, fail) - -#define __up_op_read(ptr,wake) \ - ({ \ - __asm__ __volatile__( \ - "@ up_op_read\n" \ -" mov ip, pc\n" \ -" orr lr, ip, #0x08000000\n" \ -" teqp lr, #0\n" \ -\ -" ldr lr, [%0]\n" \ -" and ip, ip, #0x0c000003\n" \ -" adds lr, lr, %1\n" \ -" str lr, [%0]\n" \ -\ -" orreq ip, ip, #0x40000000 @ Set Z \n" \ -" teqp ip, #0\n" \ -" moveq ip, %0\n" \ -" bleq " #wake \ - : \ - : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc"); \ - }) - -#endif diff --git a/include/asm-arm26/mach-types.h b/include/asm-arm26/mach-types.h deleted file mode 100644 index 0aeaedcbac96..000000000000 --- a/include/asm-arm26/mach-types.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Unlike ARM32 this is NOT automatically generated. DONT delete it - * Instead, consider FIXME-ing it so its auto-detected. - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - - -#ifndef __ASSEMBLY__ -extern unsigned int __machine_arch_type; -#endif - -#define MACH_TYPE_ARCHIMEDES 10 -#define MACH_TYPE_A5K 11 - -#ifdef CONFIG_ARCH_ARC -# define machine_arch_type MACH_TYPE_ARCHIMEDES -# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) -#else -# define machine_is_archimedes() (0) -#endif - -#ifdef CONFIG_ARCH_A5K -# define machine_arch_type MACH_TYPE_A5K -# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) -#else -# define machine_is_a5k() (0) -#endif - -#ifndef machine_arch_type -#error Unknown machine type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/include/asm-arm26/map.h b/include/asm-arm26/map.h deleted file mode 100644 index 6e12a7fa5c5d..000000000000 --- a/include/asm-arm26/map.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * linux/include/asm-arm/map.h - * - * Copyright (C) 1999-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Page table mapping constructs and function prototypes - */ -struct map_desc { - unsigned long virtual; - unsigned long physical; - unsigned long length; - unsigned int type; -}; - -struct meminfo; - -extern void create_memmap_holes(struct meminfo *); -extern void memtable_init(struct meminfo *); -extern void iotable_init(struct map_desc *); -extern void setup_io_desc(void); diff --git a/include/asm-arm26/mc146818rtc.h b/include/asm-arm26/mc146818rtc.h deleted file mode 100644 index a234130db8f1..000000000000 --- a/include/asm-arm26/mc146818rtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef _ASM_MC146818RTC_H -#define _ASM_MC146818RTC_H - -#include <asm/irq.h> -#include <asm/io.h> - -#ifndef RTC_PORT -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ -#endif - -/* - * The yet supported machines all access the RTC index register via - * an ISA port access but the way to access the date register differs ... - */ -#define CMOS_READ(addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -inb_p(RTC_PORT(1)); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -outb_p((val),RTC_PORT(1)); \ -}) - -#endif /* _ASM_MC146818RTC_H */ diff --git a/include/asm-arm26/memory.h b/include/asm-arm26/memory.h deleted file mode 100644 index 7c1e5be39060..000000000000 --- a/include/asm-arm26/memory.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linux/include/asm-arm26/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - -/* - * User space: 26MB - */ -#define TASK_SIZE (0x01a00000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -/* - * Page offset: 32MB - */ -#define PAGE_OFFSET (0x02000000UL) -#define PHYS_OFFSET (0x02000000UL) - -#define PHYS_TO_NID(addr) (0) - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * These are *only* valid on the kernel direct mapped RAM memory. - */ -static inline unsigned long virt_to_phys(void *x) -{ - return (unsigned long)x; -} - -static inline void *phys_to_virt(unsigned long x) -{ - return (void *)((unsigned long)x); -} - -#define __pa(x) (unsigned long)(x) -#define __va(x) ((void *)(unsigned long)(x)) - -/* - * Virtual <-> DMA view memory address translations - * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *deprecated*. - */ -#define virt_to_bus(x) ((unsigned long)(x)) -#define bus_to_virt(x) ((void *)((unsigned long)(x))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * page_to_pfn(page) convert a struct page * to a PFN number - * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#define ARCH_PFN_OFFSET (PHYS_PFN_OFFSET) -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((int)(kaddr) >= PAGE_OFFSET && (int)(kaddr) < (unsigned long)high_memory) - -/* - * For BIO. "will die". Kill me when bio_to_phys() and bvec_to_phys() die. - */ -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) - -/* - * We should really eliminate virt_to_bus() here - it's deprecated. - */ -#define page_to_bus(page) (page_address(page)) - -#include <asm-generic/memory_model.h> -#endif diff --git a/include/asm-arm26/mman.h b/include/asm-arm26/mman.h deleted file mode 100644 index 4000a6c1b76b..000000000000 --- a/include/asm-arm26/mman.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ARM_MMAN_H__ -#define __ARM_MMAN_H__ - -#include <asm-generic/mman.h> - -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ -#define MAP_POPULATE 0x8000 /* populate (prefault) page tables */ -#define MAP_NONBLOCK 0x10000 /* do not block on IO */ - -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#endif /* __ARM_MMAN_H__ */ diff --git a/include/asm-arm26/mmu.h b/include/asm-arm26/mmu.h deleted file mode 100644 index 9b8d3d781a1e..000000000000 --- a/include/asm-arm26/mmu.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ARM_MMU_H -#define __ARM_MMU_H - -/* - * The ARM doesn't have a mmu context - */ -typedef struct { } mm_context_t; - -#endif diff --git a/include/asm-arm26/mmu_context.h b/include/asm-arm26/mmu_context.h deleted file mode 100644 index 16c821f81b8d..000000000000 --- a/include/asm-arm26/mmu_context.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * linux/include/asm-arm/mmu_context.h - * - * Copyright (C) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ASM_ARM_MMU_CONTEXT_H -#define __ASM_ARM_MMU_CONTEXT_H - -#include <asm-generic/mm_hooks.h> - -#define init_new_context(tsk,mm) 0 -#define destroy_context(mm) do { } while(0) - -/* - * This is called when "tsk" is about to enter lazy TLB mode. - * - * mm: describes the currently active mm context - * tsk: task which is entering lazy tlb - * cpu: cpu number which is entering lazy tlb - * - * tsk->mm will be NULL - */ -static inline void -enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -/* - * This is the actual mm switch as far as the scheduler - * is concerned. No registers are touched. - */ -static inline void -switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - cpu_switch_mm(next->pgd, next); -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) -{ - cpu_switch_mm(next->pgd, next); -} - -#endif diff --git a/include/asm-arm26/module.h b/include/asm-arm26/module.h deleted file mode 100644 index 1157f178daec..000000000000 --- a/include/asm-arm26/module.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _ASM_ARM_MODULE_H -#define _ASM_ARM_MODULE_H -/* - * This file contains the arm architecture specific module code. - */ - -#endif /* _ASM_ARM_MODULE_H */ diff --git a/include/asm-arm26/msgbuf.h b/include/asm-arm26/msgbuf.h deleted file mode 100644 index 33b35b946eaa..000000000000 --- a/include/asm-arm26/msgbuf.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _ASMARM_MSGBUF_H -#define _ASMARM_MSGBUF_H - -/* - * The msqid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _ASMARM_MSGBUF_H */ diff --git a/include/asm-arm26/namei.h b/include/asm-arm26/namei.h deleted file mode 100644 index 3f5d340110eb..000000000000 --- a/include/asm-arm26/namei.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * linux/include/asm-arm26/namei.h - * - * Routines to handle famous /usr/gnemul - * Derived from the Sparc version of this file - * - * Included from linux/fs/namei.c - */ - -#ifndef __ASMARM_NAMEI_H -#define __ASMARM_NAMEI_H - -#define ARM_BSD_EMUL "usr/gnemul/bsd/" - -static inline char *__emul_prefix(void) -{ - switch (current->personality) { - case PER_BSD: - return ARM_BSD_EMUL; - default: - return NULL; - } -} - -#endif /* __ASMARM_NAMEI_H */ diff --git a/include/asm-arm26/oldlatches.h b/include/asm-arm26/oldlatches.h deleted file mode 100644 index bc87089b2152..000000000000 --- a/include/asm-arm26/oldlatches.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/include/asm-arm/arch-arc/oldlatches.h - * - * Copyright (C) 1996 Russell King, Dave Gilbert - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 04-04-1998 PJB/RMK Merged arc and a5k versions - */ -#ifndef _ASM_ARCH_OLDLATCH_H -#define _ASM_ARCH_OLDLATCH_H - -#define LATCHA_FDSEL0 (1<<0) -#define LATCHA_FDSEL1 (1<<1) -#define LATCHA_FDSEL2 (1<<2) -#define LATCHA_FDSEL3 (1<<3) -#define LATCHA_FDSELALL (0xf) -#define LATCHA_SIDESEL (1<<4) -#define LATCHA_MOTOR (1<<5) -#define LATCHA_INUSE (1<<6) -#define LATCHA_CHANGERST (1<<7) - -#define LATCHB_FDCDENSITY (1<<1) -#define LATCHB_FDCRESET (1<<3) -#define LATCHB_PRINTSTROBE (1<<4) - -/* newval=(oldval & mask)|newdata */ -void oldlatch_bupdate(unsigned char mask,unsigned char newdata); - -/* newval=(oldval & mask)|newdata */ -void oldlatch_aupdate(unsigned char mask,unsigned char newdata); - -#endif - diff --git a/include/asm-arm26/page.h b/include/asm-arm26/page.h deleted file mode 100644 index fa19de28fda0..000000000000 --- a/include/asm-arm26/page.h +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef _ASMARM_PAGE_H -#define _ASMARM_PAGE_H - - -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -extern void __clear_user_page(void *p, unsigned long user); -extern void __copy_user_page(void *to, const void *from, unsigned long user); -extern void copy_page(void *to, const void *from); - -//FIXME these may be wrong on ARM26 -#define clear_user_page(addr,vaddr,pg) \ - do { \ - preempt_disable(); \ - __clear_user_page(addr, vaddr); \ - preempt_enable(); \ - } while (0) - -#define copy_user_page(to,from,vaddr,pg) \ - do { \ - preempt_disable(); \ - __copy_user_page(to, from, vaddr); \ - preempt_enable(); \ - } while (0) - -#define clear_page(page) memzero((void *)(page), PAGE_SIZE) -#define copy_page(to, from) __copy_user_page(to, from, 0); - -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pgd_val(x) ((x).pgd) -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -#else -/* - * .. while these make it easier on the compiler - */ -typedef unsigned long pgd_t; -typedef unsigned long pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgprot_t; - -//FIXME - should these cast to unsigned long? -#define pgd_val(x) (x) -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgprot(x) (x) - -#endif /* STRICT_MM_TYPECHECKS */ -#endif /* !__ASSEMBLY__ */ -#endif /* __KERNEL__ */ - -/* PAGE_SHIFT determines the page size. This is configurable. */ -#if defined(CONFIG_PAGESIZE_16) -#define PAGE_SHIFT 14 /* 16K */ -#else /* default */ -#define PAGE_SHIFT 15 /* 32K */ -#endif - -#define EXEC_PAGESIZE 32768 - -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -#include <asm/memory.h> - -#endif /* !__ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#endif /* __KERNEL__ */ - -#include <asm-generic/page.h> - -#endif diff --git a/include/asm-arm26/param.h b/include/asm-arm26/param.h deleted file mode 100644 index 6b1e52df542e..000000000000 --- a/include/asm-arm26/param.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * linux/include/asm-arm/param.h - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PARAM_H -#define __ASM_PARAM_H - -#ifndef __KERNEL_HZ -#define __KERNEL_HZ 100 -#endif - -#ifdef __KERNEL__ -# define HZ __KERNEL_HZ /* Internal kernel timer frequency */ -# define USER_HZ 100 /* User interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#else -# define HZ 100 -#endif - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -/* max length of hostname */ -#define MAXHOSTNAMELEN 64 - -#endif - diff --git a/include/asm-arm26/parport.h b/include/asm-arm26/parport.h deleted file mode 100644 index f2f90c76ddd1..000000000000 --- a/include/asm-arm26/parport.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * linux/include/asm-arm/parport.h: ARM-specific parport initialisation - * - * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> - * - * This file should only be included by drivers/parport/parport_pc.c. - */ - -#ifndef __ASMARM_PARPORT_H -#define __ASMARM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) -{ - return parport_pc_find_isa_ports (autoirq, autodma); -} - -#endif /* !(_ASMARM_PARPORT_H) */ diff --git a/include/asm-arm26/pci.h b/include/asm-arm26/pci.h deleted file mode 100644 index 6ac67ed7718c..000000000000 --- a/include/asm-arm26/pci.h +++ /dev/null @@ -1,6 +0,0 @@ -/* Should not be needed. IDE stupidity */ -/* JMA 18.05.03 - is kinda needed, if only to tell it we don't have a PCI bus */ - -#define PCI_DMA_BUS_IS_PHYS 0 -#define pcibios_scan_all_fns(a, b) 0 - diff --git a/include/asm-arm26/percpu.h b/include/asm-arm26/percpu.h deleted file mode 100644 index b4e32d8ec072..000000000000 --- a/include/asm-arm26/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARM_PERCPU -#define __ARM_PERCPU - -#include <asm-generic/percpu.h> - -#endif diff --git a/include/asm-arm26/pgalloc.h b/include/asm-arm26/pgalloc.h deleted file mode 100644 index 7725af3ddb4d..000000000000 --- a/include/asm-arm26/pgalloc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * linux/include/asm-arm/pgalloc.h - * - * Copyright (C) 2000-2001 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _ASMARM_PGALLOC_H -#define _ASMARM_PGALLOC_H - -#include <asm/processor.h> -#include <asm/cacheflush.h> -#include <asm/tlbflush.h> -#include <linux/slab.h> - -extern struct kmem_cache *pte_cache; - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr){ - return kmem_cache_alloc(pte_cache, GFP_KERNEL); -} - -static inline void pte_free_kernel(pte_t *pte){ - if (pte) - kmem_cache_free(pte_cache, pte); -} - -/* - * Populate the pmdp entry with a pointer to the pte. This pmd is part - * of the mm address space. - * - * If 'mm' is the init tasks mm, then we are doing a vmalloc, and we - * need to set stuff up correctly for it. - */ -static inline void -pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) -{ -//FIXME - is this doing the right thing? - set_pmd(pmdp, (unsigned long)ptep | 1/*FIXME _PMD_PRESENT*/); -} - -/* - * FIXME - We use the old 2.5.5-rmk1 hack for this. - * This is not truly correct, but should be functional. - */ -#define pte_alloc_one(mm,addr) ((struct page *)pte_alloc_one_kernel(mm,addr)) -#define pte_free(pte) pte_free_kernel((pte_t *)pte) -#define pmd_populate(mm,pmdp,ptep) pmd_populate_kernel(mm,pmdp,(pte_t *)ptep) - -/* - * Since we have only two-level page tables, these are trivial - * - * trick __pmd_alloc into optimising away. The actual value is irrelevant though as it - * is thrown away. It just cant be zero. -IM - */ - -#define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) -#define pmd_free(pmd) do { } while (0) -#define pgd_populate(mm,pmd,pte) BUG() - -extern pgd_t *get_pgd_slow(struct mm_struct *mm); -extern void free_pgd_slow(pgd_t *pgd); - -#define pgd_alloc(mm) get_pgd_slow(mm) -#define pgd_free(pgd) free_pgd_slow(pgd) - -#define check_pgt_cache() do { } while (0) - -#endif diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h deleted file mode 100644 index 55a1a697d12b..000000000000 --- a/include/asm-arm26/pgtable.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * linux/include/asm-arm26/pgtable.h - * - * Copyright (C) 2000-2002 Russell King - * Copyright (C) 2003 Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _ASMARM_PGTABLE_H -#define _ASMARM_PGTABLE_H - -#include <asm-generic/4level-fixup.h> - -#include <asm/memory.h> - -/* - * The table below defines the page protection levels that we insert into our - * Linux page table version. These get translated into the best that the - * architecture can perform. Note that on most ARM hardware: - * 1) We cannot do execute protection - * 2) If we could do execute protection, then read is implied - * 3) write implies read permissions - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED - -/* - * PMD_SHIFT determines the size of the area a second-level page table can map - * PGDIR_SHIFT determines what a third-level page table entry can map - */ -#define PGD_SHIFT 25 -#define PMD_SHIFT 20 - -#define PGD_SIZE (1UL << PGD_SHIFT) -#define PGD_MASK (~(PGD_SIZE-1)) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* The kernel likes to use these names for the above (ick) */ -#define PGDIR_SIZE PGD_SIZE -#define PGDIR_MASK PGD_MASK - -#define PTRS_PER_PGD 32 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PTE 32 - -/* - * This is the lowest virtual address we can permit any user space - * mapping to be mapped at. This is particularly important for - * non-high vector CPUs. - */ -#define FIRST_USER_ADDRESS PAGE_SIZE - -#define FIRST_USER_PGD_NR 1 -#define USER_PTRS_PER_PGD ((TASK_SIZE/PGD_SIZE) - FIRST_USER_PGD_NR) - -// FIXME - WTF? -#define LIBRARY_TEXT_START 0x0c000000 - - - -#ifndef __ASSEMBLY__ -extern void __pte_error(const char *file, int line, unsigned long val); -extern void __pmd_error(const char *file, int line, unsigned long val); -extern void __pgd_error(const char *file, int line, unsigned long val); - -#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) -#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) -#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -extern struct page *empty_zero_page; -#define ZERO_PAGE(vaddr) (empty_zero_page) - -#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) -#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) -#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) -#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) -#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) - -/* - * Terminology: PGD = Page Directory, PMD = Page Middle Directory, - * PTE = Page Table Entry - * - * on arm26 we have no 2nd level page table. we simulate this by removing the - * PMD. - * - * pgd_none is 0 to prevernt pmd_alloc() calling __pmd_alloc(). This causes it - * to return pmd_offset(pgd,addr) which is a pointer to the pgd (IOW, a no-op). - * - * however, to work this way, whilst we are allocating 32 pgds, containing 32 - * PTEs, the actual work is done on the PMDs, thus: - * - * instead of mm->pgd->pmd->pte - * we have mm->pgdpmd->pte - * - * IOW, think of PGD operations and PMD ones as being the same thing, just - * that PGD stuff deals with the mm_struct side of things, wheras PMD stuff - * deals with the pte side of things. - * - * additionally, we store some bits in the PGD and PTE pointers: - * PGDs: - * o The lowest (1) bit of the PGD is to determine if it is present or swap. - * o The 2nd bit of the PGD is unused and must be zero. - * o The top 6 bits of the PGD must be zero. - * PTEs: - * o The lower 5 bits of a pte are flags. bit 1 is the 'present' flag. The - * others determine the pages attributes. - * - * the pgd_val, pmd_val, and pte_val macros seem to be private to our code. - * They get the RAW value of the PGD/PMD/PTE entry, including our flags - * encoded into the pointers. - * - * The pgd_offset, pmd_offset, and pte_offset macros are used by the kernel, - * so they shouldnt have our flags attached. - * - * If you understood that, feel free to explain it to me... - * - */ - -#define _PMD_PRESENT (0x01) - -/* These definitions allow us to optimise out stuff like pmd_alloc() */ -#define pgd_none(pgd) (0) -#define pgd_bad(pgd) (0) -#define pgd_present(pgd) (1) -#define pgd_clear(pgdp) do { } while (0) - -/* Whilst these handle our actual 'page directory' (the agglomeration of pgd and pmd) - */ -#define pmd_none(pmd) (!pmd_val(pmd)) -#define pmd_bad(pmd) ((pmd_val(pmd) & 0xfc000002)) -#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT) -#define set_pmd(pmd_ptr, pmd) ((*(pmd_ptr)) = (pmd)) -#define pmd_clear(pmdp) set_pmd(pmdp, __pmd(0)) - -/* and these handle our pte tables */ -#define pte_none(pte) (!pte_val(pte)) -#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) -#define set_pte(pte_ptr, pte) ((*(pte_ptr)) = (pte)) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) -#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0)) - -/* macros to ease the getting of pointers to stuff... */ -#define pgd_offset(mm, addr) ((pgd_t *)(mm)->pgd + __pgd_index(addr)) -#define pmd_offset(pgd, addr) ((pmd_t *)(pgd)) -#define pte_offset(pmd, addr) ((pte_t *)pmd_page(*(pmd)) + __pte_index(addr)) - -/* there is no __pmd_index as we dont use pmds */ -#define __pgd_index(addr) ((addr) >> PGD_SHIFT) -#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) - - -/* Keep the kernel happy */ -#define pgd_index(addr) __pgd_index(addr) -#define pgd_offset_k(addr) (pgd_offset(&init_mm, addr)) - -/* - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) FIXME: surely 1 page not 4k ? - */ -#define VMALLOC_START 0x01a00000 -#define VMALLOC_END 0x01c00000 - -/* Is pmd_page supposed to return a pointer to a page in some arches? ours seems to - * return a pointer to memory (no special alignment) - */ -#define pmd_page(pmd) ((struct page *)(pmd_val((pmd)) & ~_PMD_PRESENT)) -#define pmd_page_vaddr(pmd) ((pte_t *)(pmd_val((pmd)) & ~_PMD_PRESENT)) - -#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) - -#define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) -#define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) -#define pte_unmap(pte) do { } while (0) -#define pte_unmap_nested(pte) do { } while (0) - - -#define _PAGE_PRESENT 0x01 -#define _PAGE_READONLY 0x02 -#define _PAGE_NOT_USER 0x04 -#define _PAGE_OLD 0x08 -#define _PAGE_CLEAN 0x10 - -// an old page has never been read. -// a clean page has never been written. - -/* -- present -- -- !dirty -- --- !write --- ---- !user --- */ -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_CLEAN | _PAGE_READONLY | _PAGE_NOT_USER) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_CLEAN ) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_CLEAN | _PAGE_READONLY ) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_CLEAN | _PAGE_READONLY ) -#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_NOT_USER) - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_OLD | _PAGE_CLEAN) - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -#define pte_write(pte) (!(pte_val(pte) & _PAGE_READONLY)) -#define pte_dirty(pte) (!(pte_val(pte) & _PAGE_CLEAN)) -#define pte_young(pte) (!(pte_val(pte) & _PAGE_OLD)) -//ONLY when !pte_present() I think. nicked from arm32 (FIXME!) -#define pte_file(pte) (!(pte_val(pte) & _PAGE_OLD)) - -#define PTE_BIT_FUNC(fn,op) \ -static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } - -PTE_BIT_FUNC(wrprotect, |= _PAGE_READONLY); -PTE_BIT_FUNC(mkwrite, &= ~_PAGE_READONLY); -PTE_BIT_FUNC(mkclean, |= _PAGE_CLEAN); -PTE_BIT_FUNC(mkdirty, &= ~_PAGE_CLEAN); -PTE_BIT_FUNC(mkold, |= _PAGE_OLD); -PTE_BIT_FUNC(mkyoung, &= ~_PAGE_OLD); - -/* - * We don't store cache state bits in the page table here. FIXME - or do we? - */ -#define pgprot_noncached(prot) (prot) -#define pgprot_writecombine(prot) (prot) //FIXME - is a no-op? - -extern void pgtable_cache_init(void); - -//FIXME - nicked from arm32 and brutally hacked. probably wrong. -#define pte_to_pgoff(x) (pte_val(x) >> 2) -#define pgoff_to_pte(x) __pte(((x) << 2) & ~_PAGE_OLD) - -//FIXME - next line borrowed from arm32. is it right? -#define PTE_FILE_MAX_BITS 30 - - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); - return pte; -} - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; - -/* Encode and decode a swap entry. - * - * We support up to 32GB of swap on 4k machines - */ -#define __swp_type(x) (((x).val >> 2) & 0x7f) -#define __swp_offset(x) ((x).val >> 9) -#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) - -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ -/* FIXME: this is not correct */ -#define kern_addr_valid(addr) (1) - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) -{ - pte_t pte; - pte_val(pte) = physpage | pgprot_val(pgprot); - return pte; -} - - -#include <asm-generic/pgtable.h> - -/* - * remap a physical page `pfn' of size `size' with page protection `prot' - * into virtual address `from' - */ -#define io_remap_pfn_range(vma,from,pfn,size,prot) \ - remap_pfn_range(vma, from, pfn, size, prot) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASMARM_PGTABLE_H */ diff --git a/include/asm-arm26/poll.h b/include/asm-arm26/poll.h deleted file mode 100644 index 1170e7065f6a..000000000000 --- a/include/asm-arm26/poll.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASMARM_POLL_H -#define __ASMARM_POLL_H - -#include <asm-generic/poll.h> - -#undef POLLREMOVE - -#endif diff --git a/include/asm-arm26/posix_types.h b/include/asm-arm26/posix_types.h deleted file mode 100644 index f8d1eb4f4cb1..000000000000 --- a/include/asm-arm26/posix_types.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] |= (1<<((fd) & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] &= ~(1<<((fd) & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] & (1<<((fd) & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset ((fdsetp), 0, sizeof (*(fd_set *)(fdsetp)))) - -#endif - -#endif diff --git a/include/asm-arm26/proc-fns.h b/include/asm-arm26/proc-fns.h deleted file mode 100644 index a83100454055..000000000000 --- a/include/asm-arm26/proc-fns.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * linux/include/asm-arm26/proc-fns.h - * - * Copyright (C) 2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASSEMBLY__ - -#include <asm/page.h> - -/* - * Don't change this structure - ASM code - * relies on it. - */ -extern struct processor { - /* check for any bugs */ - void (*_check_bugs)(void); - /* Set up any processor specifics */ - void (*_proc_init)(void); - /* Disable any processor specifics */ - void (*_proc_fin)(void); - /* set the MEMC hardware mappings */ - void (*_set_pgd)(pgd_t *pgd); - /* XCHG */ - unsigned long (*_xchg_1)(unsigned long x, volatile void *ptr); - unsigned long (*_xchg_4)(unsigned long x, volatile void *ptr); -} processor; - -extern const struct processor arm2_processor_functions; -extern const struct processor arm250_processor_functions; -extern const struct processor arm3_processor_functions; - -#define cpu_check_bugs() processor._check_bugs() -#define cpu_proc_init() processor._proc_init() -#define cpu_proc_fin() processor._proc_fin() -#define cpu_do_idle() do { } while (0) -#define cpu_switch_mm(pgd,mm) processor._set_pgd(pgd) -#define cpu_xchg_1(x,ptr) processor._xchg_1(x,ptr) -#define cpu_xchg_4(x,ptr) processor._xchg_4(x,ptr) - - -//FIXME - these shouldnt be in proc-fn.h -extern void cpu_memc_update_all(pgd_t *pgd); -extern void cpu_memc_update_entry(pgd_t *pgd, unsigned long phys_pte, unsigned long log_addr); - -#endif diff --git a/include/asm-arm26/processor.h b/include/asm-arm26/processor.h deleted file mode 100644 index 1d2d5f7b467b..000000000000 --- a/include/asm-arm26/processor.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/include/asm-arm26/processor.h - * - * Copyright (C) 1995 Russell King - * Copyright (C) 2003 Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_PROCESSOR_H -#define __ASM_ARM_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#ifdef __KERNEL__ - -#include <asm/atomic.h> -#include <asm/ptrace.h> -#include <linux/string.h> - -#define KERNEL_STACK_SIZE 4096 - -typedef struct { - void (*put_byte)(void); /* Special calling convention */ - void (*get_byte)(void); /* Special calling convention */ - void (*put_half)(void); /* Special calling convention */ - void (*get_half)(void); /* Special calling convention */ - void (*put_word)(void); /* Special calling convention */ - void (*get_word)(void); /* Special calling convention */ - void (*put_dword)(void); /* Special calling convention */ - unsigned long (*copy_from_user)(void *to, const void *from, unsigned long sz); - unsigned long (*copy_to_user)(void *to, const void *from, unsigned long sz); - unsigned long (*clear_user)(void *addr, unsigned long sz); - unsigned long (*strncpy_from_user)(char *to, const char *from, unsigned long sz); - unsigned long (*strnlen_user)(const char *s, long n); -} uaccess_t; - -extern uaccess_t uaccess_user, uaccess_kernel; - -#define EXTRA_THREAD_STRUCT \ - uaccess_t *uaccess; /* User access functions*/ - -#define EXTRA_THREAD_STRUCT_INIT \ - .uaccess = &uaccess_kernel, - -// FIXME?!! - -#define start_thread(regs,pc,sp) \ -({ \ - unsigned long *stack = (unsigned long *)sp; \ - set_fs(USER_DS); \ - memzero(regs->uregs, sizeof (regs->uregs)); \ - regs->ARM_pc = pc | ~0xfc000003; /* pc */ \ - regs->ARM_sp = sp; /* sp */ \ - regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ - regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ - regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ -}) - -#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1020]) -#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1018]) - -struct debug_entry { - u32 address; - u32 insn; -}; - -struct debug_info { - int nsaved; - struct debug_entry bp[2]; -}; - -struct thread_struct { - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - /* debugging */ - struct debug_info debug; - EXTRA_THREAD_STRUCT -}; - -#define INIT_THREAD { \ -EXTRA_THREAD_STRUCT_INIT \ -} - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -unsigned long get_wchan(struct task_struct *p); - -#define cpu_relax() barrier() - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -/* - * Create a new kernel thread - */ -extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -#endif - -#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/include/asm-arm26/procinfo.h b/include/asm-arm26/procinfo.h deleted file mode 100644 index b28624db69ff..000000000000 --- a/include/asm-arm26/procinfo.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * linux/include/asm-arm/procinfo.h - * - * Copyright (C) 1996-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROCINFO_H -#define __ASM_PROCINFO_H - -#ifndef __ASSEMBLY__ - -//struct processor; -//struct cpu_user_fns; - -struct proc_info_item { - const char *manufacturer; - const char *cpu_name; -}; - -/* - * Note! struct processor is always defined if we're - * using MULTI_CPU, otherwise this entry is unused, - * but still exists. - * - * NOTE! The following structure is defined by assembly - * language, NOT C code. For more information, check: - * arch/arm/mm/proc-*.S and arch/arm/kernel/head-armv.S - */ -struct proc_info_list { - unsigned int cpu_val; - unsigned int cpu_mask; - const char *arch_name; - const char *elf_name; - unsigned int elf_hwcap; - struct proc_info_item *info; - struct processor *proc; -}; - -#endif /* __ASSEMBLY__ */ - -#define PROC_INFO_SZ 48 - -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 - -#endif diff --git a/include/asm-arm26/ptrace.h b/include/asm-arm26/ptrace.h deleted file mode 100644 index 6a46b5ae1156..000000000000 --- a/include/asm-arm26/ptrace.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __ASM_ARM_PTRACE_H -#define __ASM_ARM_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -#define PTRACE_OLDSETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#define MODE_USR26 0x00000000 -#define MODE_FIQ26 0x00000001 -#define MODE_IRQ26 0x00000002 -#define MODE_SVC26 0x00000003 -#define MODE_MASK 0x00000003 - -#define PSR_F_BIT 0x04000000 -#define PSR_I_BIT 0x08000000 -#define PSR_V_BIT 0x10000000 -#define PSR_C_BIT 0x20000000 -#define PSR_Z_BIT 0x40000000 -#define PSR_N_BIT 0x80000000 - -#define PCMASK 0xfc000003 - - -#ifndef __ASSEMBLY__ - -#define pc_pointer(v) ((v) & ~PCMASK) /* convert v to pc type address */ -#define instruction_pointer(regs) (pc_pointer((regs)->ARM_pc)) /* get pc */ -#define profile_pc(regs) instruction_pointer(regs) - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[17]; -}; - -#define ARM_pc uregs[15] -#define ARM_lr uregs[14] -#define ARM_sp uregs[13] -#define ARM_ip uregs[12] -#define ARM_fp uregs[11] -#define ARM_r10 uregs[10] -#define ARM_r9 uregs[9] -#define ARM_r8 uregs[8] -#define ARM_r7 uregs[7] -#define ARM_r6 uregs[6] -#define ARM_r5 uregs[5] -#define ARM_r4 uregs[4] -#define ARM_r3 uregs[3] -#define ARM_r2 uregs[2] -#define ARM_r1 uregs[1] -#define ARM_r0 uregs[0] -#define ARM_ORIG_r0 uregs[16] - -#ifdef __KERNEL__ - -#define processor_mode(regs) \ - ((regs)->ARM_pc & MODE_MASK) - -#define user_mode(regs) \ - (processor_mode(regs) == MODE_USR26) - -#define interrupts_enabled(regs) \ - (!((regs)->ARM_pc & PSR_I_BIT)) - -#define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_pc & PSR_F_BIT)) - -#define condition_codes(regs) \ - ((regs)->ARM_pc & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT)) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if (user_mode(regs) && - (regs->ARM_pc & (PSR_F_BIT | PSR_I_BIT)) == 0) - return 1; - - /* - * force it to be something sensible - */ - regs->ARM_pc &= ~(MODE_MASK | PSR_F_BIT | PSR_I_BIT); - - return 0; -} - -extern void show_regs(struct pt_regs *); - -#define predicate(x) (x & 0xf0000000) -#define PREDICATE_ALWAYS 0xe0000000 - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif - diff --git a/include/asm-arm26/resource.h b/include/asm-arm26/resource.h deleted file mode 100644 index 734b581b5b6a..000000000000 --- a/include/asm-arm26/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ARM_RESOURCE_H -#define _ARM_RESOURCE_H - -#include <asm-generic/resource.h> - -#endif diff --git a/include/asm-arm26/scatterlist.h b/include/asm-arm26/scatterlist.h deleted file mode 100644 index d9c056c7784e..000000000000 --- a/include/asm-arm26/scatterlist.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _ASMARM_SCATTERLIST_H -#define _ASMARM_SCATTERLIST_H - -#include <asm/types.h> - -struct scatterlist { - struct page *page; /* buffer page */ - unsigned int offset; /* buffer offset */ - dma_addr_t dma_address; /* dma address */ - unsigned int length; /* length */ - char *__address; /* for set_dma_addr */ -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - -#define ISA_DMA_THRESHOLD (0xffffffff) - -#endif /* _ASMARM_SCATTERLIST_H */ diff --git a/include/asm-arm26/sections.h b/include/asm-arm26/sections.h deleted file mode 100644 index 10b6370efad0..000000000000 --- a/include/asm-arm26/sections.h +++ /dev/null @@ -1,2 +0,0 @@ -//FIXME - nicked from arm32 - check its correct. -#include <asm-generic/sections.h> diff --git a/include/asm-arm26/segment.h b/include/asm-arm26/segment.h deleted file mode 100644 index 9e24c21f6304..000000000000 --- a/include/asm-arm26/segment.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_ARM_SEGMENT_H -#define __ASM_ARM_SEGMENT_H - -#define __KERNEL_CS 0x0 -#define __KERNEL_DS 0x0 - -#define __USER_CS 0x1 -#define __USER_DS 0x1 - -#endif /* __ASM_ARM_SEGMENT_H */ - diff --git a/include/asm-arm26/semaphore-helper.h b/include/asm-arm26/semaphore-helper.h deleted file mode 100644 index 1d7f1987edb9..000000000000 --- a/include/asm-arm26/semaphore-helper.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef ASMARM_SEMAPHORE_HELPER_H -#define ASMARM_SEMAPHORE_HELPER_H - -/* - * These two _must_ execute atomically wrt each other. - */ -static inline void wake_one_more(struct semaphore * sem) -{ - unsigned long flags; - - spin_lock_irqsave(&semaphore_wake_lock, flags); - if (atomic_read(&sem->count) <= 0) - sem->waking++; - spin_unlock_irqrestore(&semaphore_wake_lock, flags); -} - -static inline int waking_non_zero(struct semaphore *sem) -{ - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&semaphore_wake_lock, flags); - if (sem->waking > 0) { - sem->waking--; - ret = 1; - } - spin_unlock_irqrestore(&semaphore_wake_lock, flags); - return ret; -} - -/* - * waking non zero interruptible - * 1 got the lock - * 0 go to sleep - * -EINTR interrupted - * - * We must undo the sem->count down_interruptible() increment while we are - * protected by the spinlock in order to make this atomic_inc() with the - * atomic_read() in wake_one_more(), otherwise we can race. -arca - */ -static inline int waking_non_zero_interruptible(struct semaphore *sem, - struct task_struct *tsk) -{ - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&semaphore_wake_lock, flags); - if (sem->waking > 0) { - sem->waking--; - ret = 1; - } else if (signal_pending(tsk)) { - atomic_inc(&sem->count); - ret = -EINTR; - } - spin_unlock_irqrestore(&semaphore_wake_lock, flags); - return ret; -} - -/* - * waking_non_zero_try_lock: - * 1 failed to lock - * 0 got the lock - * - * We must undo the sem->count down_interruptible() increment while we are - * protected by the spinlock in order to make this atomic_inc() with the - * atomic_read() in wake_one_more(), otherwise we can race. -arca - */ -static inline int waking_non_zero_trylock(struct semaphore *sem) -{ - unsigned long flags; - int ret = 1; - - spin_lock_irqsave(&semaphore_wake_lock, flags); - if (sem->waking <= 0) - atomic_inc(&sem->count); - else { - sem->waking--; - ret = 0; - } - spin_unlock_irqrestore(&semaphore_wake_lock, flags); - return ret; -} - -#endif diff --git a/include/asm-arm26/semaphore.h b/include/asm-arm26/semaphore.h deleted file mode 100644 index 1fda54375ed8..000000000000 --- a/include/asm-arm26/semaphore.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/include/asm-arm26/semaphore.h - */ -#ifndef __ASM_ARM_SEMAPHORE_H -#define __ASM_ARM_SEMAPHORE_H - -#include <linux/linkage.h> -#include <linux/spinlock.h> -#include <linux/wait.h> -#include <linux/rwsem.h> - -#include <asm/atomic.h> -#include <asm/locks.h> - -struct semaphore { - atomic_t count; - int sleepers; - wait_queue_head_t wait; -}; - -#define __SEMAPHORE_INIT(name, n) \ -{ \ - .count = ATOMIC_INIT(n), \ - .sleepers = 0, \ - .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \ -} - -#define __DECLARE_SEMAPHORE_GENERIC(name,count) \ - struct semaphore name = __SEMAPHORE_INIT(name,count) - -#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) -#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) - -static inline void sema_init(struct semaphore *sem, int val) -{ - atomic_set(&sem->count, val); - sem->sleepers = 0; - init_waitqueue_head(&sem->wait); -} - -static inline void init_MUTEX(struct semaphore *sem) -{ - sema_init(sem, 1); -} - -static inline void init_MUTEX_LOCKED(struct semaphore *sem) -{ - sema_init(sem, 0); -} - -/* - * special register calling convention - */ -asmlinkage void __down_failed(void); -asmlinkage int __down_interruptible_failed(void); -asmlinkage int __down_trylock_failed(void); -asmlinkage void __up_wakeup(void); - -extern void __down(struct semaphore * sem); -extern int __down_interruptible(struct semaphore * sem); -extern int __down_trylock(struct semaphore * sem); -extern void __up(struct semaphore * sem); - -/* - * This is ugly, but we want the default case to fall through. - * "__down" is the actual routine that waits... - */ -static inline void down(struct semaphore * sem) -{ - might_sleep(); - __down_op(sem, __down_failed); -} - -/* - * This is ugly, but we want the default case to fall through. - * "__down_interruptible" is the actual routine that waits... - */ -static inline int down_interruptible (struct semaphore * sem) -{ - might_sleep(); - return __down_op_ret(sem, __down_interruptible_failed); -} - -static inline int down_trylock(struct semaphore *sem) -{ - return __down_op_ret(sem, __down_trylock_failed); -} - -/* - * Note! This is subtle. We jump to wake people up only if - * the semaphore was negative (== somebody was waiting on it). - * The default case (no contention) will result in NO - * jumps for both down() and up(). - */ -static inline void up(struct semaphore * sem) -{ - __up_op(sem, __up_wakeup); -} - -#endif diff --git a/include/asm-arm26/sembuf.h b/include/asm-arm26/sembuf.h deleted file mode 100644 index 1c0283954289..000000000000 --- a/include/asm-arm26/sembuf.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASMARM_SEMBUF_H -#define _ASMARM_SEMBUF_H - -/* - * The semid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASMARM_SEMBUF_H */ diff --git a/include/asm-arm26/serial.h b/include/asm-arm26/serial.h deleted file mode 100644 index dd86a716cb0b..000000000000 --- a/include/asm-arm26/serial.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * linux/include/asm-arm/serial.h - * - * Copyright (C) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 15-10-1996 RMK Created - */ - -#ifndef __ASM_SERIAL_H -#define __ASM_SERIAL_H - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (1843200 / 16) - -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) - -#if defined(CONFIG_ARCH_A5K) - /* UART CLK PORT IRQ FLAGS */ - -#define SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ - -#else - -#define SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */ - -#endif - -#endif diff --git a/include/asm-arm26/setup.h b/include/asm-arm26/setup.h deleted file mode 100644 index e82562306475..000000000000 --- a/include/asm-arm26/setup.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See Documentation/arm/Setup - * for more info. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -#define COMMAND_LINE_SIZE 1024 - -#ifdef __KERNEL__ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives */ -/* - * this one accidentally used virtual addresses - as such, - * it's deprecated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __used __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm26/shmbuf.h b/include/asm-arm26/shmbuf.h deleted file mode 100644 index 2e5c67ba1c97..000000000000 --- a/include/asm-arm26/shmbuf.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _ASMARM_SHMBUF_H -#define _ASMARM_SHMBUF_H - -/* - * The shmid64_ds structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASMARM_SHMBUF_H */ diff --git a/include/asm-arm26/shmparam.h b/include/asm-arm26/shmparam.h deleted file mode 100644 index d3748686631e..000000000000 --- a/include/asm-arm26/shmparam.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASMARM_SHMPARAM_H -#define _ASMARM_SHMPARAM_H - -#ifndef SHMMAX -#define SHMMAX 0x003fa000 -#endif - -/* - * This should be the size of the virtually indexed cache/ways, - * or page size, whichever is greater since the cache aliases - * every size/ways bytes. - */ -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _ASMARM_SHMPARAM_H */ diff --git a/include/asm-arm26/sigcontext.h b/include/asm-arm26/sigcontext.h deleted file mode 100644 index 013ad2074fc7..000000000000 --- a/include/asm-arm26/sigcontext.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _ASMARM_SIGCONTEXT_H -#define _ASMARM_SIGCONTEXT_H - -/* - * Signal context structure - contains all info to do with the state - * before the signal handler was invoked. Note: only add new entries - * to the end of the structure. - */ -struct sigcontext { - unsigned long trap_no; - unsigned long error_code; - unsigned long oldmask; - unsigned long arm_r0; - unsigned long arm_r1; - unsigned long arm_r2; - unsigned long arm_r3; - unsigned long arm_r4; - unsigned long arm_r5; - unsigned long arm_r6; - unsigned long arm_r7; - unsigned long arm_r8; - unsigned long arm_r9; - unsigned long arm_r10; - unsigned long arm_fp; - unsigned long arm_ip; - unsigned long arm_sp; - unsigned long arm_lr; - unsigned long arm_pc; - unsigned long fault_address; -}; - - -#endif diff --git a/include/asm-arm26/siginfo.h b/include/asm-arm26/siginfo.h deleted file mode 100644 index 5e21852e6039..000000000000 --- a/include/asm-arm26/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASMARM_SIGINFO_H -#define _ASMARM_SIGINFO_H - -#include <asm-generic/siginfo.h> - -#endif diff --git a/include/asm-arm26/signal.h b/include/asm-arm26/signal.h deleted file mode 100644 index 967ba4947e40..000000000000 --- a/include/asm-arm26/signal.h +++ /dev/null @@ -1,176 +0,0 @@ -#ifndef _ASMARM_SIGNAL_H -#define _ASMARM_SIGNAL_H - -#include <linux/types.h> - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -#define SIGSWI 32 - -/* - * SA_FLAGS values: - * - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_SIGINFO deliver the signal with SIGINFO structs - * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task - * is running in 26-bit. - * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NODEFER prevents the current signal from being masked in the handler. - * SA_RESETHAND clears the handler when the signal is delivered. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_THIRTYTWO 0x02000000 -#define SA_RESTORER 0x04000000 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#ifdef __KERNEL__ -#define SA_IRQNOMASK 0x08000000 -#endif - -#include <asm-generic/signal.h> - -#ifdef __KERNEL__ -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ -#include <asm/sigcontext.h> - -#define sigmask(sig) (1UL << ((sig) - 1)) -#endif - - -#ifdef __KERNEL__ -#include <asm/sigcontext.h> -#define ptrace_signal_deliver(regs, cookie) do { } while (0) -#endif - - -#endif diff --git a/include/asm-arm26/sizes.h b/include/asm-arm26/sizes.h deleted file mode 100644 index f8d92ca12040..000000000000 --- a/include/asm-arm26/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/include/asm-arm26/smp.h b/include/asm-arm26/smp.h deleted file mode 100644 index 38349ec8b61b..000000000000 --- a/include/asm-arm26/smp.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_SMP_H -#define __ASM_SMP_H - - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -#endif diff --git a/include/asm-arm26/socket.h b/include/asm-arm26/socket.h deleted file mode 100644 index 65a1a64bf934..000000000000 --- a/include/asm-arm26/socket.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _ASMARM_SOCKET_H -#define _ASMARM_SOCKET_H - -#include <asm/sockios.h> - -/* For setsockopt(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#endif /* _ASM_SOCKET_H */ diff --git a/include/asm-arm26/sockios.h b/include/asm-arm26/sockios.h deleted file mode 100644 index a2588a2512df..000000000000 --- a/include/asm-arm26/sockios.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ARCH_ARM_SOCKIOS_H -#define __ARCH_ARM_SOCKIOS_H - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif diff --git a/include/asm-arm26/spinlock.h b/include/asm-arm26/spinlock.h deleted file mode 100644 index e92e81deb4fd..000000000000 --- a/include/asm-arm26/spinlock.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SPINLOCK_H -#define __ASM_SPINLOCK_H - -#error ARM architecture does not support SMP spin locks - -#endif /* __ASM_SPINLOCK_H */ diff --git a/include/asm-arm26/stat.h b/include/asm-arm26/stat.h deleted file mode 100644 index e4abc4fa0850..000000000000 --- a/include/asm-arm26/stat.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef _ASMARM_STAT_H -#define _ASMARM_STAT_H - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -struct stat { - unsigned short st_dev; - unsigned short __pad1; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* Future possible st_blocks hi bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; - - unsigned long long st_ino; -}; - -#endif diff --git a/include/asm-arm26/statfs.h b/include/asm-arm26/statfs.h deleted file mode 100644 index 776dbc8f7623..000000000000 --- a/include/asm-arm26/statfs.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _ASMARM_STATFS_H -#define _ASMARM_STATFS_H - -//FIXME - this may not be appropriate for arm26. check it out. - -#include <asm-generic/statfs.h> - -#endif diff --git a/include/asm-arm26/string.h b/include/asm-arm26/string.h deleted file mode 100644 index 2a8ab162412f..000000000000 --- a/include/asm-arm26/string.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#define __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#define __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#define __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#define __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#define __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#define __HAVE_ARCH_MEMZERO -#define __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -extern void __memzero(void *ptr, __kernel_size_t n); - -#define memset(p,v,n) \ - ({ \ - if ((n) != 0) { \ - if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ - else \ - memset((p),(v),(n)); \ - } \ - (p); \ - }) - -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) - -#endif diff --git a/include/asm-arm26/suspend.h b/include/asm-arm26/suspend.h deleted file mode 100644 index 5e4c1cc0c19d..000000000000 --- a/include/asm-arm26/suspend.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifdef _ASMARM_SUSPEND_H -#define _ASMARM_SUSPEND_H - -#endif diff --git a/include/asm-arm26/sysirq.h b/include/asm-arm26/sysirq.h deleted file mode 100644 index 81dca90d9a3f..000000000000 --- a/include/asm-arm26/sysirq.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * linux/include/asm-arm/arch-arc/irqs.h - * - * Copyright (C) 1996 Russell King, Dave Gilbert - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 04-04-1998 PJB Merged arc and a5k versions - */ - - -#if defined(CONFIG_ARCH_A5K) -#define IRQ_PRINTER 0 -#define IRQ_BATLOW 1 -#define IRQ_FLOPPYINDEX 2 -#define IRQ_FLOPPYDISK 12 -#elif defined(CONFIG_ARCH_ARC) -#define IRQ_PRINTERBUSY 0 -#define IRQ_SERIALRING 1 -#define IRQ_PRINTERACK 2 -#define IRQ_FLOPPYCHANGED 12 -#endif - -#define IRQ_VSYNCPULSE 3 -#define IRQ_POWERON 4 -#define IRQ_TIMER0 5 -#define IRQ_TIMER1 6 -#define IRQ_IMMEDIATE 7 -#define IRQ_EXPCARDFIQ 8 -#define IRQ_SOUNDCHANGE 9 -#define IRQ_SERIALPORT 10 -#define IRQ_HARDDISK 11 -#define IRQ_EXPANSIONCARD 13 -#define IRQ_KEYBOARDTX 14 -#define IRQ_KEYBOARDRX 15 - -#if defined(CONFIG_ARCH_A5K) -#define FIQ_SERIALPORT 4 -#elif defined(CONFIG_ARCH_ARC) -#define FIQ_FLOPPYIRQ 1 -#define FIQ_FD1772 FIQ_FLOPPYIRQ -#endif - -#define FIQ_FLOPPYDATA 0 -#define FIQ_ECONET 2 -#define FIQ_EXPANSIONCARD 6 -#define FIQ_FORCE 7 - -#define IRQ_TIMER IRQ_TIMER0 - -/* - * This is the offset of the FIQ "IRQ" numbers - */ -#define FIQ_START 64 - -#define irq_cannonicalize(i) (i) - diff --git a/include/asm-arm26/system.h b/include/asm-arm26/system.h deleted file mode 100644 index 4703593b3bb5..000000000000 --- a/include/asm-arm26/system.h +++ /dev/null @@ -1,257 +0,0 @@ -#ifndef __ASM_ARM_SYSTEM_H -#define __ASM_ARM_SYSTEM_H - -#ifdef __KERNEL__ - - -/* - * This is used to ensure the compiler did actually allocate the register we - * asked it for some inline assembly sequences. Apparently we can't trust - * the compiler from one version to another so a bit of paranoia won't hurt. - * This string is meant to be concatenated with the inline asm string and - * will cause compilation to stop on mismatch. (From ARM32 - may come in handy) - */ -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" - -#ifndef __ASSEMBLY__ - -#include <linux/linkage.h> - -struct thread_info; -struct task_struct; - -#if 0 -/* information about the system we're running on */ -extern unsigned int system_rev; -extern unsigned int system_serial_low; -extern unsigned int system_serial_high; -extern unsigned int mem_fclk_21285; - -FIXME - sort this -/* - * We need to turn the caches off before calling the reset vector - RiscOS - * messes up if we don't - */ -#define proc_hard_reset() cpu_proc_fin() - -#endif - -struct pt_regs; - -void die(const char *msg, struct pt_regs *regs, int err) - __attribute__((noreturn)); - -void die_if_kernel(const char *str, struct pt_regs *regs, int err); - -void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, - struct pt_regs *), - int sig, const char *name); - -#include <asm/proc-fns.h> - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -extern asmlinkage void __backtrace(void); - -#define set_cr(x) \ - __asm__ __volatile__( \ - "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ - : : "r" (x) : "cc") - -#define get_cr() \ - ({ \ - unsigned int __val; \ - __asm__ __volatile__( \ - "mrc p15, 0, %0, c1, c0, 0 @ get CR" \ - : "=r" (__val) : : "cc"); \ - __val; \ - }) - -extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ -extern unsigned long cr_alignment; /* defined in entry-armv.S */ - -#define UDBG_UNDEFINED (1 << 0) -#define UDBG_SYSCALL (1 << 1) -#define UDBG_BADABORT (1 << 2) -#define UDBG_SEGV (1 << 3) -#define UDBG_BUS (1 << 4) - -extern unsigned int user_debug; - -#define vectors_base() (0) - -#define mb() __asm__ __volatile__ ("" : : : "memory") -#define rmb() mb() -#define wmb() mb() -#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); - -#define read_barrier_depends() do { } while(0) -#define set_mb(var, value) do { var = value; mb(); } while (0) - -/* - * We assume knowledge of how - * spin_unlock_irq() and friends are implemented. This avoids - * us needlessly decrementing and incrementing the preempt count. - */ -#define prepare_arch_switch(next) local_irq_enable() -#define finish_arch_switch(prev) spin_unlock(&(rq)->lock) - -/* - * switch_to(prev, next) should switch from task `prev' to `next' - * `prev' will never be the same as `next'. schedule() itself - * contains the memory barrier to tell GCC not to cache `current'. - */ -extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); - -#define switch_to(prev,next,last) \ -do { \ - last = __switch_to(prev,task_thread_info(prev),task_thread_info(next)); \ -} while (0) - -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - -/* - * Save the current interrupt enable state & disable IRQs - */ -#define local_irq_save(x) \ - do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ save_flags_cli\n" \ -" orr %1, %0, #0x08000000\n" \ -" and %0, %0, #0x0c000000\n" \ -" teqp %1, #0\n" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory"); \ - } while (0) - -/* - * Enable IRQs (sti) - */ -#define local_irq_enable() \ - do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ sti\n" \ -" bic %0, %0, #0x08000000\n" \ -" teqp %0, #0\n" \ - : "=r" (temp) \ - : \ - : "memory"); \ - } while(0) - -/* - * Disable IRQs (cli) - */ -#define local_irq_disable() \ - do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ cli\n" \ -" orr %0, %0, #0x08000000\n" \ -" teqp %0, #0\n" \ - : "=r" (temp) \ - : \ - : "memory"); \ - } while(0) - -/* Enable FIQs (stf) */ - -#define __stf() do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ stf\n" \ -" bic %0, %0, #0x04000000\n" \ -" teqp %0, #0\n" \ - : "=r" (temp)); \ - } while(0) - -/* Disable FIQs (clf) */ - -#define __clf() do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ clf\n" \ -" orr %0, %0, #0x04000000\n" \ -" teqp %0, #0\n" \ - : "=r" (temp)); \ - } while(0) - - -/* - * Save the current interrupt enable state. - */ -#define local_save_flags(x) \ - do { \ - __asm__ __volatile__( \ -" mov %0, pc @ save_flags\n" \ -" and %0, %0, #0x0c000000\n" \ - : "=r" (x)); \ - } while (0) - - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(x) \ - do { \ - unsigned long temp; \ - __asm__ __volatile__( \ -" mov %0, pc @ restore_flags\n" \ -" bic %0, %0, #0x0c000000\n" \ -" orr %0, %0, %1\n" \ -" teqp %0, #0\n" \ - : "=&r" (temp) \ - : "r" (x) \ - : "memory"); \ - } while (0) - - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) - -#define clf() __clf() -#define stf() __stf() - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - flags & PSR_I_BIT; \ -}) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) -{ - extern void __bad_xchg(volatile void *, int); - - switch (size) { - case 1: return cpu_xchg_1(x, ptr); - case 4: return cpu_xchg_4(x, ptr); - default: __bad_xchg(ptr, size); - } - return 0; -} - -#endif /* __ASSEMBLY__ */ - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm26/termbits.h b/include/asm-arm26/termbits.h deleted file mode 100644 index 48d2f5c7bcb8..000000000000 --- a/include/asm-arm26/termbits.h +++ /dev/null @@ -1,196 +0,0 @@ -#ifndef __ASM_ARM_TERMBITS_H -#define __ASM_ARM_TERMBITS_H - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif /* __ASM_ARM_TERMBITS_H */ diff --git a/include/asm-arm26/termios.h b/include/asm-arm26/termios.h deleted file mode 100644 index 293e3f1bc3f2..000000000000 --- a/include/asm-arm26/termios.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef __ASM_ARM_TERMIOS_H -#define __ASM_ARM_TERMIOS_H - -#include <asm/termbits.h> -#include <asm/ioctls.h> - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -#ifdef __KERNEL__ -/* intr=^C quit=^| erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" -#endif - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* __KERNEL__ */ - -#endif /* __ASM_ARM_TERMIOS_H */ diff --git a/include/asm-arm26/thread_info.h b/include/asm-arm26/thread_info.h deleted file mode 100644 index 9b367ebe515d..000000000000 --- a/include/asm-arm26/thread_info.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * linux/include/asm-arm26/thread_info.h - * - * Copyright (C) 2002 Russell King. - * Copyright (C) 2003 Ian Molton. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_THREAD_INFO_H -#define __ASM_ARM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -struct task_struct; -struct exec_domain; - -#include <linux/compiler.h> -#include <asm/fpstate.h> -#include <asm/ptrace.h> -#include <asm/types.h> - -typedef unsigned long mm_segment_t; - -struct cpu_context_save { - __u32 r4; - __u32 r5; - __u32 r6; - __u32 r7; - __u32 r8; - __u32 r9; - __u32 sl; - __u32 fp; - __u32 sp; - __u32 pc; -}; - -/* - * low level task data that entry.S needs immediate access to. - * We assume cpu_context follows immedately after cpu_domain. - */ -struct thread_info { - unsigned long flags; /* low level flags */ - int preempt_count; /* 0 => preemptable, <0 => bug */ - mm_segment_t addr_limit; /* address limit */ - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - __u32 cpu; /* cpu */ - struct cpu_context_save cpu_context; /* cpu context */ - struct restart_block restart_block; - union fp_state fpstate; -}; - -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task &tsk, \ - .exec_domain &default_exec_domain, \ - .flags 0, \ - .preempt_count 0, \ - .addr_limit KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - -/* - * how to get the thread information struct from C - */ -static inline struct thread_info *current_thread_info(void) __attribute_const__; - -static inline struct thread_info *current_thread_info(void) -{ - register unsigned long sp asm ("sp"); - return (struct thread_info *)(sp & ~0x1fff); -} - -#define THREAD_SIZE PAGE_SIZE -#define task_pt_regs(task) ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE - 8) - 1) - -extern struct thread_info *alloc_thread_info(struct task_struct *task); -extern void free_thread_info(struct thread_info *); - -#define thread_saved_pc(tsk) \ - ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) -#define thread_saved_fp(tsk) \ - ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) - -#else /* !__ASSEMBLY__ */ - -#define TI_FLAGS 0 -#define TI_PREEMPT 4 -#define TI_ADDR_LIMIT 8 -#define TI_TASK 12 -#define TI_EXEC_DOMAIN 16 -#define TI_CPU 20 -#define TI_CPU_SAVE 24 -#define TI_RESTART_BLOCK 28 -#define TI_FPSTATE 68 - -#endif - -#define PREEMPT_ACTIVE 0x04000000 - -/* - * thread information flags: - * TIF_SYSCALL_TRACE - syscall trace active - * TIF_NOTIFY_RESUME - resumption notification requested - * TIF_SIGPENDING - signal pending - * TIF_NEED_RESCHED - rescheduling necessary - * TIF_USEDFPU - FPU was used by this task this quantum (SMP) - * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED - */ -#define TIF_NOTIFY_RESUME 0 -#define TIF_SIGPENDING 1 -#define TIF_NEED_RESCHED 2 -#define TIF_SYSCALL_TRACE 8 -#define TIF_USED_FPU 16 -#define TIF_POLLING_NRFLAG 17 -#define TIF_MEMDIE 18 - -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_USED_FPU (1 << TIF_USED_FPU) -#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) - -/* - * Change these and you break ASM code in entry-common.S - */ -#define _TIF_WORK_MASK 0x000000ff - -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_THREAD_INFO_H */ diff --git a/include/asm-arm26/timex.h b/include/asm-arm26/timex.h deleted file mode 100644 index 68322fbc1aed..000000000000 --- a/include/asm-arm26/timex.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * linux/include/asm-arm/timex.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Architecture Specific TIME specifications - */ -#ifndef _ASMARM_TIMEX_H -#define _ASMARM_TIMEX_H - -/* - * On the RiscPC, the clock ticks at 2MHz. - */ -#define CLOCK_TICK_RATE 2000000 - -/* IS THAT RIGHT ON A5000? FIXME */ - -typedef unsigned long cycles_t; - -static inline cycles_t get_cycles (void) -{ - return 0; -} - -#endif diff --git a/include/asm-arm26/tlb.h b/include/asm-arm26/tlb.h deleted file mode 100644 index 08ddd85b8d35..000000000000 --- a/include/asm-arm26/tlb.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASMARM_TLB_H -#define __ASMARM_TLB_H - -#include <asm/pgalloc.h> -#include <asm/tlbflush.h> - -/* - * TLB handling. This allows us to remove pages from the page - * tables, and efficiently handle the TLB issues. - */ -struct mmu_gather { - struct mm_struct *mm; - unsigned int need_flush; - unsigned int fullmm; -}; - -DECLARE_PER_CPU(struct mmu_gather, mmu_gathers); - -static inline struct mmu_gather * -tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush) -{ - struct mmu_gather *tlb = &get_cpu_var(mmu_gathers); - - tlb->mm = mm; - tlb->need_flush = 0; - tlb->fullmm = full_mm_flush; - - return tlb; -} - -static inline void -tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) -{ - if (tlb->need_flush) - flush_tlb_mm(tlb->mm); - - /* keep the page table cache within bounds */ - check_pgt_cache(); - - put_cpu_var(mmu_gathers); -} - -#define tlb_remove_tlb_entry(tlb,ptep,address) do { } while (0) -//#define tlb_start_vma(tlb,vma) do { } while (0) -//FIXME - ARM32 uses this now that things changed in the kernel. seems like it may be pointless on arm26, however to get things compiling... -#define tlb_start_vma(tlb,vma) \ - do { \ - if (!tlb->fullmm) \ - flush_cache_range(vma, vma->vm_start, vma->vm_end); \ - } while (0) -#define tlb_end_vma(tlb,vma) do { } while (0) - -static inline void -tlb_remove_page(struct mmu_gather *tlb, struct page *page) -{ - tlb->need_flush = 1; - free_page_and_swap_cache(page); -} - -#define pte_free_tlb(tlb,ptep) pte_free(ptep) -#define pmd_free_tlb(tlb,pmdp) pmd_free(pmdp) - -#endif diff --git a/include/asm-arm26/tlbflush.h b/include/asm-arm26/tlbflush.h deleted file mode 100644 index f79c1cbf4f69..000000000000 --- a/include/asm-arm26/tlbflush.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef __ASMARM_TLBFLUSH_H -#define __ASMARM_TLBFLUSH_H - -/* - * TLB flushing: - * - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(vma, start, end) flushes a range of pages - */ - -#define flush_tlb_all() memc_update_all() -#define flush_tlb_mm(mm) memc_update_mm(mm) -#define flush_tlb_page(vma, vmaddr) do { printk("flush_tlb_page\n");} while (0) // IS THIS RIGHT? -#define flush_tlb_range(vma,start,end) \ - do { memc_update_mm(vma->vm_mm); (void)(start); (void)(end); } while (0) -#define flush_tlb_pgtables(mm,start,end) do { printk("flush_tlb_pgtables\n");} while (0) -#define flush_tlb_kernel_range(s,e) do { printk("flush_tlb_range\n");} while (0) - -/* - * The following handle the weird MEMC chip - */ -static inline void memc_update_all(void) -{ - struct task_struct *p; - cpu_memc_update_all(init_mm.pgd); - for_each_process(p) { - if (!p->mm) - continue; - cpu_memc_update_all(p->mm->pgd); - } - processor._set_pgd(current->active_mm->pgd); -} - -static inline void memc_update_mm(struct mm_struct *mm) -{ - cpu_memc_update_all(mm->pgd); - - if (mm == current->active_mm) - processor._set_pgd(mm->pgd); -} - -static inline void -memc_clear(struct mm_struct *mm, struct page *page) -{ - cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0); - - if (mm == current->active_mm) - processor._set_pgd(mm->pgd); -} - -static inline void -memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr) -{ - cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr); - - if (mm == current->active_mm) - processor._set_pgd(mm->pgd); -} - -static inline void -update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte) -{ - struct mm_struct *mm = vma->vm_mm; -printk("update_mmu_cache\n"); - memc_update_addr(mm, pte, addr); -} - -#endif diff --git a/include/asm-arm26/topology.h b/include/asm-arm26/topology.h deleted file mode 100644 index accbd7cad9b5..000000000000 --- a/include/asm-arm26/topology.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_ARM_TOPOLOGY_H -#define _ASM_ARM_TOPOLOGY_H - -#include <asm-generic/topology.h> - -#endif /* _ASM_ARM_TOPOLOGY_H */ diff --git a/include/asm-arm26/types.h b/include/asm-arm26/types.h deleted file mode 100644 index 81bd357ada02..000000000000 --- a/include/asm-arm26/types.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm26/uaccess-asm.h b/include/asm-arm26/uaccess-asm.h deleted file mode 100644 index ade76ec02995..000000000000 --- a/include/asm-arm26/uaccess-asm.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * linux/include/asm-arm/proc-armo/uaccess.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * The fs functions are implemented on the ARM2 and ARM3 architectures - * manually. - * Use *_user functions to access user memory with faulting behaving - * as though the user is accessing the memory. - * Use set_fs(get_ds()) and then the *_user functions to allow them to - * access kernel memory. - */ - -/* - * These are the values used to represent the user `fs' and the kernel `ds' - * FIXME - the KERNEL_DS should end at 0x03000000 but we want to access ROM at - * 0x03400000. ideally we want to forbid access to the IO space inbetween. - */ -#define KERNEL_DS 0x03FFFFFF -#define USER_DS 0x02000000 - -extern uaccess_t uaccess_user, uaccess_kernel; - -static inline void set_fs (mm_segment_t fs) -{ - current_thread_info()->addr_limit = fs; - current->thread.uaccess = (fs == USER_DS ? &uaccess_user : &uaccess_kernel); -} - -#define __range_ok(addr,size) ({ \ - unsigned long flag, roksum; \ - __asm__ __volatile__("subs %1, %0, %3; cmpcs %1, %2; movcs %0, #0" \ - : "=&r" (flag), "=&r" (roksum) \ - : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \ - : "cc"); \ - flag; }) - -#define __addr_ok(addr) ({ \ - unsigned long flag; \ - __asm__ __volatile__("cmp %2, %0; movlo %0, #0" \ - : "=&r" (flag) \ - : "0" (current_thread_info()->addr_limit), "r" (addr) \ - : "cc"); \ - (flag == 0); }) - -#define __put_user_asm_byte(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %1\n" \ - " mov r1, %2\n" \ - " mov r2, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r2\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "r" (current->thread.uaccess->put_byte), \ - "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __put_user_asm_half(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %1\n" \ - " mov r1, %2\n" \ - " mov r2, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r2\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "r" (current->thread.uaccess->put_half), \ - "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __put_user_asm_word(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %1\n" \ - " mov r1, %2\n" \ - " mov r2, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r2\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "r" (current->thread.uaccess->put_word), \ - "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __put_user_asm_dword(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %1\n" \ - " mov r1, %2\n" \ - " mov r2, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r2\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "r" (current->thread.uaccess->put_dword), \ - "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __get_user_asm_byte(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %2\n" \ - " mov r1, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r1\n" \ - " mov %1, r0\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "r" (current->thread.uaccess->get_byte), "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __get_user_asm_half(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %2\n" \ - " mov r1, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r1\n" \ - " mov %1, r0\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "r" (current->thread.uaccess->get_half), "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __get_user_asm_word(x,addr,err) \ - __asm__ __volatile__( \ - " mov r0, %2\n" \ - " mov r1, %0\n" \ - " mov lr, pc\n" \ - " mov pc, %3\n" \ - " mov %0, r1\n" \ - " mov %1, r0\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "r" (current->thread.uaccess->get_word), "0" (err) \ - : "r0", "r1", "r2", "lr") - -#define __do_copy_from_user(to,from,n) \ - (n) = current->thread.uaccess->copy_from_user((to),(from),(n)) - -#define __do_copy_to_user(to,from,n) \ - (n) = current->thread.uaccess->copy_to_user((to),(from),(n)) - -#define __do_clear_user(addr,sz) \ - (sz) = current->thread.uaccess->clear_user((addr),(sz)) - -#define __do_strncpy_from_user(dst,src,count,res) \ - (res) = current->thread.uaccess->strncpy_from_user(dst,src,count) - -#define __do_strnlen_user(s,n,res) \ - (res) = current->thread.uaccess->strnlen_user(s,n) diff --git a/include/asm-arm26/uaccess.h b/include/asm-arm26/uaccess.h deleted file mode 100644 index d64ed84cb2d3..000000000000 --- a/include/asm-arm26/uaccess.h +++ /dev/null @@ -1,293 +0,0 @@ -#ifndef _ASMARM_UACCESS_H -#define _ASMARM_UACCESS_H - -/* - * User space memory access functions - */ -#include <linux/sched.h> -#include <asm/errno.h> - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); -extern int fixup_exception(struct pt_regs *regs); - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define segment_eq(a,b) ((a) == (b)) - -#include <asm/uaccess-asm.h> - -#define access_ok(type,addr,size) (__range_ok(addr,size) == 0) - -/* - * Single-value transfer routines. They automatically use the right - * size if we just have the right pointer type. Note that the functions - * which read from user space (*get_*) need to take care not to leak - * kernel data even if the calling code is buggy and fails to check - * the return value. This means zeroing out the destination variable - * or buffer on error. Normally this is done out of line by the - * fixup code, but there are a few places where it intrudes on the - * main code path. When we only write to user space, there is no - * problem. - * - * The "__xxx" versions of the user access functions do not verify the - * address space - it must have been done previously with a separate - * "access_ok()" call. - * - * The "xxx_error" versions set the third argument to EFAULT if an - * error occurs, and leave it unchanged on success. Note that these - * versions are void (ie, don't return a value as such). - */ - -extern int __get_user_1(void *); -extern int __get_user_2(void *); -extern int __get_user_4(void *); -extern int __get_user_8(void *); -extern int __get_user_bad(void); - -#define __get_user_x(__r1,__p,__e,__s,__i...) \ - __asm__ __volatile__ ("bl __get_user_" #__s \ - : "=&r" (__e), "=r" (__r1) \ - : "0" (__p) \ - : __i) - -#define get_user(x,p) \ - ({ \ - register const typeof(*(p)) *__p asm("r0") = (p); \ - register typeof(*(p)) __r1 asm("r1"); \ - register int __e asm("r0"); \ - switch (sizeof(*(p))) { \ - case 1: \ - __get_user_x(__r1, __p, __e, 1, "lr"); \ - break; \ - case 2: \ - __get_user_x(__r1, __p, __e, 2, "r2", "lr"); \ - break; \ - case 4: \ - __get_user_x(__r1, __p, __e, 4, "lr"); \ - break; \ - case 8: \ - __get_user_x(__r1, __p, __e, 8, "lr"); \ - break; \ - default: __e = __get_user_bad(); break; \ - } \ - x = __r1; \ - __e; \ - }) - - -#define __get_user(x,ptr) \ -({ \ - long __gu_err = 0; \ - __get_user_err((x),(ptr),__gu_err); \ - __gu_err; \ -}) - -#define __get_user_error(x,ptr,err) \ -({ \ - __get_user_err((x),(ptr),err); \ - (void) 0; \ -}) - -#define __get_user_err(x,ptr,err) \ -do { \ - unsigned long __gu_addr = (unsigned long)(ptr); \ - unsigned long __gu_val; \ - switch (sizeof(*(ptr))) { \ - case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ - case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ - case 4: __get_user_asm_word(__gu_val,__gu_addr,err); break; \ - default: (__gu_val) = __get_user_bad(); \ - } \ - (x) = (__typeof__(*(ptr)))__gu_val; \ -} while (0) - -extern int __put_user_1(void *, unsigned int); -extern int __put_user_2(void *, unsigned int); -extern int __put_user_4(void *, unsigned int); -extern int __put_user_8(void *, unsigned long long); -extern int __put_user_bad(void); - -#define __put_user_x(__r1,__p,__e,__s) \ - __asm__ __volatile__ ( \ - __asmeq("%0", "r0") __asmeq("%2", "r1") \ - "bl __put_user_" #__s \ - : "=&r" (__e) \ - : "0" (__p), "r" (__r1) \ - : "ip", "lr", "cc") - -#define put_user(x,p) \ - ({ \ - register const typeof(*(p)) __r1 asm("r1") = (x); \ - register const typeof(*(p)) *__p asm("r0") = (p); \ - register int __e asm("r0"); \ - switch (sizeof(*(__p))) { \ - case 1: \ - __put_user_x(__r1, __p, __e, 1); \ - break; \ - case 2: \ - __put_user_x(__r1, __p, __e, 2); \ - break; \ - case 4: \ - __put_user_x(__r1, __p, __e, 4); \ - break; \ - case 8: \ - __put_user_x(__r1, __p, __e, 8); \ - break; \ - default: __e = __put_user_bad(); break; \ - } \ - __e; \ - }) - -#if 0 -/********************* OLD METHOD *******************/ -#define __put_user_x(__r1,__p,__e,__s,__i...) \ - __asm__ __volatile__ ("bl __put_user_" #__s \ - : "=&r" (__e) \ - : "0" (__p), "r" (__r1) \ - : __i) - -#define put_user(x,p) \ - ({ \ - register const typeof(*(p)) __r1 asm("r1") = (x); \ - register const typeof(*(p)) *__p asm("r0") = (p); \ - register int __e asm("r0"); \ - switch (sizeof(*(p))) { \ - case 1: \ - __put_user_x(__r1, __p, __e, 1, "r2", "lr"); \ - break; \ - case 2: \ - __put_user_x(__r1, __p, __e, 2, "r2", "lr"); \ - break; \ - case 4: \ - __put_user_x(__r1, __p, __e, 4, "r2", "lr"); \ - break; \ - case 8: \ - __put_user_x(__r1, __p, __e, 8, "r2", "ip", "lr"); \ - break; \ - default: __e = __put_user_bad(); break; \ - } \ - __e; \ - }) -/*************************************************/ -#endif - -#define __put_user(x,ptr) \ -({ \ - long __pu_err = 0; \ - __put_user_err((x),(ptr),__pu_err); \ - __pu_err; \ -}) - -#define __put_user_error(x,ptr,err) \ -({ \ - __put_user_err((x),(ptr),err); \ - (void) 0; \ -}) - -#define __put_user_err(x,ptr,err) \ -do { \ - unsigned long __pu_addr = (unsigned long)(ptr); \ - __typeof__(*(ptr)) __pu_val = (x); \ - switch (sizeof(*(ptr))) { \ - case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ - case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ - case 4: __put_user_asm_word(__pu_val,__pu_addr,err); break; \ - case 8: __put_user_asm_dword(__pu_val,__pu_addr,err); break; \ - default: __put_user_bad(); \ - } \ -} while (0) - -static __inline__ unsigned long copy_from_user(void *to, const void *from, unsigned long n) -{ - if (access_ok(VERIFY_READ, from, n)) - __do_copy_from_user(to, from, n); - else /* security hole - plug it */ - memzero(to, n); - return n; -} - -static __inline__ unsigned long __copy_from_user(void *to, const void *from, unsigned long n) -{ - __do_copy_from_user(to, from, n); - return n; -} - -static __inline__ unsigned long copy_to_user(void *to, const void *from, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - __do_copy_to_user(to, from, n); - return n; -} - -static __inline__ unsigned long __copy_to_user(void *to, const void *from, unsigned long n) -{ - __do_copy_to_user(to, from, n); - return n; -} - -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - -static __inline__ unsigned long clear_user (void *to, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - __do_clear_user(to, n); - return n; -} - -static __inline__ unsigned long __clear_user (void *to, unsigned long n) -{ - __do_clear_user(to, n); - return n; -} - -static __inline__ long strncpy_from_user (char *dst, const char *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - __do_strncpy_from_user(dst, src, count, res); - return res; -} - -static __inline__ long __strncpy_from_user (char *dst, const char *src, long count) -{ - long res; - __do_strncpy_from_user(dst, src, count, res); - return res; -} - -#define strlen_user(s) strnlen_user(s, ~0UL >> 1) - -static inline long strnlen_user(const char *s, long n) -{ - unsigned long res = 0; - - if (__addr_ok(s)) - __do_strnlen_user(s, n, res); - - return res; -} - -#endif /* _ASMARM_UACCESS_H */ diff --git a/include/asm-arm26/ucontext.h b/include/asm-arm26/ucontext.h deleted file mode 100644 index f853130137cc..000000000000 --- a/include/asm-arm26/ucontext.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASMARM_UCONTEXT_H -#define _ASMARM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* !_ASMARM_UCONTEXT_H */ diff --git a/include/asm-arm26/unaligned.h b/include/asm-arm26/unaligned.h deleted file mode 100644 index d992782089fd..000000000000 --- a/include/asm-arm26/unaligned.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifndef __ASM_ARM_UNALIGNED_H -#define __ASM_ARM_UNALIGNED_H - -#include <asm/types.h> - -extern int __bug_unaligned_x(void *ptr); - -/* - * What is the most efficient way of loading/storing an unaligned value? - * - * That is the subject of this file. Efficiency here is defined as - * minimum code size with minimum register usage for the common cases. - * It is currently not believed that long longs are common, so we - * trade efficiency for the chars, shorts and longs against the long - * longs. - * - * Current stats with gcc 2.7.2.2 for these functions: - * - * ptrsize get: code regs put: code regs - * 1 1 1 1 2 - * 2 3 2 3 2 - * 4 7 3 7 3 - * 8 20 6 16 6 - * - * gcc 2.95.1 seems to code differently: - * - * ptrsize get: code regs put: code regs - * 1 1 1 1 2 - * 2 3 2 3 2 - * 4 7 4 7 4 - * 8 19 8 15 6 - * - * which may or may not be more efficient (depending upon whether - * you can afford the extra registers). Hopefully the gcc 2.95 - * is inteligent enough to decide if it is better to use the - * extra register, but evidence so far seems to suggest otherwise. - * - * Unfortunately, gcc is not able to optimise the high word - * out of long long >> 32, or the low word from long long << 32 - */ - -#define __get_unaligned_2_le(__p) \ - (__p[0] | __p[1] << 8) - -#define __get_unaligned_4_le(__p) \ - (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24) - -#define __get_unaligned_le(ptr) \ - ({ \ - __typeof__(*(ptr)) __v; \ - __u8 *__p = (__u8 *)(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: __v = *(ptr); break; \ - case 2: __v = __get_unaligned_2_le(__p); break; \ - case 4: __v = __get_unaligned_4_le(__p); break; \ - case 8: { \ - unsigned int __v1, __v2; \ - __v2 = __get_unaligned_4_le((__p+4)); \ - __v1 = __get_unaligned_4_le(__p); \ - __v = ((unsigned long long)__v2 << 32 | __v1); \ - } \ - break; \ - default: __v = __bug_unaligned_x(__p); break; \ - } \ - __v; \ - }) - -static inline void __put_unaligned_2_le(__u32 __v, register __u8 *__p) -{ - *__p++ = __v; - *__p++ = __v >> 8; -} - -static inline void __put_unaligned_4_le(__u32 __v, register __u8 *__p) -{ - __put_unaligned_2_le(__v >> 16, __p + 2); - __put_unaligned_2_le(__v, __p); -} - -static inline void __put_unaligned_8_le(const unsigned long long __v, register __u8 *__p) -{ - /* - * tradeoff: 8 bytes of stack for all unaligned puts (2 - * instructions), or an extra register in the long long - * case - go for the extra register. - */ - __put_unaligned_4_le(__v >> 32, __p+4); - __put_unaligned_4_le(__v, __p); -} - -/* - * Try to store an unaligned value as efficiently as possible. - */ -#define __put_unaligned_le(val,ptr) \ - ({ \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(ptr) = (val); \ - break; \ - case 2: __put_unaligned_2_le((val),(__u8 *)(ptr)); \ - break; \ - case 4: __put_unaligned_4_le((val),(__u8 *)(ptr)); \ - break; \ - case 8: __put_unaligned_8_le((val),(__u8 *)(ptr)); \ - break; \ - default: __bug_unaligned_x(ptr); \ - break; \ - } \ - (void) 0; \ - }) - -/* - * Select endianness - */ -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif diff --git a/include/asm-arm26/uncompress.h b/include/asm-arm26/uncompress.h deleted file mode 100644 index df2cba816a4e..000000000000 --- a/include/asm-arm26/uncompress.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/include/asm-arm/arch-arc/uncompress.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#define VIDMEM ((char *)0x02000000) - -int video_num_columns, video_num_lines, video_size_row; -int white, bytes_per_char_h; -extern unsigned long con_charconvtable[256]; - -struct param_struct { - unsigned long page_size; - unsigned long nr_pages; - unsigned long ramdisk_size; - unsigned long mountrootrdonly; - unsigned long rootdev; - unsigned long video_num_cols; - unsigned long video_num_rows; - unsigned long video_x; - unsigned long video_y; - unsigned long memc_control_reg; - unsigned char sounddefault; - unsigned char adfsdrives; - unsigned char bytes_per_char_h; - unsigned char bytes_per_char_v; - unsigned long unused[256/4-11]; -}; - -static struct param_struct *params = (struct param_struct *)0x0207c000; - -/* - * This does not append a newline - */ -static void puts(const char *s) -{ - extern void ll_write_char(char *, unsigned long); - int x,y; - unsigned char c; - char *ptr; - - x = params->video_x; - y = params->video_y; - - while ( ( c = *(unsigned char *)s++ ) != '\0' ) { - if ( c == '\n' ) { - x = 0; - if ( ++y >= video_num_lines ) { - y--; - } - } else { - ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); - ll_write_char(ptr, c|(white<<16)); - if ( ++x >= video_num_columns ) { - x = 0; - if ( ++y >= video_num_lines ) { - y--; - } - } - } - } - - params->video_x = x; - params->video_y = y; -} - -static void error(char *x); - -/* - * Setup for decompression - */ -static void arch_decomp_setup(void) -{ - int i; - - video_num_lines = params->video_num_rows; - video_num_columns = params->video_num_cols; - bytes_per_char_h = params->bytes_per_char_h; - video_size_row = video_num_columns * bytes_per_char_h; - if (bytes_per_char_h == 4) - for (i = 0; i < 256; i++) - con_charconvtable[i] = - (i & 128 ? 1 << 0 : 0) | - (i & 64 ? 1 << 4 : 0) | - (i & 32 ? 1 << 8 : 0) | - (i & 16 ? 1 << 12 : 0) | - (i & 8 ? 1 << 16 : 0) | - (i & 4 ? 1 << 20 : 0) | - (i & 2 ? 1 << 24 : 0) | - (i & 1 ? 1 << 28 : 0); - else - for (i = 0; i < 16; i++) - con_charconvtable[i] = - (i & 8 ? 1 << 0 : 0) | - (i & 4 ? 1 << 8 : 0) | - (i & 2 ? 1 << 16 : 0) | - (i & 1 ? 1 << 24 : 0); - - white = bytes_per_char_h == 8 ? 0xfc : 7; - - if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n"); -} - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/include/asm-arm26/unistd.h b/include/asm-arm26/unistd.h deleted file mode 100644 index 4c3b919177e5..000000000000 --- a/include/asm-arm26/unistd.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * linux/include/asm-arm/unistd.h - * - * Copyright (C) 2001-2003 Russell King - * Modified 25/11/04 Ian Molton for arm26. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Please forward _all_ changes to this file to spyro@f2s.com - * no matter what the change is. Thanks! - */ -#ifndef __ASM_ARM_UNISTD_H -#define __ASM_ARM_UNISTD_H - -#define __NR_SYSCALL_BASE 0x900000 - -/* - * This file contains the system call numbers. - */ - -#define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) -#define __NR_exit (__NR_SYSCALL_BASE+ 1) -#define __NR_fork (__NR_SYSCALL_BASE+ 2) -#define __NR_read (__NR_SYSCALL_BASE+ 3) -#define __NR_write (__NR_SYSCALL_BASE+ 4) -#define __NR_open (__NR_SYSCALL_BASE+ 5) -#define __NR_close (__NR_SYSCALL_BASE+ 6) - /* 7 was sys_waitpid */ -#define __NR_creat (__NR_SYSCALL_BASE+ 8) -#define __NR_link (__NR_SYSCALL_BASE+ 9) -#define __NR_unlink (__NR_SYSCALL_BASE+ 10) -#define __NR_execve (__NR_SYSCALL_BASE+ 11) -#define __NR_chdir (__NR_SYSCALL_BASE+ 12) -#define __NR_time (__NR_SYSCALL_BASE+ 13) -#define __NR_mknod (__NR_SYSCALL_BASE+ 14) -#define __NR_chmod (__NR_SYSCALL_BASE+ 15) -#define __NR_lchown (__NR_SYSCALL_BASE+ 16) - /* 17 was sys_break */ - /* 18 was sys_stat */ -#define __NR_lseek (__NR_SYSCALL_BASE+ 19) -#define __NR_getpid (__NR_SYSCALL_BASE+ 20) -#define __NR_mount (__NR_SYSCALL_BASE+ 21) -#define __NR_umount (__NR_SYSCALL_BASE+ 22) -#define __NR_setuid (__NR_SYSCALL_BASE+ 23) -#define __NR_getuid (__NR_SYSCALL_BASE+ 24) -#define __NR_stime (__NR_SYSCALL_BASE+ 25) -#define __NR_ptrace (__NR_SYSCALL_BASE+ 26) -#define __NR_alarm (__NR_SYSCALL_BASE+ 27) - /* 28 was sys_fstat */ -#define __NR_pause (__NR_SYSCALL_BASE+ 29) -#define __NR_utime (__NR_SYSCALL_BASE+ 30) - /* 31 was sys_stty */ - /* 32 was sys_gtty */ -#define __NR_access (__NR_SYSCALL_BASE+ 33) -#define __NR_nice (__NR_SYSCALL_BASE+ 34) - /* 35 was sys_ftime */ -#define __NR_sync (__NR_SYSCALL_BASE+ 36) -#define __NR_kill (__NR_SYSCALL_BASE+ 37) -#define __NR_rename (__NR_SYSCALL_BASE+ 38) -#define __NR_mkdir (__NR_SYSCALL_BASE+ 39) -#define __NR_rmdir (__NR_SYSCALL_BASE+ 40) -#define __NR_dup (__NR_SYSCALL_BASE+ 41) -#define __NR_pipe (__NR_SYSCALL_BASE+ 42) -#define __NR_times (__NR_SYSCALL_BASE+ 43) - /* 44 was sys_prof */ -#define __NR_brk (__NR_SYSCALL_BASE+ 45) -#define __NR_setgid (__NR_SYSCALL_BASE+ 46) -#define __NR_getgid (__NR_SYSCALL_BASE+ 47) - /* 48 was sys_signal */ -#define __NR_geteuid (__NR_SYSCALL_BASE+ 49) -#define __NR_getegid (__NR_SYSCALL_BASE+ 50) -#define __NR_acct (__NR_SYSCALL_BASE+ 51) -#define __NR_umount2 (__NR_SYSCALL_BASE+ 52) - /* 53 was sys_lock */ -#define __NR_ioctl (__NR_SYSCALL_BASE+ 54) -#define __NR_fcntl (__NR_SYSCALL_BASE+ 55) - /* 56 was sys_mpx */ -#define __NR_setpgid (__NR_SYSCALL_BASE+ 57) - /* 58 was sys_ulimit */ - /* 59 was sys_olduname */ -#define __NR_umask (__NR_SYSCALL_BASE+ 60) -#define __NR_chroot (__NR_SYSCALL_BASE+ 61) -#define __NR_ustat (__NR_SYSCALL_BASE+ 62) -#define __NR_dup2 (__NR_SYSCALL_BASE+ 63) -#define __NR_getppid (__NR_SYSCALL_BASE+ 64) -#define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) -#define __NR_setsid (__NR_SYSCALL_BASE+ 66) -#define __NR_sigaction (__NR_SYSCALL_BASE+ 67) - /* 68 was sys_sgetmask */ - /* 69 was sys_ssetmask */ -#define __NR_setreuid (__NR_SYSCALL_BASE+ 70) -#define __NR_setregid (__NR_SYSCALL_BASE+ 71) -#define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) -#define __NR_sigpending (__NR_SYSCALL_BASE+ 73) -#define __NR_sethostname (__NR_SYSCALL_BASE+ 74) -#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) -#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ -#define __NR_getrusage (__NR_SYSCALL_BASE+ 77) -#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) -#define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) -#define __NR_getgroups (__NR_SYSCALL_BASE+ 80) -#define __NR_setgroups (__NR_SYSCALL_BASE+ 81) -#define __NR_select (__NR_SYSCALL_BASE+ 82) -#define __NR_symlink (__NR_SYSCALL_BASE+ 83) - /* 84 was sys_lstat */ -#define __NR_readlink (__NR_SYSCALL_BASE+ 85) -#define __NR_uselib (__NR_SYSCALL_BASE+ 86) -#define __NR_swapon (__NR_SYSCALL_BASE+ 87) -#define __NR_reboot (__NR_SYSCALL_BASE+ 88) -#define __NR_readdir (__NR_SYSCALL_BASE+ 89) -#define __NR_mmap (__NR_SYSCALL_BASE+ 90) -#define __NR_munmap (__NR_SYSCALL_BASE+ 91) -#define __NR_truncate (__NR_SYSCALL_BASE+ 92) -#define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) -#define __NR_fchmod (__NR_SYSCALL_BASE+ 94) -#define __NR_fchown (__NR_SYSCALL_BASE+ 95) -#define __NR_getpriority (__NR_SYSCALL_BASE+ 96) -#define __NR_setpriority (__NR_SYSCALL_BASE+ 97) - /* 98 was sys_profil */ -#define __NR_statfs (__NR_SYSCALL_BASE+ 99) -#define __NR_fstatfs (__NR_SYSCALL_BASE+100) - /* 101 was sys_ioperm */ -#define __NR_socketcall (__NR_SYSCALL_BASE+102) -#define __NR_syslog (__NR_SYSCALL_BASE+103) -#define __NR_setitimer (__NR_SYSCALL_BASE+104) -#define __NR_getitimer (__NR_SYSCALL_BASE+105) -#define __NR_stat (__NR_SYSCALL_BASE+106) -#define __NR_lstat (__NR_SYSCALL_BASE+107) -#define __NR_fstat (__NR_SYSCALL_BASE+108) - /* 109 was sys_uname */ - /* 110 was sys_iopl */ -#define __NR_vhangup (__NR_SYSCALL_BASE+111) - /* 112 was sys_idle */ -#define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ -#define __NR_wait4 (__NR_SYSCALL_BASE+114) -#define __NR_swapoff (__NR_SYSCALL_BASE+115) -#define __NR_sysinfo (__NR_SYSCALL_BASE+116) -#define __NR_ipc (__NR_SYSCALL_BASE+117) -#define __NR_fsync (__NR_SYSCALL_BASE+118) -#define __NR_sigreturn (__NR_SYSCALL_BASE+119) -#define __NR_clone (__NR_SYSCALL_BASE+120) -#define __NR_setdomainname (__NR_SYSCALL_BASE+121) -#define __NR_uname (__NR_SYSCALL_BASE+122) - /* 123 was sys_modify_ldt */ -#define __NR_adjtimex (__NR_SYSCALL_BASE+124) -#define __NR_mprotect (__NR_SYSCALL_BASE+125) -#define __NR_sigprocmask (__NR_SYSCALL_BASE+126) - /* 127 was sys_create_module */ -#define __NR_init_module (__NR_SYSCALL_BASE+128) -#define __NR_delete_module (__NR_SYSCALL_BASE+129) - /* 130 was sys_get_kernel_syms */ -#define __NR_quotactl (__NR_SYSCALL_BASE+131) -#define __NR_getpgid (__NR_SYSCALL_BASE+132) -#define __NR_fchdir (__NR_SYSCALL_BASE+133) -#define __NR_bdflush (__NR_SYSCALL_BASE+134) -#define __NR_sysfs (__NR_SYSCALL_BASE+135) -#define __NR_personality (__NR_SYSCALL_BASE+136) - /* 137 was sys_afs_syscall */ -#define __NR_setfsuid (__NR_SYSCALL_BASE+138) -#define __NR_setfsgid (__NR_SYSCALL_BASE+139) -#define __NR__llseek (__NR_SYSCALL_BASE+140) -#define __NR_getdents (__NR_SYSCALL_BASE+141) -#define __NR__newselect (__NR_SYSCALL_BASE+142) -#define __NR_flock (__NR_SYSCALL_BASE+143) -#define __NR_msync (__NR_SYSCALL_BASE+144) -#define __NR_readv (__NR_SYSCALL_BASE+145) -#define __NR_writev (__NR_SYSCALL_BASE+146) -#define __NR_getsid (__NR_SYSCALL_BASE+147) -#define __NR_fdatasync (__NR_SYSCALL_BASE+148) -#define __NR__sysctl (__NR_SYSCALL_BASE+149) -#define __NR_mlock (__NR_SYSCALL_BASE+150) -#define __NR_munlock (__NR_SYSCALL_BASE+151) -#define __NR_mlockall (__NR_SYSCALL_BASE+152) -#define __NR_munlockall (__NR_SYSCALL_BASE+153) -#define __NR_sched_setparam (__NR_SYSCALL_BASE+154) -#define __NR_sched_getparam (__NR_SYSCALL_BASE+155) -#define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) -#define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) -#define __NR_sched_yield (__NR_SYSCALL_BASE+158) -#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) -#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) -#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) -#define __NR_nanosleep (__NR_SYSCALL_BASE+162) -#define __NR_mremap (__NR_SYSCALL_BASE+163) -#define __NR_setresuid (__NR_SYSCALL_BASE+164) -#define __NR_getresuid (__NR_SYSCALL_BASE+165) - /* 166 was sys_vm86 */ - /* 167 was sys_query_module */ -#define __NR_poll (__NR_SYSCALL_BASE+168) -#define __NR_nfsservctl (__NR_SYSCALL_BASE+169) -#define __NR_setresgid (__NR_SYSCALL_BASE+170) -#define __NR_getresgid (__NR_SYSCALL_BASE+171) -#define __NR_prctl (__NR_SYSCALL_BASE+172) -#define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) -#define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) -#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) -#define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) -#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) -#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) -#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) -#define __NR_pread64 (__NR_SYSCALL_BASE+180) -#define __NR_pwrite64 (__NR_SYSCALL_BASE+181) -#define __NR_chown (__NR_SYSCALL_BASE+182) -#define __NR_getcwd (__NR_SYSCALL_BASE+183) -#define __NR_capget (__NR_SYSCALL_BASE+184) -#define __NR_capset (__NR_SYSCALL_BASE+185) -#define __NR_sigaltstack (__NR_SYSCALL_BASE+186) -#define __NR_sendfile (__NR_SYSCALL_BASE+187) - /* 188 reserved */ - /* 189 reserved */ -#define __NR_vfork (__NR_SYSCALL_BASE+190) -#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ -#define __NR_mmap2 (__NR_SYSCALL_BASE+192) -#define __NR_truncate64 (__NR_SYSCALL_BASE+193) -#define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) -#define __NR_stat64 (__NR_SYSCALL_BASE+195) -#define __NR_lstat64 (__NR_SYSCALL_BASE+196) -#define __NR_fstat64 (__NR_SYSCALL_BASE+197) -#define __NR_lchown32 (__NR_SYSCALL_BASE+198) -#define __NR_getuid32 (__NR_SYSCALL_BASE+199) -#define __NR_getgid32 (__NR_SYSCALL_BASE+200) -#define __NR_geteuid32 (__NR_SYSCALL_BASE+201) -#define __NR_getegid32 (__NR_SYSCALL_BASE+202) -#define __NR_setreuid32 (__NR_SYSCALL_BASE+203) -#define __NR_setregid32 (__NR_SYSCALL_BASE+204) -#define __NR_getgroups32 (__NR_SYSCALL_BASE+205) -#define __NR_setgroups32 (__NR_SYSCALL_BASE+206) -#define __NR_fchown32 (__NR_SYSCALL_BASE+207) -#define __NR_setresuid32 (__NR_SYSCALL_BASE+208) -#define __NR_getresuid32 (__NR_SYSCALL_BASE+209) -#define __NR_setresgid32 (__NR_SYSCALL_BASE+210) -#define __NR_getresgid32 (__NR_SYSCALL_BASE+211) -#define __NR_chown32 (__NR_SYSCALL_BASE+212) -#define __NR_setuid32 (__NR_SYSCALL_BASE+213) -#define __NR_setgid32 (__NR_SYSCALL_BASE+214) -#define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) -#define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) -#define __NR_getdents64 (__NR_SYSCALL_BASE+217) -#define __NR_pivot_root (__NR_SYSCALL_BASE+218) -#define __NR_mincore (__NR_SYSCALL_BASE+219) -#define __NR_madvise (__NR_SYSCALL_BASE+220) -#define __NR_fcntl64 (__NR_SYSCALL_BASE+221) - /* 222 for tux */ - /* 223 is unused */ -#define __NR_gettid (__NR_SYSCALL_BASE+224) -#define __NR_readahead (__NR_SYSCALL_BASE+225) -#define __NR_setxattr (__NR_SYSCALL_BASE+226) -#define __NR_lsetxattr (__NR_SYSCALL_BASE+227) -#define __NR_fsetxattr (__NR_SYSCALL_BASE+228) -#define __NR_getxattr (__NR_SYSCALL_BASE+229) -#define __NR_lgetxattr (__NR_SYSCALL_BASE+230) -#define __NR_fgetxattr (__NR_SYSCALL_BASE+231) -#define __NR_listxattr (__NR_SYSCALL_BASE+232) -#define __NR_llistxattr (__NR_SYSCALL_BASE+233) -#define __NR_flistxattr (__NR_SYSCALL_BASE+234) -#define __NR_removexattr (__NR_SYSCALL_BASE+235) -#define __NR_lremovexattr (__NR_SYSCALL_BASE+236) -#define __NR_fremovexattr (__NR_SYSCALL_BASE+237) -#define __NR_tkill (__NR_SYSCALL_BASE+238) -#define __NR_sendfile64 (__NR_SYSCALL_BASE+239) -#define __NR_futex (__NR_SYSCALL_BASE+240) -#define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) -#define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) -#define __NR_io_setup (__NR_SYSCALL_BASE+243) -#define __NR_io_destroy (__NR_SYSCALL_BASE+244) -#define __NR_io_getevents (__NR_SYSCALL_BASE+245) -#define __NR_io_submit (__NR_SYSCALL_BASE+246) -#define __NR_io_cancel (__NR_SYSCALL_BASE+247) -#define __NR_exit_group (__NR_SYSCALL_BASE+248) -#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) -#define __NR_epoll_create (__NR_SYSCALL_BASE+250) -#define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) -#define __NR_epoll_wait (__NR_SYSCALL_BASE+252) -#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) - /* 254 for set_thread_area */ - /* 255 for get_thread_area */ - /* 256 for set_tid_address */ -#define __NR_timer_create (__NR_SYSCALL_BASE+257) -#define __NR_timer_settime (__NR_SYSCALL_BASE+258) -#define __NR_timer_gettime (__NR_SYSCALL_BASE+259) -#define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) -#define __NR_timer_delete (__NR_SYSCALL_BASE+261) -#define __NR_clock_settime (__NR_SYSCALL_BASE+262) -#define __NR_clock_gettime (__NR_SYSCALL_BASE+263) -#define __NR_clock_getres (__NR_SYSCALL_BASE+264) -#define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) -#define __NR_statfs64 (__NR_SYSCALL_BASE+266) -#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) -#define __NR_tgkill (__NR_SYSCALL_BASE+268) -#define __NR_utimes (__NR_SYSCALL_BASE+269) -#define __NR_fadvise64_64 (__NR_SYSCALL_BASE+270) -#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) -#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) -#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) -#define __NR_mq_open (__NR_SYSCALL_BASE+274) -#define __NR_mq_unlink (__NR_SYSCALL_BASE+275) -#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) -#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) -#define __NR_mq_notify (__NR_SYSCALL_BASE+278) -#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) -#define __NR_waitid (__NR_SYSCALL_BASE+280) - -/* - * The following SWIs are ARM private. FIXME - make appropriate for arm26 - */ -#define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000) -#define __ARM_NR_breakpoint (__ARM_NR_BASE+1) -#define __ARM_NR_cacheflush (__ARM_NR_BASE+2) -#define __ARM_NR_usr26 (__ARM_NR_BASE+3) - -#ifdef __KERNEL__ - -#define __ARCH_WANT_IPC_PARSE_VERSION -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") - -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_UNISTD_H */ diff --git a/include/asm-arm26/user.h b/include/asm-arm26/user.h deleted file mode 100644 index 3e8b0f879159..000000000000 --- a/include/asm-arm26/user.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef _ARM_USER_H -#define _ARM_USER_H - -#include <asm/page.h> -#include <asm/ptrace.h> -/* Core file format: The core file is written in such a way that gdb - can understand it and provide useful information to the user (under - linux we use the 'trad-core' bfd). There are quite a number of - obstacles to being able to view the contents of the floating point - registers, and until these are solved you will not be able to view the - contents of them. Actually, you can read in the core file and look at - the contents of the user struct to find out what the floating point - registers contain. - The actual file contents are as follows: - UPAGE: 1 page consisting of a user struct that tells gdb what is present - in the file. Directly after this is a copy of the task_struct, which - is currently not used by gdb, but it may come in useful at some point. - All of the registers are stored as part of the upage. The upage should - always be only one page. - DATA: The data area is stored. We use current->end_text to - current->brk to pick up all of the user variables, plus any memory - that may have been malloced. No attempt is made to determine if a page - is demand-zero or if a page is totally unused, we just cover the entire - range. All of the addresses are rounded in such a way that an integral - number of pages is written. - STACK: We need the stack information in order to get a meaningful - backtrace. We need to write the data from (esp) to - current->start_stack, so we round each of these off in order to be able - to write an integer number of pages. - The minimum core file size is 3 pages, or 12288 bytes. -*/ - -struct user_fp { - struct fp_reg { - unsigned int sign1:1; - unsigned int unused:15; - unsigned int sign2:1; - unsigned int exponent:14; - unsigned int j:1; - unsigned int mantissa1:31; - unsigned int mantissa0:32; - } fpregs[8]; - unsigned int fpsr:32; - unsigned int fpcr:32; - unsigned char ftype[8]; - unsigned int init_flag; -}; - -/* When the kernel dumps core, it starts by dumping the user struct - - this will be used by gdb to figure out where the data and stack segments - are within the file, and what virtual addresses to use. */ -struct user{ -/* We start with the registers, to mimic the way that "memory" is returned - from the ptrace(3,...) function. */ - struct pt_regs regs; /* Where the registers are actually stored */ -/* ptrace does not yet supply these. Someday.... */ - int u_fpvalid; /* True if math co-processor being used. */ - /* for this mess. Not yet used. */ -/* The rest of this junk is to help gdb figure out what goes where */ - unsigned long int u_tsize; /* Text segment size (pages). */ - unsigned long int u_dsize; /* Data segment size (pages). */ - unsigned long int u_ssize; /* Stack segment size (pages). */ - unsigned long start_code; /* Starting virtual address of text. */ - unsigned long start_stack; /* Starting virtual address of stack area. - This is actually the bottom of the stack, - the top of the stack is always found in the - esp register. */ - long int signal; /* Signal that caused the core dump. */ - int reserved; /* No longer used */ - struct pt_regs * u_ar0; /* Used by gdb to help find the values for */ - /* the registers. */ - unsigned long magic; /* To uniquely identify a core file */ - char u_comm[32]; /* User command that was responsible */ - int u_debugreg[8]; - struct user_fp u_fp; /* FP state */ - struct user_fp_struct * u_fp0;/* Used by gdb to help find the values for */ - /* the FP registers. */ -}; -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* _ARM_USER_H */ diff --git a/include/asm-arm26/xor.h b/include/asm-arm26/xor.h deleted file mode 100644 index e7c4cf58bed1..000000000000 --- a/include/asm-arm26/xor.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * linux/include/asm-arm/xor.h - * - * Copyright (C) 2001 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <asm-generic/xor.h> - -#define __XOR(a1, a2) a1 ^= a2 - -#define GET_BLOCK_2(dst) \ - __asm__("ldmia %0, {%1, %2}" \ - : "=r" (dst), "=r" (a1), "=r" (a2) \ - : "0" (dst)) - -#define GET_BLOCK_4(dst) \ - __asm__("ldmia %0, {%1, %2, %3, %4}" \ - : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \ - : "0" (dst)) - -#define XOR_BLOCK_2(src) \ - __asm__("ldmia %0!, {%1, %2}" \ - : "=r" (src), "=r" (b1), "=r" (b2) \ - : "0" (src)); \ - __XOR(a1, b1); __XOR(a2, b2); - -#define XOR_BLOCK_4(src) \ - __asm__("ldmia %0!, {%1, %2, %3, %4}" \ - : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \ - : "0" (src)); \ - __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4) - -#define PUT_BLOCK_2(dst) \ - __asm__ __volatile__("stmia %0!, {%2, %3}" \ - : "=r" (dst) \ - : "0" (dst), "r" (a1), "r" (a2)) - -#define PUT_BLOCK_4(dst) \ - __asm__ __volatile__("stmia %0!, {%2, %3, %4, %5}" \ - : "=r" (dst) \ - : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4)) - -static void -xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) -{ - unsigned int lines = bytes / sizeof(unsigned long) / 4; - register unsigned int a1 __asm__("r4"); - register unsigned int a2 __asm__("r5"); - register unsigned int a3 __asm__("r6"); - register unsigned int a4 __asm__("r7"); - register unsigned int b1 __asm__("r8"); - register unsigned int b2 __asm__("r9"); - register unsigned int b3 __asm__("ip"); - register unsigned int b4 __asm__("lr"); - - do { - GET_BLOCK_4(p1); - XOR_BLOCK_4(p2); - PUT_BLOCK_4(p1); - } while (--lines); -} - -static void -xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, - unsigned long *p3) -{ - unsigned int lines = bytes / sizeof(unsigned long) / 4; - register unsigned int a1 __asm__("r4"); - register unsigned int a2 __asm__("r5"); - register unsigned int a3 __asm__("r6"); - register unsigned int a4 __asm__("r7"); - register unsigned int b1 __asm__("r8"); - register unsigned int b2 __asm__("r9"); - register unsigned int b3 __asm__("ip"); - register unsigned int b4 __asm__("lr"); - - do { - GET_BLOCK_4(p1); - XOR_BLOCK_4(p2); - XOR_BLOCK_4(p3); - PUT_BLOCK_4(p1); - } while (--lines); -} - -static void -xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, - unsigned long *p3, unsigned long *p4) -{ - unsigned int lines = bytes / sizeof(unsigned long) / 2; - register unsigned int a1 __asm__("r8"); - register unsigned int a2 __asm__("r9"); - register unsigned int b1 __asm__("ip"); - register unsigned int b2 __asm__("lr"); - - do { - GET_BLOCK_2(p1); - XOR_BLOCK_2(p2); - XOR_BLOCK_2(p3); - XOR_BLOCK_2(p4); - PUT_BLOCK_2(p1); - } while (--lines); -} - -static void -xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, - unsigned long *p3, unsigned long *p4, unsigned long *p5) -{ - unsigned int lines = bytes / sizeof(unsigned long) / 2; - register unsigned int a1 __asm__("r8"); - register unsigned int a2 __asm__("r9"); - register unsigned int b1 __asm__("ip"); - register unsigned int b2 __asm__("lr"); - - do { - GET_BLOCK_2(p1); - XOR_BLOCK_2(p2); - XOR_BLOCK_2(p3); - XOR_BLOCK_2(p4); - XOR_BLOCK_2(p5); - PUT_BLOCK_2(p1); - } while (--lines); -} - -static struct xor_block_template xor_block_arm4regs = { - .name = "arm4regs", - .do_2 = xor_arm4regs_2, - .do_3 = xor_arm4regs_3, - .do_4 = xor_arm4regs_4, - .do_5 = xor_arm4regs_5, -}; - -#undef XOR_TRY_TEMPLATES -#define XOR_TRY_TEMPLATES \ - do { \ - xor_speed(&xor_block_arm4regs); \ - xor_speed(&xor_block_8regs); \ - xor_speed(&xor_block_32regs); \ - } while (0) diff --git a/include/asm-avr32/a.out.h b/include/asm-avr32/a.out.h index 50bf6e31a143..9f398ab28ed0 100644 --- a/include/asm-avr32/a.out.h +++ b/include/asm-avr32/a.out.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h index 974480438849..7dbd603c38cc 100644 --- a/include/asm-avr32/arch-at32ap/board.h +++ b/include/asm-avr32/arch-at32ap/board.h @@ -6,6 +6,8 @@ #include <linux/types.h> +#define GPIO_PIN_NONE (-1) + /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */ void at32_add_system_devices(void); @@ -36,4 +38,24 @@ struct platform_device * at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, unsigned long fbmem_start, unsigned long fbmem_len); +struct usba_platform_data { + int vbus_pin; +}; +struct platform_device * +at32_add_device_usba(unsigned int id, struct usba_platform_data *data); + +/* depending on what's hooked up, not all SSC pins will be used */ +#define ATMEL_SSC_TK 0x01 +#define ATMEL_SSC_TF 0x02 +#define ATMEL_SSC_TD 0x04 +#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD) + +#define ATMEL_SSC_RK 0x10 +#define ATMEL_SSC_RF 0x20 +#define ATMEL_SSC_RD 0x40 +#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD) + +struct platform_device * +at32_add_device_ssc(unsigned int id, unsigned int flags); + #endif /* __ASM_ARCH_BOARD_H */ diff --git a/include/asm-avr32/arch-at32ap/portmux.h b/include/asm-avr32/arch-at32ap/portmux.h index 9930871decde..b1abe6b4e4ef 100644 --- a/include/asm-avr32/arch-at32ap/portmux.h +++ b/include/asm-avr32/arch-at32ap/portmux.h @@ -19,6 +19,7 @@ #define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */ #define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */ #define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */ +#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */ void at32_select_periph(unsigned int pin, unsigned int periph, unsigned long flags); diff --git a/include/asm-avr32/arch-at32ap/sm.h b/include/asm-avr32/arch-at32ap/sm.h deleted file mode 100644 index 265a9ead20bf..000000000000 --- a/include/asm-avr32/arch-at32ap/sm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * AT32 System Manager interface. - * - * Copyright (C) 2006 Atmel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_AVR32_AT32_SM_H__ -#define __ASM_AVR32_AT32_SM_H__ - -struct irq_chip; -struct platform_device; - -struct at32_sm { - spinlock_t lock; - void __iomem *regs; - struct irq_chip *eim_chip; - unsigned int eim_first_irq; - struct platform_device *pdev; -}; - -extern struct platform_device at32_sm_device; -extern struct at32_sm system_manager; - -#endif /* __ASM_AVR32_AT32_SM_H__ */ diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h index 07152b7fd9c9..c98eea44a70a 100644 --- a/include/asm-avr32/arch-at32ap/smc.h +++ b/include/asm-avr32/arch-at32ap/smc.h @@ -15,22 +15,50 @@ /* * All timing parameters are in nanoseconds. */ +struct smc_timing { + /* Delay from address valid to assertion of given strobe */ + int ncs_read_setup; + int nrd_setup; + int ncs_write_setup; + int nwe_setup; + + /* Pulse length of given strobe */ + int ncs_read_pulse; + int nrd_pulse; + int ncs_write_pulse; + int nwe_pulse; + + /* Total cycle length of given operation */ + int read_cycle; + int write_cycle; + + /* Minimal recovery times, will extend cycle if needed */ + int ncs_read_recover; + int nrd_recover; + int ncs_write_recover; + int nwe_recover; +}; + +/* + * All timing parameters are in clock cycles. + */ struct smc_config { + /* Delay from address valid to assertion of given strobe */ - u16 ncs_read_setup; - u16 nrd_setup; - u16 ncs_write_setup; - u16 nwe_setup; + u8 ncs_read_setup; + u8 nrd_setup; + u8 ncs_write_setup; + u8 nwe_setup; /* Pulse length of given strobe */ - u16 ncs_read_pulse; - u16 nrd_pulse; - u16 ncs_write_pulse; - u16 nwe_pulse; + u8 ncs_read_pulse; + u8 nrd_pulse; + u8 ncs_write_pulse; + u8 nwe_pulse; /* Total cycle length of given operation */ - u16 read_cycle; - u16 write_cycle; + u8 read_cycle; + u8 write_cycle; /* Bus width in bytes */ u8 bus_width; @@ -76,6 +104,9 @@ struct smc_config { unsigned int tdf_mode:1; }; +extern void smc_set_timing(struct smc_config *config, + const struct smc_timing *timing); + extern int smc_set_configuration(int cs, const struct smc_config *config); extern struct smc_config *smc_get_configuration(int cs); diff --git a/include/asm-avr32/atomic.h b/include/asm-avr32/atomic.h index b9c2548a52f3..7ef3862a73d0 100644 --- a/include/asm-avr32/atomic.h +++ b/include/asm-avr32/atomic.h @@ -101,7 +101,7 @@ static inline int atomic_sub_unless(atomic_t *v, int a, int u) " mov %1, 1\n" "1:" : "=&r"(tmp), "=&r"(result), "=o"(v->counter) - : "m"(v->counter), "rKs21"(a), "rKs21"(u) + : "m"(v->counter), "rKs21"(a), "rKs21"(u), "1"(result) : "cc", "memory"); return result; @@ -137,7 +137,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u) " mov %1, 1\n" "1:" : "=&r"(tmp), "=&r"(result), "=o"(v->counter) - : "m"(v->counter), "r"(a), "ir"(u) + : "m"(v->counter), "r"(a), "ir"(u), "1"(result) : "cc", "memory"); } diff --git a/include/asm-avr32/bug.h b/include/asm-avr32/bug.h index afdcd79a2966..331d45bab18f 100644 --- a/include/asm-avr32/bug.h +++ b/include/asm-avr32/bug.h @@ -57,7 +57,7 @@ #define WARN_ON(condition) \ ({ \ - typeof(condition) __ret_warn_on = (condition); \ + int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ _BUG_OR_WARN(BUGFLAG_WARNING); \ unlikely(__ret_warn_on); \ diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h index 21bb60bbb9a1..81e342636ac4 100644 --- a/include/asm-avr32/dma-mapping.h +++ b/include/asm-avr32/dma-mapping.h @@ -264,7 +264,11 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - dma_cache_sync(dev, bus_to_virt(dma_handle), size, direction); + /* + * No need to do anything since the CPU isn't supposed to + * touch this memory after we flushed it at mapping- or + * sync-for-device time. + */ } static inline void @@ -309,12 +313,11 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction) { - int i; - - for (i = 0; i < nents; i++) { - dma_cache_sync(dev, page_address(sg[i].page) + sg[i].offset, - sg[i].length, direction); - } + /* + * No need to do anything since the CPU isn't supposed to + * touch this memory after we flushed it at mapping- or + * sync-for-device time. + */ } static inline void diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index e30d4b3bd836..64bb92bb6773 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -255,6 +255,8 @@ static inline void memset_io(volatile void __iomem *addr, unsigned char val, memset((void __force *)addr, val, count); } +#define mmiowb() + #define IO_SPACE_LIMIT 0xffffffff extern void __iomem *__ioremap(unsigned long offset, size_t size, diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h index bb82e70cde8d..0e680f47209f 100644 --- a/include/asm-avr32/pgalloc.h +++ b/include/asm-avr32/pgalloc.h @@ -27,13 +27,7 @@ static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, */ static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm) { - unsigned int pgd_size = (USER_PTRS_PER_PGD * sizeof(pgd_t)); - pgd_t *pgd = kmalloc(pgd_size, GFP_KERNEL); - - if (pgd) - memset(pgd, 0, pgd_size); - - return pgd; + return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); } static inline void pgd_free(pgd_t *pgd) @@ -44,18 +38,9 @@ static inline void pgd_free(pgd_t *pgd) static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) { - int count = 0; pte_t *pte; - do { - pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_REPEAT); - if (pte) - clear_page(pte); - else { - current->state = TASK_UNINTERRUPTIBLE; - schedule_timeout(HZ); - } - } while (!pte && (count++ < 10)); + pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT); return pte; } @@ -63,18 +48,9 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) { - int count = 0; struct page *pte; - do { - pte = alloc_pages(GFP_KERNEL, 0); - if (pte) - clear_page(page_address(pte)); - else { - current->state = TASK_UNINTERRUPTIBLE; - schedule_timeout(HZ); - } - } while (!pte && (count++ < 10)); + pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); return pte; } diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h index c07bdd10b891..018f6e2a0242 100644 --- a/include/asm-avr32/pgtable.h +++ b/include/asm-avr32/pgtable.h @@ -32,8 +32,6 @@ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 -#define PTE_PHYS_MASK 0x1ffff000 - #ifndef __ASSEMBLY__ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); @@ -265,7 +263,7 @@ static inline pte_t pte_mkyoung(pte_t pte) * trivial. */ #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) -#define pte_page(x) phys_to_page(pte_val(x) & PTE_PHYS_MASK) +#define pte_page(x) (pfn_to_page(pte_pfn(x))) /* * Mark the prot value as uncacheable and unbufferable diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h index a8236bacc878..dc2d527cef41 100644 --- a/include/asm-avr32/system.h +++ b/include/asm-avr32/system.h @@ -73,11 +73,16 @@ extern struct task_struct *__switch_to(struct task_struct *, extern void __xchg_called_with_bad_pointer(void); -#ifdef __CHECKER__ -extern unsigned long __builtin_xchg(void *ptr, unsigned long x); -#endif +static inline unsigned long xchg_u32(u32 val, volatile u32 *m) +{ + u32 ret; -#define xchg_u32(val, m) __builtin_xchg((void *)m, val) + asm volatile("xchg %[ret], %[m], %[val]" + : [ret] "=&r"(ret), "=m"(*m) + : "m"(*m), [m] "r"(m), [val] "r"(val) + : "memory"); + return ret; +} static inline unsigned long __xchg(unsigned long x, volatile void *ptr, diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h index a2e606dd4f4a..17dacf3f36d3 100644 --- a/include/asm-avr32/thread_info.h +++ b/include/asm-avr32/thread_info.h @@ -74,20 +74,18 @@ static inline struct thread_info *current_thread_info(void) * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_BREAKPOINT 5 /* true if we should break after return */ -#define TIF_SINGLE_STEP 6 /* single step after next break */ -#define TIF_MEMDIE 7 -#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal */ -#define TIF_CPU_GOING_TO_SLEEP 9 /* CPU is entering sleep 0 mode */ +#define TIF_BREAKPOINT 4 /* true if we should break after return */ +#define TIF_SINGLE_STEP 5 /* single step after next break */ +#define TIF_MEMDIE 6 +#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */ +#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */ #define TIF_USERSPACE 31 /* true if FS sets userspace */ #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) diff --git a/include/asm-avr32/unaligned.h b/include/asm-avr32/unaligned.h index 3042723fcbfd..36f5fd430543 100644 --- a/include/asm-avr32/unaligned.h +++ b/include/asm-avr32/unaligned.h @@ -7,19 +7,10 @@ * words, but halfwords must be halfword-aligned, and doublewords must * be word-aligned. * - * TODO: Make all this CPU-specific and optimize. + * However, swapped word loads must be word-aligned so we can't + * optimize word loads in general. */ -#include <linux/string.h> - -/* Use memmove here, so gcc does not insert a __builtin_memcpy. */ - -#define get_unaligned(ptr) \ - ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; }) - -#define put_unaligned(val, ptr) \ - ({ __typeof__(*(ptr)) __tmp = (val); \ - memmove((ptr), &__tmp, sizeof(*(ptr))); \ - (void)0; }) +#include <asm-generic/unaligned.h> #endif /* __ASM_AVR32_UNALIGNED_H */ diff --git a/include/asm-avr32/unistd.h b/include/asm-avr32/unistd.h index 3b4e35b55c82..de09009593f8 100644 --- a/include/asm-avr32/unistd.h +++ b/include/asm-avr32/unistd.h @@ -303,6 +303,19 @@ #ifdef __KERNEL__ #define NR_syscalls 282 +/* Old stuff */ +#define __IGNORE_uselib +#define __IGNORE_mmap + +/* NUMA stuff */ +#define __IGNORE_mbind +#define __IGNORE_get_mempolicy +#define __IGNORE_set_mempolicy +#define __IGNORE_migrate_pages +#define __IGNORE_move_pages + +/* SMP stuff */ +#define __IGNORE_getcpu #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_STAT64 diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index c4d6cbbf96d4..a970781a0f98 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -61,6 +61,7 @@ extern void bfin_dcache_init(void); extern int read_iloc(void); extern int bfin_console_init(void); extern asmlinkage void lower_to_irq14(void); +extern void init_exception_vectors(void); extern void init_dma(void); extern void program_IAR(void); extern void evt14_softirq(void); diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h index 95c1c952e7c1..f617d8765451 100644 --- a/include/asm-blackfin/bfin5xx_spi.h +++ b/include/asm-blackfin/bfin5xx_spi.h @@ -21,8 +21,6 @@ #ifndef _SPI_CHANNEL_H_ #define _SPI_CHANNEL_H_ -#define SPI0_REGBASE 0xffc00500 - #define SPI_READ 0 #define SPI_WRITE 1 diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index 25b934b7f829..984b74f0a2ec 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -11,78 +11,57 @@ #define HI(con32) (((con32) >> 16) & 0xFFFF) #define hi(con32) (((con32) >> 16) & 0xFFFF) -#include <asm/mach/blackfin.h> -#include <asm/bfin-global.h> +#include <asm/mach/anomaly.h> #ifndef __ASSEMBLY__ /* SSYNC implementation for C file */ -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) -static inline void SSYNC (void) -{ - int _tmp; - __asm__ __volatile__ ("cli %0;\n\t" - "nop;nop;\n\t" - "ssync;\n\t" - "sti %0;\n\t" - :"=d"(_tmp):); -} -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) -static inline void SSYNC (void) +static inline void SSYNC(void) { int _tmp; - __asm__ __volatile__ ("cli %0;\n\t" - "ssync;\n\t" - "sti %0;\n\t" - :"=d"(_tmp):); + if (ANOMALY_05000312) + __asm__ __volatile__( + "cli %0;" + "nop;" + "nop;" + "ssync;" + "sti %0;" + : "=d" (_tmp) + ); + else if (ANOMALY_05000244) + __asm__ __volatile__( + "nop;" + "nop;" + "nop;" + "ssync;" + ); + else + __asm__ __volatile__("ssync;"); } -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) -static inline void SSYNC (void) -{ - __asm__ __volatile__ ("nop; nop; nop;\n\t" - "ssync;\n\t" - ::); -} -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) -static inline void SSYNC (void) -{ - __asm__ __volatile__ ("ssync;\n\t"); -} -#endif /* CSYNC implementation for C file */ -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) -static inline void CSYNC (void) -{ - int _tmp; - __asm__ __volatile__ ("cli %0;\n\t" - "nop;nop;\n\t" - "csync;\n\t" - "sti %0;\n\t" - :"=d"(_tmp):); -} -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) -static inline void CSYNC (void) +static inline void CSYNC(void) { int _tmp; - __asm__ __volatile__ ("cli %0;\n\t" - "csync;\n\t" - "sti %0;\n\t" - :"=d"(_tmp):); -} -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) -static inline void CSYNC (void) -{ - __asm__ __volatile__ ("nop; nop; nop;\n\t" - "ssync;\n\t" - ::); + if (ANOMALY_05000312) + __asm__ __volatile__( + "cli %0;" + "nop;" + "nop;" + "csync;" + "sti %0;" + : "=d" (_tmp) + ); + else if (ANOMALY_05000244) + __asm__ __volatile__( + "nop;" + "nop;" + "nop;" + "csync;" + ); + else + __asm__ __volatile__("csync;"); } -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) -static inline void CSYNC (void) -{ - __asm__ __volatile__ ("csync;\n\t"); -} -#endif #else /* __ASSEMBLY__ */ @@ -91,19 +70,15 @@ static inline void CSYNC (void) #define ssync(x) SSYNC(x) #define csync(x) CSYNC(x) -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) +#if ANOMALY_05000312 #define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; #define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) -#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; -#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; - -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) +#elif ANOMALY_05000244 #define SSYNC(scratch) nop; nop; nop; SSYNC; #define CSYNC(scratch) nop; nop; nop; CSYNC; -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) +#else #define SSYNC(scratch) SSYNC; #define CSYNC(scratch) CSYNC; @@ -111,4 +86,7 @@ static inline void CSYNC (void) #endif /* __ASSEMBLY__ */ +#include <asm/mach/blackfin.h> +#include <asm/bfin-global.h> + #endif /* _BLACKFIN_H_ */ diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h index e5e000de3c36..d81a77545a04 100644 --- a/include/asm-blackfin/cacheflush.h +++ b/include/asm-blackfin/cacheflush.h @@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *); static inline void flush_icache_range(unsigned start, unsigned end) { -#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE) +#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) -# if defined(CONFIG_BLKFIN_WT) +# if defined(CONFIG_BFIN_WT) blackfin_icache_flush_range((start), (end)); # else blackfin_icache_dcache_flush_range((start), (end)); @@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end) #else -# if defined(CONFIG_BLKFIN_CACHE) +# if defined(CONFIG_BFIN_ICACHE) blackfin_icache_flush_range((start), (end)); # endif -# if defined(CONFIG_BLKFIN_DCACHE) +# if defined(CONFIG_BFIN_DCACHE) blackfin_dcache_flush_range((start), (end)); # endif @@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \ } while (0) #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) -#if defined(CONFIG_BLKFIN_DCACHE) +#if defined(CONFIG_BFIN_DCACHE) # define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) #else # define invalidate_dcache_range(start,end) do { } while (0) #endif -#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB) +#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) #else @@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \ # define flush_dcache_page(page) do { } while (0) #endif -#endif /* _BLACKFIN_CACHEFLUSH_H */ +#endif /* _BLACKFIN_ICACHEFLUSH_H */ diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index e0dd56bfa4c7..06828d77a58f 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -1,17 +1,100 @@ -/************************************************************************ +/* + * File: include/asm-blackfin/cplb.h + * Based on: include/asm-blackfin/mach-bf537/bf537.h + * Author: Robin Getz <rgetz@blackfin.uclinux.org> * - * cplb.h + * Created: 2000 + * Description: Common CPLB definitions for CPLB init * - * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * Modified: + * Copyright 2004-2007 Analog Devices Inc. * - ************************************************************************/ - -/* Defines necessary for cplb initialisation routines. */ + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #ifndef _CPLB_H #define _CPLB_H -# include <asm/blackfin.h> +#include <asm/blackfin.h> +#include <asm/mach/anomaly.h> + +#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) +#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) +#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ + +#if ANOMALY_05000158 +#define ANOMALY_05000158_WORKAROUND 0x200 +#else +#define ANOMALY_05000158_WORKAROUND 0x0 +#endif + +#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) + +#ifdef CONFIG_BFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) +#else /*Write Through */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +#endif + +#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) +#define L2_MEMORY (CPLB_COMMON) +#define SDRAM_DNON_CHBL (CPLB_COMMON) +#define SDRAM_EBIU (CPLB_COMMON) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) + +#define SIZE_1K 0x00000400 /* 1K */ +#define SIZE_4K 0x00001000 /* 4K */ +#define SIZE_1M 0x00100000 /* 1M */ +#define SIZE_4M 0x00400000 /* 4M */ + +#define MAX_CPLBS (16 * 2) + +#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* possibly 1 for L2 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ + + +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ + +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) + #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 @@ -39,8 +122,6 @@ #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h index be0d913e5516..b42a531e7a1b 100644 --- a/include/asm-blackfin/dma.h +++ b/include/asm-blackfin/dma.h @@ -152,6 +152,7 @@ struct dma_channel { /* functions to set register mode */ void set_dma_start_addr(unsigned int channel, unsigned long addr); void set_dma_next_desc_addr(unsigned int channel, unsigned long addr); +void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr); void set_dma_x_count(unsigned int channel, unsigned short x_count); void set_dma_x_modify(unsigned int channel, short x_modify); void set_dma_y_count(unsigned int channel, unsigned short y_count); @@ -159,6 +160,7 @@ void set_dma_y_modify(unsigned int channel, short y_modify); void set_dma_config(unsigned int channel, unsigned short config); unsigned short set_bfin_dma_config(char direction, char flow_mode, char intr_mode, char dma_mode, char width); +void set_dma_curr_addr(unsigned int channel, unsigned long addr); /* get curr status for polling */ unsigned short get_dma_curr_irqstat(unsigned int channel); diff --git a/include/asm-blackfin/early_printk.h b/include/asm-blackfin/early_printk.h new file mode 100644 index 000000000000..110f1c1f845c --- /dev/null +++ b/include/asm-blackfin/early_printk.h @@ -0,0 +1,28 @@ +/* + * File: include/asm-blackfin/early_printk.h + * Author: Robin Getz <rgetz@blackfin.uclinux.org + * + * Created: 14Aug2007 + * Description: function prototpyes for early printk + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifdef CONFIG_EARLY_PRINTK +extern int setup_early_printk(char *); +#else +#define setup_early_printk(fmt) do { } while (0) +#endif /* CONFIG_EARLY_PRINTK */ diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index 7480cfa7e2d6..dd203cd93796 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -144,6 +144,24 @@ #ifdef BF533_FAMILY #define MAX_BLACKFIN_GPIOS 16 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 + #endif #ifdef BF537_FAMILY @@ -421,6 +439,19 @@ unsigned short gpio_get_value(unsigned short gpio); void gpio_direction_input(unsigned short gpio); void gpio_direction_output(unsigned short gpio); +#include <asm-generic/gpio.h> /* cansleep wrappers */ +#include <asm/irq.h> + +static inline int gpio_to_irq(unsigned gpio) +{ + return (gpio + GPIO_IRQ_BASE); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return (irq - GPIO_IRQ_BASE); +} + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 142cb333db29..525179bf43d7 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -115,21 +115,21 @@ static inline unsigned int readl(const volatile void __iomem *addr) #ifndef __ASSEMBLY__ -extern void outsb(void __iomem *port, const void *addr, unsigned short count); -extern void outsw(void __iomem *port, const void *addr, unsigned short count); -extern void outsl(void __iomem *port, const void *addr, unsigned short count); +extern void outsb(unsigned long port, const void *addr, unsigned long count); +extern void outsw(unsigned long port, const void *addr, unsigned long count); +extern void outsl(unsigned long port, const void *addr, unsigned long count); -extern void insb(const void __iomem *port, void *addr, unsigned short count); -extern void insw(const void __iomem *port, void *addr, unsigned short count); -extern void insl(const void __iomem *port, void *addr, unsigned short count); +extern void insb(unsigned long port, void *addr, unsigned long count); +extern void insw(unsigned long port, void *addr, unsigned long count); +extern void insl(unsigned long port, void *addr, unsigned long count); -extern void dma_outsb(void __iomem *port, const void *addr, unsigned short count); -extern void dma_outsw(void __iomem *port, const void *addr, unsigned short count); -extern void dma_outsl(void __iomem *port, const void *addr, unsigned short count); +extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); +extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); +extern void dma_outsl(unsigned long port, const void *addr, unsigned short count); -extern void dma_insb(const void __iomem *port, void *addr, unsigned short count); -extern void dma_insw(const void __iomem *port, void *addr, unsigned short count); -extern void dma_insl(const void __iomem *port, void *addr, unsigned short count); +extern void dma_insb(unsigned long port, void *addr, unsigned short count); +extern void dma_insw(unsigned long port, void *addr, unsigned short count); +extern void dma_insl(unsigned long port, void *addr, unsigned short count); /* * Map some physical address range into the kernel address space. diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h index 8356204151db..895e3173165d 100644 --- a/include/asm-blackfin/ioctls.h +++ b/include/asm-blackfin/ioctls.h @@ -47,8 +47,13 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TCGETS2 _IOR('T', 0x2A, struct termios2) +#define TCSETS2 _IOW('T', 0x2B, struct termios2) +#define TCSETSW2 _IOW('T', 0x2C, struct termios2) +#define TCSETSF2 _IOW('T', 0x2D, struct termios2) +/* Get Pty Number (of pty-mux device) */ +#define TIOCGPTN _IOR('T', 0x30, unsigned int) +#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ #define FIOCLEX 0x5451 diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h index d830f0a49a1c..139b5208f9d8 100644 --- a/include/asm-blackfin/irq_handler.h +++ b/include/asm-blackfin/irq_handler.h @@ -1,13 +1,15 @@ #ifndef _IRQ_HANDLER_H #define _IRQ_HANDLER_H +#include <linux/types.h> +#include <linux/linkage.h> + /* BASE LEVEL interrupt handler routines */ -asmlinkage void evt_emulation(void); asmlinkage void evt_exception(void); asmlinkage void trap(void); asmlinkage void evt_ivhw(void); asmlinkage void evt_timer(void); -asmlinkage void evt_evt2(void); +asmlinkage void evt_nmi(void); asmlinkage void evt_evt7(void); asmlinkage void evt_evt8(void); asmlinkage void evt_evt9(void); @@ -18,5 +20,14 @@ asmlinkage void evt_evt13(void); asmlinkage void evt_soft_int1(void); asmlinkage void evt_system_call(void); asmlinkage void init_exception_buff(void); +asmlinkage void trap_c(struct pt_regs *fp); +asmlinkage void ex_replaceable(void); +asmlinkage void early_trap(void); + +extern void *ex_table[]; +extern void return_from_exception(void); + +extern int bfin_request_exception(unsigned int exception, void (*handler)(void)); +extern int bfin_free_exception(unsigned int exception, void (*handler)(void)); #endif diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h index 532bd9052004..0f73847fd6bc 100644 --- a/include/asm-blackfin/kgdb.h +++ b/include/asm-blackfin/kgdb.h @@ -179,5 +179,6 @@ enum regnames { #define STATDA1 0x80 extern void kgdb_print(const char *fmt, ...); +extern void init_kgdb_uart(void); #endif diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h new file mode 100644 index 000000000000..991db986cd4b --- /dev/null +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -0,0 +1,41 @@ +/* + * File: include/asm-blackfin/mach-bf527/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* This file shoule be up to date with: + * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ +#define ANOMALY_05000301 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (1) +/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +#define ANOMALY_05000342 (1) +/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000323 (0) +#endif diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index 0b2fb5036ed0..b1ff67db01f8 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h @@ -102,6 +102,7 @@ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ @@ -480,6 +481,7 @@ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_REGBASE 0xFFC01400 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 7302f290b93d..f36ff5af1b91 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -1,247 +1,259 @@ /* - * File: include/asm-blackfin/mach-bf533/anomaly.h - * Based on: - * Author: + * File: include/asm-blackfin/mach-bf533/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List - * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List - * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List + * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List + * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List + * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ /* We do not support 0.1 or 0.2 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) -#error Kernel will not work on BF533 Version 0.1 or 0.2 +#if __SILICON_REVISION__ < 3 +# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 #endif -/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ - || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on - every corresponding match */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ -#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ -#define ANOMALY_05000311 /* Erroneous flag pin operations under specific - sequences */ -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC - registers are interrupted */ -#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */ -#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On - * Next System MMR Access */ -#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V - * and 1.15V Not Allowed for LQFP Packages */ -#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ +#if defined(__ADSPBF531__) +# define ANOMALY_BF531 1 +#else +# define ANOMALY_BF531 0 +#endif +#if defined(__ADSPBF532__) +# define ANOMALY_BF532 1 +#else +# define ANOMALY_BF532 0 +#endif +#if defined(__ADSPBF533__) +# define ANOMALY_BF533 1 +#else +# define ANOMALY_BF533 0 +#endif -/* These issues only occur on 0.3 or 0.4 BF533 */ -#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ -#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data - Cache Fill can be corrupted after or during - Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ -#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by - preceding memory read */ -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ -#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag - situation */ -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data*/ -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ -#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware - errors */ -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to increase. */ -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ -#endif /* issues only occur on 0.3 or 0.4 BF533 */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +#define ANOMALY_05000074 (1) +/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ +#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) +/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ +#define ANOMALY_05000105 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ +#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) +/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +#define ANOMALY_05000166 (1) +/* Turning Serial Ports on with External Frame Syncs */ +#define ANOMALY_05000167 (1) +/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ +#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ +#define ANOMALY_05000180 (1) +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ +#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) +/* False Protection Exceptions */ +#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) +/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ +#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) +/* Restarting SPORT in Specific Modes May Cause Data Corruption */ +#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) +/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) +/* Current DMA Address Shows Wrong Value During Carry Fix */ +#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) +/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ +#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) +/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ +#define ANOMALY_05000201 (__SILICON_REVISION__ < 4) +/* Possible Infinite Stall with Specific Dual-DAG Situation */ +#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) +/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ +#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) +/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) +/* Recovery from "Brown-Out" Condition */ +#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) +/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ +#define ANOMALY_05000208 (1) +/* Speed Path in Computational Unit Affects Certain Instructions */ +#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) +/* UART TX Interrupt Masked Erroneously */ +#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) +/* NMI Event at Boot Time Results in Unpredictable State */ +#define ANOMALY_05000219 (1) +/* Incorrect Pulse-Width of UART Start Bit */ +#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) +/* Scratchpad Memory Bank Reads May Return Incorrect Data */ +#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) +/* SPI Slave Boot Mode Modifies Registers from Reset Value */ +#define ANOMALY_05000229 (1) +/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ +#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) +/* UART STB Bit Incorrectly Affects Receiver Setting */ +#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) +/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ +#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) +/* Incorrect Revision Number in DSPID Register */ +#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) +/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ +#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Data CPLBs Should Prevent Spurious Hardware Errors */ +#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ +#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) +/* Maximum External Clock Speed for Timers */ +#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ +#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ +#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) +/* ICPLB_STATUS MMR Register May Be Corrupted */ +#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) +/* Stores To Data Cache May Be Lost */ +#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ +#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ +#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ +#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ +#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) +/* Spontaneous Reset of Internal Voltage Regulator */ +#define ANOMALY_05000271 (__SILICON_REVISION__ < 4) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* Writes to Synchronous SDRAM Memory May Be Lost */ +#define ANOMALY_05000273 (1) +/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ +#define ANOMALY_05000276 (1) +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ +#define ANOMALY_05000277 (1) +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ +#define ANOMALY_05000278 (1) +/* False Hardware Error Exception When ISR Context Is Not Restored */ +#define ANOMALY_05000281 (1) +/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ +#define ANOMALY_05000282 (1) +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +#define ANOMALY_05000283 (1) +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ +#define ANOMALY_05000288 (1) +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ +#define ANOMALY_05000301 (1) +/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ +#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) +/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ +#define ANOMALY_05000311 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* PPI Is Level-Sensitive on First Transfer */ +#define ANOMALY_05000313 (1) +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +#define ANOMALY_05000315 (1) +/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ +#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) -/* These issues are only on 0.4 silicon */ -#if (defined(CONFIG_BF_REV_0_4)) -#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ -#endif /* issues are only on 0.4 silicon */ +/* These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ -/* These issues are only on 0.3 silicon */ -#if defined(CONFIG_BF_REV_0_3) -#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ -#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative - Instruction or Data Fetches, or by Fetches at the - boundary of reserved memory space */ -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ -#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data - corruption */ -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ -#define ANOMALY_05000201 /* Receive frame sync not ignored during active - frames in sport MCM */ -#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA - stopping */ -#if defined(CONFIG_BF533) -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ -#endif /* CONFIG_BF533 */ -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ -#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame - Sync Transmit Mode */ -#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ -#endif /* only on 0.3 silicon */ +/* Watchpoints (Hardware Breakpoints) are not supported */ +#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) +/* Reserved bits in SYSCFG register not set at power on */ +#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) +/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) +/* Erroneous exception when enabling cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* SPI clock polarity and phase bits incorrect during booting */ +#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL is not set on Reset */ +#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) +/* SPI boot will not complete if there is a zero fill block in the loader file */ +#define ANOMALY_05000138 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* The source MDMA descriptor may stop with a DMA Error */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ +#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) +/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* SPORT transmit data is not gated by external frame sync in certain conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* SDRAM auto-refresh and subsequent Power Ups */ +#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) +/* DATA CPLB page miss can result in lost write-through cache data writes */ +#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* Cache Fill Buffer Data lost */ +#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) +/* Overlapping Sequencer and Memory Stalls */ +#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) +/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) +/* Disabling the PPI resets the PPI configuration registers */ +#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) +/* PPI TX Mode with 2 External Frame Syncs */ +#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* In PPI Transmit Modes with External Frame Syncs POLC */ +#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) +/* Internal Voltage Regulator may not start up */ +#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) -#if defined(CONFIG_BF_REV_0_2) -#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not - * supported */ -#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at - * power on */ -#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into - * emulation mode and/or exception, NMI, reset - * handlers */ -#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be - * incorrect if data cache or DMA is active */ -#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, - * or 1:1 */ -#define ANOMALY_05000125 /* Erroneous exception when enabling cache */ -#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect - * during booting */ -#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */ -#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill - * block in the loader file */ -#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an - * overflow */ -#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence - * of consecutive dual dag events */ -#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input - * flag is configured to be edge sensitive */ -#define ANOMALY_05000143 /* A read from external memory may return a wrong - * value with data cache enabled */ -#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing - * external memory */ -#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to - * generate a waveform from PPI_CLK */ -#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor - * chain */ -#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA - * Error */ -#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory - * device, the upper 8-bits of each word must be - * 0x00 */ -#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode - * outside of valid channels */ -#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a - * certain PPI mode is in use */ -#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to - * the next system MMR access thinking it should be - * 32-bit. */ -#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame - * sync in certain conditions */ -#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ -#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost - * write-through cache data writes */ -#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */ -#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ -#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an - * accumulator saturation */ -#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration - * registers */ -#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in - * Transmit Modes */ -#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs - * POLC */ -#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */ +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000266 (0) +#define ANOMALY_05000323 (0) #endif - -#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h index 185fc1284858..12a416931991 100644 --- a/include/asm-blackfin/mach-bf533/bf533.h +++ b/include/asm-blackfin/mach-bf533/bf533.h @@ -52,12 +52,12 @@ /***************************/ -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -141,97 +141,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) -#define MAX_VC 650000000 -#define MIN_VC 50000000 - -#ifdef CONFIG_BFIN_KERNEL_CLOCK -/********************************PLL Settings **************************************/ -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT > 64) -#error "VCO Multiplier is more than 64. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) -#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF533 #define CPU "BF533" #define CPUID 0x027a5000 @@ -249,58 +158,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM mem size must be multible of 4MB" -#endif - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#endif - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - #endif /* __MACH_BF533_H__ */ diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index e043cafa3c42..69b9f8e120e9 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -1,5 +1,6 @@ #include <linux/serial.h> #include <asm/dma.h> +#include <asm/portmux.h> #define NR_PORTS 1 @@ -92,18 +93,24 @@ struct bfin_serial_res bfin_serial_resource[] = { } }; +#define DRIVER_NAME "bfin-uart" int nr_ports = NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { +#ifdef CONFIG_SERIAL_BFIN_UART0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, NULL); + gpio_request(uart->cts_pin, DRIVER_NAME); gpio_direction_input(uart->cts_pin); } if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, NULL); + gpio_request(uart->rts_pin, DRIVER_NAME); gpio_direction_input(uart->rts_pin); } #endif diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h index e4384491e972..f3b240abf170 100644 --- a/include/asm-blackfin/mach-bf533/blackfin.h +++ b/include/asm-blackfin/mach-bf533/blackfin.h @@ -38,7 +38,7 @@ #include "defBF532.h" #include "anomaly.h" -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #include "cdefBF532.h" #endif diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h index 74f967b235e2..c803e14b529c 100644 --- a/include/asm-blackfin/mach-bf533/cdefBF532.h +++ b/include/asm-blackfin/mach-bf533/cdefBF532.h @@ -30,11 +30,9 @@ #ifndef _CDEF_BF532_H #define _CDEF_BF532_H -/* -#if !defined(__ADSPLPBLACKFIN__) -#warning cdefBF532.h should only be included for 532 compatible chips. -#endif -*/ + +#include <asm/blackfin.h> + /*include all Core registers and bit definitions*/ #include "defBF532.h" @@ -65,7 +63,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR, IWR_ENABLE(0)); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); @@ -132,10 +130,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val) #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) @@ -152,10 +146,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val) #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) @@ -165,6 +155,50 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) + +#if ANOMALY_05000311 +#define BFIN_WRITE_FIO_FLAG(name) \ +static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\ +{\ + unsigned long flags;\ + local_irq_save(flags);\ + bfin_write16(FIO_FLAG_ ## name,val);\ + bfin_read_CHIPID();\ + local_irq_restore(flags);\ +} +BFIN_WRITE_FIO_FLAG(D) +BFIN_WRITE_FIO_FLAG(C) +BFIN_WRITE_FIO_FLAG(S) +BFIN_WRITE_FIO_FLAG(T) + +#define BFIN_READ_FIO_FLAG(name) \ +static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\ +{\ + unsigned long flags;\ + unsigned short ret;\ + local_irq_save(flags);\ + ret = bfin_read16(FIO_FLAG_ ## name);\ + bfin_read_CHIPID();\ + local_irq_restore(flags);\ + return ret;\ +} +BFIN_READ_FIO_FLAG(D) +BFIN_READ_FIO_FLAG(C) +BFIN_READ_FIO_FLAG(S) +BFIN_READ_FIO_FLAG(T) + +#else +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#endif + + /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 6a3cf93f8b57..37134aaf9954 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h @@ -104,6 +104,7 @@ #define UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ @@ -928,7 +929,7 @@ #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 9879e68e315c..452fb825d891 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h @@ -128,6 +128,8 @@ Core Emulation ** #define IRQ_PF14 47 #define IRQ_PF15 48 +#define GPIO_IRQ_BASE IRQ_PF0 + #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PF15+1) #else diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h index e84baa3e939d..94d8c4062eb7 100644 --- a/include/asm-blackfin/mach-bf533/mem_map.h +++ b/include/asm-blackfin/mach-bf533/mem_map.h @@ -51,10 +51,10 @@ /* Level 1 Memory */ -#ifdef CONFIG_BLKFIN_CACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif /* Memory Map for ADSP-BF533 processors */ @@ -64,35 +64,35 @@ #define L1_DATA_A_START 0xFF800000 #define L1_DATA_B_START 0xFF900000 -#ifdef CONFIG_BLKFIN_CACHE +#ifdef CONFIG_BFIN_ICACHE #define L1_CODE_LENGTH (0x14000 - 0x4000) #else #define L1_CODE_LENGTH 0x14000 #endif -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /* Memory Map for ADSP-BF532 processors */ @@ -102,36 +102,36 @@ #define L1_DATA_A_START 0xFF804000 #define L1_DATA_B_START 0xFF904000 -#ifdef CONFIG_BLKFIN_CACHE +#ifdef CONFIG_BFIN_ICACHE #define L1_CODE_LENGTH (0xC000 - 0x4000) #else #define L1_CODE_LENGTH 0xC000 #endif -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /* Memory Map for ADSP-BF531 processors */ @@ -144,16 +144,16 @@ #define L1_DATA_B_LENGTH 0x0000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 #endif #endif diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 4453e614c3b1..2b66ecf489f7 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -1,139 +1,144 @@ - /* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. + * File: include/asm-blackfin/mach-bf537/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List - * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List - * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List + * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List + * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List + * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ /* We do not support 0.1 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1)) -#error Kernel will not work on BF537/6/4 Version 0.1 +#if __SILICON_REVISION__ < 2 +# error Kernel will not work on BF537 silicon version 0.0 or 0.1 #endif -#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits*/ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is - Changed */ -#endif -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - control */ -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when - killed in a particular stage*/ -#define ANOMALY_05000310 /* False hardware errors caused by fetches at the - * boundary of reserved memory */ -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC - registers are interrupted */ -#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */ -#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not - * received properly */ +#if defined(__ADSPBF534__) +# define ANOMALY_BF534 1 +#else +# define ANOMALY_BF534 0 #endif - -#if defined(CONFIG_BF_REV_0_2) -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or - IDLE around a Change of Control causes - unpredictable results */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */ +#if defined(__ADSPBF536__) +# define ANOMALY_BF536 1 +#else +# define ANOMALY_BF536 0 #endif -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) -#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */ +#if defined(__ADSPBF537__) +# define ANOMALY_BF537 1 +#else +# define ANOMALY_BF537 0 #endif -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware - loops may cause the instruction fetch unit to - malfunction */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of - the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE - instruction will cause an infinite stall in the - second to last instruction in a hardware loop */ -#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running - and non-zero DEB_TRAFFIC_PERIOD value */ -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the - internal voltage regulator (VDDint) to decrease */ -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after - an edge is detected may clear interrupt */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000280 /* SPI Master boot mode does not work well with - Atmel Dataflash devices */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context - * is not restored */ -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic - * control */ -#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When - * Killed in a Particular Stage */ -#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment - * (Not Available On Older Silicon) */ -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ -#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously - * On Next System MMR Access */ -#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex - * mode */ -#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with - * status No Carrier */ -#endif /* CONFIG_BF_REV_0_2 */ -#endif /* _MACH_ANOMALY_H_ */ +/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ +#define ANOMALY_05000119 (1) +/* Rx.H cannot be used to access 16-bit System MMR registers */ +#define ANOMALY_05000122 (1) +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ +#define ANOMALY_05000180 (1) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* Spurious Hardware Error from an access in the shadow of a conditional branch */ +#define ANOMALY_05000245 (1) +/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +#define ANOMALY_05000247 (1) +/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ +#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) +/* EMAC Tx DMA error after an early frame abort */ +#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) +/* Maximum external clock speed for Timers */ +#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ +#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) +/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ +#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) +/* EMAC MDIO input latched on wrong MDC edge */ +#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) +/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) +/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ +#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) +/* ICPLB_STATUS MMR register may be corrupted */ +#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) +/* DCPLB_FAULT_ADDR MMR register may be corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) +/* Stores to data cache may be lost */ +#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) +/* Hardware loop corrupted when taking an ICPLB exception */ +#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) +/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ +#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) +/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ +#define ANOMALY_05000265 (1) +/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) +/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ +#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) +/* Certain data cache write through modes fail for VDDint <=0.9V */ +#define ANOMALY_05000272 (1) +/* Writes to Synchronous SDRAM memory may be lost */ +#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) +/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +/* Disabling Peripherals with DMA running may cause DMA system instability */ +#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) +/* SPI Master boot mode does not work well with Atmel Data flash devices */ +#define ANOMALY_05000280 (1) +/* False Hardware Error Exception when ISR context is not restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) +/* Memory DMA corruption with 32-bit data and traffic control */ +#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) +/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) +/* SPORTs may receive bad data if FIFOs fill up */ +#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) +/* Memory to memory DMA source/destination descriptors must be in same memory space */ +#define ANOMALY_05000301 (1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ +#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) +/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) +/* False hardware errors caused by fetches at the boundary of reserved memory */ +#define ANOMALY_05000310 (1) +/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +#define ANOMALY_05000312 (1) +/* PPI is level sensitive on first transfer */ +#define ANOMALY_05000313 (1) +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode: collisions occur in Full Duplex mode */ +#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) +/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +#define ANOMALY_05000322 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000125 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) + +#endif diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h index b8924cd7730c..cfe2a221112e 100644 --- a/include/asm-blackfin/mach-bf537/bf537.h +++ b/include/asm-blackfin/mach-bf537/bf537.h @@ -62,12 +62,12 @@ /***************************/ -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -121,97 +121,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) -#define MAX_VC 650000000 -#define MIN_VC 50000000 - -/********************************PLL Settings **************************************/ -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT > 64) -#error "VCO Multiplier is more than 64. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) -#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF537 #define CPU "BF537" #define CPUID 0x027c8000 @@ -229,59 +138,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM mem size must be multible of 4MB" -#endif - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#endif - - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - #endif /* __MACH_BF537_H__ */ diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 8f5d9c4d8d5b..6fb328f5186a 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -1,5 +1,6 @@ #include <linux/serial.h> #include <asm/dma.h> +#include <asm/portmux.h> #define NR_PORTS 2 @@ -122,25 +123,29 @@ struct bfin_serial_res bfin_serial_resource[] = { int nr_ports = ARRAY_SIZE(bfin_serial_resource); +#define DRIVER_NAME "bfin-uart" + static void bfin_serial_hw_init(struct bfin_serial_port *uart) { - unsigned short val; - val = bfin_read16(BFIN_PORT_MUX); - val &= ~(PFDE | PFTE); - bfin_write16(BFIN_PORT_MUX, val); - val = bfin_read16(PORTF_FER); - val |= 0xF; - bfin_write16(PORTF_FER, val); +#ifdef CONFIG_SERIAL_BFIN_UART0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); +#endif #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, NULL); + gpio_request(uart->cts_pin, DRIVER_NAME); gpio_direction_input(uart->cts_pin); } if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, NULL); + gpio_request(uart->rts_pin, DRIVER_NAME); gpio_direction_output(uart->rts_pin); } #endif diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index bbd97051ec9c..53fcfa3408d0 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h @@ -43,7 +43,7 @@ #include "defBF537.h" #endif -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #include "cdefBF534.h" /* UART 0*/ @@ -143,284 +143,6 @@ #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) #define STOPCK_OFF STOPCK -/* FIO USE PORT F*/ -#ifdef CONFIG_BF537_PORT_F -#define bfin_read_PORT_FER() bfin_read_PORTF_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val) -#define FIO_FLAG_D PORTFIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val) -#define FIO_FLAG_C PORTFIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val) -#define FIO_FLAG_S PORTFIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val) -#define FIO_FLAG_T PORTFIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val) -#define FIO_MASKA_D PORTFIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTFIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val) -#define FIO_MASKA_S PORTFIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTFIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val) -#define FIO_MASKB_D PORTFIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTFIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val) -#define FIO_MASKB_S PORTFIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTFIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val) -#define FIO_DIR PORTFIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val) -#define FIO_POLAR PORTFIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val) -#define FIO_EDGE PORTFIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val) -#define FIO_BOTH PORTFIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val) -#define FIO_INEN PORTFIO_INEN -#endif - -/* FIO USE PORT G*/ -#ifdef CONFIG_BF537_PORT_G -#define bfin_read_PORT_FER() bfin_read_PORTG_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val) -#define FIO_FLAG_D PORTGIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val) -#define FIO_FLAG_C PORTGIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val) -#define FIO_FLAG_S PORTGIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val) -#define FIO_FLAG_T PORTGIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val) -#define FIO_MASKA_D PORTGIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTGIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val) -#define FIO_MASKA_S PORTGIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTGIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val) -#define FIO_MASKB_D PORTGIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTGIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val) -#define FIO_MASKB_S PORTGIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTGIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val) -#define FIO_DIR PORTGIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val) -#define FIO_POLAR PORTGIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val) -#define FIO_EDGE PORTGIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val) -#define FIO_BOTH PORTGIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val) -#define FIO_INEN PORTGIO_INEN - -#endif - -/* FIO USE PORT H*/ -#ifdef CONFIG_BF537_PORT_H -#define bfin_read_PORT_FER() bfin_read_PORTH_FER() -#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val) -#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val) -#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val) -#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val) -#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val) -#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val) -#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val) -#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val) -#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val) -#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val) -#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val) -#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val) -#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val) -#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val) -#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val) -#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val) -#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val) -#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val) - -#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO() -#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val) -#define FIO_FLAG_D PORTHIO -#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR() -#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val) -#define FIO_FLAG_C PORTHIO_CLEAR -#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET() -#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val) -#define FIO_FLAG_S PORTHIO_SET -#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE() -#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val) -#define FIO_FLAG_T PORTHIO_TOGGLE -#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA() -#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val) -#define FIO_MASKA_D PORTHIO_MASKA -#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR() -#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val) -#define FIO_MASKA_C PORTHIO_MASKA_CLEAR -#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET() -#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val) -#define FIO_MASKA_S PORTHIO_MASKA_SET -#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE() -#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val) -#define FIO_MASKA_T PORTHIO_MASKA_TOGGLE -#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB() -#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val) -#define FIO_MASKB_D PORTHIO_MASKB -#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR() -#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val) -#define FIO_MASKB_C PORTHIO_MASKB_CLEAR -#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET() -#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val) -#define FIO_MASKB_S PORTHIO_MASKB_SET -#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE() -#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val) -#define FIO_MASKB_T PORTHIO_MASKB_TOGGLE -#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val) -#define FIO_DIR PORTHIO_DIR -#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR() -#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val) -#define FIO_POLAR PORTHIO_POLAR -#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE() -#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val) -#define FIO_EDGE PORTHIO_EDGE -#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH() -#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val) -#define FIO_BOTH PORTHIO_BOTH -#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val) -#define FIO_INEN PORTHIO_INEN - -#endif - /* PLL_DIV Masks */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 84e58fa73dce..78227bc855df 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h @@ -32,6 +32,8 @@ #ifndef _CDEF_BF534_H #define _CDEF_BF534_H +#include <asm/blackfin.h> + /* Include all Core registers and bit definitions */ #include "defBF534.h" @@ -57,7 +59,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR, IWR_ENABLE(0)); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h index 1859f2fee5a7..d0d80d3152ba 100644 --- a/include/asm-blackfin/mach-bf537/defBF534.h +++ b/include/asm-blackfin/mach-bf537/defBF534.h @@ -86,6 +86,7 @@ #define UART0_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ @@ -456,6 +457,7 @@ #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#define TWI0_REGBASE 0xFFC01400 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ @@ -1165,7 +1167,7 @@ #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ #define PSSE 0x0010 /* Slave-Select Input Enable */ #define EMISO 0x0020 /* Enable MISO As Output */ -#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */ +#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ #define LSBF 0x0200 /* LSB First */ #define CPHA 0x0400 /* Clock Phase */ #define CPOL 0x0800 /* Clock Polarity */ diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index 8af2a832ef6b..36c44bc1a917 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h @@ -160,6 +160,8 @@ Core Emulation ** #define IRQ_PH14 96 #define IRQ_PH15 97 +#define GPIO_IRQ_BASE IRQ_PF0 + #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PH15+1) #else diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h index 2a808c1202bf..18759e38eaae 100644 --- a/include/asm-blackfin/mach-bf537/mem_map.h +++ b/include/asm-blackfin/mach-bf537/mem_map.h @@ -52,10 +52,10 @@ /* Memory Map for ADSP-BF537 processors */ -#ifdef CONFIG_BLKFIN_CACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif @@ -66,29 +66,29 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /*CONFIG_BF537*/ @@ -102,30 +102,30 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif @@ -138,30 +138,30 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h index 23e13c5abc4d..5a3f7d3bf73d 100644 --- a/include/asm-blackfin/mach-bf537/portmux.h +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -99,11 +99,44 @@ #define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) #define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0)) #define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) #define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) -#endif /* _MACH_PORTMUX_H_ */ +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MDC, \ + P_MDIO, 0} + + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_RMII0_REF_CLK, \ + P_RMII0_MDINT, \ + P_RMII0_CRS_DV, \ + P_MDC, \ + P_MDIO, 0} +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index aca1d4ba145c..c5b63759cdee 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -1,74 +1,85 @@ - /* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* This file shoule be up to date with: + * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the - Shadow of a Conditional Branch */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the - Boundary of Reserved Memory */ -#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and - LC Registers Are Interrupted */ -#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to - the USB FIFO Simultaneously */ -#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() - function */ -#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional - */ -#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ -#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM - Skew */ -#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration - of Host DMA Port */ -#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent - Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#endif /* _MACH_ANOMALY_H_ */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* False Hardware Error Exception when ISR context is not restored */ +#define ANOMALY_05000281 (1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (1) +/* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000325 (1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (1) +/* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000330 (1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (1) +/* USB Calibration Value Is Not Intialized */ +#define ANOMALY_05000346 (1) +/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000125 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) + +#endif diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 9498313a2cb7..7e6d349beb08 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -52,12 +52,12 @@ /***************************/ -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -106,93 +106,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) -#define MAX_VC 650000000 -#define MIN_VC 50000000 - -/********************************PLL Settings **************************************/ -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT > 64) -#error "VCO Multiplier is more than 64. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF542 #define CPU "BF542" #define CPUID 0x027c8000 @@ -213,59 +126,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM mem size must be multible of 4MB" -#endif - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#endif - - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - #endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 2f4afc90db11..f21a1620e6bd 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -1,5 +1,6 @@ #include <linux/serial.h> #include <asm/dma.h> +#include <asm/portmux.h> #define NR_PORTS 4 @@ -143,50 +144,48 @@ struct bfin_serial_res bfin_serial_resource[] = { int nr_ports = ARRAY_SIZE(bfin_serial_resource); +#define DRIVER_NAME "bfin-uart" + static void bfin_serial_hw_init(struct bfin_serial_port *uart) { #ifdef CONFIG_SERIAL_BFIN_UART0 - /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ - bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); - bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); #endif #ifdef CONFIG_SERIAL_BFIN_UART1 - /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ - bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); - bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); + #ifdef CONFIG_BFIN_UART1_CTSRTS - /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ - bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); - bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); + peripheral_request(P_UART1_RTS, DRIVER_NAME); + peripheral_request(P_UART1_CTS DRIVER_NAME); #endif #endif #ifdef CONFIG_SERIAL_BFIN_UART2 - /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ - bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); + peripheral_request(P_UART2_TX, DRIVER_NAME); + peripheral_request(P_UART2_RX, DRIVER_NAME); #endif #ifdef CONFIG_SERIAL_BFIN_UART3 - /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ - bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); + peripheral_request(P_UART3_TX, DRIVER_NAME); + peripheral_request(P_UART3_RX, DRIVER_NAME); + #ifdef CONFIG_BFIN_UART3_CTSRTS - /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ - bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); + peripheral_request(P_UART3_RTS, DRIVER_NAME); + peripheral_request(P_UART3_CTS DRIVER_NAME); #endif #endif SSYNC(); #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, NULL); + gpio_request(uart->cts_pin, DRIVER_NAME); gpio_direction_input(uart->cts_pin); } if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, NULL); + gpio_request(uart->rts_pin, DRIVER_NAME); gpio_direction_output(uart->rts_pin); } #endif diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 791218fe7d94..19e84dd4c99c 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -54,7 +54,7 @@ #include "defBF549.h" #endif -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #ifdef CONFIG_BF542 #include "cdefBF542.h" #endif diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 98d35a929116..aefab3f618c1 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -31,6 +31,8 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H +#include <asm/blackfin.h> + #include "defBF54x_base.h" #include <asm/system.h> @@ -60,7 +62,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR2, 0); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); @@ -242,6 +244,39 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) +#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) +#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) +#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) +#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) +#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) +#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) +#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) +#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) +#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) +#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) +#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) +#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) +#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) +#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) +#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) +#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) +#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) +#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) +#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) +#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) +#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) +#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) +#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) +#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) + /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index dd955dcd39b8..760307e34b9e 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -81,6 +81,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index 8d4214e0807c..70af33c963b0 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -120,6 +120,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ @@ -139,6 +140,7 @@ /* SPI2 Registers */ +#define SPI2_REGBASE 0xffc02400 #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index c2f4734da48d..50b3fe55ef0c 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -121,6 +121,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ @@ -140,6 +141,7 @@ /* SPI2 Registers */ +#define SPI2_REGBASE 0xffc02400 #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 895ddd40a838..e2632db74baa 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -109,6 +109,7 @@ /* SPI0 Registers */ +#define SPI0_REGBASE 0xffc00500 #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ @@ -121,6 +122,7 @@ /* Two Wire Interface Registers (TWI0) */ +#define TWI0_REGBASE 0xffc00700 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ @@ -978,6 +980,7 @@ /* SPI1 Registers */ +#define SPI1_REGBASE 0xffc02300 #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h index dbf66bcabe35..cb8b0f15c9a6 100644 --- a/include/asm-blackfin/mach-bf548/gpio.h +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -209,8 +209,3 @@ struct gpio_port_t { unsigned short dummy7; unsigned int port_mux; }; - -int gpio_request(unsigned short gpio, const char *label); -void peripheral_free(unsigned short per); -int peripheral_request_list(unsigned short per[], const char *label); -void peripheral_free_list(unsigned short per[]); diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 0b3325bb1fff..3b08cf9bd6f3 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -55,286 +55,288 @@ Events (highest priority) EMU 0 /* The ABSTRACT IRQ definitions */ /** the first seven of the following are fixed, the rest you change if you need to **/ -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt*/ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define BFIN_IRQ(x) ((x) + 7) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ -#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ -#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ -#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ -#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ -#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ -#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ -#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ -#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ -#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ -#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ -#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ -#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ -#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ -#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ -#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ -#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ -#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ -#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ -#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ -#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ -#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ -#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ -#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ -#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ -#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ -#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ -#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ -#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ -#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ -#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ -#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ -#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ -#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ -#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ -#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ -#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ -#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ -#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ -#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ -#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ -#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ -#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ -#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ -#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ -#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ -#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ -#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ -#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ -#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ -#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ -#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ -#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ -#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ -#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ -#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ -#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ -#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ -#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ -#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ -#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ -#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ -#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ -#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ -#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ -#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ -#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ -#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ -#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ -#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ -#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ -#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ -#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ -#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ -#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ -#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ -#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ -#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ - -#define SYS_IRQS IRQ_PINT3 - -#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) -#define IRQ_PA0 BFIN_PA_IRQ(0) -#define IRQ_PA1 BFIN_PA_IRQ(1) -#define IRQ_PA2 BFIN_PA_IRQ(2) -#define IRQ_PA3 BFIN_PA_IRQ(3) -#define IRQ_PA4 BFIN_PA_IRQ(4) -#define IRQ_PA5 BFIN_PA_IRQ(5) -#define IRQ_PA6 BFIN_PA_IRQ(6) -#define IRQ_PA7 BFIN_PA_IRQ(7) -#define IRQ_PA8 BFIN_PA_IRQ(8) -#define IRQ_PA9 BFIN_PA_IRQ(9) -#define IRQ_PA10 BFIN_PA_IRQ(10) -#define IRQ_PA11 BFIN_PA_IRQ(11) -#define IRQ_PA12 BFIN_PA_IRQ(12) -#define IRQ_PA13 BFIN_PA_IRQ(13) -#define IRQ_PA14 BFIN_PA_IRQ(14) -#define IRQ_PA15 BFIN_PA_IRQ(15) - -#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) -#define IRQ_PB0 BFIN_PB_IRQ(0) -#define IRQ_PB1 BFIN_PB_IRQ(1) -#define IRQ_PB2 BFIN_PB_IRQ(2) -#define IRQ_PB3 BFIN_PB_IRQ(3) -#define IRQ_PB4 BFIN_PB_IRQ(4) -#define IRQ_PB5 BFIN_PB_IRQ(5) -#define IRQ_PB6 BFIN_PB_IRQ(6) -#define IRQ_PB7 BFIN_PB_IRQ(7) -#define IRQ_PB8 BFIN_PB_IRQ(8) -#define IRQ_PB9 BFIN_PB_IRQ(9) -#define IRQ_PB10 BFIN_PB_IRQ(10) -#define IRQ_PB11 BFIN_PB_IRQ(11) -#define IRQ_PB12 BFIN_PB_IRQ(12) -#define IRQ_PB13 BFIN_PB_IRQ(13) -#define IRQ_PB14 BFIN_PB_IRQ(14) -#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ - -#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) -#define IRQ_PC0 BFIN_PC_IRQ(0) -#define IRQ_PC1 BFIN_PC_IRQ(1) -#define IRQ_PC2 BFIN_PC_IRQ(2) -#define IRQ_PC3 BFIN_PC_IRQ(3) -#define IRQ_PC4 BFIN_PC_IRQ(4) -#define IRQ_PC5 BFIN_PC_IRQ(5) -#define IRQ_PC6 BFIN_PC_IRQ(6) -#define IRQ_PC7 BFIN_PC_IRQ(7) -#define IRQ_PC8 BFIN_PC_IRQ(8) -#define IRQ_PC9 BFIN_PC_IRQ(9) -#define IRQ_PC10 BFIN_PC_IRQ(10) -#define IRQ_PC11 BFIN_PC_IRQ(11) -#define IRQ_PC12 BFIN_PC_IRQ(12) -#define IRQ_PC13 BFIN_PC_IRQ(13) -#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ -#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ - -#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) -#define IRQ_PD0 BFIN_PD_IRQ(0) -#define IRQ_PD1 BFIN_PD_IRQ(1) -#define IRQ_PD2 BFIN_PD_IRQ(2) -#define IRQ_PD3 BFIN_PD_IRQ(3) -#define IRQ_PD4 BFIN_PD_IRQ(4) -#define IRQ_PD5 BFIN_PD_IRQ(5) -#define IRQ_PD6 BFIN_PD_IRQ(6) -#define IRQ_PD7 BFIN_PD_IRQ(7) -#define IRQ_PD8 BFIN_PD_IRQ(8) -#define IRQ_PD9 BFIN_PD_IRQ(9) -#define IRQ_PD10 BFIN_PD_IRQ(10) -#define IRQ_PD11 BFIN_PD_IRQ(11) -#define IRQ_PD12 BFIN_PD_IRQ(12) -#define IRQ_PD13 BFIN_PD_IRQ(13) -#define IRQ_PD14 BFIN_PD_IRQ(14) -#define IRQ_PD15 BFIN_PD_IRQ(15) - -#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) -#define IRQ_PE0 BFIN_PE_IRQ(0) -#define IRQ_PE1 BFIN_PE_IRQ(1) -#define IRQ_PE2 BFIN_PE_IRQ(2) -#define IRQ_PE3 BFIN_PE_IRQ(3) -#define IRQ_PE4 BFIN_PE_IRQ(4) -#define IRQ_PE5 BFIN_PE_IRQ(5) -#define IRQ_PE6 BFIN_PE_IRQ(6) -#define IRQ_PE7 BFIN_PE_IRQ(7) -#define IRQ_PE8 BFIN_PE_IRQ(8) -#define IRQ_PE9 BFIN_PE_IRQ(9) -#define IRQ_PE10 BFIN_PE_IRQ(10) -#define IRQ_PE11 BFIN_PE_IRQ(11) -#define IRQ_PE12 BFIN_PE_IRQ(12) -#define IRQ_PE13 BFIN_PE_IRQ(13) -#define IRQ_PE14 BFIN_PE_IRQ(14) -#define IRQ_PE15 BFIN_PE_IRQ(15) - -#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) -#define IRQ_PF0 BFIN_PF_IRQ(0) -#define IRQ_PF1 BFIN_PF_IRQ(1) -#define IRQ_PF2 BFIN_PF_IRQ(2) -#define IRQ_PF3 BFIN_PF_IRQ(3) -#define IRQ_PF4 BFIN_PF_IRQ(4) -#define IRQ_PF5 BFIN_PF_IRQ(5) -#define IRQ_PF6 BFIN_PF_IRQ(6) -#define IRQ_PF7 BFIN_PF_IRQ(7) -#define IRQ_PF8 BFIN_PF_IRQ(8) -#define IRQ_PF9 BFIN_PF_IRQ(9) -#define IRQ_PF10 BFIN_PF_IRQ(10) -#define IRQ_PF11 BFIN_PF_IRQ(11) -#define IRQ_PF12 BFIN_PF_IRQ(12) -#define IRQ_PF13 BFIN_PF_IRQ(13) -#define IRQ_PF14 BFIN_PF_IRQ(14) -#define IRQ_PF15 BFIN_PF_IRQ(15) - -#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) -#define IRQ_PG0 BFIN_PG_IRQ(0) -#define IRQ_PG1 BFIN_PG_IRQ(1) -#define IRQ_PG2 BFIN_PG_IRQ(2) -#define IRQ_PG3 BFIN_PG_IRQ(3) -#define IRQ_PG4 BFIN_PG_IRQ(4) -#define IRQ_PG5 BFIN_PG_IRQ(5) -#define IRQ_PG6 BFIN_PG_IRQ(6) -#define IRQ_PG7 BFIN_PG_IRQ(7) -#define IRQ_PG8 BFIN_PG_IRQ(8) -#define IRQ_PG9 BFIN_PG_IRQ(9) -#define IRQ_PG10 BFIN_PG_IRQ(10) -#define IRQ_PG11 BFIN_PG_IRQ(11) -#define IRQ_PG12 BFIN_PG_IRQ(12) -#define IRQ_PG13 BFIN_PG_IRQ(13) -#define IRQ_PG14 BFIN_PG_IRQ(14) -#define IRQ_PG15 BFIN_PG_IRQ(15) - -#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) -#define IRQ_PH0 BFIN_PH_IRQ(0) -#define IRQ_PH1 BFIN_PH_IRQ(1) -#define IRQ_PH2 BFIN_PH_IRQ(2) -#define IRQ_PH3 BFIN_PH_IRQ(3) -#define IRQ_PH4 BFIN_PH_IRQ(4) -#define IRQ_PH5 BFIN_PH_IRQ(5) -#define IRQ_PH6 BFIN_PH_IRQ(6) -#define IRQ_PH7 BFIN_PH_IRQ(7) -#define IRQ_PH8 BFIN_PH_IRQ(8) -#define IRQ_PH9 BFIN_PH_IRQ(9) -#define IRQ_PH10 BFIN_PH_IRQ(10) -#define IRQ_PH11 BFIN_PH_IRQ(11) -#define IRQ_PH12 BFIN_PH_IRQ(12) -#define IRQ_PH13 BFIN_PH_IRQ(13) -#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ -#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ - -#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) -#define IRQ_PI0 BFIN_PI_IRQ(0) -#define IRQ_PI1 BFIN_PI_IRQ(1) -#define IRQ_PI2 BFIN_PI_IRQ(2) -#define IRQ_PI3 BFIN_PI_IRQ(3) -#define IRQ_PI4 BFIN_PI_IRQ(4) -#define IRQ_PI5 BFIN_PI_IRQ(5) -#define IRQ_PI6 BFIN_PI_IRQ(6) -#define IRQ_PI7 BFIN_PI_IRQ(7) -#define IRQ_PI8 BFIN_PI_IRQ(8) -#define IRQ_PI9 BFIN_PI_IRQ(9) -#define IRQ_PI10 BFIN_PI_IRQ(10) -#define IRQ_PI11 BFIN_PI_IRQ(11) -#define IRQ_PI12 BFIN_PI_IRQ(12) -#define IRQ_PI13 BFIN_PI_IRQ(13) -#define IRQ_PI14 BFIN_PI_IRQ(14) -#define IRQ_PI15 BFIN_PI_IRQ(15) - -#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) -#define IRQ_PJ0 BFIN_PJ_IRQ(0) -#define IRQ_PJ1 BFIN_PJ_IRQ(1) -#define IRQ_PJ2 BFIN_PJ_IRQ(2) -#define IRQ_PJ3 BFIN_PJ_IRQ(3) -#define IRQ_PJ4 BFIN_PJ_IRQ(4) -#define IRQ_PJ5 BFIN_PJ_IRQ(5) -#define IRQ_PJ6 BFIN_PJ_IRQ(6) -#define IRQ_PJ7 BFIN_PJ_IRQ(7) -#define IRQ_PJ8 BFIN_PJ_IRQ(8) -#define IRQ_PJ9 BFIN_PJ_IRQ(9) -#define IRQ_PJ10 BFIN_PJ_IRQ(10) -#define IRQ_PJ11 BFIN_PJ_IRQ(11) -#define IRQ_PJ12 BFIN_PJ_IRQ(12) -#define IRQ_PJ13 BFIN_PJ_IRQ(13) -#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ -#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ +#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ + +#define GPIO_IRQ_BASE IRQ_PA0 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PJ15+1) @@ -342,6 +344,34 @@ Events (highest priority) EMU 0 #define NR_IRQS (SYS_IRQS+1) #endif +/* For compatibility reasons with existing code */ + +#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR +#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR +#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR +#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR +#define IRQ_SPI0_ERR IRQ_SPI0_ERROR +#define IRQ_UART0_ERR IRQ_UART0_ERROR +#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR +#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR +#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR +#define IRQ_SPI1_ERR IRQ_SPI1_ERROR +#define IRQ_SPI2_ERR IRQ_SPI2_ERROR +#define IRQ_UART1_ERR IRQ_UART1_ERROR +#define IRQ_UART2_ERR IRQ_UART2_ERROR +#define IRQ_CAN0_ERR IRQ_CAN0_ERROR +#define IRQ_MXVR_ERR IRQ_MXVR_ERROR +#define IRQ_EPP1_ERR IRQ_EPP1_ERROR +#define IRQ_EPP2_ERR IRQ_EPP2_ERROR +#define IRQ_UART3_ERR IRQ_UART3_ERROR +#define IRQ_HOST_ERR IRQ_HOST_ERROR +#define IRQ_PIXC_ERR IRQ_PIXC_ERROR +#define IRQ_NFC_ERR IRQ_NFC_ERROR +#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR +#define IRQ_CAN1_ERR IRQ_CAN1_ERROR +#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR + + #define IVG7 7 #define IVG8 8 #define IVG9 9 diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index 72d80e8a6e81..ec1597e31831 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -51,10 +51,10 @@ /* Level 1 Memory */ /* Memory Map for ADSP-BF548 processors */ -#ifdef CONFIG_BLKFIN_ICACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif #define L1_CODE_START 0xFFA00000 @@ -63,29 +63,29 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ /* Scratch Pad Memory */ diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index f5b32d66517d..bed956456884 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -1,184 +1,256 @@ - /* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * File: include/asm-blackfin/mach-bf561/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List + * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* We do not support 0.1 or 0.4 silicon - sorry */ -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) -#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 +/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ +#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 +# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Issues that are common to 0.5 and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not - updated at the same time. */ -#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned - memory locations */ -#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR - registers */ -#define ANOMALY_05000127 /* Signbits instruction not functional under certain - conditions */ -#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out - upper bits */ -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame - syncs */ -#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz - and higher devices */ -#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ -#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not - functional */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the - shadow of a conditional branch */ -#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop - may cause bad instruction fetches */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - external SPORT TX and RX clocks */ -#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ -#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal - voltage regulator (VDDint) to increase */ -#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal - voltage regulator (VDDint) to decrease */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ -#define ANOMALY_05000274 /* Data cache write back to external synchronous memory - may be lost */ -#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC - registers are interrupted */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +#define ANOMALY_05000074 (1) +/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ +#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) +/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* Testset instructions restricted to 32-bit aligned memory locations */ +#define ANOMALY_05000120 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Erroneous exception when enabling cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* Signbits instruction not functional under certain conditions */ +#define ANOMALY_05000127 (1) +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) +/* Stall in multi-unit DMA operations */ +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* IMDMA S1/D1 channel may stall */ +#define ANOMALY_05000149 (1) +/* DMA engine may lose data due to incorrect handshaking */ +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) +/* DMA stalls when all three controllers read data from the same source */ +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) +/* Execution stall when executing in L2 and doing external accesses */ +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ +#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL<12> is not set on Reset */ +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) +/* SPORT transmit data is not gated by external frame sync in certain conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +#define ANOMALY_05000166 (1) +/* Turning Serial Ports on with External Frame Syncs */ +#define ANOMALY_05000167 (1) +/* SDRAM auto-refresh and subsequent Power Ups */ +#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) +/* DATA CPLB page miss can result in lost write-through cache data writes */ +#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) +/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) +/* DSPID register values incorrect */ +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* Cache Fill Buffer Data lost */ +#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) +/* Overlapping Sequencer and Memory Stalls */ +#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) +/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) +/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ +#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ +#define ANOMALY_05000180 (1) +/* Disabling the PPI resets the PPI configuration registers */ +#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) +/* IMDMA does not operate to full speed for 600MHz and higher devices */ +#define ANOMALY_05000182 (1) +/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) +/* PPI TX Mode with 2 External Frame Syncs */ +#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) +/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) +/* IMDMA Corrupted Data after a Halt */ +#define ANOMALY_05000187 (1) +/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ +#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) +/* False Protection Exceptions */ +#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) +/* PPI not functional at core voltage < 1Volt */ +#define ANOMALY_05000190 (1) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ +#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) +/* Restarting SPORT in Specific Modes May Cause Data Corruption */ +#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) +/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) +/* Current DMA Address Shows Wrong Value During Carry Fix */ +#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) +/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ +#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) +/* Possible Infinite Stall with Specific Dual-DAG Situation */ +#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) +/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) +/* Specific sequence that can cause DMA error or DMA stopping */ +#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) +/* Recovery from "Brown-Out" Condition */ +#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) +/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ +#define ANOMALY_05000208 (1) +/* Speed Path in Computational Unit Affects Certain Instructions */ +#define ANOMALY_05000209 (__SILICON_REVISION__ < 5) +/* UART TX Interrupt Masked Erroneously */ +#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) +/* NMI Event at Boot Time Results in Unpredictable State */ +#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) +/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ +#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) +/* Incorrect Pulse-Width of UART Start Bit */ +#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) +/* Scratchpad Memory Bank Reads May Return Incorrect Data */ +#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) +/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ +#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) +/* UART STB Bit Incorrectly Affects Receiver Setting */ +#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) +/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) +/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ +#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) +/* TESTSET operation forces stall on the other core */ +#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ +#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) +/* Exception Not Generated for MMR Accesses in Reserved Region */ +#define ANOMALY_05000251 (__SILICON_REVISION__ < 5) +/* Maximum External Clock Speed for Timers */ +#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ +#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) +/* ICPLB_STATUS MMR Register May Be Corrupted */ +#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) +/* Stores To Data Cache May Be Lost */ +#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ +#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ +#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) +/* IMDMA destination IRQ status must be read prior to using IMDMA */ +#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) +/* IMDMA may corrupt data under certain conditions */ +#define ANOMALY_05000267 (1) +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ +#define ANOMALY_05000269 (1) +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ +#define ANOMALY_05000270 (1) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* Data cache write back to external synchronous memory may be lost */ +#define ANOMALY_05000274 (1) +/* PPI Timing and Sampling Information Updates */ +#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) +/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ +#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ +#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) +/* False Hardware Error Exception When ISR Context Is Not Restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +#define ANOMALY_05000283 (1) +/* A read will receive incorrect data under certain conditions */ +#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ +#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ +#define ANOMALY_05000301 (1) +/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +#define ANOMALY_05000302 (1) +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ +#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* PPI Is Level-Sensitive on First Transfer */ +#define ANOMALY_05000313 (1) +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +#define ANOMALY_05000315 (1) +/* PF2 Output Remains Asserted After SPI Master Boot */ +#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) +/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +#define ANOMALY_05000323 (1) +/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) +/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) +/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) +/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000158 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000311 (0) -#if (defined(CONFIG_BF_REV_0_5)) -#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT - mode with external clock */ -#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to - using IMDMA */ #endif - -#if (defined(CONFIG_BF_REV_0_3)) -#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) - Mode with 0 Frame Syncs */ -#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ -#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through - cache data writes */ -#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ -#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ -#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an - accumulator saturation */ -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General - Purpose TX or RX modes */ -#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration - registers */ -#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with - External Frame Syncs */ -#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits - (not a meaningful mode) */ -#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer - Placement in Memory */ -#define ANOMALY_05000189 /* False Protection Exception */ -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs - when polarity setting is changed */ -#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data - corruption */ -#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding - memory read */ -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry - fix */ -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during - inactive channels in certain conditions */ -#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG - situation */ -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and - allocate cache lines on reads only mode */ -#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA - stopping */ -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain - instructions */ -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable - state */ -#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and - Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect - data */ -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate - Differences in certain Conditions */ -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ -#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in - multichannel mode */ -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to - hardware reset */ -#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of - Control causes failures */ -#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel - (TDM) mode in certain conditions */ -#define ANOMALY_05000251 /* Exception not generated for MMR accesses in - reserved region */ -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 - of the ICPLB Data registers differ */ -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ -#define ANOMALY_05000262 /* Stores to data cache may be lost */ -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB - exception */ -#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second - to last instruction in hardware loop */ -#define ANOMALY_05000276 /* Timing requirements change for External Frame - Sync PPI Modes with non-zero PPI_DELAY */ -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause - DMA system instability */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ -#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed - in a particular stage */ -#define ANOMALY_05000287 /* A read will receive incorrect data under certain - conditions */ -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ -#endif - -#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h index 96a5d3a47e45..17e1d5dcef02 100644 --- a/include/asm-blackfin/mach-bf561/bf561.h +++ b/include/asm-blackfin/mach-bf561/bf561.h @@ -73,13 +73,13 @@ */ -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -230,93 +230,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) -#define MAX_VC 600000000 -#define MIN_VC 50000000 - -/******************************* PLL Settings ********************************/ -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) -#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF561 #define CPU "BF561" #define CPUID 0x027bb000 @@ -326,83 +239,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM memory size must be a multiple of 4MB!" -#endif -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#endif - - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) - -#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for L2 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 64 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for L2 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) - -#if 0 /* comment by mhfan */ -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 -#endif /* comment by mhfan */ - #endif /* __MACH_BF561_H__ */ diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index e043cafa3c42..69b9f8e120e9 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -1,5 +1,6 @@ #include <linux/serial.h> #include <asm/dma.h> +#include <asm/portmux.h> #define NR_PORTS 1 @@ -92,18 +93,24 @@ struct bfin_serial_res bfin_serial_resource[] = { } }; +#define DRIVER_NAME "bfin-uart" int nr_ports = NR_PORTS; static void bfin_serial_hw_init(struct bfin_serial_port *uart) { +#ifdef CONFIG_SERIAL_BFIN_UART0 + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); +#endif + #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, NULL); + gpio_request(uart->cts_pin, DRIVER_NAME); gpio_direction_input(uart->cts_pin); } if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, NULL); + gpio_request(uart->rts_pin, DRIVER_NAME); gpio_direction_input(uart->rts_pin); } #endif diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h index 2537c845e8b0..562aee39895c 100644 --- a/include/asm-blackfin/mach-bf561/blackfin.h +++ b/include/asm-blackfin/mach-bf561/blackfin.h @@ -38,7 +38,7 @@ #include "defBF561.h" #include "anomaly.h" -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #include "cdefBF561.h" #endif diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 1a8ec9e46922..d667816486c0 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -31,11 +31,8 @@ #ifndef _CDEF_BF561_H #define _CDEF_BF561_H -/* -#if !defined(__ADSPBF561__) -#warning cdefBF561.h should only be included for BF561 chip. -#endif -*/ +#include <asm/blackfin.h> + /* include all Core registers and bit definitions */ #include "defBF561.h" @@ -67,7 +64,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); @@ -81,6 +78,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) #define bfin_read_CHIPID() bfin_read32(CHIPID) +/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ +#define bfin_read_SWRST() bfin_read_SICA_SWRST() +#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) +#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() +#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) + /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 89150ecb909d..bf7dc4e00065 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -52,6 +52,10 @@ #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ #define CHIPID 0xFFC00014 /* Chip ID Register */ +/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ +#define SWRST SICA_SWRST +#define SYSCR SICA_SYSCR + /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define SICA_SWRST 0xFFC00100 /* Software Reset register */ #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ @@ -116,6 +120,7 @@ #define UART_GCTL 0xFFC00424 /* Global Control Register */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI0_REGBASE 0xFFC00500 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */ diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h index a753ce720d74..12789927db3d 100644 --- a/include/asm-blackfin/mach-bf561/irq.h +++ b/include/asm-blackfin/mach-bf561/irq.h @@ -289,6 +289,8 @@ #define IRQ_PF46 119 #define IRQ_PF47 120 +#define GPIO_IRQ_BASE IRQ_PF0 + #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PF47 + 1) #else diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h index ebac9a8d838d..f7ac09cf2c3d 100644 --- a/include/asm-blackfin/mach-bf561/mem_map.h +++ b/include/asm-blackfin/mach-bf561/mem_map.h @@ -21,10 +21,10 @@ /* Level 1 Memory */ -#ifdef CONFIG_BLKFIN_CACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif /* Memory Map for ADSP-BF561 processors */ @@ -36,29 +36,29 @@ #define L1_CODE_LENGTH 0x4000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /* Level 2 Memory */ diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h index 10d11d5ffe23..132ad31665e3 100644 --- a/include/asm-blackfin/mach-bf561/portmux.h +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -81,7 +81,7 @@ #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) #define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) #define P_SPI0_SCK (P_DONTCARE) #endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index 94ed381e5606..ede210eca4ec 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h @@ -39,7 +39,7 @@ #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#ifdef ANOMALY_05000125 +#if ANOMALY_05000125 extern void bfin_write_DMEM_CONTROL(unsigned int val); #else #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) @@ -129,7 +129,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val); #define DTEST_DATA3 0xFFE0040C */ #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#ifdef ANOMALY_05000125 +#if ANOMALY_05000125 extern void bfin_write_IMEM_CONTROL(unsigned int val); #else #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h new file mode 100644 index 000000000000..033bba92d61c --- /dev/null +++ b/include/asm-blackfin/mach-common/clocks.h @@ -0,0 +1,70 @@ +/* + * File: include/asm-blackfin/mach-common/clocks.h + * Based on: include/asm-blackfin/mach-bf537/bf537.h + * Author: Robin Getz <rgetz@blackfin.uclinux.org> + * + * Created: 25Jul07 + * Description: Common Clock definitions for various kernel files + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BFIN_CLOCKS_H +#define _BFIN_CLOCKS_H + +#ifdef CONFIG_CCLK_DIV_1 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +# define CONFIG_CCLK_DIV 1 +#endif + +#ifdef CONFIG_CCLK_DIV_2 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +# define CONFIG_CCLK_DIV 2 +#endif + +#ifdef CONFIG_CCLK_DIV_4 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +# define CONFIG_CCLK_DIV 4 +#endif + +#ifdef CONFIG_CCLK_DIV_8 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +# define CONFIG_CCLK_DIV 8 +#endif + +#ifndef CONFIG_PLL_BYPASS +# ifndef CONFIG_CLKIN_HALF +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +# else +# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) +# endif + +# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) +# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) + +#else +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_VCO_MULT 0 +#endif + +#endif diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h index be1ece8c0c27..c1d8c4a78fcf 100644 --- a/include/asm-blackfin/mach-common/def_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h @@ -33,81 +33,77 @@ #include <asm/mach/anomaly.h> -/*#if !defined(__ADSPLPBLACKFIN__) -#warning def_LPBlackfin.h should only be included for 532 compatible chips. -#endif -*/ - #define MK_BMSK_(x) (1<<x) -#if defined(ANOMALY_05000198) - -#define bfin_read8(addr) ({ unsigned char __v; \ - __asm__ __volatile__ ("NOP;\n\t" \ - "%0 = b[%1] (z);\n\t" \ - : "=d"(__v) : "a"(addr)); \ - __v; }) - -#define bfin_read16(addr) ({ unsigned __v; \ - __asm__ __volatile__ ("NOP;\n\t"\ - "%0 = w[%1] (z);\n\t"\ - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) - -#define bfin_read32(addr) ({ unsigned __v; \ - __asm__ __volatile__ ("NOP;\n\t"\ - "%0 = [%1];\n\t"\ - : "=d"(__v) : "a"(addr)); __v; }) - -#define bfin_write8(addr, val) ({ \ - __asm__ __volatile__ ("NOP;\n\t" \ - "b[%0] = %1;\n\t" \ - : : "a"(addr), "d"(val) : "memory");}) +#ifndef __ASSEMBLY__ -#define bfin_write16(addr,val) ({\ - __asm__ __volatile__ ("NOP;\n\t"\ - "w[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - -#define bfin_write32(addr,val) ({\ - __asm__ __volatile__ ("NOP;\n\t"\ - "[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) +#include <linux/types.h> +#if ANOMALY_05000198 +# define NOP_PAD_ANOMALY_05000198 "nop;" #else - -#define bfin_read8(addr) ({ unsigned char __v; \ - __asm__ __volatile__ ( \ - "%0 = b[%1] (z);\n\t" \ - :"=d"(__v) : "a"(addr)); \ - __v; }) - -#define bfin_read16(addr) ({ unsigned __v; \ - __asm__ __volatile__ (\ - "%0 = w[%1] (z);\n\t"\ - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) - -#define bfin_read32(addr) ({ unsigned __v; \ - __asm__ __volatile__ (\ - "%0 = [%1];\n\t"\ - : "=d"(__v) : "a"(addr)); __v; }) - -#define bfin_write8(addr, val) ({ \ - __asm__ __volatile__ ( \ - "b[%0] = %1; \n\t" \ - ::"a"(addr), "d"(val) : "memory");}) - -#define bfin_write16(addr,val) ({\ - __asm__ __volatile__ (\ - "w[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - -#define bfin_write32(addr,val) ({\ - __asm__ __volatile__ (\ - "[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - +# define NOP_PAD_ANOMALY_05000198 #endif +#define bfin_read8(addr) ({ \ + uint8_t __v; \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "%0 = b[%1] (z);" \ + : "=d" (__v) \ + : "a" (addr) \ + ); \ + __v; }) + +#define bfin_read16(addr) ({ \ + uint16_t __v; \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "%0 = w[%1] (z);" \ + : "=d" (__v) \ + : "a" (addr) \ + ); \ + __v; }) + +#define bfin_read32(addr) ({ \ + uint32_t __v; \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "%0 = [%1];" \ + : "=d" (__v) \ + : "a" (addr) \ + ); \ + __v; }) + +#define bfin_write8(addr, val) \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "b[%0] = %1;" \ + : \ + : "a" (addr), "d" (val) \ + : "memory" \ + ) + +#define bfin_write16(addr, val) \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "w[%0] = %1;" \ + : \ + : "a" (addr), "d" (val) \ + : "memory" \ + ) + +#define bfin_write32(addr, val) \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "[%0] = %1;" \ + : \ + : "a" (addr), "d" (val) \ + : "memory" \ + ) + +#endif /* __ASSEMBLY__ */ + /************************************************** * System Register Bits **************************************************/ @@ -643,6 +639,7 @@ #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access * allowed (user mode) */ + #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ @@ -675,6 +672,8 @@ */ #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + /* TBUFCTL Masks */ #define TBUFPWR 0x0001 #define TBUFEN 0x0002 diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h index 5a8f9e431c40..b11b114689c0 100644 --- a/include/asm-blackfin/pgtable.h +++ b/include/asm-blackfin/pgtable.h @@ -4,7 +4,7 @@ #include <asm-generic/4level-fixup.h> #include <asm/page.h> -#include <asm/cplb.h> +#include <asm/mach-common/def_LPBlackfin.h> typedef pte_t *pte_addr_t; /* diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h index 9d3681e42111..0d3f650d2d99 100644 --- a/include/asm-blackfin/portmux.h +++ b/include/asm-blackfin/portmux.h @@ -14,6 +14,12 @@ #define P_MAYSHARE 0x2000 #define P_DONTCARE 0x1000 + +int peripheral_request(unsigned short per, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(unsigned short per[], const char *label); +void peripheral_free_list(unsigned short per[]); + #include <asm/gpio.h> #include <asm/mach/portmux.h> @@ -145,6 +151,22 @@ #define P_SPI2_SSEL3 P_UNDEF #endif +#ifndef P_SPI2_SSEL4 +#define P_SPI2_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL5 +#define P_SPI2_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL6 +#define P_SPI2_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL7 +#define P_SPI2_SSEL7 P_UNDEF +#endif + #ifndef P_SPI2_SCK #define P_SPI2_SCK P_UNDEF #endif @@ -513,6 +535,22 @@ #define P_SPI0_SSEL3 P_UNDEF #endif +#ifndef P_SPI0_SSEL4 +#define P_SPI0_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL5 +#define P_SPI0_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL6 +#define P_SPI0_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL7 +#define P_SPI0_SSEL7 P_UNDEF +#endif + #ifndef P_UART0_TX #define P_UART0_TX P_UNDEF #endif @@ -741,6 +779,23 @@ #define P_SPI1_SSEL3 P_UNDEF #endif + +#ifndef P_SPI1_SSEL4 +#define P_SPI1_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL5 +#define P_SPI1_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL6 +#define P_SPI1_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL7 +#define P_SPI1_SSEL7 P_UNDEF +#endif + #ifndef P_SPI1_SCK #define P_SPI1_SCK P_UNDEF #endif diff --git a/include/asm-blackfin/reboot.h b/include/asm-blackfin/reboot.h new file mode 100644 index 000000000000..6d448b5f5985 --- /dev/null +++ b/include/asm-blackfin/reboot.h @@ -0,0 +1,20 @@ +/* + * include/asm-blackfin/reboot.h - shutdown/reboot header + * + * Copyright 2004-2007 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_REBOOT_H__ +#define __ASM_REBOOT_H__ + +/* optional board specific hooks */ +extern void native_machine_restart(char *cmd); +extern void native_machine_halt(void); +extern void native_machine_power_off(void); + +/* common reboot workarounds */ +extern void bfin_gpio_reset_spi0_ssel1(void); + +#endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 6f1eb7d6d3cb..e8ada91ab002 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -9,13 +9,16 @@ extern inline char *strcpy(char *dest, const char *src) char *xdest = dest; char temp = 0; - __asm__ __volatile__ - ("1:\t%2 = B [%1++] (Z);\n\t" - "B [%0++] = %2;\n\t" - "CC = %2;\n\t" - "if cc jump 1b (bp);\n" - : "+&a" (dest), "+&a" (src), "=&d" (temp) - ::"memory", "CC"); + __asm__ __volatile__ ( + "1:" + "%2 = B [%1++] (Z);" + "B [%0++] = %2;" + "CC = %2;" + "if cc jump 1b (bp);" + : "+&a" (dest), "+&a" (src), "=&d" (temp) + : + : "memory", "CC"); + return xdest; } @@ -28,37 +31,56 @@ extern inline char *strncpy(char *dest, const char *src, size_t n) if (n == 0) return xdest; - __asm__ __volatile__ - ("1:\t%3 = B [%1++] (Z);\n\t" - "B [%0++] = %3;\n\t" - "CC = %3;\n\t" - "if ! cc jump 2f;\n\t" - "%2 += -1;\n\t" - "CC = %2 == 0;\n\t" - "if ! cc jump 1b (bp);\n" - "2:\n" - : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp) - ::"memory", "CC"); + __asm__ __volatile__ ( + "1:" + "%3 = B [%1++] (Z);" + "B [%0++] = %3;" + "CC = %3;" + "if ! cc jump 2f;" + "%2 += -1;" + "CC = %2 == 0;" + "if ! cc jump 1b (bp);" + "jump 4f;" + "2:" + /* if src is shorter than n, we need to null pad bytes now */ + "%3 = 0;" + "3:" + "%2 += -1;" + "CC = %2 == 0;" + "if cc jump 4f;" + "B [%0++] = %3;" + "jump 3b;" + "4:" + : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp) + : + : "memory", "CC"); + return xdest; } #define __HAVE_ARCH_STRCMP extern inline int strcmp(const char *cs, const char *ct) { - char __res1, __res2; - - __asm__ - ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */ - "%3 = B[%1++] (Z);\n\t" /* get *ct */ - "CC = %2 == %3;\n\t" /* compare a byte */ - "if ! cc jump 2f;\n\t" /* not equal, break out */ - "CC = %2;\n\t" /* at end of cs? */ - "if cc jump 1b (bp);\n\t" /* no, keep going */ - "jump.s 3f;\n" /* strings are equal */ - "2:\t%2 = %2 - %3;\n" /* *cs - *ct */ - "3:\n" - : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2) - : : "CC"); + /* need to use int's here so the char's in the assembly don't get + * sign extended incorrectly when we don't want them to be + */ + int __res1, __res2; + + __asm__ __volatile__ ( + "1:" + "%2 = B[%0++] (Z);" /* get *cs */ + "%3 = B[%1++] (Z);" /* get *ct */ + "CC = %2 == %3;" /* compare a byte */ + "if ! cc jump 2f;" /* not equal, break out */ + "CC = %2;" /* at end of cs? */ + "if cc jump 1b (bp);" /* no, keep going */ + "jump.s 3f;" /* strings are equal */ + "2:" + "%2 = %2 - %3;" /* *cs - *ct */ + "3:" + : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2) + : + : "memory", "CC"); return __res1; } @@ -66,26 +88,35 @@ extern inline int strcmp(const char *cs, const char *ct) #define __HAVE_ARCH_STRNCMP extern inline int strncmp(const char *cs, const char *ct, size_t count) { - char __res1, __res2; + /* need to use int's here so the char's in the assembly don't get + * sign extended incorrectly when we don't want them to be + */ + int __res1, __res2; if (!count) return 0; - __asm__ - ("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */ - "%4 = B[%1++] (Z);\n\t" /* get *ct */ - "CC = %3 == %4;\n\t" /* compare a byte */ - "if ! cc jump 3f;\n\t" /* not equal, break out */ - "CC = %3;\n\t" /* at end of cs? */ - "if ! cc jump 4f;\n\t" /* yes, all done */ - "%2 += -1;\n\t" /* no, adjust count */ - "CC = %2 == 0;\n\t" - "if ! cc jump 1b;\n" /* more to do, keep going */ - "2:\t%3 = 0;\n\t" /* strings are equal */ - "jump.s 4f;\n" - "3:\t%3 = %3 - %4;\n" /* *cs - *ct */ - "4:" - : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2) - : : "CC"); + + __asm__ __volatile__ ( + "1:" + "%3 = B[%0++] (Z);" /* get *cs */ + "%4 = B[%1++] (Z);" /* get *ct */ + "CC = %3 == %4;" /* compare a byte */ + "if ! cc jump 3f;" /* not equal, break out */ + "CC = %3;" /* at end of cs? */ + "if ! cc jump 4f;" /* yes, all done */ + "%2 += -1;" /* no, adjust count */ + "CC = %2 == 0;" + "if ! cc jump 1b;" /* more to do, keep going */ + "2:" + "%3 = 0;" /* strings are equal */ + "jump.s 4f;" + "3:" + "%3 = %3 - %4;" /* *cs - *ct */ + "4:" + : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2) + : + : "memory", "CC"); + return __res1; } diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h index 5e5f1a0566c0..2b3d47d0bbb6 100644 --- a/include/asm-blackfin/system.h +++ b/include/asm-blackfin/system.h @@ -36,6 +36,7 @@ #include <linux/linkage.h> #include <linux/compiler.h> +#include <asm/mach/anomaly.h> /* * Interrupt configuring macros. @@ -43,53 +44,60 @@ extern unsigned long irq_flags; -#define local_irq_enable() do { \ - __asm__ __volatile__ ( \ - "sti %0;" \ - ::"d"(irq_flags)); \ -} while (0) +#define local_irq_enable() \ + __asm__ __volatile__( \ + "sti %0;" \ + : \ + : "d" (irq_flags) \ + ) -#define local_irq_disable() do { \ - int _tmp_dummy; \ - __asm__ __volatile__ ( \ - "cli %0;" \ - :"=d" (_tmp_dummy):); \ -} while (0) +#define local_irq_disable() \ + do { \ + int __tmp_dummy; \ + __asm__ __volatile__( \ + "cli %0;" \ + : "=d" (__tmp_dummy) \ + ); \ + } while (0) -#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE) -#define idle_with_irq_disabled() do { \ - __asm__ __volatile__ ( \ - "nop; nop;\n" \ - ".align 8;\n" \ - "sti %0; idle;\n" \ - ::"d" (irq_flags)); \ -} while (0) +#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) +# define NOP_PAD_ANOMALY_05000244 "nop; nop;" #else -#define idle_with_irq_disabled() do { \ - __asm__ __volatile__ ( \ - ".align 8;\n" \ - "sti %0; idle;\n" \ - ::"d" (irq_flags)); \ -} while (0) +# define NOP_PAD_ANOMALY_05000244 #endif +#define idle_with_irq_disabled() \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000244 \ + ".align 8;" \ + "sti %0;" \ + "idle;" \ + : \ + : "d" (irq_flags) \ + ) + #ifdef CONFIG_DEBUG_HWERR -#define __save_and_cli(x) do { \ - __asm__ __volatile__ ( \ - "cli %0;\n\tsti %1;" \ - :"=&d"(x): "d" (0x3F)); \ -} while (0) +# define __save_and_cli(x) \ + __asm__ __volatile__( \ + "cli %0;" \ + "sti %1;" \ + : "=&d" (x) \ + : "d" (0x3F) \ + ) #else -#define __save_and_cli(x) do { \ - __asm__ __volatile__ ( \ - "cli %0;" \ - :"=&d"(x):); \ -} while (0) +# define __save_and_cli(x) \ + __asm__ __volatile__( \ + "cli %0;" \ + : "=&d" (x) \ + ) #endif -#define local_save_flags(x) asm volatile ("cli %0;" \ - "sti %0;" \ - :"=d"(x):); +#define local_save_flags(x) \ + __asm__ __volatile__( \ + "cli %0;" \ + "sti %0;" \ + : "=d" (x) \ + ) #ifdef CONFIG_DEBUG_HWERR #define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0) @@ -97,10 +105,11 @@ extern unsigned long irq_flags; #define irqs_enabled_from_flags(x) ((x) != 0x1f) #endif -#define local_irq_restore(x) do { \ - if (irqs_enabled_from_flags(x)) \ - local_irq_enable (); \ -} while (0) +#define local_irq_restore(x) \ + do { \ + if (irqs_enabled_from_flags(x)) \ + local_irq_enable(); \ + } while (0) /* For spinlocks etc */ #define local_irq_save(x) __save_and_cli(x) diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h index 4eac38de8ce1..f37feb7cf895 100644 --- a/include/asm-blackfin/termbits.h +++ b/include/asm-blackfin/termbits.h @@ -140,6 +140,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -155,10 +156,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h index 5c41478a51c6..e31fe859650b 100644 --- a/include/asm-blackfin/termios.h +++ b/include/asm-blackfin/termios.h @@ -98,8 +98,14 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) \ + copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) \ + copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) \ + copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) \ + copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h index fa8f08cf283e..15b99cf4f50b 100644 --- a/include/asm-blackfin/thread_info.h +++ b/include/asm-blackfin/thread_info.h @@ -39,6 +39,11 @@ */ #define ALIGN_PAGE_MASK 0xffffe000 +/* + * Size of kernel stack for each process. This must be a power of 2... + */ +#define THREAD_SIZE 8192 /* 2 pages */ + #ifndef __ASSEMBLY__ typedef unsigned long mm_segment_t; @@ -76,11 +81,6 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) #define init_stack (init_thread_union.stack) -/* - * Size of kernel stack for each process. This must be a power of 2... - */ -#define THREAD_SIZE 8192 /* 2 pages */ - /* How to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) @@ -94,7 +94,7 @@ static inline struct thread_info *current_thread_info(void) struct thread_info *ti; __asm__("%0 = sp;": "=&d"(ti): ); - return (struct thread_info *)((long)ti & ~8191UL); + return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); } /* thread information allocation */ @@ -118,18 +118,16 @@ static inline struct thread_info *current_thread_info(void) * thread information flag bit numbers */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 5 -#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ -#define TIF_FREEZE 7 /* is freezing for suspend */ +#define TIF_MEMDIE 4 +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ +#define TIF_FREEZE 6 /* is freezing for suspend */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h index 9c2474c9a589..6313aace9d59 100644 --- a/include/asm-blackfin/trace.h +++ b/include/asm-blackfin/trace.h @@ -6,23 +6,46 @@ #ifndef _BLACKFIN_TRACE_ #define _BLACKFIN_TRACE_ +/* Normally, we use ON, but you can't turn on software expansion until + * interrupts subsystem is ready + */ + +#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03) +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND +#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2)) +#else +#define BFIN_TRACE_ON (BFIN_TRACE_INIT) +#endif + #ifndef __ASSEMBLY__ +extern unsigned long trace_buff_offset; +extern unsigned long software_trace_buff[]; + /* Trace Macros for C files */ +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + #define trace_buffer_save(x) \ - do { \ - (x) = bfin_read_TBUFCTL(); \ - bfin_write_TBUFCTL((x) & ~TBUFEN); \ - } while (0) + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) #define trace_buffer_restore(x) \ - do { \ - bfin_write_TBUFCTL((x)); \ - } while (0) + do { \ + bfin_write_TBUFCTL((x)); \ + } while (0) +#else /* DEBUG_BFIN_HWTRACE_ON */ + +#define trace_buffer_save(x) +#define trace_buffer_restore(x) +#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ #else /* Trace Macros for Assembly files */ +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + #define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) #define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) @@ -32,12 +55,26 @@ dreg = 0x1; \ [preg] = dreg; -#define trace_buffer_start(preg, dreg) \ +#define trace_buffer_start(preg, dreg) \ preg.L = LO(TBUFCTL); \ preg.H = HI(TBUFCTL); \ - dreg = 0x13; \ + dreg = BFIN_TRACE_ON; \ + [preg] = dreg; + +#define trace_buffer_init(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = BFIN_TRACE_INIT; \ [preg] = dreg; +#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ + +#define trace_buffer_stop(preg, dreg) +#define trace_buffer_start(preg, dreg) +#define trace_buffer_init(preg, dreg) + +#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ + #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE # define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) # define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index 0df9f2d322a3..07ffe8b718c5 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -3,6 +3,7 @@ /* * This file contains the system call numbers. */ +#define __NR_restart_syscall 0 #define __NR_exit 1 #define __NR_fork 2 #define __NR_read 3 @@ -165,13 +166,13 @@ #define __NR_sched_get_priority_min 160 #define __NR_sched_rr_get_interval 161 #define __NR_nanosleep 162 - /* 163 __NR_mremap */ +#define __NR_mremap 163 #define __NR_setresuid 164 #define __NR_getresuid 165 /* 166 __NR_vm86 */ /* 167 __NR_query_module */ /* 168 __NR_poll */ - /* 169 __NR_nfsservctl */ +#define __NR_nfsservctl 169 #define __NR_setresgid 170 #define __NR_getresgid 171 #define __NR_prctl 172 @@ -227,7 +228,7 @@ /* 222 reserved for TUX */ /* 223 reserved for TUX */ #define __NR_gettid 224 - /* 225 __NR_readahead */ +#define __NR_readahead 225 #define __NR_setxattr 226 #define __NR_lsetxattr 227 #define __NR_fsetxattr 228 @@ -287,7 +288,7 @@ #define __NR_mq_timedreceive (__NR_mq_open+3) #define __NR_mq_notify (__NR_mq_open+4) #define __NR_mq_getsetattr (__NR_mq_open+5) - /* 284 __NR_sys_kexec_load */ +#define __NR_kexec_load 284 #define __NR_waitid 285 #define __NR_add_key 286 #define __NR_request_key 287 @@ -352,9 +353,54 @@ #define __NR_shmdt 340 #define __NR_shmget 341 -#define __NR_syscall 342 +#define __NR_splice 342 +#define __NR_sync_file_range 343 +#define __NR_tee 344 +#define __NR_vmsplice 345 + +#define __NR_epoll_pwait 346 +#define __NR_utimensat 347 +#define __NR_signalfd 348 +#define __NR_timerfd 349 +#define __NR_eventfd 350 +#define __NR_pread64 351 +#define __NR_pwrite64 352 +#define __NR_fadvise64 353 +#define __NR_set_robust_list 354 +#define __NR_get_robust_list 355 +#define __NR_fallocate 356 + +#define __NR_syscall 357 #define NR_syscalls __NR_syscall +/* Old optional stuff no one actually uses */ +#define __IGNORE_sysfs +#define __IGNORE_uselib + +/* Implement the newer interfaces */ +#define __IGNORE_mmap +#define __IGNORE_poll +#define __IGNORE_select +#define __IGNORE_utime + +/* Not relevant on no-mmu */ +#define __IGNORE_swapon +#define __IGNORE_swapoff +#define __IGNORE_msync +#define __IGNORE_mlock +#define __IGNORE_munlock +#define __IGNORE_mlockall +#define __IGNORE_munlockall +#define __IGNORE_mincore +#define __IGNORE_madvise +#define __IGNORE_remap_file_pages +#define __IGNORE_mbind +#define __IGNORE_get_mempolicy +#define __IGNORE_set_mempolicy +#define __IGNORE_migrate_pages +#define __IGNORE_move_pages +#define __IGNORE_getcpu + #ifdef __KERNEL__ #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_STAT64 diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h index 770734ce54a6..919b34a084f8 100644 --- a/include/asm-cris/a.out.h +++ b/include/asm-cris/a.out.h @@ -8,6 +8,7 @@ /* grabbed from the intel stuff */ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP struct exec diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h index 7ad853c3f74e..fde39f6c49c7 100644 --- a/include/asm-cris/thread_info.h +++ b/include/asm-cris/thread_info.h @@ -79,14 +79,12 @@ struct thread_info { * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 17 #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-frv/mb86943a.h b/include/asm-frv/mb86943a.h index b89fd0b56bb3..e87ef924bfb4 100644 --- a/include/asm-frv/mb86943a.h +++ b/include/asm-frv/mb86943a.h @@ -36,4 +36,7 @@ #define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70) #define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78) +#define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014) +#define MB86943_PCIARB_EN 0x00000001 + #endif /* _ASM_MB86943A_H */ diff --git a/include/asm-frv/mem-layout.h b/include/asm-frv/mem-layout.h index a025dd4514e7..aaf2a773d9d3 100644 --- a/include/asm-frv/mem-layout.h +++ b/include/asm-frv/mem-layout.h @@ -60,6 +60,7 @@ */ #define BRK_BASE __UL(2 * 1024 * 1024 + PAGE_SIZE) #define STACK_TOP __UL(2 * 1024 * 1024) +#define STACK_TOP_MAX STACK_TOP /* userspace process size */ #ifdef CONFIG_MMU diff --git a/include/asm-frv/thread_info.h b/include/asm-frv/thread_info.h index d881f518e6a9..cc5433e78b52 100644 --- a/include/asm-frv/thread_info.h +++ b/include/asm-frv/thread_info.h @@ -108,18 +108,16 @@ register struct thread_info *__current_thread_info asm("gr15"); * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ -#define TIF_IRET 5 /* return with iret */ -#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */ +#define TIF_IRET 4 /* return with iret */ +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 17 /* OOM killer killed process */ #define TIF_FREEZE 18 /* freezing for suspend */ #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) diff --git a/include/asm-frv/unistd.h b/include/asm-frv/unistd.h index 7306c71a8926..cd84f1771e34 100644 --- a/include/asm-frv/unistd.h +++ b/include/asm-frv/unistd.h @@ -330,10 +330,11 @@ #define __NR_signalfd 321 #define __NR_timerfd 322 #define __NR_eventfd 323 +#define __NR_fallocate 324 #ifdef __KERNEL__ -#define NR_syscalls 324 +#define NR_syscalls 325 #define __ARCH_WANT_IPC_PARSE_VERSION /* #define __ARCH_WANT_OLD_READDIR */ diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h index 344e3091af24..d56fedbb457a 100644 --- a/include/asm-generic/bug.h +++ b/include/asm-generic/bug.h @@ -33,7 +33,7 @@ struct bug_entry { #ifndef HAVE_ARCH_WARN_ON #define WARN_ON(condition) ({ \ - typeof(condition) __ret_warn_on = (condition); \ + int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) { \ printk("WARNING: at %s:%d %s()\n", __FILE__, \ __LINE__, __FUNCTION__); \ @@ -54,7 +54,7 @@ struct bug_entry { #ifndef HAVE_ARCH_WARN_ON #define WARN_ON(condition) ({ \ - typeof(condition) __ret_warn_on = (condition); \ + int __ret_warn_on = !!(condition); \ unlikely(__ret_warn_on); \ }) #endif @@ -62,7 +62,7 @@ struct bug_entry { #define WARN_ON_ONCE(condition) ({ \ static int __warned; \ - typeof(condition) __ret_warn_once = (condition); \ + int __ret_warn_once = !!(condition); \ \ if (unlikely(__ret_warn_once)) \ if (WARN_ON(!__warned)) \ diff --git a/include/asm-generic/libata-portmap.h b/include/asm-generic/libata-portmap.h index 62fb3618293d..cf14f2ff40b6 100644 --- a/include/asm-generic/libata-portmap.h +++ b/include/asm-generic/libata-portmap.h @@ -1,12 +1,7 @@ #ifndef __ASM_GENERIC_LIBATA_PORTMAP_H #define __ASM_GENERIC_LIBATA_PORTMAP_H -#define ATA_PRIMARY_CMD 0x1F0 -#define ATA_PRIMARY_CTL 0x3F6 #define ATA_PRIMARY_IRQ(dev) 14 - -#define ATA_SECONDARY_CMD 0x170 -#define ATA_SECONDARY_CTL 0x376 #define ATA_SECONDARY_IRQ(dev) 15 #endif diff --git a/include/asm-generic/percpu.h b/include/asm-generic/percpu.h index d984a9041436..d85172e9ed45 100644 --- a/include/asm-generic/percpu.h +++ b/include/asm-generic/percpu.h @@ -14,6 +14,11 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; #define DEFINE_PER_CPU(type, name) \ __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp + /* var is in discarded region: offset to particular copy we want */ #define per_cpu(var, cpu) (*({ \ extern int simple_identifier_##var(void); \ @@ -34,6 +39,9 @@ do { \ #define DEFINE_PER_CPU(type, name) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) + #define per_cpu(var, cpu) (*((void)(cpu), &per_cpu__##var)) #define __get_cpu_var(var) per_cpu__##var #define __raw_get_cpu_var(var) per_cpu__##var diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index f605e8d0eed3..5f0d797d33fd 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -2,6 +2,7 @@ #define _ASM_GENERIC_PGTABLE_H #ifndef __ASSEMBLY__ +#ifdef CONFIG_MMU #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* @@ -133,41 +134,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres #endif /* - * A facility to provide lazy MMU batching. This allows PTE updates and - * page invalidations to be delayed until a call to leave lazy MMU mode - * is issued. Some architectures may benefit from doing this, and it is - * beneficial for both shadow and direct mode hypervisors, which may batch - * the PTE updates which happen during this window. Note that using this - * interface requires that read hazards be removed from the code. A read - * hazard could result in the direct mode hypervisor case, since the actual - * write to the page tables may not yet have taken place, so reads though - * a raw PTE pointer after it has been modified are not guaranteed to be - * up to date. This mode can only be entered and left under the protection of - * the page table locks for all page tables which may be modified. In the UP - * case, this is required so that preemption is disabled, and in the SMP case, - * it must synchronize the delayed page table writes properly on other CPUs. - */ -#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE -#define arch_enter_lazy_mmu_mode() do {} while (0) -#define arch_leave_lazy_mmu_mode() do {} while (0) -#define arch_flush_lazy_mmu_mode() do {} while (0) -#endif - -/* - * A facility to provide batching of the reload of page tables with the - * actual context switch code for paravirtualized guests. By convention, - * only one of the lazy modes (CPU, MMU) should be active at any given - * time, entry should never be nested, and entry and exits should always - * be paired. This is for sanity of maintaining and reasoning about the - * kernel code. - */ -#ifndef __HAVE_ARCH_ENTER_LAZY_CPU_MODE -#define arch_enter_lazy_cpu_mode() do {} while (0) -#define arch_leave_lazy_cpu_mode() do {} while (0) -#define arch_flush_lazy_cpu_mode() do {} while (0) -#endif - -/* * When walking page tables, get the address of the next boundary, * or the end address of the range if that comes earlier. Although no * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. @@ -233,6 +199,43 @@ static inline int pmd_none_or_clear_bad(pmd_t *pmd) } return 0; } +#endif /* CONFIG_MMU */ + +/* + * A facility to provide lazy MMU batching. This allows PTE updates and + * page invalidations to be delayed until a call to leave lazy MMU mode + * is issued. Some architectures may benefit from doing this, and it is + * beneficial for both shadow and direct mode hypervisors, which may batch + * the PTE updates which happen during this window. Note that using this + * interface requires that read hazards be removed from the code. A read + * hazard could result in the direct mode hypervisor case, since the actual + * write to the page tables may not yet have taken place, so reads though + * a raw PTE pointer after it has been modified are not guaranteed to be + * up to date. This mode can only be entered and left under the protection of + * the page table locks for all page tables which may be modified. In the UP + * case, this is required so that preemption is disabled, and in the SMP case, + * it must synchronize the delayed page table writes properly on other CPUs. + */ +#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE +#define arch_enter_lazy_mmu_mode() do {} while (0) +#define arch_leave_lazy_mmu_mode() do {} while (0) +#define arch_flush_lazy_mmu_mode() do {} while (0) +#endif + +/* + * A facility to provide batching of the reload of page tables with the + * actual context switch code for paravirtualized guests. By convention, + * only one of the lazy modes (CPU, MMU) should be active at any given + * time, entry should never be nested, and entry and exits should always + * be paired. This is for sanity of maintaining and reasoning about the + * kernel code. + */ +#ifndef __HAVE_ARCH_ENTER_LAZY_CPU_MODE +#define arch_enter_lazy_cpu_mode() do {} while (0) +#define arch_leave_lazy_cpu_mode() do {} while (0) +#define arch_flush_lazy_cpu_mode() do {} while (0) +#endif + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_GENERIC_PGTABLE_H */ diff --git a/include/asm-generic/termios.h b/include/asm-generic/termios.h index 3769e6bd63b1..33dca30a3c45 100644 --- a/include/asm-generic/termios.h +++ b/include/asm-generic/termios.h @@ -63,6 +63,8 @@ static inline int kernel_termios_to_user_termio(struct termio __user *termio, #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __ARCH_TERMIO_GETPUT */ diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 16a466e50681..2fe1b2e67f01 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -79,24 +79,24 @@ static inline void __ustw(__u16 val, __u16 *addr) #define __get_unaligned(ptr, size) ({ \ const void *__gu_p = ptr; \ - __u64 val; \ + __u64 __val; \ switch (size) { \ case 1: \ - val = *(const __u8 *)__gu_p; \ + __val = *(const __u8 *)__gu_p; \ break; \ case 2: \ - val = __uldw(__gu_p); \ + __val = __uldw(__gu_p); \ break; \ case 4: \ - val = __uldl(__gu_p); \ + __val = __uldl(__gu_p); \ break; \ case 8: \ - val = __uldq(__gu_p); \ + __val = __uldq(__gu_p); \ break; \ default: \ bad_unaligned_access_length(); \ }; \ - (__force __typeof__(*(ptr)))val; \ + (__force __typeof__(*(ptr)))__val; \ }) #define __put_unaligned(val, ptr, size) \ diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 84155eb67f1d..0240e0506a07 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -224,7 +224,11 @@ } #define NOTES \ - .notes : { *(.note.*) } :note + .notes : AT(ADDR(.notes) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_notes) = .; \ + *(.note.*) \ + VMLINUX_SYMBOL(__stop_notes) = .; \ + } #define INITCALLS \ *(.initcall0.init) \ @@ -245,3 +249,11 @@ *(.initcall7.init) \ *(.initcall7s.init) +#define PERCPU(align) \ + . = ALIGN(align); \ + __per_cpu_start = .; \ + .data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { \ + *(.data.percpu) \ + *(.data.percpu.shared_aligned) \ + } \ + __per_cpu_end = .; diff --git a/include/asm-h8300/a.out.h b/include/asm-h8300/a.out.h index 3c70939f9f00..aa5d22778235 100644 --- a/include/asm-h8300/a.out.h +++ b/include/asm-h8300/a.out.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-h8300/flat.h b/include/asm-h8300/flat.h index c20eee767d6f..2a873508a9a1 100644 --- a/include/asm-h8300/flat.h +++ b/include/asm-h8300/flat.h @@ -9,6 +9,7 @@ #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) 1 #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) +#define flat_set_persistent(relval, p) 0 /* * on the H8 a couple of the relocations have an instruction in the @@ -18,7 +19,7 @@ */ #define flat_get_relocate_addr(rel) (rel) -#define flat_get_addr_from_rp(rp, relval, flags) \ +#define flat_get_addr_from_rp(rp, relval, flags, persistent) \ (get_unaligned(rp) & ((flags & FLAT_FLAG_GOTPIC) ? 0xffffffff: 0x00ffffff)) #define flat_put_addr_at_rp(rp, addr, rel) \ put_unaligned (((*(char *)(rp)) << 24) | ((addr) & 0x00ffffff), rp) diff --git a/include/asm-h8300/irq.h b/include/asm-h8300/irq.h index 41be646c3514..56eec28cc2c4 100644 --- a/include/asm-h8300/irq.h +++ b/include/asm-h8300/irq.h @@ -59,7 +59,4 @@ static __inline__ int irq_canonicalize(int irq) return irq; } -extern void enable_irq(unsigned int); -extern void disable_irq(unsigned int); - #endif /* _H8300_IRQ_H_ */ diff --git a/include/asm-h8300/thread_info.h b/include/asm-h8300/thread_info.h index aee4009a498e..27bb95e2944c 100644 --- a/include/asm-h8300/thread_info.h +++ b/include/asm-h8300/thread_info.h @@ -86,17 +86,15 @@ static inline struct thread_info *current_thread_info(void) * thread information flag bit numbers */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 5 -#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ +#define TIF_MEMDIE 4 +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-i386/8253pit.h b/include/asm-i386/8253pit.h deleted file mode 100644 index 96c7c3592daf..000000000000 --- a/include/asm-i386/8253pit.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * 8253/8254 Programmable Interval Timer - */ - -#ifndef _8253PIT_H -#define _8253PIT_H - -#include <asm/timex.h> - -#define PIT_TICK_RATE CLOCK_TICK_RATE - -#endif diff --git a/include/asm-i386/Kbuild b/include/asm-i386/Kbuild deleted file mode 100644 index cbf6e8f1087b..000000000000 --- a/include/asm-i386/Kbuild +++ /dev/null @@ -1,12 +0,0 @@ -include include/asm-generic/Kbuild.asm - -header-y += boot.h -header-y += debugreg.h -header-y += ldt.h -header-y += msr-index.h -header-y += ptrace-abi.h -header-y += ucontext.h - -unifdef-y += msr.h -unifdef-y += mtrr.h -unifdef-y += vm86.h diff --git a/include/asm-i386/hpet.h b/include/asm-i386/hpet.h deleted file mode 100644 index dddeedf504b7..000000000000 --- a/include/asm-i386/hpet.h +++ /dev/null @@ -1,120 +0,0 @@ - -#ifndef _I386_HPET_H -#define _I386_HPET_H - -#ifdef CONFIG_HPET_TIMER - -#include <linux/errno.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/time.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/smp.h> - -#include <asm/io.h> -#include <asm/smp.h> -#include <asm/irq.h> -#include <asm/msr.h> -#include <asm/delay.h> -#include <asm/mpspec.h> -#include <asm/uaccess.h> -#include <asm/processor.h> - -#include <linux/timex.h> - -/* - * Documentation on HPET can be found at: - * http://www.intel.com/ial/home/sp/pcmmspec.htm - * ftp://download.intel.com/ial/home/sp/mmts098.pdf - */ - -#define HPET_MMAP_SIZE 1024 - -#define HPET_ID 0x000 -#define HPET_PERIOD 0x004 -#define HPET_CFG 0x010 -#define HPET_STATUS 0x020 -#define HPET_COUNTER 0x0f0 -#define HPET_T0_CFG 0x100 -#define HPET_T0_CMP 0x108 -#define HPET_T0_ROUTE 0x110 -#define HPET_T1_CFG 0x120 -#define HPET_T1_CMP 0x128 -#define HPET_T1_ROUTE 0x130 -#define HPET_T2_CFG 0x140 -#define HPET_T2_CMP 0x148 -#define HPET_T2_ROUTE 0x150 - -#define HPET_ID_LEGSUP 0x00008000 -#define HPET_ID_NUMBER 0x00001f00 -#define HPET_ID_REV 0x000000ff -#define HPET_ID_NUMBER_SHIFT 8 - -#define HPET_CFG_ENABLE 0x001 -#define HPET_CFG_LEGACY 0x002 -#define HPET_LEGACY_8254 2 -#define HPET_LEGACY_RTC 8 - -#define HPET_TN_ENABLE 0x004 -#define HPET_TN_PERIODIC 0x008 -#define HPET_TN_PERIODIC_CAP 0x010 -#define HPET_TN_SETVAL 0x040 -#define HPET_TN_32BIT 0x100 - -/* Use our own asm for 64 bit multiply/divide */ -#define ASM_MUL64_REG(eax_out,edx_out,reg_in,eax_in) \ - __asm__ __volatile__("mull %2" \ - :"=a" (eax_out), "=d" (edx_out) \ - :"r" (reg_in), "0" (eax_in)) - -#define ASM_DIV64_REG(eax_out,edx_out,reg_in,eax_in,edx_in) \ - __asm__ __volatile__("divl %2" \ - :"=a" (eax_out), "=d" (edx_out) \ - :"r" (reg_in), "0" (eax_in), "1" (edx_in)) - -#define KERNEL_TICK_USEC (1000000UL/HZ) /* tick value in microsec */ -/* Max HPET Period is 10^8 femto sec as in HPET spec */ -#define HPET_MAX_PERIOD (100000000UL) -/* - * Min HPET period is 10^5 femto sec just for safety. If it is less than this, - * then 32 bit HPET counter wrapsaround in less than 0.5 sec. - */ -#define HPET_MIN_PERIOD (100000UL) -#define HPET_TICK_RATE (HZ * 100000UL) - -extern unsigned long hpet_address; /* hpet memory map physical address */ -extern int is_hpet_enabled(void); - -#ifdef CONFIG_X86_64 -extern unsigned long hpet_tick; /* hpet clks count per tick */ -extern int hpet_use_timer; -extern int hpet_rtc_timer_init(void); -extern int hpet_enable(void); -extern int is_hpet_capable(void); -extern int hpet_readl(unsigned long a); -#else -extern int hpet_enable(void); -#endif - -#ifdef CONFIG_HPET_EMULATE_RTC -extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask); -extern int hpet_set_rtc_irq_bit(unsigned long bit_mask); -extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec); -extern int hpet_set_periodic_freq(unsigned long freq); -extern int hpet_rtc_dropped_irq(void); -extern int hpet_rtc_timer_init(void); -extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); -#endif /* CONFIG_HPET_EMULATE_RTC */ - -#else - -static inline int hpet_enable(void) { return 0; } - -#endif /* CONFIG_HPET_TIMER */ -#endif /* _I386_HPET_H */ diff --git a/include/asm-i386/i8253.h b/include/asm-i386/i8253.h deleted file mode 100644 index 6cb0dd4dcdde..000000000000 --- a/include/asm-i386/i8253.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __ASM_I8253_H__ -#define __ASM_I8253_H__ - -#include <linux/clockchips.h> - -extern spinlock_t i8253_lock; - -extern struct clock_event_device *global_clock_event; - -/** - * pit_interrupt_hook - hook into timer tick - * @regs: standard registers from interrupt - * - * Call the global clock event handler. - **/ -static inline void pit_interrupt_hook(void) -{ - global_clock_event->event_handler(global_clock_event); -} - -#endif /* __ASM_I8253_H__ */ diff --git a/include/asm-i386/ioctl.h b/include/asm-i386/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-i386/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ioctl.h> diff --git a/include/asm-i386/ipc.h b/include/asm-i386/ipc.h deleted file mode 100644 index a46e3d9c2a3f..000000000000 --- a/include/asm-i386/ipc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ipc.h> diff --git a/include/asm-i386/k8.h b/include/asm-i386/k8.h deleted file mode 100644 index dfd88a6e6040..000000000000 --- a/include/asm-i386/k8.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-x86_64/k8.h> diff --git a/include/asm-i386/pci-direct.h b/include/asm-i386/pci-direct.h deleted file mode 100644 index 4f6738b08206..000000000000 --- a/include/asm-i386/pci-direct.h +++ /dev/null @@ -1 +0,0 @@ -#include "asm-x86_64/pci-direct.h" diff --git a/include/asm-i386/serial.h b/include/asm-i386/serial.h deleted file mode 100644 index 57a4306cdf63..000000000000 --- a/include/asm-i386/serial.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * include/asm-i386/serial.h - */ - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD ( 1843200 / 16 ) diff --git a/include/asm-i386/stacktrace.h b/include/asm-i386/stacktrace.h deleted file mode 100644 index 7d1f6a5cbfca..000000000000 --- a/include/asm-i386/stacktrace.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-x86_64/stacktrace.h> diff --git a/include/asm-i386/timer.h b/include/asm-i386/timer.h deleted file mode 100644 index 153770e25faa..000000000000 --- a/include/asm-i386/timer.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASMi386_TIMER_H -#define _ASMi386_TIMER_H -#include <linux/init.h> -#include <linux/pm.h> - -#define TICK_SIZE (tick_nsec / 1000) - -void setup_pit_timer(void); -unsigned long long native_sched_clock(void); -unsigned long native_calculate_cpu_khz(void); - -extern int timer_ack; -extern int no_timer_check; -extern int no_sync_cmos_clock; -extern int recalibrate_cpu_khz(void); - -#ifndef CONFIG_PARAVIRT -#define get_scheduled_cycles(val) rdtscll(val) -#define calculate_cpu_khz() native_calculate_cpu_khz() -#endif - -#endif diff --git a/include/asm-i386/timex.h b/include/asm-i386/timex.h deleted file mode 100644 index 3666044409f0..000000000000 --- a/include/asm-i386/timex.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * linux/include/asm-i386/timex.h - * - * i386 architecture timex specifications - */ -#ifndef _ASMi386_TIMEX_H -#define _ASMi386_TIMEX_H - -#include <asm/processor.h> -#include <asm/tsc.h> - -#ifdef CONFIG_X86_ELAN -# define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */ -#else -# define CLOCK_TICK_RATE 1193182 /* Underlying HZ */ -#endif - - -extern int read_current_timer(unsigned long *timer_value); -#define ARCH_HAS_READ_CURRENT_TIMER 1 - -#endif diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 5b526357d178..49730ffbbae4 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -100,6 +100,11 @@ const char *acpi_get_sysname (void); int acpi_request_vector (u32 int_type); int acpi_gsi_to_irq (u32 gsi, unsigned int *irq); +/* routines for saving/restoring kernel state */ +extern int acpi_save_state_mem(void); +extern void acpi_restore_state_mem(void); +extern unsigned long acpi_wakeup_address; + /* * Record the cpei override flag and current logical cpu. This is * useful for CPU removal. diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h index 1fc3b83325da..50c2b83fd5a0 100644 --- a/include/asm-ia64/atomic.h +++ b/include/asm-ia64/atomic.h @@ -55,7 +55,7 @@ ia64_atomic64_add (__s64 i, atomic64_t *v) do { CMPXCHG_BUGCHECK(v); - old = atomic_read(v); + old = atomic64_read(v); new = old + i; } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); return new; @@ -83,7 +83,7 @@ ia64_atomic64_sub (__s64 i, atomic64_t *v) do { CMPXCHG_BUGCHECK(v); - old = atomic_read(v); + old = atomic64_read(v); new = old - i; } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); return new; diff --git a/include/asm-ia64/hpsim.h b/include/asm-ia64/hpsim.h new file mode 100644 index 000000000000..892ab198a9da --- /dev/null +++ b/include/asm-ia64/hpsim.h @@ -0,0 +1,16 @@ +#ifndef _ASMIA64_HPSIM_H +#define _ASMIA64_HPSIM_H + +#ifndef CONFIG_HP_SIMSERIAL_CONSOLE +static inline int simcons_register(void) { return 1; } +#else +int simcons_register(void); +#endif + +struct tty_driver; +extern struct tty_driver *hp_simserial_driver; + +void ia64_ssc_connect_irq(long intr, long irq); +void ia64_ctl_trace(long on); + +#endif diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h index c054d7a9aaa7..bba5baa3c7fc 100644 --- a/include/asm-ia64/hw_irq.h +++ b/include/asm-ia64/hw_irq.h @@ -90,13 +90,27 @@ enum { extern __u8 isa_irq_to_vector_map[16]; #define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] +struct irq_cfg { + ia64_vector vector; + cpumask_t domain; +}; +extern spinlock_t vector_lock; +extern struct irq_cfg irq_cfg[NR_IRQS]; +#define irq_to_domain(x) irq_cfg[(x)].domain +DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); + extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ +extern int bind_irq_vector(int irq, int vector, cpumask_t domain); extern int assign_irq_vector (int irq); /* allocate a free vector */ extern void free_irq_vector (int vector); extern int reserve_irq_vector (int vector); +extern void __setup_vector_irq(int cpu); +extern int reassign_irq_vector(int irq, int cpu); extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); extern void register_percpu_irq (ia64_vector vec, struct irqaction *action); +extern int check_irq_used (int irq); +extern void destroy_and_reserve_irq (unsigned int irq); static inline void ia64_resend_irq(unsigned int vector) { @@ -110,10 +124,15 @@ static inline void ia64_resend_irq(unsigned int vector) extern irq_desc_t irq_desc[NR_IRQS]; #ifndef CONFIG_IA64_GENERIC +static inline ia64_vector __ia64_irq_to_vector(int irq) +{ + return irq_cfg[irq].vector; +} + static inline unsigned int __ia64_local_vector_to_irq (ia64_vector vec) { - return (unsigned int) vec; + return __get_cpu_var(vector_irq)[vec]; } #endif @@ -131,7 +150,7 @@ __ia64_local_vector_to_irq (ia64_vector vec) static inline ia64_vector irq_to_vector (int irq) { - return (ia64_vector) irq; + return platform_irq_to_vector(irq); } /* diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h index 5ff8d74c3e00..2390ee145aa1 100644 --- a/include/asm-ia64/ia32.h +++ b/include/asm-ia64/ia32.h @@ -27,11 +27,12 @@ extern int ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs) extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set, struct pt_regs *regs); #if PAGE_SHIFT > IA32_PAGE_SHIFT -extern int ia32_copy_partial_page_list (struct task_struct *, unsigned long); -extern void ia32_drop_partial_page_list (struct task_struct *); +extern int ia32_copy_ia64_partial_page_list(struct task_struct *, + unsigned long); +extern void ia32_drop_ia64_partial_page_list(struct task_struct *); #else -# define ia32_copy_partial_page_list(a1, a2) 0 -# define ia32_drop_partial_page_list(a1) do { ; } while (0) +# define ia32_copy_ia64_partial_page_list(a1, a2) 0 +# define ia32_drop_ia64_partial_page_list(a1) do { ; } while (0) #endif #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h index 421cb6b62a7c..b8f712859140 100644 --- a/include/asm-ia64/iosapic.h +++ b/include/asm-ia64/iosapic.h @@ -47,19 +47,21 @@ #define IOSAPIC_MASK_SHIFT 16 #define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT) +#define IOSAPIC_VECTOR_MASK 0xffffff00 + #ifndef __ASSEMBLY__ #ifdef CONFIG_IOSAPIC #define NR_IOSAPICS 256 -static inline unsigned int iosapic_read(char __iomem *iosapic, unsigned int reg) +static inline unsigned int __iosapic_read(char __iomem *iosapic, unsigned int reg) { writel(reg, iosapic + IOSAPIC_REG_SELECT); return readl(iosapic + IOSAPIC_WINDOW); } -static inline void iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) +static inline void __iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) { writel(reg, iosapic + IOSAPIC_REG_SELECT); writel(val, iosapic + IOSAPIC_WINDOW); diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h index 67221615e317..a66d26827cbb 100644 --- a/include/asm-ia64/irq.h +++ b/include/asm-ia64/irq.h @@ -14,8 +14,13 @@ #include <linux/types.h> #include <linux/cpumask.h> -#define NR_IRQS 256 -#define NR_IRQ_VECTORS NR_IRQS +#define NR_VECTORS 256 + +#if (NR_VECTORS + 32 * NR_CPUS) < 1024 +#define NR_IRQS (NR_VECTORS + 32 * NR_CPUS) +#else +#define NR_IRQS 1024 +#endif static __inline__ int irq_canonicalize (int irq) @@ -28,9 +33,6 @@ irq_canonicalize (int irq) return ((irq == 2) ? 9 : irq); } -extern void disable_irq (unsigned int); -extern void disable_irq_nosync (unsigned int); -extern void enable_irq (unsigned int); extern void set_irq_affinity_info (unsigned int irq, int dest, int redir); bool is_affinity_mask_valid(cpumask_t cpumask); diff --git a/include/asm-ia64/kprobes.h b/include/asm-ia64/kprobes.h index 6382e52ec227..067d9dea68f9 100644 --- a/include/asm-ia64/kprobes.h +++ b/include/asm-ia64/kprobes.h @@ -82,8 +82,6 @@ struct kprobe_ctlblk { struct prev_kprobe prev_kprobe[ARCH_PREV_KPROBE_SZ]; }; -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry - #define ARCH_SUPPORTS_KRETPROBES #define ARCH_INACTIVE_KPROBE_COUNT 1 diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index ca33eb181ff2..c201a2020aa4 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -30,6 +30,7 @@ typedef void ia64_mv_send_ipi_t (int, int, int, int); typedef void ia64_mv_timer_interrupt_t (int, void *); typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long); typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *); +typedef u8 ia64_mv_irq_to_vector (int); typedef unsigned int ia64_mv_local_vector_to_irq (u8); typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *); typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val, @@ -145,6 +146,7 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *); # define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device # define platform_dma_mapping_error ia64_mv.dma_mapping_error # define platform_dma_supported ia64_mv.dma_supported +# define platform_irq_to_vector ia64_mv.irq_to_vector # define platform_local_vector_to_irq ia64_mv.local_vector_to_irq # define platform_pci_get_legacy_mem ia64_mv.pci_get_legacy_mem # define platform_pci_legacy_read ia64_mv.pci_legacy_read @@ -198,6 +200,7 @@ struct ia64_machine_vector { ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device; ia64_mv_dma_mapping_error *dma_mapping_error; ia64_mv_dma_supported *dma_supported; + ia64_mv_irq_to_vector *irq_to_vector; ia64_mv_local_vector_to_irq *local_vector_to_irq; ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem; ia64_mv_pci_legacy_read_t *pci_legacy_read; @@ -247,6 +250,7 @@ struct ia64_machine_vector { platform_dma_sync_sg_for_device, \ platform_dma_mapping_error, \ platform_dma_supported, \ + platform_irq_to_vector, \ platform_local_vector_to_irq, \ platform_pci_get_legacy_mem, \ platform_pci_legacy_read, \ @@ -275,6 +279,7 @@ struct ia64_machine_vector { extern struct ia64_machine_vector ia64_mv; extern void machvec_init (const char *name); +extern void machvec_init_from_cmdline(const char *cmdline); # else # error Unknown configuration. Update asm-ia64/machvec.h. @@ -365,6 +370,9 @@ extern ia64_mv_dma_supported swiotlb_dma_supported; #ifndef platform_dma_supported # define platform_dma_supported swiotlb_dma_supported #endif +#ifndef platform_irq_to_vector +# define platform_irq_to_vector __ia64_irq_to_vector +#endif #ifndef platform_local_vector_to_irq # define platform_local_vector_to_irq __ia64_local_vector_to_irq #endif diff --git a/include/asm-ia64/machvec_init.h b/include/asm-ia64/machvec_init.h index 2d36f6840f0b..7f21249fba3f 100644 --- a/include/asm-ia64/machvec_init.h +++ b/include/asm-ia64/machvec_init.h @@ -2,6 +2,7 @@ extern ia64_mv_send_ipi_t ia64_send_ipi; extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge; +extern ia64_mv_irq_to_vector __ia64_irq_to_vector; extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq; extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem; extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read; diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h index eaa2fce0fecd..61439a7f5b08 100644 --- a/include/asm-ia64/machvec_sn2.h +++ b/include/asm-ia64/machvec_sn2.h @@ -35,6 +35,7 @@ extern ia64_mv_send_ipi_t sn2_send_IPI; extern ia64_mv_timer_interrupt_t sn_timer_interrupt; extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge; extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish; +extern ia64_mv_irq_to_vector sn_irq_to_vector; extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq; extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem; extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read; @@ -104,6 +105,7 @@ extern ia64_mv_pci_fixup_bus_t sn_pci_fixup_bus; #define platform_readw_relaxed __sn_readw_relaxed #define platform_readl_relaxed __sn_readl_relaxed #define platform_readq_relaxed __sn_readq_relaxed +#define platform_irq_to_vector sn_irq_to_vector #define platform_local_vector_to_irq sn_local_vector_to_irq #define platform_pci_get_legacy_mem sn_pci_get_legacy_mem #define platform_pci_legacy_read sn_pci_legacy_read diff --git a/include/asm-ia64/percpu.h b/include/asm-ia64/percpu.h index fbe5cf3ab8dc..43a7aac414e0 100644 --- a/include/asm-ia64/percpu.h +++ b/include/asm-ia64/percpu.h @@ -29,6 +29,16 @@ __attribute__((__section__(".data.percpu"))) \ __SMALL_ADDR_AREA __typeof__(type) per_cpu__##name +#ifdef CONFIG_SMP +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __SMALL_ADDR_AREA __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp +#else +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) +#endif + /* * Pretty much a literal copy of asm-generic/percpu.h, except that percpu_modcopy() is an * external routine, to avoid include-hell. diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index db81ba406cef..be3b0ae43270 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -220,7 +220,7 @@ struct desc_struct { #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8) -struct partial_page_list; +struct ia64_partial_page_list; #endif struct thread_struct { @@ -242,7 +242,7 @@ struct thread_struct { __u64 fdr; /* IA32 fp except. data reg */ __u64 old_k1; /* old value of ar.k1 */ __u64 old_iob; /* old IOBase value */ - struct partial_page_list *ppl; /* partial page list for 4K page size issue */ + struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */ /* cached TLS descriptors. */ struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; @@ -295,9 +295,9 @@ struct thread_struct { regs->ar_bspstore = current->thread.rbs_bot; \ regs->ar_fpsr = FPSR_DEFAULT; \ regs->loadrs = 0; \ - regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \ + regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \ regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \ - if (unlikely(!current->mm->dumpable)) { \ + if (unlikely(!get_dumpable(current->mm))) { \ /* \ * Zap scratch regs to avoid leaking bits between processes with different \ * uid/privileges. \ diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h index 2d1640cc240a..8aba06a7b038 100644 --- a/include/asm-ia64/rwsem.h +++ b/include/asm-ia64/rwsem.h @@ -21,6 +21,10 @@ #ifndef _ASM_IA64_RWSEM_H #define _ASM_IA64_RWSEM_H +#ifndef _LINUX_RWSEM_H +#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead." +#endif + #include <linux/list.h> #include <linux/spinlock.h> diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index c60024989ebd..6314b29e8c4d 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -116,7 +116,6 @@ max_xtp (void) extern int __cpu_disable (void); extern void __cpu_die (unsigned int cpu); extern void cpu_die (void) __attribute__ ((noreturn)); -extern int __cpu_up (unsigned int cpu); extern void __init smp_build_cpu_map(void); extern void __init init_smp_config (void); diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 16adc93d7a72..7caa1f44cd95 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -81,5 +81,6 @@ extern u8 sn_sharing_domain_size; extern u8 sn_region_size; extern void sn_flush_all_caches(long addr, long bytes); +extern bool sn_cpu_disable_allowed(int cpu); #endif /* _ASM_IA64_SN_ARCH_H */ diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index 12b54ddb06be..e0487aa97418 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -60,6 +60,7 @@ extern u64 sn_intr_alloc(nasid_t, int, int, nasid_t, int); extern void sn_intr_free(nasid_t, int, struct sn_irq_info *); extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int); +extern void sn_set_err_irq_affinity(unsigned int); extern struct list_head **sn_irq_lh; #define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector) diff --git a/include/asm-ia64/sn/sn_feature_sets.h b/include/asm-ia64/sn/sn_feature_sets.h index bfdc36273ed4..8e83ac117ace 100644 --- a/include/asm-ia64/sn/sn_feature_sets.h +++ b/include/asm-ia64/sn/sn_feature_sets.h @@ -31,6 +31,7 @@ extern int sn_prom_feature_available(int id); #define PRF_PAL_CACHE_FLUSH_SAFE 0 #define PRF_DEVICE_FLUSH_LIST 1 #define PRF_HOTPLUG_SUPPORT 2 +#define PRF_CPU_DISABLE_SUPPORT 3 /* --------------------- OS Features -------------------------------*/ diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 384fbf7f2a0f..91bb8e00066c 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -259,7 +259,6 @@ extern void ia64_load_extra (struct task_struct *task); #define ia64_platform_is(x) (strcmp(x, platform_name) == 0) void cpu_idle_wait(void); -void sched_cacheflush(void); #define arch_align_stack(x) (x) diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h index 7d0241db622b..d16031e72efa 100644 --- a/include/asm-ia64/thread_info.h +++ b/include/asm-ia64/thread_info.h @@ -79,13 +79,13 @@ struct thread_info { * - pending work-to-be-done flags are in least-significant 16 bits, other flags * in top 16 bits */ -#define TIF_NOTIFY_RESUME 0 /* resumption notification requested */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_SYSCALL_TRACE 3 /* syscall trace active */ -#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ -#define TIF_SINGLESTEP 5 /* restore singlestep on return to user mode */ -#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ +#define TIF_SIGPENDING 0 /* signal pending */ +#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ +#define TIF_SYSCALL_TRACE 2 /* syscall trace active */ +#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ +#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ +#define TIF_PERFMON_WORK 6 /* work for pfm_handle_work() */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 17 #define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */ @@ -96,8 +96,8 @@ struct thread_info { #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) #define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) +#define _TIF_PERFMON_WORK (1 << TIF_PERFMON_WORK) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) @@ -106,7 +106,9 @@ struct thread_info { #define _TIF_FREEZE (1 << TIF_FREEZE) /* "work to do on user-return" bits */ -#define TIF_ALLWORK_MASK (_TIF_NOTIFY_RESUME|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_RESTORE_SIGMASK) +#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_PERFMON_WORK|_TIF_SYSCALL_AUDIT|\ + _TIF_NEED_RESCHED| _TIF_SYSCALL_TRACE|\ + _TIF_RESTORE_SIGMASK) /* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */ #define TIF_WORK_MASK (TIF_ALLWORK_MASK&~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)) diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index 441c9e001776..315f8de950a2 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -292,7 +292,7 @@ #define __NR_sync_file_range 1300 #define __NR_tee 1301 #define __NR_vmsplice 1302 -/* 1303 reserved for move_pages */ +#define __NR_fallocate 1303 #define __NR_getcpu 1304 #define __NR_epoll_pwait 1305 #define __NR_utimensat 1306 diff --git a/include/asm-ia64/ustack.h b/include/asm-ia64/ustack.h index a349467913ea..504167c35b8b 100644 --- a/include/asm-ia64/ustack.h +++ b/include/asm-ia64/ustack.h @@ -11,6 +11,7 @@ /* The absolute hard limit for stack size is 1/2 of the mappable space in the region */ #define MAX_USER_STACK_SIZE (RGN_MAP_LIMIT/2) #define STACK_TOP (0x6000000000000000UL + RGN_MAP_LIMIT) +#define STACK_TOP_MAX STACK_TOP #endif /* Make a default stack size of 2GiB */ diff --git a/include/asm-m32r/a.out.h b/include/asm-m32r/a.out.h index 9a4a5d20160a..6a1b5d42f328 100644 --- a/include/asm-m32r/a.out.h +++ b/include/asm-m32r/a.out.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-m32r/assembler.h b/include/asm-m32r/assembler.h index 47041d19d4a8..26351539b5ff 100644 --- a/include/asm-m32r/assembler.h +++ b/include/asm-m32r/assembler.h @@ -52,27 +52,27 @@ .endm #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) -#define STI(reg) STI_M reg - .macro STI_M reg +#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg + .macro ENABLE_INTERRUPTS reg setpsw #0x40 -> nop ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). .endm -#define CLI(reg) CLI_M reg - .macro CLI_M reg +#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg + .macro DISABLE_INTERRUPTS reg clrpsw #0x40 -> nop ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). .endm #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ -#define STI(reg) STI_M reg - .macro STI_M reg +#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg + .macro ENABLE_INTERRUPTS reg mvfc \reg, psw or3 \reg, \reg, #0x0040 mvtc \reg, psw .endm -#define CLI(reg) CLI_M reg - .macro CLI_M reg +#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg + .macro DISABLE_INTERRUPTS reg mvfc \reg, psw and3 \reg, \reg, #0xffbf mvtc \reg, psw diff --git a/include/asm-m32r/flat.h b/include/asm-m32r/flat.h index 1b285f65cab6..d851cf0c4aa5 100644 --- a/include/asm-m32r/flat.h +++ b/include/asm-m32r/flat.h @@ -15,9 +15,10 @@ #define flat_stack_align(sp) (*sp += (*sp & 3 ? (4 - (*sp & 3)): 0)) #define flat_argvp_envp_on_stack() 0 #define flat_old_ram_flag(flags) (flags) +#define flat_set_persistent(relval, p) 0 #define flat_reloc_valid(reloc, size) \ (((reloc) - textlen_for_m32r_lo16_data) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags) \ +#define flat_get_addr_from_rp(rp, relval, flags, persistent) \ m32r_flat_get_addr_from_rp(rp, relval, (text_len) ) #define flat_put_addr_at_rp(rp, addr, relval) \ diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h index decfc59907c7..214b44b40757 100644 --- a/include/asm-m32r/m32r.h +++ b/include/asm-m32r/m32r.h @@ -22,12 +22,26 @@ #include <asm/m32700ut/m32700ut_pld.h> #include <asm/m32700ut/m32700ut_lan.h> #include <asm/m32700ut/m32700ut_lcd.h> +/* for ei_handler:linux/arch/m32r/kernel/entry.S */ +#define M32R_INT1ICU_ISTS PLD_ICUISTS +#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE +#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS +#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE +#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS +#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE #endif /* CONFIG_PLAT_M32700UT */ #if defined(CONFIG_PLAT_OPSPUT) #include <asm/opsput/opsput_pld.h> #include <asm/opsput/opsput_lan.h> #include <asm/opsput/opsput_lcd.h> +/* for ei_handler:linux/arch/m32r/kernel/entry.S */ +#define M32R_INT1ICU_ISTS PLD_ICUISTS +#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE +#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS +#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE +#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS +#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE #endif /* CONFIG_PLAT_OPSPUT */ #if defined(CONFIG_PLAT_MAPPI2) @@ -40,10 +54,16 @@ #if defined(CONFIG_PLAT_USRV) #include <asm/m32700ut/m32700ut_pld.h> +/* for ei_handler:linux/arch/m32r/kernel/entry.S */ +#define M32R_INT1ICU_ISTS PLD_ICUISTS +#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE #endif #if defined(CONFIG_PLAT_M32104UT) #include <asm/m32104ut/m32104ut_pld.h> +/* for ei_handler:linux/arch/m32r/kernel/entry.S */ +#define M32R_INT1ICU_ISTS PLD_ICUISTS +#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE #endif /* CONFIG_PLAT_M32104 */ /* diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index 8ee73d3f316d..2365de5c2955 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h @@ -54,16 +54,6 @@ ); \ } while(0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - /* Interrupt Control */ #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) #define local_irq_enable() \ diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h index 22aff3222d22..b7ccc3e68604 100644 --- a/include/asm-m32r/thread_info.h +++ b/include/asm-m32r/thread_info.h @@ -146,17 +146,15 @@ static inline unsigned int get_thread_fault_code(void) * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ -#define TIF_IRET 5 /* return with iret */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */ +#define TIF_IRET 4 /* return with iret */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ /* 31..28 fault code */ #define TIF_MEMDIE 17 #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) diff --git a/include/asm-m68k/a.out.h b/include/asm-m68k/a.out.h index eda1662773b8..6fc86a221a94 100644 --- a/include/asm-m68k/a.out.h +++ b/include/asm-m68k/a.out.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 5e0fcf41804d..47bb9cf107b7 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -27,6 +27,7 @@ #include <asm/raw_io.h> #include <asm/virtconvert.h> +#include <asm-generic/iomap.h> #ifdef CONFIG_ATARI #include <asm/atarihw.h> @@ -152,6 +153,16 @@ static inline u16 __iomem *isa_itw(unsigned long addr) default: return NULL; /* avoid warnings, just in case */ } } +static inline u32 __iomem *isa_itl(unsigned long addr) +{ + switch(ISA_TYPE) + { +#ifdef CONFIG_AMIGA_PCMCIA + case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr); +#endif + default: return 0; /* avoid warnings, just in case */ + } +} static inline u8 __iomem *isa_mtb(unsigned long addr) { switch(ISA_TYPE) @@ -188,8 +199,10 @@ static inline u16 __iomem *isa_mtw(unsigned long addr) #define isa_inb(port) in_8(isa_itb(port)) #define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port))) +#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port))) #define isa_outb(val,port) out_8(isa_itb(port),(val)) #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val))) +#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val))) #define isa_readb(p) in_8(isa_mtb((unsigned long)(p))) #define isa_readw(p) \ @@ -234,6 +247,15 @@ static inline void isa_delay(void) #define isa_outsw(port, buf, nr) \ (ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \ raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr))) + +#define isa_insl(port, buf, nr) \ + (ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \ + raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1)) + +#define isa_outsl(port, buf, nr) \ + (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \ + raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1)) + #endif /* CONFIG_ISA */ @@ -246,14 +268,16 @@ static inline void isa_delay(void) #define inw_p isa_inw_p #define outw isa_outw #define outw_p isa_outw_p -#define inl isa_inw -#define inl_p isa_inw_p -#define outl isa_outw -#define outl_p isa_outw_p +#define inl isa_inl +#define inl_p isa_inl_p +#define outl isa_outl +#define outl_p isa_outl_p #define insb isa_insb #define insw isa_insw +#define insl isa_insl #define outsb isa_outsb #define outsw isa_outsw +#define outsl isa_outsl #define readb isa_readb #define readw isa_readw #define writeb isa_writeb @@ -262,8 +286,6 @@ static inline void isa_delay(void) #if defined(CONFIG_PCI) -#define inl(port) in_le32(port) -#define outl(val,port) out_le32((port),(val)) #define readl(addr) in_le32(addr) #define writel(val,addr) out_le32((addr),(val)) @@ -282,6 +304,8 @@ static inline void isa_delay(void) #define outb(val,port) out_8((port),(val)) #define inw(port) in_le16(port) #define outw(val,port) out_le16((port),(val)) +#define inl(port) in_le32(port) +#define outl(val,port) out_le32((port),(val)) #else /* @@ -306,20 +330,35 @@ static inline void isa_delay(void) #endif #endif /* CONFIG_PCI */ -#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI) && defined(CONFIG_HP300) +#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI) /* - * We need to define dummy functions otherwise drivers/serial/8250.c doesn't link + * We need to define dummy functions for GENERIC_IOMAP support. */ -#define inb(port) 0xff -#define inb_p(port) 0xff -#define outb(val,port) do { } while (0) -#define outb_p(val,port) do { } while (0) +#define inb(port) 0xff +#define inb_p(port) 0xff +#define outb(val,port) ((void)0) +#define outb_p(val,port) ((void)0) +#define inw(port) 0xffff +#define outw(val,port) ((void)0) +#define inl(port) 0xffffffffUL +#define outl(val,port) ((void)0) + +#define insb(port,buf,nr) ((void)0) +#define outsb(port,buf,nr) ((void)0) +#define insw(port,buf,nr) ((void)0) +#define outsw(port,buf,nr) ((void)0) +#define insl(port,buf,nr) ((void)0) +#define outsl(port,buf,nr) ((void)0) /* * These should be valid on any ioremap()ed region */ #define readb(addr) in_8(addr) #define writeb(val,addr) out_8((addr),(val)) +#define readw(addr) in_le16(addr) +#define writew(val,addr) out_le16((addr),(val)) +#endif +#if !defined(CONFIG_PCI) #define readl(addr) in_le32(addr) #define writel(val,addr) out_le32((addr),(val)) #endif @@ -351,6 +390,18 @@ extern void dma_cache_wback_inv(unsigned long start, unsigned long size); extern void dma_cache_wback(unsigned long start, unsigned long size); extern void dma_cache_inv(unsigned long start, unsigned long size); +static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) +{ + __builtin_memset((void __force *) addr, val, count); +} +static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) +{ + __builtin_memcpy(dst, (void __force *) src, count); +} +static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) +{ + __builtin_memcpy((void __force *) dst, src, count); +} #ifndef CONFIG_SUN3 #define IO_SPACE_LIMIT 0xffff diff --git a/include/asm-m68k/ioctls.h b/include/asm-m68k/ioctls.h index 0c48929ab444..b8d2f4be7fd7 100644 --- a/include/asm-m68k/ioctls.h +++ b/include/asm-m68k/ioctls.h @@ -46,6 +46,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-m68k/irq.h b/include/asm-m68k/irq.h index 4901cb105e2f..eb29a5260591 100644 --- a/include/asm-m68k/irq.h +++ b/include/asm-m68k/irq.h @@ -59,9 +59,6 @@ #define IRQ_USER 8 extern unsigned int irq_canonicalize(unsigned int irq); -extern void enable_irq(unsigned int); -extern void disable_irq(unsigned int); -#define disable_irq_nosync disable_irq struct pt_regs; diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h index 9e6d0d6debdb..1431ea0b59e0 100644 --- a/include/asm-m68k/page.h +++ b/include/asm-m68k/page.h @@ -4,17 +4,15 @@ #ifdef __KERNEL__ +#include <linux/const.h> + /* PAGE_SHIFT determines the page size */ #ifndef CONFIG_SUN3 #define PAGE_SHIFT (12) #else #define PAGE_SHIFT (13) #endif -#ifdef __ASSEMBLY__ -#define PAGE_SIZE (1 << PAGE_SHIFT) -#else -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#endif +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #include <asm/setup.h> @@ -27,6 +25,8 @@ #ifndef __ASSEMBLY__ +#include <linux/compiler.h> + #include <asm/module.h> #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h index 8455f778b601..4453ec379c5d 100644 --- a/include/asm-m68k/processor.h +++ b/include/asm-m68k/processor.h @@ -38,12 +38,8 @@ static inline void wrusp(unsigned long usp) #ifndef CONFIG_SUN3 #define TASK_SIZE (0xF0000000UL) #else -#ifdef __ASSEMBLY__ -#define TASK_SIZE (0x0E000000) -#else #define TASK_SIZE (0x0E000000UL) #endif -#endif /* This decides where the kernel will search for a free chunk of vm * space during mmap's. diff --git a/include/asm-m68k/raw_io.h b/include/asm-m68k/raw_io.h index 811ccd25d4a6..d9eb9834ccc8 100644 --- a/include/asm-m68k/raw_io.h +++ b/include/asm-m68k/raw_io.h @@ -36,23 +36,29 @@ extern void __iounmap(void *addr, unsigned long size); #define in_be32(addr) \ ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; }) #define in_le16(addr) \ - ({ u16 __v = le16_to_cpu(*(__force volatile u16 *) (addr)); __v; }) + ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; }) #define in_le32(addr) \ - ({ u32 __v = le32_to_cpu(*(__force volatile u32 *) (addr)); __v; }) + ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; }) #define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b)) #define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w)) #define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l)) -#define out_le16(addr,w) (void)((*(__force volatile u16 *) (addr)) = cpu_to_le16(w)) -#define out_le32(addr,l) (void)((*(__force volatile u32 *) (addr)) = cpu_to_le32(l)) +#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w)) +#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l)) #define raw_inb in_8 #define raw_inw in_be16 #define raw_inl in_be32 +#define __raw_readb in_8 +#define __raw_readw in_be16 +#define __raw_readl in_be32 #define raw_outb(val,port) out_8((port),(val)) #define raw_outw(val,port) out_be16((port),(val)) #define raw_outl(val,port) out_be32((port),(val)) +#define __raw_writeb(val,addr) out_8((addr),(val)) +#define __raw_writew(val,addr) out_be16((addr),(val)) +#define __raw_writel(val,addr) out_be32((addr),(val)) static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len) { @@ -336,8 +342,6 @@ static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf, : "d0", "a0", "a1", "d6"); } -#define __raw_writel raw_outl - #endif /* __KERNEL__ */ #endif /* _RAW_IO_H */ diff --git a/include/asm-m68k/system.h b/include/asm-m68k/system.h index 198878b53a61..caa9b1663e45 100644 --- a/include/asm-m68k/system.h +++ b/include/asm-m68k/system.h @@ -46,6 +46,22 @@ asmlinkage void resume(void); } while (0) +/* + * Force strict CPU ordering. + * Not really required on m68k... + */ +#define nop() do { asm volatile ("nop"); barrier(); } while (0) +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define read_barrier_depends() ((void)0) +#define set_mb(var, value) ({ (var) = (value); wmb(); }) + +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() ((void)0) + /* interrupt control.. */ #if 0 #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") @@ -70,23 +86,6 @@ static inline int irqs_disabled(void) /* For spinlocks etc */ #define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); }) -/* - * Force strict CPU ordering. - * Not really required on m68k... - */ -#define nop() do { asm volatile ("nop"); barrier(); } while (0) -#define mb() barrier() -#define rmb() barrier() -#define wmb() barrier() -#define read_barrier_depends() ((void)0) -#define set_mb(var, value) ({ (var) = (value); wmb(); }) - -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() ((void)0) - - #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) struct __xchg_dummy { unsigned long a[100]; }; diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h index 0e520f328f53..8c14170996bb 100644 --- a/include/asm-m68k/termbits.h +++ b/include/asm-m68k/termbits.h @@ -141,6 +141,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -156,10 +157,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 diff --git a/include/asm-m68k/termios.h b/include/asm-m68k/termios.h index 00edabd76168..0823032e4045 100644 --- a/include/asm-m68k/termios.h +++ b/include/asm-m68k/termios.h @@ -82,8 +82,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h index fdbb60e6a0d4..a30fe9c64143 100644 --- a/include/asm-m68k/unistd.h +++ b/include/asm-m68k/unistd.h @@ -313,10 +313,20 @@ #define __NR_tee 308 #define __NR_vmsplice 309 #define __NR_move_pages 310 +#define __NR_sched_setaffinity 311 +#define __NR_sched_getaffinity 312 +#define __NR_kexec_load 313 +#define __NR_getcpu 314 +#define __NR_epoll_pwait 315 +#define __NR_utimensat 316 +#define __NR_signalfd 317 +#define __NR_timerfd 318 +#define __NR_eventfd 319 +#define __NR_fallocate 320 #ifdef __KERNEL__ -#define NR_syscalls 311 +#define NR_syscalls 321 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/include/asm-m68knommu/flat.h b/include/asm-m68knommu/flat.h index 2d836edc4344..814b5174a8e0 100644 --- a/include/asm-m68knommu/flat.h +++ b/include/asm-m68knommu/flat.h @@ -9,8 +9,9 @@ #define flat_argvp_envp_on_stack() 1 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp) +#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) +#define flat_set_persistent(relval, p) 0 #endif /* __M68KNOMMU_FLAT_H__ */ diff --git a/include/asm-m68knommu/hardirq.h b/include/asm-m68knommu/hardirq.h index 980075bab792..bfad28149a49 100644 --- a/include/asm-m68knommu/hardirq.h +++ b/include/asm-m68knommu/hardirq.h @@ -22,4 +22,6 @@ typedef struct { # error HARDIRQ_BITS is too low! #endif +void ack_bad_irq(unsigned int irq); + #endif /* __M68K_HARDIRQ_H */ diff --git a/include/asm-m68knommu/hw_irq.h b/include/asm-m68knommu/hw_irq.h new file mode 100644 index 000000000000..f3ec9e5ae049 --- /dev/null +++ b/include/asm-m68knommu/hw_irq.h @@ -0,0 +1,4 @@ +#ifndef __M68KNOMMU_HW_IRQ_H__ +#define __M68KNOMMU_HW_IRQ_H__ + +#endif /* __M68KNOMMU_HW_IRQ_H__ */ diff --git a/include/asm-m68knommu/irq.h b/include/asm-m68knommu/irq.h index 7b8f874f8429..9373c31ac87d 100644 --- a/include/asm-m68knommu/irq.h +++ b/include/asm-m68knommu/irq.h @@ -1,7 +1,5 @@ -#ifndef _M68K_IRQ_H_ -#define _M68K_IRQ_H_ - -#include <asm/ptrace.h> +#ifndef _M68KNOMMU_IRQ_H_ +#define _M68KNOMMU_IRQ_H_ #ifdef CONFIG_COLDFIRE /* @@ -17,75 +15,12 @@ /* * # of m68k interrupts */ -#define SYS_IRQS 8 -#define NR_IRQS (24+SYS_IRQS) +#define SYS_IRQS 8 +#define NR_IRQS (24 + SYS_IRQS) #endif /* CONFIG_COLDFIRE */ -/* - * Interrupt source definitions - * General interrupt sources are the level 1-7. - * Adding an interrupt service routine for one of these sources - * results in the addition of that routine to a chain of routines. - * Each one is called in succession. Each individual interrupt - * service routine should determine if the device associated with - * that routine requires service. - */ -#define IRQ1 (1) /* level 1 interrupt */ -#define IRQ2 (2) /* level 2 interrupt */ -#define IRQ3 (3) /* level 3 interrupt */ -#define IRQ4 (4) /* level 4 interrupt */ -#define IRQ5 (5) /* level 5 interrupt */ -#define IRQ6 (6) /* level 6 interrupt */ -#define IRQ7 (7) /* level 7 interrupt (non-maskable) */ - -/* - * Machine specific interrupt sources. - * - * Adding an interrupt service routine for a source with this bit - * set indicates a special machine specific interrupt source. - * The machine specific files define these sources. - * - * The IRQ_MACHSPEC bit is now gone - the only thing it did was to - * introduce unnecessary overhead. - * - * All interrupt handling is actually machine specific so it is better - * to use function pointers, as used by the Sparc port, and select the - * interrupt handling functions when initializing the kernel. This way - * we save some unnecessary overhead at run-time. - * 01/11/97 - Jes - */ - -extern void (*mach_enable_irq)(unsigned int); -extern void (*mach_disable_irq)(unsigned int); - -/* - * various flags for request_irq() - the Amiga now uses the standard - * mechanism like all other architectures - IRQF_DISABLED and - * IRQF_SHARED are your friends. - */ -#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ -#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ -#define IRQ_FLG_FAST (0x0004) -#define IRQ_FLG_SLOW (0x0008) -#define IRQ_FLG_STD (0x8000) /* internally used */ - -#ifdef CONFIG_M68360 - -#define CPM_INTERRUPT IRQ4 - -/* see MC68360 User's Manual, p. 7-377 */ -#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */ - -#endif /* CONFIG_M68360 */ - -/* - * Some drivers want these entry points - */ -#define enable_irq(x) do { } while (0) -#define disable_irq(x) do { } while (0) -#define disable_irq_nosync(x) disable_irq(x) #define irq_canonicalize(irq) (irq) -#endif /* _M68K_IRQ_H_ */ +#endif /* _M68KNOMMU_IRQ_H_ */ diff --git a/include/asm-m68knommu/irqnode.h b/include/asm-m68knommu/irqnode.h deleted file mode 100644 index 6132a9858b52..000000000000 --- a/include/asm-m68knommu/irqnode.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef _M68K_IRQNODE_H_ -#define _M68K_IRQNODE_H_ - -#include <linux/interrupt.h> - -/* - * This structure is used to chain together the ISRs for a particular - * interrupt source (if it supports chaining). - */ -typedef struct irq_node { - irq_handler_t handler; - unsigned long flags; - void *dev_id; - const char *devname; - struct irq_node *next; -} irq_node_t; - -/* - * This structure has only 4 elements for speed reasons - */ -struct irq_entry { - irq_handler_t handler; - unsigned long flags; - void *dev_id; - const char *devname; -}; - -/* count of spurious interrupts */ -extern volatile unsigned int num_spurious; - -/* - * This function returns a new irq_node_t - */ -extern irq_node_t *new_irq_node(void); - -#endif /* _M68K_IRQNODE_H_ */ diff --git a/include/asm-m68knommu/m68360.h b/include/asm-m68knommu/m68360.h index dd11b070884b..eb7d39ef2855 100644 --- a/include/asm-m68knommu/m68360.h +++ b/include/asm-m68knommu/m68360.h @@ -3,3 +3,11 @@ #include "m68360_quicc.h" #include "m68360_enet.h" +#ifdef CONFIG_M68360 + +#define CPM_INTERRUPT 4 + +/* see MC68360 User's Manual, p. 7-377 */ +#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */ + +#endif /* CONFIG_M68360 */ diff --git a/include/asm-m68knommu/machdep.h b/include/asm-m68knommu/machdep.h index 6ce28f8e0ead..708d7863ba68 100644 --- a/include/asm-m68knommu/machdep.h +++ b/include/asm-m68knommu/machdep.h @@ -1,53 +1,21 @@ #ifndef _M68KNOMMU_MACHDEP_H #define _M68KNOMMU_MACHDEP_H -#include <linux/seq_file.h> #include <linux/interrupt.h> -struct pt_regs; -struct kbd_repeat; -struct mktime; -struct hwclk_time; -struct gendisk; -struct buffer_head; - -extern void (*mach_sched_init) (irqreturn_t (*handler)(int, void *, struct pt_regs *)); -/* machine dependent keyboard functions */ -extern int (*mach_keyb_init) (void); -extern int (*mach_kbdrate) (struct kbd_repeat *); -extern void (*mach_kbd_leds) (unsigned int); -/* machine dependent irq functions */ -extern void (*mach_init_IRQ) (void); -extern irq_handler_t mach_default_handler; -extern int (*mach_request_irq) (unsigned int irq, void (*handler)(int, void *, struct pt_regs *), - unsigned long flags, const char *devname, void *dev_id); -extern void (*mach_free_irq) (unsigned int irq, void *dev_id); -extern void (*mach_get_model) (char *model); -extern int (*mach_get_hardware_list) (char *buffer); -extern int (*mach_get_irq_list) (struct seq_file *p, void *v); -extern void (*mach_process_int) (int irq, struct pt_regs *fp); +extern void (*mach_sched_init) (irq_handler_t handler); /* machine dependent timer functions */ extern unsigned long (*mach_gettimeoffset)(void); extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, int *min, int *sec); -extern int (*mach_hwclk)(int, struct hwclk_time*); extern int (*mach_set_clock_mmss)(unsigned long); + +/* machine dependent power off functions */ extern void (*mach_reset)( void ); extern void (*mach_halt)( void ); extern void (*mach_power_off)( void ); -extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); -extern void (*mach_hd_setup)(char *, int *); -extern long mach_max_dma_address; -extern void (*mach_floppy_eject)(void); -extern void (*mach_heartbeat) (int); -extern void (*mach_l2_flush) (int); -extern int mach_sysrq_key; -extern int mach_sysrq_shift_state; -extern int mach_sysrq_shift_mask; -extern char *mach_sysrq_xlate; extern void config_BSP(char *command, int len); extern void (*mach_tick)(void); -extern void (*mach_trap_init)(void); #endif /* _M68KNOMMU_MACHDEP_H */ diff --git a/include/asm-m68knommu/mcfdma.h b/include/asm-m68knommu/mcfdma.h index ea729e81a6be..705c52c79cd8 100644 --- a/include/asm-m68knommu/mcfdma.h +++ b/include/asm-m68knommu/mcfdma.h @@ -133,7 +133,7 @@ #define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ #define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ -#define MCFDMA_DIR_INV 0x1000 /* Invalid Combination */ +#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ #define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ #define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ #define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ diff --git a/include/asm-m68knommu/pgtable.h b/include/asm-m68knommu/pgtable.h index 9dfbbc24aa71..46251016e821 100644 --- a/include/asm-m68knommu/pgtable.h +++ b/include/asm-m68knommu/pgtable.h @@ -49,7 +49,6 @@ static inline int pte_file(pte_t pte) { return 0; } * These would be in other places but having them here reduces the diffs. */ extern unsigned int kobjsize(const void *objp); -extern int is_in_rom(unsigned long); /* * No page table caches to initialise. @@ -66,4 +65,6 @@ extern int is_in_rom(unsigned long); #define VMALLOC_START 0 #define VMALLOC_END 0xffffffff +#include <asm-generic/pgtable.h> + #endif /* _M68KNOMMU_PGTABLE_H */ diff --git a/include/asm-m68knommu/system.h b/include/asm-m68knommu/system.h index 5e5ed18bb78f..5da43a5d12a3 100644 --- a/include/asm-m68knommu/system.h +++ b/include/asm-m68knommu/system.h @@ -296,7 +296,7 @@ cmpxchg(volatile int *p, int old, int new) ({ \ unsigned char volatile *reset; \ asm("move.w #0x2700, %sr"); \ - reset = ((volatile unsigned short *)(MCF_IPSBAR + 0x110000)); \ + reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \ while(1) \ *reset |= (0x01 << 7);\ }) @@ -318,7 +318,7 @@ cmpxchg(volatile int *p, int old, int new) ({ \ unsigned char volatile *reset; \ asm("move.w #0x2700, %sr"); \ - reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000)); \ + reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \ while(1) \ *reset |= 0x80; \ }) diff --git a/include/asm-m68knommu/thread_info.h b/include/asm-m68knommu/thread_info.h index b8f009edf2b2..95996d978bed 100644 --- a/include/asm-m68knommu/thread_info.h +++ b/include/asm-m68knommu/thread_info.h @@ -83,16 +83,14 @@ static inline struct thread_info *current_thread_info(void) * thread information flag bit numbers */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 5 +#define TIF_MEMDIE 4 /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-m68knommu/timex.h b/include/asm-m68knommu/timex.h index 85069998db52..109050f3fe91 100644 --- a/include/asm-m68knommu/timex.h +++ b/include/asm-m68knommu/timex.h @@ -1 +1,23 @@ -#include <asm-m68k/timex.h> +/* + * linux/include/asm-m68knommu/timex.h + * + * m68knommu architecture timex specifications + */ +#ifndef _ASM_M68KNOMMU_TIMEX_H +#define _ASM_M68KNOMMU_TIMEX_H + +#ifdef CONFIG_COLDFIRE +#include <asm/coldfire.h> +#define CLOCK_TICK_RATE MCF_CLK +#else +#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#endif + +typedef unsigned long cycles_t; + +static inline cycles_t get_cycles(void) +{ + return 0; +} + +#endif diff --git a/include/asm-m68knommu/traps.h b/include/asm-m68knommu/traps.h index f2a81317cc10..d0671e5f8e29 100644 --- a/include/asm-m68knommu/traps.h +++ b/include/asm-m68knommu/traps.h @@ -16,6 +16,10 @@ typedef void (*e_vector)(void); extern e_vector vectors[]; +extern void init_vectors(void); +extern void enable_vector(unsigned int irq); +extern void disable_vector(unsigned int irq); +extern void ack_vector(unsigned int irq); #endif diff --git a/include/asm-m68knommu/uaccess.h b/include/asm-m68knommu/uaccess.h index 62b29b10bc6d..9ed9169a8849 100644 --- a/include/asm-m68knommu/uaccess.h +++ b/include/asm-m68knommu/uaccess.h @@ -15,12 +15,15 @@ #define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) +/* + * It is not enough to just have access_ok check for a real RAM address. + * This would disallow the case of code/ro-data running XIP in flash/rom. + * Ideally we would check the possible flash ranges too, but that is + * currently not so easy. + */ static inline int _access_ok(unsigned long addr, unsigned long size) { - extern unsigned long memory_start, memory_end; - - return (((addr >= memory_start) && (addr+size < memory_end)) || - (is_in_rom(addr) && is_in_rom(addr+size))); + return 1; } /* diff --git a/include/asm-m68knommu/unistd.h b/include/asm-m68knommu/unistd.h index 82e03195f325..eb1b566793fe 100644 --- a/include/asm-m68knommu/unistd.h +++ b/include/asm-m68knommu/unistd.h @@ -314,10 +314,20 @@ #define __NR_tee 308 #define __NR_vmsplice 309 #define __NR_move_pages 310 +#define __NR_sched_setaffinity 311 +#define __NR_sched_getaffinity 312 +#define __NR_kexec_load 313 +#define __NR_getcpu 314 +#define __NR_epoll_pwait 315 +#define __NR_utimensat 316 +#define __NR_signalfd 317 +#define __NR_timerfd 318 +#define __NR_eventfd 319 +#define __NR_fallocate 320 #ifdef __KERNEL__ -#define NR_syscalls 311 +#define NR_syscalls 321 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index ef33c3f13484..bf55a5b34bef 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -38,8 +38,10 @@ struct exec #define STACK_TOP TASK_SIZE #endif #ifdef CONFIG_64BIT -#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) +#define STACK_TOP \ + (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) #endif +#define STACK_TOP_MAX TASK_SIZE #endif diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 0b3ff9c48409..0bb7a93b7a5e 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -123,10 +123,10 @@ /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) /* diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index 838eb3144d81..12e17581b823 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -21,11 +21,11 @@ #ifndef CAT #ifdef __STDC__ -#define __CAT(str1,str2) str1##str2 +#define __CAT(str1, str2) str1##str2 #else -#define __CAT(str1,str2) str1/**/str2 +#define __CAT(str1, str2) str1/**/str2 #endif -#define CAT(str1,str2) __CAT(str1,str2) +#define CAT(str1, str2) __CAT(str1, str2) #endif /* @@ -51,9 +51,9 @@ #define LEAF(symbol) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra + .type symbol, @function; \ + .ent symbol, 0; \ +symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point @@ -61,8 +61,8 @@ symbol: .frame sp,0,ra #define NESTED(symbol, framesize, rpc) \ .globl symbol; \ .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, framesize, rpc /* @@ -70,7 +70,7 @@ symbol: .frame sp, framesize, rpc */ #define END(function) \ .end function; \ - .size function,.-function + .size function, .-function /* * EXPORT - export definition of symbol @@ -84,7 +84,7 @@ symbol: */ #define FEXPORT(symbol) \ .globl symbol; \ - .type symbol,@function; \ + .type symbol, @function; \ symbol: /* @@ -97,7 +97,7 @@ symbol = value #define PANIC(msg) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal panic; \ 9: b 9b; \ .set pop; \ @@ -110,7 +110,7 @@ symbol = value #define PRINT(string) \ .set push; \ .set reorder; \ - PTR_LA a0,8f; \ + PTR_LA a0, 8f; \ jal printk; \ .set pop; \ TEXT(string) @@ -146,19 +146,19 @@ symbol = value #define PREF(hint,addr) \ .set push; \ .set mips4; \ - pref hint,addr; \ + pref hint, addr; \ .set pop #define PREFX(hint,addr) \ .set push; \ .set mips4; \ - prefx hint,addr; \ + prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ -#define PREF(hint,addr) -#define PREFX(hint,addr) +#define PREF(hint, addr) +#define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,43 +166,43 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt,9f; \ - move rd,rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt,9f; \ - move rd,rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd,rs,rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt,9f; \ - move rd,rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd,rs,rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt,9f; \ - move rd,rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd,rs,rt) \ - movn rd,rs,rt -#define MOVZ(rd,rs,rt) \ - movz rd,rs,rt +#define MOVN(rd, rs, rt) \ + movn rd, rs, rt +#define MOVZ(rd, rs, rt) \ + movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ /* @@ -396,6 +396,6 @@ symbol = value #define MTC0 dmtc0 #endif -#define SSNOP sll zero,zero,1 +#define SSNOP sll zero, zero, 1 #endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index c5f20df780e9..7a881755800f 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -56,27 +56,27 @@ * Temporary until all gas have MT ASE support */ .macro DMT reg=0 - .word (0x41600bc1 | (\reg << 16)) + .word 0x41600bc1 | (\reg << 16) .endm .macro EMT reg=0 - .word (0x41600be1 | (\reg << 16)) + .word 0x41600be1 | (\reg << 16) .endm .macro DVPE reg=0 - .word (0x41600001 | (\reg << 16)) + .word 0x41600001 | (\reg << 16) .endm .macro EVPE reg=0 - .word (0x41600021 | (\reg << 16)) + .word 0x41600021 | (\reg << 16) .endm .macro MFTR rt=0, rd=0, u=0, sel=0 - .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm .macro MTTR rt=0, rd=0, u=0, sel=0 - .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) + .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm #endif /* _ASM_ASMMACRO_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 1b60624dab7e..a798d6299a79 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -39,7 +39,7 @@ typedef struct { volatile int counter; } atomic_t; * * Atomically sets the value of @v to @i. */ -#define atomic_set(v,i) ((v)->counter = (i)) +#define atomic_set(v, i) ((v)->counter = (i)) /* * atomic_add - add integer to atomic variable @@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -335,8 +335,8 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) } #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) +#define atomic_dec_return(v) atomic_sub_return(1, (v)) +#define atomic_inc_return(v) atomic_add_return(1, (v)) /* * atomic_sub_and_test - subtract value from variable and test result @@ -347,7 +347,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * true if the result is zero, or false for all * other cases. */ -#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) /* * atomic_inc_and_test - increment and test @@ -381,7 +381,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically increments @v by 1. */ -#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_inc(v) atomic_add(1, (v)) /* * atomic_dec - decrement and test @@ -389,7 +389,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * * Atomically decrements @v by 1. */ -#define atomic_dec(v) atomic_sub(1,(v)) +#define atomic_dec(v) atomic_sub(1, (v)) /* * atomic_add_negative - add and test if negative @@ -400,7 +400,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) +#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0) #ifdef CONFIG_64BIT @@ -420,7 +420,7 @@ typedef struct { volatile long counter; } atomic64_t; * @v: pointer of type atomic64_t * @i: required value */ -#define atomic64_set(v,i) ((v)->counter = (i)) +#define atomic64_set(v, i) ((v)->counter = (i)) /* * atomic64_add - add integer to atomic variable @@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -718,8 +718,8 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) -#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) -#define atomic64_inc_return(v) atomic64_add_return(1,(v)) +#define atomic64_dec_return(v) atomic64_sub_return(1, (v)) +#define atomic64_inc_return(v) atomic64_add_return(1, (v)) /* * atomic64_sub_and_test - subtract value from variable and test result @@ -730,7 +730,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * true if the result is zero, or false for all * other cases. */ -#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) +#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0) /* * atomic64_inc_and_test - increment and test @@ -764,7 +764,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically increments @v by 1. */ -#define atomic64_inc(v) atomic64_add(1,(v)) +#define atomic64_inc(v) atomic64_add(1, (v)) /* * atomic64_dec - decrement and test @@ -772,7 +772,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * * Atomically decrements @v by 1. */ -#define atomic64_dec(v) atomic64_sub(1,(v)) +#define atomic64_dec(v) atomic64_sub(1, (v)) /* * atomic64_add_negative - add and test if negative @@ -783,7 +783,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) +#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0) #endif /* CONFIG_64BIT */ @@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * atomic*_return operations are serializing but not the non-*_return * versions. */ -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() +#define smp_mb__before_atomic_dec() smp_llsc_mb() +#define smp_mb__after_atomic_dec() smp_llsc_mb() +#define smp_mb__before_atomic_inc() smp_llsc_mb() +#define smp_mb__after_atomic_inc() smp_llsc_mb() #include <asm-generic/atomic.h> + #endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index ed82631b0017..9d8cfbb5e796 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h @@ -121,6 +121,11 @@ #else #define __WEAK_ORDERING_MB " \n" #endif +#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) +#define __WEAK_LLSC_MB " sync \n" +#else +#define __WEAK_LLSC_MB " \n" +#endif #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") @@ -129,4 +134,8 @@ #define set_mb(var, value) \ do { var = value; smp_mb(); } while (0) +#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") + #endif /* __ASM_BARRIER_H */ diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h index 3646a3f2ed38..0ba9d6ef76a7 100644 --- a/include/asm-mips/bcache.h +++ b/include/asm-mips/bcache.h @@ -21,7 +21,6 @@ struct bcache_ops { }; extern void indy_sc_init(void); -extern void sni_pcimt_sc_init(void); #ifdef CONFIG_BOARD_SCACHE diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d9e81af53f78..899357a72ac4 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -19,14 +19,14 @@ #include <asm/sgidefs.h> #include <asm/war.h> -#if (_MIPS_SZLONG == 32) +#if _MIPS_SZLONG == 32 #define SZLONG_LOG 5 #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " #define __INS "ins " #define __EXT "ext " -#elif (_MIPS_SZLONG == 64) +#elif _MIPS_SZLONG == 64 #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " @@ -38,8 +38,8 @@ /* * clear_bit() doesn't provide any barrier for the compiler. */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#define smp_mb__before_clear_bit() smp_llsc_mb() +#define smp_mb__after_clear_bit() smp_llsc_mb() /* * set_bit - Atomically set a bit in memory @@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x) int lz; if (sizeof(x) == 4) { - __asm__ ( + __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" @@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x) BUG_ON(sizeof(x) != 8); - __asm__ ( + __asm__( " .set push \n" " .set mips64 \n" " dclz %0, %1 \n" @@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word) */ static inline int fls(int word) { - __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); + __asm__("clz %0, %1" : "=r" (word) : "r" (word)); return 32 - word; } @@ -516,7 +516,7 @@ static inline int fls(int word) #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) static inline int fls64(__u64 word) { - __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); return 64 - word; } diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 087126a5faf9..b2dd9b33de8f 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -15,21 +15,19 @@ #include <asm/setup.h> /* - * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining - * MACH_ values equivalent to product IDs. As such the numbers do not - * necessarily reflect technical relations or similarities between systems. + * The MACH_ IDs are sort of equivalent to PCI product IDs. As such the + * numbers do not necessarily reflect technical relations or similarities + * between systems. */ /* * Valid machtype values for group unknown */ -#define MACH_GROUP_UNKNOWN 0 /* whatever... */ #define MACH_UNKNOWN 0 /* whatever... */ /* * Valid machtype values for group JAZZ */ -#define MACH_GROUP_JAZZ 1 /* Jazz */ #define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ #define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ #define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ @@ -37,7 +35,6 @@ /* * Valid machtype for group DEC */ -#define MACH_GROUP_DEC 2 /* Digital Equipment */ #define MACH_DSUNKNOWN 0 #define MACH_DS23100 1 /* DECstation 2100 or 3100 */ #define MACH_DS5100 2 /* DECsystem 5100 */ @@ -53,26 +50,22 @@ /* * Valid machtype for group ARC */ -#define MACH_GROUP_ARC 3 /* Deskstation */ #define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ #define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ /* * Valid machtype for group SNI_RM */ -#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ #define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ /* * Valid machtype for group ACN */ -#define MACH_GROUP_ACN 5 #define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ /* * Valid machtype for group SGI */ -#define MACH_GROUP_SGI 6 /* Silicon Graphics */ #define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ #define MACH_SGI_IP28 2 /* Indigo2 Impact */ @@ -82,36 +75,22 @@ /* * Valid machtype for group COBALT */ -#define MACH_GROUP_COBALT 7 /* Cobalt servers */ #define MACH_COBALT_27 0 /* Proto "27" hardware */ /* - * Valid machtype for group NEC DDB - */ -#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ -#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ -#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ -#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ -#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ - -/* * Valid machtype for group BAGET */ -#define MACH_GROUP_BAGET 9 /* Baget */ #define MACH_BAGET201 0 /* BT23-201 */ #define MACH_BAGET202 1 /* BT23-202 */ /* * Cosine boards. */ -#define MACH_GROUP_COSINE 10 /* CoSine Orion */ #define MACH_COSINE_ORION 0 /* * Valid machtype for group MOMENCO */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ #define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ @@ -121,7 +100,6 @@ /* * Valid machtype for group PHILIPS */ -#define MACH_GROUP_PHILIPS 14 #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ #define MACH_PHILIPS_JBS 2 /* JBS */ @@ -130,13 +108,11 @@ /* * Valid machtype for group SIBYTE */ -#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ #define MACH_SWARM 0 /* * Valid machtypes for group Toshiba */ -#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ #define MACH_PALLAS 0 #define MACH_TOPAS 1 #define MACH_JMR 2 @@ -145,13 +121,9 @@ #define MACH_TOSHIBA_RBTX4937 5 #define MACH_TOSHIBA_RBTX4938 6 -#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ - "RBTX4927", "RBTX4937" } - /* * Valid machtype for group Alchemy */ -#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */ #define MACH_PB1000 0 /* Au1000-based eval board */ #define MACH_PB1100 1 /* Au1100-based eval board */ #define MACH_PB1500 2 /* Au1500-based eval board */ @@ -173,7 +145,6 @@ * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by * technical properties, so no new additions to this group. */ -#define MACH_GROUP_NEC_VR41XX 19 #define MACH_NEC_OSPREY 0 /* Osprey eval board */ #define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ #define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ @@ -184,32 +155,33 @@ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ #define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ -#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ #define MACH_HP_LASERJET 1 /* + * Valid machtype for group LASAT + */ +#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ + +/* * Valid machtype for group TITAN */ -#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ #define MACH_TITAN_EXCITE 2 /* Basler eXcite */ /* * Valid machtype for group NEC EMMA2RH */ -#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ /* * Valid machtype for group LEMOTE */ -#define MACH_GROUP_LEMOTE 27 #define MACH_LEMOTE_FULONG 0 /* * Valid machtype for group PMC-MSP */ -#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ #define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ #define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ #define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ @@ -218,15 +190,19 @@ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ -#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ #define MACH_WRPPMC 1 +/* + * Valid machtype for group Broadcom + */ +#define MACH_GROUP_BRCM 23 /* Broadcom */ +#define MACH_BCM47XX 1 /* Broadcom BCM47XX */ + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); extern unsigned long mips_machtype; -extern unsigned long mips_machgroup; #define BOOT_MEM_MAP_MAX 32 #define BOOT_MEM_RAM 1 diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index eee83cbdf2b0..fe7dc2d59b69 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) #endif /* __GNUC__ */ -#if defined (__MIPSEB__) +#if defined(__MIPSEB__) # include <linux/byteorder/big_endian.h> -#elif defined (__MIPSEL__) +#elif defined(__MIPSEL__) # include <linux/byteorder/little_endian.h> #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h new file mode 100644 index 000000000000..a5ec0e5dc5b8 --- /dev/null +++ b/include/asm-mips/cmpxchg.h @@ -0,0 +1,107 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_CMPXCHG_H +#define __ASM_CMPXCHG_H + +#include <linux/irqflags.h> + +#define __HAVE_ARCH_CMPXCHG 1 + +#define __cmpxchg_asm(ld, st, m, old, new) \ +({ \ + __typeof(*(m)) __ret; \ + \ + if (cpu_has_llsc && R10000_LLSC_WAR) { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips3 \n" \ + "1: " ld " %0, %2 # __cmpxchg_asm \n" \ + " bne %0, %z3, 2f \n" \ + " .set mips0 \n" \ + " move $1, %z4 \n" \ + " .set mips3 \n" \ + " " st " $1, %1 \n" \ + " beqzl $1, 1b \n" \ + "2: \n" \ + " .set pop \n" \ + : "=&r" (__ret), "=R" (*m) \ + : "R" (*m), "Jr" (old), "Jr" (new) \ + : "memory"); \ + } else if (cpu_has_llsc) { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips3 \n" \ + "1: " ld " %0, %2 # __cmpxchg_asm \n" \ + " bne %0, %z3, 2f \n" \ + " .set mips0 \n" \ + " move $1, %z4 \n" \ + " .set mips3 \n" \ + " " st " $1, %1 \n" \ + " beqz $1, 3f \n" \ + "2: \n" \ + " .subsection 2 \n" \ + "3: b 1b \n" \ + " .previous \n" \ + " .set pop \n" \ + : "=&r" (__ret), "=R" (*m) \ + : "R" (*m), "Jr" (old), "Jr" (new) \ + : "memory"); \ + } else { \ + unsigned long __flags; \ + \ + raw_local_irq_save(__flags); \ + __ret = *m; \ + if (__ret == old) \ + *m = new; \ + raw_local_irq_restore(__flags); \ + } \ + \ + __ret; \ +}) + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern void __cmpxchg_called_with_bad_pointer(void); + +#define __cmpxchg(ptr, old, new, barrier) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) __new = (new); \ + __typeof__(*(ptr)) __res = 0; \ + \ + barrier; \ + \ + switch (sizeof(*(__ptr))) { \ + case 4: \ + __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \ + break; \ + case 8: \ + if (sizeof(long) == 8) { \ + __res = __cmpxchg_asm("lld", "scd", __ptr, \ + __old, __new); \ + break; \ + } \ + default: \ + __cmpxchg_called_with_bad_pointer(); \ + break; \ + } \ + \ + barrier; \ + \ + __res; \ +}) + +#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) +#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) + +#endif /* __ASM_CMPXCHG_H */ diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h index 169ae26105e9..aa6b876bbd78 100644 --- a/include/asm-mips/compiler.h +++ b/include/asm-mips/compiler.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2004, 2007 Maciej W. Rozycki * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -9,8 +9,10 @@ #define _ASM_COMPILER_H #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) +#define GCC_IMM_ASM "n" #define GCC_REG_ACCUM "$0" #else +#define GCC_IMM_ASM "rn" #define GCC_REG_ACCUM "accum" #endif diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index d95a83e3e1d7..f6bd308f047f 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -9,11 +9,14 @@ #ifndef __ASM_CPU_FEATURES_H #define __ASM_CPU_FEATURES_H - #include <asm/cpu.h> #include <asm/cpu-info.h> #include <cpu-feature-overrides.h> +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. @@ -35,9 +38,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_sb1_cache -#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 22fe8453fcc7..94f1c8172360 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -14,10 +14,6 @@ #include <asm/cache.h> -#ifdef CONFIG_SGI_IP27 -#include <asm/sn/types.h> -#endif - /* * Descriptor for a cache */ @@ -43,20 +39,6 @@ struct cache_desc { struct cpuinfo_mips { unsigned long udelay_val; unsigned long asid_cache; -#if defined(CONFIG_SGI_IP27) -// cpuid_t p_cpuid; /* PROM assigned cpuid */ - cnodeid_t p_nodeid; /* my node ID in compact-id-space */ - nasid_t p_nasid; /* my node ID in numa-as-id-space */ - unsigned char p_slice; /* Physical position on node board */ -#endif -#if 0 - unsigned long loops_per_sec; - unsigned long ipi_count; - unsigned long irq_attempt[NR_IRQS]; - unsigned long smp_local_irq_count; - unsigned long prof_multiplier; - unsigned long prof_counter; -#endif /* * Capability and feature descriptor structure for MIPS CPU @@ -92,4 +74,7 @@ extern struct cpuinfo_mips cpu_data[]; extern void cpu_probe(void); extern void cpu_report(void); +extern const char *__cpu_name[]; +#define cpu_name_string() __cpu_name[smp_processor_id()] + #endif /* __ASM_CPU_INFO_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 3857358fb6de..54fc18a4e5a8 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -106,6 +106,13 @@ #define PRID_IMP_SR71000 0x0400 /* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BCM4710 0x4000 +#define PRID_IMP_BCM3302 0x9000 + +/* * Definitions for 7:0 on legacy processors */ @@ -150,75 +157,55 @@ #define FPIR_IMP_NONE 0x0000 -#define CPU_UNKNOWN 0 -#define CPU_R2000 1 -#define CPU_R3000 2 -#define CPU_R3000A 3 -#define CPU_R3041 4 -#define CPU_R3051 5 -#define CPU_R3052 6 -#define CPU_R3081 7 -#define CPU_R3081E 8 -#define CPU_R4000PC 9 -#define CPU_R4000SC 10 -#define CPU_R4000MC 11 -#define CPU_R4200 12 -#define CPU_R4400PC 13 -#define CPU_R4400SC 14 -#define CPU_R4400MC 15 -#define CPU_R4600 16 -#define CPU_R6000 17 -#define CPU_R6000A 18 -#define CPU_R8000 19 -#define CPU_R10000 20 -#define CPU_R12000 21 -#define CPU_R4300 22 -#define CPU_R4650 23 -#define CPU_R4700 24 -#define CPU_R5000 25 -#define CPU_R5000A 26 -#define CPU_R4640 27 -#define CPU_NEVADA 28 -#define CPU_RM7000 29 -#define CPU_R5432 30 -#define CPU_4KC 31 -#define CPU_5KC 32 -#define CPU_R4310 33 -#define CPU_SB1 34 -#define CPU_TX3912 35 -#define CPU_TX3922 36 -#define CPU_TX3927 37 -#define CPU_AU1000 38 -#define CPU_4KEC 39 -#define CPU_4KSC 40 -#define CPU_VR41XX 41 -#define CPU_R5500 42 -#define CPU_TX49XX 43 -#define CPU_AU1500 44 -#define CPU_20KC 45 -#define CPU_VR4111 46 -#define CPU_VR4121 47 -#define CPU_VR4122 48 -#define CPU_VR4131 49 -#define CPU_VR4181 50 -#define CPU_VR4181A 51 -#define CPU_AU1100 52 -#define CPU_SR71000 53 -#define CPU_RM9000 54 -#define CPU_25KF 55 -#define CPU_VR4133 56 -#define CPU_AU1550 57 -#define CPU_24K 58 -#define CPU_AU1200 59 -#define CPU_34K 60 -#define CPU_PR4450 61 -#define CPU_SB1A 62 -#define CPU_74K 63 -#define CPU_R14000 64 -#define CPU_LOONGSON1 65 -#define CPU_LOONGSON2 66 - -#define CPU_LAST 66 +enum cpu_type_enum { + CPU_UNKNOWN, + + /* + * R2000 class processors + */ + CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, + CPU_R3081, CPU_R3081E, + + /* + * R6000 class processors + */ + CPU_R6000, CPU_R6000A, + + /* + * R4000 class processors + */ + CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, + CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, + CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, + CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, + CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, + CPU_SR71000, CPU_RM9000, CPU_TX49XX, + + /* + * R8000 class processors + */ + CPU_R8000, + + /* + * TX3900 class processors + */ + CPU_TX3912, CPU_TX3922, CPU_TX3927, + + /* + * MIPS32 class processors + */ + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, + CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, + CPU_BCM3302, CPU_BCM4710, + + /* + * MIPS64 class processors + */ + CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + + CPU_LAST +}; + /* * ISA Level encodings @@ -247,24 +234,23 @@ #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ -#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ -#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ -#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ -#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ -#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ -#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ -#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ -#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h deleted file mode 100644 index 6cf177caf6d5..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ /dev/null @@ -1,342 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * include/asm-mips/ddb5xxx/ddb5477.h - * DDB 5477 specific definitions and macros. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - *********************************************************************** - */ - -#ifndef __ASM_DDB5XXX_DDB5477_H -#define __ASM_DDB5XXX_DDB5477_H - -#include <irq.h> - -/* - * This contains macros that are specific to DDB5477 or renamed from - * DDB5476. - */ - -/* - * renamed PADRs - */ -#define DDB_LCS0 DDB_DCS2 -#define DDB_LCS1 DDB_DCS3 -#define DDB_LCS2 DDB_DCS4 -#define DDB_VRC5477 DDB_INTCS - -/* - * New CPU interface registers - */ -#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ -#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */ -#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */ -#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */ - -#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */ -#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */ -#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */ -#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */ -#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */ -#define DDB_NMISTAT 0x0450 /* NMI Status [R] */ - -#define DDB_INTCLR32 0x0468 /* Interrupt Clear */ - -#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ -#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ - -#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */ -#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */ -#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */ - - -/* - * Timer registers - */ -#define DDB_REFCTRL_L DDB_T0CTRL -#define DDB_REFCTRL_H (DDB_T0CTRL+4) -#define DDB_REFCNTR DDB_T0CNTR -#define DDB_SPT0CTRL_L DDB_T1CTRL -#define DDB_SPT0CTRL_H (DDB_T1CTRL+4) -#define DDB_SPT1CTRL_L DDB_T2CTRL -#define DDB_SPT1CTRL_H (DDB_T2CTRL+4) -#define DDB_SPT1CNTR DDB_T1CTRL -#define DDB_WDTCTRL_L DDB_T3CTRL -#define DDB_WDTCTRL_H (DDB_T3CTRL+4) -#define DDB_WDTCNTR DDB_T3CNTR - -/* - * DMA registers are moved. We don't care about it for now. TODO. - */ - -/* - * BARs for ext PCI (PCI0) - */ -#undef DDB_BARC -#undef DDB_BARB - -#define DDB_BARC0 0x0210 /* PCI0 Control */ -#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */ -#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */ -#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */ -#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */ -#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */ -#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */ -#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */ -#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */ -#define DDB_BARB0 0x0280 /* PCI0 BOOT */ -#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */ -#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */ - -/* - * BARs for IOPIC (PCI1) - */ -#define DDB_BARC1 0x0610 /* PCI1 Control */ -#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */ -#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */ -#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */ -#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */ -#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */ -#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */ -#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */ -#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */ -#define DDB_BARB1 0x0680 /* PCI1 BOOT */ -#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */ -#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */ - -/* - * Other registers for ext PCI (PCI0) - */ -#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */ -#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */ - -#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */ -#define DDB_PCIERR0 0x02b8 /* PCI0 Error */ - -#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ -#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */ -#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */ -#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */ - -/* - * Other registers for IOPCI (PCI1) - */ -#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */ -#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */ - -#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */ -#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */ - -#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */ -#define DDB_PCIERR1 0x06b8 /* PCI1 Error */ - -#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */ -#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */ -#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */ -#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */ - -/* - * Local Bus - */ -#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */ -#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */ -#undef DDB_LCST2 -#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */ -#undef DDB_LCST3 -#undef DDB_LCST4 -#undef DDB_LCST5 -#undef DDB_LCST6 -#undef DDB_LCST7 -#undef DDB_LCST8 -#define DDB_ERRADR 0x0150 /* Error Address Register */ -#define DDB_ERRCS 0x0160 -#define DDB_BTM 0x0170 /* Boot Time Mode value */ - -/* - * MISC registers - */ -#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */ -#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */ - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ - -/* the actual ram size is detected at run-time */ -#define DDB_SDRAM_BASE 0x00000000 -#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */ - -#define DDB_PCI0_MEM_BASE 0x08000000 -#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI1_MEM_BASE 0x10000000 -#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI0_CONFIG_BASE 0x18000000 -#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI1_CONFIG_BASE 0x19000000 -#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */ -#define DDB_PCI0_IO_BASE 0x1a000000 -#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */ -#define DDB_PCI1_IO_BASE 0x1b000000 -#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS0_BASE 0x1c000000 /* flash memory */ -#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS1_BASE 0x1d000000 /* misc */ -#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */ -#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */ - -#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */ -#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */ - -#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ -#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ - -#define DDB_LED DDB_LCS1_BASE + 0x10000 - - -/* - * DDB5477 specific functions - */ -#ifndef __ASSEMBLY__ -extern void ddb5477_irq_setup(void); - -/* route irq to cpu int pin */ -extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip); - -/* low-level routine for enabling vrc5477 irq, bypassing high-level */ -extern void ll_vrc5477_irq_enable(int vrc5477_irq); -extern void ll_vrc5477_irq_disable(int vrc5477_irq); -#endif /* !__ASSEMBLY__ */ - -/* PCI intr ack share PCIW0 with PCI IO */ -#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE - -/* - * Interrupt mapping - * - * We have three interrupt controllers: - * - * . CPU itself - 8 sources - * . i8259 - 16 sources - * . vrc5477 - 32 sources - * - * They connected as follows: - * all vrc5477 interrupts are routed to cpu IP2 (by software setting) - * all i8359 are routed to INTC in vrc5477 (by hardware connection) - * - * All VRC5477 PCI interrupts are level-triggered (no ack needed). - * All PCI irq but INTC are active low. - */ - -/* - * irq number block assignment - */ - -#define NUM_CPU_IRQ 8 -#define NUM_VRC5477_IRQ 32 - -#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE -#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) - -/* - * vrc5477 irq defs - */ - -#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */ -#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */ -#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */ -#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */ -#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */ -#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */ -#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */ -#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */ -#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */ -#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */ -#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */ -#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */ -#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */ -#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */ -#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */ -#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ -#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ -#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ -#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ -#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ -#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */ -#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */ -#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */ -#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE) - -/* - * i2859 irq assignment - */ -#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) -#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) -#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ -#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) -#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ -#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ -#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) -#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ -#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ - - -/* - * misc - */ -#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE) -#define CPU_VRC5477_CASCADE 2 - -/* - * debug routines - */ -#ifndef __ASSEMBLY__ -#if defined(CONFIG_RUNTIME_DEBUG) -extern void vrc5477_show_pdar_regs(void); -extern void vrc5477_show_pci_regs(void); -extern void vrc5477_show_bar_regs(void); -extern void vrc5477_show_int_regs(void); -extern void vrc5477_show_all_regs(void); -#endif - -/* - * RAM size - */ -extern int board_ram_size; -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_DDB5XXX_DDB5477_H */ diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h deleted file mode 100644 index e97fcc8d548b..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * include/asm-mips/ddb5xxx/ddb5xxx.h - * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __ASM_DDB5XXX_DDB5XXX_H -#define __ASM_DDB5XXX_DDB5XXX_H - -#include <linux/types.h> - -/* - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - * - * [jsun] It is modified so that this file only contains the macros - * that are true for all DDB 5xxx boards. The modification is based on - * - * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke) - * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000 - * - */ - - -#define DDB_BASE 0xbfa00000 -#define DDB_SIZE 0x00200000 /* 2 MB */ - - -/* - * Physical Device Address Registers (PDARs) - */ - -#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ -/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */ - -/* - * CPU Interface Registers - */ -#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - -/* - * Memory-Interface Registers - */ -#define DDB_MEMCTRL 0x00C0 /* Memory Control */ -#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - -/* - * PCI-Bus Registers - */ -#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */ - - -/* - * Local-Bus Registers - */ -#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - -/* - * DMA Registers - */ -#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - -/* - * Timer Registers - */ -#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - -/* - * PCI Configuration Space Registers - */ -#define DDB_PCI_BASE 0x0200 - -#define DDB_VID 0x0200 /* PCI Vendor ID [R] */ -#define DDB_DID 0x0202 /* PCI Device ID [R] */ -#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */ -#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */ -#define DDB_REVID 0x0208 /* PCI Revision ID [R] */ -#define DDB_CLASS 0x0209 /* PCI Class Code [R] */ -#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define DDB_HTYPE 0x020E /* PCI Header Type [R] */ -#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */ -#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - -/* - * Nile 4 Register Access - */ - -static inline void ddb_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void ddb_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u32 ddb_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u16 ddb_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u8 ddb_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - - -/* - * Physical Device Address Registers - */ - -extern u32 -ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible); -extern void -ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int pci_visible); - -/* - * PCI Master Registers - */ - -#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define DDB_PCICMD_IO 1 /* PCI I/O Space */ -#define DDB_PCICMD_MEM 3 /* PCI Memory Space */ -#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */ - -/* - * additional options for pci init reg (no shifting needed) - */ -#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */ -#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */ - - -extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options); - -/* - * we need to reset pci bus when we start up and shutdown - */ -extern void ddb_pci_reset_bus(void); - - -/* - * include the board dependent part - */ -#if defined(CONFIG_DDB5477) -#include <asm/ddb5xxx/ddb5477.h> -#else -#error "Unknown DDB board!" -#endif - -#endif /* __ASM_DDB5XXX_DDB5XXX_H */ diff --git a/include/asm-mips/dec/serial.h b/include/asm-mips/dec/serial.h deleted file mode 100644 index acad75890a05..000000000000 --- a/include/asm-mips/dec/serial.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * include/asm-mips/dec/serial.h - * - * Definitions common to all DECstation serial devices. - * - * Copyright (C) 2004 Maciej W. Rozycki - * - * Based on bits extracted from drivers/tc/zs.h for which - * the following copyrights apply: - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) - * Copyright (C) Harald Koerfgen - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_SERIAL_H -#define __ASM_MIPS_DEC_SERIAL_H - -struct dec_serial_hook { - int (*init_channel)(void *handle); - void (*init_info)(void *handle); - void (*rx_char)(unsigned char ch, unsigned char fl); - int (*poll_rx_char)(void *handle); - int (*poll_tx_char)(void *handle, unsigned char ch); - unsigned int cflags; -}; - -extern int register_dec_serial_hook(unsigned int channel, - struct dec_serial_hook *hook); -extern int unregister_dec_serial_hook(unsigned int channel); - -#endif /* __ASM_MIPS_DEC_SERIAL_H */ diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index 223d156efb9f..fab32131e9b4 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -81,7 +81,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val -#define udelay(usecs) __udelay((usecs),__udelay_val) +#define udelay(usecs) __udelay((usecs), __udelay_val) /* make sure "usecs *= ..." in udelay do not overflow. */ #if HZ >= 1000 diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h deleted file mode 100644 index 1ff8b73f7a6a..000000000000 --- a/include/asm-mips/ds1216.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _DS1216_H -#define _DS1216_H - -extern volatile unsigned char *ds1216_base; -unsigned long ds1216_get_cmos_time(void); -int ds1216_set_rtc_mmss(unsigned long nowtime); - -#define DS1216_SEC_BYTE 1 -#define DS1216_MIN_BYTE 2 -#define DS1216_HOUR_BYTE 3 -#define DS1216_HOUR_MASK (0x1f) -#define DS1216_AMPM_MASK (1<<5) -#define DS1216_1224_MASK (1<<7) -#define DS1216_DAY_BYTE 4 -#define DS1216_DAY_MASK (0x7) -#define DS1216_DATE_BYTE 5 -#define DS1216_DATE_MASK (0x3f) -#define DS1216_MONTH_BYTE 6 -#define DS1216_MONTH_MASK (0x1f) -#define DS1216_YEAR_BYTE 7 - -#define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE]) -#define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE]) -#define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK) -#define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK) -#define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK) -#define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK) -#define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK) -#define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE]) - -#endif diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h new file mode 100644 index 000000000000..4da0c1fe30d9 --- /dev/null +++ b/include/asm-mips/edac.h @@ -0,0 +1,34 @@ +#ifndef ASM_EDAC_H +#define ASM_EDAC_H + +/* ECC atomic, DMA, SMP and interrupt safe scrub function */ + +static inline void atomic_scrub(void *va, u32 size) +{ + unsigned long *virt_addr = va; + unsigned long temp; + u32 i; + + for (i = 0; i < size / sizeof(unsigned long); i++) { + /* + * Very carefully read and write to memory atomically + * so we are interrupt, DMA and SMP safe. + * + * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr)); + */ + + __asm__ __volatile__ ( + " .set mips2 \n" + "1: ll %0, %1 # atomic_scrub \n" + " addu %0, $0 \n" + " sc %0, %1 \n" + " beqz %0, 1b \n" + " .set mips0 \n" + : "=&r" (temp), "=m" (*virt_addr) + : "m" (*virt_addr)); + + virt_addr++; + } +} + +#endif diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index ebd6bfb19d66..766f91ad5cd3 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -265,7 +265,7 @@ do { \ #ifdef CONFIG_MIPS32_N32 #define __SET_PERSONALITY32_N32() \ do { \ - current->thread.mflags |= MF_N32; \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_n32; \ } while (0) #else @@ -276,7 +276,8 @@ do { \ #ifdef CONFIG_MIPS32_O32 #define __SET_PERSONALITY32_O32() \ do { \ - current->thread.mflags |= MF_O32; \ + set_thread_flag(TIF_32BIT_REGS); \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_32; \ } while (0) #else @@ -299,13 +300,13 @@ do { \ #define SET_PERSONALITY(ex, ibcs2) \ do { \ - current->thread.mflags &= ~MF_ABI_MASK; \ + clear_thread_flag(TIF_32BIT_REGS); \ + clear_thread_flag(TIF_32BIT_ADDR); \ + \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ __SET_PERSONALITY32(ex); \ - else { \ - current->thread.mflags |= MF_N64; \ + else \ current->thread.abi = &mips_abi; \ - } \ \ if (ibcs2) \ set_personality(PER_SVR4); \ @@ -318,7 +319,7 @@ do { \ struct task_struct; extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); -extern int dump_task_regs (struct task_struct *, elf_gregset_t *); +extern int dump_task_regs(struct task_struct *, elf_gregset_t *); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_REGS(elf_regs, regs) \ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h index 00a50ec1c19f..2a52333a062d 100644 --- a/include/asm-mips/fcntl.h +++ b/include/asm-mips/fcntl.h @@ -13,6 +13,7 @@ #define O_SYNC 0x0010 #define O_NONBLOCK 0x0080 #define O_CREAT 0x0100 /* not fcntl */ +#define O_TRUNC 0x0200 /* not fcntl */ #define O_EXCL 0x0400 /* not fcntl */ #define O_NOCTTY 0x0800 /* not fcntl */ #define FASYNC 0x1000 /* fcntl, for BSD compatibility */ diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h index 02c8a13fc894..f27b96cfac2e 100644 --- a/include/asm-mips/fixmap.h +++ b/include/asm-mips/fixmap.h @@ -60,8 +60,8 @@ enum fixed_addresses { __end_of_fixed_addresses }; -extern void __set_fixmap (enum fixed_addresses idx, - unsigned long phys, pgprot_t flags); +extern void __set_fixmap(enum fixed_addresses idx, + unsigned long phys, pgprot_t flags); #define set_fixmap(idx, phys) \ __set_fixmap(idx, phys, PAGE_KERNEL) diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h index aa1ef8b352cc..a62d0990c8ae 100644 --- a/include/asm-mips/floppy.h +++ b/include/asm-mips/floppy.h @@ -10,9 +10,11 @@ #ifndef _ASM_FLOPPY_H #define _ASM_FLOPPY_H +#include <linux/dma-mapping.h> + static inline void fd_cacheflush(char * addr, long size) { - dma_cache_wback_inv((unsigned long)addr,size); + dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL); } #define MAX_BUFFER_SECTORS 24 @@ -47,7 +49,7 @@ static inline void fd_cacheflush(char * addr, long size) * Actually this needs to be a bit more complicated since the so much different * hardware available with MIPS CPUs ... */ -#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) +#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) #define EXTRA_FLOPPY_PARAMS diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index 47e5679c2353..3e7e30d4f418 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -29,7 +29,7 @@ " .set mips3 \n" \ "2: sc $1, %2 \n" \ " beqzl $1, 1b \n" \ - __WEAK_ORDERING_MB \ + __WEAK_LLSC_MB \ "3: \n" \ " .set pop \n" \ " .set mips0 \n" \ @@ -55,7 +55,7 @@ " .set mips3 \n" \ "2: sc $1, %2 \n" \ " beqz $1, 1b \n" \ - __WEAK_ORDERING_MB \ + __WEAK_LLSC_MB \ "3: \n" \ " .set pop \n" \ " .set mips0 \n" \ @@ -75,7 +75,7 @@ } static inline int -futex_atomic_op_inuser (int encoded_op, int __user *uaddr) +futex_atomic_op_inuser(int encoded_op, int __user *uaddr) { int op = (encoded_op >> 28) & 7; int cmp = (encoded_op >> 24) & 15; @@ -152,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set mips3 \n" "2: sc $1, %1 \n" " beqzl $1, 1b \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" @@ -179,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set mips3 \n" "2: sc $1, %1 \n" " beqz $1, 1b \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" diff --git a/include/asm-mips/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h index ee792bf04002..e6ff4add04e2 100644 --- a/include/asm-mips/arc/hinv.h +++ b/include/asm-mips/fw/arc/hinv.h @@ -4,7 +4,8 @@ #ifndef _ASM_ARC_HINV_H #define _ASM_ARC_HINV_H -#include <asm/arc/types.h> +#include <asm/sgidefs.h> +#include <asm/fw/arc/types.h> /* configuration query defines */ typedef enum configclass { @@ -110,7 +111,7 @@ union key_u { ULONG FullKey; }; -#if _MIPS_SIM == _ABI64 +#if _MIPS_SIM == _MIPS_SIM_ABI64 #define SGI_ARCS_VERS 64 /* sgi 64-bit version */ #define SGI_ARCS_REV 0 /* rev .00 */ #else diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/fw/arc/types.h index b9adcd6f0860..b9adcd6f0860 100644 --- a/include/asm-mips/arc/types.h +++ b/include/asm-mips/fw/arc/types.h diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h new file mode 100644 index 000000000000..41cf050b6810 --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_api.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api.h + * + * This file contains declarations for doing callbacks to + * cfe from an application. It should be the only header + * needed by the application to use this library + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_H +#define CFE_API_H + +/* + * Apply customizations here for different OSes. These need to: + * * typedef uint64_t, int64_t, intptr_t, uintptr_t. + * * define cfe_strlen() if use of an existing function is desired. + * * define CFE_API_IMPL_NAMESPACE if API functions are to use + * names in the implementation namespace. + * Also, optionally, if the build environment does not do so automatically, + * CFE_API_* can be defined here as desired. + */ +/* Begin customization. */ +#include <linux/types.h> +#include <linux/string.h> + +typedef long intptr_t; + +#define cfe_strlen strlen + +#define CFE_API_ALL +#define CFE_API_STRLEN_CUSTOM +/* End customization. */ + + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +/* Seal indicating CFE's presence, passed to user program. */ +#define CFE_EPTSEAL 0x43464531 + +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ +#define CFE_MI_AVAILABLE 1 /* memory is available */ + +#define CFE_FLG_WARMSTART 0x00000001 +#define CFE_FLG_FULL_ARENA 0x00000001 +#define CFE_FLG_ENV_PERMANENT 0x00000001 + +#define CFE_CPU_CMD_START 1 +#define CFE_CPU_CMD_STOP 0 + +#define CFE_STDHANDLE_CONSOLE 0 + +#define CFE_DEV_NETWORK 1 +#define CFE_DEV_DISK 2 +#define CFE_DEV_FLASH 3 +#define CFE_DEV_SERIAL 4 +#define CFE_DEV_CPU 5 +#define CFE_DEV_NVRAM 6 +#define CFE_DEV_CLOCK 7 +#define CFE_DEV_OTHER 8 +#define CFE_DEV_MASK 0x0F + +#define CFE_CACHE_FLUSH_D 1 +#define CFE_CACHE_INVAL_I 2 +#define CFE_CACHE_INVAL_D 4 +#define CFE_CACHE_INVAL_L2 8 + +#define CFE_FWI_64BIT 0x00000001 +#define CFE_FWI_32BIT 0x00000002 +#define CFE_FWI_RELOC 0x00000004 +#define CFE_FWI_UNCACHED 0x00000008 +#define CFE_FWI_MULTICPU 0x00000010 +#define CFE_FWI_FUNCSIM 0x00000020 +#define CFE_FWI_RTLSIM 0x00000040 + +typedef struct { + int64_t fwi_version; /* major, minor, eco version */ + int64_t fwi_totalmem; /* total installed mem */ + int64_t fwi_flags; /* various flags */ + int64_t fwi_boardid; /* board ID */ + int64_t fwi_bootarea_va; /* VA of boot area */ + int64_t fwi_bootarea_pa; /* PA of boot area */ + int64_t fwi_bootarea_size; /* size of boot area */ +} cfe_fwinfo_t; + + +/* + * cfe_strlen is handled specially: If already defined, it has been + * overridden in this environment with a standard strlen-like function. + */ +#ifdef cfe_strlen +# define CFE_API_STRLEN_CUSTOM +#else +# ifdef CFE_API_IMPL_NAMESPACE +# define cfe_strlen(a) __cfe_strlen(a) +# endif +int cfe_strlen(char *name); +#endif + +/* + * Defines and prototypes for functions which take no arguments. + */ +#ifdef CFE_API_IMPL_NAMESPACE +int64_t __cfe_getticks(void); +#define cfe_getticks() __cfe_getticks() +#else +int64_t cfe_getticks(void); +#endif + +/* + * Defines and prototypes for the rest of the functions. + */ +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_close(a) __cfe_close(a) +#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e) +#define cfe_cpu_stop(a) __cfe_cpu_stop(a) +#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f) +#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e) +#define cfe_exit(a, b) __cfe_exit(a, b) +#define cfe_flushcache(a) __cfe_cacheflush(a) +#define cfe_getdevinfo(a) __cfe_getdevinfo(a) +#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c) +#define cfe_getfwinfo(a) __cfe_getfwinfo(a) +#define cfe_getstdhandle(a) __cfe_getstdhandle(a) +#define cfe_init(a, b) __cfe_init(a, b) +#define cfe_inpstat(a) __cfe_inpstat(a) +#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f) +#define cfe_open(a) __cfe_open(a) +#define cfe_read(a, b, c) __cfe_read(a, b, c) +#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d) +#define cfe_setenv(a, b) __cfe_setenv(a, b) +#define cfe_write(a, b, c) __cfe_write(a, b, c) +#define cfe_writeblk(a, b, c, d __cfe_writeblk(a, b, c, d) +#endif /* CFE_API_IMPL_NAMESPACE */ + +int cfe_close(int handle); +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); +int cfe_cpu_stop(int cpu); +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); +int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, + uint64_t * type); +int cfe_exit(int warm, int status); +int cfe_flushcache(int flg); +int cfe_getdevinfo(char *name); +int cfe_getenv(char *name, char *dest, int destlen); +int cfe_getfwinfo(cfe_fwinfo_t * info); +int cfe_getstdhandle(int flg); +int cfe_init(uint64_t handle, uint64_t ept); +int cfe_inpstat(int handle); +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, uint64_t offset); +int cfe_open(char *name); +int cfe_read(int handle, unsigned char *buffer, int length); +int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, + int length); +int cfe_setenv(char *name, char *val); +int cfe_write(int handle, unsigned char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, + int length); + +#endif /* CFE_API_H */ diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h new file mode 100644 index 000000000000..975f00002cbe --- /dev/null +++ b/include/asm-mips/fw/cfe/cfe_error.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Error codes File: cfe_error.h + * + * CFE's global error code list is here. + * + * Author: Mitch Lichtenberg + * + ********************************************************************* */ + + +#define CFE_OK 0 +#define CFE_ERR -1 /* generic error */ +#define CFE_ERR_INV_COMMAND -2 +#define CFE_ERR_EOF -3 +#define CFE_ERR_IOERR -4 +#define CFE_ERR_NOMEM -5 +#define CFE_ERR_DEVNOTFOUND -6 +#define CFE_ERR_DEVOPEN -7 +#define CFE_ERR_INV_PARAM -8 +#define CFE_ERR_ENVNOTFOUND -9 +#define CFE_ERR_ENVREADONLY -10 + +#define CFE_ERR_NOTELF -11 +#define CFE_ERR_NOT32BIT -12 +#define CFE_ERR_WRONGENDIAN -13 +#define CFE_ERR_BADELFVERS -14 +#define CFE_ERR_NOTMIPS -15 +#define CFE_ERR_BADELFFMT -16 +#define CFE_ERR_BADADDR -17 + +#define CFE_ERR_FILENOTFOUND -18 +#define CFE_ERR_UNSUPPORTED -19 + +#define CFE_ERR_HOSTUNKNOWN -20 + +#define CFE_ERR_TIMEOUT -21 + +#define CFE_ERR_PROTOCOLERR -22 + +#define CFE_ERR_NETDOWN -23 +#define CFE_ERR_NONAMESERVER -24 + +#define CFE_ERR_NOHANDLES -25 +#define CFE_ERR_ALREADYBOUND -26 + +#define CFE_ERR_CANNOTSET -27 +#define CFE_ERR_NOMORE -28 +#define CFE_ERR_BADFILESYS -29 +#define CFE_ERR_FSNOTAVAIL -30 + +#define CFE_ERR_INVBOOTBLOCK -31 +#define CFE_ERR_WRONGDEVTYPE -32 +#define CFE_ERR_BBCHECKSUM -33 +#define CFE_ERR_BOOTPROGCHKSUM -34 + +#define CFE_ERR_LDRNOTAVAIL -35 + +#define CFE_ERR_NOTREADY -36 + +#define CFE_ERR_GETMEM -37 +#define CFE_ERR_SETMEM -38 + +#define CFE_ERR_NOTCONN -39 +#define CFE_ERR_ADDRINUSE -40 diff --git a/include/asm-mips/gfx.h b/include/asm-mips/gfx.h deleted file mode 100644 index 37235e41a6fd..000000000000 --- a/include/asm-mips/gfx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This is the user-visible SGI GFX interface. - * - * This must be used verbatim into the GNU libc. It does not include - * any kernel-only bits on it. - * - * miguel@nuclecu.unam.mx - */ -#ifndef _ASM_GFX_H -#define _ASM_GFX_H - -/* The iocls, yes, they do not make sense, but such is life */ -#define GFX_BASE 100 -#define GFX_GETNUM_BOARDS (GFX_BASE + 1) -#define GFX_GETBOARD_INFO (GFX_BASE + 2) -#define GFX_ATTACH_BOARD (GFX_BASE + 3) -#define GFX_DETACH_BOARD (GFX_BASE + 4) -#define GFX_IS_MANAGED (GFX_BASE + 5) - -#define GFX_MAPALL (GFX_BASE + 10) -#define GFX_LABEL (GFX_BASE + 11) - -#define GFX_INFO_NAME_SIZE 16 -#define GFX_INFO_LABEL_SIZE 16 - -struct gfx_info { - char name [GFX_INFO_NAME_SIZE]; /* board name */ - char label [GFX_INFO_LABEL_SIZE]; /* label name */ - unsigned short int xpmax, ypmax; /* screen resolution */ - unsigned int lenght; /* size of a complete gfx_info for this board */ -}; - -struct gfx_getboardinfo_args { - unsigned int board; /* board number. starting from zero */ - void *buf; /* pointer to gfx_info */ - unsigned int len; /* buffer size of buf */ -}; - -struct gfx_attach_board_args { - unsigned int board; /* board number, starting from zero */ - void *vaddr; /* address where the board registers should be mapped */ -}; - -#ifdef __KERNEL__ -/* umap.c */ -extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long); -extern void *vmalloc_uncached (unsigned long size); -extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr); -#endif - -#endif /* _ASM_GFX_H */ diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h deleted file mode 100644 index 8f9bd341ed49..000000000000 --- a/include/asm-mips/gt64240.h +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright - Galileo technology. - * Copyright (C) 2004 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MV64240_H -#define __ASM_MIPS_MV64240_H - -#include <asm/addrspace.h> -#include <asm/marvell.h> - -/* - * CPU Control Registers - */ - -#define CPU_CONFIGURATION 0x000 -#define CPU_MODE 0x120 -#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170 -#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178 - -/* - * Processor Address Space - */ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - -#define INTERNAL_SPACE_DECODE 0x068 - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - -/* - * CPU Sync Barrier - */ - -#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 -#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 - - -/* - * CPU Access Protect - */ - -#define CPU_LOW_PROTECT_ADDRESS_0 0X180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0X188 -#define CPU_LOW_PROTECT_ADDRESS_1 0X190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0X198 -#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 -#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 - - -/* - * Snoop Control - */ - -#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 - -/* - * CPU Error Report - */ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -/* - * Pslave Debug - */ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 -#define WRITE_DATA_LOW 0x3c0 -#define WRITE_DATA_HIGH 0x3c8 -#define WRITE_BYTE_ENABLE 0X3e0 -#define READ_DATA_LOW 0x3d0 -#define READ_DATA_HIGH 0x3d8 -#define READ_ID 0x3e8 - - -/* - * SDRAM and Device Address Space - */ - - -/* - * SDRAM Configuration - */ - -#define SDRAM_CONFIGURATION 0x448 -#define SDRAM_OPERATION_MODE 0x474 -#define SDRAM_ADDRESS_DECODE 0x47C -#define SDRAM_TIMING_PARAMETERS 0x4b4 -#define SDRAM_UMA_CONTROL 0x4a4 -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac -#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 - - -/* - * SDRAM Parameters - */ - -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK1PARAMETERS 0x450 -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_BANK3PARAMETERS 0x458 - - -/* - * SDRAM Error Report - */ - -#define SDRAM_ERROR_DATA_LOW 0x484 -#define SDRAM_ERROR_DATA_HIGH 0x480 -#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 -#define SDRAM_RECEIVED_ECC 0x488 -#define SDRAM_CALCULATED_ECC 0x48c -#define SDRAM_ECC_CONTROL 0x494 -#define SDRAM_ECC_ERROR_COUNTER 0x498 - - -/* - * SDunit Debug (for internal use) - */ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - - -/* - * Device Parameters - */ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - - -/* - * Device Interrupt - */ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - -/* - * DMA Record - */ - -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C -#define CHANNEL4_DMA_BYTE_COUNT 0x900 -#define CHANNEL5_DMA_BYTE_COUNT 0x904 -#define CHANNEL6_DMA_BYTE_COUNT 0x908 -#define CHANNEL7_DMA_BYTE_COUNT 0x90C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 -#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 -#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 -#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 -#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 -#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 -#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL4NEXT_RECORD_POINTER 0x930 -#define CHANNEL5NEXT_RECORD_POINTER 0x934 -#define CHANNEL6NEXT_RECORD_POINTER 0x938 -#define CHANNEL7NEXT_RECORD_POINTER 0x93C -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 -#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 -#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 -#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C -#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 -#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 -#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 -#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c -#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 -#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 -#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 -#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c -#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 -#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 -#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 -#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac -#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 -#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 -#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 -#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac -#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 -#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 -#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 -#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc -#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 -#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 -#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 -#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc - -/* - * DMA Channel Control - */ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 - -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 - -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 - -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define CHANNEL4CONTROL 0x940 -#define CHANNEL4CONTROL_HIGH 0x980 - -#define CHANNEL5CONTROL 0x944 -#define CHANNEL5CONTROL_HIGH 0x984 - -#define CHANNEL6CONTROL 0x948 -#define CHANNEL6CONTROL_HIGH 0x988 - -#define CHANNEL7CONTROL 0x94C -#define CHANNEL7CONTROL_HIGH 0x98C - - -/* - * DMA Arbiter - */ - -#define ARBITER_CONTROL_0_3 0x860 -#define ARBITER_CONTROL_4_7 0x960 - - -/* - * DMA Interrupt - */ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc -#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 -#define CHANELS4_7_INTERRUPT_MASK 0x9c4 -#define CHANELS4_7_ERROR_ADDRESS 0x9c8 -#define CHANELS4_7_ERROR_SELECT 0x9cc - - -/* - * DMA Debug (for internal use) - */ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 -#define DMA_X0_WRITE_DATA_LOW 0x8e8 -#define DMA_X0_WRITE_DATA_HIGH 0x8ec -#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 -#define DMA_X0_READ_DATA_LOW 0x8f0 -#define DMA_X0_READ_DATA_HIGH 0x8f4 -#define DMA_X0_READ_ID 0x8fc -#define DMA_X1_ADDRESS 0x9e0 -#define DMA_X1_COMMAND_AND_ID 0x9e4 -#define DMA_X1_WRITE_DATA_LOW 0x9e8 -#define DMA_X1_WRITE_DATA_HIGH 0x9ec -#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 -#define DMA_X1_READ_DATA_LOW 0x9f0 -#define DMA_X1_READ_DATA_HIGH 0x9f4 -#define DMA_X1_READ_ID 0x9fc - -/* - * Timer_Counter - */ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c -#define TIMER_COUNTER4 0x950 -#define TIMER_COUNTER5 0x954 -#define TIMER_COUNTER6 0x958 -#define TIMER_COUNTER7 0x95C -#define TIMER_COUNTER_4_7_CONTROL 0x964 -#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 -#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c - -/* - * PCI Slave Address Decoding - */ - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/* - * PCI Control - */ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/* - * PCI Snoop Control - */ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/* - * PCI Configuration Address - */ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/* - * PCI Error Report - */ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c - -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/* - * Lslave Debug (for internal use) - */ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */ - -/* - * PCI Configuration Function 0 - */ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0X04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/* - * PCI Configuration Function 1 - */ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/* - * PCI Configuration Function 2 - */ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/* - * PCI Configuration Function 4 - */ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/* - * PCI Configuration Function 5 - */ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/* - * PCI Configuration Function 6 - */ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/* - * PCI Configuration Function 7 - */ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 -#endif - -/* - * Interrupts - */ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 -#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c -#define CPU_SELECT_CAUSE_REGISTER 0xc70 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 -#define PCI_0SELECT_CAUSE 0xc74 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 -#define PCI_1SELECT_CAUSE 0xcf4 -#define CPU_INT_0_MASK 0xe60 -#define CPU_INT_1_MASK 0xe64 -#define CPU_INT_2_MASK 0xe68 -#define CPU_INT_3_MASK 0xe6c - -/* - * I20 Support registers - */ - -#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC - -#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090 -#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094 -#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098 -#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C -#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8 -#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4 -#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C -#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44 -#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC - -#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90 -#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94 -#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98 -#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C -#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8 -#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4 -#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C - -/* - * Communication Unit Registers - */ - -#define ETHERNET_0_ADDRESS_CONTROL_LOW -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 -#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 -#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 - -/* - * Cunit Debug (for internal use) - */ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/* - * Fast Ethernet Unit Registers - */ - -/* Ethernet */ - -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 - -/* Ethernet 0 */ - -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 - -/* Ethernet 1 */ - -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 - -/* Ethernet 2 */ - -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 - -/* - * SDMA Registers - */ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -#define CHANNEL1_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL1_COMMAND_REGISTER 0x6008 -#define CHANNEL1_RX_CMD_STATUS 0x6800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL1_RX_BUFFER_POINTER 0x6808 -#define CHANNEL1_RX_NEXT_POINTER 0x680c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL1_TX_CMD_STATUS 0x6C00 -#define CHANNEL1_TX_PACKET_SIZE 0x6C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL1_TX_NEXT_POINTER 0x6C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 - -/* SDMA Interrupt */ - -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 - - -/* - * Baude Rate Generators Registers - */ - -/* BRG 0 */ - -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ - -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ - -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ - -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 - - -/* - * Flex TDM Registers - */ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/* - * GPP Interface Registers - */ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c - -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 -#define SERIAL_PORT_MULTIPLEX 0xf010 - -/* - * I2C Registers - */ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c - -/* - * MPSC Registers - */ - -/* - * MPSC0 - */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* - * MPSC1 - */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004 -#define MPSC1_PROTOCOL_CONFIGURATION 0x9008 -#define CHANNEL1_REGISTER1 0x900c -#define CHANNEL1_REGISTER2 0x9010 -#define CHANNEL1_REGISTER3 0x9014 -#define CHANNEL1_REGISTER4 0x9018 -#define CHANNEL1_REGISTER5 0x901c -#define CHANNEL1_REGISTER6 0x9020 -#define CHANNEL1_REGISTER7 0x9024 -#define CHANNEL1_REGISTER8 0x9028 -#define CHANNEL1_REGISTER9 0x902c -#define CHANNEL1_REGISTER10 0x9030 -#define CHANNEL1_REGISTER11 0x9034 - -/* - * MPSCs Interupts - */ - -#define MPSC0_CAUSE 0xb804 -#define MPSC0_MASK 0xb884 -#define MPSC1_CAUSE 0xb80c -#define MPSC1_MASK 0xb88c - -#endif /* __ASM_MIPS_MV64240_H */ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d9119f43f9aa..2de638f84c86 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,18 +3,19 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> * Copyright (C) MIPS Technologies, Inc. * written by Ralf Baechle <ralf@linux-mips.org> */ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H - #ifdef __ASSEMBLY__ #define ASMMACRO(name, code...) .macro name; code; .endm #else +#include <asm/cpu-features.h> + #define ASMMACRO(name, code...) \ __asm__(".macro " #name "; " #code "; .endm"); \ \ @@ -23,6 +24,11 @@ static inline void name(void) \ __asm__ __volatile__ (#name); \ } +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + #endif ASMMACRO(_ssnop, @@ -81,6 +87,57 @@ do { \ : "=r" (tmp)); \ } while (0) +#elif defined(CONFIG_CPU_MIPSR1) + +/* + * These are slightly complicated by the fact that we guarantee R1 kernels to + * run fine on R2 processors. + */ +ASMMACRO(mtc0_tlbw_hazard, + _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlbw_use_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlb_probe_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_disable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(back_to_back_c0_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define __instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ + __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) + +#define instruction_hazard() \ +do { \ + if (cpu_has_mips_r2) \ + __instruction_hazard(); \ +} while (0) + #elif defined(CONFIG_CPU_R10000) /* @@ -167,6 +224,7 @@ ASMMACRO(tlb_probe_hazard, nop; nop; nop ) ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; ) ASMMACRO(irq_disable_hazard, nop; nop; nop @@ -187,7 +245,7 @@ ASMMACRO(enable_fpu_hazard, .set mips64; .set noreorder; _ssnop; - bnezl $0,.+4; + bnezl $0, .+4; _ssnop; .set pop ) diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h index 458d9fdc76bf..aca05a43a97b 100644 --- a/include/asm-mips/hw_irq.h +++ b/include/asm-mips/hw_irq.h @@ -8,15 +8,8 @@ #ifndef __ASM_HW_IRQ_H #define __ASM_HW_IRQ_H -#include <linux/profile.h> #include <asm/atomic.h> -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); - extern atomic_t irq_err_count; /* diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h new file mode 100644 index 000000000000..8f689d7df6b1 --- /dev/null +++ b/include/asm-mips/i8253.h @@ -0,0 +1,30 @@ +/* + * Machine specific IO port address definition for generic. + * Written by Osamu Tomita <tomita@cinet.co.jp> + */ +#ifndef _MACH_IO_PORTS_H +#define _MACH_IO_PORTS_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 +#define PIT_CH2 0x42 + +/* i8259A PIC registers */ +#define PIC_MASTER_CMD 0x20 +#define PIC_MASTER_IMR 0x21 +#define PIC_MASTER_ISR PIC_MASTER_CMD +#define PIC_MASTER_POLL PIC_MASTER_ISR +#define PIC_MASTER_OCW3 PIC_MASTER_ISR +#define PIC_SLAVE_CMD 0xa0 +#define PIC_SLAVE_IMR 0xa1 + +/* i8259A PIC related value */ +#define PIC_CASCADE_IR 2 +#define MASTER_ICW4_DEFAULT 0x01 +#define SLAVE_ICW4_DEFAULT 0x01 +#define PIC_ICW4_AEOI 2 + +extern void setup_pit_timer(void); + +#endif /* !_MACH_IO_PORTS_H */ diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index e88a01607fea..8572a2d90484 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h @@ -37,9 +37,8 @@ extern spinlock_t i8259A_lock; -extern void init_8259A(int auto_eoi); -extern void enable_8259A_irq(unsigned int irq); -extern void disable_8259A_irq(unsigned int irq); +extern int i8259A_irq_pending(unsigned int irq); +extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h index 92d90f75a636..cc88aed23f0f 100644 --- a/include/asm-mips/inventory.h +++ b/include/asm-mips/inventory.h @@ -17,8 +17,8 @@ typedef struct inventory_s { extern int inventory_items; -extern void add_to_inventory (int class, int type, int controller, int unit, int state); -extern int dump_inventory_to_user (void __user *userbuf, int size); +extern void add_to_inventory(int class, int type, int controller, int unit, int state); +extern int dump_inventory_to_user(void __user *userbuf, int size); extern int __init init_inventory(void); #endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 7ba92890ea13..2cd8323c8586 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -40,11 +40,11 @@ * hardware. An example use would be for flash memory that's used for * execute in place. */ -# define __raw_ioswabb(a,x) (x) -# define __raw_ioswabw(a,x) (x) -# define __raw_ioswabl(a,x) (x) -# define __raw_ioswabq(a,x) (x) -# define ____raw_ioswabq(a,x) (x) +# define __raw_ioswabb(a, x) (x) +# define __raw_ioswabw(a, x) (x) +# define __raw_ioswabl(a, x) (x) +# define __raw_ioswabq(a, x) (x) +# define ____raw_ioswabq(a, x) (x) /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ @@ -561,9 +561,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start, size) _dma_cache_wback(start,size) -#define dma_cache_inv(start, size) _dma_cache_inv(start,size) +#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) +#define dma_cache_wback(start, size) _dma_cache_wback(start, size) +#define dma_cache_inv(start, size) _dma_cache_inv(start, size) #else /* Sane hardware */ @@ -587,7 +587,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define __CSR_32_ADJUST 0 #endif -#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) +#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) /* diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h index 2036fcb9f117..85067e248a83 100644 --- a/include/asm-mips/ioctl.h +++ b/include/asm-mips/ioctl.h @@ -54,7 +54,7 @@ #define _IOC_IN 0x80000000 #define _IOC_INOUT (IOC_IN|IOC_OUT) -#define _IOC(dir,type,nr,size) \ +#define _IOC(dir, type, nr, size) \ (((dir) << _IOC_DIRSHIFT) | \ ((type) << _IOC_TYPESHIFT) | \ ((nr) << _IOC_NRSHIFT) | \ @@ -68,13 +68,13 @@ extern unsigned int __invalid_size_argument_for_IOC; sizeof(t) : __invalid_size_argument_for_IOC) /* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) +#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size))) +#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size)) +#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size)) +#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size)) /* used to decode them.. */ diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h index 92f6c36aac4d..3f04a995ec54 100644 --- a/include/asm-mips/ioctls.h +++ b/include/asm-mips/ioctls.h @@ -77,8 +77,12 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x7416 /* Return the session ID of FD */ -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TCGETS2 _IOR('T', 0x2A, struct termios2) +#define TCSETS2 _IOW('T', 0x2B, struct termios2) +#define TCSETSW2 _IOW('T', 0x2C, struct termios2) +#define TCSETSF2 _IOW('T', 0x2D, struct termios2) +#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ diff --git a/include/asm-mips/ip32/machine.h b/include/asm-mips/ip32/machine.h deleted file mode 100644 index 1b631b8da6f8..000000000000 --- a/include/asm-mips/ip32/machine.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * machine.h -- Machine/group probing for ip32 - * - * Copyright (C) 2001 Keith M Wesolowski - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _ASM_IP32_MACHINE_H -#define _ASM_IP32_MACHINE_H - - -#ifdef CONFIG_SGI_IP32 - -#define SGI_MACH_O2 0x3201 - -#endif /* CONFIG_SGI_IP32 */ - -#endif /* _ASM_SGI_MACHINE_H */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 97102ebc54b1..a58f0eecc68f 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -24,7 +24,62 @@ static inline int irq_canonicalize(int irq) #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ #endif +#ifdef CONFIG_MIPS_MT_SMTC + +struct irqaction; + +extern unsigned long irq_hwmask[]; +extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, + unsigned long hwmask); + +static inline void smtc_im_ack_irq(unsigned int irq) +{ + if (irq_hwmask[irq] & ST0_IM) + set_c0_status(irq_hwmask[irq] & ST0_IM); +} + +#else + +static inline void smtc_im_ack_irq(unsigned int irq) +{ +} + +#endif /* CONFIG_MIPS_MT_SMTC */ + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +#include <linux/cpumask.h> + +extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity); +extern void smtc_forward_irq(unsigned int irq); + +/* + * IRQ affinity hook invoked at the beginning of interrupt dispatch + * if option is enabled. + * + * Up through Linux 2.6.22 (at least) cpumask operations are very + * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity + * used a "fast path" per-IRQ-descriptor cache of affinity information + * to reduce latency. As there is a project afoot to optimize the + * cpumask implementations, this version is optimistically assuming + * that cpumask.h macro overhead is reasonable during interrupt dispatch. + */ +#define IRQ_AFFINITY_HOOK(irq) \ +do { \ + if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + smtc_forward_irq(irq); \ + irq_exit(); \ + return; \ + } \ +} while (0) + +#else /* Not doing SMTC affinity */ + +#define IRQ_AFFINITY_HOOK(irq) do { } while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP + /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() @@ -33,12 +88,27 @@ static inline int irq_canonicalize(int irq) */ #define __DO_IRQ_SMTC_HOOK(irq) \ do { \ + IRQ_AFFINITY_HOOK(irq); \ if (irq_hwmask[irq] & 0x0000ff00) \ write_c0_tccontext(read_c0_tccontext() & \ - ~(irq_hwmask[irq] & 0x0000ff00)); \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ +} while (0) + +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ +do { \ + if (irq_hwmask[irq] & 0x0000ff00) \ + write_c0_tccontext(read_c0_tccontext() & \ + ~(irq_hwmask[irq] & 0x0000ff00)); \ } while (0) + #else -#define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) + +#define __DO_IRQ_SMTC_HOOK(irq) \ +do { \ + IRQ_AFFINITY_HOOK(irq); \ +} while (0) +#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) + #endif /* @@ -57,16 +127,25 @@ do { \ irq_exit(); \ } while (0) -extern void arch_init_irq(void); -extern void spurious_interrupt(void); +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * To avoid inefficient and in some cases pathological re-checking of + * IRQ affinity, we have this variant that skips the affinity check. + */ -#ifdef CONFIG_MIPS_MT_SMTC -struct irqaction; -extern unsigned long irq_hwmask[]; -extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, - unsigned long hwmask); -#endif /* CONFIG_MIPS_MT_SMTC */ +#define do_IRQ_no_affinity(irq) \ +do { \ + irq_enter(); \ + __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) + +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ + +extern void arch_init_irq(void); +extern void spurious_interrupt(void); extern int allocate_irqno(void); extern void alloc_legacy_irqno(void); diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h new file mode 100644 index 000000000000..f9a7c3ac2e66 --- /dev/null +++ b/include/asm-mips/irq_gt641xx.h @@ -0,0 +1,60 @@ +/* + * Galileo/Marvell GT641xx IRQ definitions. + * + * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _ASM_IRQ_GT641XX_H +#define _ASM_IRQ_GT641XX_H + +#ifndef GT641XX_IRQ_BASE +#define GT641XX_IRQ_BASE 8 +#endif + +#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) +#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) +#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) +#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) +#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) +#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) +#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) +#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) +#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) +#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) +#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) +#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) +#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) +#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) +#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) +#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) +#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) +#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) +#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) +#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) +#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) +#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) +#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) +#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) +#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) +#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) +#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) +#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) +#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) + +extern void gt641xx_irq_dispatch(void); +extern void gt641xx_irq_init(void); + +#endif /* _ASM_IRQ_GT641XX_H */ diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h index e459fa05db83..881e8866501d 100644 --- a/include/asm-mips/irqflags.h +++ b/include/asm-mips/irqflags.h @@ -16,7 +16,7 @@ #include <linux/compiler.h> #include <asm/hazards.h> -__asm__ ( +__asm__( " .macro raw_local_irq_enable \n" " .set push \n" " .set reorder \n" @@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void) * * Workaround: mask EXL bit of the result or place a nop before mfc0. */ -__asm__ ( +__asm__( " .macro raw_local_irq_disable\n" " .set push \n" " .set noat \n" @@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void) : "memory"); } -__asm__ ( +__asm__( " .macro raw_local_save_flags flags \n" " .set push \n" " .set reorder \n" @@ -113,7 +113,7 @@ __asm__ __volatile__( \ "raw_local_save_flags %0" \ : "=r" (x)) -__asm__ ( +__asm__( " .macro raw_local_irq_save result \n" " .set push \n" " .set reorder \n" @@ -145,7 +145,7 @@ __asm__ __volatile__( \ : /* no inputs */ \ : "memory") -__asm__ ( +__asm__( " .macro raw_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h index 81cbf004fd13..83f449dec95e 100644 --- a/include/asm-mips/jazz.h +++ b/include/asm-mips/jazz.h @@ -185,37 +185,25 @@ typedef struct { #define JAZZ_IO_IRQ_ENABLE 0xe0010002 /* - * JAZZ interrupt enable bits - */ -#define JAZZ_IE_PARALLEL (1 << 0) -#define JAZZ_IE_FLOPPY (1 << 1) -#define JAZZ_IE_SOUND (1 << 2) -#define JAZZ_IE_VIDEO (1 << 3) -#define JAZZ_IE_ETHERNET (1 << 4) -#define JAZZ_IE_SCSI (1 << 5) -#define JAZZ_IE_KEYBOARD (1 << 6) -#define JAZZ_IE_MOUSE (1 << 7) -#define JAZZ_IE_SERIAL1 (1 << 8) -#define JAZZ_IE_SERIAL2 (1 << 9) - -/* * JAZZ Interrupt Level definitions * * This is somewhat broken. For reasons which nobody can remember anymore * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ -#define JAZZ_PARALLEL_IRQ 16 -#define JAZZ_FLOPPY_IRQ 17 -#define JAZZ_SOUND_IRQ 18 -#define JAZZ_VIDEO_IRQ 19 -#define JAZZ_ETHERNET_IRQ 20 -#define JAZZ_SCSI_IRQ 21 -#define JAZZ_KEYBOARD_IRQ 22 -#define JAZZ_MOUSE_IRQ 23 -#define JAZZ_SERIAL1_IRQ 24 -#define JAZZ_SERIAL2_IRQ 25 - -#define JAZZ_TIMER_IRQ 31 +#define JAZZ_IRQ_START 24 +#define JAZZ_IRQ_END (24 + 9) +#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) +#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) +#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) +#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) +#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) +#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) +#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) +#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) +#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) +#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) + +#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) /* diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h index 0a205b77e505..8bb37bba68f0 100644 --- a/include/asm-mips/jazzdma.h +++ b/include/asm-mips/jazzdma.h @@ -7,7 +7,6 @@ /* * Prototypes and macros */ -extern void vdma_init(void); extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); extern int vdma_free(unsigned long laddr); extern int vdma_remap(unsigned long laddr, unsigned long paddr, diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h index 958e29706e2d..b2dc35f56181 100644 --- a/include/asm-mips/jmr3927/jmr3927.h +++ b/include/asm-mips/jmr3927/jmr3927.h @@ -13,6 +13,7 @@ #include <asm/jmr3927/tx3927.h> #include <asm/addrspace.h> #include <asm/system.h> +#include <asm/txx9irq.h> /* CS */ #define JMR3927_ROMCE0 0x1fc00000 /* 4M */ @@ -115,7 +116,7 @@ #define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ #define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ -#define JMR3927_IRQ_IRC 16 +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE #define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) #define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 0b9073bfb759..211bcf47fffb 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -50,41 +50,26 @@ struct tx3927_dma_reg { volatile unsigned long unused0; }; -struct tx3927_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; - #include <asm/byteorder.h> #ifdef __BIG_ENDIAN -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif struct tx3927_pcic_reg { @@ -225,26 +210,6 @@ struct tx3927_ccfg_reg { /* * IRC */ -#define TX3927_IR_MAX_LEVEL 7 - -/* IRCER : Int. Control Enable */ -#define TX3927_IRCER_ICE 0x00000001 - -/* IRCR : Int. Control */ -#define TX3927_IRCR_LOW 0x00000000 -#define TX3927_IRCR_HIGH 0x00000001 -#define TX3927_IRCR_DOWN 0x00000002 -#define TX3927_IRCR_UP 0x00000003 - -/* IRSCR : Int. Status Control */ -#define TX3927_IRSCR_EIClrE 0x00000100 -#define TX3927_IRSCR_EIClr_MASK 0x0000000f - -/* IRCSR : Int. Current Status */ -#define TX3927_IRCSR_IF 0x00010000 -#define TX3927_IRCSR_ILV_MASK 0x00000700 -#define TX3927_IRCSR_IVL_MASK 0x0000001f - #define TX3927_IR_INT0 0 #define TX3927_IR_INT1 1 #define TX3927_IR_INT2 2 @@ -347,7 +312,6 @@ struct tx3927_ccfg_reg { #define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) #define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG) #define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) #define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h new file mode 100644 index 000000000000..edcd7544b358 --- /dev/null +++ b/include/asm-mips/lasat/ds1603.h @@ -0,0 +1,18 @@ +#include <asm/addrspace.h> + +/* Lasat 100 */ +#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) +#define DS1603_RST_100 (1 << 2) +#define DS1603_CLK_100 (1 << 0) +#define DS1603_DATA_SHIFT_100 1 +#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) + +/* Lasat 200 */ +#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) +#define DS1603_RST_200 (1 << 3) +#define DS1603_CLK_200 (1 << 4) +#define DS1603_DATA_200 (1 << 5) + +#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) +#define DS1603_DATA_READ_SHIFT_200 9 +#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h new file mode 100644 index 000000000000..3dac203697fa --- /dev/null +++ b/include/asm-mips/lasat/eeprom.h @@ -0,0 +1,17 @@ +#include <asm/addrspace.h> + +/* lasat 100 */ +#define AT93C_REG_100 KSEG1ADDR(0x1c810000) +#define AT93C_RDATA_REG_100 AT93C_REG_100 +#define AT93C_RDATA_SHIFT_100 4 +#define AT93C_WDATA_SHIFT_100 4 +#define AT93C_CS_M_100 (1 << 5) +#define AT93C_CLK_M_100 (1 << 3) + +/* lasat 200 */ +#define AT93C_REG_200 KSEG1ADDR(0x11000000) +#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) +#define AT93C_RDATA_SHIFT_200 8 +#define AT93C_WDATA_SHIFT_200 2 +#define AT93C_CS_M_200 (1 << 0) +#define AT93C_CLK_M_200 (1 << 1) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h new file mode 100644 index 000000000000..f5589f31a197 --- /dev/null +++ b/include/asm-mips/lasat/head.h @@ -0,0 +1,22 @@ +/* + * Image header stuff + */ +#ifndef _HEAD_H +#define _HEAD_H + +#define LASAT_K_MAGIC0_VAL 0xfedeabba +#define LASAT_K_MAGIC1_VAL 0x00bedead + +#ifndef _LANGUAGE_ASSEMBLY +#include <linux/types.h> +struct bootloader_header { + u32 magic[2]; + u32 version; + u32 image_start; + u32 image_size; + u32 kernel_start; + u32 kernel_entry; +}; +#endif + +#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h new file mode 100644 index 000000000000..ea04d9262edc --- /dev/null +++ b/include/asm-mips/lasat/lasat.h @@ -0,0 +1,256 @@ +/* + * lasat.h + * + * Thomas Horsten <thh@lasat.com> + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Configuration for LASAT boards, loads the appropriate include files. + */ +#ifndef _LASAT_H +#define _LASAT_H + +#ifndef _LANGUAGE_ASSEMBLY + +extern struct lasat_misc { + volatile u32 *reset_reg; + volatile u32 *flash_wp_reg; + u32 flash_wp_bit; +} *lasat_misc; + +enum lasat_mtdparts { + LASAT_MTD_BOOTLOADER, + LASAT_MTD_SERVICE, + LASAT_MTD_NORMAL, + LASAT_MTD_CONFIG, + LASAT_MTD_FS, + LASAT_MTD_LAST +}; + +/* + * The format of the data record in the EEPROM. + * See Documentation/LASAT/eeprom.txt for a detailed description + * of the fields in this struct, and the LASAT Hardware Configuration + * field specification for a detailed description of the config + * field. + */ +#include <linux/types.h> + +#define LASAT_EEPROM_VERSION 7 +struct lasat_eeprom_struct { + unsigned int version; + unsigned int cfg[3]; + unsigned char hwaddr[6]; + unsigned char print_partno[12]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[12]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[16]; + unsigned char pwdnull; + unsigned char vendid; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[11]; + unsigned char debugaccess; + unsigned short prid; + unsigned int serviceflag; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +struct lasat_eeprom_struct_pre7 { + unsigned int version; + unsigned int flags[3]; + unsigned char hwaddr0[6]; + unsigned char hwaddr1[6]; + unsigned char print_partno[9]; + unsigned char term0; + unsigned char print_serial[14]; + unsigned char term1; + unsigned char prod_partno[9]; + unsigned char term2; + unsigned char prod_serial[14]; + unsigned char term3; + unsigned char passwd_hash[24]; + unsigned char pwdnull; + unsigned char vendor; + unsigned char ts_ref; + unsigned char ts_signoff; + unsigned char reserved[6]; + unsigned int writecount; + unsigned int ipaddr; + unsigned int netmask; + unsigned int crc32; +}; + +/* Configuration descriptor encoding - see the doc for details */ + +#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) +#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) +#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) +#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf) +#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf) +#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) +#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) + +#define LASAT_W1_EDHAC(v) (((v)) & 0xf) +#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) +#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) +#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) +#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1) +#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1) +#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1) +#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1) +#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf) +#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf) +#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf) +#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf) +#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf) + +/* Routines specific to LASAT boards */ + +#define LASAT_BMID_MASQUERADE2 0 +#define LASAT_BMID_MASQUERADEPRO 1 +#define LASAT_BMID_SAFEPIPE25 2 +#define LASAT_BMID_SAFEPIPE50 3 +#define LASAT_BMID_SAFEPIPE100 4 +#define LASAT_BMID_SAFEPIPE5000 5 +#define LASAT_BMID_SAFEPIPE7000 6 +#define LASAT_BMID_SAFEPIPE1000 7 +#if 0 +#define LASAT_BMID_SAFEPIPE30 7 +#define LASAT_BMID_SAFEPIPE5100 8 +#define LASAT_BMID_SAFEPIPE7100 9 +#endif +#define LASAT_BMID_UNKNOWN 0xf +#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */ + +#define LASAT_HAS_EDHAC (1 << 0) +#define LASAT_EDHAC_FAST (1 << 1) +#define LASAT_HAS_EADI (1 << 2) +#define LASAT_HAS_HIFN (1 << 3) +#define LASAT_HAS_ISDN (1 << 4) +#define LASAT_HAS_LEASEDLINE_IF (1 << 5) +#define LASAT_HAS_HDC (1 << 6) + +#define LASAT_PRID_MASQUERADE2 0 +#define LASAT_PRID_MASQUERADEPRO 1 +#define LASAT_PRID_SAFEPIPE25 2 +#define LASAT_PRID_SAFEPIPE50 3 +#define LASAT_PRID_SAFEPIPE100 4 +#define LASAT_PRID_SAFEPIPE5000 5 +#define LASAT_PRID_SAFEPIPE7000 6 +#define LASAT_PRID_SAFEPIPE30 7 +#define LASAT_PRID_SAFEPIPE5100 8 +#define LASAT_PRID_SAFEPIPE7100 9 + +#define LASAT_PRID_SAFEPIPE1110 10 +#define LASAT_PRID_SAFEPIPE3020 11 +#define LASAT_PRID_SAFEPIPE3030 12 +#define LASAT_PRID_SAFEPIPE5020 13 +#define LASAT_PRID_SAFEPIPE5030 14 +#define LASAT_PRID_SAFEPIPE1120 15 +#define LASAT_PRID_SAFEPIPE1130 16 +#define LASAT_PRID_SAFEPIPE6010 17 +#define LASAT_PRID_SAFEPIPE6110 18 +#define LASAT_PRID_SAFEPIPE6210 19 +#define LASAT_PRID_SAFEPIPE1020 20 +#define LASAT_PRID_SAFEPIPE1040 21 +#define LASAT_PRID_SAFEPIPE1060 22 + +struct lasat_info { + unsigned int li_cpu_hz; + unsigned int li_bus_hz; + unsigned int li_bmid; + unsigned int li_memsize; + unsigned int li_flash_size; + unsigned int li_prid; + unsigned char li_bmstr[16]; + unsigned char li_namestr[32]; + unsigned char li_typestr[16]; + /* Info on the Flash layout */ + unsigned int li_flash_base; + unsigned long li_flashpart_base[LASAT_MTD_LAST]; + unsigned long li_flashpart_size[LASAT_MTD_LAST]; + struct lasat_eeprom_struct li_eeprom_info; + unsigned int li_eeprom_upgrade_version; + unsigned int li_debugaccess; +}; + +extern struct lasat_info lasat_board_info; + +static inline unsigned long lasat_flash_partition_start(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_base[partno]; +} + +static inline unsigned long lasat_flash_partition_size(int partno) +{ + if (partno < 0 || partno >= LASAT_MTD_LAST) + return 0; + + return lasat_board_info.li_flashpart_size[partno]; +} + +/* Called from setup() to initialize the global board_info struct */ +extern int lasat_init_board_info(void); + +/* Write the modified EEPROM info struct */ +extern void lasat_write_eeprom_info(void); + +#define N_MACHTYPES 2 +/* for calibration of delays */ + +/* the lasat_ndelay function is necessary because it is used at an + * early stage of the boot process where ndelay is not calibrated. + * It is used for the bit-banging rtc and eeprom drivers */ + +#include <linux/delay.h> + +/* calculating with the slowest board with 100 MHz clock */ +#define LASAT_100_DIVIDER 20 +/* All 200's run at 250 MHz clock */ +#define LASAT_200_DIVIDER 8 + +extern unsigned int lasat_ndelay_divider; + +static inline void lasat_ndelay(unsigned int ns) +{ + __delay(ns / lasat_ndelay_divider); +} + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef +#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba + +/* Lasat 100 boards */ +#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) + +/* Lasat 200 boards */ +#define Vrc5074_PHYS_BASE 0x1fa00000 +#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) +#define PCI_WINDOW1 0x1a000000 + +#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h new file mode 100644 index 000000000000..065474feeccc --- /dev/null +++ b/include/asm-mips/lasat/lasatint.h @@ -0,0 +1,12 @@ +#define LASATINT_END 16 + +/* lasat 100 */ +#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) +#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) +#define LASATINT_MASK_SHIFT_100 0 + +/* lasat 200 */ +#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) +#define LASATINT_MASK_SHIFT_200 16 + diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h new file mode 100644 index 000000000000..42a492edc40e --- /dev/null +++ b/include/asm-mips/lasat/picvue.h @@ -0,0 +1,15 @@ +/* Lasat 100 */ +#define PVC_REG_100 KSEG1ADDR(0x1c820000) +#define PVC_DATA_SHIFT_100 0 +#define PVC_DATA_M_100 0xFF +#define PVC_E_100 (1 << 8) +#define PVC_RW_100 (1 << 9) +#define PVC_RS_100 (1 << 10) + +/* Lasat 200 */ +#define PVC_REG_200 KSEG1ADDR(0x11000000) +#define PVC_DATA_SHIFT_200 24 +#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) +#define PVC_E_200 (1 << 16) +#define PVC_RW_200 (1 << 17) +#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h new file mode 100644 index 000000000000..bafe68b10614 --- /dev/null +++ b/include/asm-mips/lasat/serial.h @@ -0,0 +1,13 @@ +#include <asm/lasat/lasat.h> + +/* Lasat 100 boards serial configuration */ +#define LASAT_BASE_BAUD_100 (7372800 / 16) +#define LASAT_UART_REGS_BASE_100 0x1c8b0000 +#define LASAT_UART_REGS_SHIFT_100 2 +#define LASATINT_UART_100 8 + +/* * LASAT 200 boards serial configuration */ +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) +#define LASAT_UART_REGS_SHIFT_200 3 +#define LASATINT_UART_200 13 diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h index b6185d3cfe68..e9a940d1b0c6 100644 --- a/include/asm-mips/linkage.h +++ b/include/asm-mips/linkage.h @@ -5,4 +5,6 @@ #include <asm/asm.h> #endif +#define __weak __attribute__((weak)) + #endif diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index ed882c88e0ca..f96fd59e0845 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -4,6 +4,7 @@ #include <linux/percpu.h> #include <linux/bitops.h> #include <asm/atomic.h> +#include <asm/cmpxchg.h> #include <asm/war.h> typedef struct @@ -14,10 +15,10 @@ typedef struct #define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } #define local_read(l) atomic_long_read(&(l)->a) -#define local_set(l,i) atomic_long_set(&(l)->a, (i)) +#define local_set(l, i) atomic_long_set(&(l)->a, (i)) -#define local_add(i,l) atomic_long_add((i),(&(l)->a)) -#define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) +#define local_add(i, l) atomic_long_add((i), (&(l)->a)) +#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) #define local_inc(l) atomic_long_inc(&(l)->a) #define local_dec(l) atomic_long_dec(&(l)->a) @@ -114,71 +115,9 @@ static __inline__ long local_sub_return(long i, local_t * l) return result; } -/* - * local_sub_if_positive - conditionally subtract integer from atomic variable - * @i: integer value to subtract - * @l: pointer of type local_t - * - * Atomically test @l and subtract @i if @l is greater or equal than @i. - * The function returns the old value of @l minus @i. - */ -static __inline__ long local_sub_if_positive(long i, local_t * l) -{ - unsigned long result; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - __SC "%0, %2 \n" - " .set noreorder \n" - " beqzl %0, 1b \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - __SC "%0, %2 \n" - " .set noreorder \n" - " beqz %0, 1b \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - result = l->a.counter; - result -= i; - if (result >= 0) - l->a.counter = result; - local_irq_restore(flags); - } - - return result; -} - #define local_cmpxchg(l, o, n) \ ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) -#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) +#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n))) /** * local_add_unless - add unless the number is a given value @@ -199,8 +138,8 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) -#define local_dec_return(l) local_sub_return(1,(l)) -#define local_inc_return(l) local_add_return(1,(l)) +#define local_dec_return(l) local_sub_return(1, (l)) +#define local_inc_return(l) local_add_return(1, (l)) /* * local_sub_and_test - subtract value from variable and test result @@ -211,7 +150,7 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) * true if the result is zero, or false for all * other cases. */ -#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) +#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0) /* * local_inc_and_test - increment and test @@ -234,12 +173,6 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) #define local_dec_and_test(l) (local_sub_return(1, (l)) == 0) /* - * local_dec_if_positive - decrement by 1 if old value positive - * @l: pointer of type local_t - */ -#define local_dec_if_positive(l) local_sub_if_positive(1, l) - -/* * local_add_negative - add and test if negative * @l: pointer of type local_t * @i: integer value to add @@ -248,7 +181,7 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) * if the result is negative, or false when * result is greater than or equal to zero. */ -#define local_add_negative(i,l) (local_add_return(i, (l)) < 0) +#define local_add_negative(i, l) (local_add_return(i, (l)) < 0) /* Use these for per-cpu local_t variables: on some archs they are * much more efficient than these naive implementations. Note they take @@ -257,8 +190,8 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) #define __local_inc(l) ((l)->a.counter++) #define __local_dec(l) ((l)->a.counter++) -#define __local_add(i,l) ((l)->a.counter+=(i)) -#define __local_sub(i,l) ((l)->a.counter-=(i)) +#define __local_add(i, l) ((l)->a.counter+=(i)) +#define __local_sub(i, l) ((l)->a.counter-=(i)) /* Need to disable preemption for the cpu local counters otherwise we could still access a variable of a previous CPU in a non atomic way. */ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 58fca8a5a9a6..10f613f23c33 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) - #define SYS_CNTRL_E1S (1<<23) - #define SYS_CNTRL_T1S (1<<20) - #define SYS_CNTRL_M21 (1<<19) - #define SYS_CNTRL_M11 (1<<18) - #define SYS_CNTRL_M01 (1<<17) - #define SYS_CNTRL_C1S (1<<16) - #define SYS_CNTRL_BP (1<<14) - #define SYS_CNTRL_EN1 (1<<13) - #define SYS_CNTRL_BT1 (1<<12) - #define SYS_CNTRL_EN0 (1<<11) - #define SYS_CNTRL_BT0 (1<<10) - #define SYS_CNTRL_E0 (1<<8) - #define SYS_CNTRL_E0S (1<<7) - #define SYS_CNTRL_32S (1<<5) - #define SYS_CNTRL_T0S (1<<4) - #define SYS_CNTRL_M20 (1<<3) - #define SYS_CNTRL_M10 (1<<2) - #define SYS_CNTRL_M00 (1<<1) - #define SYS_CNTRL_C0S (1<<0) +# define SYS_CNTRL_E1S (1<<23) +# define SYS_CNTRL_T1S (1<<20) +# define SYS_CNTRL_M21 (1<<19) +# define SYS_CNTRL_M11 (1<<18) +# define SYS_CNTRL_M01 (1<<17) +# define SYS_CNTRL_C1S (1<<16) +# define SYS_CNTRL_BP (1<<14) +# define SYS_CNTRL_EN1 (1<<13) +# define SYS_CNTRL_BT1 (1<<12) +# define SYS_CNTRL_EN0 (1<<11) +# define SYS_CNTRL_BT0 (1<<10) +# define SYS_CNTRL_E0 (1<<8) +# define SYS_CNTRL_E0S (1<<7) +# define SYS_CNTRL_32S (1<<5) +# define SYS_CNTRL_T0S (1<<4) +# define SYS_CNTRL_M20 (1<<3) +# define SYS_CNTRL_M10 (1<<2) +# define SYS_CNTRL_M00 (1<<1) +# define SYS_CNTRL_C0S (1<<0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) @@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* I2S Controller */ #define I2S_DATA 0xB1000000 - #define I2S_DATA_MASK (0xffffff) +# define I2S_DATA_MASK (0xffffff) #define I2S_CONFIG 0xB1000004 - #define I2S_CONFIG_XU (1<<25) - #define I2S_CONFIG_XO (1<<24) - #define I2S_CONFIG_RU (1<<23) - #define I2S_CONFIG_RO (1<<22) - #define I2S_CONFIG_TR (1<<21) - #define I2S_CONFIG_TE (1<<20) - #define I2S_CONFIG_TF (1<<19) - #define I2S_CONFIG_RR (1<<18) - #define I2S_CONFIG_RE (1<<17) - #define I2S_CONFIG_RF (1<<16) - #define I2S_CONFIG_PD (1<<11) - #define I2S_CONFIG_LB (1<<10) - #define I2S_CONFIG_IC (1<<9) - #define I2S_CONFIG_FM_BIT 7 - #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) - #define I2S_CONFIG_TN (1<<6) - #define I2S_CONFIG_RN (1<<5) - #define I2S_CONFIG_SZ_BIT 0 - #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) +# define I2S_CONFIG_XU (1<<25) +# define I2S_CONFIG_XO (1<<24) +# define I2S_CONFIG_RU (1<<23) +# define I2S_CONFIG_RO (1<<22) +# define I2S_CONFIG_TR (1<<21) +# define I2S_CONFIG_TE (1<<20) +# define I2S_CONFIG_TF (1<<19) +# define I2S_CONFIG_RR (1<<18) +# define I2S_CONFIG_RE (1<<17) +# define I2S_CONFIG_RF (1<<16) +# define I2S_CONFIG_PD (1<<11) +# define I2S_CONFIG_LB (1<<10) +# define I2S_CONFIG_IC (1<<9) +# define I2S_CONFIG_FM_BIT 7 +# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) +# define I2S_CONFIG_TN (1<<6) +# define I2S_CONFIG_RN (1<<5) +# define I2S_CONFIG_SZ_BIT 0 +# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 - #define I2S_CONTROL_D (1<<1) - #define I2S_CONTROL_CE (1<<0) +# define I2S_CONTROL_D (1<<1) +# define I2S_CONTROL_CE (1<<0) /* USB Host Controller */ #ifndef USB_OHCI_LEN @@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define USBD_EP5RD 0xB0200014 #define USBD_INTEN 0xB0200018 #define USBD_INTSTAT 0xB020001C - #define USBDEV_INT_SOF (1<<12) - #define USBDEV_INT_HF_BIT 6 - #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) - #define USBDEV_INT_CMPLT_BIT 0 - #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) +# define USBDEV_INT_SOF (1<<12) +# define USBDEV_INT_HF_BIT 6 +# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) +# define USBDEV_INT_CMPLT_BIT 0 +# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) #define USBD_CONFIG 0xB0200020 #define USBD_EP0CS 0xB0200024 #define USBD_EP2CS 0xB0200028 #define USBD_EP3CS 0xB020002C #define USBD_EP4CS 0xB0200030 #define USBD_EP5CS 0xB0200034 - #define USBDEV_CS_SU (1<<14) - #define USBDEV_CS_NAK (1<<13) - #define USBDEV_CS_ACK (1<<12) - #define USBDEV_CS_BUSY (1<<11) - #define USBDEV_CS_TSIZE_BIT 1 - #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) - #define USBDEV_CS_STALL (1<<0) +# define USBDEV_CS_SU (1<<14) +# define USBDEV_CS_NAK (1<<13) +# define USBDEV_CS_ACK (1<<12) +# define USBDEV_CS_BUSY (1<<11) +# define USBDEV_CS_TSIZE_BIT 1 +# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) +# define USBDEV_CS_STALL (1<<0) #define USBD_EP0RDSTAT 0xB0200040 #define USBD_EP0WRSTAT 0xB0200044 #define USBD_EP2WRSTAT 0xB0200048 #define USBD_EP3WRSTAT 0xB020004C #define USBD_EP4RDSTAT 0xB0200050 #define USBD_EP5RDSTAT 0xB0200054 - #define USBDEV_FSTAT_FLUSH (1<<6) - #define USBDEV_FSTAT_UF (1<<5) - #define USBDEV_FSTAT_OF (1<<4) - #define USBDEV_FSTAT_FCNT_BIT 0 - #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) +# define USBDEV_FSTAT_FLUSH (1<<6) +# define USBDEV_FSTAT_UF (1<<5) +# define USBDEV_FSTAT_OF (1<<4) +# define USBDEV_FSTAT_FCNT_BIT 0 +# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) #define USBD_ENABLE 0xB0200058 - #define USBDEV_ENABLE (1<<1) - #define USBDEV_CE (1<<0) +# define USBDEV_ENABLE (1<<1) +# define USBDEV_CE (1<<0) #endif /* !CONFIG_SOC_AU1200 */ @@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 - #define MAC_RX_ENABLE (1<<2) - #define MAC_TX_ENABLE (1<<3) - #define MAC_DEF_CHECK (1<<5) - #define MAC_SET_BL(X) (((X)&0x3)<<6) - #define MAC_AUTO_PAD (1<<8) - #define MAC_DISABLE_RETRY (1<<10) - #define MAC_DISABLE_BCAST (1<<11) - #define MAC_LATE_COL (1<<12) - #define MAC_HASH_MODE (1<<13) - #define MAC_HASH_ONLY (1<<15) - #define MAC_PASS_ALL (1<<16) - #define MAC_INVERSE_FILTER (1<<17) - #define MAC_PROMISCUOUS (1<<18) - #define MAC_PASS_ALL_MULTI (1<<19) - #define MAC_FULL_DUPLEX (1<<20) - #define MAC_NORMAL_MODE 0 - #define MAC_INT_LOOPBACK (1<<21) - #define MAC_EXT_LOOPBACK (1<<22) - #define MAC_DISABLE_RX_OWN (1<<23) - #define MAC_BIG_ENDIAN (1<<30) - #define MAC_RX_ALL (1<<31) +# define MAC_RX_ENABLE (1<<2) +# define MAC_TX_ENABLE (1<<3) +# define MAC_DEF_CHECK (1<<5) +# define MAC_SET_BL(X) (((X)&0x3)<<6) +# define MAC_AUTO_PAD (1<<8) +# define MAC_DISABLE_RETRY (1<<10) +# define MAC_DISABLE_BCAST (1<<11) +# define MAC_LATE_COL (1<<12) +# define MAC_HASH_MODE (1<<13) +# define MAC_HASH_ONLY (1<<15) +# define MAC_PASS_ALL (1<<16) +# define MAC_INVERSE_FILTER (1<<17) +# define MAC_PROMISCUOUS (1<<18) +# define MAC_PASS_ALL_MULTI (1<<19) +# define MAC_FULL_DUPLEX (1<<20) +# define MAC_NORMAL_MODE 0 +# define MAC_INT_LOOPBACK (1<<21) +# define MAC_EXT_LOOPBACK (1<<22) +# define MAC_DISABLE_RX_OWN (1<<23) +# define MAC_BIG_ENDIAN (1<<30) +# define MAC_RX_ALL (1<<31) #define MAC_ADDRESS_HIGH 0x4 #define MAC_ADDRESS_LOW 0x8 #define MAC_MCAST_HIGH 0xC #define MAC_MCAST_LOW 0x10 #define MAC_MII_CNTRL 0x14 - #define MAC_MII_BUSY (1<<0) - #define MAC_MII_READ 0 - #define MAC_MII_WRITE (1<<1) - #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) - #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) +# define MAC_MII_BUSY (1<<0) +# define MAC_MII_READ 0 +# define MAC_MII_WRITE (1<<1) +# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) +# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) #define MAC_MII_DATA 0x18 #define MAC_FLOW_CNTRL 0x1C - #define MAC_FLOW_CNTRL_BUSY (1<<0) - #define MAC_FLOW_CNTRL_ENABLE (1<<1) - #define MAC_PASS_CONTROL (1<<2) - #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) +# define MAC_FLOW_CNTRL_BUSY (1<<0) +# define MAC_FLOW_CNTRL_ENABLE (1<<1) +# define MAC_PASS_CONTROL (1<<2) +# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) #define MAC_VLAN1_TAG 0x20 #define MAC_VLAN2_TAG 0x24 /* Ethernet Controller Enable */ - #define MAC_EN_CLOCK_ENABLE (1<<0) - #define MAC_EN_RESET0 (1<<1) - #define MAC_EN_TOSS (0<<2) - #define MAC_EN_CACHEABLE (1<<3) - #define MAC_EN_RESET1 (1<<4) - #define MAC_EN_RESET2 (1<<5) - #define MAC_DMA_RESET (1<<6) +# define MAC_EN_CLOCK_ENABLE (1<<0) +# define MAC_EN_RESET0 (1<<1) +# define MAC_EN_TOSS (0<<2) +# define MAC_EN_CACHEABLE (1<<3) +# define MAC_EN_RESET1 (1<<4) +# define MAC_EN_RESET2 (1<<5) +# define MAC_DMA_RESET (1<<6) /* Ethernet Controller DMA Channels */ @@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_TX_DMA_ADDR 0xB4004200 /* offsets from MAC_TX_RING_ADDR address */ #define MAC_TX_BUFF0_STATUS 0x0 - #define TX_FRAME_ABORTED (1<<0) - #define TX_JAB_TIMEOUT (1<<1) - #define TX_NO_CARRIER (1<<2) - #define TX_LOSS_CARRIER (1<<3) - #define TX_EXC_DEF (1<<4) - #define TX_LATE_COLL_ABORT (1<<5) - #define TX_EXC_COLL (1<<6) - #define TX_UNDERRUN (1<<7) - #define TX_DEFERRED (1<<8) - #define TX_LATE_COLL (1<<9) - #define TX_COLL_CNT_MASK (0xF<<10) - #define TX_PKT_RETRY (1<<31) +# define TX_FRAME_ABORTED (1<<0) +# define TX_JAB_TIMEOUT (1<<1) +# define TX_NO_CARRIER (1<<2) +# define TX_LOSS_CARRIER (1<<3) +# define TX_EXC_DEF (1<<4) +# define TX_LATE_COLL_ABORT (1<<5) +# define TX_EXC_COLL (1<<6) +# define TX_UNDERRUN (1<<7) +# define TX_DEFERRED (1<<8) +# define TX_LATE_COLL (1<<9) +# define TX_COLL_CNT_MASK (0xF<<10) +# define TX_PKT_RETRY (1<<31) #define MAC_TX_BUFF0_ADDR 0x4 - #define TX_DMA_ENABLE (1<<0) - #define TX_T_DONE (1<<1) - #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define TX_DMA_ENABLE (1<<0) +# define TX_T_DONE (1<<1) +# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define MAC_TX_BUFF0_LEN 0x8 #define MAC_TX_BUFF1_STATUS 0x10 #define MAC_TX_BUFF1_ADDR 0x14 @@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 - #define RX_FRAME_LEN_MASK 0x3fff - #define RX_WDOG_TIMER (1<<14) - #define RX_RUNT (1<<15) - #define RX_OVERLEN (1<<16) - #define RX_COLL (1<<17) - #define RX_ETHER (1<<18) - #define RX_MII_ERROR (1<<19) - #define RX_DRIBBLING (1<<20) - #define RX_CRC_ERROR (1<<21) - #define RX_VLAN1 (1<<22) - #define RX_VLAN2 (1<<23) - #define RX_LEN_ERROR (1<<24) - #define RX_CNTRL_FRAME (1<<25) - #define RX_U_CNTRL_FRAME (1<<26) - #define RX_MCAST_FRAME (1<<27) - #define RX_BCAST_FRAME (1<<28) - #define RX_FILTER_FAIL (1<<29) - #define RX_PACKET_FILTER (1<<30) - #define RX_MISSED_FRAME (1<<31) - - #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ +# define RX_FRAME_LEN_MASK 0x3fff +# define RX_WDOG_TIMER (1<<14) +# define RX_RUNT (1<<15) +# define RX_OVERLEN (1<<16) +# define RX_COLL (1<<17) +# define RX_ETHER (1<<18) +# define RX_MII_ERROR (1<<19) +# define RX_DRIBBLING (1<<20) +# define RX_CRC_ERROR (1<<21) +# define RX_VLAN1 (1<<22) +# define RX_VLAN2 (1<<23) +# define RX_LEN_ERROR (1<<24) +# define RX_CNTRL_FRAME (1<<25) +# define RX_U_CNTRL_FRAME (1<<26) +# define RX_MCAST_FRAME (1<<27) +# define RX_BCAST_FRAME (1<<28) +# define RX_FILTER_FAIL (1<<29) +# define RX_PACKET_FILTER (1<<30) +# define RX_MISSED_FRAME (1<<31) + +# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 - #define RX_DMA_ENABLE (1<<0) - #define RX_T_DONE (1<<1) - #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) - #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) +# define RX_DMA_ENABLE (1<<0) +# define RX_T_DONE (1<<1) +# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) #define MAC_RX_BUFF1_STATUS 0x10 #define MAC_RX_BUFF1_ADDR 0x14 #define MAC_RX_BUFF2_STATUS 0x20 @@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* SSIO */ #define SSI0_STATUS 0xB1600000 - #define SSI_STATUS_BF (1<<4) - #define SSI_STATUS_OF (1<<3) - #define SSI_STATUS_UF (1<<2) - #define SSI_STATUS_D (1<<1) - #define SSI_STATUS_B (1<<0) +# define SSI_STATUS_BF (1<<4) +# define SSI_STATUS_OF (1<<3) +# define SSI_STATUS_UF (1<<2) +# define SSI_STATUS_D (1<<1) +# define SSI_STATUS_B (1<<0) #define SSI0_INT 0xB1600004 - #define SSI_INT_OI (1<<3) - #define SSI_INT_UI (1<<2) - #define SSI_INT_DI (1<<1) +# define SSI_INT_OI (1<<3) +# define SSI_INT_UI (1<<2) +# define SSI_INT_DI (1<<1) #define SSI0_INT_ENABLE 0xB1600008 - #define SSI_INTE_OIE (1<<3) - #define SSI_INTE_UIE (1<<2) - #define SSI_INTE_DIE (1<<1) +# define SSI_INTE_OIE (1<<3) +# define SSI_INTE_UIE (1<<2) +# define SSI_INTE_DIE (1<<1) #define SSI0_CONFIG 0xB1600020 - #define SSI_CONFIG_AO (1<<24) - #define SSI_CONFIG_DO (1<<23) - #define SSI_CONFIG_ALEN_BIT 20 - #define SSI_CONFIG_ALEN_MASK (0x7<<20) - #define SSI_CONFIG_DLEN_BIT 16 - #define SSI_CONFIG_DLEN_MASK (0x7<<16) - #define SSI_CONFIG_DD (1<<11) - #define SSI_CONFIG_AD (1<<10) - #define SSI_CONFIG_BM_BIT 8 - #define SSI_CONFIG_BM_MASK (0x3<<8) - #define SSI_CONFIG_CE (1<<7) - #define SSI_CONFIG_DP (1<<6) - #define SSI_CONFIG_DL (1<<5) - #define SSI_CONFIG_EP (1<<4) +# define SSI_CONFIG_AO (1<<24) +# define SSI_CONFIG_DO (1<<23) +# define SSI_CONFIG_ALEN_BIT 20 +# define SSI_CONFIG_ALEN_MASK (0x7<<20) +# define SSI_CONFIG_DLEN_BIT 16 +# define SSI_CONFIG_DLEN_MASK (0x7<<16) +# define SSI_CONFIG_DD (1<<11) +# define SSI_CONFIG_AD (1<<10) +# define SSI_CONFIG_BM_BIT 8 +# define SSI_CONFIG_BM_MASK (0x3<<8) +# define SSI_CONFIG_CE (1<<7) +# define SSI_CONFIG_DP (1<<6) +# define SSI_CONFIG_DL (1<<5) +# define SSI_CONFIG_EP (1<<4) #define SSI0_ADATA 0xB1600024 - #define SSI_AD_D (1<<24) - #define SSI_AD_ADDR_BIT 16 - #define SSI_AD_ADDR_MASK (0xff<<16) - #define SSI_AD_DATA_BIT 0 - #define SSI_AD_DATA_MASK (0xfff<<0) +# define SSI_AD_D (1<<24) +# define SSI_AD_ADDR_BIT 16 +# define SSI_AD_ADDR_MASK (0xff<<16) +# define SSI_AD_DATA_BIT 0 +# define SSI_AD_DATA_MASK (0xfff<<0) #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 - #define SSI_CONTROL_CD (1<<1) - #define SSI_CONTROL_E (1<<0) +# define SSI_CONTROL_CD (1<<1) +# define SSI_CONTROL_E (1<<0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 @@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) #define IR_INT_CLEAR (IRDA_BASE+0x18) #define IR_CONFIG_1 (IRDA_BASE+0x20) - #define IR_RX_INVERT_LED (1<<0) - #define IR_TX_INVERT_LED (1<<1) - #define IR_ST (1<<2) - #define IR_SF (1<<3) - #define IR_SIR (1<<4) - #define IR_MIR (1<<5) - #define IR_FIR (1<<6) - #define IR_16CRC (1<<7) - #define IR_TD (1<<8) - #define IR_RX_ALL (1<<9) - #define IR_DMA_ENABLE (1<<10) - #define IR_RX_ENABLE (1<<11) - #define IR_TX_ENABLE (1<<12) - #define IR_LOOPBACK (1<<14) - #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ +# define IR_RX_INVERT_LED (1<<0) +# define IR_TX_INVERT_LED (1<<1) +# define IR_ST (1<<2) +# define IR_SF (1<<3) +# define IR_SIR (1<<4) +# define IR_MIR (1<<5) +# define IR_FIR (1<<6) +# define IR_16CRC (1<<7) +# define IR_TD (1<<8) +# define IR_RX_ALL (1<<9) +# define IR_DMA_ENABLE (1<<10) +# define IR_RX_ENABLE (1<<11) +# define IR_TX_ENABLE (1<<12) +# define IR_LOOPBACK (1<<14) +# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) #define IR_SIR_FLAGS (IRDA_BASE+0x24) #define IR_ENABLE (IRDA_BASE+0x28) - #define IR_RX_STATUS (1<<9) - #define IR_TX_STATUS (1<<10) +# define IR_RX_STATUS (1<<9) +# define IR_TX_STATUS (1<<10) #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) #define IR_CONFIG_2 (IRDA_BASE+0x3C) - #define IR_MODE_INV (1<<0) - #define IR_ONE_PIN (1<<1) +# define IR_MODE_INV (1<<0) +# define IR_ONE_PIN (1<<1) #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ #define SYS_PINFUNC 0xB190002C - #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ - #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ - #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ - #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ - #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ - #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ - #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ - #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ - #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ - #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ - #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ - #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ - #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ - #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ - #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ - #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ +# define SYS_PF_USB (1<<15) /* 2nd USB device/host */ +# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ +# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ +# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ +# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ +# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ +# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ +# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ +# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ +# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ +# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ +# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ +# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ +# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ +# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ +# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ /* Au1100 Only */ - #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ - #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ - #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ - #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ +# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ +# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ +# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ +# define SYS_PF_EX0 (1<<9) /* gpio2/clock */ /* Au1550 Only. Redefines lots of pins */ - #define SYS_PF_PSC2_MASK (7 << 17) - #define SYS_PF_PSC2_AC97 (0) - #define SYS_PF_PSC2_SPI (0) - #define SYS_PF_PSC2_I2S (1 << 17) - #define SYS_PF_PSC2_SMBUS (3 << 17) - #define SYS_PF_PSC2_GPIO (7 << 17) - #define SYS_PF_PSC3_MASK (7 << 20) - #define SYS_PF_PSC3_AC97 (0) - #define SYS_PF_PSC3_SPI (0) - #define SYS_PF_PSC3_I2S (1 << 20) - #define SYS_PF_PSC3_SMBUS (3 << 20) - #define SYS_PF_PSC3_GPIO (7 << 20) - #define SYS_PF_PSC1_S1 (1 << 1) - #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) +# define SYS_PF_PSC2_MASK (7 << 17) +# define SYS_PF_PSC2_AC97 (0) +# define SYS_PF_PSC2_SPI (0) +# define SYS_PF_PSC2_I2S (1 << 17) +# define SYS_PF_PSC2_SMBUS (3 << 17) +# define SYS_PF_PSC2_GPIO (7 << 17) +# define SYS_PF_PSC3_MASK (7 << 20) +# define SYS_PF_PSC3_AC97 (0) +# define SYS_PF_PSC3_SPI (0) +# define SYS_PF_PSC3_I2S (1 << 20) +# define SYS_PF_PSC3_SMBUS (3 << 20) +# define SYS_PF_PSC3_GPIO (7 << 20) +# define SYS_PF_PSC1_S1 (1 << 1) +# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 Only */ #ifdef CONFIG_SOC_AU1200 @@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 - #define SYS_FC_FRDIV2_BIT 22 - #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) - #define SYS_FC_FE2 (1<<21) - #define SYS_FC_FS2 (1<<20) - #define SYS_FC_FRDIV1_BIT 12 - #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) - #define SYS_FC_FE1 (1<<11) - #define SYS_FC_FS1 (1<<10) - #define SYS_FC_FRDIV0_BIT 2 - #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) - #define SYS_FC_FE0 (1<<1) - #define SYS_FC_FS0 (1<<0) +# define SYS_FC_FRDIV2_BIT 22 +# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) +# define SYS_FC_FE2 (1<<21) +# define SYS_FC_FS2 (1<<20) +# define SYS_FC_FRDIV1_BIT 12 +# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) +# define SYS_FC_FE1 (1<<11) +# define SYS_FC_FS1 (1<<10) +# define SYS_FC_FRDIV0_BIT 2 +# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) +# define SYS_FC_FE0 (1<<1) +# define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 - #define SYS_FC_FRDIV5_BIT 22 - #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) - #define SYS_FC_FE5 (1<<21) - #define SYS_FC_FS5 (1<<20) - #define SYS_FC_FRDIV4_BIT 12 - #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) - #define SYS_FC_FE4 (1<<11) - #define SYS_FC_FS4 (1<<10) - #define SYS_FC_FRDIV3_BIT 2 - #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) - #define SYS_FC_FE3 (1<<1) - #define SYS_FC_FS3 (1<<0) +# define SYS_FC_FRDIV5_BIT 22 +# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) +# define SYS_FC_FE5 (1<<21) +# define SYS_FC_FS5 (1<<20) +# define SYS_FC_FRDIV4_BIT 12 +# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) +# define SYS_FC_FE4 (1<<11) +# define SYS_FC_FS4 (1<<10) +# define SYS_FC_FRDIV3_BIT 2 +# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) +# define SYS_FC_FE3 (1<<1) +# define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 - #define SYS_CS_ME1_BIT 27 - #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) - #define SYS_CS_DE1 (1<<26) - #define SYS_CS_CE1 (1<<25) - #define SYS_CS_ME0_BIT 22 - #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) - #define SYS_CS_DE0 (1<<21) - #define SYS_CS_CE0 (1<<20) - #define SYS_CS_MI2_BIT 17 - #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) - #define SYS_CS_DI2 (1<<16) - #define SYS_CS_CI2 (1<<15) +# define SYS_CS_ME1_BIT 27 +# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) +# define SYS_CS_DE1 (1<<26) +# define SYS_CS_CE1 (1<<25) +# define SYS_CS_ME0_BIT 22 +# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) +# define SYS_CS_DE0 (1<<21) +# define SYS_CS_CE0 (1<<20) +# define SYS_CS_MI2_BIT 17 +# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) +# define SYS_CS_DI2 (1<<16) +# define SYS_CS_CI2 (1<<15) #ifdef CONFIG_SOC_AU1100 - #define SYS_CS_ML_BIT 7 - #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) - #define SYS_CS_DL (1<<6) - #define SYS_CS_CL (1<<5) +# define SYS_CS_ML_BIT 7 +# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) +# define SYS_CS_DL (1<<6) +# define SYS_CS_CL (1<<5) #else - #define SYS_CS_MUH_BIT 12 - #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) - #define SYS_CS_DUH (1<<11) - #define SYS_CS_CUH (1<<10) - #define SYS_CS_MUD_BIT 7 - #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) - #define SYS_CS_DUD (1<<6) - #define SYS_CS_CUD (1<<5) +# define SYS_CS_MUH_BIT 12 +# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) +# define SYS_CS_DUH (1<<11) +# define SYS_CS_CUH (1<<10) +# define SYS_CS_MUD_BIT 7 +# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) +# define SYS_CS_DUD (1<<6) +# define SYS_CS_CUD (1<<5) #endif - #define SYS_CS_MIR_BIT 2 - #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) - #define SYS_CS_DIR (1<<1) - #define SYS_CS_CIR (1<<0) - - #define SYS_CS_MUX_AUX 0x1 - #define SYS_CS_MUX_FQ0 0x2 - #define SYS_CS_MUX_FQ1 0x3 - #define SYS_CS_MUX_FQ2 0x4 - #define SYS_CS_MUX_FQ3 0x5 - #define SYS_CS_MUX_FQ4 0x6 - #define SYS_CS_MUX_FQ5 0x7 +# define SYS_CS_MIR_BIT 2 +# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) +# define SYS_CS_DIR (1<<1) +# define SYS_CS_CIR (1<<0) + +# define SYS_CS_MUX_AUX 0x1 +# define SYS_CS_MUX_FQ0 0x2 +# define SYS_CS_MUX_FQ1 0x3 +# define SYS_CS_MUX_FQ2 0x4 +# define SYS_CS_MUX_FQ3 0x5 +# define SYS_CS_MUX_FQ4 0x6 +# define SYS_CS_MUX_FQ5 0x7 #define SYS_CPUPLL 0xB1900060 #define SYS_AUXPLL 0xB1900064 /* AC97 Controller */ #define AC97C_CONFIG 0xB0000000 - #define AC97C_RECV_SLOTS_BIT 13 - #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) - #define AC97C_XMIT_SLOTS_BIT 3 - #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) - #define AC97C_SG (1<<2) - #define AC97C_SYNC (1<<1) - #define AC97C_RESET (1<<0) +# define AC97C_RECV_SLOTS_BIT 13 +# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) +# define AC97C_XMIT_SLOTS_BIT 3 +# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) +# define AC97C_SG (1<<2) +# define AC97C_SYNC (1<<1) +# define AC97C_RESET (1<<0) #define AC97C_STATUS 0xB0000004 - #define AC97C_XU (1<<11) - #define AC97C_XO (1<<10) - #define AC97C_RU (1<<9) - #define AC97C_RO (1<<8) - #define AC97C_READY (1<<7) - #define AC97C_CP (1<<6) - #define AC97C_TR (1<<5) - #define AC97C_TE (1<<4) - #define AC97C_TF (1<<3) - #define AC97C_RR (1<<2) - #define AC97C_RE (1<<1) - #define AC97C_RF (1<<0) +# define AC97C_XU (1<<11) +# define AC97C_XO (1<<10) +# define AC97C_RU (1<<9) +# define AC97C_RO (1<<8) +# define AC97C_READY (1<<7) +# define AC97C_CP (1<<6) +# define AC97C_TR (1<<5) +# define AC97C_TE (1<<4) +# define AC97C_TF (1<<3) +# define AC97C_RR (1<<2) +# define AC97C_RE (1<<1) +# define AC97C_RF (1<<0) #define AC97C_DATA 0xB0000008 #define AC97C_CMD 0xB000000C - #define AC97C_WD_BIT 16 - #define AC97C_READ (1<<7) - #define AC97C_INDEX_MASK 0x7f +# define AC97C_WD_BIT 16 +# define AC97C_READ (1<<7) +# define AC97C_INDEX_MASK 0x7f #define AC97C_CNTRL 0xB0000010 - #define AC97C_RS (1<<1) - #define AC97C_CE (1<<0) +# define AC97C_RS (1<<1) +# define AC97C_CE (1<<0) /* Secure Digital (SD) Controller */ @@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SD1_XMIT_FIFO 0xB0680000 #define SD1_RECV_FIFO 0xB0680004 -#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) +#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) - #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) +# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index eeb0c3115b6a..93d507cea518 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -199,7 +199,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 /* THis macro is used to find/create custom device types */ -#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) +#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) #define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) @@ -373,14 +373,14 @@ void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); Some compatibilty macros -- Needed to make changes to API without breaking existing drivers */ -#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) +#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) -#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) +#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) +#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) +#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) /* * Flags for the put_source/put_dest functions. diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 4663e8b415c9..aef0edbfe4c6 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port); void auide_outsw(unsigned long port, void *addr, u32 count); void auide_outsl(unsigned long port, void *addr, u32 count); static void auide_tune_drive(ide_drive_t *drive, byte pio); -static int auide_tune_chipset (ide_drive_t *drive, u8 speed); +static int auide_tune_chipset(ide_drive_t *drive, u8 speed); static int auide_ddma_init( _auide_hwif *auide ); static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); int __init auide_probe(void); diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h new file mode 100644 index 000000000000..dd57d03d68ba --- /dev/null +++ b/include/asm-mips/mach-au1x00/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H +#define __ASM_MIPS_MACH_AU1X00_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h new file mode 100644 index 000000000000..d008f47a28bd --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BCM47XX_H +#define __ASM_BCM47XX_H + +/* SSB bus */ +extern struct ssb_bus ssb_bcm47xx; + +#endif /* __ASM_BCM47XX_H */ diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h new file mode 100644 index 000000000000..cfc8f4d618ce --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/gpio.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> + */ + +#ifndef __BCM47XX_GPIO_H +#define __BCM47XX_GPIO_H + +#define BCM47XX_EXTIF_GPIO_LINES 5 +#define BCM47XX_CHIPCO_GPIO_LINES 16 + +extern int bcm47xx_gpio_to_irq(unsigned gpio); +extern int bcm47xx_gpio_get_value(unsigned gpio); +extern void bcm47xx_gpio_set_value(unsigned gpio, int value); +extern int bcm47xx_gpio_direction_input(unsigned gpio); +extern int bcm47xx_gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return bcm47xx_gpio_to_irq(gpio); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bcm47xx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bcm47xx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bcm47xx_gpio_direction_output(gpio, value); +} + + +/* cansleep wrappers */ +#include <asm-generic/gpio.h> + +#endif /* __BCM47XX_GPIO_H */ diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h new file mode 100644 index 000000000000..4a2b7986b582 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H +#define __ASM_MIPS_MACH_BCM947XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 9c9d2b998ca4..a79e7caf3a86 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -12,71 +12,16 @@ #ifndef __ASM_COBALT_H #define __ASM_COBALT_H -#include <irq.h> - -/* - * i8259 legacy interrupts used on Cobalt: - * - * 8 - RTC - * 9 - PCI - * 14 - IDE0 - * 15 - IDE1 - */ -#define COBALT_QUBE_SLOT_IRQ 9 - -/* - * CPU IRQs are 16 ... 23 - */ -#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE - -#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) -#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4) -#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5) -#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */ - /* - * PCI configuration space manifest constants. These are wired into - * the board layout according to the PCI spec to enable the software - * to probe the hardware configuration space in a well defined manner. - * - * The PCI_DEVSHFT() macro transforms these values into numbers - * suitable for passing as the dev parameter to the various - * pcibios_read/write_config routines. + * The Cobalt board ID information. */ -#define COBALT_PCICONF_CPU 0x06 -#define COBALT_PCICONF_ETH0 0x07 -#define COBALT_PCICONF_RAQSCSI 0x08 -#define COBALT_PCICONF_VIA 0x09 -#define COBALT_PCICONF_PCISLOT 0x0A -#define COBALT_PCICONF_ETH1 0x0C - +extern int cobalt_board_id; -/* - * The Cobalt board id information. The boards have an ID number wired - * into the VIA that is available in the high nibble of register 94. - * This register is available in the VIA configuration space through the - * interface routines qube_pcibios_read/write_config. See cobalt/pci.c - */ -#define VIA_COBALT_BRD_ID_REG 0x94 -#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4) #define COBALT_BRD_ID_QUBE1 0x3 #define COBALT_BRD_ID_RAQ1 0x4 #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 -extern int cobalt_board_id; - -#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) -# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ -# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ -# define COBALT_LED_WEB (1 << 2) /* RaQ */ -# define COBALT_LED_POWER_OFF (1 << 3) /* RaQ */ -# define COBALT_LED_RESET 0x0f - #define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK) # define COBALT_KEY_CLEAR (1 << 1) # define COBALT_KEY_LEFT (1 << 2) @@ -87,6 +32,4 @@ extern int cobalt_board_id; # define COBALT_KEY_SELECT (1 << 7) # define COBALT_KEY_MASK 0xfe -#define COBALT_UART ((volatile unsigned char *) CKSEG1ADDR(0x1c800000)) - #endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index c6dfa59d1986..b3314cf53194 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H @@ -14,7 +14,6 @@ #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 -#define cpu_has_sb1_cache 0 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 @@ -46,6 +45,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h new file mode 100644 index 000000000000..179d0e850b59 --- /dev/null +++ b/include/asm-mips/mach-cobalt/irq.h @@ -0,0 +1,58 @@ +/* + * Cobalt IRQ definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Cobalt Microserver + * Copyright (C) 1997, 2003 Ralf Baechle + * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) + * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> + */ +#ifndef _ASM_COBALT_IRQ_H +#define _ASM_COBALT_IRQ_H + +/* + * i8259 interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI slot + * 14 - IDE0 + * 15 - IDE1(no connector on board) + */ +#define I8259A_IRQ_BASE 0 + +#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) + +/* + * CPU interrupts used on Cobalt: + * + * 0 - Software interrupt 0 (unused) + * 1 - Software interrupt 0 (unused) + * 2 - cascade GT64111 + * 3 - ethernet or SCSI host controller + * 4 - ethernet + * 5 - 16550 UART + * 6 - cascade i8259 + * 7 - CP0 counter (unused) + */ +#define MIPS_CPU_IRQ_BASE 16 + +#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) +#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) +#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) + + +#define GT641XX_IRQ_BASE 24 + +#include <asm/irq_gt641xx.h> + +#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) + +#endif /* _ASM_COBALT_IRQ_H */ diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h new file mode 100644 index 000000000000..97884fd18ac0 --- /dev/null +++ b/include/asm-mips/mach-cobalt/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_COBALT_WAR_H +#define __ASM_MIPS_MACH_COBALT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h new file mode 100644 index 000000000000..ca5e2ef909ad --- /dev/null +++ b/include/asm-mips/mach-dec/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_DEC_WAR_H +#define __ASM_MIPS_MACH_DEC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_DEC_WAR_H */ diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h new file mode 100644 index 000000000000..b660a4c30e6a --- /dev/null +++ b/include/asm-mips/mach-emma2rh/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H +#define __ASM_MIPS_MACH_EMMA2RH_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 0d31854222f9..107104c3cd12 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -4,6 +4,7 @@ * for more details. * * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H @@ -27,10 +28,17 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h new file mode 100644 index 000000000000..1f82180c1598 --- /dev/null +++ b/include/asm-mips/mach-excite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H +#define __ASM_MIPS_MACH_EXCITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h index 6eba2e576aaa..a77128362a7d 100644 --- a/include/asm-mips/mach-generic/ide.h +++ b/include/asm-mips/mach-generic/ide.h @@ -33,13 +33,24 @@ static __inline__ int ide_probe_legacy(void) { #ifdef CONFIG_PCI struct pci_dev *dev; - if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL || - (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) { - pci_dev_put(dev); - - return 1; - } + /* + * This can be called on the ide_setup() path, super-early in + * boot. But the down_read() will enable local interrupts, + * which can cause some machines to crash. So here we detect + * and flag that situation and bail out early. + */ + if (no_pci_devices()) + return 0; + dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL); + if (dev) + goto found; + dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); + if (dev) + goto found; return 0; +found: + pci_dev_put(dev); + return 1; #elif defined(CONFIG_EISA) || defined(CONFIG_ISA) return 1; #else @@ -49,48 +60,42 @@ static __inline__ int ide_probe_legacy(void) static __inline__ int ide_default_irq(unsigned long base) { - if (ide_probe_legacy()) - switch (base) { - case 0x1f0: - return 14; - case 0x170: - return 15; - case 0x1e8: - return 11; - case 0x168: - return 10; - case 0x1e0: - return 8; - case 0x160: - return 12; + switch (base) { + case 0x1f0: return 14; + case 0x170: return 15; + case 0x1e8: return 11; + case 0x168: return 10; + case 0x1e0: return 8; + case 0x160: return 12; default: return 0; - } - else - return 0; + } } static __inline__ unsigned long ide_default_io_base(int index) { - if (ide_probe_legacy()) + if (!ide_probe_legacy()) + return 0; + /* + * If PCI is present then it is not safe to poke around + * the other legacy IDE ports. Only 0x1f0 and 0x170 are + * defined compatibility mode ports for PCI. A user can + * override this using ide= but we must default safe. + */ + if (no_pci_devices()) { switch (index) { - case 0: - return 0x1f0; - case 1: - return 0x170; - case 2: - return 0x1e8; - case 3: - return 0x168; - case 4: - return 0x1e0; - case 5: - return 0x160; - default: - return 0; + case 2: return 0x1e8; + case 3: return 0x168; + case 4: return 0x1e0; + case 5: return 0x160; } - else + } + switch (index) { + case 0: return 0x1f0; + case 1: return 0x170; + default: return 0; + } } #define IDE_ARCH_OBSOLETE_INIT diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h index 6e1b0c075de7..f49dc990214b 100644 --- a/include/asm-mips/mach-generic/mangle-port.h +++ b/include/asm-mips/mach-generic/mangle-port.h @@ -27,25 +27,25 @@ */ #if defined(CONFIG_SWAP_IO_SPACE) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) le16_to_cpu(x) -# define __mem_ioswabw(a,x) (x) -# define ioswabl(a,x) le32_to_cpu(x) -# define __mem_ioswabl(a,x) (x) -# define ioswabq(a,x) le64_to_cpu(x) -# define __mem_ioswabq(a,x) (x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) le16_to_cpu(x) +# define __mem_ioswabw(a, x) (x) +# define ioswabl(a, x) le32_to_cpu(x) +# define __mem_ioswabl(a, x) (x) +# define ioswabq(a, x) le64_to_cpu(x) +# define __mem_ioswabq(a, x) (x) #else -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index f7c5dc8a5336..9c8735158da1 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H @@ -30,6 +30,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 000000000000..a44fa9656a82 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP22_WAR_H +#define __ASM_MIPS_MACH_IP22_WAR_H + +/* + * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 1 +#define R4600_V1_HIT_CACHEOP_WAR 1 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index a071974b67bb..fe076380c189 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H @@ -27,6 +27,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h index 25f0c3f39adf..cf4384bfa846 100644 --- a/include/asm-mips/mach-ip27/irq.h +++ b/include/asm-mips/mach-ip27/irq.h @@ -17,4 +17,6 @@ */ #define NR_IRQS 256 +#include_next <irq.h> + #endif /* __ASM_MACH_IP27_IRQ_H */ diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h index d615312a451a..f6e4912ea062 100644 --- a/include/asm-mips/mach-ip27/mangle-port.h +++ b/include/asm-mips/mach-ip27/mangle-port.h @@ -13,13 +13,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h index 61d9be3f3175..372291f53fb9 100644 --- a/include/asm-mips/mach-ip27/topology.h +++ b/include/asm-mips/mach-ip27/topology.h @@ -2,9 +2,27 @@ #define _ASM_MACH_TOPOLOGY_H 1 #include <asm/sn/hub.h> +#include <asm/sn/types.h> #include <asm/mmzone.h> -#define cpu_to_node(cpu) (cpu_data[(cpu)].p_nodeid) +struct cpuinfo_ip27 { +// cpuid_t p_cpuid; /* PROM assigned cpuid */ + cnodeid_t p_nodeid; /* my node ID in compact-id-space */ + nasid_t p_nasid; /* my node ID in numa-as-id-space */ + unsigned char p_slice; /* Physical position on node board */ +#if 0 + unsigned long loops_per_sec; + unsigned long ipi_count; + unsigned long irq_attempt[NR_IRQS]; + unsigned long smp_local_irq_count; + unsigned long prof_multiplier; + unsigned long prof_counter; +#endif +}; + +extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; + +#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) #define parent_node(node) (node) #define node_to_cpumask(node) (hub_data(node)->h_cpus) #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h new file mode 100644 index 000000000000..e2ddcc9b1fff --- /dev/null +++ b/include/asm-mips/mach-ip27/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP27_WAR_H +#define __ASM_MIPS_MACH_IP27_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 1 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 2a3de092bf13..6782fccebe8d 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 2005 Ilya A. Volynets-Evenbakh - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H @@ -38,6 +38,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_has_4k_cache 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h index f6198a21fba1..b1e0be60f720 100644 --- a/include/asm-mips/mach-ip32/kmalloc.h +++ b/include/asm-mips/mach-ip32/kmalloc.h @@ -2,7 +2,7 @@ #define __ASM_MACH_IP32_KMALLOC_H -#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) +#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000) #define ARCH_KMALLOC_MINALIGN 32 #else #define ARCH_KMALLOC_MINALIGN 128 diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h index 81320eb55324..f1d0f1756a9f 100644 --- a/include/asm-mips/mach-ip32/mangle-port.h +++ b/include/asm-mips/mach-ip32/mangle-port.h @@ -14,13 +14,13 @@ #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -# define ioswabb(a,x) (x) -# define __mem_ioswabb(a,x) (x) -# define ioswabw(a,x) (x) -# define __mem_ioswabw(a,x) cpu_to_le16(x) -# define ioswabl(a,x) (x) -# define __mem_ioswabl(a,x) cpu_to_le32(x) -# define ioswabq(a,x) (x) -# define __mem_ioswabq(a,x) cpu_to_le32(x) +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le32(x) #endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h new file mode 100644 index 000000000000..d194056dcd7a --- /dev/null +++ b/include/asm-mips/mach-ip32/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_IP32_WAR_H +#define __ASM_MIPS_MACH_IP32_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h index f44fdba1998b..987f727afe25 100644 --- a/include/asm-mips/mach-jazz/mc146818rtc.h +++ b/include/asm-mips/mach-jazz/mc146818rtc.h @@ -4,12 +4,15 @@ * for more details. * * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * Copyright (C) 2007 Thomas Bogendoerfer * * RTC routines for Jazz style attached Dallas chip. */ #ifndef __ASM_MACH_JAZZ_MC146818RTC_H #define __ASM_MACH_JAZZ_MC146818RTC_H +#include <linux/delay.h> + #include <asm/io.h> #include <asm/jazz.h> @@ -19,16 +22,17 @@ static inline unsigned char CMOS_READ(unsigned long addr) { outb_p(addr, RTC_PORT(0)); - - return *(char *)JAZZ_RTC_BASE; + return *(volatile char *)JAZZ_RTC_BASE; } static inline void CMOS_WRITE(unsigned char data, unsigned long addr) { outb_p(addr, RTC_PORT(0)); - *(char *)JAZZ_RTC_BASE = data; + *(volatile char *)JAZZ_RTC_BASE = data; } #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) + 1980) + #endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h new file mode 100644 index 000000000000..6158ee861bfd --- /dev/null +++ b/include/asm-mips/mach-jazz/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H +#define __ASM_MIPS_MACH_JAZZ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h index 501a202631b5..11bffcd1043b 100644 --- a/include/asm-mips/mach-jmr3927/mangle-port.h +++ b/include/asm-mips/mach-jmr3927/mangle-port.h @@ -6,13 +6,13 @@ extern unsigned long __swizzle_addr_b(unsigned long port); #define __swizzle_addr_l(port) (port) #define __swizzle_addr_q(port) (port) -#define ioswabb(a,x) (x) -#define __mem_ioswabb(a,x) (x) -#define ioswabw(a,x) le16_to_cpu(x) -#define __mem_ioswabw(a,x) (x) -#define ioswabl(a,x) le32_to_cpu(x) -#define __mem_ioswabl(a,x) (x) -#define ioswabq(a,x) le64_to_cpu(x) -#define __mem_ioswabq(a,x) (x) +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) #endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h new file mode 100644 index 000000000000..1ff55fb3fbcb --- /dev/null +++ b/include/asm-mips/mach-jmr3927/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H +#define __ASM_MIPS_MACH_JMR3927_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h new file mode 100644 index 000000000000..1a9ad45cc135 --- /dev/null +++ b/include/asm-mips/mach-lasat/mach-gt64120.h @@ -0,0 +1,27 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H +#define _ASM_GT64120_LASAT_GT64120_DEP_H + +/* + * GT64120 config space base address on Lasat 100 + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h new file mode 100644 index 000000000000..bb1e0325c9be --- /dev/null +++ b/include/asm-mips/mach-lasat/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_LASAT_WAR_H +#define __ASM_MIPS_MACH_LASAT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h new file mode 100644 index 000000000000..05f89e0f2a11 --- /dev/null +++ b/include/asm-mips/mach-lemote/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H +#define __ASM_MIPS_MACH_LEMOTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h index 511f7cf3a6be..0f863148f3b6 100644 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ b/include/asm-mips/mach-mips/mach-gt64120.h @@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120; */ #define GT64120_BASE _pcictrl_gt64120 -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h new file mode 100644 index 000000000000..7c6931d5f45f --- /dev/null +++ b/include/asm-mips/mach-mips/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h new file mode 100644 index 000000000000..c8a74a3515e0 --- /dev/null +++ b/include/asm-mips/mach-mipssim/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H +#define __ASM_MIPS_MACH_MIPSSIM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h deleted file mode 100644 index a62ecb53c751..000000000000 --- a/include/asm-mips/mach-ocelot/mach-gt64120.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H -#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H - -/* - * PCI address allocation - */ -#define GT_PCI_MEM_BASE (0x22000000UL) -#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE -#define GT_PCI_IO_BASE (0x20000000UL) -#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE - -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* - * GT timer irq - */ -#define GT_TIMER 6 - -#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h index 50c1e413a688..b52e0e7ee3fb 100644 --- a/include/asm-mips/mach-pb1x00/pb1000.h +++ b/include/asm-mips/mach-pb1x00/pb1000.h @@ -32,38 +32,38 @@ #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) #define PB1000_PCR 0xBE000000 - #define PCR_SLOT_0_VPP0 (1<<0) - #define PCR_SLOT_0_VPP1 (1<<1) - #define PCR_SLOT_0_VCC0 (1<<2) - #define PCR_SLOT_0_VCC1 (1<<3) - #define PCR_SLOT_0_RST (1<<4) - - #define PCR_SLOT_1_VPP0 (1<<8) - #define PCR_SLOT_1_VPP1 (1<<9) - #define PCR_SLOT_1_VCC0 (1<<10) - #define PCR_SLOT_1_VCC1 (1<<11) - #define PCR_SLOT_1_RST (1<<12) +# define PCR_SLOT_0_VPP0 (1<<0) +# define PCR_SLOT_0_VPP1 (1<<1) +# define PCR_SLOT_0_VCC0 (1<<2) +# define PCR_SLOT_0_VCC1 (1<<3) +# define PCR_SLOT_0_RST (1<<4) + +# define PCR_SLOT_1_VPP0 (1<<8) +# define PCR_SLOT_1_VPP1 (1<<9) +# define PCR_SLOT_1_VCC0 (1<<10) +# define PCR_SLOT_1_VCC1 (1<<11) +# define PCR_SLOT_1_RST (1<<12) #define PB1000_MDR 0xBE000004 - #define MDR_PI (1<<5) /* pcmcia int latch */ - #define MDR_EPI (1<<14) /* enable pcmcia int */ - #define MDR_CPI (1<<15) /* clear pcmcia int */ +# define MDR_PI (1<<5) /* pcmcia int latch */ +# define MDR_EPI (1<<14) /* enable pcmcia int */ +# define MDR_CPI (1<<15) /* clear pcmcia int */ #define PB1000_ACR1 0xBE000008 - #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ - #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ - #define ACR1_SLOT_0_READY (1<<2) /* ready */ - #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ - #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ - #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ - #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ - #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ - #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ - #define ACR1_SLOT_1_READY (1<<10) /* ready */ - #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ - #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ - #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ - #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ +# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ +# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ +# define ACR1_SLOT_0_READY (1<<2) /* ready */ +# define ACR1_SLOT_0_STATUS (1<<3) /* status change */ +# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ +# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ +# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ +# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ +# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ +# define ACR1_SLOT_1_READY (1<<10) /* ready */ +# define ACR1_SLOT_1_STATUS (1<<11) /* status change */ +# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ +# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ +# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ #define CPLD_AUX0 0xBE00000C #define CPLD_AUX1 0xBE000010 diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h index 4c5a1cd01841..63aa3926b297 100644 --- a/include/asm-mips/mach-pb1x00/pb1100.h +++ b/include/asm-mips/mach-pb1x00/pb1100.h @@ -29,44 +29,44 @@ #define PB1100_IDENT 0xAE000000 #define BOARD_STATUS_REG 0xAE000004 - #define PB1100_ROM_SEL (1<<15) - #define PB1100_ROM_SIZ (1<<14) - #define PB1100_SWAP_BOOT (1<<13) - #define PB1100_FLASH_WP (1<<12) - #define PB1100_ROM_H_STS (1<<11) - #define PB1100_ROM_L_STS (1<<10) - #define PB1100_FLASH_H_STS (1<<9) - #define PB1100_FLASH_L_STS (1<<8) - #define PB1100_SRAM_SIZ (1<<7) - #define PB1100_TSC_BUSY (1<<6) - #define PB1100_PCMCIA_VS_MASK (3<<4) - #define PB1100_RS232_CD (1<<3) - #define PB1100_RS232_CTS (1<<2) - #define PB1100_RS232_DSR (1<<1) - #define PB1100_RS232_RI (1<<0) +# define PB1100_ROM_SEL (1<<15) +# define PB1100_ROM_SIZ (1<<14) +# define PB1100_SWAP_BOOT (1<<13) +# define PB1100_FLASH_WP (1<<12) +# define PB1100_ROM_H_STS (1<<11) +# define PB1100_ROM_L_STS (1<<10) +# define PB1100_FLASH_H_STS (1<<9) +# define PB1100_FLASH_L_STS (1<<8) +# define PB1100_SRAM_SIZ (1<<7) +# define PB1100_TSC_BUSY (1<<6) +# define PB1100_PCMCIA_VS_MASK (3<<4) +# define PB1100_RS232_CD (1<<3) +# define PB1100_RS232_CTS (1<<2) +# define PB1100_RS232_DSR (1<<1) +# define PB1100_RS232_RI (1<<0) #define PB1100_IRDA_RS232 0xAE00000C - #define PB1100_IRDA_FULL (0<<14) /* full power */ - #define PB1100_IRDA_SHUTDOWN (1<<14) - #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ - #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ - #define PB1100_IRDA_FIR (1<<13) +# define PB1100_IRDA_FULL (0<<14) /* full power */ +# define PB1100_IRDA_SHUTDOWN (1<<14) +# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ +# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ +# define PB1100_IRDA_FIR (1<<13) #define PCMCIA_BOARD_REG 0xAE000010 - #define PB1100_SD_WP1_RO (1<<15) /* read only */ - #define PB1100_SD_WP0_RO (1<<14) /* read only */ - #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ - #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ - #define PB1100_SEL_SD_CONN1 (1<<9) - #define PB1100_SEL_SD_CONN0 (1<<8) - #define PC_DEASSERT_RST (1<<7) - #define PC_DRV_EN (1<<4) +# define PB1100_SD_WP1_RO (1<<15) /* read only */ +# define PB1100_SD_WP0_RO (1<<14) /* read only */ +# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ +# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ +# define PB1100_SEL_SD_CONN1 (1<<9) +# define PB1100_SEL_SD_CONN0 (1<<8) +# define PC_DEASSERT_RST (1<<7) +# define PC_DRV_EN (1<<4) #define PB1100_G_CONTROL 0xAE000014 /* graphics control */ #define PB1100_RST_VDDI 0xAE00001C - #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ - #define PB1100_VDDI_MASK (0x1F) +# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ +# define PB1100_VDDI_MASK (0x1F) #define PB1100_LEDS 0xAE000018 diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h index 57102fa9da51..bdde00c9199b 100644 --- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h +++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h @@ -44,7 +44,7 @@ cache_begin: li t0, (1<<28) mfc0 t0, CP0_CONFIG, 7 HAZARD_CP0 - and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ + and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */ mtc0 t0, CP0_CONFIG, 7 HAZARD_CP0 @@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated: icache_invd_loop: /* 9 == register t1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ - .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ + .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */ + .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ + (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */ addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ @@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated: dcache_wbinvd_loop: /* 9 == register t1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ - .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */ + .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ + (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */ addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h index 814a7a15ab49..ad7608d44874 100644 --- a/include/asm-mips/mach-pnx8550/uart.h +++ b/include/asm-mips/mach-pnx8550/uart.h @@ -15,7 +15,7 @@ /* early macros needed for prom/kgdb */ -#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) +#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h new file mode 100644 index 000000000000..d0458dd082f9 --- /dev/null +++ b/include/asm-mips/mach-pnx8550/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H +#define __ASM_MIPS_MACH_PNX8550_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h index 529445dacedb..d2daaed235d5 100644 --- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h +++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H @@ -24,6 +24,7 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 0 diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h new file mode 100644 index 000000000000..0eaf0c548a47 --- /dev/null +++ b/include/asm-mips/mach-qemu/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_QEMU_WAR_H +#define __ASM_MIPS_MACH_QEMU_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h index 7e07283140a3..ccf543363537 100644 --- a/include/asm-mips/mach-rm/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) * * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. */ @@ -32,6 +32,8 @@ #define cpu_has_dsp 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h new file mode 100644 index 000000000000..948d3129a114 --- /dev/null +++ b/include/asm-mips/mach-rm/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_RM_WAR_H +#define __ASM_MIPS_MACH_RM_WAR_H + +/* + * The RM200C seems to have been shipped only with V2.0 R4600s + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index a25968f277a2..1c1f92415b9a 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -3,13 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -26,11 +26,18 @@ #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h new file mode 100644 index 000000000000..7950ef4f032c --- /dev/null +++ b/include/asm-mips/mach-sibyte/war.h @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H +#define __ASM_MIPS_MACH_SIBYTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 + +#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ + defined(CONFIG_SB1_PASS_2_WORKAROUNDS) + +#define BCM1250_M3_WAR 1 +#define SIBYTE_1956_WAR 1 + +#else + +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 + +#endif + +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h new file mode 100644 index 000000000000..275eaf92c748 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_llsc 1 +#define cpu_has_64bits 1 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/include/asm-mips/mach-tx49xx/kmalloc.h new file mode 100644 index 000000000000..913ff196259d --- /dev/null +++ b/include/asm-mips/mach-tx49xx/kmalloc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_MACH_TX49XX_KMALLOC_H +#define __ASM_MACH_TX49XX_KMALLOC_H + +/* + * All happy, no need to define ARCH_KMALLOC_MINALIGN + */ + +#endif /* __ASM_MACH_TX49XX_KMALLOC_H */ diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h new file mode 100644 index 000000000000..39b5d1177c57 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H +#define __ASM_MIPS_MACH_TX49XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h new file mode 100644 index 000000000000..56a38926412a --- /dev/null +++ b/include/asm-mips/mach-vr41xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H +#define __ASM_MIPS_MACH_VR41XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index ba9205a04582..00d8bf6164a9 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -43,7 +43,6 @@ #define GT_PCI_MEM_SIZE 0x02000000UL #define GT_PCI_IO_BASE 0x11000000UL #define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE /* * PCI interrupts will come in on either the INTA or INTD interrups lines, diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h new file mode 100644 index 000000000000..ac48629bb1ce --- /dev/null +++ b/include/asm-mips/mach-wrppmc/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H +#define __ASM_MIPS_MACH_WRPPMC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 42cebb7ce7a6..470e5e9e10d6 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H @@ -26,6 +26,8 @@ #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h new file mode 100644 index 000000000000..e5c6d53efc86 --- /dev/null +++ b/include/asm-mips/mach-yosemite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H +#define __ASM_MIPS_MACH_YOSEMITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h deleted file mode 100644 index b6144bafc565..000000000000 --- a/include/asm-mips/marvell.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MARVELL_H -#define __ASM_MIPS_MARVELL_H - -#include <linux/pci.h> - -#include <asm/byteorder.h> - -extern unsigned long marvell_base; - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ -#define __MV_READ(ofs) \ - (*(volatile u32 *)(marvell_base+(ofs))) -#define __MV_WRITE(ofs, data) \ - do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0) - -#define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs)) -#define MV_WRITE(ofs, data) __MV_WRITE(ofs, cpu_to_le32(data)) - -#define MV_READ_16(ofs) \ - le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs))) -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data) - -#define MV_READ_8(ofs) \ - *(volatile u8 *)(marvell_base+(ofs)) -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(marvell_base+(ofs)) = data - -#define MV_SET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits)) -#define MV_RESET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits)) - -extern struct pci_ops mv_pci_ops; - -struct mv_pci_controller { - struct pci_controller pcic; - - /* - * GT-64240/MV-64340 specific, per host bus information - */ - unsigned long config_addr; - unsigned long config_vreg; -}; - -extern void ll_mv64340_irq(void); -extern void mv64340_irq_init(unsigned int base); - -#endif /* __ASM_MIPS_MARVELL_H */ diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h index 41ac8d363c67..cdc379a0a94e 100644 --- a/include/asm-mips/mc146818-time.h +++ b/include/asm-mips/mc146818-time.h @@ -63,8 +63,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) BIN_TO_BCD(real_seconds); BIN_TO_BCD(real_minutes); } - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); + CMOS_WRITE(real_seconds, RTC_SECONDS); + CMOS_WRITE(real_minutes, RTC_MINUTES); } else { printk(KERN_WARNING "set_rtc_mmss: can't update from %d to %d\n", diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index dc3fc32eedd8..a0f04bb99c99 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -387,7 +387,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 #define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 #define BONITO_PCIMAP_PCIMAP_2 0x00040000 -#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) +#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) #define BONITO_PCIMAP_WINSIZE (1<<26) #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) @@ -412,19 +412,19 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMEMBASECFG_ASHIFT 23 #define BONITO_PCIMEMBASECFG_AMASK 0x007fffff -#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) -#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) +#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) +#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) -#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) +#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ +#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ ) /* PCICmd */ diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index c8ebcc3e1267..d58977483534 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 +#define MIPS_REVISION_CORID_CORE_FPGA4 11 /**** Artificial corid defines ****/ /* diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index eec91001bb65..93bf4e51b8a4 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h @@ -72,7 +72,7 @@ static inline unsigned long get_msc_port_base(unsigned long reg) #define SMSC_CONFIG_ACTIVATE_ENABLE 1 -#define SMSC_WRITE(x,a) outb(x,a) +#define SMSC_WRITE(x, a) outb(x, a) #define MALTA_JMPRS_REG 0x1f000210 diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index 8045abc78d0f..ac7935203f89 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h @@ -8,6 +8,12 @@ #include <linux/cpumask.h> +/* + * How many VPEs and TCs is Linux allowed to use? 0 means no limit. + */ +extern int tclimit; +extern int vpelimit; + extern cpumask_t mt_fpu_cpumask; extern unsigned long mt_fpemul_threshold; diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 294bca12cd3f..5a2f8a3a6a1f 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -41,27 +41,27 @@ * Macros for use in assembly language code */ -#define CP0_MVPCONTROL $0,1 -#define CP0_MVPCONF0 $0,2 -#define CP0_MVPCONF1 $0,3 -#define CP0_VPECONTROL $1,1 -#define CP0_VPECONF0 $1,2 -#define CP0_VPECONF1 $1,3 -#define CP0_YQMASK $1,4 -#define CP0_VPESCHEDULE $1,5 -#define CP0_VPESCHEFBK $1,6 -#define CP0_TCSTATUS $2,1 -#define CP0_TCBIND $2,2 -#define CP0_TCRESTART $2,3 -#define CP0_TCHALT $2,4 -#define CP0_TCCONTEXT $2,5 -#define CP0_TCSCHEDULE $2,6 -#define CP0_TCSCHEFBK $2,7 -#define CP0_SRSCONF0 $6,1 -#define CP0_SRSCONF1 $6,2 -#define CP0_SRSCONF2 $6,3 -#define CP0_SRSCONF3 $6,4 -#define CP0_SRSCONF4 $6,5 +#define CP0_MVPCONTROL $0, 1 +#define CP0_MVPCONF0 $0, 2 +#define CP0_MVPCONF1 $0, 3 +#define CP0_VPECONTROL $1, 1 +#define CP0_VPECONF0 $1, 2 +#define CP0_VPECONF1 $1, 3 +#define CP0_YQMASK $1, 4 +#define CP0_VPESCHEDULE $1, 5 +#define CP0_VPESCHEFBK $1, 6 +#define CP0_TCSTATUS $2, 1 +#define CP0_TCBIND $2, 2 +#define CP0_TCRESTART $2, 3 +#define CP0_TCHALT $2, 4 +#define CP0_TCCONTEXT $2, 5 +#define CP0_TCSCHEDULE $2, 6 +#define CP0_TCSCHEFBK $2, 7 +#define CP0_SRSCONF0 $6, 1 +#define CP0_SRSCONF1 $6, 2 +#define CP0_SRSCONF2 $6, 3 +#define CP0_SRSCONF3 $6, 4 +#define CP0_SRSCONF4 $6, 5 #endif @@ -291,7 +291,7 @@ static inline void ehb(void) __res; \ }) -#define mftr(rt,u,sel) \ +#define mftr(rt, u, sel) \ ({ \ unsigned long __res; \ \ @@ -315,7 +315,7 @@ do { \ : : "r" (v)); \ } while (0) -#define mttc0(rd,sel,v) \ +#define mttc0(rd, sel, v) \ ({ \ __asm__ __volatile__( \ " .set push \n" \ @@ -330,7 +330,7 @@ do { \ }) -#define mttr(rd,u,sel,v) \ +#define mttr(rd, u, sel, v) \ ({ \ __asm__ __volatile__( \ "mttr %0," #rd ", " #u ", " #sel \ @@ -362,7 +362,7 @@ do { \ #define write_vpe_c0_config1(val) mttc0(16, 1, val) #define read_vpe_c0_config7() mftc0(16, 7) #define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15,1) +#define read_vpe_c0_ebase() mftc0(15, 1) #define write_vpe_c0_ebase(val) mttc0(15, 1, val) #define write_vpe_c0_compare(val) mttc0(11, 0, val) #define read_vpe_c0_badvaddr() mftc0(8, 0) @@ -372,15 +372,15 @@ do { \ /* TC */ #define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2,1,val) +#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) #define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2,2,val) +#define write_tc_c0_tcbind(val) mttc0(2, 2, val) #define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2,3,val) +#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) #define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2,4,val) +#define write_tc_c0_tchalt(val) mttc0(2, 4, val) #define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2,5,val) +#define write_tc_c0_tccontext(val) mttc0(2, 5, val) /* GPR */ #define read_tc_gpr_sp() mftgpr(29) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 18f47f1e8cd5..aa17f658f73c 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -981,7 +981,7 @@ do { \ #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) /* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7,0) +#define read_c0_hwrena() __read_32bit_c0_register($7, 0) #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) #define read_c0_intctl() __read_32bit_c0_register($12, 1) @@ -993,7 +993,7 @@ do { \ #define read_c0_srsmap() __read_32bit_c0_register($12, 3) #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) -#define read_c0_ebase() __read_32bit_c0_register($15,1) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) /* diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 65024ffd7879..0c4f245eaeb2 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -107,7 +107,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) #else /* CONFIG_MIPS_MT_SMTC */ -#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu)) +#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) #endif /* CONFIG_MIPS_MT_SMTC */ @@ -120,7 +120,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; - for (i = 0; i < num_online_cpus(); i++) + for_each_online_cpu(i) cpu_context(i, mm) = 0; return 0; @@ -191,7 +191,7 @@ static inline void destroy_context(struct mm_struct *mm) { } -#define deactivate_mm(tsk,mm) do { } while (0) +#define deactivate_mm(tsk, mm) do { } while (0) /* * After we have set current->mm to a new value, this activates @@ -284,7 +284,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) int i; /* SMTC shares the TLB (and ASIDs) across VPEs */ - for (i = 0; i < num_online_cpus(); i++) { + for_each_online_cpu(i) { if((smtc_status & SMTC_TLB_SHARED) || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) cpu_context(i, mm) = 0; diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h new file mode 100644 index 000000000000..c3ca959aa4d9 --- /dev/null +++ b/include/asm-mips/nile4.h @@ -0,0 +1,310 @@ +/* + * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions + * + * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> + * Sony Software Development Center Europe (SDCE), Brussels + * + * This file is based on the following documentation: + * + * NEC Vrc 5074 System Controller Data Sheet, June 1998 + */ + +#ifndef _ASM_NILE4_H +#define _ASM_NILE4_H + +#define NILE4_BASE 0xbfa00000 +#define NILE4_SIZE 0x00200000 /* 2 MB */ + + + /* + * Physical Device Address Registers (PDARs) + */ + +#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ +#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ +#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ +#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ +#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ +#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ +#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ +#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ +#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ +#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ +#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ +#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ + /* [R/W] */ +#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ + + + /* + * CPU Interface Registers + */ + +#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ +#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ +#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ +#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ + /* Enable [R/W] */ +#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ +#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ + + + /* + * Memory-Interface Registers + */ + +#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ +#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ +#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ + + + /* + * PCI-Bus Registers + */ + +#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ +#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ +#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ +#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ +#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ + + + /* + * Local-Bus Registers + */ + +#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ +#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ +#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ +#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ +#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ +#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ +#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ +#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ +#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ + /* Enables [R/W] */ +#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ +#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ + + + /* + * DMA Registers + */ + +#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ +#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ +#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ +#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ +#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ +#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ + + + /* + * Timer Registers + */ + +#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ +#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ +#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ +#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ +#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ +#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ +#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ +#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ + + + /* + * PCI Configuration Space Registers + */ + +#define NILE4_PCI_BASE 0x0200 + +#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ +#define NILE4_DID 0x0202 /* PCI Device ID [R] */ +#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ +#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ +#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ +#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ +#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ +#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ +#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ +#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ +#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ +#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ +#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ +#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ + /* (unimplemented) */ +#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ +#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ +#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ + /* (unimplemented) */ +#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ +#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ +#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ +#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ +#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ +#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ +#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ +#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ +#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ +#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ +#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ +#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ + + + /* + * Serial-Port Registers + */ + +#define NILE4_UART_BASE 0x0300 + +#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ +#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ +#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ +#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ +#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ +#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ +#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ +#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ +#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ +#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ +#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ +#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ + +#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ + + + /* + * Interrupt Lines + */ + +#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ +#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ +#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ +#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ +#define NILE4_INT_UART 4 /* UART Interrupt */ +#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ +#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ +#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ +#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ +#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ +#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ +#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ +#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ +#define NILE4_INT_RESV 13 /* Reserved */ +#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ +#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ + + + /* + * Nile 4 Register Access + */ + +static inline void nile4_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void nile4_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u32 nile4_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u16 nile4_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + +static inline void nile4_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(NILE4_BASE+offset) = val; + nile4_sync(); +} + +static inline u8 nile4_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(NILE4_BASE+offset); + nile4_sync(); + return val; +} + + + /* + * Physical Device Address Registers + */ + +extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, + int on_memory_bus, int visible); + + + /* + * PCI Master Registers + */ + +#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ +#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ +#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ +#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ + + + /* + * PCI Address Spaces + * + * Note that these are multiplexed using PCIINIT[01]! + */ + +#define NILE4_PCI_IO_BASE 0xa6000000 +#define NILE4_PCI_MEM_BASE 0xa8000000 +#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE +#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE + + +extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); + + + /* + * Interrupt Programming + */ + +#define NUM_I8259_INTERRUPTS 16 +#define NUM_NILE4_INTERRUPTS 16 + +#define IRQ_I8259_CASCADE NILE4_INT_INTE +#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) +#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) +#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) + +extern void nile4_map_irq(int nile4_irq, int cpu_irq); +extern void nile4_map_irq_all(int cpu_irq); +extern void nile4_enable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq(unsigned int nile4_irq); +extern void nile4_disable_irq_all(void); +extern u16 nile4_get_irq_stat(int cpu_irq); +extern void nile4_enable_irq_output(int cpu_irq); +extern void nile4_disable_irq_output(int cpu_irq); +extern void nile4_set_pci_irq_polarity(int pci_irq, int high); +extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); +extern void nile4_clear_irq(int nile4_irq); +extern void nile4_clear_irq_mask(u32 mask); +extern u8 nile4_i8259_iack(void); +extern void nile4_dump_irq_status(void); /* Debug */ + +#endif + diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 8c08fa904b2c..c2394f8b0fe1 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -25,13 +25,13 @@ extern asmlinkage void handle_ibe(void); extern asmlinkage void handle_dbe(void); -#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) -#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) +#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr))) +#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr))) struct __large_pstruct { unsigned long buf[100]; }; #define __mp(x) (*(struct __large_pstruct *)(x)) -#define __get_dbe(x,ptr,size) \ +#define __get_dbe(x, ptr, size) \ ({ \ long __gu_err; \ __typeof__(*(ptr)) __gu_val; \ @@ -70,7 +70,7 @@ struct __large_pstruct { unsigned long buf[100]; }; extern void __get_dbe_unknown(void); -#define __put_dbe(x,ptr,size) \ +#define __put_dbe(x, ptr, size) \ ({ \ long __pu_err; \ __typeof__(*(ptr)) __pu_val; \ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index b92dd8c760da..d2ea983bec06 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -142,7 +142,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * __pa()/__va() should be used only during mem init. */ -#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) +#ifdef CONFIG_64BIT #define __pa(x) \ ({ \ unsigned long __x = (unsigned long)(x); \ @@ -153,7 +153,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) +#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h index a742e04e82de..f52656826cce 100644 --- a/include/asm-mips/parport.h +++ b/include/asm-mips/parport.h @@ -6,10 +6,10 @@ #ifndef _ASM_PARPORT_H #define _ASM_PARPORT_H -static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) +static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); +static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) { - return parport_pc_find_isa_ports (autoirq, autodma); + return parport_pc_find_isa_ports(autoirq, autodma); } #endif /* _ASM_PARPORT_H */ diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 4fcc185cb2d1..301ff2f28012 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -150,8 +150,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -#ifdef CONFIG_PCI_DOMAINS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) @@ -160,8 +158,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } -#endif /* CONFIG_PCI_DOMAINS */ - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h index 0c45e7598f3f..b84feebf2cef 100644 --- a/include/asm-mips/pci/bridge.h +++ b/include/asm-mips/pci/bridge.h @@ -360,7 +360,7 @@ typedef struct bridge_err_cmdword_s { #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) -#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ +#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 9fb57c035213..81b72122207a 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -95,7 +95,7 @@ static inline void pte_free(struct page *pte) __free_pages(pte, PTE_ORDER); } -#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) +#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) #ifdef CONFIG_32BIT @@ -104,7 +104,7 @@ static inline void pte_free(struct page *pte) * inside the pgd, so has no extra memory associated with it. */ #define pmd_free(x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) +#define __pmd_free_tlb(tlb, x) do { } while (0) #endif @@ -125,7 +125,7 @@ static inline void pmd_free(pmd_t *pmd) free_pages((unsigned long)pmd, PMD_ORDER); } -#define __pmd_free_tlb(tlb,x) pmd_free(x) +#define __pmd_free_tlb(tlb, x) pmd_free(x) #endif diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 2fbd47eba32d..a0947092d0e0 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, */ /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGDIR_SHIFT 21 -#else -#define PGDIR_SHIFT 22 -#endif +#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -55,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, * Entries per page directory level: we use two-level, so * we don't really have any PUD/PMD directory physically. */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGD_ORDER 1 +#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) +#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 1 #define PTE_ORDER 0 -#else -#define PGD_ORDER 0 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 1 -#define PTE_ORDER 0 -#endif #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) @@ -150,7 +140,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 49f5a1a2dfcd..943515f0ef87 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -104,7 +104,7 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) -#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \ +#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ #define MODULE_START CKSSEG @@ -193,7 +193,7 @@ static inline void pud_clear(pud_t *pudp) #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) +#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) static inline unsigned long pud_page_vaddr(pud_t pud) { @@ -237,7 +237,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define __swp_type(x) (((x).val >> 32) & 0xff) #define __swp_offset(x) ((x).val >> 40) -#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) +#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 2e2d70d13ff6..17a7703a2969 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -103,7 +103,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) } } } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { @@ -140,7 +140,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) } #endif } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { @@ -168,11 +168,15 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt #define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) #endif -#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) -#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) -#define PTE_T_LOG2 ffz(~sizeof(pte_t)) +#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) +#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1) +#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; +/* + * We used to declare this array with size but gcc 3.3 and older are not able + * to find that this expression is a constant, so the size is dropped. + */ +extern pgd_t swapper_pg_dir[]; /* * The following only work if pte_present() is true. diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h index 260f3448ccf1..6ad519189ce2 100644 --- a/include/asm-mips/pmon.h +++ b/include/asm-mips/pmon.h @@ -22,7 +22,7 @@ struct callvectors { char* (*gets) (char*); union { int (*smpfork) (unsigned long cp, char *sp); - int (*cpustart) (long, long, long, long); + int (*cpustart) (long, void (*)(void), void *, long); } _s; int (*semlock) (int sem); void (*semunlock) (int sem); diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h index 4aaaff670361..8121a9a75bfd 100644 --- a/include/asm-mips/prctl.h +++ b/include/asm-mips/prctl.h @@ -36,6 +36,6 @@ struct prda { #define t_sys prda_sys -ptrdiff_t prctl (int op, int v1, int v2); +ptrdiff_t prctl(int op, int v1, int v2); #endif diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 1d8b9a8ae324..83bc94534084 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -62,8 +62,9 @@ extern unsigned int vced_count, vcei_count; * This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ - PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) +#define TASK_UNMAPPED_BASE \ + (test_thread_flag(TIF_32BIT_ADDR) ? \ + PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) #endif #define NUM_FPU_REGS 32 @@ -132,22 +133,11 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; -#define MF_FIXADE 1 /* Fix address errors in software */ -#define MF_LOGADE 2 /* Log address errors to syslog */ -#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ -#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ -#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */ - unsigned long mflags; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; struct mips_abi *abi; }; -#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_N32 MF_32BIT_ADDR -#define MF_N64 0 - #ifdef CONFIG_MIPS_MT_FPAFF #define FPAFF_INIT \ .emulated_fp = 0, \ @@ -200,10 +190,6 @@ struct thread_struct { .cp0_baduaddr = 0, \ .error_code = 0, \ .trap_no = 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - .mflags = MF_FIXADE, \ .irix_trampoline = 0, \ .irix_oldctx = 0, \ } diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h index 531caf44560c..487ced4a40de 100644 --- a/include/asm-mips/qemu.h +++ b/include/asm-mips/qemu.h @@ -12,7 +12,7 @@ * Interrupt numbers */ #define Q_PIC_IRQ_BASE 0 -#define Q_COUNT_COMPARE_IRQ 16 +#define Q_COUNT_COMPARE_IRQ 23 /* * Qemu clock rate. Unlike on real MIPS this has no relation to the diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 3c8e3c8d1a9a..2b8466ffd3ca 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -354,7 +354,7 @@ static inline void blast_##pfx##cache##lsize(void) \ \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } \ @@ -367,7 +367,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ __##pfx##flush_prologue \ \ do { \ - cache##lsize##_unroll32(start,hitop); \ + cache##lsize##_unroll32(start, hitop); \ start += lsize * 32; \ } while (start < end); \ \ @@ -388,7 +388,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ for (ws = 0; ws < ws_end; ws += ws_inc) \ for (addr = start; addr < end; addr += lsize * 32) \ - cache##lsize##_unroll32(addr|ws,indexop); \ + cache##lsize##_unroll32(addr|ws, indexop); \ \ __##pfx##flush_epilogue \ } diff --git a/include/asm-mips/seccomp.h b/include/asm-mips/seccomp.h new file mode 100644 index 000000000000..36ed44070256 --- /dev/null +++ b/include/asm-mips/seccomp.h @@ -0,0 +1,37 @@ +#ifndef __ASM_SECCOMP_H + +#include <linux/thread_info.h> +#include <linux/unistd.h> + +#define __NR_seccomp_read __NR_read +#define __NR_seccomp_write __NR_write +#define __NR_seccomp_exit __NR_exit +#define __NR_seccomp_sigreturn __NR_rt_sigreturn + +/* + * Kludge alert: + * + * The generic seccomp code currently allows only a single compat ABI. Until + * this is fixed we priorize O32 as the compat ABI over N32. + */ +#ifdef CONFIG_MIPS32_O32 + +#define TIF_32BIT TIF_32BIT_REGS + +#define __NR_seccomp_read_32 4003 +#define __NR_seccomp_write_32 4004 +#define __NR_seccomp_exit_32 4001 +#define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */ + +#elif defined(CONFIG_MIPS32_N32) + +#define TIF_32BIT _TIF_32BIT_ADDR + +#define __NR_seccomp_read_32 6000 +#define __NR_seccomp_write_32 6001 +#define __NR_seccomp_exit_32 6058 +#define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */ + +#endif /* CONFIG_MIPS32_O32 */ + +#endif /* __ASM_SECCOMP_H */ diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h index 3d6aa7c7ea81..080daa77f867 100644 --- a/include/asm-mips/semaphore.h +++ b/include/asm-mips/semaphore.h @@ -46,23 +46,23 @@ struct semaphore { } #define __DECLARE_SEMAPHORE_GENERIC(name, count) \ - struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) + struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) -static inline void sema_init (struct semaphore *sem, int val) +static inline void sema_init(struct semaphore *sem, int val) { atomic_set(&sem->count, val); init_waitqueue_head(&sem->wait); } -static inline void init_MUTEX (struct semaphore *sem) +static inline void init_MUTEX(struct semaphore *sem) { sema_init(sem, 1); } -static inline void init_MUTEX_LOCKED (struct semaphore *sem) +static inline void init_MUTEX_LOCKED(struct semaphore *sem) { sema_init(sem, 0); } diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 439bce7daa3a..721327f88601 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -13,7 +13,7 @@ #define _ASM_SGIARCS_H #include <asm/types.h> -#include <asm/arc/types.h> +#include <asm/fw/arc/types.h> /* Various ARCS error codes. */ #define PROM_ESUCCESS 0x00 @@ -369,8 +369,8 @@ struct linux_smonblock { #if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) #define __arc_clobbers \ - "$2","$3" /* ... */, "$8","$9","$10","$11", \ - "$12","$13","$14","$15","$16","$24","$25","$31" + "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ + "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31" #define ARC_CALL0(dest) \ ({ long __res; \ @@ -382,11 +382,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec) \ - : __arc_clobbers, "$4","$5","$6","$7"); \ + : __arc_clobbers, "$4", "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ long __vec = (long) romvec->dest; \ @@ -397,11 +397,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1) \ - : __arc_clobbers, "$5","$6","$7"); \ + : __arc_clobbers, "$5", "$6", "$7"); \ (unsigned long) __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -413,11 +413,11 @@ struct linux_smonblock { "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ : "1" (__vec), "r" (__a1), "r" (__a2) \ - : __arc_clobbers, "$6","$7"); \ + : __arc_clobbers, "$6", "$7"); \ __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -434,7 +434,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -453,7 +453,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ @@ -468,8 +468,8 @@ struct linux_smonblock { "daddu\t$29, 32\n\t" \ "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ + : "1" (__vec), \ + "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ "r" (__a5) \ : __arc_clobbers); \ __res; \ @@ -488,7 +488,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL1(dest,a1) \ +#define ARC_CALL1(dest, a1) \ ({ long __res; \ long __a1 = (long) (a1); \ long (*__vec)(long) = (void *) romvec->dest; \ @@ -497,7 +497,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL2(dest,a1,a2) \ +#define ARC_CALL2(dest, a1, a2) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -507,7 +507,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL3(dest,a1,a2,a3) \ +#define ARC_CALL3(dest, a1, a2, a3) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -518,7 +518,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL4(dest,a1,a2,a3,a4) \ +#define ARC_CALL4(dest, a1, a2, a3, a4) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ @@ -530,7 +530,7 @@ struct linux_smonblock { __res; \ }) -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ +#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \ ({ long __res; \ long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h index c0d5206020fd..6109557c14e9 100644 --- a/include/asm-mips/sibyte/bcm1480_int.h +++ b/include/asm-mips/sibyte/bcm1480_int.h @@ -157,7 +157,7 @@ * Mask values for each interrupt */ -#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F)) +#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) @@ -196,7 +196,7 @@ #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) -#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) @@ -269,9 +269,9 @@ */ #define S_BCM1480_INT_HT_INTMSG 0 -#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) -#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) -#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) #define K_BCM1480_INT_HT_INTMSG_FIXED 0 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 @@ -291,14 +291,14 @@ #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE #define S_BCM1480_INT_HT_INTDEST 5 -#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) -#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) -#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) #define S_BCM1480_INT_HT_VECTOR 13 -#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) -#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) -#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) /* * Vector prefix (Table 4-7) diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h index 886b099565e6..fd75817f7ac4 100644 --- a/include/asm-mips/sibyte/bcm1480_l2c.h +++ b/include/asm-mips/sibyte/bcm1480_l2c.h @@ -40,22 +40,22 @@ */ #define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) +#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) +#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) +#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) #define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) +#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) +#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) +#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) #define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) #define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) #define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) +#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) #define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 @@ -68,36 +68,36 @@ */ #define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) +#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) #define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) +#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) +#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) +#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) /* Note that index bit 16 is also tag bit 40 */ #define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) +#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) +#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) +#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) #define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) +#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) +#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) +#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) #define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) +#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) +#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) +#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) #define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) #define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) #define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) +#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) +#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) +#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) /* @@ -105,24 +105,24 @@ */ #define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) -#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) +#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) +#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) #define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) -#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) +#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) +#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) #define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) -#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) +#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) +#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 -#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) +#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) #define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) -#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) +#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) +#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) #define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 #define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) @@ -136,24 +136,24 @@ */ #define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) #define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) #define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) #define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) #define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) -#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) /* @@ -161,16 +161,16 @@ */ #define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) #define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) #define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) -#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) #endif /* _BCM1480_L2C_H */ diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h index a6a437451da4..f26a41a82b59 100644 --- a/include/asm-mips/sibyte/bcm1480_mc.h +++ b/include/asm-mips/sibyte/bcm1480_mc.h @@ -40,27 +40,27 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) #define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) +#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) +#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) #define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) +#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) +#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ @@ -81,131 +81,131 @@ */ #define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) +#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) +#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) +#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) #define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) +#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) +#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) +#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) #define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) +#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) +#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) +#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) #define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) +#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) +#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) +#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) /* * Chip Select End Address Register (Table 83) */ #define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) +#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) +#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) +#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) #define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) +#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) +#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) +#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) #define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) +#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) +#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) +#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) #define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) +#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) +#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) +#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) /* * Row Address Bit Select Register 0 (Table 84) */ #define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) +#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) +#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) +#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) #define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) +#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) +#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) +#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) #define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) +#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) +#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) +#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) #define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) +#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) +#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) +#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) #define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) +#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) +#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) +#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) #define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) +#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) +#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) +#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) #define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) +#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) +#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) +#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) #define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) +#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) +#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) +#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) /* * Row Address Bit Select Register 1 (Table 85) */ #define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) +#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) +#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) +#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) #define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) +#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) +#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) +#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) #define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) +#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) +#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) +#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) #define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) +#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) +#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) +#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) #define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) +#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) +#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) +#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) #define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) +#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) +#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) +#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) #define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) +#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) +#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) +#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) #define K_BCM1480_MC_ROWX_BIT_SPACING 8 @@ -214,80 +214,80 @@ */ #define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) +#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) +#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) +#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) #define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) +#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) +#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) +#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) #define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) +#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) +#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) +#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) #define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) +#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) +#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) +#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) #define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) +#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) +#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) +#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) #define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) +#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) +#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) +#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) #define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) +#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) +#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) +#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) #define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) +#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) +#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) +#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) /* * Column Address Bit Select Register 1 (Table 87) */ #define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) +#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) +#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) +#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) #define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) +#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) +#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) +#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ #define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) +#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) +#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) +#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) #define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) +#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) +#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) +#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) #define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) +#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) +#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) +#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) #define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) +#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) +#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) +#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) #define K_BCM1480_MC_COLX_BIT_SPACING 8 @@ -296,38 +296,38 @@ */ #define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) +#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) +#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) +#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) #define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) +#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) +#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) +#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) #define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) +#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) +#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) +#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) /* * CS2 and CS3 Bank Address Bit Select Register (Table 89) */ #define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) +#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) +#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) +#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) #define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) +#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) +#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) +#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) #define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) +#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) +#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) +#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 @@ -336,9 +336,9 @@ */ #define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) +#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) +#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) +#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) #define K_BCM1480_MC_COMMAND_EMRS 0 #define K_BCM1480_MC_COMMAND_MRS 1 @@ -382,9 +382,9 @@ #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) -#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) +#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) +#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) +#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) @@ -393,21 +393,21 @@ */ #define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) +#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) +#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) #define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) +#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) +#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) #define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) +#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) +#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) +#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 @@ -431,9 +431,9 @@ #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) #define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) +#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) +#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) +#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) #define K_BCM1480_MC_PG_POLICY_CLOSED 0 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 @@ -454,16 +454,16 @@ */ #define S_BCM1480_MC_CLK_RATIO 0 -#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) -#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) +#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) +#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) +#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) #define S_BCM1480_MC_REF_RATE 8 -#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) -#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) -#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) +#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) +#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) +#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) #define K_BCM1480_MC_REF_RATE_100MHz 0x31 #define K_BCM1480_MC_REF_RATE_200MHz 0x62 @@ -519,20 +519,20 @@ #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) #define S_BCM1480_MC_ODT0 0 -#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) -#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) +#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) +#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) #define S_BCM1480_MC_ODT2 8 -#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) -#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) +#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) +#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) #define S_BCM1480_MC_ODT4 16 -#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) -#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) +#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) +#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) #define S_BCM1480_MC_ODT6 24 -#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) -#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) +#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) +#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) #endif /* @@ -540,70 +540,70 @@ */ #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 -#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) -#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) +#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 -#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) -#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) +#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_ADDR_FINE_ADJ 8 -#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) -#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) +#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) +#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) #define S_BCM1480_MC_DQI_COARSE_ADJ 16 -#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) -#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) +#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) +#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQI_FREQ_RANGE 24 -#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) -#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) +#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) +#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQI_FINE_ADJ 24 -#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) -#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) +#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) +#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) #define S_BCM1480_MC_DQO_COARSE_ADJ 32 -#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) -#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) +#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) +#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DQO_FREQ_RANGE 40 -#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) -#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) +#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) +#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DQO_FINE_ADJ 40 -#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) -#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) +#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) +#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_PDSEL 44 -#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) -#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) +#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) +#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) @@ -611,38 +611,38 @@ #endif #define S_BCM1480_MC_DLL_DEFAULT 48 -#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) -#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) +#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) +#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_REGCTRL 54 -#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) -#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) +#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) +#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) #endif #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_FREQ_RANGE 56 -#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) -#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) +#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) +#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) #endif #define S_BCM1480_MC_DLL_STEP_SIZE 56 -#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) -#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) +#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) +#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_BGCTRL 60 -#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) -#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) +#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) +#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) #endif @@ -653,37 +653,37 @@ */ #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 -#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) -#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) +#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) #define S_BCM1480_MC_RTT_BYP_PULLUP 6 -#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) -#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) -#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) +#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) +#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) +#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 -#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 -#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 -#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) +#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 -#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) @@ -703,111 +703,111 @@ */ #define S_BCM1480_MC_DATA_INVERT 0 -#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) +#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) /* * ECC Test ECC Register (Table 96) */ #define S_BCM1480_MC_ECC_INVERT 0 -#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) +#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) /* * SDRAM Timing Register (Table 97) */ #define S_BCM1480_MC_tRCD 0 -#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) -#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) -#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) +#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) +#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) +#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) #define K_BCM1480_MC_tRCD_DEFAULT 3 #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) #define S_BCM1480_MC_tCL 4 -#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) -#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) -#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) +#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) +#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) +#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) #define K_BCM1480_MC_tCL_DEFAULT 2 #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) #define S_BCM1480_MC_tWR 9 -#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) -#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) -#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) +#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) +#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) +#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) #define K_BCM1480_MC_tWR_DEFAULT 2 #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) #define S_BCM1480_MC_tCwD 12 -#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) -#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) -#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) +#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) +#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) +#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) #define K_BCM1480_MC_tCwD_DEFAULT 1 #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) #define S_BCM1480_MC_tRP 16 -#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) -#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) -#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) +#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) +#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) +#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) #define K_BCM1480_MC_tRP_DEFAULT 4 #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) #define S_BCM1480_MC_tRRD 20 -#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) -#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) -#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) +#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) +#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) +#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) #define K_BCM1480_MC_tRRD_DEFAULT 2 #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) #define S_BCM1480_MC_tRCw 24 -#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) -#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) -#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) +#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) +#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) +#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) #define K_BCM1480_MC_tRCw_DEFAULT 10 #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) #define S_BCM1480_MC_tRCr 32 -#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) -#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) -#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) +#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) +#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) +#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) #define K_BCM1480_MC_tRCr_DEFAULT 9 #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tFAW 40 -#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) -#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) -#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) +#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) +#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) +#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) #define K_BCM1480_MC_tFAW_DEFAULT 0 #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) #endif #define S_BCM1480_MC_tRFC 48 -#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) -#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) -#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) +#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) +#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) +#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) #define K_BCM1480_MC_tRFC_DEFAULT 12 #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) #define S_BCM1480_MC_tFIFO 56 -#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) -#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) -#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) +#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) +#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) +#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) #define K_BCM1480_MC_tFIFO_DEFAULT 0 #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) #define S_BCM1480_MC_tW2R 58 -#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) -#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) -#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) +#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) +#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) +#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) #define K_BCM1480_MC_tW2R_DEFAULT 1 #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) #define S_BCM1480_MC_tR2W 60 -#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) -#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) -#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) +#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) +#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) +#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) #define K_BCM1480_MC_tR2W_DEFAULT 0 #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) @@ -835,30 +835,30 @@ #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_tAL 0 -#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) -#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) -#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) +#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) +#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) +#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) #define K_BCM1480_MC_tAL_DEFAULT 0 #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) #define S_BCM1480_MC_tRTP 4 -#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) -#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) -#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) +#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) +#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) +#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) #define K_BCM1480_MC_tRTP_DEFAULT 2 #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) #define S_BCM1480_MC_tW2W 8 -#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) -#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) -#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) +#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) +#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) +#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) #define K_BCM1480_MC_tW2W_DEFAULT 0 #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) #define S_BCM1480_MC_tRAP 12 -#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) -#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) -#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) +#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) +#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) +#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) #define K_BCM1480_MC_tRAP_DEFAULT 0 #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) @@ -875,30 +875,30 @@ */ #define S_BCM1480_MC_BLK_SET_MARK 8 -#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) -#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) -#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) +#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) +#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) +#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) #define S_BCM1480_MC_BLK_CLR_MARK 12 -#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) -#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) -#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) +#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) +#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) +#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) #define S_BCM1480_MC_MAX_AGE 20 -#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) -#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) -#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) +#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) +#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) +#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) #define S_BCM1480_MC_SLEW 33 -#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) -#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) -#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) +#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) +#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) +#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) @@ -907,19 +907,19 @@ */ #define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) #define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) #define S_BCM1480_MC_INTLV_MODE 16 -#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) -#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) -#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) +#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) +#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) +#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 #define K_BCM1480_MC_INTLV_MODE_01 0x1 @@ -938,9 +938,9 @@ */ #define S_BCM1480_MC_ECC_ERR_ADDR 0 -#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) -#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) -#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) +#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) +#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) +#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) @@ -955,27 +955,27 @@ */ #define S_BCM1480_MC_ECC_CORR_ADDR 0 -#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) -#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) -#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) +#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) +#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) +#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) /* * Global ECC Correction Register (Table 103) */ #define S_BCM1480_MC_ECC_CORRECT 0 -#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) -#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) -#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) +#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) +#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) +#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) /* * Global ECC Performance Counters Control Register (Table 104) */ #define S_BCM1480_MC_CHANNEL_SELECT 0 -#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) -#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) -#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) +#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) +#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) +#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index 2738c1366f66..b4077bb72611 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -87,7 +87,7 @@ #define BCM1480_MC_REGISTER_SPACING 0x1000 #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) -#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) +#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) #define R_BCM1480_MC_CONFIG 0x0000000100 #define R_BCM1480_MC_CS_START 0x0000000120 @@ -227,10 +227,15 @@ (A_BCM1480_DUART(chan) + \ BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) +#define DUART_IMRISR_SPACING 0x20 +#define DUART_INCHNG_SPACING 0x10 + #define R_BCM1480_DUART_IMRREG(chan) \ (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) #define R_BCM1480_DUART_ISRREG(chan) \ (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) +#define R_BCM1480_DUART_INCHREG(chan) \ + (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING) #define A_BCM1480_DUART_IMRREG(chan) \ (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) @@ -322,7 +327,7 @@ #define BCM1480_SCD_NUM_WDOGS 4 #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) -#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) +#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 @@ -367,7 +372,7 @@ #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) -#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) +#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) /* Most IMR registers are 128 bits, implemented as non-contiguous 64-bit registers high (_H) and low (_L) */ @@ -408,7 +413,7 @@ #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) -#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) +#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ @@ -422,7 +427,7 @@ #define R_BCM1480_IMR_MAILBOX_SET 0x08 #define R_BCM1480_IMR_MAILBOX_CLR 0x10 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 -#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ +#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ (A_BCM1480_IMR_CPU0_BASE + \ (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ (cpu * BCM1480_IMR_REGISTER_SPACING) + \ @@ -545,7 +550,7 @@ #define BCM1480_HR_REGISTER_SPACING 0x80000 #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) -#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) +#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) #define R_BCM1480_HR_CFG 0x0000000000 @@ -594,9 +599,9 @@ #define BCM1480_PM_NUM_CHANNELS 32 #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) #define BCM1480_PM_INT_PACKING 8 #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 @@ -716,7 +721,7 @@ #define BCM1480_HSP_REGISTER_SPACING 0x80000 #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) -#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) +#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h index 6111d6dcf117..25ef24cbb92a 100644 --- a/include/asm-mips/sibyte/bcm1480_scd.h +++ b/include/asm-mips/sibyte/bcm1480_scd.h @@ -99,22 +99,22 @@ #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -129,16 +129,16 @@ #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) #define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) #define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) @@ -196,9 +196,9 @@ #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) -#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 @@ -244,24 +244,24 @@ */ #define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) +#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) +#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) +#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) #define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) +#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) +#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) +#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) #define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) +#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) +#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) +#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) #define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) +#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) +#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) +#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) /* * System Performance Counter Control Register (Table 32) @@ -281,9 +281,9 @@ */ #define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) @@ -322,13 +322,13 @@ * slightly different. */ -#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -337,9 +337,9 @@ #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) #define K_BCM1480_BUS_AGENT_CPU0 0 @@ -354,9 +354,9 @@ #define K_BCM1480_BUS_AGENT_PM 10 #define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 @@ -382,9 +382,9 @@ #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) /* * Trace Control Register (Table 49) @@ -395,9 +395,9 @@ */ #define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index 73bce901a378..da198a1c8c81 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -41,7 +41,7 @@ #ifdef __ASSEMBLY__ #ifdef LEDS_PHYS -#define setleds(t0,t1,c0,c1,c2,c3) \ +#define setleds(t0, t1, c0, c1, c2, c3) \ li t0, (LEDS_PHYS|0xa0000000); \ li t1, c0; \ sb t1, 0x18(t0); \ @@ -52,7 +52,7 @@ li t1, c3; \ sb t1, 0x00(t0) #else -#define setleds(t0,t1,c0,c1,c2,c3) +#define setleds(t0, t1, c0, c1, c2, c3) #endif /* LEDS_PHYS */ #else diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index a885491217c1..09365f9111fa 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -232,18 +232,18 @@ * Make a mask for 'v' bits at position 'n' */ -#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) +#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) +#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) /* * Make a value at 'v' at bit position 'n' */ -#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) -#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) +#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) +#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n)) -#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) -#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) +#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) +#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) /* * Macros to read/write on-chip registers @@ -252,7 +252,7 @@ #if defined(__mips64) && !defined(__ASSEMBLY__) -#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) +#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) #endif /* __ASSEMBLY__ */ diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index e6145f524fbd..bad56171d747 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -57,9 +57,9 @@ #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) #define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) +#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) +#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) +#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) #define K_DMA_DESC_TYPE_RING_AL 0 #define K_DMA_DESC_TYPE_CHAIN_AL 1 @@ -76,24 +76,24 @@ #define M_DMA_TDX_EN _SB_MAKEMASK1(7) #define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) +#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) +#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) +#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) #define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) +#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) +#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) +#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) +#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) +#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) +#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) +#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) +#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) +#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) @@ -116,37 +116,37 @@ #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) +#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) #define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) +#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) +#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) +#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) -#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) +#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) +#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) +#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) +#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) +#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) +#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) +#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) /* * Ethernet and Serial DMA Descriptor base address (Table 7-6) */ -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) +#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) /* * ASIC Mode Base Address (Table 7-7) */ -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) +#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) /* * DMA Descriptor Count Registers (Table 7-8) @@ -160,9 +160,9 @@ */ #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) +#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) +#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) @@ -173,12 +173,12 @@ */ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) +#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) +#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) +#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) +#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* ********************************************************************* @@ -190,39 +190,39 @@ */ #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) +#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) +#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) +#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) +#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) +#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) +#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) +#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) +#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) -#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) -#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) +#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT) +#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) +#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) +#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) +#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) /* * Descriptor doubleword "B" (Table 7-13) @@ -230,49 +230,49 @@ #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) +#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) +#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) +#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) +#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) +#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) +#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) /* Note: Don't shift the address over, just mask it with the mask below */ #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) +#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) +#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) +#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) +#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) -#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) -#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) -#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) +#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB) +#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB) +#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) +#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) +#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) +#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) /* * from pass2 some bits in dscr_b are also used for rx status */ #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) +#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) +#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) +#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) /* * Ethernet Descriptor Status Bits (Table 7-15) @@ -293,14 +293,14 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) +#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) +#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) +#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) #define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) +#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) +#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) +#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) #define K_DMA_ETHRX_PKTTYPE_IPV4 0 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 @@ -385,21 +385,21 @@ * Register: DM_DSCR_BASE_3 */ -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) +#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) /* Note: Just mask the base address and then OR it in. */ #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) +#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) -#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) -#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) +#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) +#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) +#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) -#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) -#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) +#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) +#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) +#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) #define K_DM_DSCR_BASE_PRIORITY_1 0 #define K_DM_DSCR_BASE_PRIORITY_2 1 @@ -429,12 +429,12 @@ */ #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) +#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) -#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) -#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) -#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ +#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) +#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) +#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ M_DM_CUR_DSCR_DSCR_COUNT) @@ -447,15 +447,15 @@ * Register: DM_PARTIAL_3 */ #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) -#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) -#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) -#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ +#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) +#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) +#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ M_DM_PARTIAL_CRC_PARTIAL) #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) -#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) -#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) -#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ +#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) +#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) +#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ M_DM_PARTIAL_TCPCS_PARTIAL) #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) @@ -469,15 +469,15 @@ * Register: CRC_DEF_1 */ #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ +#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) +#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) +#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ M_CRC_DEF_CRC_INIT) #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ +#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) +#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) +#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ M_CRC_DEF_CRC_POLY) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ @@ -489,21 +489,21 @@ * Register: CTCP_DEF_1 */ #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ +#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) +#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) +#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ M_CTCP_DEF_CRC_TXOR) #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) -#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) -#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ +#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) +#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) +#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ M_CTCP_DEF_TCPCS_INIT) #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ +#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) +#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) +#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ M_CTCP_DEF_CRC_WIDTH) #define K_CTCP_DEF_CRC_WIDTH_4 0 @@ -519,7 +519,7 @@ */ #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) +#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) @@ -529,30 +529,30 @@ #endif /* up to 1250 PASS1 */ #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) +#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) +#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) #define K_DM_DSCRA_DIR_DEST_INCR 0 #define K_DM_DSCRA_DIR_DEST_DECR 1 #define K_DM_DSCRA_DIR_DEST_CONST 2 -#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) +#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) +#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) #define K_DM_DSCRA_DIR_SRC_INCR 0 #define K_DM_DSCRA_DIR_SRC_DECR 1 #define K_DM_DSCRA_DIR_SRC_CONST 2 -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) @@ -576,19 +576,19 @@ #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) +#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) /* * Data Mover Descriptor Doubleword "B" (Table 7-25) */ #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) +#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) -#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) -#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) +#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) +#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) +#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) #endif diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 1b5cbc5c6454..94e9c7c8e783 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -11,7 +11,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -47,7 +47,7 @@ #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) #define S_IO_WIDTH_SEL 2 -#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) +#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) #define K_IO_WIDTH_SEL_1 0 #define K_IO_WIDTH_SEL_2 1 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ @@ -55,8 +55,8 @@ #define K_IO_WIDTH_SEL_1L 2 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define K_IO_WIDTH_SEL_4 3 -#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) -#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) +#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) +#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) #define S_IO_PARITY_ENA 4 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) @@ -71,18 +71,18 @@ #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) #define S_IO_TIMEOUT 8 -#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) -#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) -#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) +#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) +#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) +#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) /* * Generic Bus Region Size register (Table 11-5) */ #define S_IO_MULT_SIZE 0 -#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) -#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) -#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) +#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) +#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) +#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ @@ -91,9 +91,9 @@ */ #define S_IO_START_ADDR 0 -#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) -#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) -#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) +#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) +#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) +#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ @@ -105,9 +105,9 @@ */ #define S_IO_ALE_WIDTH 0 -#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) -#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) -#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) +#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) +#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) +#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -115,27 +115,27 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_ALE_TO_CS 4 -#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) -#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) -#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) +#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) +#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) +#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) +#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) +#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) +#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_CS_WIDTH 8 -#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) -#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) -#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) +#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) +#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) +#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) #define S_IO_RDY_SMPLE 13 -#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) -#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) -#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) +#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) +#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) +#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) /* @@ -143,9 +143,9 @@ */ #define S_IO_ALE_TO_WRITE 0 -#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) -#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) -#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) +#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) +#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) +#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -153,30 +153,30 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_WRITE_WIDTH 4 -#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) -#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) -#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) +#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) +#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) +#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) #define S_IO_IDLE_CYCLE 8 -#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) -#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) -#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) +#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) +#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) +#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) #define S_IO_OE_TO_CS 12 -#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) -#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) -#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) +#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) +#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) +#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) #define S_IO_CS_TO_OE 14 -#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) -#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) -#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) +#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) +#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) +#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) /* * Generic Bus Interrupt Status Register (Table 11-9) */ -#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) +#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) @@ -200,116 +200,116 @@ */ #define S_IO_SLEW0 0 -#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) -#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) -#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) +#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) +#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) +#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) #define S_IO_DRV_A 2 -#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) -#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) -#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) +#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) +#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) +#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) #define S_IO_DRV_B 6 -#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) -#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) -#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) +#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) +#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) +#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) #define S_IO_DRV_C 10 -#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) -#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) -#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) +#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) +#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) +#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) #define S_IO_DRV_D 14 -#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) -#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) -#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) +#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) +#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) +#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) /* * Generic Bus Output Drive Control Register 1 (Table 14-19) */ #define S_IO_DRV_E 2 -#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) -#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) -#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) +#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) +#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) +#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) #define S_IO_DRV_F 6 -#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) -#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) -#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) +#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) +#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) +#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) #define S_IO_SLEW1 8 -#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) -#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) -#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) +#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) +#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) +#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) #define S_IO_DRV_G 10 -#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) -#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) -#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) +#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) +#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) +#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) #define S_IO_SLEW2 12 -#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) -#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) -#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) +#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) +#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) +#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) #define S_IO_DRV_H 14 -#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) -#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) -#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) +#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) +#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) +#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) /* * Generic Bus Output Drive Control Register 2 (Table 14-20) */ #define S_IO_DRV_J 2 -#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) -#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) -#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) +#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) +#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) +#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) #define S_IO_DRV_K 6 -#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) -#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) -#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) +#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) +#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) +#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) #define S_IO_DRV_L 10 -#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) -#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) -#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) +#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) +#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) +#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) #define S_IO_DRV_M 14 -#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) -#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) -#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) +#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) +#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) +#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) /* * Generic Bus Output Drive Control Register 3 (Table 14-21) */ #define S_IO_SLEW3 0 -#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) -#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) -#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) +#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) +#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) +#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) #define S_IO_DRV_N 2 -#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) -#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) -#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) +#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) +#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) +#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) #define S_IO_DRV_P 6 -#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) -#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) -#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) +#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) +#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) +#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) #define S_IO_DRV_Q 10 -#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) -#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) -#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) +#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) +#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) +#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) #define S_IO_DRV_R 14 -#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) -#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) -#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) +#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) +#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) +#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) /* @@ -329,9 +329,9 @@ #if SIBYTE_HDR_FEATURE_CHIP(1480) #define S_PCMCIA_MODE 16 -#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) -#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) -#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) +#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) +#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) +#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ @@ -369,49 +369,49 @@ #define K_GPIO_INTR_SPLIT 3 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) +#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) +#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) +#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) #define S_GPIO_INTR_TYPE0 0 -#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) -#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) -#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) +#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) +#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) +#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) #define S_GPIO_INTR_TYPE2 2 -#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) -#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) -#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) +#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) +#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) +#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) #define S_GPIO_INTR_TYPE4 4 -#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) -#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) -#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) +#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) +#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) +#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) #define S_GPIO_INTR_TYPE6 6 -#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) -#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) -#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) +#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) +#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) +#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) #define S_GPIO_INTR_TYPE8 8 -#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) -#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) -#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) +#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) +#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) +#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) #define S_GPIO_INTR_TYPE10 10 -#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) -#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) -#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) +#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) +#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) +#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) #define S_GPIO_INTR_TYPE12 12 -#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) -#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) -#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) +#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) +#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) +#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) #define S_GPIO_INTR_TYPE14 14 -#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) -#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) -#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) +#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) +#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) +#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) #if SIBYTE_HDR_FEATURE_CHIP(1480) @@ -425,49 +425,49 @@ #define K_GPIO_INTR_UNPRED2 3 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) -#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) -#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) +#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) +#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) +#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) #define S_GPIO_INTR_ATYPE0 0 -#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) -#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) -#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) +#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) +#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) +#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) #define S_GPIO_INTR_ATYPE2 2 -#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) -#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) -#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) +#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) +#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) +#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) #define S_GPIO_INTR_ATYPE4 4 -#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) -#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) -#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) +#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) +#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) +#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) #define S_GPIO_INTR_ATYPE6 6 -#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) -#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) -#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) +#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) +#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) +#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) #define S_GPIO_INTR_ATYPE8 8 -#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) -#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) -#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) +#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) +#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) +#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) #define S_GPIO_INTR_ATYPE10 10 -#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) -#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) -#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) +#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) +#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) +#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) #define S_GPIO_INTR_ATYPE12 12 -#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) -#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) -#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) +#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) +#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) +#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) #define S_GPIO_INTR_ATYPE14 14 -#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) -#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) -#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) +#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) +#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) +#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) #endif diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index 94e8299b0a2a..f2850b4bcfd4 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -150,7 +150,7 @@ #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0) +#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) @@ -208,9 +208,9 @@ */ #define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) +#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) +#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) +#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) #define K_INT_LDT_INTMSG_FIXED 0 #define K_INT_LDT_INTMSG_ARBITRATED 1 @@ -228,14 +228,14 @@ #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) #define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) +#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) +#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) +#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) #define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) +#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) +#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) +#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) /* * Vector format (Table 4-6) diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 842f205094af..6554dcf05cfe 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -40,27 +40,27 @@ */ #define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) +#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) #define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) +#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) +#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) +#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) #define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) +#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) +#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) +#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) #define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) +#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) +#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) +#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) #define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) +#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) +#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) +#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) #define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) #define M_L2C_TAG_VALID _SB_MAKEMASK1(49) @@ -70,32 +70,32 @@ */ #define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) +#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) +#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) +#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) #define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) +#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) +#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) +#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) #define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) +#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) #define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) +#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) +#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) +#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) #define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) +#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) +#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) +#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) #define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) +#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) +#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) +#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) #define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) #define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) @@ -111,9 +111,9 @@ * L2 Read Misc. register (A_L2_READ_MISC) */ #define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) +#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) +#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) +#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) #define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) #define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index 7092535d1108..081e8b1c4ad0 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -81,14 +81,14 @@ */ #define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) +#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) +#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) +#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) #define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) +#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) +#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) +#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) /* @@ -111,14 +111,14 @@ */ #define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) +#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) +#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) +#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) #define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) +#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) +#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) +#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) #define K_LDT_REV 0x01 #define K_LDT_CLASS 0x060000 @@ -128,26 +128,26 @@ */ #define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) +#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) +#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) +#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) #define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) +#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) +#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) +#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) #define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) +#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) +#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) +#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) #define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 #define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) +#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) +#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) +#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) @@ -170,9 +170,9 @@ #define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) #define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) +#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) +#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) +#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) #define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) #define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) @@ -208,9 +208,9 @@ #define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) #define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) +#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) +#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) +#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) /* * LDT link control register (Table 8-18), and (Table 8-19) @@ -225,35 +225,35 @@ #define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) #define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) +#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) +#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) +#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) #define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) +#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) +#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) +#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) #define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) #define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) +#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) +#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) +#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) #define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) #define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) +#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) +#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) +#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) #define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) #define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) +#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) +#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) +#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) @@ -262,9 +262,9 @@ */ #define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) +#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) +#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) +#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) #define K_LDT_LINKFREQ_200MHZ 0 #define K_LDT_LINKFREQ_300MHZ 1 @@ -293,16 +293,16 @@ #define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) +#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) +#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) +#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) #define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) #define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) +#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) +#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) +#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) @@ -340,73 +340,73 @@ */ #define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) +#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) +#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) +#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) #define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) +#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) +#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) +#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) #define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) +#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) +#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) +#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) #define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) +#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) +#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) +#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) #define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) +#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) +#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) +#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) #define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) +#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) +#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) +#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) #define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) +#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) +#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) +#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) /* * LDT SRI Transmit Buffer Count register (Table 8-26) */ #define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) +#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) +#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) +#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) #define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) +#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) +#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) +#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) #define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) +#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) +#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) +#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) #define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) +#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) +#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) +#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) #define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) +#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) +#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) +#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) #define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) +#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) +#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) +#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* @@ -414,9 +414,9 @@ */ #define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) +#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) +#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) +#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) #endif /* 1250 PASS2 || 112x PASS1 */ #endif diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 833c8b59d687..b6faf08ca81d 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -55,8 +55,8 @@ #define M_MAC_BURST_EN _SB_MAKEMASK1(5) #define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) +#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) +#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) #define K_MAC_TX_PAUSE_CNT_512 0 #define K_MAC_TX_PAUSE_CNT_1K 1 @@ -76,7 +76,7 @@ #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) -#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) +#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) @@ -91,15 +91,15 @@ #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) -#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) +#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) #define M_MAC_HDX_EN _SB_MAKEMASK1(33) #define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) -#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) -#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) +#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) +#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) +#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) #define K_MAC_SPEED_SEL_10MBPS 0 #define K_MAC_SPEED_SEL_100MBPS 1 @@ -117,9 +117,9 @@ #define M_MAC_SS_EN _SB_MAKEMASK1(39) #define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) +#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) +#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) +#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) #define K_MAC_BYPASS_GMII 0 #define K_MAC_BYPASS_ENCODED 1 @@ -138,9 +138,9 @@ #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) -#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) -#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) +#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) +#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) +#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) #define K_MAC_FC_CMD_DISABLED 0 #define K_MAC_FC_CMD_ENABLED 1 @@ -153,14 +153,14 @@ #define M_MAC_FC_SEL _SB_MAKEMASK1(54) #define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) +#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) +#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) +#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) #define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) +#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) +#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) +#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) /* @@ -202,14 +202,14 @@ */ #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) -#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) +#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) +#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) +#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) -#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) +#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) +#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) +#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) /* * MAC Fifo Threshhold registers (Table 9-14) @@ -221,50 +221,50 @@ #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ +/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) +#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) +#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) +#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ +/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) +#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) +#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) +#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) +#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) +#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) +#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) +#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) +#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) +#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) +#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) +#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) +#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) +#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) +#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) +#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) +#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) +#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) +#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* @@ -276,51 +276,51 @@ /* XXXCGD: ??? Unused in pass2? */ #define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) +#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) +#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) +#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) +#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) +#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) +#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) +#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) +#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) +#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) #define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) +#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) +#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) +#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) +#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) +#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) +#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) #define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) +#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) +#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) +#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) #define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) +#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) +#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) +#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) +#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) +#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) +#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) +#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) +#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) +#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) /* * These constants are used to configure the fields within the Frame @@ -377,20 +377,20 @@ */ #define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) +#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) +#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) +#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) +#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) +#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) +#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) +#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) +#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) +#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) #endif /* 1250 PASS3 || 112x PASS1 */ @@ -425,7 +425,7 @@ * is that you'll use one of the "S_" things above * and pass just the six bits to a DMA-channel-specific ISR */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) +#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) @@ -440,19 +440,19 @@ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see * also DMA_TX/DMA_RX in sb_regs.h). */ -#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) +#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) -#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) +#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) @@ -467,9 +467,9 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) +#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) +#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) +#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) @@ -483,24 +483,24 @@ */ #define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) +#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) +#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) +#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) +#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) #define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) +#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) +#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) +#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) #define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) +#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) +#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) +#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) /* * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] @@ -510,14 +510,14 @@ */ #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) +#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) +#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) +#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) +#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) +#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) +#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) /* * MAC Recieve Address Filter Exact Match Registers (Table 9-21) @@ -565,24 +565,24 @@ #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) #define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) +#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) +#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) +#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) #define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) +#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) +#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) +#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) #define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) +#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) +#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) +#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) #define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) +#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) +#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) +#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) /* * MAC Receive Address Filter Control Registers (Table 9-24) @@ -603,28 +603,28 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) -#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) -#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) +#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) +#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) +#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) -#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) -#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) +#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) +#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) +#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) -#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) -#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) +#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) +#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) +#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) -#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) -#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) +#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) +#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) +#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 4fe848ffbc31..1eb1b5a88736 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -10,7 +10,7 @@ * ********************************************************************* * - * Copyright 2000,2001,2002,2003 + * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or @@ -40,73 +40,73 @@ */ #define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) +#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) #define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) +#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) +#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) +#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) #define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) +#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) +#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) +#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) #define K_MC_BANK0_MAP_DEFAULT 0x00 #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) #define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) +#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) +#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) +#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) #define K_MC_BANK1_MAP_DEFAULT 0x08 #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) #define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) +#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) +#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) +#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) #define K_MC_BANK2_MAP_DEFAULT 0x09 #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) #define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) +#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) +#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) +#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) #define K_MC_BANK3_MAP_DEFAULT 0x0C #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) -#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) +#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) #define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) +#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) +#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) +#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) #define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) +#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) +#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) +#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) #define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) +#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) +#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) +#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) -#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) +#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) #define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) +#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) +#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) +#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) #define K_MC_CS_MODE_MSB_CS 0 #define K_MC_CS_MODE_INTLV_CS 15 @@ -138,9 +138,9 @@ */ #define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) +#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) +#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) +#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) #define K_MC_CLK_RATIO_2X 4 #define K_MC_CLK_RATIO_25X 5 @@ -158,9 +158,9 @@ #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X #define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) +#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) +#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) +#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 @@ -172,21 +172,21 @@ #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz #define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) +#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) +#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) +#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) #define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) +#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) +#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) +#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) #define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) +#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) +#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) +#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) @@ -196,27 +196,27 @@ #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) #define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) +#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) +#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) +#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) #define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) +#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) +#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) +#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) #define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) +#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) +#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) +#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) #define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) +#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) +#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) +#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ @@ -235,9 +235,9 @@ */ #define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) +#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) +#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) +#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) #define K_MC_COMMAND_EMRS 0 #define K_MC_COMMAND_MRS 1 @@ -267,21 +267,21 @@ */ #define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) +#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) +#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) +#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) #define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) +#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) +#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) +#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) #define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) +#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) +#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) +#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) #define K_MC_DRAM_TYPE_JEDEC 0 #define K_MC_DRAM_TYPE_FCRAM 1 @@ -309,16 +309,16 @@ #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) #define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) +#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) +#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) +#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) #define K_MC_tFIFO_DEFAULT 1 #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) #define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) +#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) +#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) +#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) #define K_MC_tRFC_DEFAULT 12 #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) @@ -327,44 +327,44 @@ #endif #define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) +#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) +#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) +#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) #define K_MC_tCwCr_DEFAULT 4 #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) #define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) +#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) +#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) +#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) #define K_MC_tRCr_DEFAULT 9 #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) #define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) +#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) +#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) +#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) #define K_MC_tRCw_DEFAULT 10 #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) #define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) +#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) +#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) +#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) #define K_MC_tRRD_DEFAULT 2 #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) #define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) +#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) +#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) +#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) #define K_MC_tRP_DEFAULT 4 #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) #define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) +#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) +#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) +#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) #define K_MC_tCwD_DEFAULT 1 #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) @@ -372,16 +372,16 @@ #define M_MC_tCrDh M_tCrDh #define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) +#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) +#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) +#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) #define K_MC_tCrD_DEFAULT 2 #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) #define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) +#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) +#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) +#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) #define K_MC_tRCD_DEFAULT 3 #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) @@ -409,76 +409,76 @@ */ #define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) +#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) +#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) +#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) #define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) +#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) +#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) +#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) #define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) +#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) +#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) +#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) #define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) +#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) +#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) +#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) /* * Chip Select End Address Register (Table 6-18) */ #define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) +#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) +#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) +#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) #define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) +#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) +#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) +#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) #define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) +#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) +#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) +#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) #define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) +#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) +#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) +#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) /* * Chip Select Interleave Register (Table 6-19) */ #define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) +#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) #define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) +#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) +#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) #define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) +#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) /* * Row Address Bits Register (Table 6-20) */ #define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) +#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) #define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) +#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) +#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) #define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) +#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) /* @@ -486,14 +486,14 @@ */ #define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) +#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) #define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) +#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) +#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) #define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) +#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) /* @@ -501,14 +501,14 @@ */ #define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) +#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) #define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) +#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) +#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) #define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) +#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) /* * Chip Select Attribute Register (Table 6-23) @@ -520,31 +520,31 @@ #define K_MC_CS_ATTR_OPEN 3 #define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) +#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) +#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) +#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) #define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) +#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) +#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) +#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) #define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) +#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) +#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) +#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) #define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) +#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) +#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) +#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) /* * ECC Test ECC Register (Table 6-25) */ #define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) +#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) #endif diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 220b7e94f1bf..8f53ec817a5e 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -66,7 +66,7 @@ #define MC_REGISTER_SPACING 0x1000 #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) -#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) +#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) #define R_MC_CONFIG 0x0000000100 #define R_MC_DRAMCMD 0x0000000120 @@ -173,23 +173,23 @@ #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ -#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ +#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ ((A_MAC_CHANNEL_BASE(macnum)) + \ R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ +#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ (R_MAC_DMA_CHANNELS + \ (MAC_DMA_TXRX_SPACING*(txrx)) + \ (MAC_DMA_CHANNEL_SPACING*(chan))) -#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ +#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ + (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ (reg)) -#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ +#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ + (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ (reg)) /* @@ -415,8 +415,8 @@ R_SER_DMA_CHANNELS + \ (SER_DMA_TXRX_SPACING*(txrx))) -#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ +#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ + (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ (reg)) @@ -499,7 +499,7 @@ #define IO_EXT_REGISTER_SPACING 8 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) -#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) +#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) #define R_IO_EXT_CFG 0x0000 #define R_IO_EXT_MULT_SIZE 0x0100 @@ -587,7 +587,7 @@ #define A_SMB_1 0x0010060008 #define SMB_REGISTER_SPACING 0x8 #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) -#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) +#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) #define R_SMB_XTRA 0x0000000000 #define R_SMB_FREQ 0x0000000010 @@ -611,7 +611,7 @@ #define SCD_WDOG_SPACING 0x100 #define SCD_NUM_WDOGS 2 #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) -#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) +#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) #define R_SCD_WDOG_INIT 0x0000000000 #define R_SCD_WDOG_CNT 0x0000000008 @@ -635,7 +635,7 @@ #define A_SCD_TIMER_3 0x0010020178 #define SCD_NUM_TIMERS 4 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) -#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) +#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) #define R_SCD_TIMER_INIT 0x0000000000 #define R_SCD_TIMER_CNT 0x0000000010 @@ -714,7 +714,7 @@ #define IMR_REGISTER_SPACING_SHIFT 13 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) -#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) +#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) #define R_IMR_INTERRUPT_DIAG 0x0010 #define R_IMR_INTERRUPT_LDT 0x0018 @@ -821,7 +821,7 @@ #define DM_REGISTER_SPACING 0x20 #define DM_NUM_CHANNELS 4 #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) -#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) +#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) #define R_DM_DSCR_BASE 0x0000000000 #define R_DM_DSCR_COUNT 0x0000000008 @@ -843,7 +843,7 @@ #define DM_CRC_REGISTER_SPACING 0x10 #define DM_CRC_NUM_CHANNELS 2 #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) -#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) +#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) #define R_CRC_DEF_0 0x00 #define R_CTCP_DEF_0 0x08 diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 9ea3da367ab6..e49c3e89b5ee 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -42,12 +42,12 @@ * System Revision Register (Table 4-1) */ -#define M_SYS_RESERVED _SB_MAKEMASK(8,0) +#define M_SYS_RESERVED _SB_MAKEMASK(8, 0) #define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) +#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) +#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) +#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) #define K_SYS_REVISION_BCM1250_PASS1 0x01 @@ -94,9 +94,9 @@ /*Cache size - 23:20 of revision register*/ #define S_SYS_L2C_SIZE _SB_MAKE64(20) -#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) -#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) -#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) +#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) +#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) +#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) #define K_SYS_L2C_SIZE_1MB 0 #define K_SYS_L2C_SIZE_512KB 5 @@ -110,16 +110,16 @@ /* Number of CPU cores, bits 27:24 of revision register*/ #define S_SYS_NUM_CPUS _SB_MAKE64(24) -#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) -#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) -#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) +#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) +#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) +#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) /* XXX: discourage people from using these constants. */ #define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) +#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) +#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) +#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) /* XXX: discourage people from using these constants. */ #define K_SYS_PART_SB1250 0x1250 @@ -131,9 +131,9 @@ /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ #define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) +#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) +#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) +#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) #define K_SYS_SOC_TYPE_BCM1250 0x0 #define K_SYS_SOC_TYPE_BCM1120 0x1 @@ -170,9 +170,9 @@ #endif #define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) +#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) +#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) +#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) /* * System Manufacturing Register @@ -182,36 +182,36 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) +#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) +#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) +#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) #define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) -#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) -#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) +#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) +#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) +#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) +#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) +#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) +#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) +#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) +#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) +#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) #define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) +#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) +#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) +#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) #define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) +#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) +#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) +#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) #endif @@ -227,9 +227,9 @@ #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) #define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) +#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) +#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) +#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) @@ -238,9 +238,9 @@ #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) #define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) +#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) +#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) +#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) #define K_SYS_BOOT_MODE_ROM32 0 #define K_SYS_BOOT_MODE_ROM8 1 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 @@ -255,9 +255,9 @@ #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) #define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) +#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) +#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) +#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) /* The following bits are writeable by JTAG only. */ @@ -265,20 +265,20 @@ #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) #define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) +#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) +#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) +#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) #define S_SYS_PLL_IREF 43 -#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) +#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) #define S_SYS_PLL_VCO 45 -#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) +#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) #define S_SYS_PLL_VREG 47 -#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) +#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) @@ -314,13 +314,13 @@ */ #define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) +#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) #define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) +#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) #define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) +#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) #define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) +#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) /* * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) @@ -330,18 +330,18 @@ #define V_SCD_WDOG_FREQ 1000000 #define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) +#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) #define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) +#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) #define S_SCD_WDOG_ENABLE 0 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) #define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) -#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) -#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) +#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) +#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) +#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ #define K_SCD_WDOG_RESET_SOFT 1 @@ -363,15 +363,15 @@ #define V_SCD_TIMER_FREQ 1000000 #define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) +#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) +#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) +#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) #define V_SCD_TIMER_WIDTH 23 #define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) +#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) +#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) +#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) @@ -382,24 +382,24 @@ */ #define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) +#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) +#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) +#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) #define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) +#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) +#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) +#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) #define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) +#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) +#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) +#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) #define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) +#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) +#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) +#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) #if SIBYTE_HDR_FEATURE_1250_112x #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) @@ -412,57 +412,57 @@ */ #define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) +#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) +#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) +#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) #define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) +#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) +#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) +#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) #define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) +#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) +#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) +#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) #define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) +#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) +#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) +#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) #define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) +#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) +#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) +#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) #define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) +#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) +#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) +#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) #define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) +#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) +#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) +#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) #define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) +#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) +#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) +#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) #define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) +#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) +#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) +#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) #define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) +#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) +#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) +#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) /* @@ -470,13 +470,13 @@ */ #if SIBYTE_HDR_FEATURE_1250_112x -#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) +#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) +#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) #define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) +#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) +#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) +#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) @@ -485,9 +485,9 @@ #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) #define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) +#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) +#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) +#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) #define K_BUS_AGENT_CPU0 0 #define K_BUS_AGENT_CPU1 1 @@ -498,9 +498,9 @@ #define K_BUS_AGENT_MC 7 #define S_ATRAP_CFG_CATTR 12 -#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) -#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) -#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) +#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) +#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) +#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) #define K_ATRAP_CFG_CATTR_IGNORE 0 #define K_ATRAP_CFG_CATTR_UNC 1 @@ -541,18 +541,18 @@ #endif /* 1480 */ #endif /* 1250/112x */ -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) +#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) +#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) +#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) /* * Trace Event registers */ #define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) +#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) +#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) +#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) @@ -563,48 +563,48 @@ #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) #define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) +#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) +#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) +#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) #define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) +#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) +#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) +#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) #define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) +#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) +#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) +#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) #define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) +#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) +#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) +#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) /* * Trace Sequence registers */ #define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) +#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) +#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) +#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) #define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) +#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) +#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) +#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) #define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) +#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) +#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) +#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) #define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) +#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) +#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) +#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) #define K_SCD_TRSEQ_E0 0 #define K_SCD_TRSEQ_E1 1 @@ -629,9 +629,9 @@ V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) #define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) +#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) +#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) +#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) #define K_SCD_TRSEQ_FUNC_NOP 0 #define K_SCD_TRSEQ_FUNC_START 1 diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 279a912213cd..04769923cf1e 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -41,16 +41,16 @@ */ #define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) +#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) +#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) #define K_SMB_FREQ_400KHZ 0x1F #define K_SMB_FREQ_100KHZ 0x7D #define K_SMB_FREQ_10KHZ 1250 #define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) +#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) +#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) /* * SMBus control register (Table 14-4) @@ -61,7 +61,7 @@ #define S_SMB_DATA_OUT 4 #define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) -#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) +#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR @@ -79,35 +79,35 @@ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_SCL_IN 5 #define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) -#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) -#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) +#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) +#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ #define S_SMB_REF 6 #define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) -#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) -#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) +#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) +#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) #define S_SMB_DATA_IN 7 #define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) -#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) -#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) +#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) +#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) /* * SMBus Start/Command registers (Table 14-9) */ #define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) +#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) +#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) +#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) #define M_SMB_QDATA _SB_MAKEMASK1(7) #define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) +#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) +#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) +#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) #define K_SMB_TT_WR1BYTE 0 #define K_SMB_TT_WR2BYTE 1 @@ -134,12 +134,12 @@ */ #define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) +#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) +#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) #define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) +#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) +#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) /* @@ -147,22 +147,22 @@ */ #define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) +#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) +#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) +#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) +#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) #define M_SMB_EXTEND _SB_MAKEMASK1(14) #define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) +#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) +#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) +#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) #define K_SMB_DFMT_1BYTE 0 #define K_SMB_DFMT_2BYTE 1 @@ -183,9 +183,9 @@ #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) #define S_SMB_AFMT 11 -#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) -#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) -#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) +#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) +#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) +#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) #define K_SMB_AFMT_NONE 0 #define K_SMB_AFMT_ADDR 1 diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index dd154ac505d8..d4b8558e0bf1 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -43,8 +43,8 @@ #define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) #define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) +#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) +#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) #define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) #define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) @@ -59,8 +59,8 @@ #define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) #define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) +#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) +#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) #define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) #define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) @@ -72,8 +72,8 @@ #define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) #define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) +#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) +#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) #define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) #define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) @@ -137,8 +137,8 @@ #define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) #define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) +#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) +#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) #define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) #define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index cf74fedcbef1..d835bf280140 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -46,8 +46,8 @@ */ #define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) -#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) +#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) +#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) #define K_DUART_BITS_PER_CHAR_RSV0 0 #define K_DUART_BITS_PER_CHAR_RSV1 1 @@ -64,8 +64,8 @@ #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) #define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) +#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) +#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) #define K_DUART_PARITY_MODE_ADD 0 #define K_DUART_PARITY_MODE_ADD_FIXED 1 @@ -89,7 +89,7 @@ * Register: DUART_MODE_REG_2_B */ -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ +#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) #define M_DUART_STOP_BIT_LEN_1 0 @@ -100,8 +100,8 @@ #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ #define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) -#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) +#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) +#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) #define K_DUART_CHAN_MODE_NORMAL 0 #define K_DUART_CHAN_MODE_LCL_LOOP 2 @@ -123,8 +123,8 @@ #define M_DUART_TX_DIS _SB_MAKEMASK1(3) #define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) +#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) +#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) #define K_DUART_MISC_CMD_NOACTION0 0 #define K_DUART_MISC_CMD_NOACTION1 1 @@ -168,7 +168,7 @@ * Register: DUART_CLK_SEL_B */ -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) +#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) /* @@ -179,8 +179,8 @@ * Register: DUART_TX_HOLD_B */ -#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) +#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) +#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) /* * DUART Input Port Register (Table 10-10) @@ -202,10 +202,10 @@ */ #define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) +#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) #define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) +#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) /* @@ -217,7 +217,7 @@ #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ +#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ /* * DUART Aux Control Register (Table 10-15) @@ -228,7 +228,7 @@ #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) @@ -242,18 +242,18 @@ #define S_DUART_ISR_RX_A 1 #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) -#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) -#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) +#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) +#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Status Register (Table 10-17) @@ -266,8 +266,8 @@ #define M_DUART_ISR_RX _SB_MAKEMASK1(1) #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) #define M_DUART_ISR_IN _SB_MAKEMASK1(3) -#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Interrupt Mask Register (Table 10-19) @@ -278,13 +278,13 @@ #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) +#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Mask Register (Table 10-20) @@ -297,8 +297,8 @@ #define M_DUART_IMR_RX _SB_MAKEMASK1(1) #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) #define M_DUART_IMR_IN _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) +#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) /* @@ -310,7 +310,7 @@ #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port Clear Register (Table 10-23) @@ -321,7 +321,7 @@ #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port RTS Register (Table 10-24) @@ -332,7 +332,7 @@ #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) +#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_OUT_PIN_SET(chan) \ (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) @@ -345,14 +345,14 @@ */ #define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) +#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) +#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) +#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) #define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) +#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) +#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) +#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 2e32949bd674..96e28f18dad1 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -106,8 +106,8 @@ typedef struct siginfo { #undef SI_TIMER #undef SI_MESGQ #define SI_ASYNCIO -2 /* sent by AIO completion */ -#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ -#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */ +#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */ +#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */ #ifdef __KERNEL__ diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 67c4fe52bb42..0cd719fabb51 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -18,7 +18,7 @@ #ifdef CONFIG_32BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ @@ -46,7 +46,7 @@ __asm__ ( \ #ifdef CONFIG_64BIT #define save_static_function(symbol) \ -__asm__ ( \ +__asm__( \ ".text\n\t" \ ".globl\t" #symbol "\n\t" \ ".align\t2\n\t" \ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 13aef6af422c..dc770025a9b0 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -60,6 +60,15 @@ extern cpumask_t phys_cpu_present_map; */ extern void core_send_ipi(int cpu, unsigned int action); +static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + core_send_ipi(i, action); +} + + /* * Firmware CPU startup hook */ diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index 44dfa4adecf3..ff3e8936b493 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h @@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t); #define PARKED_INDEX ((unsigned int)0x80000000) +/* + * Define low-level interrupt mask for IPIs, if necessary. + * By default, use SW interrupt 1, which requires no external + * hardware support, but which works only for single-core + * MIPS MT systems. + */ +#ifndef MIPS_CPU_IPI_IRQ +#define MIPS_CPU_IPI_IRQ 1 +#endif + #endif /* _ASM_SMTC_MT_H */ diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h index a52a4a7a36e0..e09131a6127d 100644 --- a/include/asm-mips/smtc_ipi.h +++ b/include/asm-mips/smtc_ipi.h @@ -34,6 +34,7 @@ struct smtc_ipi { #define LINUX_SMP_IPI 1 #define SMTC_CLOCK_TICK 2 +#define IRQ_AFFINITY_IPI 3 /* * A queue of IPI messages diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 8fa0af6b68d2..fec9bdd34913 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -50,7 +50,7 @@ #define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) #define CHANGE_ADDR_NASID(_pa, _nasid) \ - ((UINT64_CAST (_pa) & ~NASID_MASK) | \ + ((UINT64_CAST(_pa) & ~NASID_MASK) | \ (UINT64_CAST(_nasid) << NASID_SHFT)) @@ -75,7 +75,7 @@ #define RAW_NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) @@ -192,31 +192,31 @@ #define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x200) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4 + \ 0x208) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x1f << 4) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 0x1f << 4) #define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE * 3 / 4) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ (_rgn) << 3) -#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) -#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) -#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))) +#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn))) +#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val)) +#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))) #define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ NODE_ADDRSPACE_SIZE / 2) | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ - UINT64_CAST (_pa) >> 3 & 3) + UINT64_CAST(_pa) & NASID_MASK | \ + UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \ + UINT64_CAST(_pa) >> 3 & 3) /* * Macro to convert a back door directory or protection address into the @@ -225,16 +225,16 @@ #define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) #define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 0x1f << 4) << 3) +#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 0x1f << 4) << 3) -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) +#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2) -#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ - (UINT64_CAST (_ba) & 3) << 3) +#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ + (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \ + (UINT64_CAST(_ba) & 3) << 3) #endif /* CONFIG_SGI_IP27 */ @@ -282,7 +282,7 @@ * the base of the register space. */ #define HUB_REG_PTR(_base, _off) \ - (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) + (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) #define HUB_REG_PTR_L(_base, _off) \ HUB_L(HUB_REG_PTR((_base), (_off))) diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h index da523de628be..bd75945e10ff 100644 --- a/include/asm-mips/sn/arch.h +++ b/include/asm-mips/sn/arch.h @@ -19,8 +19,8 @@ typedef u64 hubreg_t; -#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) -#define cputoslice(cpu) (cpu_data[(cpu)].p_slice) +#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid) +#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice) #define makespnum(_nasid, _slice) \ (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h index ab2fa8cd2627..24c6775fbb0f 100644 --- a/include/asm-mips/sn/io.h +++ b/include/asm-mips/sn/io.h @@ -9,7 +9,7 @@ #ifndef _ASM_SN_IO_H #define _ASM_SN_IO_H -#if defined (CONFIG_SGI_IP27) +#if defined(CONFIG_SGI_IP27) #include <asm/sn/sn0/hubio.h> #endif diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 82aeb9e322db..96cfd2ab1bcd 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -51,8 +51,8 @@ #if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) #include <asm/sn/agent.h> -#include <asm/arc/types.h> -#include <asm/arc/hinv.h> +#include <asm/fw/arc/types.h> +#include <asm/fw/arc/hinv.h> #if defined(CONFIG_SGI_IP35) // The hack file has to be before vector and after sn0_fru.... #include <asm/hack.h> @@ -405,7 +405,7 @@ typedef struct kl_config_hdr { #define KLTYPE(_x) ((_x) & KLTYPE_MASK) #define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ (l->brd_flags & SECOND_NIC_PRESENT)) -#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2)) +#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2)) /* * board structures diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h index 0573cbffc104..1327e12e9645 100644 --- a/include/asm-mips/sn/kldir.h +++ b/include/asm-mips/sn/kldir.h @@ -140,7 +140,7 @@ */ #define SYMMON_STACK_SIZE 0x8000 -#if defined (PROM) +#if defined(PROM) /* * These defines are prom version dependent. No code other than the IP27 diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h index 9e8cc52910f6..b06190093bbc 100644 --- a/include/asm-mips/sn/sn0/addrs.h +++ b/include/asm-mips/sn/sn0/addrs.h @@ -91,7 +91,7 @@ : RAW_NODE_SWIN_BASE(nasid, widget)) #else /* __ASSEMBLY__ */ #define NODE_SWIN_BASE(nasid, widget) \ - (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) + (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) #endif /* __ASSEMBLY__ */ /* @@ -106,7 +106,7 @@ #define BWIN_WIDGET_MASK 0x7 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ - (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) @@ -259,7 +259,7 @@ * CACHE_ERR_SP_PTR could either contain an address to the stack, or * the stack could start at CACHE_ERR_SP_PTR */ -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define CACHE_ERR_EFRAME 0x480 #else /* HUB_ERR_STS_WAR */ #define CACHE_ERR_EFRAME 0x400 @@ -275,7 +275,7 @@ #define _ARCSPROM -#if defined (HUB_ERR_STS_WAR) +#if defined(HUB_ERR_STS_WAR) #define ERR_STS_WAR_REGISTER IIO_IIBUSERR #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index ddaf36a1e389..4d43dbb7f8b8 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -194,17 +194,17 @@ extern unsigned int sni_brd_type; #define PCIMT_INT_ACKNOWLEDGE 0xba000000 /* board specific init functions */ -extern void sni_a20r_init (void); -extern void sni_pcit_init (void); -extern void sni_rm200_init (void); -extern void sni_pcimt_init (void); +extern void sni_a20r_init(void); +extern void sni_pcit_init(void); +extern void sni_rm200_init(void); +extern void sni_pcimt_init(void); /* board specific irq init functions */ -extern void sni_a20r_irq_init (void); -extern void sni_pcit_irq_init (void); -extern void sni_pcit_cplus_irq_init (void); -extern void sni_rm200_irq_init (void); -extern void sni_pcimt_irq_init (void); +extern void sni_a20r_irq_init(void); +extern void sni_pcit_irq_init(void); +extern void sni_pcit_cplus_irq_init(void); +extern void sni_rm200_irq_init(void); +extern void sni_pcimt_irq_init(void); /* timer inits */ extern void sni_cpu_time_init(void); diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 35e431cd796b..bb897016c491 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -67,7 +67,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) : "memory"); } - smp_mb(); + smp_llsc_mb(); } static inline void __raw_spin_unlock(raw_spinlock_t *lock) @@ -118,7 +118,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) : "memory"); } - smp_mb(); + smp_llsc_mb(); return res == 0; } @@ -183,7 +183,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) : "memory"); } - smp_mb(); + smp_llsc_mb(); } /* Note the use of sub, not subu which will make the kernel die with an @@ -193,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) { unsigned int tmp; - smp_mb(); + smp_llsc_mb(); if (R10000_LLSC_WAR) { __asm__ __volatile__( @@ -262,7 +262,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) : "memory"); } - smp_mb(); + smp_llsc_mb(); } static inline void __raw_write_unlock(raw_rwlock_t *rw) @@ -293,7 +293,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) " .set reorder \n" " beqzl %1, 1b \n" " nop \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" "2: \n" : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) @@ -310,7 +310,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) " beqz %1, 1b \n" " nop \n" " .set reorder \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" "2: \n" : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) @@ -336,7 +336,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) " sc %1, %0 \n" " beqzl %1, 1b \n" " nop \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" " .set reorder \n" "2: \n" @@ -354,7 +354,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) " beqz %1, 3f \n" " li %2, 1 \n" "2: \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " .subsection 2 \n" "3: b 1b \n" " li %2, 0 \n" diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index ed33366b85b8..fb41a8d76392 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -91,14 +91,14 @@ #else MFC0 k0, CP0_CONTEXT #endif -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, 16 daddiu k1, %hi(kernelsp) dsll k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_SRL k0, PTEBASE_SHIFT LONG_ADDU k1, k0 @@ -116,14 +116,14 @@ .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) +#else lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, k1, 16 daddiu k1, %hi(kernelsp) dsll k1, k1, 16 -#else - lui k1, %hi(kernelsp) #endif LONG_L k1, %lo(kernelsp)(k1) .endm @@ -393,11 +393,11 @@ * and disable interrupts only for the * current TC, using the TCStatus register. */ - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS @@ -429,11 +429,11 @@ * current TC, using the TCStatus register. */ _ehb - mfc0 t0,CP0_TCSTATUS + mfc0 t0, CP0_TCSTATUS /* Fortunately CU 0 is in the same place in both registers */ /* Set TCU0, TKSU (for later inversion) and IXMT */ li t1, ST0_CU0 | 0x08001c00 - or t0,t1 + or t0, t1 /* Clear TKSU *and* IXMT */ xori t0, 0x00001c00 mtc0 t0, CP0_TCSTATUS diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h index 07f873351a86..0bf82818aa53 100644 --- a/include/asm-mips/stacktrace.h +++ b/include/asm-mips/stacktrace.h @@ -9,7 +9,11 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, unsigned long pc, unsigned long *ra); #else #define raw_show_trace 1 -#define unwind_stack(task, sp, pc, ra) 0 +static inline unsigned long unwind_stack(struct task_struct *task, + unsigned long *sp, unsigned long pc, unsigned long *ra) +{ + return 0; +} #endif static __always_inline void prepare_frametrace(struct pt_regs *regs) diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 46bdb3f566f9..90e4b403f531 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -17,6 +17,7 @@ #include <asm/addrspace.h> #include <asm/barrier.h> +#include <asm/cmpxchg.h> #include <asm/cpu-features.h> #include <asm/dsp.h> #include <asm/war.h> @@ -46,10 +47,12 @@ struct task_struct; #define __mips_mt_fpaff_switch_to(prev) \ do { \ + struct thread_info *__prev_ti = task_thread_info(prev); \ + \ if (cpu_has_fpu && \ - (prev->thread.mflags & MF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - prev->thread.mflags &= ~MF_FPUBOUND; \ + test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ + (!(KSTK_STATUS(prev) & ST0_CU1))) { \ + clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ prev->cpus_allowed = prev->thread.user_cpus_allowed; \ } \ next->thread.emulated_fp = 0; \ @@ -59,7 +62,7 @@ do { \ #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) #endif -#define switch_to(prev,next,last) \ +#define switch_to(prev, next, last) \ do { \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ @@ -71,16 +74,6 @@ do { \ write_c0_userlocal(task_thread_info(current)->tp_value);\ } while(0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { __u32 retval; @@ -127,7 +120,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -175,7 +168,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -200,273 +193,13 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz return x; } -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -#define __HAVE_ARCH_CMPXCHG 1 - -static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, - unsigned long new) -{ - __u32 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqz $1, 3f \n" - "2: \n" - " .subsection 2 \n" - "3: b 1b \n" - " .previous \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_mb(); - - return retval; -} - -static inline unsigned long __cmpxchg_u32_local(volatile int * m, - unsigned long old, unsigned long new) -{ - __u32 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqz $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - } - - return retval; -} - -#ifdef CONFIG_64BIT -static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, - unsigned long new) -{ - __u64 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqz $1, 3f \n" - "2: \n" - " .subsection 2 \n" - "3: b 1b \n" - " .previous \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_mb(); - - return retval; -} - -static inline unsigned long __cmpxchg_u64_local(volatile int * m, - unsigned long old, unsigned long new) -{ - __u64 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqz $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - } - - return retval; -} - -#else -extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels( - volatile int * m, unsigned long old, unsigned long new); -#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels -extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels( - volatile int * m, unsigned long old, unsigned long new); -#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels -#endif - -/* This function doesn't exist, so you'll get a linker error - if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); - case 8: - return __cmpxchg_u64(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -static inline unsigned long __cmpxchg_local(volatile void * ptr, - unsigned long old, unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32_local(ptr, old, new); - case 8: - return __cmpxchg_u64_local(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr,old,new) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), \ - (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) - -#define cmpxchg_local(ptr,old,new) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ - (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) +#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) -extern void set_handler (unsigned long offset, void *addr, unsigned long len); -extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); +extern void set_handler(unsigned long offset, void *addr, unsigned long len); +extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); typedef void (*vi_handler_t)(void); -extern void *set_vi_handler (int n, vi_handler_t addr); +extern void *set_vi_handler(int n, vi_handler_t addr); extern void *set_except_vector(int n, void *addr); extern unsigned long ebase; @@ -480,6 +213,6 @@ extern int stop_a_enabled; */ #define __ARCH_WANT_UNLOCKED_CTXSW -#define arch_align_stack(x) (x) +extern unsigned long arch_align_stack(unsigned long sp); #endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 5bfdc3b64510..c83c68444e86 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h @@ -164,6 +164,7 @@ struct ktermios { #define HUPCL 0002000 /* Hang up on last close. */ #define CLOCAL 0004000 /* Ignore modem status lines. */ #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -179,9 +180,11 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ +#define CRTSCTS 020000000000 /* flow control */ + +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ /* c_lflag bits */ #define ISIG 0000001 /* Enable signals. */ diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h index 2ce07f4be369..a275661fa7e1 100644 --- a/include/asm-mips/termios.h +++ b/include/asm-mips/termios.h @@ -122,8 +122,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* defined(__KERNEL__) */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index fbcda8204473..b2772df1a1bd 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -46,7 +46,7 @@ struct thread_info { { \ .task = &tsk, \ .exec_domain = &default_exec_domain, \ - .flags = 0, \ + .flags = _TIF_FIXADE, \ .cpu = 0, \ .preempt_count = 1, \ .addr_limit = KERNEL_DS, \ @@ -87,9 +87,8 @@ register struct thread_info *__current_thread_info __asm__("$28"); ({ \ struct thread_info *ret; \ \ - ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \ - if (ret) \ - memset(ret, 0, THREAD_SIZE); \ + ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ + \ ret; \ }) #else @@ -109,20 +108,23 @@ register struct thread_info *__current_thread_info __asm__("$28"); * - pending work-to-be-done flags are in LSW * - other flags in MSW */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ -#define TIF_SECCOMP 5 /* secure computing */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ +#define TIF_SECCOMP 4 /* secure computing */ #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 +#define TIF_FIXADE 20 /* Fix address errors in software */ +#define TIF_LOGADE 21 /* Log address errors to syslog */ +#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ +#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ +#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) @@ -131,6 +133,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_USEDFPU (1<<TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_FREEZE (1<<TIF_FREEZE) +#define _TIF_FIXADE (1<<TIF_FIXADE) +#define _TIF_LOGADE (1<<TIF_LOGADE) +#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) +#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) +#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index a632cef830a2..35555bd5c52d 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -26,15 +26,13 @@ extern spinlock_t rtc_lock; /* - * RTC ops. By default, they point to no-RTC functions. - * rtc_mips_get_time - mktime(year, mon, day, hour, min, sec) in seconds. + * RTC ops. By default, they point to weak no-op RTC functions. * rtc_mips_set_time - reverse the above translation and set time to RTC. * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need * to be set. Used by RTC sync-up. */ -extern unsigned long (*rtc_mips_get_time)(void); -extern int (*rtc_mips_set_time)(unsigned long); -extern int (*rtc_mips_set_mmss)(unsigned long); +extern int rtc_mips_set_time(unsigned long); +extern int rtc_mips_set_mmss(unsigned long); /* * Timer interrupt functions. @@ -51,35 +49,15 @@ extern void (*mips_timer_ack)(void); extern struct clocksource clocksource_mips; /* - * to_tm() converts system time back to (year, mon, day, hour, min, sec). - * It is intended to help implement rtc_set_time() functions. - * Copied from PPC implementation. - */ -extern void to_tm(unsigned long tim, struct rtc_time *tm); - -/* - * high-level timer interrupt routines. - */ -extern irqreturn_t timer_interrupt(int irq, void *dev_id); - -/* - * the corresponding low-level timer interrupt routine. - */ -extern asmlinkage void ll_timer_interrupt(int irq); - -/* * profiling and process accouting is done separately in local_timer_interrupt */ extern void local_timer_interrupt(int irq, void *dev_id); -extern asmlinkage void ll_local_timer_interrupt(int irq); /* * board specific routines required by time_init(). - * board_time_init is defaulted to NULL and can remain so. - * plat_timer_setup must be setup properly in machine setup routine. */ struct irqaction; -extern void (*board_time_init)(void); +extern void plat_time_init(void); extern void plat_timer_setup(struct irqaction *irq); /* @@ -89,4 +67,15 @@ extern void plat_timer_setup(struct irqaction *irq); */ extern unsigned int mips_hpt_frequency; +/* + * The performance counter IRQ on MIPS is a close relative to the timer IRQ + * so it lives here. + */ +extern int (*perf_irq)(void); + +/* + * Initialize the calling CPU's compare interrupt as clockevent device + */ +extern void mips_clockevent_init(void); + #endif /* _ASM_TIME_H */ diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h index b80de8e0fbbd..87c68ae76ff8 100644 --- a/include/asm-mips/timex.h +++ b/include/asm-mips/timex.h @@ -48,7 +48,7 @@ typedef unsigned int cycles_t; -static inline cycles_t get_cycles (void) +static inline cycles_t get_cycles(void) { return read_c0_count(); } diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h index 276be77c3e85..730e841fb08a 100644 --- a/include/asm-mips/tlbflush.h +++ b/include/asm-mips/tlbflush.h @@ -37,10 +37,10 @@ extern void flush_tlb_one(unsigned long vaddr); #define flush_tlb_all() local_flush_tlb_all() #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) -#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) +#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end) #define flush_tlb_kernel_range(vmaddr,end) \ local_flush_tlb_kernel_range(vmaddr, end) -#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) +#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) #define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) #endif /* CONFIG_SMP */ diff --git a/include/asm-mips/tx3912.h b/include/asm-mips/tx3912.h deleted file mode 100644 index d709d87363d0..000000000000 --- a/include/asm-mips/tx3912.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - * include/asm-mips/tx3912.h - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Registers for TMPR3912/05 and PR31700 processors - */ -#ifndef _TX3912_H_ -#define _TX3912_H_ - -/***************************************************************************** - * Clock Subsystem * - * --------------- * - * Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * - *****************************************************************************/ -#define TX3912_CLK_CTRL 0x01c0 - -/* - * Clock control register values - */ -#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 -#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 -#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 -#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 -#define TX3912_CLK_CTRL_CHICLKDIR 0x00100000 -#define TX3912_CLK_CTRL_ENCHIMCLK 0x00080000 -#define TX3912_CLK_CTRL_ENVIDCLK 0x00040000 -#define TX3912_CLK_CTRL_ENMBUSCLK 0x00020000 -#define TX3912_CLK_CTRL_ENSPICLK 0x00010000 -#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 -#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 -#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 -#define TX3912_CLK_CTRL_reserved1 0x00001000 -#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 -#define TX3912_CLK_CTRL_SIBMCLKDIV_6 0x00000600 -#define TX3912_CLK_CTRL_SIBMCLKDIV_5 0x00000500 -#define TX3912_CLK_CTRL_SIBMCLKDIV_4 0x00000400 -#define TX3912_CLK_CTRL_SIBMCLKDIV_3 0x00000300 -#define TX3912_CLK_CTRL_SIBMCLKDIV_2 0x00000200 -#define TX3912_CLK_CTRL_SIBMCLKDIV_1 0x00000100 -#define TX3912_CLK_CTRL_CSERSEL 0x00000080 -#define TX3912_CLK_CTRL_CSERDIV_6 0x00000060 -#define TX3912_CLK_CTRL_CSERDIV_5 0x00000050 -#define TX3912_CLK_CTRL_CSERDIV_4 0x00000040 -#define TX3912_CLK_CTRL_CSERDIV_3 0x00000030 -#define TX3912_CLK_CTRL_CSERDIV_2 0x00000020 -#define TX3912_CLK_CTRL_CSERDIV_1 0x00000010 -#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 -#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 -#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 -#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 - - -/***************************************************************************** - * Interrupt Subsystem * - * ------------------- * - * Chapter 8 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * - *****************************************************************************/ -#define TX3912_INT1_CLEAR 0x0100 -#define TX3912_INT2_CLEAR 0x0104 -#define TX3912_INT3_CLEAR 0x0108 -#define TX3912_INT4_CLEAR 0x010c -#define TX3912_INT5_CLEAR 0x0110 -#define TX3912_INT1_ENABLE 0x0118 -#define TX3912_INT2_ENABLE 0x011c -#define TX3912_INT3_ENABLE 0x0120 -#define TX3912_INT4_ENABLE 0x0124 -#define TX3912_INT5_ENABLE 0x0128 -#define TX3912_INT6_ENABLE 0x012c -#define TX3912_INT1_STATUS 0x0100 -#define TX3912_INT2_STATUS 0x0104 -#define TX3912_INT3_STATUS 0x0108 -#define TX3912_INT4_STATUS 0x010c -#define TX3912_INT5_STATUS 0x0110 -#define TX3912_INT6_STATUS 0x0114 - -/* - * Interrupt 2 register values - */ -#define TX3912_INT2_UARTARXINT 0x80000000 -#define TX3912_INT2_UARTARXOVERRUNINT 0x40000000 -#define TX3912_INT2_UARTAFRAMEERRINT 0x20000000 -#define TX3912_INT2_UARTABREAKINT 0x10000000 -#define TX3912_INT2_UARTAPARITYINT 0x08000000 -#define TX3912_INT2_UARTATXINT 0x04000000 -#define TX3912_INT2_UARTATXOVERRUNINT 0x02000000 -#define TX3912_INT2_UARTAEMPTYINT 0x01000000 -#define TX3912_INT2_UARTADMAFULLINT 0x00800000 -#define TX3912_INT2_UARTADMAHALFINT 0x00400000 -#define TX3912_INT2_UARTBRXINT 0x00200000 -#define TX3912_INT2_UARTBRXOVERRUNINT 0x00100000 -#define TX3912_INT2_UARTBFRAMEERRINT 0x00080000 -#define TX3912_INT2_UARTBBREAKINT 0x00040000 -#define TX3912_INT2_UARTBPARITYINT 0x00020000 -#define TX3912_INT2_UARTBTXINT 0x00010000 -#define TX3912_INT2_UARTBTXOVERRUNINT 0x00008000 -#define TX3912_INT2_UARTBEMPTYINT 0x00004000 -#define TX3912_INT2_UARTBDMAFULLINT 0x00002000 -#define TX3912_INT2_UARTBDMAHALFINT 0x00001000 -#define TX3912_INT2_UARTA_RX_BITS 0xf8000000 -#define TX3912_INT2_UARTA_TX_BITS 0x07c00000 -#define TX3912_INT2_UARTB_RX_BITS 0x003e0000 -#define TX3912_INT2_UARTB_TX_BITS 0x0001f000 - -/* - * Interrupt 5 register values - */ -#define TX3912_INT5_RTCINT 0x80000000 -#define TX3912_INT5_ALARMINT 0x40000000 -#define TX3912_INT5_PERINT 0x20000000 -#define TX3912_INT5_STPTIMERINT 0x10000000 -#define TX3912_INT5_POSPWRINT 0x08000000 -#define TX3912_INT5_NEGPWRINT 0x04000000 -#define TX3912_INT5_POSPWROKINT 0x02000000 -#define TX3912_INT5_NEGPWROKINT 0x01000000 -#define TX3912_INT5_POSONBUTINT 0x00800000 -#define TX3912_INT5_NEGONBUTINT 0x00400000 -#define TX3912_INT5_SPIBUFAVAILINT 0x00200000 -#define TX3912_INT5_SPIERRINT 0x00100000 -#define TX3912_INT5_SPIRCVINT 0x00080000 -#define TX3912_INT5_SPIEMPTYINT 0x00040000 -#define TX3912_INT5_IRCONSMINT 0x00020000 -#define TX3912_INT5_CARSTINT 0x00010000 -#define TX3912_INT5_POSCARINT 0x00008000 -#define TX3912_INT5_NEGCARINT 0x00004000 -#define TX3912_INT5_IOPOSINT6 0x00002000 -#define TX3912_INT5_IOPOSINT5 0x00001000 -#define TX3912_INT5_IOPOSINT4 0x00000800 -#define TX3912_INT5_IOPOSINT3 0x00000400 -#define TX3912_INT5_IOPOSINT2 0x00000200 -#define TX3912_INT5_IOPOSINT1 0x00000100 -#define TX3912_INT5_IOPOSINT0 0x00000080 -#define TX3912_INT5_IONEGINT6 0x00000040 -#define TX3912_INT5_IONEGINT5 0x00000020 -#define TX3912_INT5_IONEGINT4 0x00000010 -#define TX3912_INT5_IONEGINT3 0x00000008 -#define TX3912_INT5_IONEGINT2 0x00000004 -#define TX3912_INT5_IONEGINT1 0x00000002 -#define TX3912_INT5_IONEGINT0 0x00000001 - -/* - * Interrupt 6 status register values - */ -#define TX3912_INT6_STATUS_IRQHIGH 0x80000000 -#define TX3912_INT6_STATUS_IRQLOW 0x40000000 -#define TX3912_INT6_STATUS_reserved6 0x3fffffc0 -#define TX3912_INT6_STATUS_INTVEC_POSNEGPWROKINT 0x0000003c -#define TX3912_INT6_STATUS_INTVEC_ALARMINT 0x00000038 -#define TX3912_INT6_STATUS_INTVEC_PERINT 0x00000034 -#define TX3912_INT6_STATUS_INTVEC_reserved5 0x00000030 -#define TX3912_INT6_STATUS_INTVEC_UARTARXINT 0x0000002c -#define TX3912_INT6_STATUS_INTVEC_UARTBRXINT 0x00000028 -#define TX3912_INT6_STATUS_INTVEC_reserved4 0x00000024 -#define TX3912_INT6_STATUS_INTVEC_IOPOSINT65 0x00000020 -#define TX3912_INT6_STATUS_INTVEC_reserved3 0x0000001c -#define TX3912_INT6_STATUS_INTVEC_IONEGINT65 0x00000018 -#define TX3912_INT6_STATUS_INTVEC_reserved2 0x00000014 -#define TX3912_INT6_STATUS_INTVEC_SNDDMACNTINT 0x00000010 -#define TX3912_INT6_STATUS_INTVEC_TELDMACNTINT 0x0000000c -#define TX3912_INT6_STATUS_INTVEC_CHIDMACNTINT 0x00000008 -#define TX3912_INT6_STATUS_INTVEC_IOPOSNEGINT0 0x00000004 -#define TX3912_INT6_STATUS_INTVEC_STDHANDLER 0x00000000 -#define TX3912_INT6_STATUS_reserved1 0x00000003 - -/* - * Interrupt 6 enable register values - */ -#define TX3912_INT6_ENABLE_reserved5 0xfff80000 -#define TX3912_INT6_ENABLE_GLOBALEN 0x00040000 -#define TX3912_INT6_ENABLE_IRQPRITEST 0x00020000 -#define TX3912_INT6_ENABLE_IRQTEST 0x00010000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_POSNEGPWROKINT 0x00008000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_ALARMINT 0x00004000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_PERINT 0x00002000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved4 0x00001000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT 0x00000800 -#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTBRXINT 0x00000400 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved3 0x00000200 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSINT65 0x00000100 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved2 0x00000080 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IONEGINT65 0x00000040 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved1 0x00000020 -#define TX3912_INT6_ENABLE_PRIORITYMASK_SNDDMACNTINT 0x00000010 -#define TX3912_INT6_ENABLE_PRIORITYMASK_TELDMACNTINT 0x00000008 -#define TX3912_INT6_ENABLE_PRIORITYMASK_CHIDMACNTINT 0x00000004 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSNEGINT0 0x00000002 -#define TX3912_INT6_ENABLE_PRIORITYMASK_STDHANDLER 0x00000001 -#define TX3912_INT6_ENABLE_HIGH_PRIORITY 0x0000ffff - - -/***************************************************************************** - * Power Subsystem * - * --------------- * - * Chapter 11 in Philips PR31700 User Manual * - * Chapter 12 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_POWER_CTRL 0x01c4 - -/* - * Power control register values - */ -#define TX3912_POWER_CTRL_ONBUTN 0x80000000 -#define TX3912_POWER_CTRL_PWRINT 0x40000000 -#define TX3912_POWER_CTRL_PWROK 0x20000000 -#define TX3912_POWER_CTRL_VIDRF_MASK 0x18000000 -#define TX3912_POWER_CTRL_SLOWBUS 0x04000000 -#define TX3912_POWER_CTRL_DIVMOD 0x02000000 -#define TX3912_POWER_CTRL_reserved2 0x01ff0000 -#define TX3912_POWER_CTRL_STPTIMERVAL_MASK 0x0000f000 -#define TX3912_POWER_CTRL_ENSTPTIMER 0x00000800 -#define TX3912_POWER_CTRL_ENFORCESHUTDWN 0x00000400 -#define TX3912_POWER_CTRL_FORCESHUTDWN 0x00000200 -#define TX3912_POWER_CTRL_FORCESHUTDWNOCC 0x00000100 -#define TX3912_POWER_CTRL_SELC2MS 0x00000080 -#define TX3912_POWER_CTRL_reserved1 0x00000040 -#define TX3912_POWER_CTRL_BPDBVCC3 0x00000020 -#define TX3912_POWER_CTRL_STOPCPU 0x00000010 -#define TX3912_POWER_CTRL_DBNCONBUTN 0x00000008 -#define TX3912_POWER_CTRL_COLDSTART 0x00000004 -#define TX3912_POWER_CTRL_PWRCS 0x00000002 -#define TX3912_POWER_CTRL_VCCON 0x00000001 - - -/***************************************************************************** - * Timer Subsystem * - * --------------- * - * Chapter 14 in Philips PR31700 User Manual * - * Chapter 15 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_RTC_HIGH 0x0140 -#define TX3912_RTC_LOW 0x0144 -#define TX3912_RTC_ALARM_HIGH 0x0148 -#define TX3912_RTC_ALARM_LOW 0x014c -#define TX3912_TIMER_CTRL 0x0150 -#define TX3912_TIMER_PERIOD 0x0154 - -/* - * Timer control register values - */ -#define TX3912_TIMER_CTRL_FREEZEPRE 0x00000080 -#define TX3912_TIMER_CTRL_FREEZERTC 0x00000040 -#define TX3912_TIMER_CTRL_FREEZETIMER 0x00000020 -#define TX3912_TIMER_CTRL_ENPERTIMER 0x00000010 -#define TX3912_TIMER_CTRL_RTCCLEAR 0x00000008 -#define TX3912_TIMER_CTRL_TESTC8MS 0x00000004 -#define TX3912_TIMER_CTRL_ENTESTCLK 0x00000002 -#define TX3912_TIMER_CTRL_ENRTCTST 0x00000001 - -/* - * The periodic timer has granularity of 868 nanoseconds which - * results in a count of (1.152 x 10^6 / 100) in order to achieve - * a 10 millisecond periodic system clock. - */ -#define TX3912_SYS_TIMER_VALUE (1152000/HZ) - - -/***************************************************************************** - * UART Subsystem * - * -------------- * - * Chapter 15 in Philips PR31700 User Manual * - * Chapter 16 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_UARTA_CTRL1 0x00b0 -#define TX3912_UARTA_CTRL2 0x00b4 -#define TX3912_UARTA_DMA_CTRL1 0x00b8 -#define TX3912_UARTA_DMA_CTRL2 0x00bc -#define TX3912_UARTA_DMA_CNT 0x00c0 -#define TX3912_UARTA_DATA 0x00c4 -#define TX3912_UARTB_CTRL1 0x00c8 -#define TX3912_UARTB_CTRL2 0x00cc -#define TX3912_UARTB_DMA_CTRL1 0x00d0 -#define TX3912_UARTB_DMA_CTRL2 0x00d4 -#define TX3912_UARTB_DMA_CNT 0x00d8 -#define TX3912_UARTB_DATA 0x00dc - -/* - * UART Control Register 1 values - */ -#define TX3912_UART_CTRL1_UARTON 0x80000000 -#define TX3912_UART_CTRL1_EMPTY 0x40000000 -#define TX3912_UART_CTRL1_PRXHOLDFULL 0x20000000 -#define TX3912_UART_CTRL1_RXHOLDFULL 0x10000000 -#define TX3912_UART_CTRL1_reserved1 0x0fff0000 -#define TX3912_UART_CTRL1_ENDMARX 0x00008000 -#define TX3912_UART_CTRL1_ENDMATX 0x00004000 -#define TX3912_UART_CTRL1_TESTMODE 0x00002000 -#define TX3912_UART_CTRL1_ENBREAKHALT 0x00001000 -#define TX3912_UART_CTRL1_ENDMATEST 0x00000800 -#define TX3912_UART_CTRL1_ENDMALOOP 0x00000400 -#define TX3912_UART_CTRL1_PULSEOPT1 0x00000200 -#define TX3912_UART_CTRL1_PULSEOPT1 0x00000100 -#define TX3912_UART_CTRL1_DTINVERT 0x00000080 -#define TX3912_UART_CTRL1_DISTXD 0x00000040 -#define TX3912_UART_CTRL1_TWOSTOP 0x00000020 -#define TX3912_UART_CTRL1_LOOPBACK 0x00000010 -#define TX3912_UART_CTRL1_BIT_7 0x00000008 -#define TX3912_UART_CTRL1_EVENPARITY 0x00000004 -#define TX3912_UART_CTRL1_ENPARITY 0x00000002 -#define TX3912_UART_CTRL1_ENUART 0x00000001 - -/* - * UART Control Register 2 values - */ -#define TX3912_UART_CTRL2_B230400 0x0000 /* 0 */ -#define TX3912_UART_CTRL2_B115200 0x0001 /* 1 */ -#define TX3912_UART_CTRL2_B76800 0x0002 /* 2 */ -#define TX3912_UART_CTRL2_B57600 0x0003 /* 3 */ -#define TX3912_UART_CTRL2_B38400 0x0005 /* 5 */ -#define TX3912_UART_CTRL2_B19200 0x000b /* 11 */ -#define TX3912_UART_CTRL2_B9600 0x0016 /* 22 */ -#define TX3912_UART_CTRL2_B4800 0x002f /* 47 */ -#define TX3912_UART_CTRL2_B2400 0x005f /* 95 */ -#define TX3912_UART_CTRL2_B1200 0x00bf /* 191 */ -#define TX3912_UART_CTRL2_B600 0x017f /* 383 */ -#define TX3912_UART_CTRL2_B300 0x02ff /* 767 */ - -/***************************************************************************** - * Video Subsystem * - * --------------- * - * Chapter 16 in Philips PR31700 User Manual * - * Chapter 17 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_VIDEO_CTRL1 0x0028 -#define TX3912_VIDEO_CTRL2 0x002c -#define TX3912_VIDEO_CTRL3 0x0030 -#define TX3912_VIDEO_CTRL4 0x0034 -#define TX3912_VIDEO_CTRL5 0x0038 -#define TX3912_VIDEO_CTRL6 0x003c -#define TX3912_VIDEO_CTRL7 0x0040 -#define TX3912_VIDEO_CTRL8 0x0044 -#define TX3912_VIDEO_CTRL9 0x0048 -#define TX3912_VIDEO_CTRL10 0x004c -#define TX3912_VIDEO_CTRL11 0x0050 -#define TX3912_VIDEO_CTRL12 0x0054 -#define TX3912_VIDEO_CTRL13 0x0058 -#define TX3912_VIDEO_CTRL14 0x005c - -/* - * Video Control Register 1 values - */ -#define TX3912_VIDEO_CTRL1_LINECNT 0xffc00000 -#define TX3912_VIDEO_CTRL1_LOADDLY 0x00200000 -#define TX3912_VIDEO_CTRL1_BAUDVAL 0x001f0000 -#define TX3912_VIDEO_CTRL1_VIDDONEVAL 0x0000fe00 -#define TX3912_VIDEO_CTRL1_ENFREEZEFRAME 0x00000100 -#define TX3912_VIDEO_CTRL1_BITSEL_MASK 0x000000c0 -#define TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR 0x000000c0 -#define TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY 0x00000080 -#define TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY 0x00000040 -#define TX3912_VIDEO_CTRL1_DISPSPLIT 0x00000020 -#define TX3912_VIDEO_CTRL1_DISP8 0x00000010 -#define TX3912_VIDEO_CTRL1_DFMODE 0x00000008 -#define TX3912_VIDEO_CTRL1_INVVID 0x00000004 -#define TX3912_VIDEO_CTRL1_DISPON 0x00000002 -#define TX3912_VIDEO_CTRL1_ENVID 0x00000001 - -#endif /* _TX3912_H_ */ diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index 94bef03d9635..b188a659ce02 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,28 +28,26 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include <asm/tx4927/tx4927.h> -#include <asm/tx4927/tx4927_mips.h> #ifdef CONFIG_PCI #include <asm/tx4927/tx4927_pci.h> #endif -#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 ) - - #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO #else #define TBTX4927_ISA_IO_OFFSET 0 #endif -#define RBTX4927_SW_RESET_DO 0xbc00f000 +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL #define RBTX4927_SW_RESET_DO_SET 0x01 -#define RBTX4927_SW_RESET_ENABLE 0xbc00f002 +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (29) +#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) + +int toshiba_rbtx4927_irq_nested(int sw_irq); #endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index de85bd2245f7..193e80a17c12 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -27,491 +27,13 @@ #ifndef __ASM_TX4927_TX4927_H #define __ASM_TX4927_TX4927_H -#include <asm/tx4927/tx4927_mips.h> +#include <asm/txx9irq.h> -/* - This register naming came from the integrated CPU/controller name TX4927 - followed by the device name from table 4.2.2 on page 4-3 and then followed - by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". - */ - -#define TX4927_SIO_0_BASE - -/* TX4927 controller */ -#define TX4927_BASE 0xfff1f0000 -#define TX4927_BASE 0xfff1f0000 -#define TX4927_LIMIT 0xfff1fffff - - -/* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 -#define TX4927_SDRAMC_SDCCR1 0x8008 -#define TX4927_SDRAMC_SDCCR2 0x8010 -#define TX4927_SDRAMC_SDCCR3 0x8018 -#define TX4927_SDRAMC_SDCTR 0x8040 -#define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff - - -/* TX4927 external bus controller (64-bit registers) */ -#define TX4927_EBUSC_BASE 0x9000 -#define TX4927_EBUSC_EBCCR0 0x9000 -#define TX4927_EBUSC_EBCCR1 0x9008 -#define TX4927_EBUSC_EBCCR2 0x9010 -#define TX4927_EBUSC_EBCCR3 0x9018 -#define TX4927_EBUSC_EBCCR4 0x9020 -#define TX4927_EBUSC_EBCCR5 0x9028 -#define TX4927_EBUSC_EBCCR6 0x9030 -#define TX4927_EBUSC_EBCCR7 0x9008 -#define TX4927_EBUSC_LIMIT 0x9fff - - -/* TX4927 SDRRAM Error Check Correction (64-bit registers) */ -#define TX4927_ECC_BASE 0xa000 -#define TX4927_ECC_ECCCR 0xa000 -#define TX4927_ECC_ECCSR 0xa008 -#define TX4927_ECC_LIMIT 0xafff - - -/* TX4927 DMA Controller (64-bit registers) */ -#define TX4927_DMAC_BASE 0xb000 -#define TX4927_DMAC_TBD 0xb000 -#define TX4927_DMAC_LIMIT 0xbfff - - -/* TX4927 PCI Controller (32-bit registers) */ -#define TX4927_PCIC_BASE 0xd000 -#define TX4927_PCIC_TBD 0xb000 -#define TX4927_PCIC_LIMIT 0xdfff - - -/* TX4927 Configuration registers (64-bit registers) */ -#define TX4927_CONFIG_BASE 0xe000 -#define TX4927_CONFIG_CCFG 0xe000 -#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 -#define TX4927_CONFIG_CCFG_WDRST BM_41_41 -#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 -#define TX4927_CONFIG_CCFG_BCFG BM_39_32 -#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 -#define TX4927_CONFIG_CCFG_GTOT BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 -#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 -#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 -#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) -#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 -#define TX4927_CONFIG_CCFG_PCI66 BM_23_23 -#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 -#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 -#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 -#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) -#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 -#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 -#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) -#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 -#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 -#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 -#define TX4927_CONFIG_CCFG_BEOW BM_16_16 -#define TX4927_CONFIG_CCFG_WR BM_15_15 -#define TX4927_CONFIG_CCFG_TOE BM_14_14 -#define TX4927_CONFIG_CCFG_PCIARB BM_13_13 -#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 -#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 -#define TX4927_CONFIG_CCFG_SYSSP BM_07_06 -#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 -#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 -#define TX4927_CONFIG_CCFG_ARMODE BM_01_01 -#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 -#define TX4927_CONFIG_REVID 0xe008 -#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 -#define TX4927_CONFIG_REVID_PCODE BM_16_31 -#define TX4927_CONFIG_REVID_MJERREV BM_12_15 -#define TX4927_CONFIG_REVID_MINEREV BM_08_11 -#define TX4927_CONFIG_REVID_MJREV BM_04_07 -#define TX4927_CONFIG_REVID_MINREV BM_00_03 -#define TX4927_CONFIG_PCFG 0xe010 -#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 -#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 -#define TX4927_CONFIG_PCFG_DRVCB BM_55_55 -#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 -#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 -#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 -#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 -#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 -#define TX4927_CONFIG_PCFG_DRVWE BM_49_49 -#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 -#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 -#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k -#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 -#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 -#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 -#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 -#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 -#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 -#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 -#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 -#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 -#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 -#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 -#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 -#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 -#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 -#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 -#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 -#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 -#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 -#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 -#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 -#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 -#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 -#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 -#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_PCFG_SEL2 BM_09_09 -#define TX4927_CONFIG_PCFG_SEL1 BM_08_08 -#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 -#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 -#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) -#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 -#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 -#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 -#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) -#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 -#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 -#define TX4927_CONFIG_TOEA 0xe018 -#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 -#define TX4927_CONFIG_TOEA_TOEA BM_00_35 -#define TX4927_CONFIG_CLKCTR 0xe020 -#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 -#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 -#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 -#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 -#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 -#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 -#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 -#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 -#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 -#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 -#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 -#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 -#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 -#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 -#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 -#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 -#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 -#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 -#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 -#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 -#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 -#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 -#define TX4927_CONFIG_GARBC 0xe030 -#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 -#define TX4927_CONFIG_GARBC_SET_09 BM_09_09 -#define TX4927_CONFIG_GARBC_ARBMD BM_08_08 -#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 -#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) -#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 -#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) -#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 -#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) -#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 -#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 -#define TX4927_CONFIG_RAMP 0xe048 -#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 -#define TX4927_CONFIG_RAMP_RAMP BM_00_19 -#define TX4927_CONFIG_LIMIT 0xefff - - -/* TX4927 Timer 0 (32-bit registers) */ -#define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf000 -#define TX4927_TMR0_TMTISR0 0xf004 -#define TX4927_TMR0_TMCPRA0 0xf008 -#define TX4927_TMR0_TMCPRB0 0xf00c -#define TX4927_TMR0_TMITMR0 0xf010 -#define TX4927_TMR0_TMCCDR0 0xf020 -#define TX4927_TMR0_TMPGMR0 0xf030 -#define TX4927_TMR0_TMTRR0 0xf0f0 -#define TX4927_TMR0_LIMIT 0xf0ff - - -/* TX4927 Timer 1 (32-bit registers) */ -#define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf100 -#define TX4927_TMR1_TMTISR1 0xf104 -#define TX4927_TMR1_TMCPRA1 0xf108 -#define TX4927_TMR1_TMCPRB1 0xf10c -#define TX4927_TMR1_TMITMR1 0xf110 -#define TX4927_TMR1_TMCCDR1 0xf120 -#define TX4927_TMR1_TMPGMR1 0xf130 -#define TX4927_TMR1_TMTRR1 0xf1f0 -#define TX4927_TMR1_LIMIT 0xf1ff - - -/* TX4927 Timer 2 (32-bit registers) */ -#define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf200 -#define TX4927_TMR2_TMTISR2 0xf204 -#define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMITMR2 0xf210 -#define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMWTMR2 0xf240 -#define TX4927_TMR2_TMTRR2 0xf2f0 -#define TX4927_TMR2_LIMIT 0xf2ff - - -/* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 -#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SILCR0_RWUB BM_15_15 -#define TX4927_SIO0_SILCR0_TWUB BM_14_14 -#define TX4927_SIO0_SILCR0_UODE BM_13_13 -#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 -#define TX4927_SIO0_SILCR0_SCS BM_05_06 -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) -#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 -#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 -#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 -#define TX4927_SIO0_SILCR0_UEPS BM_04_04 -#define TX4927_SIO0_SILCR0_UPEN BM_03_03 -#define TX4927_SIO0_SILCR0_USBL BM_02_02 -#define TX4927_SIO0_SILCR0_UMODE BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) -#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 -#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 -#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDICR0_TDE BM_15_15 -#define TX4927_SIO0_SIDICR0_RDE BM_14_14 -#define TX4927_SIO0_SIDICR0_TIE BM_13_13 -#define TX4927_SIO0_SIDICR0_RIE BM_12_12 -#define TX4927_SIO0_SIDICR0_SPIE BM_11_11 -#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 -#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) -#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 -#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 -#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 -#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 -#define TX4927_SIO0_SIDICR0_STIE BM_00_05 -#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) -#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 -#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 -#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 -#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 -#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 -#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 -#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 -#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 -#define TX4927_SIO0_SIDISR0_UFER BM_13_13 -#define TX4927_SIO0_SIDISR0_UPER BM_12_12 -#define TX4927_SIO0_SIDISR0_UOER BM_11_11 -#define TX4927_SIO0_SIDISR0_ERI BM_10_10 -#define TX4927_SIO0_SIDISR0_TOUT BM_09_09 -#define TX4927_SIO0_SIDISR0_TDIS BM_08_08 -#define TX4927_SIO0_SIDISR0_RDIS BM_07_07 -#define TX4927_SIO0_SIDISR0_STIS BM_06_06 -#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 -#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c -#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 -#define TX4927_SIO0_SISCISR0_OERS BM_05_05 -#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 -#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 -#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 -#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 -#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 -#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 -#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 -#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 -#define TX4927_SIO0_SIFCR0_RDIL BM_16_31 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 -#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 -#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFCR0_TDIL BM_03_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 -#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 -#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 -#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 -#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 -#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 -#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 -#define TX4927_SIO0_SIFLCR0_TES BM_11_11 -#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 -#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 -#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 -#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 -#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 -#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 -#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 -#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 -#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 -#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) -#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 -#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 -#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 -#define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c -#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 -#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff - - -/* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff - - -/* TX4927 parallel port (32-bit registers) */ -#define TX4927_PIO_BASE 0xf500 -#define TX4927_PIO_PIOD0 0xf500 -#define TX4927_PIO_PIODI 0xf504 -#define TX4927_PIO_PIODIR 0xf508 -#define TX4927_PIO_PIOOD 0xf50c -#define TX4927_PIO_LIMIT 0xf50f - - -/* TX4927 Interrupt Controller (32-bit registers) */ -#define TX4927_IRC_BASE 0xf510 -#define TX4927_IRC_IRFLAG0 0xf510 -#define TX4927_IRC_IRFLAG1 0xf514 -#define TX4927_IRC_IRPOL 0xf518 -#define TX4927_IRC_IRRCNT 0xf51c -#define TX4927_IRC_IRMASKINT 0xf520 -#define TX4927_IRC_IRMASKEXT 0xf524 -#define TX4927_IRC_IRDEN 0xf600 -#define TX4927_IRC_IRDM0 0xf604 -#define TX4927_IRC_IRDM1 0xf608 -#define TX4927_IRC_IRLVL0 0xf610 -#define TX4927_IRC_IRLVL1 0xf614 -#define TX4927_IRC_IRLVL2 0xf618 -#define TX4927_IRC_IRLVL3 0xf61c -#define TX4927_IRC_IRLVL4 0xf620 -#define TX4927_IRC_IRLVL5 0xf624 -#define TX4927_IRC_IRLVL6 0xf628 -#define TX4927_IRC_IRLVL7 0xf62c -#define TX4927_IRC_IRMSK 0xf640 -#define TX4927_IRC_IREDC 0xf660 -#define TX4927_IRC_IRPND 0xf680 -#define TX4927_IRC_IRCS 0xf6a0 -#define TX4927_IRC_LIMIT 0xf6ff - - -/* TX4927 AC-link controller (32-bit registers) */ -#define TX4927_ACLC_BASE 0xf700 -#define TX4927_ACLC_ACCTLEN 0xf700 -#define TX4927_ACLC_ACCTLDIS 0xf704 -#define TX4927_ACLC_ACREGACC 0xf708 -#define TX4927_ACLC_ACINTSTS 0xf710 -#define TX4927_ACLC_ACINTMSTS 0xf714 -#define TX4927_ACLC_ACINTEN 0xf718 -#define TX4927_ACLC_ACINTDIS 0xf71c -#define TX4927_ACLC_ACSEMAPH 0xf720 -#define TX4927_ACLC_ACGPIDAT 0xf740 -#define TX4927_ACLC_ACGPODAT 0xf744 -#define TX4927_ACLC_ACSLTEN 0xf748 -#define TX4927_ACLC_ACSLTDIS 0xf74c -#define TX4927_ACLC_ACFIFOSTS 0xf750 -#define TX4927_ACLC_ACDMASTS 0xf780 -#define TX4927_ACLC_ACDMASEL 0xf784 -#define TX4927_ACLC_ACAUDODAT 0xf7a0 -#define TX4927_ACLC_ACSURRDAT 0xf7a4 -#define TX4927_ACLC_ACCENTDAT 0xf7a8 -#define TX4927_ACLC_ACLFEDAT 0xf7ac -#define TX4927_ACLC_ACAUDIDAT 0xf7b0 -#define TX4927_ACLC_ACMODODAT 0xf7b8 -#define TX4927_ACLC_ACMODIDAT 0xf7bc -#define TX4927_ACLC_ACREVID 0xf7fc -#define TX4927_ACLC_LIMIT 0xf7ff - - -#define TX4927_REG(x) ((TX4927_BASE)+(x)) - -#define TX4927_RD08( reg ) (*(vu08*)(reg)) -#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) - -#define TX4927_RD16( reg ) (*(vu16*)(reg)) -#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) - -#define TX4927_RD32( reg ) (*(vu32*)(reg)) -#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) - -#define TX4927_RD64( reg ) (*(vu64*)(reg)) -#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) - -#define TX4927_RD( reg ) TX4927_RD32( reg ) -#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) - - - - - -#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ -#define MI8259_IRQ_ISA_RAW_END 15 -#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */ -#define TX4927_IRQ_CP0_RAW_END 7 -#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */ -#define TX4927_IRQ_PIC_RAW_END 31 - - -#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ -#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ - -#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */ -#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */ +#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) -#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */ -#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */ +#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) #define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) diff --git a/include/asm-mips/tx4927/tx4927_mips.h b/include/asm-mips/tx4927/tx4927_mips.h deleted file mode 100644 index 242ab93bf2e2..000000000000 --- a/include/asm-mips/tx4927/tx4927_mips.h +++ /dev/null @@ -1,4177 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_MIPS_H -#define __ASM_TX4927_TX4927_MIPS_H - -#ifndef __ASSEMBLY__ - -static inline void asm_wait(void) -{ - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) -#define reg_rd16(r) ((u16)(*((vu16*)(r)))) -#define reg_rd32(r) ((u32)(*((vu32*)(r)))) -#define reg_rd64(r) ((u64)(*((vu64*)(r)))) - -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) - -typedef volatile __signed char vs8; -typedef volatile unsigned char vu8; - -typedef volatile __signed short vs16; -typedef volatile unsigned short vu16; - -typedef volatile __signed int vs32; -typedef volatile unsigned int vu32; - -typedef s8 s08; -typedef vs8 vs08; - -typedef u8 u08; -typedef vu8 vu08; - - -#if (_MIPS_SZLONG == 64) - -typedef volatile __signed__ long vs64; -typedef volatile unsigned long vu64; - -#else - -typedef volatile __signed__ long long vs64; -typedef volatile unsigned long long vu64; - -#endif - - -#define BM_00_00 0x0000000000000001 -#define BM_01_00 0x0000000000000003 -#define BM_00_01 BM_01_00 -#define BM_02_00 0x0000000000000007 -#define BM_00_02 BM_02_00 -#define BM_03_00 0x000000000000000f -#define BM_00_03 BM_03_00 -#define BM_04_00 0x000000000000001f -#define BM_00_04 BM_04_00 -#define BM_05_00 0x000000000000003f -#define BM_00_05 BM_05_00 -#define BM_06_00 0x000000000000007f -#define BM_00_06 BM_06_00 -#define BM_07_00 0x00000000000000ff -#define BM_00_07 BM_07_00 -#define BM_08_00 0x00000000000001ff -#define BM_00_08 BM_08_00 -#define BM_09_00 0x00000000000003ff -#define BM_00_09 BM_09_00 -#define BM_10_00 0x00000000000007ff -#define BM_00_10 BM_10_00 -#define BM_11_00 0x0000000000000fff -#define BM_00_11 BM_11_00 -#define BM_12_00 0x0000000000001fff -#define BM_00_12 BM_12_00 -#define BM_13_00 0x0000000000003fff -#define BM_00_13 BM_13_00 -#define BM_14_00 0x0000000000007fff -#define BM_00_14 BM_14_00 -#define BM_15_00 0x000000000000ffff -#define BM_00_15 BM_15_00 -#define BM_16_00 0x000000000001ffff -#define BM_00_16 BM_16_00 -#define BM_17_00 0x000000000003ffff -#define BM_00_17 BM_17_00 -#define BM_18_00 0x000000000007ffff -#define BM_00_18 BM_18_00 -#define BM_19_00 0x00000000000fffff -#define BM_00_19 BM_19_00 -#define BM_20_00 0x00000000001fffff -#define BM_00_20 BM_20_00 -#define BM_21_00 0x00000000003fffff -#define BM_00_21 BM_21_00 -#define BM_22_00 0x00000000007fffff -#define BM_00_22 BM_22_00 -#define BM_23_00 0x0000000000ffffff -#define BM_00_23 BM_23_00 -#define BM_24_00 0x0000000001ffffff -#define BM_00_24 BM_24_00 -#define BM_25_00 0x0000000003ffffff -#define BM_00_25 BM_25_00 -#define BM_26_00 0x0000000007ffffff -#define BM_00_26 BM_26_00 -#define BM_27_00 0x000000000fffffff -#define BM_00_27 BM_27_00 -#define BM_28_00 0x000000001fffffff -#define BM_00_28 BM_28_00 -#define BM_29_00 0x000000003fffffff -#define BM_00_29 BM_29_00 -#define BM_30_00 0x000000007fffffff -#define BM_00_30 BM_30_00 -#define BM_31_00 0x00000000ffffffff -#define BM_00_31 BM_31_00 -#define BM_32_00 0x00000001ffffffff -#define BM_00_32 BM_32_00 -#define BM_33_00 0x00000003ffffffff -#define BM_00_33 BM_33_00 -#define BM_34_00 0x00000007ffffffff -#define BM_00_34 BM_34_00 -#define BM_35_00 0x0000000fffffffff -#define BM_00_35 BM_35_00 -#define BM_36_00 0x0000001fffffffff -#define BM_00_36 BM_36_00 -#define BM_37_00 0x0000003fffffffff -#define BM_00_37 BM_37_00 -#define BM_38_00 0x0000007fffffffff -#define BM_00_38 BM_38_00 -#define BM_39_00 0x000000ffffffffff -#define BM_00_39 BM_39_00 -#define BM_40_00 0x000001ffffffffff -#define BM_00_40 BM_40_00 -#define BM_41_00 0x000003ffffffffff -#define BM_00_41 BM_41_00 -#define BM_42_00 0x000007ffffffffff -#define BM_00_42 BM_42_00 -#define BM_43_00 0x00000fffffffffff -#define BM_00_43 BM_43_00 -#define BM_44_00 0x00001fffffffffff -#define BM_00_44 BM_44_00 -#define BM_45_00 0x00003fffffffffff -#define BM_00_45 BM_45_00 -#define BM_46_00 0x00007fffffffffff -#define BM_00_46 BM_46_00 -#define BM_47_00 0x0000ffffffffffff -#define BM_00_47 BM_47_00 -#define BM_48_00 0x0001ffffffffffff -#define BM_00_48 BM_48_00 -#define BM_49_00 0x0003ffffffffffff -#define BM_00_49 BM_49_00 -#define BM_50_00 0x0007ffffffffffff -#define BM_00_50 BM_50_00 -#define BM_51_00 0x000fffffffffffff -#define BM_00_51 BM_51_00 -#define BM_52_00 0x001fffffffffffff -#define BM_00_52 BM_52_00 -#define BM_53_00 0x003fffffffffffff -#define BM_00_53 BM_53_00 -#define BM_54_00 0x007fffffffffffff -#define BM_00_54 BM_54_00 -#define BM_55_00 0x00ffffffffffffff -#define BM_00_55 BM_55_00 -#define BM_56_00 0x01ffffffffffffff -#define BM_00_56 BM_56_00 -#define BM_57_00 0x03ffffffffffffff -#define BM_00_57 BM_57_00 -#define BM_58_00 0x07ffffffffffffff -#define BM_00_58 BM_58_00 -#define BM_59_00 0x0fffffffffffffff -#define BM_00_59 BM_59_00 -#define BM_60_00 0x1fffffffffffffff -#define BM_00_60 BM_60_00 -#define BM_61_00 0x3fffffffffffffff -#define BM_00_61 BM_61_00 -#define BM_62_00 0x7fffffffffffffff -#define BM_00_62 BM_62_00 -#define BM_63_00 0xffffffffffffffff -#define BM_00_63 BM_63_00 -#define BM_01_01 0x0000000000000002 -#define BM_02_01 0x0000000000000006 -#define BM_01_02 BM_02_01 -#define BM_03_01 0x000000000000000e -#define BM_01_03 BM_03_01 -#define BM_04_01 0x000000000000001e -#define BM_01_04 BM_04_01 -#define BM_05_01 0x000000000000003e -#define BM_01_05 BM_05_01 -#define BM_06_01 0x000000000000007e -#define BM_01_06 BM_06_01 -#define BM_07_01 0x00000000000000fe -#define BM_01_07 BM_07_01 -#define BM_08_01 0x00000000000001fe -#define BM_01_08 BM_08_01 -#define BM_09_01 0x00000000000003fe -#define BM_01_09 BM_09_01 -#define BM_10_01 0x00000000000007fe -#define BM_01_10 BM_10_01 -#define BM_11_01 0x0000000000000ffe -#define BM_01_11 BM_11_01 -#define BM_12_01 0x0000000000001ffe -#define BM_01_12 BM_12_01 -#define BM_13_01 0x0000000000003ffe -#define BM_01_13 BM_13_01 -#define BM_14_01 0x0000000000007ffe -#define BM_01_14 BM_14_01 -#define BM_15_01 0x000000000000fffe -#define BM_01_15 BM_15_01 -#define BM_16_01 0x000000000001fffe -#define BM_01_16 BM_16_01 -#define BM_17_01 0x000000000003fffe -#define BM_01_17 BM_17_01 -#define BM_18_01 0x000000000007fffe -#define BM_01_18 BM_18_01 -#define BM_19_01 0x00000000000ffffe -#define BM_01_19 BM_19_01 -#define BM_20_01 0x00000000001ffffe -#define BM_01_20 BM_20_01 -#define BM_21_01 0x00000000003ffffe -#define BM_01_21 BM_21_01 -#define BM_22_01 0x00000000007ffffe -#define BM_01_22 BM_22_01 -#define BM_23_01 0x0000000000fffffe -#define BM_01_23 BM_23_01 -#define BM_24_01 0x0000000001fffffe -#define BM_01_24 BM_24_01 -#define BM_25_01 0x0000000003fffffe -#define BM_01_25 BM_25_01 -#define BM_26_01 0x0000000007fffffe -#define BM_01_26 BM_26_01 -#define BM_27_01 0x000000000ffffffe -#define BM_01_27 BM_27_01 -#define BM_28_01 0x000000001ffffffe -#define BM_01_28 BM_28_01 -#define BM_29_01 0x000000003ffffffe -#define BM_01_29 BM_29_01 -#define BM_30_01 0x000000007ffffffe -#define BM_01_30 BM_30_01 -#define BM_31_01 0x00000000fffffffe -#define BM_01_31 BM_31_01 -#define BM_32_01 0x00000001fffffffe -#define BM_01_32 BM_32_01 -#define BM_33_01 0x00000003fffffffe -#define BM_01_33 BM_33_01 -#define BM_34_01 0x00000007fffffffe -#define BM_01_34 BM_34_01 -#define BM_35_01 0x0000000ffffffffe -#define BM_01_35 BM_35_01 -#define BM_36_01 0x0000001ffffffffe -#define BM_01_36 BM_36_01 -#define BM_37_01 0x0000003ffffffffe -#define BM_01_37 BM_37_01 -#define BM_38_01 0x0000007ffffffffe -#define BM_01_38 BM_38_01 -#define BM_39_01 0x000000fffffffffe -#define BM_01_39 BM_39_01 -#define BM_40_01 0x000001fffffffffe -#define BM_01_40 BM_40_01 -#define BM_41_01 0x000003fffffffffe -#define BM_01_41 BM_41_01 -#define BM_42_01 0x000007fffffffffe -#define BM_01_42 BM_42_01 -#define BM_43_01 0x00000ffffffffffe -#define BM_01_43 BM_43_01 -#define BM_44_01 0x00001ffffffffffe -#define BM_01_44 BM_44_01 -#define BM_45_01 0x00003ffffffffffe -#define BM_01_45 BM_45_01 -#define BM_46_01 0x00007ffffffffffe -#define BM_01_46 BM_46_01 -#define BM_47_01 0x0000fffffffffffe -#define BM_01_47 BM_47_01 -#define BM_48_01 0x0001fffffffffffe -#define BM_01_48 BM_48_01 -#define BM_49_01 0x0003fffffffffffe -#define BM_01_49 BM_49_01 -#define BM_50_01 0x0007fffffffffffe -#define BM_01_50 BM_50_01 -#define BM_51_01 0x000ffffffffffffe -#define BM_01_51 BM_51_01 -#define BM_52_01 0x001ffffffffffffe -#define BM_01_52 BM_52_01 -#define BM_53_01 0x003ffffffffffffe -#define BM_01_53 BM_53_01 -#define BM_54_01 0x007ffffffffffffe -#define BM_01_54 BM_54_01 -#define BM_55_01 0x00fffffffffffffe -#define BM_01_55 BM_55_01 -#define BM_56_01 0x01fffffffffffffe -#define BM_01_56 BM_56_01 -#define BM_57_01 0x03fffffffffffffe -#define BM_01_57 BM_57_01 -#define BM_58_01 0x07fffffffffffffe -#define BM_01_58 BM_58_01 -#define BM_59_01 0x0ffffffffffffffe -#define BM_01_59 BM_59_01 -#define BM_60_01 0x1ffffffffffffffe -#define BM_01_60 BM_60_01 -#define BM_61_01 0x3ffffffffffffffe -#define BM_01_61 BM_61_01 -#define BM_62_01 0x7ffffffffffffffe -#define BM_01_62 BM_62_01 -#define BM_63_01 0xfffffffffffffffe -#define BM_01_63 BM_63_01 -#define BM_02_02 0x0000000000000004 -#define BM_03_02 0x000000000000000c -#define BM_02_03 BM_03_02 -#define BM_04_02 0x000000000000001c -#define BM_02_04 BM_04_02 -#define BM_05_02 0x000000000000003c -#define BM_02_05 BM_05_02 -#define BM_06_02 0x000000000000007c -#define BM_02_06 BM_06_02 -#define BM_07_02 0x00000000000000fc -#define BM_02_07 BM_07_02 -#define BM_08_02 0x00000000000001fc -#define BM_02_08 BM_08_02 -#define BM_09_02 0x00000000000003fc -#define BM_02_09 BM_09_02 -#define BM_10_02 0x00000000000007fc -#define BM_02_10 BM_10_02 -#define BM_11_02 0x0000000000000ffc -#define BM_02_11 BM_11_02 -#define BM_12_02 0x0000000000001ffc -#define BM_02_12 BM_12_02 -#define BM_13_02 0x0000000000003ffc -#define BM_02_13 BM_13_02 -#define BM_14_02 0x0000000000007ffc -#define BM_02_14 BM_14_02 -#define BM_15_02 0x000000000000fffc -#define BM_02_15 BM_15_02 -#define BM_16_02 0x000000000001fffc -#define BM_02_16 BM_16_02 -#define BM_17_02 0x000000000003fffc -#define BM_02_17 BM_17_02 -#define BM_18_02 0x000000000007fffc -#define BM_02_18 BM_18_02 -#define BM_19_02 0x00000000000ffffc -#define BM_02_19 BM_19_02 -#define BM_20_02 0x00000000001ffffc -#define BM_02_20 BM_20_02 -#define BM_21_02 0x00000000003ffffc -#define BM_02_21 BM_21_02 -#define BM_22_02 0x00000000007ffffc -#define BM_02_22 BM_22_02 -#define BM_23_02 0x0000000000fffffc -#define BM_02_23 BM_23_02 -#define BM_24_02 0x0000000001fffffc -#define BM_02_24 BM_24_02 -#define BM_25_02 0x0000000003fffffc -#define BM_02_25 BM_25_02 -#define BM_26_02 0x0000000007fffffc -#define BM_02_26 BM_26_02 -#define BM_27_02 0x000000000ffffffc -#define BM_02_27 BM_27_02 -#define BM_28_02 0x000000001ffffffc -#define BM_02_28 BM_28_02 -#define BM_29_02 0x000000003ffffffc -#define BM_02_29 BM_29_02 -#define BM_30_02 0x000000007ffffffc -#define BM_02_30 BM_30_02 -#define BM_31_02 0x00000000fffffffc -#define BM_02_31 BM_31_02 -#define BM_32_02 0x00000001fffffffc -#define BM_02_32 BM_32_02 -#define BM_33_02 0x00000003fffffffc -#define BM_02_33 BM_33_02 -#define BM_34_02 0x00000007fffffffc -#define BM_02_34 BM_34_02 -#define BM_35_02 0x0000000ffffffffc -#define BM_02_35 BM_35_02 -#define BM_36_02 0x0000001ffffffffc -#define BM_02_36 BM_36_02 -#define BM_37_02 0x0000003ffffffffc -#define BM_02_37 BM_37_02 -#define BM_38_02 0x0000007ffffffffc -#define BM_02_38 BM_38_02 -#define BM_39_02 0x000000fffffffffc -#define BM_02_39 BM_39_02 -#define BM_40_02 0x000001fffffffffc -#define BM_02_40 BM_40_02 -#define BM_41_02 0x000003fffffffffc -#define BM_02_41 BM_41_02 -#define BM_42_02 0x000007fffffffffc -#define BM_02_42 BM_42_02 -#define BM_43_02 0x00000ffffffffffc -#define BM_02_43 BM_43_02 -#define BM_44_02 0x00001ffffffffffc -#define BM_02_44 BM_44_02 -#define BM_45_02 0x00003ffffffffffc -#define BM_02_45 BM_45_02 -#define BM_46_02 0x00007ffffffffffc -#define BM_02_46 BM_46_02 -#define BM_47_02 0x0000fffffffffffc -#define BM_02_47 BM_47_02 -#define BM_48_02 0x0001fffffffffffc -#define BM_02_48 BM_48_02 -#define BM_49_02 0x0003fffffffffffc -#define BM_02_49 BM_49_02 -#define BM_50_02 0x0007fffffffffffc -#define BM_02_50 BM_50_02 -#define BM_51_02 0x000ffffffffffffc -#define BM_02_51 BM_51_02 -#define BM_52_02 0x001ffffffffffffc -#define BM_02_52 BM_52_02 -#define BM_53_02 0x003ffffffffffffc -#define BM_02_53 BM_53_02 -#define BM_54_02 0x007ffffffffffffc -#define BM_02_54 BM_54_02 -#define BM_55_02 0x00fffffffffffffc -#define BM_02_55 BM_55_02 -#define BM_56_02 0x01fffffffffffffc -#define BM_02_56 BM_56_02 -#define BM_57_02 0x03fffffffffffffc -#define BM_02_57 BM_57_02 -#define BM_58_02 0x07fffffffffffffc -#define BM_02_58 BM_58_02 -#define BM_59_02 0x0ffffffffffffffc -#define BM_02_59 BM_59_02 -#define BM_60_02 0x1ffffffffffffffc -#define BM_02_60 BM_60_02 -#define BM_61_02 0x3ffffffffffffffc -#define BM_02_61 BM_61_02 -#define BM_62_02 0x7ffffffffffffffc -#define BM_02_62 BM_62_02 -#define BM_63_02 0xfffffffffffffffc -#define BM_02_63 BM_63_02 -#define BM_03_03 0x0000000000000008 -#define BM_04_03 0x0000000000000018 -#define BM_03_04 BM_04_03 -#define BM_05_03 0x0000000000000038 -#define BM_03_05 BM_05_03 -#define BM_06_03 0x0000000000000078 -#define BM_03_06 BM_06_03 -#define BM_07_03 0x00000000000000f8 -#define BM_03_07 BM_07_03 -#define BM_08_03 0x00000000000001f8 -#define BM_03_08 BM_08_03 -#define BM_09_03 0x00000000000003f8 -#define BM_03_09 BM_09_03 -#define BM_10_03 0x00000000000007f8 -#define BM_03_10 BM_10_03 -#define BM_11_03 0x0000000000000ff8 -#define BM_03_11 BM_11_03 -#define BM_12_03 0x0000000000001ff8 -#define BM_03_12 BM_12_03 -#define BM_13_03 0x0000000000003ff8 -#define BM_03_13 BM_13_03 -#define BM_14_03 0x0000000000007ff8 -#define BM_03_14 BM_14_03 -#define BM_15_03 0x000000000000fff8 -#define BM_03_15 BM_15_03 -#define BM_16_03 0x000000000001fff8 -#define BM_03_16 BM_16_03 -#define BM_17_03 0x000000000003fff8 -#define BM_03_17 BM_17_03 -#define BM_18_03 0x000000000007fff8 -#define BM_03_18 BM_18_03 -#define BM_19_03 0x00000000000ffff8 -#define BM_03_19 BM_19_03 -#define BM_20_03 0x00000000001ffff8 -#define BM_03_20 BM_20_03 -#define BM_21_03 0x00000000003ffff8 -#define BM_03_21 BM_21_03 -#define BM_22_03 0x00000000007ffff8 -#define BM_03_22 BM_22_03 -#define BM_23_03 0x0000000000fffff8 -#define BM_03_23 BM_23_03 -#define BM_24_03 0x0000000001fffff8 -#define BM_03_24 BM_24_03 -#define BM_25_03 0x0000000003fffff8 -#define BM_03_25 BM_25_03 -#define BM_26_03 0x0000000007fffff8 -#define BM_03_26 BM_26_03 -#define BM_27_03 0x000000000ffffff8 -#define BM_03_27 BM_27_03 -#define BM_28_03 0x000000001ffffff8 -#define BM_03_28 BM_28_03 -#define BM_29_03 0x000000003ffffff8 -#define BM_03_29 BM_29_03 -#define BM_30_03 0x000000007ffffff8 -#define BM_03_30 BM_30_03 -#define BM_31_03 0x00000000fffffff8 -#define BM_03_31 BM_31_03 -#define BM_32_03 0x00000001fffffff8 -#define BM_03_32 BM_32_03 -#define BM_33_03 0x00000003fffffff8 -#define BM_03_33 BM_33_03 -#define BM_34_03 0x00000007fffffff8 -#define BM_03_34 BM_34_03 -#define BM_35_03 0x0000000ffffffff8 -#define BM_03_35 BM_35_03 -#define BM_36_03 0x0000001ffffffff8 -#define BM_03_36 BM_36_03 -#define BM_37_03 0x0000003ffffffff8 -#define BM_03_37 BM_37_03 -#define BM_38_03 0x0000007ffffffff8 -#define BM_03_38 BM_38_03 -#define BM_39_03 0x000000fffffffff8 -#define BM_03_39 BM_39_03 -#define BM_40_03 0x000001fffffffff8 -#define BM_03_40 BM_40_03 -#define BM_41_03 0x000003fffffffff8 -#define BM_03_41 BM_41_03 -#define BM_42_03 0x000007fffffffff8 -#define BM_03_42 BM_42_03 -#define BM_43_03 0x00000ffffffffff8 -#define BM_03_43 BM_43_03 -#define BM_44_03 0x00001ffffffffff8 -#define BM_03_44 BM_44_03 -#define BM_45_03 0x00003ffffffffff8 -#define BM_03_45 BM_45_03 -#define BM_46_03 0x00007ffffffffff8 -#define BM_03_46 BM_46_03 -#define BM_47_03 0x0000fffffffffff8 -#define BM_03_47 BM_47_03 -#define BM_48_03 0x0001fffffffffff8 -#define BM_03_48 BM_48_03 -#define BM_49_03 0x0003fffffffffff8 -#define BM_03_49 BM_49_03 -#define BM_50_03 0x0007fffffffffff8 -#define BM_03_50 BM_50_03 -#define BM_51_03 0x000ffffffffffff8 -#define BM_03_51 BM_51_03 -#define BM_52_03 0x001ffffffffffff8 -#define BM_03_52 BM_52_03 -#define BM_53_03 0x003ffffffffffff8 -#define BM_03_53 BM_53_03 -#define BM_54_03 0x007ffffffffffff8 -#define BM_03_54 BM_54_03 -#define BM_55_03 0x00fffffffffffff8 -#define BM_03_55 BM_55_03 -#define BM_56_03 0x01fffffffffffff8 -#define BM_03_56 BM_56_03 -#define BM_57_03 0x03fffffffffffff8 -#define BM_03_57 BM_57_03 -#define BM_58_03 0x07fffffffffffff8 -#define BM_03_58 BM_58_03 -#define BM_59_03 0x0ffffffffffffff8 -#define BM_03_59 BM_59_03 -#define BM_60_03 0x1ffffffffffffff8 -#define BM_03_60 BM_60_03 -#define BM_61_03 0x3ffffffffffffff8 -#define BM_03_61 BM_61_03 -#define BM_62_03 0x7ffffffffffffff8 -#define BM_03_62 BM_62_03 -#define BM_63_03 0xfffffffffffffff8 -#define BM_03_63 BM_63_03 -#define BM_04_04 0x0000000000000010 -#define BM_05_04 0x0000000000000030 -#define BM_04_05 BM_05_04 -#define BM_06_04 0x0000000000000070 -#define BM_04_06 BM_06_04 -#define BM_07_04 0x00000000000000f0 -#define BM_04_07 BM_07_04 -#define BM_08_04 0x00000000000001f0 -#define BM_04_08 BM_08_04 -#define BM_09_04 0x00000000000003f0 -#define BM_04_09 BM_09_04 -#define BM_10_04 0x00000000000007f0 -#define BM_04_10 BM_10_04 -#define BM_11_04 0x0000000000000ff0 -#define BM_04_11 BM_11_04 -#define BM_12_04 0x0000000000001ff0 -#define BM_04_12 BM_12_04 -#define BM_13_04 0x0000000000003ff0 -#define BM_04_13 BM_13_04 -#define BM_14_04 0x0000000000007ff0 -#define BM_04_14 BM_14_04 -#define BM_15_04 0x000000000000fff0 -#define BM_04_15 BM_15_04 -#define BM_16_04 0x000000000001fff0 -#define BM_04_16 BM_16_04 -#define BM_17_04 0x000000000003fff0 -#define BM_04_17 BM_17_04 -#define BM_18_04 0x000000000007fff0 -#define BM_04_18 BM_18_04 -#define BM_19_04 0x00000000000ffff0 -#define BM_04_19 BM_19_04 -#define BM_20_04 0x00000000001ffff0 -#define BM_04_20 BM_20_04 -#define BM_21_04 0x00000000003ffff0 -#define BM_04_21 BM_21_04 -#define BM_22_04 0x00000000007ffff0 -#define BM_04_22 BM_22_04 -#define BM_23_04 0x0000000000fffff0 -#define BM_04_23 BM_23_04 -#define BM_24_04 0x0000000001fffff0 -#define BM_04_24 BM_24_04 -#define BM_25_04 0x0000000003fffff0 -#define BM_04_25 BM_25_04 -#define BM_26_04 0x0000000007fffff0 -#define BM_04_26 BM_26_04 -#define BM_27_04 0x000000000ffffff0 -#define BM_04_27 BM_27_04 -#define BM_28_04 0x000000001ffffff0 -#define BM_04_28 BM_28_04 -#define BM_29_04 0x000000003ffffff0 -#define BM_04_29 BM_29_04 -#define BM_30_04 0x000000007ffffff0 -#define BM_04_30 BM_30_04 -#define BM_31_04 0x00000000fffffff0 -#define BM_04_31 BM_31_04 -#define BM_32_04 0x00000001fffffff0 -#define BM_04_32 BM_32_04 -#define BM_33_04 0x00000003fffffff0 -#define BM_04_33 BM_33_04 -#define BM_34_04 0x00000007fffffff0 -#define BM_04_34 BM_34_04 -#define BM_35_04 0x0000000ffffffff0 -#define BM_04_35 BM_35_04 -#define BM_36_04 0x0000001ffffffff0 -#define BM_04_36 BM_36_04 -#define BM_37_04 0x0000003ffffffff0 -#define BM_04_37 BM_37_04 -#define BM_38_04 0x0000007ffffffff0 -#define BM_04_38 BM_38_04 -#define BM_39_04 0x000000fffffffff0 -#define BM_04_39 BM_39_04 -#define BM_40_04 0x000001fffffffff0 -#define BM_04_40 BM_40_04 -#define BM_41_04 0x000003fffffffff0 -#define BM_04_41 BM_41_04 -#define BM_42_04 0x000007fffffffff0 -#define BM_04_42 BM_42_04 -#define BM_43_04 0x00000ffffffffff0 -#define BM_04_43 BM_43_04 -#define BM_44_04 0x00001ffffffffff0 -#define BM_04_44 BM_44_04 -#define BM_45_04 0x00003ffffffffff0 -#define BM_04_45 BM_45_04 -#define BM_46_04 0x00007ffffffffff0 -#define BM_04_46 BM_46_04 -#define BM_47_04 0x0000fffffffffff0 -#define BM_04_47 BM_47_04 -#define BM_48_04 0x0001fffffffffff0 -#define BM_04_48 BM_48_04 -#define BM_49_04 0x0003fffffffffff0 -#define BM_04_49 BM_49_04 -#define BM_50_04 0x0007fffffffffff0 -#define BM_04_50 BM_50_04 -#define BM_51_04 0x000ffffffffffff0 -#define BM_04_51 BM_51_04 -#define BM_52_04 0x001ffffffffffff0 -#define BM_04_52 BM_52_04 -#define BM_53_04 0x003ffffffffffff0 -#define BM_04_53 BM_53_04 -#define BM_54_04 0x007ffffffffffff0 -#define BM_04_54 BM_54_04 -#define BM_55_04 0x00fffffffffffff0 -#define BM_04_55 BM_55_04 -#define BM_56_04 0x01fffffffffffff0 -#define BM_04_56 BM_56_04 -#define BM_57_04 0x03fffffffffffff0 -#define BM_04_57 BM_57_04 -#define BM_58_04 0x07fffffffffffff0 -#define BM_04_58 BM_58_04 -#define BM_59_04 0x0ffffffffffffff0 -#define BM_04_59 BM_59_04 -#define BM_60_04 0x1ffffffffffffff0 -#define BM_04_60 BM_60_04 -#define BM_61_04 0x3ffffffffffffff0 -#define BM_04_61 BM_61_04 -#define BM_62_04 0x7ffffffffffffff0 -#define BM_04_62 BM_62_04 -#define BM_63_04 0xfffffffffffffff0 -#define BM_04_63 BM_63_04 -#define BM_05_05 0x0000000000000020 -#define BM_06_05 0x0000000000000060 -#define BM_05_06 BM_06_05 -#define BM_07_05 0x00000000000000e0 -#define BM_05_07 BM_07_05 -#define BM_08_05 0x00000000000001e0 -#define BM_05_08 BM_08_05 -#define BM_09_05 0x00000000000003e0 -#define BM_05_09 BM_09_05 -#define BM_10_05 0x00000000000007e0 -#define BM_05_10 BM_10_05 -#define BM_11_05 0x0000000000000fe0 -#define BM_05_11 BM_11_05 -#define BM_12_05 0x0000000000001fe0 -#define BM_05_12 BM_12_05 -#define BM_13_05 0x0000000000003fe0 -#define BM_05_13 BM_13_05 -#define BM_14_05 0x0000000000007fe0 -#define BM_05_14 BM_14_05 -#define BM_15_05 0x000000000000ffe0 -#define BM_05_15 BM_15_05 -#define BM_16_05 0x000000000001ffe0 -#define BM_05_16 BM_16_05 -#define BM_17_05 0x000000000003ffe0 -#define BM_05_17 BM_17_05 -#define BM_18_05 0x000000000007ffe0 -#define BM_05_18 BM_18_05 -#define BM_19_05 0x00000000000fffe0 -#define BM_05_19 BM_19_05 -#define BM_20_05 0x00000000001fffe0 -#define BM_05_20 BM_20_05 -#define BM_21_05 0x00000000003fffe0 -#define BM_05_21 BM_21_05 -#define BM_22_05 0x00000000007fffe0 -#define BM_05_22 BM_22_05 -#define BM_23_05 0x0000000000ffffe0 -#define BM_05_23 BM_23_05 -#define BM_24_05 0x0000000001ffffe0 -#define BM_05_24 BM_24_05 -#define BM_25_05 0x0000000003ffffe0 -#define BM_05_25 BM_25_05 -#define BM_26_05 0x0000000007ffffe0 -#define BM_05_26 BM_26_05 -#define BM_27_05 0x000000000fffffe0 -#define BM_05_27 BM_27_05 -#define BM_28_05 0x000000001fffffe0 -#define BM_05_28 BM_28_05 -#define BM_29_05 0x000000003fffffe0 -#define BM_05_29 BM_29_05 -#define BM_30_05 0x000000007fffffe0 -#define BM_05_30 BM_30_05 -#define BM_31_05 0x00000000ffffffe0 -#define BM_05_31 BM_31_05 -#define BM_32_05 0x00000001ffffffe0 -#define BM_05_32 BM_32_05 -#define BM_33_05 0x00000003ffffffe0 -#define BM_05_33 BM_33_05 -#define BM_34_05 0x00000007ffffffe0 -#define BM_05_34 BM_34_05 -#define BM_35_05 0x0000000fffffffe0 -#define BM_05_35 BM_35_05 -#define BM_36_05 0x0000001fffffffe0 -#define BM_05_36 BM_36_05 -#define BM_37_05 0x0000003fffffffe0 -#define BM_05_37 BM_37_05 -#define BM_38_05 0x0000007fffffffe0 -#define BM_05_38 BM_38_05 -#define BM_39_05 0x000000ffffffffe0 -#define BM_05_39 BM_39_05 -#define BM_40_05 0x000001ffffffffe0 -#define BM_05_40 BM_40_05 -#define BM_41_05 0x000003ffffffffe0 -#define BM_05_41 BM_41_05 -#define BM_42_05 0x000007ffffffffe0 -#define BM_05_42 BM_42_05 -#define BM_43_05 0x00000fffffffffe0 -#define BM_05_43 BM_43_05 -#define BM_44_05 0x00001fffffffffe0 -#define BM_05_44 BM_44_05 -#define BM_45_05 0x00003fffffffffe0 -#define BM_05_45 BM_45_05 -#define BM_46_05 0x00007fffffffffe0 -#define BM_05_46 BM_46_05 -#define BM_47_05 0x0000ffffffffffe0 -#define BM_05_47 BM_47_05 -#define BM_48_05 0x0001ffffffffffe0 -#define BM_05_48 BM_48_05 -#define BM_49_05 0x0003ffffffffffe0 -#define BM_05_49 BM_49_05 -#define BM_50_05 0x0007ffffffffffe0 -#define BM_05_50 BM_50_05 -#define BM_51_05 0x000fffffffffffe0 -#define BM_05_51 BM_51_05 -#define BM_52_05 0x001fffffffffffe0 -#define BM_05_52 BM_52_05 -#define BM_53_05 0x003fffffffffffe0 -#define BM_05_53 BM_53_05 -#define BM_54_05 0x007fffffffffffe0 -#define BM_05_54 BM_54_05 -#define BM_55_05 0x00ffffffffffffe0 -#define BM_05_55 BM_55_05 -#define BM_56_05 0x01ffffffffffffe0 -#define BM_05_56 BM_56_05 -#define BM_57_05 0x03ffffffffffffe0 -#define BM_05_57 BM_57_05 -#define BM_58_05 0x07ffffffffffffe0 -#define BM_05_58 BM_58_05 -#define BM_59_05 0x0fffffffffffffe0 -#define BM_05_59 BM_59_05 -#define BM_60_05 0x1fffffffffffffe0 -#define BM_05_60 BM_60_05 -#define BM_61_05 0x3fffffffffffffe0 -#define BM_05_61 BM_61_05 -#define BM_62_05 0x7fffffffffffffe0 -#define BM_05_62 BM_62_05 -#define BM_63_05 0xffffffffffffffe0 -#define BM_05_63 BM_63_05 -#define BM_06_06 0x0000000000000040 -#define BM_07_06 0x00000000000000c0 -#define BM_06_07 BM_07_06 -#define BM_08_06 0x00000000000001c0 -#define BM_06_08 BM_08_06 -#define BM_09_06 0x00000000000003c0 -#define BM_06_09 BM_09_06 -#define BM_10_06 0x00000000000007c0 -#define BM_06_10 BM_10_06 -#define BM_11_06 0x0000000000000fc0 -#define BM_06_11 BM_11_06 -#define BM_12_06 0x0000000000001fc0 -#define BM_06_12 BM_12_06 -#define BM_13_06 0x0000000000003fc0 -#define BM_06_13 BM_13_06 -#define BM_14_06 0x0000000000007fc0 -#define BM_06_14 BM_14_06 -#define BM_15_06 0x000000000000ffc0 -#define BM_06_15 BM_15_06 -#define BM_16_06 0x000000000001ffc0 -#define BM_06_16 BM_16_06 -#define BM_17_06 0x000000000003ffc0 -#define BM_06_17 BM_17_06 -#define BM_18_06 0x000000000007ffc0 -#define BM_06_18 BM_18_06 -#define BM_19_06 0x00000000000fffc0 -#define BM_06_19 BM_19_06 -#define BM_20_06 0x00000000001fffc0 -#define BM_06_20 BM_20_06 -#define BM_21_06 0x00000000003fffc0 -#define BM_06_21 BM_21_06 -#define BM_22_06 0x00000000007fffc0 -#define BM_06_22 BM_22_06 -#define BM_23_06 0x0000000000ffffc0 -#define BM_06_23 BM_23_06 -#define BM_24_06 0x0000000001ffffc0 -#define BM_06_24 BM_24_06 -#define BM_25_06 0x0000000003ffffc0 -#define BM_06_25 BM_25_06 -#define BM_26_06 0x0000000007ffffc0 -#define BM_06_26 BM_26_06 -#define BM_27_06 0x000000000fffffc0 -#define BM_06_27 BM_27_06 -#define BM_28_06 0x000000001fffffc0 -#define BM_06_28 BM_28_06 -#define BM_29_06 0x000000003fffffc0 -#define BM_06_29 BM_29_06 -#define BM_30_06 0x000000007fffffc0 -#define BM_06_30 BM_30_06 -#define BM_31_06 0x00000000ffffffc0 -#define BM_06_31 BM_31_06 -#define BM_32_06 0x00000001ffffffc0 -#define BM_06_32 BM_32_06 -#define BM_33_06 0x00000003ffffffc0 -#define BM_06_33 BM_33_06 -#define BM_34_06 0x00000007ffffffc0 -#define BM_06_34 BM_34_06 -#define BM_35_06 0x0000000fffffffc0 -#define BM_06_35 BM_35_06 -#define BM_36_06 0x0000001fffffffc0 -#define BM_06_36 BM_36_06 -#define BM_37_06 0x0000003fffffffc0 -#define BM_06_37 BM_37_06 -#define BM_38_06 0x0000007fffffffc0 -#define BM_06_38 BM_38_06 -#define BM_39_06 0x000000ffffffffc0 -#define BM_06_39 BM_39_06 -#define BM_40_06 0x000001ffffffffc0 -#define BM_06_40 BM_40_06 -#define BM_41_06 0x000003ffffffffc0 -#define BM_06_41 BM_41_06 -#define BM_42_06 0x000007ffffffffc0 -#define BM_06_42 BM_42_06 -#define BM_43_06 0x00000fffffffffc0 -#define BM_06_43 BM_43_06 -#define BM_44_06 0x00001fffffffffc0 -#define BM_06_44 BM_44_06 -#define BM_45_06 0x00003fffffffffc0 -#define BM_06_45 BM_45_06 -#define BM_46_06 0x00007fffffffffc0 -#define BM_06_46 BM_46_06 -#define BM_47_06 0x0000ffffffffffc0 -#define BM_06_47 BM_47_06 -#define BM_48_06 0x0001ffffffffffc0 -#define BM_06_48 BM_48_06 -#define BM_49_06 0x0003ffffffffffc0 -#define BM_06_49 BM_49_06 -#define BM_50_06 0x0007ffffffffffc0 -#define BM_06_50 BM_50_06 -#define BM_51_06 0x000fffffffffffc0 -#define BM_06_51 BM_51_06 -#define BM_52_06 0x001fffffffffffc0 -#define BM_06_52 BM_52_06 -#define BM_53_06 0x003fffffffffffc0 -#define BM_06_53 BM_53_06 -#define BM_54_06 0x007fffffffffffc0 -#define BM_06_54 BM_54_06 -#define BM_55_06 0x00ffffffffffffc0 -#define BM_06_55 BM_55_06 -#define BM_56_06 0x01ffffffffffffc0 -#define BM_06_56 BM_56_06 -#define BM_57_06 0x03ffffffffffffc0 -#define BM_06_57 BM_57_06 -#define BM_58_06 0x07ffffffffffffc0 -#define BM_06_58 BM_58_06 -#define BM_59_06 0x0fffffffffffffc0 -#define BM_06_59 BM_59_06 -#define BM_60_06 0x1fffffffffffffc0 -#define BM_06_60 BM_60_06 -#define BM_61_06 0x3fffffffffffffc0 -#define BM_06_61 BM_61_06 -#define BM_62_06 0x7fffffffffffffc0 -#define BM_06_62 BM_62_06 -#define BM_63_06 0xffffffffffffffc0 -#define BM_06_63 BM_63_06 -#define BM_07_07 0x0000000000000080 -#define BM_08_07 0x0000000000000180 -#define BM_07_08 BM_08_07 -#define BM_09_07 0x0000000000000380 -#define BM_07_09 BM_09_07 -#define BM_10_07 0x0000000000000780 -#define BM_07_10 BM_10_07 -#define BM_11_07 0x0000000000000f80 -#define BM_07_11 BM_11_07 -#define BM_12_07 0x0000000000001f80 -#define BM_07_12 BM_12_07 -#define BM_13_07 0x0000000000003f80 -#define BM_07_13 BM_13_07 -#define BM_14_07 0x0000000000007f80 -#define BM_07_14 BM_14_07 -#define BM_15_07 0x000000000000ff80 -#define BM_07_15 BM_15_07 -#define BM_16_07 0x000000000001ff80 -#define BM_07_16 BM_16_07 -#define BM_17_07 0x000000000003ff80 -#define BM_07_17 BM_17_07 -#define BM_18_07 0x000000000007ff80 -#define BM_07_18 BM_18_07 -#define BM_19_07 0x00000000000fff80 -#define BM_07_19 BM_19_07 -#define BM_20_07 0x00000000001fff80 -#define BM_07_20 BM_20_07 -#define BM_21_07 0x00000000003fff80 -#define BM_07_21 BM_21_07 -#define BM_22_07 0x00000000007fff80 -#define BM_07_22 BM_22_07 -#define BM_23_07 0x0000000000ffff80 -#define BM_07_23 BM_23_07 -#define BM_24_07 0x0000000001ffff80 -#define BM_07_24 BM_24_07 -#define BM_25_07 0x0000000003ffff80 -#define BM_07_25 BM_25_07 -#define BM_26_07 0x0000000007ffff80 -#define BM_07_26 BM_26_07 -#define BM_27_07 0x000000000fffff80 -#define BM_07_27 BM_27_07 -#define BM_28_07 0x000000001fffff80 -#define BM_07_28 BM_28_07 -#define BM_29_07 0x000000003fffff80 -#define BM_07_29 BM_29_07 -#define BM_30_07 0x000000007fffff80 -#define BM_07_30 BM_30_07 -#define BM_31_07 0x00000000ffffff80 -#define BM_07_31 BM_31_07 -#define BM_32_07 0x00000001ffffff80 -#define BM_07_32 BM_32_07 -#define BM_33_07 0x00000003ffffff80 -#define BM_07_33 BM_33_07 -#define BM_34_07 0x00000007ffffff80 -#define BM_07_34 BM_34_07 -#define BM_35_07 0x0000000fffffff80 -#define BM_07_35 BM_35_07 -#define BM_36_07 0x0000001fffffff80 -#define BM_07_36 BM_36_07 -#define BM_37_07 0x0000003fffffff80 -#define BM_07_37 BM_37_07 -#define BM_38_07 0x0000007fffffff80 -#define BM_07_38 BM_38_07 -#define BM_39_07 0x000000ffffffff80 -#define BM_07_39 BM_39_07 -#define BM_40_07 0x000001ffffffff80 -#define BM_07_40 BM_40_07 -#define BM_41_07 0x000003ffffffff80 -#define BM_07_41 BM_41_07 -#define BM_42_07 0x000007ffffffff80 -#define BM_07_42 BM_42_07 -#define BM_43_07 0x00000fffffffff80 -#define BM_07_43 BM_43_07 -#define BM_44_07 0x00001fffffffff80 -#define BM_07_44 BM_44_07 -#define BM_45_07 0x00003fffffffff80 -#define BM_07_45 BM_45_07 -#define BM_46_07 0x00007fffffffff80 -#define BM_07_46 BM_46_07 -#define BM_47_07 0x0000ffffffffff80 -#define BM_07_47 BM_47_07 -#define BM_48_07 0x0001ffffffffff80 -#define BM_07_48 BM_48_07 -#define BM_49_07 0x0003ffffffffff80 -#define BM_07_49 BM_49_07 -#define BM_50_07 0x0007ffffffffff80 -#define BM_07_50 BM_50_07 -#define BM_51_07 0x000fffffffffff80 -#define BM_07_51 BM_51_07 -#define BM_52_07 0x001fffffffffff80 -#define BM_07_52 BM_52_07 -#define BM_53_07 0x003fffffffffff80 -#define BM_07_53 BM_53_07 -#define BM_54_07 0x007fffffffffff80 -#define BM_07_54 BM_54_07 -#define BM_55_07 0x00ffffffffffff80 -#define BM_07_55 BM_55_07 -#define BM_56_07 0x01ffffffffffff80 -#define BM_07_56 BM_56_07 -#define BM_57_07 0x03ffffffffffff80 -#define BM_07_57 BM_57_07 -#define BM_58_07 0x07ffffffffffff80 -#define BM_07_58 BM_58_07 -#define BM_59_07 0x0fffffffffffff80 -#define BM_07_59 BM_59_07 -#define BM_60_07 0x1fffffffffffff80 -#define BM_07_60 BM_60_07 -#define BM_61_07 0x3fffffffffffff80 -#define BM_07_61 BM_61_07 -#define BM_62_07 0x7fffffffffffff80 -#define BM_07_62 BM_62_07 -#define BM_63_07 0xffffffffffffff80 -#define BM_07_63 BM_63_07 -#define BM_08_08 0x0000000000000100 -#define BM_09_08 0x0000000000000300 -#define BM_08_09 BM_09_08 -#define BM_10_08 0x0000000000000700 -#define BM_08_10 BM_10_08 -#define BM_11_08 0x0000000000000f00 -#define BM_08_11 BM_11_08 -#define BM_12_08 0x0000000000001f00 -#define BM_08_12 BM_12_08 -#define BM_13_08 0x0000000000003f00 -#define BM_08_13 BM_13_08 -#define BM_14_08 0x0000000000007f00 -#define BM_08_14 BM_14_08 -#define BM_15_08 0x000000000000ff00 -#define BM_08_15 BM_15_08 -#define BM_16_08 0x000000000001ff00 -#define BM_08_16 BM_16_08 -#define BM_17_08 0x000000000003ff00 -#define BM_08_17 BM_17_08 -#define BM_18_08 0x000000000007ff00 -#define BM_08_18 BM_18_08 -#define BM_19_08 0x00000000000fff00 -#define BM_08_19 BM_19_08 -#define BM_20_08 0x00000000001fff00 -#define BM_08_20 BM_20_08 -#define BM_21_08 0x00000000003fff00 -#define BM_08_21 BM_21_08 -#define BM_22_08 0x00000000007fff00 -#define BM_08_22 BM_22_08 -#define BM_23_08 0x0000000000ffff00 -#define BM_08_23 BM_23_08 -#define BM_24_08 0x0000000001ffff00 -#define BM_08_24 BM_24_08 -#define BM_25_08 0x0000000003ffff00 -#define BM_08_25 BM_25_08 -#define BM_26_08 0x0000000007ffff00 -#define BM_08_26 BM_26_08 -#define BM_27_08 0x000000000fffff00 -#define BM_08_27 BM_27_08 -#define BM_28_08 0x000000001fffff00 -#define BM_08_28 BM_28_08 -#define BM_29_08 0x000000003fffff00 -#define BM_08_29 BM_29_08 -#define BM_30_08 0x000000007fffff00 -#define BM_08_30 BM_30_08 -#define BM_31_08 0x00000000ffffff00 -#define BM_08_31 BM_31_08 -#define BM_32_08 0x00000001ffffff00 -#define BM_08_32 BM_32_08 -#define BM_33_08 0x00000003ffffff00 -#define BM_08_33 BM_33_08 -#define BM_34_08 0x00000007ffffff00 -#define BM_08_34 BM_34_08 -#define BM_35_08 0x0000000fffffff00 -#define BM_08_35 BM_35_08 -#define BM_36_08 0x0000001fffffff00 -#define BM_08_36 BM_36_08 -#define BM_37_08 0x0000003fffffff00 -#define BM_08_37 BM_37_08 -#define BM_38_08 0x0000007fffffff00 -#define BM_08_38 BM_38_08 -#define BM_39_08 0x000000ffffffff00 -#define BM_08_39 BM_39_08 -#define BM_40_08 0x000001ffffffff00 -#define BM_08_40 BM_40_08 -#define BM_41_08 0x000003ffffffff00 -#define BM_08_41 BM_41_08 -#define BM_42_08 0x000007ffffffff00 -#define BM_08_42 BM_42_08 -#define BM_43_08 0x00000fffffffff00 -#define BM_08_43 BM_43_08 -#define BM_44_08 0x00001fffffffff00 -#define BM_08_44 BM_44_08 -#define BM_45_08 0x00003fffffffff00 -#define BM_08_45 BM_45_08 -#define BM_46_08 0x00007fffffffff00 -#define BM_08_46 BM_46_08 -#define BM_47_08 0x0000ffffffffff00 -#define BM_08_47 BM_47_08 -#define BM_48_08 0x0001ffffffffff00 -#define BM_08_48 BM_48_08 -#define BM_49_08 0x0003ffffffffff00 -#define BM_08_49 BM_49_08 -#define BM_50_08 0x0007ffffffffff00 -#define BM_08_50 BM_50_08 -#define BM_51_08 0x000fffffffffff00 -#define BM_08_51 BM_51_08 -#define BM_52_08 0x001fffffffffff00 -#define BM_08_52 BM_52_08 -#define BM_53_08 0x003fffffffffff00 -#define BM_08_53 BM_53_08 -#define BM_54_08 0x007fffffffffff00 -#define BM_08_54 BM_54_08 -#define BM_55_08 0x00ffffffffffff00 -#define BM_08_55 BM_55_08 -#define BM_56_08 0x01ffffffffffff00 -#define BM_08_56 BM_56_08 -#define BM_57_08 0x03ffffffffffff00 -#define BM_08_57 BM_57_08 -#define BM_58_08 0x07ffffffffffff00 -#define BM_08_58 BM_58_08 -#define BM_59_08 0x0fffffffffffff00 -#define BM_08_59 BM_59_08 -#define BM_60_08 0x1fffffffffffff00 -#define BM_08_60 BM_60_08 -#define BM_61_08 0x3fffffffffffff00 -#define BM_08_61 BM_61_08 -#define BM_62_08 0x7fffffffffffff00 -#define BM_08_62 BM_62_08 -#define BM_63_08 0xffffffffffffff00 -#define BM_08_63 BM_63_08 -#define BM_09_09 0x0000000000000200 -#define BM_10_09 0x0000000000000600 -#define BM_09_10 BM_10_09 -#define BM_11_09 0x0000000000000e00 -#define BM_09_11 BM_11_09 -#define BM_12_09 0x0000000000001e00 -#define BM_09_12 BM_12_09 -#define BM_13_09 0x0000000000003e00 -#define BM_09_13 BM_13_09 -#define BM_14_09 0x0000000000007e00 -#define BM_09_14 BM_14_09 -#define BM_15_09 0x000000000000fe00 -#define BM_09_15 BM_15_09 -#define BM_16_09 0x000000000001fe00 -#define BM_09_16 BM_16_09 -#define BM_17_09 0x000000000003fe00 -#define BM_09_17 BM_17_09 -#define BM_18_09 0x000000000007fe00 -#define BM_09_18 BM_18_09 -#define BM_19_09 0x00000000000ffe00 -#define BM_09_19 BM_19_09 -#define BM_20_09 0x00000000001ffe00 -#define BM_09_20 BM_20_09 -#define BM_21_09 0x00000000003ffe00 -#define BM_09_21 BM_21_09 -#define BM_22_09 0x00000000007ffe00 -#define BM_09_22 BM_22_09 -#define BM_23_09 0x0000000000fffe00 -#define BM_09_23 BM_23_09 -#define BM_24_09 0x0000000001fffe00 -#define BM_09_24 BM_24_09 -#define BM_25_09 0x0000000003fffe00 -#define BM_09_25 BM_25_09 -#define BM_26_09 0x0000000007fffe00 -#define BM_09_26 BM_26_09 -#define BM_27_09 0x000000000ffffe00 -#define BM_09_27 BM_27_09 -#define BM_28_09 0x000000001ffffe00 -#define BM_09_28 BM_28_09 -#define BM_29_09 0x000000003ffffe00 -#define BM_09_29 BM_29_09 -#define BM_30_09 0x000000007ffffe00 -#define BM_09_30 BM_30_09 -#define BM_31_09 0x00000000fffffe00 -#define BM_09_31 BM_31_09 -#define BM_32_09 0x00000001fffffe00 -#define BM_09_32 BM_32_09 -#define BM_33_09 0x00000003fffffe00 -#define BM_09_33 BM_33_09 -#define BM_34_09 0x00000007fffffe00 -#define BM_09_34 BM_34_09 -#define BM_35_09 0x0000000ffffffe00 -#define BM_09_35 BM_35_09 -#define BM_36_09 0x0000001ffffffe00 -#define BM_09_36 BM_36_09 -#define BM_37_09 0x0000003ffffffe00 -#define BM_09_37 BM_37_09 -#define BM_38_09 0x0000007ffffffe00 -#define BM_09_38 BM_38_09 -#define BM_39_09 0x000000fffffffe00 -#define BM_09_39 BM_39_09 -#define BM_40_09 0x000001fffffffe00 -#define BM_09_40 BM_40_09 -#define BM_41_09 0x000003fffffffe00 -#define BM_09_41 BM_41_09 -#define BM_42_09 0x000007fffffffe00 -#define BM_09_42 BM_42_09 -#define BM_43_09 0x00000ffffffffe00 -#define BM_09_43 BM_43_09 -#define BM_44_09 0x00001ffffffffe00 -#define BM_09_44 BM_44_09 -#define BM_45_09 0x00003ffffffffe00 -#define BM_09_45 BM_45_09 -#define BM_46_09 0x00007ffffffffe00 -#define BM_09_46 BM_46_09 -#define BM_47_09 0x0000fffffffffe00 -#define BM_09_47 BM_47_09 -#define BM_48_09 0x0001fffffffffe00 -#define BM_09_48 BM_48_09 -#define BM_49_09 0x0003fffffffffe00 -#define BM_09_49 BM_49_09 -#define BM_50_09 0x0007fffffffffe00 -#define BM_09_50 BM_50_09 -#define BM_51_09 0x000ffffffffffe00 -#define BM_09_51 BM_51_09 -#define BM_52_09 0x001ffffffffffe00 -#define BM_09_52 BM_52_09 -#define BM_53_09 0x003ffffffffffe00 -#define BM_09_53 BM_53_09 -#define BM_54_09 0x007ffffffffffe00 -#define BM_09_54 BM_54_09 -#define BM_55_09 0x00fffffffffffe00 -#define BM_09_55 BM_55_09 -#define BM_56_09 0x01fffffffffffe00 -#define BM_09_56 BM_56_09 -#define BM_57_09 0x03fffffffffffe00 -#define BM_09_57 BM_57_09 -#define BM_58_09 0x07fffffffffffe00 -#define BM_09_58 BM_58_09 -#define BM_59_09 0x0ffffffffffffe00 -#define BM_09_59 BM_59_09 -#define BM_60_09 0x1ffffffffffffe00 -#define BM_09_60 BM_60_09 -#define BM_61_09 0x3ffffffffffffe00 -#define BM_09_61 BM_61_09 -#define BM_62_09 0x7ffffffffffffe00 -#define BM_09_62 BM_62_09 -#define BM_63_09 0xfffffffffffffe00 -#define BM_09_63 BM_63_09 -#define BM_10_10 0x0000000000000400 -#define BM_11_10 0x0000000000000c00 -#define BM_10_11 BM_11_10 -#define BM_12_10 0x0000000000001c00 -#define BM_10_12 BM_12_10 -#define BM_13_10 0x0000000000003c00 -#define BM_10_13 BM_13_10 -#define BM_14_10 0x0000000000007c00 -#define BM_10_14 BM_14_10 -#define BM_15_10 0x000000000000fc00 -#define BM_10_15 BM_15_10 -#define BM_16_10 0x000000000001fc00 -#define BM_10_16 BM_16_10 -#define BM_17_10 0x000000000003fc00 -#define BM_10_17 BM_17_10 -#define BM_18_10 0x000000000007fc00 -#define BM_10_18 BM_18_10 -#define BM_19_10 0x00000000000ffc00 -#define BM_10_19 BM_19_10 -#define BM_20_10 0x00000000001ffc00 -#define BM_10_20 BM_20_10 -#define BM_21_10 0x00000000003ffc00 -#define BM_10_21 BM_21_10 -#define BM_22_10 0x00000000007ffc00 -#define BM_10_22 BM_22_10 -#define BM_23_10 0x0000000000fffc00 -#define BM_10_23 BM_23_10 -#define BM_24_10 0x0000000001fffc00 -#define BM_10_24 BM_24_10 -#define BM_25_10 0x0000000003fffc00 -#define BM_10_25 BM_25_10 -#define BM_26_10 0x0000000007fffc00 -#define BM_10_26 BM_26_10 -#define BM_27_10 0x000000000ffffc00 -#define BM_10_27 BM_27_10 -#define BM_28_10 0x000000001ffffc00 -#define BM_10_28 BM_28_10 -#define BM_29_10 0x000000003ffffc00 -#define BM_10_29 BM_29_10 -#define BM_30_10 0x000000007ffffc00 -#define BM_10_30 BM_30_10 -#define BM_31_10 0x00000000fffffc00 -#define BM_10_31 BM_31_10 -#define BM_32_10 0x00000001fffffc00 -#define BM_10_32 BM_32_10 -#define BM_33_10 0x00000003fffffc00 -#define BM_10_33 BM_33_10 -#define BM_34_10 0x00000007fffffc00 -#define BM_10_34 BM_34_10 -#define BM_35_10 0x0000000ffffffc00 -#define BM_10_35 BM_35_10 -#define BM_36_10 0x0000001ffffffc00 -#define BM_10_36 BM_36_10 -#define BM_37_10 0x0000003ffffffc00 -#define BM_10_37 BM_37_10 -#define BM_38_10 0x0000007ffffffc00 -#define BM_10_38 BM_38_10 -#define BM_39_10 0x000000fffffffc00 -#define BM_10_39 BM_39_10 -#define BM_40_10 0x000001fffffffc00 -#define BM_10_40 BM_40_10 -#define BM_41_10 0x000003fffffffc00 -#define BM_10_41 BM_41_10 -#define BM_42_10 0x000007fffffffc00 -#define BM_10_42 BM_42_10 -#define BM_43_10 0x00000ffffffffc00 -#define BM_10_43 BM_43_10 -#define BM_44_10 0x00001ffffffffc00 -#define BM_10_44 BM_44_10 -#define BM_45_10 0x00003ffffffffc00 -#define BM_10_45 BM_45_10 -#define BM_46_10 0x00007ffffffffc00 -#define BM_10_46 BM_46_10 -#define BM_47_10 0x0000fffffffffc00 -#define BM_10_47 BM_47_10 -#define BM_48_10 0x0001fffffffffc00 -#define BM_10_48 BM_48_10 -#define BM_49_10 0x0003fffffffffc00 -#define BM_10_49 BM_49_10 -#define BM_50_10 0x0007fffffffffc00 -#define BM_10_50 BM_50_10 -#define BM_51_10 0x000ffffffffffc00 -#define BM_10_51 BM_51_10 -#define BM_52_10 0x001ffffffffffc00 -#define BM_10_52 BM_52_10 -#define BM_53_10 0x003ffffffffffc00 -#define BM_10_53 BM_53_10 -#define BM_54_10 0x007ffffffffffc00 -#define BM_10_54 BM_54_10 -#define BM_55_10 0x00fffffffffffc00 -#define BM_10_55 BM_55_10 -#define BM_56_10 0x01fffffffffffc00 -#define BM_10_56 BM_56_10 -#define BM_57_10 0x03fffffffffffc00 -#define BM_10_57 BM_57_10 -#define BM_58_10 0x07fffffffffffc00 -#define BM_10_58 BM_58_10 -#define BM_59_10 0x0ffffffffffffc00 -#define BM_10_59 BM_59_10 -#define BM_60_10 0x1ffffffffffffc00 -#define BM_10_60 BM_60_10 -#define BM_61_10 0x3ffffffffffffc00 -#define BM_10_61 BM_61_10 -#define BM_62_10 0x7ffffffffffffc00 -#define BM_10_62 BM_62_10 -#define BM_63_10 0xfffffffffffffc00 -#define BM_10_63 BM_63_10 -#define BM_11_11 0x0000000000000800 -#define BM_12_11 0x0000000000001800 -#define BM_11_12 BM_12_11 -#define BM_13_11 0x0000000000003800 -#define BM_11_13 BM_13_11 -#define BM_14_11 0x0000000000007800 -#define BM_11_14 BM_14_11 -#define BM_15_11 0x000000000000f800 -#define BM_11_15 BM_15_11 -#define BM_16_11 0x000000000001f800 -#define BM_11_16 BM_16_11 -#define BM_17_11 0x000000000003f800 -#define BM_11_17 BM_17_11 -#define BM_18_11 0x000000000007f800 -#define BM_11_18 BM_18_11 -#define BM_19_11 0x00000000000ff800 -#define BM_11_19 BM_19_11 -#define BM_20_11 0x00000000001ff800 -#define BM_11_20 BM_20_11 -#define BM_21_11 0x00000000003ff800 -#define BM_11_21 BM_21_11 -#define BM_22_11 0x00000000007ff800 -#define BM_11_22 BM_22_11 -#define BM_23_11 0x0000000000fff800 -#define BM_11_23 BM_23_11 -#define BM_24_11 0x0000000001fff800 -#define BM_11_24 BM_24_11 -#define BM_25_11 0x0000000003fff800 -#define BM_11_25 BM_25_11 -#define BM_26_11 0x0000000007fff800 -#define BM_11_26 BM_26_11 -#define BM_27_11 0x000000000ffff800 -#define BM_11_27 BM_27_11 -#define BM_28_11 0x000000001ffff800 -#define BM_11_28 BM_28_11 -#define BM_29_11 0x000000003ffff800 -#define BM_11_29 BM_29_11 -#define BM_30_11 0x000000007ffff800 -#define BM_11_30 BM_30_11 -#define BM_31_11 0x00000000fffff800 -#define BM_11_31 BM_31_11 -#define BM_32_11 0x00000001fffff800 -#define BM_11_32 BM_32_11 -#define BM_33_11 0x00000003fffff800 -#define BM_11_33 BM_33_11 -#define BM_34_11 0x00000007fffff800 -#define BM_11_34 BM_34_11 -#define BM_35_11 0x0000000ffffff800 -#define BM_11_35 BM_35_11 -#define BM_36_11 0x0000001ffffff800 -#define BM_11_36 BM_36_11 -#define BM_37_11 0x0000003ffffff800 -#define BM_11_37 BM_37_11 -#define BM_38_11 0x0000007ffffff800 -#define BM_11_38 BM_38_11 -#define BM_39_11 0x000000fffffff800 -#define BM_11_39 BM_39_11 -#define BM_40_11 0x000001fffffff800 -#define BM_11_40 BM_40_11 -#define BM_41_11 0x000003fffffff800 -#define BM_11_41 BM_41_11 -#define BM_42_11 0x000007fffffff800 -#define BM_11_42 BM_42_11 -#define BM_43_11 0x00000ffffffff800 -#define BM_11_43 BM_43_11 -#define BM_44_11 0x00001ffffffff800 -#define BM_11_44 BM_44_11 -#define BM_45_11 0x00003ffffffff800 -#define BM_11_45 BM_45_11 -#define BM_46_11 0x00007ffffffff800 -#define BM_11_46 BM_46_11 -#define BM_47_11 0x0000fffffffff800 -#define BM_11_47 BM_47_11 -#define BM_48_11 0x0001fffffffff800 -#define BM_11_48 BM_48_11 -#define BM_49_11 0x0003fffffffff800 -#define BM_11_49 BM_49_11 -#define BM_50_11 0x0007fffffffff800 -#define BM_11_50 BM_50_11 -#define BM_51_11 0x000ffffffffff800 -#define BM_11_51 BM_51_11 -#define BM_52_11 0x001ffffffffff800 -#define BM_11_52 BM_52_11 -#define BM_53_11 0x003ffffffffff800 -#define BM_11_53 BM_53_11 -#define BM_54_11 0x007ffffffffff800 -#define BM_11_54 BM_54_11 -#define BM_55_11 0x00fffffffffff800 -#define BM_11_55 BM_55_11 -#define BM_56_11 0x01fffffffffff800 -#define BM_11_56 BM_56_11 -#define BM_57_11 0x03fffffffffff800 -#define BM_11_57 BM_57_11 -#define BM_58_11 0x07fffffffffff800 -#define BM_11_58 BM_58_11 -#define BM_59_11 0x0ffffffffffff800 -#define BM_11_59 BM_59_11 -#define BM_60_11 0x1ffffffffffff800 -#define BM_11_60 BM_60_11 -#define BM_61_11 0x3ffffffffffff800 -#define BM_11_61 BM_61_11 -#define BM_62_11 0x7ffffffffffff800 -#define BM_11_62 BM_62_11 -#define BM_63_11 0xfffffffffffff800 -#define BM_11_63 BM_63_11 -#define BM_12_12 0x0000000000001000 -#define BM_13_12 0x0000000000003000 -#define BM_12_13 BM_13_12 -#define BM_14_12 0x0000000000007000 -#define BM_12_14 BM_14_12 -#define BM_15_12 0x000000000000f000 -#define BM_12_15 BM_15_12 -#define BM_16_12 0x000000000001f000 -#define BM_12_16 BM_16_12 -#define BM_17_12 0x000000000003f000 -#define BM_12_17 BM_17_12 -#define BM_18_12 0x000000000007f000 -#define BM_12_18 BM_18_12 -#define BM_19_12 0x00000000000ff000 -#define BM_12_19 BM_19_12 -#define BM_20_12 0x00000000001ff000 -#define BM_12_20 BM_20_12 -#define BM_21_12 0x00000000003ff000 -#define BM_12_21 BM_21_12 -#define BM_22_12 0x00000000007ff000 -#define BM_12_22 BM_22_12 -#define BM_23_12 0x0000000000fff000 -#define BM_12_23 BM_23_12 -#define BM_24_12 0x0000000001fff000 -#define BM_12_24 BM_24_12 -#define BM_25_12 0x0000000003fff000 -#define BM_12_25 BM_25_12 -#define BM_26_12 0x0000000007fff000 -#define BM_12_26 BM_26_12 -#define BM_27_12 0x000000000ffff000 -#define BM_12_27 BM_27_12 -#define BM_28_12 0x000000001ffff000 -#define BM_12_28 BM_28_12 -#define BM_29_12 0x000000003ffff000 -#define BM_12_29 BM_29_12 -#define BM_30_12 0x000000007ffff000 -#define BM_12_30 BM_30_12 -#define BM_31_12 0x00000000fffff000 -#define BM_12_31 BM_31_12 -#define BM_32_12 0x00000001fffff000 -#define BM_12_32 BM_32_12 -#define BM_33_12 0x00000003fffff000 -#define BM_12_33 BM_33_12 -#define BM_34_12 0x00000007fffff000 -#define BM_12_34 BM_34_12 -#define BM_35_12 0x0000000ffffff000 -#define BM_12_35 BM_35_12 -#define BM_36_12 0x0000001ffffff000 -#define BM_12_36 BM_36_12 -#define BM_37_12 0x0000003ffffff000 -#define BM_12_37 BM_37_12 -#define BM_38_12 0x0000007ffffff000 -#define BM_12_38 BM_38_12 -#define BM_39_12 0x000000fffffff000 -#define BM_12_39 BM_39_12 -#define BM_40_12 0x000001fffffff000 -#define BM_12_40 BM_40_12 -#define BM_41_12 0x000003fffffff000 -#define BM_12_41 BM_41_12 -#define BM_42_12 0x000007fffffff000 -#define BM_12_42 BM_42_12 -#define BM_43_12 0x00000ffffffff000 -#define BM_12_43 BM_43_12 -#define BM_44_12 0x00001ffffffff000 -#define BM_12_44 BM_44_12 -#define BM_45_12 0x00003ffffffff000 -#define BM_12_45 BM_45_12 -#define BM_46_12 0x00007ffffffff000 -#define BM_12_46 BM_46_12 -#define BM_47_12 0x0000fffffffff000 -#define BM_12_47 BM_47_12 -#define BM_48_12 0x0001fffffffff000 -#define BM_12_48 BM_48_12 -#define BM_49_12 0x0003fffffffff000 -#define BM_12_49 BM_49_12 -#define BM_50_12 0x0007fffffffff000 -#define BM_12_50 BM_50_12 -#define BM_51_12 0x000ffffffffff000 -#define BM_12_51 BM_51_12 -#define BM_52_12 0x001ffffffffff000 -#define BM_12_52 BM_52_12 -#define BM_53_12 0x003ffffffffff000 -#define BM_12_53 BM_53_12 -#define BM_54_12 0x007ffffffffff000 -#define BM_12_54 BM_54_12 -#define BM_55_12 0x00fffffffffff000 -#define BM_12_55 BM_55_12 -#define BM_56_12 0x01fffffffffff000 -#define BM_12_56 BM_56_12 -#define BM_57_12 0x03fffffffffff000 -#define BM_12_57 BM_57_12 -#define BM_58_12 0x07fffffffffff000 -#define BM_12_58 BM_58_12 -#define BM_59_12 0x0ffffffffffff000 -#define BM_12_59 BM_59_12 -#define BM_60_12 0x1ffffffffffff000 -#define BM_12_60 BM_60_12 -#define BM_61_12 0x3ffffffffffff000 -#define BM_12_61 BM_61_12 -#define BM_62_12 0x7ffffffffffff000 -#define BM_12_62 BM_62_12 -#define BM_63_12 0xfffffffffffff000 -#define BM_12_63 BM_63_12 -#define BM_13_13 0x0000000000002000 -#define BM_14_13 0x0000000000006000 -#define BM_13_14 BM_14_13 -#define BM_15_13 0x000000000000e000 -#define BM_13_15 BM_15_13 -#define BM_16_13 0x000000000001e000 -#define BM_13_16 BM_16_13 -#define BM_17_13 0x000000000003e000 -#define BM_13_17 BM_17_13 -#define BM_18_13 0x000000000007e000 -#define BM_13_18 BM_18_13 -#define BM_19_13 0x00000000000fe000 -#define BM_13_19 BM_19_13 -#define BM_20_13 0x00000000001fe000 -#define BM_13_20 BM_20_13 -#define BM_21_13 0x00000000003fe000 -#define BM_13_21 BM_21_13 -#define BM_22_13 0x00000000007fe000 -#define BM_13_22 BM_22_13 -#define BM_23_13 0x0000000000ffe000 -#define BM_13_23 BM_23_13 -#define BM_24_13 0x0000000001ffe000 -#define BM_13_24 BM_24_13 -#define BM_25_13 0x0000000003ffe000 -#define BM_13_25 BM_25_13 -#define BM_26_13 0x0000000007ffe000 -#define BM_13_26 BM_26_13 -#define BM_27_13 0x000000000fffe000 -#define BM_13_27 BM_27_13 -#define BM_28_13 0x000000001fffe000 -#define BM_13_28 BM_28_13 -#define BM_29_13 0x000000003fffe000 -#define BM_13_29 BM_29_13 -#define BM_30_13 0x000000007fffe000 -#define BM_13_30 BM_30_13 -#define BM_31_13 0x00000000ffffe000 -#define BM_13_31 BM_31_13 -#define BM_32_13 0x00000001ffffe000 -#define BM_13_32 BM_32_13 -#define BM_33_13 0x00000003ffffe000 -#define BM_13_33 BM_33_13 -#define BM_34_13 0x00000007ffffe000 -#define BM_13_34 BM_34_13 -#define BM_35_13 0x0000000fffffe000 -#define BM_13_35 BM_35_13 -#define BM_36_13 0x0000001fffffe000 -#define BM_13_36 BM_36_13 -#define BM_37_13 0x0000003fffffe000 -#define BM_13_37 BM_37_13 -#define BM_38_13 0x0000007fffffe000 -#define BM_13_38 BM_38_13 -#define BM_39_13 0x000000ffffffe000 -#define BM_13_39 BM_39_13 -#define BM_40_13 0x000001ffffffe000 -#define BM_13_40 BM_40_13 -#define BM_41_13 0x000003ffffffe000 -#define BM_13_41 BM_41_13 -#define BM_42_13 0x000007ffffffe000 -#define BM_13_42 BM_42_13 -#define BM_43_13 0x00000fffffffe000 -#define BM_13_43 BM_43_13 -#define BM_44_13 0x00001fffffffe000 -#define BM_13_44 BM_44_13 -#define BM_45_13 0x00003fffffffe000 -#define BM_13_45 BM_45_13 -#define BM_46_13 0x00007fffffffe000 -#define BM_13_46 BM_46_13 -#define BM_47_13 0x0000ffffffffe000 -#define BM_13_47 BM_47_13 -#define BM_48_13 0x0001ffffffffe000 -#define BM_13_48 BM_48_13 -#define BM_49_13 0x0003ffffffffe000 -#define BM_13_49 BM_49_13 -#define BM_50_13 0x0007ffffffffe000 -#define BM_13_50 BM_50_13 -#define BM_51_13 0x000fffffffffe000 -#define BM_13_51 BM_51_13 -#define BM_52_13 0x001fffffffffe000 -#define BM_13_52 BM_52_13 -#define BM_53_13 0x003fffffffffe000 -#define BM_13_53 BM_53_13 -#define BM_54_13 0x007fffffffffe000 -#define BM_13_54 BM_54_13 -#define BM_55_13 0x00ffffffffffe000 -#define BM_13_55 BM_55_13 -#define BM_56_13 0x01ffffffffffe000 -#define BM_13_56 BM_56_13 -#define BM_57_13 0x03ffffffffffe000 -#define BM_13_57 BM_57_13 -#define BM_58_13 0x07ffffffffffe000 -#define BM_13_58 BM_58_13 -#define BM_59_13 0x0fffffffffffe000 -#define BM_13_59 BM_59_13 -#define BM_60_13 0x1fffffffffffe000 -#define BM_13_60 BM_60_13 -#define BM_61_13 0x3fffffffffffe000 -#define BM_13_61 BM_61_13 -#define BM_62_13 0x7fffffffffffe000 -#define BM_13_62 BM_62_13 -#define BM_63_13 0xffffffffffffe000 -#define BM_13_63 BM_63_13 -#define BM_14_14 0x0000000000004000 -#define BM_15_14 0x000000000000c000 -#define BM_14_15 BM_15_14 -#define BM_16_14 0x000000000001c000 -#define BM_14_16 BM_16_14 -#define BM_17_14 0x000000000003c000 -#define BM_14_17 BM_17_14 -#define BM_18_14 0x000000000007c000 -#define BM_14_18 BM_18_14 -#define BM_19_14 0x00000000000fc000 -#define BM_14_19 BM_19_14 -#define BM_20_14 0x00000000001fc000 -#define BM_14_20 BM_20_14 -#define BM_21_14 0x00000000003fc000 -#define BM_14_21 BM_21_14 -#define BM_22_14 0x00000000007fc000 -#define BM_14_22 BM_22_14 -#define BM_23_14 0x0000000000ffc000 -#define BM_14_23 BM_23_14 -#define BM_24_14 0x0000000001ffc000 -#define BM_14_24 BM_24_14 -#define BM_25_14 0x0000000003ffc000 -#define BM_14_25 BM_25_14 -#define BM_26_14 0x0000000007ffc000 -#define BM_14_26 BM_26_14 -#define BM_27_14 0x000000000fffc000 -#define BM_14_27 BM_27_14 -#define BM_28_14 0x000000001fffc000 -#define BM_14_28 BM_28_14 -#define BM_29_14 0x000000003fffc000 -#define BM_14_29 BM_29_14 -#define BM_30_14 0x000000007fffc000 -#define BM_14_30 BM_30_14 -#define BM_31_14 0x00000000ffffc000 -#define BM_14_31 BM_31_14 -#define BM_32_14 0x00000001ffffc000 -#define BM_14_32 BM_32_14 -#define BM_33_14 0x00000003ffffc000 -#define BM_14_33 BM_33_14 -#define BM_34_14 0x00000007ffffc000 -#define BM_14_34 BM_34_14 -#define BM_35_14 0x0000000fffffc000 -#define BM_14_35 BM_35_14 -#define BM_36_14 0x0000001fffffc000 -#define BM_14_36 BM_36_14 -#define BM_37_14 0x0000003fffffc000 -#define BM_14_37 BM_37_14 -#define BM_38_14 0x0000007fffffc000 -#define BM_14_38 BM_38_14 -#define BM_39_14 0x000000ffffffc000 -#define BM_14_39 BM_39_14 -#define BM_40_14 0x000001ffffffc000 -#define BM_14_40 BM_40_14 -#define BM_41_14 0x000003ffffffc000 -#define BM_14_41 BM_41_14 -#define BM_42_14 0x000007ffffffc000 -#define BM_14_42 BM_42_14 -#define BM_43_14 0x00000fffffffc000 -#define BM_14_43 BM_43_14 -#define BM_44_14 0x00001fffffffc000 -#define BM_14_44 BM_44_14 -#define BM_45_14 0x00003fffffffc000 -#define BM_14_45 BM_45_14 -#define BM_46_14 0x00007fffffffc000 -#define BM_14_46 BM_46_14 -#define BM_47_14 0x0000ffffffffc000 -#define BM_14_47 BM_47_14 -#define BM_48_14 0x0001ffffffffc000 -#define BM_14_48 BM_48_14 -#define BM_49_14 0x0003ffffffffc000 -#define BM_14_49 BM_49_14 -#define BM_50_14 0x0007ffffffffc000 -#define BM_14_50 BM_50_14 -#define BM_51_14 0x000fffffffffc000 -#define BM_14_51 BM_51_14 -#define BM_52_14 0x001fffffffffc000 -#define BM_14_52 BM_52_14 -#define BM_53_14 0x003fffffffffc000 -#define BM_14_53 BM_53_14 -#define BM_54_14 0x007fffffffffc000 -#define BM_14_54 BM_54_14 -#define BM_55_14 0x00ffffffffffc000 -#define BM_14_55 BM_55_14 -#define BM_56_14 0x01ffffffffffc000 -#define BM_14_56 BM_56_14 -#define BM_57_14 0x03ffffffffffc000 -#define BM_14_57 BM_57_14 -#define BM_58_14 0x07ffffffffffc000 -#define BM_14_58 BM_58_14 -#define BM_59_14 0x0fffffffffffc000 -#define BM_14_59 BM_59_14 -#define BM_60_14 0x1fffffffffffc000 -#define BM_14_60 BM_60_14 -#define BM_61_14 0x3fffffffffffc000 -#define BM_14_61 BM_61_14 -#define BM_62_14 0x7fffffffffffc000 -#define BM_14_62 BM_62_14 -#define BM_63_14 0xffffffffffffc000 -#define BM_14_63 BM_63_14 -#define BM_15_15 0x0000000000008000 -#define BM_16_15 0x0000000000018000 -#define BM_15_16 BM_16_15 -#define BM_17_15 0x0000000000038000 -#define BM_15_17 BM_17_15 -#define BM_18_15 0x0000000000078000 -#define BM_15_18 BM_18_15 -#define BM_19_15 0x00000000000f8000 -#define BM_15_19 BM_19_15 -#define BM_20_15 0x00000000001f8000 -#define BM_15_20 BM_20_15 -#define BM_21_15 0x00000000003f8000 -#define BM_15_21 BM_21_15 -#define BM_22_15 0x00000000007f8000 -#define BM_15_22 BM_22_15 -#define BM_23_15 0x0000000000ff8000 -#define BM_15_23 BM_23_15 -#define BM_24_15 0x0000000001ff8000 -#define BM_15_24 BM_24_15 -#define BM_25_15 0x0000000003ff8000 -#define BM_15_25 BM_25_15 -#define BM_26_15 0x0000000007ff8000 -#define BM_15_26 BM_26_15 -#define BM_27_15 0x000000000fff8000 -#define BM_15_27 BM_27_15 -#define BM_28_15 0x000000001fff8000 -#define BM_15_28 BM_28_15 -#define BM_29_15 0x000000003fff8000 -#define BM_15_29 BM_29_15 -#define BM_30_15 0x000000007fff8000 -#define BM_15_30 BM_30_15 -#define BM_31_15 0x00000000ffff8000 -#define BM_15_31 BM_31_15 -#define BM_32_15 0x00000001ffff8000 -#define BM_15_32 BM_32_15 -#define BM_33_15 0x00000003ffff8000 -#define BM_15_33 BM_33_15 -#define BM_34_15 0x00000007ffff8000 -#define BM_15_34 BM_34_15 -#define BM_35_15 0x0000000fffff8000 -#define BM_15_35 BM_35_15 -#define BM_36_15 0x0000001fffff8000 -#define BM_15_36 BM_36_15 -#define BM_37_15 0x0000003fffff8000 -#define BM_15_37 BM_37_15 -#define BM_38_15 0x0000007fffff8000 -#define BM_15_38 BM_38_15 -#define BM_39_15 0x000000ffffff8000 -#define BM_15_39 BM_39_15 -#define BM_40_15 0x000001ffffff8000 -#define BM_15_40 BM_40_15 -#define BM_41_15 0x000003ffffff8000 -#define BM_15_41 BM_41_15 -#define BM_42_15 0x000007ffffff8000 -#define BM_15_42 BM_42_15 -#define BM_43_15 0x00000fffffff8000 -#define BM_15_43 BM_43_15 -#define BM_44_15 0x00001fffffff8000 -#define BM_15_44 BM_44_15 -#define BM_45_15 0x00003fffffff8000 -#define BM_15_45 BM_45_15 -#define BM_46_15 0x00007fffffff8000 -#define BM_15_46 BM_46_15 -#define BM_47_15 0x0000ffffffff8000 -#define BM_15_47 BM_47_15 -#define BM_48_15 0x0001ffffffff8000 -#define BM_15_48 BM_48_15 -#define BM_49_15 0x0003ffffffff8000 -#define BM_15_49 BM_49_15 -#define BM_50_15 0x0007ffffffff8000 -#define BM_15_50 BM_50_15 -#define BM_51_15 0x000fffffffff8000 -#define BM_15_51 BM_51_15 -#define BM_52_15 0x001fffffffff8000 -#define BM_15_52 BM_52_15 -#define BM_53_15 0x003fffffffff8000 -#define BM_15_53 BM_53_15 -#define BM_54_15 0x007fffffffff8000 -#define BM_15_54 BM_54_15 -#define BM_55_15 0x00ffffffffff8000 -#define BM_15_55 BM_55_15 -#define BM_56_15 0x01ffffffffff8000 -#define BM_15_56 BM_56_15 -#define BM_57_15 0x03ffffffffff8000 -#define BM_15_57 BM_57_15 -#define BM_58_15 0x07ffffffffff8000 -#define BM_15_58 BM_58_15 -#define BM_59_15 0x0fffffffffff8000 -#define BM_15_59 BM_59_15 -#define BM_60_15 0x1fffffffffff8000 -#define BM_15_60 BM_60_15 -#define BM_61_15 0x3fffffffffff8000 -#define BM_15_61 BM_61_15 -#define BM_62_15 0x7fffffffffff8000 -#define BM_15_62 BM_62_15 -#define BM_63_15 0xffffffffffff8000 -#define BM_15_63 BM_63_15 -#define BM_16_16 0x0000000000010000 -#define BM_17_16 0x0000000000030000 -#define BM_16_17 BM_17_16 -#define BM_18_16 0x0000000000070000 -#define BM_16_18 BM_18_16 -#define BM_19_16 0x00000000000f0000 -#define BM_16_19 BM_19_16 -#define BM_20_16 0x00000000001f0000 -#define BM_16_20 BM_20_16 -#define BM_21_16 0x00000000003f0000 -#define BM_16_21 BM_21_16 -#define BM_22_16 0x00000000007f0000 -#define BM_16_22 BM_22_16 -#define BM_23_16 0x0000000000ff0000 -#define BM_16_23 BM_23_16 -#define BM_24_16 0x0000000001ff0000 -#define BM_16_24 BM_24_16 -#define BM_25_16 0x0000000003ff0000 -#define BM_16_25 BM_25_16 -#define BM_26_16 0x0000000007ff0000 -#define BM_16_26 BM_26_16 -#define BM_27_16 0x000000000fff0000 -#define BM_16_27 BM_27_16 -#define BM_28_16 0x000000001fff0000 -#define BM_16_28 BM_28_16 -#define BM_29_16 0x000000003fff0000 -#define BM_16_29 BM_29_16 -#define BM_30_16 0x000000007fff0000 -#define BM_16_30 BM_30_16 -#define BM_31_16 0x00000000ffff0000 -#define BM_16_31 BM_31_16 -#define BM_32_16 0x00000001ffff0000 -#define BM_16_32 BM_32_16 -#define BM_33_16 0x00000003ffff0000 -#define BM_16_33 BM_33_16 -#define BM_34_16 0x00000007ffff0000 -#define BM_16_34 BM_34_16 -#define BM_35_16 0x0000000fffff0000 -#define BM_16_35 BM_35_16 -#define BM_36_16 0x0000001fffff0000 -#define BM_16_36 BM_36_16 -#define BM_37_16 0x0000003fffff0000 -#define BM_16_37 BM_37_16 -#define BM_38_16 0x0000007fffff0000 -#define BM_16_38 BM_38_16 -#define BM_39_16 0x000000ffffff0000 -#define BM_16_39 BM_39_16 -#define BM_40_16 0x000001ffffff0000 -#define BM_16_40 BM_40_16 -#define BM_41_16 0x000003ffffff0000 -#define BM_16_41 BM_41_16 -#define BM_42_16 0x000007ffffff0000 -#define BM_16_42 BM_42_16 -#define BM_43_16 0x00000fffffff0000 -#define BM_16_43 BM_43_16 -#define BM_44_16 0x00001fffffff0000 -#define BM_16_44 BM_44_16 -#define BM_45_16 0x00003fffffff0000 -#define BM_16_45 BM_45_16 -#define BM_46_16 0x00007fffffff0000 -#define BM_16_46 BM_46_16 -#define BM_47_16 0x0000ffffffff0000 -#define BM_16_47 BM_47_16 -#define BM_48_16 0x0001ffffffff0000 -#define BM_16_48 BM_48_16 -#define BM_49_16 0x0003ffffffff0000 -#define BM_16_49 BM_49_16 -#define BM_50_16 0x0007ffffffff0000 -#define BM_16_50 BM_50_16 -#define BM_51_16 0x000fffffffff0000 -#define BM_16_51 BM_51_16 -#define BM_52_16 0x001fffffffff0000 -#define BM_16_52 BM_52_16 -#define BM_53_16 0x003fffffffff0000 -#define BM_16_53 BM_53_16 -#define BM_54_16 0x007fffffffff0000 -#define BM_16_54 BM_54_16 -#define BM_55_16 0x00ffffffffff0000 -#define BM_16_55 BM_55_16 -#define BM_56_16 0x01ffffffffff0000 -#define BM_16_56 BM_56_16 -#define BM_57_16 0x03ffffffffff0000 -#define BM_16_57 BM_57_16 -#define BM_58_16 0x07ffffffffff0000 -#define BM_16_58 BM_58_16 -#define BM_59_16 0x0fffffffffff0000 -#define BM_16_59 BM_59_16 -#define BM_60_16 0x1fffffffffff0000 -#define BM_16_60 BM_60_16 -#define BM_61_16 0x3fffffffffff0000 -#define BM_16_61 BM_61_16 -#define BM_62_16 0x7fffffffffff0000 -#define BM_16_62 BM_62_16 -#define BM_63_16 0xffffffffffff0000 -#define BM_16_63 BM_63_16 -#define BM_17_17 0x0000000000020000 -#define BM_18_17 0x0000000000060000 -#define BM_17_18 BM_18_17 -#define BM_19_17 0x00000000000e0000 -#define BM_17_19 BM_19_17 -#define BM_20_17 0x00000000001e0000 -#define BM_17_20 BM_20_17 -#define BM_21_17 0x00000000003e0000 -#define BM_17_21 BM_21_17 -#define BM_22_17 0x00000000007e0000 -#define BM_17_22 BM_22_17 -#define BM_23_17 0x0000000000fe0000 -#define BM_17_23 BM_23_17 -#define BM_24_17 0x0000000001fe0000 -#define BM_17_24 BM_24_17 -#define BM_25_17 0x0000000003fe0000 -#define BM_17_25 BM_25_17 -#define BM_26_17 0x0000000007fe0000 -#define BM_17_26 BM_26_17 -#define BM_27_17 0x000000000ffe0000 -#define BM_17_27 BM_27_17 -#define BM_28_17 0x000000001ffe0000 -#define BM_17_28 BM_28_17 -#define BM_29_17 0x000000003ffe0000 -#define BM_17_29 BM_29_17 -#define BM_30_17 0x000000007ffe0000 -#define BM_17_30 BM_30_17 -#define BM_31_17 0x00000000fffe0000 -#define BM_17_31 BM_31_17 -#define BM_32_17 0x00000001fffe0000 -#define BM_17_32 BM_32_17 -#define BM_33_17 0x00000003fffe0000 -#define BM_17_33 BM_33_17 -#define BM_34_17 0x00000007fffe0000 -#define BM_17_34 BM_34_17 -#define BM_35_17 0x0000000ffffe0000 -#define BM_17_35 BM_35_17 -#define BM_36_17 0x0000001ffffe0000 -#define BM_17_36 BM_36_17 -#define BM_37_17 0x0000003ffffe0000 -#define BM_17_37 BM_37_17 -#define BM_38_17 0x0000007ffffe0000 -#define BM_17_38 BM_38_17 -#define BM_39_17 0x000000fffffe0000 -#define BM_17_39 BM_39_17 -#define BM_40_17 0x000001fffffe0000 -#define BM_17_40 BM_40_17 -#define BM_41_17 0x000003fffffe0000 -#define BM_17_41 BM_41_17 -#define BM_42_17 0x000007fffffe0000 -#define BM_17_42 BM_42_17 -#define BM_43_17 0x00000ffffffe0000 -#define BM_17_43 BM_43_17 -#define BM_44_17 0x00001ffffffe0000 -#define BM_17_44 BM_44_17 -#define BM_45_17 0x00003ffffffe0000 -#define BM_17_45 BM_45_17 -#define BM_46_17 0x00007ffffffe0000 -#define BM_17_46 BM_46_17 -#define BM_47_17 0x0000fffffffe0000 -#define BM_17_47 BM_47_17 -#define BM_48_17 0x0001fffffffe0000 -#define BM_17_48 BM_48_17 -#define BM_49_17 0x0003fffffffe0000 -#define BM_17_49 BM_49_17 -#define BM_50_17 0x0007fffffffe0000 -#define BM_17_50 BM_50_17 -#define BM_51_17 0x000ffffffffe0000 -#define BM_17_51 BM_51_17 -#define BM_52_17 0x001ffffffffe0000 -#define BM_17_52 BM_52_17 -#define BM_53_17 0x003ffffffffe0000 -#define BM_17_53 BM_53_17 -#define BM_54_17 0x007ffffffffe0000 -#define BM_17_54 BM_54_17 -#define BM_55_17 0x00fffffffffe0000 -#define BM_17_55 BM_55_17 -#define BM_56_17 0x01fffffffffe0000 -#define BM_17_56 BM_56_17 -#define BM_57_17 0x03fffffffffe0000 -#define BM_17_57 BM_57_17 -#define BM_58_17 0x07fffffffffe0000 -#define BM_17_58 BM_58_17 -#define BM_59_17 0x0ffffffffffe0000 -#define BM_17_59 BM_59_17 -#define BM_60_17 0x1ffffffffffe0000 -#define BM_17_60 BM_60_17 -#define BM_61_17 0x3ffffffffffe0000 -#define BM_17_61 BM_61_17 -#define BM_62_17 0x7ffffffffffe0000 -#define BM_17_62 BM_62_17 -#define BM_63_17 0xfffffffffffe0000 -#define BM_17_63 BM_63_17 -#define BM_18_18 0x0000000000040000 -#define BM_19_18 0x00000000000c0000 -#define BM_18_19 BM_19_18 -#define BM_20_18 0x00000000001c0000 -#define BM_18_20 BM_20_18 -#define BM_21_18 0x00000000003c0000 -#define BM_18_21 BM_21_18 -#define BM_22_18 0x00000000007c0000 -#define BM_18_22 BM_22_18 -#define BM_23_18 0x0000000000fc0000 -#define BM_18_23 BM_23_18 -#define BM_24_18 0x0000000001fc0000 -#define BM_18_24 BM_24_18 -#define BM_25_18 0x0000000003fc0000 -#define BM_18_25 BM_25_18 -#define BM_26_18 0x0000000007fc0000 -#define BM_18_26 BM_26_18 -#define BM_27_18 0x000000000ffc0000 -#define BM_18_27 BM_27_18 -#define BM_28_18 0x000000001ffc0000 -#define BM_18_28 BM_28_18 -#define BM_29_18 0x000000003ffc0000 -#define BM_18_29 BM_29_18 -#define BM_30_18 0x000000007ffc0000 -#define BM_18_30 BM_30_18 -#define BM_31_18 0x00000000fffc0000 -#define BM_18_31 BM_31_18 -#define BM_32_18 0x00000001fffc0000 -#define BM_18_32 BM_32_18 -#define BM_33_18 0x00000003fffc0000 -#define BM_18_33 BM_33_18 -#define BM_34_18 0x00000007fffc0000 -#define BM_18_34 BM_34_18 -#define BM_35_18 0x0000000ffffc0000 -#define BM_18_35 BM_35_18 -#define BM_36_18 0x0000001ffffc0000 -#define BM_18_36 BM_36_18 -#define BM_37_18 0x0000003ffffc0000 -#define BM_18_37 BM_37_18 -#define BM_38_18 0x0000007ffffc0000 -#define BM_18_38 BM_38_18 -#define BM_39_18 0x000000fffffc0000 -#define BM_18_39 BM_39_18 -#define BM_40_18 0x000001fffffc0000 -#define BM_18_40 BM_40_18 -#define BM_41_18 0x000003fffffc0000 -#define BM_18_41 BM_41_18 -#define BM_42_18 0x000007fffffc0000 -#define BM_18_42 BM_42_18 -#define BM_43_18 0x00000ffffffc0000 -#define BM_18_43 BM_43_18 -#define BM_44_18 0x00001ffffffc0000 -#define BM_18_44 BM_44_18 -#define BM_45_18 0x00003ffffffc0000 -#define BM_18_45 BM_45_18 -#define BM_46_18 0x00007ffffffc0000 -#define BM_18_46 BM_46_18 -#define BM_47_18 0x0000fffffffc0000 -#define BM_18_47 BM_47_18 -#define BM_48_18 0x0001fffffffc0000 -#define BM_18_48 BM_48_18 -#define BM_49_18 0x0003fffffffc0000 -#define BM_18_49 BM_49_18 -#define BM_50_18 0x0007fffffffc0000 -#define BM_18_50 BM_50_18 -#define BM_51_18 0x000ffffffffc0000 -#define BM_18_51 BM_51_18 -#define BM_52_18 0x001ffffffffc0000 -#define BM_18_52 BM_52_18 -#define BM_53_18 0x003ffffffffc0000 -#define BM_18_53 BM_53_18 -#define BM_54_18 0x007ffffffffc0000 -#define BM_18_54 BM_54_18 -#define BM_55_18 0x00fffffffffc0000 -#define BM_18_55 BM_55_18 -#define BM_56_18 0x01fffffffffc0000 -#define BM_18_56 BM_56_18 -#define BM_57_18 0x03fffffffffc0000 -#define BM_18_57 BM_57_18 -#define BM_58_18 0x07fffffffffc0000 -#define BM_18_58 BM_58_18 -#define BM_59_18 0x0ffffffffffc0000 -#define BM_18_59 BM_59_18 -#define BM_60_18 0x1ffffffffffc0000 -#define BM_18_60 BM_60_18 -#define BM_61_18 0x3ffffffffffc0000 -#define BM_18_61 BM_61_18 -#define BM_62_18 0x7ffffffffffc0000 -#define BM_18_62 BM_62_18 -#define BM_63_18 0xfffffffffffc0000 -#define BM_18_63 BM_63_18 -#define BM_19_19 0x0000000000080000 -#define BM_20_19 0x0000000000180000 -#define BM_19_20 BM_20_19 -#define BM_21_19 0x0000000000380000 -#define BM_19_21 BM_21_19 -#define BM_22_19 0x0000000000780000 -#define BM_19_22 BM_22_19 -#define BM_23_19 0x0000000000f80000 -#define BM_19_23 BM_23_19 -#define BM_24_19 0x0000000001f80000 -#define BM_19_24 BM_24_19 -#define BM_25_19 0x0000000003f80000 -#define BM_19_25 BM_25_19 -#define BM_26_19 0x0000000007f80000 -#define BM_19_26 BM_26_19 -#define BM_27_19 0x000000000ff80000 -#define BM_19_27 BM_27_19 -#define BM_28_19 0x000000001ff80000 -#define BM_19_28 BM_28_19 -#define BM_29_19 0x000000003ff80000 -#define BM_19_29 BM_29_19 -#define BM_30_19 0x000000007ff80000 -#define BM_19_30 BM_30_19 -#define BM_31_19 0x00000000fff80000 -#define BM_19_31 BM_31_19 -#define BM_32_19 0x00000001fff80000 -#define BM_19_32 BM_32_19 -#define BM_33_19 0x00000003fff80000 -#define BM_19_33 BM_33_19 -#define BM_34_19 0x00000007fff80000 -#define BM_19_34 BM_34_19 -#define BM_35_19 0x0000000ffff80000 -#define BM_19_35 BM_35_19 -#define BM_36_19 0x0000001ffff80000 -#define BM_19_36 BM_36_19 -#define BM_37_19 0x0000003ffff80000 -#define BM_19_37 BM_37_19 -#define BM_38_19 0x0000007ffff80000 -#define BM_19_38 BM_38_19 -#define BM_39_19 0x000000fffff80000 -#define BM_19_39 BM_39_19 -#define BM_40_19 0x000001fffff80000 -#define BM_19_40 BM_40_19 -#define BM_41_19 0x000003fffff80000 -#define BM_19_41 BM_41_19 -#define BM_42_19 0x000007fffff80000 -#define BM_19_42 BM_42_19 -#define BM_43_19 0x00000ffffff80000 -#define BM_19_43 BM_43_19 -#define BM_44_19 0x00001ffffff80000 -#define BM_19_44 BM_44_19 -#define BM_45_19 0x00003ffffff80000 -#define BM_19_45 BM_45_19 -#define BM_46_19 0x00007ffffff80000 -#define BM_19_46 BM_46_19 -#define BM_47_19 0x0000fffffff80000 -#define BM_19_47 BM_47_19 -#define BM_48_19 0x0001fffffff80000 -#define BM_19_48 BM_48_19 -#define BM_49_19 0x0003fffffff80000 -#define BM_19_49 BM_49_19 -#define BM_50_19 0x0007fffffff80000 -#define BM_19_50 BM_50_19 -#define BM_51_19 0x000ffffffff80000 -#define BM_19_51 BM_51_19 -#define BM_52_19 0x001ffffffff80000 -#define BM_19_52 BM_52_19 -#define BM_53_19 0x003ffffffff80000 -#define BM_19_53 BM_53_19 -#define BM_54_19 0x007ffffffff80000 -#define BM_19_54 BM_54_19 -#define BM_55_19 0x00fffffffff80000 -#define BM_19_55 BM_55_19 -#define BM_56_19 0x01fffffffff80000 -#define BM_19_56 BM_56_19 -#define BM_57_19 0x03fffffffff80000 -#define BM_19_57 BM_57_19 -#define BM_58_19 0x07fffffffff80000 -#define BM_19_58 BM_58_19 -#define BM_59_19 0x0ffffffffff80000 -#define BM_19_59 BM_59_19 -#define BM_60_19 0x1ffffffffff80000 -#define BM_19_60 BM_60_19 -#define BM_61_19 0x3ffffffffff80000 -#define BM_19_61 BM_61_19 -#define BM_62_19 0x7ffffffffff80000 -#define BM_19_62 BM_62_19 -#define BM_63_19 0xfffffffffff80000 -#define BM_19_63 BM_63_19 -#define BM_20_20 0x0000000000100000 -#define BM_21_20 0x0000000000300000 -#define BM_20_21 BM_21_20 -#define BM_22_20 0x0000000000700000 -#define BM_20_22 BM_22_20 -#define BM_23_20 0x0000000000f00000 -#define BM_20_23 BM_23_20 -#define BM_24_20 0x0000000001f00000 -#define BM_20_24 BM_24_20 -#define BM_25_20 0x0000000003f00000 -#define BM_20_25 BM_25_20 -#define BM_26_20 0x0000000007f00000 -#define BM_20_26 BM_26_20 -#define BM_27_20 0x000000000ff00000 -#define BM_20_27 BM_27_20 -#define BM_28_20 0x000000001ff00000 -#define BM_20_28 BM_28_20 -#define BM_29_20 0x000000003ff00000 -#define BM_20_29 BM_29_20 -#define BM_30_20 0x000000007ff00000 -#define BM_20_30 BM_30_20 -#define BM_31_20 0x00000000fff00000 -#define BM_20_31 BM_31_20 -#define BM_32_20 0x00000001fff00000 -#define BM_20_32 BM_32_20 -#define BM_33_20 0x00000003fff00000 -#define BM_20_33 BM_33_20 -#define BM_34_20 0x00000007fff00000 -#define BM_20_34 BM_34_20 -#define BM_35_20 0x0000000ffff00000 -#define BM_20_35 BM_35_20 -#define BM_36_20 0x0000001ffff00000 -#define BM_20_36 BM_36_20 -#define BM_37_20 0x0000003ffff00000 -#define BM_20_37 BM_37_20 -#define BM_38_20 0x0000007ffff00000 -#define BM_20_38 BM_38_20 -#define BM_39_20 0x000000fffff00000 -#define BM_20_39 BM_39_20 -#define BM_40_20 0x000001fffff00000 -#define BM_20_40 BM_40_20 -#define BM_41_20 0x000003fffff00000 -#define BM_20_41 BM_41_20 -#define BM_42_20 0x000007fffff00000 -#define BM_20_42 BM_42_20 -#define BM_43_20 0x00000ffffff00000 -#define BM_20_43 BM_43_20 -#define BM_44_20 0x00001ffffff00000 -#define BM_20_44 BM_44_20 -#define BM_45_20 0x00003ffffff00000 -#define BM_20_45 BM_45_20 -#define BM_46_20 0x00007ffffff00000 -#define BM_20_46 BM_46_20 -#define BM_47_20 0x0000fffffff00000 -#define BM_20_47 BM_47_20 -#define BM_48_20 0x0001fffffff00000 -#define BM_20_48 BM_48_20 -#define BM_49_20 0x0003fffffff00000 -#define BM_20_49 BM_49_20 -#define BM_50_20 0x0007fffffff00000 -#define BM_20_50 BM_50_20 -#define BM_51_20 0x000ffffffff00000 -#define BM_20_51 BM_51_20 -#define BM_52_20 0x001ffffffff00000 -#define BM_20_52 BM_52_20 -#define BM_53_20 0x003ffffffff00000 -#define BM_20_53 BM_53_20 -#define BM_54_20 0x007ffffffff00000 -#define BM_20_54 BM_54_20 -#define BM_55_20 0x00fffffffff00000 -#define BM_20_55 BM_55_20 -#define BM_56_20 0x01fffffffff00000 -#define BM_20_56 BM_56_20 -#define BM_57_20 0x03fffffffff00000 -#define BM_20_57 BM_57_20 -#define BM_58_20 0x07fffffffff00000 -#define BM_20_58 BM_58_20 -#define BM_59_20 0x0ffffffffff00000 -#define BM_20_59 BM_59_20 -#define BM_60_20 0x1ffffffffff00000 -#define BM_20_60 BM_60_20 -#define BM_61_20 0x3ffffffffff00000 -#define BM_20_61 BM_61_20 -#define BM_62_20 0x7ffffffffff00000 -#define BM_20_62 BM_62_20 -#define BM_63_20 0xfffffffffff00000 -#define BM_20_63 BM_63_20 -#define BM_21_21 0x0000000000200000 -#define BM_22_21 0x0000000000600000 -#define BM_21_22 BM_22_21 -#define BM_23_21 0x0000000000e00000 -#define BM_21_23 BM_23_21 -#define BM_24_21 0x0000000001e00000 -#define BM_21_24 BM_24_21 -#define BM_25_21 0x0000000003e00000 -#define BM_21_25 BM_25_21 -#define BM_26_21 0x0000000007e00000 -#define BM_21_26 BM_26_21 -#define BM_27_21 0x000000000fe00000 -#define BM_21_27 BM_27_21 -#define BM_28_21 0x000000001fe00000 -#define BM_21_28 BM_28_21 -#define BM_29_21 0x000000003fe00000 -#define BM_21_29 BM_29_21 -#define BM_30_21 0x000000007fe00000 -#define BM_21_30 BM_30_21 -#define BM_31_21 0x00000000ffe00000 -#define BM_21_31 BM_31_21 -#define BM_32_21 0x00000001ffe00000 -#define BM_21_32 BM_32_21 -#define BM_33_21 0x00000003ffe00000 -#define BM_21_33 BM_33_21 -#define BM_34_21 0x00000007ffe00000 -#define BM_21_34 BM_34_21 -#define BM_35_21 0x0000000fffe00000 -#define BM_21_35 BM_35_21 -#define BM_36_21 0x0000001fffe00000 -#define BM_21_36 BM_36_21 -#define BM_37_21 0x0000003fffe00000 -#define BM_21_37 BM_37_21 -#define BM_38_21 0x0000007fffe00000 -#define BM_21_38 BM_38_21 -#define BM_39_21 0x000000ffffe00000 -#define BM_21_39 BM_39_21 -#define BM_40_21 0x000001ffffe00000 -#define BM_21_40 BM_40_21 -#define BM_41_21 0x000003ffffe00000 -#define BM_21_41 BM_41_21 -#define BM_42_21 0x000007ffffe00000 -#define BM_21_42 BM_42_21 -#define BM_43_21 0x00000fffffe00000 -#define BM_21_43 BM_43_21 -#define BM_44_21 0x00001fffffe00000 -#define BM_21_44 BM_44_21 -#define BM_45_21 0x00003fffffe00000 -#define BM_21_45 BM_45_21 -#define BM_46_21 0x00007fffffe00000 -#define BM_21_46 BM_46_21 -#define BM_47_21 0x0000ffffffe00000 -#define BM_21_47 BM_47_21 -#define BM_48_21 0x0001ffffffe00000 -#define BM_21_48 BM_48_21 -#define BM_49_21 0x0003ffffffe00000 -#define BM_21_49 BM_49_21 -#define BM_50_21 0x0007ffffffe00000 -#define BM_21_50 BM_50_21 -#define BM_51_21 0x000fffffffe00000 -#define BM_21_51 BM_51_21 -#define BM_52_21 0x001fffffffe00000 -#define BM_21_52 BM_52_21 -#define BM_53_21 0x003fffffffe00000 -#define BM_21_53 BM_53_21 -#define BM_54_21 0x007fffffffe00000 -#define BM_21_54 BM_54_21 -#define BM_55_21 0x00ffffffffe00000 -#define BM_21_55 BM_55_21 -#define BM_56_21 0x01ffffffffe00000 -#define BM_21_56 BM_56_21 -#define BM_57_21 0x03ffffffffe00000 -#define BM_21_57 BM_57_21 -#define BM_58_21 0x07ffffffffe00000 -#define BM_21_58 BM_58_21 -#define BM_59_21 0x0fffffffffe00000 -#define BM_21_59 BM_59_21 -#define BM_60_21 0x1fffffffffe00000 -#define BM_21_60 BM_60_21 -#define BM_61_21 0x3fffffffffe00000 -#define BM_21_61 BM_61_21 -#define BM_62_21 0x7fffffffffe00000 -#define BM_21_62 BM_62_21 -#define BM_63_21 0xffffffffffe00000 -#define BM_21_63 BM_63_21 -#define BM_22_22 0x0000000000400000 -#define BM_23_22 0x0000000000c00000 -#define BM_22_23 BM_23_22 -#define BM_24_22 0x0000000001c00000 -#define BM_22_24 BM_24_22 -#define BM_25_22 0x0000000003c00000 -#define BM_22_25 BM_25_22 -#define BM_26_22 0x0000000007c00000 -#define BM_22_26 BM_26_22 -#define BM_27_22 0x000000000fc00000 -#define BM_22_27 BM_27_22 -#define BM_28_22 0x000000001fc00000 -#define BM_22_28 BM_28_22 -#define BM_29_22 0x000000003fc00000 -#define BM_22_29 BM_29_22 -#define BM_30_22 0x000000007fc00000 -#define BM_22_30 BM_30_22 -#define BM_31_22 0x00000000ffc00000 -#define BM_22_31 BM_31_22 -#define BM_32_22 0x00000001ffc00000 -#define BM_22_32 BM_32_22 -#define BM_33_22 0x00000003ffc00000 -#define BM_22_33 BM_33_22 -#define BM_34_22 0x00000007ffc00000 -#define BM_22_34 BM_34_22 -#define BM_35_22 0x0000000fffc00000 -#define BM_22_35 BM_35_22 -#define BM_36_22 0x0000001fffc00000 -#define BM_22_36 BM_36_22 -#define BM_37_22 0x0000003fffc00000 -#define BM_22_37 BM_37_22 -#define BM_38_22 0x0000007fffc00000 -#define BM_22_38 BM_38_22 -#define BM_39_22 0x000000ffffc00000 -#define BM_22_39 BM_39_22 -#define BM_40_22 0x000001ffffc00000 -#define BM_22_40 BM_40_22 -#define BM_41_22 0x000003ffffc00000 -#define BM_22_41 BM_41_22 -#define BM_42_22 0x000007ffffc00000 -#define BM_22_42 BM_42_22 -#define BM_43_22 0x00000fffffc00000 -#define BM_22_43 BM_43_22 -#define BM_44_22 0x00001fffffc00000 -#define BM_22_44 BM_44_22 -#define BM_45_22 0x00003fffffc00000 -#define BM_22_45 BM_45_22 -#define BM_46_22 0x00007fffffc00000 -#define BM_22_46 BM_46_22 -#define BM_47_22 0x0000ffffffc00000 -#define BM_22_47 BM_47_22 -#define BM_48_22 0x0001ffffffc00000 -#define BM_22_48 BM_48_22 -#define BM_49_22 0x0003ffffffc00000 -#define BM_22_49 BM_49_22 -#define BM_50_22 0x0007ffffffc00000 -#define BM_22_50 BM_50_22 -#define BM_51_22 0x000fffffffc00000 -#define BM_22_51 BM_51_22 -#define BM_52_22 0x001fffffffc00000 -#define BM_22_52 BM_52_22 -#define BM_53_22 0x003fffffffc00000 -#define BM_22_53 BM_53_22 -#define BM_54_22 0x007fffffffc00000 -#define BM_22_54 BM_54_22 -#define BM_55_22 0x00ffffffffc00000 -#define BM_22_55 BM_55_22 -#define BM_56_22 0x01ffffffffc00000 -#define BM_22_56 BM_56_22 -#define BM_57_22 0x03ffffffffc00000 -#define BM_22_57 BM_57_22 -#define BM_58_22 0x07ffffffffc00000 -#define BM_22_58 BM_58_22 -#define BM_59_22 0x0fffffffffc00000 -#define BM_22_59 BM_59_22 -#define BM_60_22 0x1fffffffffc00000 -#define BM_22_60 BM_60_22 -#define BM_61_22 0x3fffffffffc00000 -#define BM_22_61 BM_61_22 -#define BM_62_22 0x7fffffffffc00000 -#define BM_22_62 BM_62_22 -#define BM_63_22 0xffffffffffc00000 -#define BM_22_63 BM_63_22 -#define BM_23_23 0x0000000000800000 -#define BM_24_23 0x0000000001800000 -#define BM_23_24 BM_24_23 -#define BM_25_23 0x0000000003800000 -#define BM_23_25 BM_25_23 -#define BM_26_23 0x0000000007800000 -#define BM_23_26 BM_26_23 -#define BM_27_23 0x000000000f800000 -#define BM_23_27 BM_27_23 -#define BM_28_23 0x000000001f800000 -#define BM_23_28 BM_28_23 -#define BM_29_23 0x000000003f800000 -#define BM_23_29 BM_29_23 -#define BM_30_23 0x000000007f800000 -#define BM_23_30 BM_30_23 -#define BM_31_23 0x00000000ff800000 -#define BM_23_31 BM_31_23 -#define BM_32_23 0x00000001ff800000 -#define BM_23_32 BM_32_23 -#define BM_33_23 0x00000003ff800000 -#define BM_23_33 BM_33_23 -#define BM_34_23 0x00000007ff800000 -#define BM_23_34 BM_34_23 -#define BM_35_23 0x0000000fff800000 -#define BM_23_35 BM_35_23 -#define BM_36_23 0x0000001fff800000 -#define BM_23_36 BM_36_23 -#define BM_37_23 0x0000003fff800000 -#define BM_23_37 BM_37_23 -#define BM_38_23 0x0000007fff800000 -#define BM_23_38 BM_38_23 -#define BM_39_23 0x000000ffff800000 -#define BM_23_39 BM_39_23 -#define BM_40_23 0x000001ffff800000 -#define BM_23_40 BM_40_23 -#define BM_41_23 0x000003ffff800000 -#define BM_23_41 BM_41_23 -#define BM_42_23 0x000007ffff800000 -#define BM_23_42 BM_42_23 -#define BM_43_23 0x00000fffff800000 -#define BM_23_43 BM_43_23 -#define BM_44_23 0x00001fffff800000 -#define BM_23_44 BM_44_23 -#define BM_45_23 0x00003fffff800000 -#define BM_23_45 BM_45_23 -#define BM_46_23 0x00007fffff800000 -#define BM_23_46 BM_46_23 -#define BM_47_23 0x0000ffffff800000 -#define BM_23_47 BM_47_23 -#define BM_48_23 0x0001ffffff800000 -#define BM_23_48 BM_48_23 -#define BM_49_23 0x0003ffffff800000 -#define BM_23_49 BM_49_23 -#define BM_50_23 0x0007ffffff800000 -#define BM_23_50 BM_50_23 -#define BM_51_23 0x000fffffff800000 -#define BM_23_51 BM_51_23 -#define BM_52_23 0x001fffffff800000 -#define BM_23_52 BM_52_23 -#define BM_53_23 0x003fffffff800000 -#define BM_23_53 BM_53_23 -#define BM_54_23 0x007fffffff800000 -#define BM_23_54 BM_54_23 -#define BM_55_23 0x00ffffffff800000 -#define BM_23_55 BM_55_23 -#define BM_56_23 0x01ffffffff800000 -#define BM_23_56 BM_56_23 -#define BM_57_23 0x03ffffffff800000 -#define BM_23_57 BM_57_23 -#define BM_58_23 0x07ffffffff800000 -#define BM_23_58 BM_58_23 -#define BM_59_23 0x0fffffffff800000 -#define BM_23_59 BM_59_23 -#define BM_60_23 0x1fffffffff800000 -#define BM_23_60 BM_60_23 -#define BM_61_23 0x3fffffffff800000 -#define BM_23_61 BM_61_23 -#define BM_62_23 0x7fffffffff800000 -#define BM_23_62 BM_62_23 -#define BM_63_23 0xffffffffff800000 -#define BM_23_63 BM_63_23 -#define BM_24_24 0x0000000001000000 -#define BM_25_24 0x0000000003000000 -#define BM_24_25 BM_25_24 -#define BM_26_24 0x0000000007000000 -#define BM_24_26 BM_26_24 -#define BM_27_24 0x000000000f000000 -#define BM_24_27 BM_27_24 -#define BM_28_24 0x000000001f000000 -#define BM_24_28 BM_28_24 -#define BM_29_24 0x000000003f000000 -#define BM_24_29 BM_29_24 -#define BM_30_24 0x000000007f000000 -#define BM_24_30 BM_30_24 -#define BM_31_24 0x00000000ff000000 -#define BM_24_31 BM_31_24 -#define BM_32_24 0x00000001ff000000 -#define BM_24_32 BM_32_24 -#define BM_33_24 0x00000003ff000000 -#define BM_24_33 BM_33_24 -#define BM_34_24 0x00000007ff000000 -#define BM_24_34 BM_34_24 -#define BM_35_24 0x0000000fff000000 -#define BM_24_35 BM_35_24 -#define BM_36_24 0x0000001fff000000 -#define BM_24_36 BM_36_24 -#define BM_37_24 0x0000003fff000000 -#define BM_24_37 BM_37_24 -#define BM_38_24 0x0000007fff000000 -#define BM_24_38 BM_38_24 -#define BM_39_24 0x000000ffff000000 -#define BM_24_39 BM_39_24 -#define BM_40_24 0x000001ffff000000 -#define BM_24_40 BM_40_24 -#define BM_41_24 0x000003ffff000000 -#define BM_24_41 BM_41_24 -#define BM_42_24 0x000007ffff000000 -#define BM_24_42 BM_42_24 -#define BM_43_24 0x00000fffff000000 -#define BM_24_43 BM_43_24 -#define BM_44_24 0x00001fffff000000 -#define BM_24_44 BM_44_24 -#define BM_45_24 0x00003fffff000000 -#define BM_24_45 BM_45_24 -#define BM_46_24 0x00007fffff000000 -#define BM_24_46 BM_46_24 -#define BM_47_24 0x0000ffffff000000 -#define BM_24_47 BM_47_24 -#define BM_48_24 0x0001ffffff000000 -#define BM_24_48 BM_48_24 -#define BM_49_24 0x0003ffffff000000 -#define BM_24_49 BM_49_24 -#define BM_50_24 0x0007ffffff000000 -#define BM_24_50 BM_50_24 -#define BM_51_24 0x000fffffff000000 -#define BM_24_51 BM_51_24 -#define BM_52_24 0x001fffffff000000 -#define BM_24_52 BM_52_24 -#define BM_53_24 0x003fffffff000000 -#define BM_24_53 BM_53_24 -#define BM_54_24 0x007fffffff000000 -#define BM_24_54 BM_54_24 -#define BM_55_24 0x00ffffffff000000 -#define BM_24_55 BM_55_24 -#define BM_56_24 0x01ffffffff000000 -#define BM_24_56 BM_56_24 -#define BM_57_24 0x03ffffffff000000 -#define BM_24_57 BM_57_24 -#define BM_58_24 0x07ffffffff000000 -#define BM_24_58 BM_58_24 -#define BM_59_24 0x0fffffffff000000 -#define BM_24_59 BM_59_24 -#define BM_60_24 0x1fffffffff000000 -#define BM_24_60 BM_60_24 -#define BM_61_24 0x3fffffffff000000 -#define BM_24_61 BM_61_24 -#define BM_62_24 0x7fffffffff000000 -#define BM_24_62 BM_62_24 -#define BM_63_24 0xffffffffff000000 -#define BM_24_63 BM_63_24 -#define BM_25_25 0x0000000002000000 -#define BM_26_25 0x0000000006000000 -#define BM_25_26 BM_26_25 -#define BM_27_25 0x000000000e000000 -#define BM_25_27 BM_27_25 -#define BM_28_25 0x000000001e000000 -#define BM_25_28 BM_28_25 -#define BM_29_25 0x000000003e000000 -#define BM_25_29 BM_29_25 -#define BM_30_25 0x000000007e000000 -#define BM_25_30 BM_30_25 -#define BM_31_25 0x00000000fe000000 -#define BM_25_31 BM_31_25 -#define BM_32_25 0x00000001fe000000 -#define BM_25_32 BM_32_25 -#define BM_33_25 0x00000003fe000000 -#define BM_25_33 BM_33_25 -#define BM_34_25 0x00000007fe000000 -#define BM_25_34 BM_34_25 -#define BM_35_25 0x0000000ffe000000 -#define BM_25_35 BM_35_25 -#define BM_36_25 0x0000001ffe000000 -#define BM_25_36 BM_36_25 -#define BM_37_25 0x0000003ffe000000 -#define BM_25_37 BM_37_25 -#define BM_38_25 0x0000007ffe000000 -#define BM_25_38 BM_38_25 -#define BM_39_25 0x000000fffe000000 -#define BM_25_39 BM_39_25 -#define BM_40_25 0x000001fffe000000 -#define BM_25_40 BM_40_25 -#define BM_41_25 0x000003fffe000000 -#define BM_25_41 BM_41_25 -#define BM_42_25 0x000007fffe000000 -#define BM_25_42 BM_42_25 -#define BM_43_25 0x00000ffffe000000 -#define BM_25_43 BM_43_25 -#define BM_44_25 0x00001ffffe000000 -#define BM_25_44 BM_44_25 -#define BM_45_25 0x00003ffffe000000 -#define BM_25_45 BM_45_25 -#define BM_46_25 0x00007ffffe000000 -#define BM_25_46 BM_46_25 -#define BM_47_25 0x0000fffffe000000 -#define BM_25_47 BM_47_25 -#define BM_48_25 0x0001fffffe000000 -#define BM_25_48 BM_48_25 -#define BM_49_25 0x0003fffffe000000 -#define BM_25_49 BM_49_25 -#define BM_50_25 0x0007fffffe000000 -#define BM_25_50 BM_50_25 -#define BM_51_25 0x000ffffffe000000 -#define BM_25_51 BM_51_25 -#define BM_52_25 0x001ffffffe000000 -#define BM_25_52 BM_52_25 -#define BM_53_25 0x003ffffffe000000 -#define BM_25_53 BM_53_25 -#define BM_54_25 0x007ffffffe000000 -#define BM_25_54 BM_54_25 -#define BM_55_25 0x00fffffffe000000 -#define BM_25_55 BM_55_25 -#define BM_56_25 0x01fffffffe000000 -#define BM_25_56 BM_56_25 -#define BM_57_25 0x03fffffffe000000 -#define BM_25_57 BM_57_25 -#define BM_58_25 0x07fffffffe000000 -#define BM_25_58 BM_58_25 -#define BM_59_25 0x0ffffffffe000000 -#define BM_25_59 BM_59_25 -#define BM_60_25 0x1ffffffffe000000 -#define BM_25_60 BM_60_25 -#define BM_61_25 0x3ffffffffe000000 -#define BM_25_61 BM_61_25 -#define BM_62_25 0x7ffffffffe000000 -#define BM_25_62 BM_62_25 -#define BM_63_25 0xfffffffffe000000 -#define BM_25_63 BM_63_25 -#define BM_26_26 0x0000000004000000 -#define BM_27_26 0x000000000c000000 -#define BM_26_27 BM_27_26 -#define BM_28_26 0x000000001c000000 -#define BM_26_28 BM_28_26 -#define BM_29_26 0x000000003c000000 -#define BM_26_29 BM_29_26 -#define BM_30_26 0x000000007c000000 -#define BM_26_30 BM_30_26 -#define BM_31_26 0x00000000fc000000 -#define BM_26_31 BM_31_26 -#define BM_32_26 0x00000001fc000000 -#define BM_26_32 BM_32_26 -#define BM_33_26 0x00000003fc000000 -#define BM_26_33 BM_33_26 -#define BM_34_26 0x00000007fc000000 -#define BM_26_34 BM_34_26 -#define BM_35_26 0x0000000ffc000000 -#define BM_26_35 BM_35_26 -#define BM_36_26 0x0000001ffc000000 -#define BM_26_36 BM_36_26 -#define BM_37_26 0x0000003ffc000000 -#define BM_26_37 BM_37_26 -#define BM_38_26 0x0000007ffc000000 -#define BM_26_38 BM_38_26 -#define BM_39_26 0x000000fffc000000 -#define BM_26_39 BM_39_26 -#define BM_40_26 0x000001fffc000000 -#define BM_26_40 BM_40_26 -#define BM_41_26 0x000003fffc000000 -#define BM_26_41 BM_41_26 -#define BM_42_26 0x000007fffc000000 -#define BM_26_42 BM_42_26 -#define BM_43_26 0x00000ffffc000000 -#define BM_26_43 BM_43_26 -#define BM_44_26 0x00001ffffc000000 -#define BM_26_44 BM_44_26 -#define BM_45_26 0x00003ffffc000000 -#define BM_26_45 BM_45_26 -#define BM_46_26 0x00007ffffc000000 -#define BM_26_46 BM_46_26 -#define BM_47_26 0x0000fffffc000000 -#define BM_26_47 BM_47_26 -#define BM_48_26 0x0001fffffc000000 -#define BM_26_48 BM_48_26 -#define BM_49_26 0x0003fffffc000000 -#define BM_26_49 BM_49_26 -#define BM_50_26 0x0007fffffc000000 -#define BM_26_50 BM_50_26 -#define BM_51_26 0x000ffffffc000000 -#define BM_26_51 BM_51_26 -#define BM_52_26 0x001ffffffc000000 -#define BM_26_52 BM_52_26 -#define BM_53_26 0x003ffffffc000000 -#define BM_26_53 BM_53_26 -#define BM_54_26 0x007ffffffc000000 -#define BM_26_54 BM_54_26 -#define BM_55_26 0x00fffffffc000000 -#define BM_26_55 BM_55_26 -#define BM_56_26 0x01fffffffc000000 -#define BM_26_56 BM_56_26 -#define BM_57_26 0x03fffffffc000000 -#define BM_26_57 BM_57_26 -#define BM_58_26 0x07fffffffc000000 -#define BM_26_58 BM_58_26 -#define BM_59_26 0x0ffffffffc000000 -#define BM_26_59 BM_59_26 -#define BM_60_26 0x1ffffffffc000000 -#define BM_26_60 BM_60_26 -#define BM_61_26 0x3ffffffffc000000 -#define BM_26_61 BM_61_26 -#define BM_62_26 0x7ffffffffc000000 -#define BM_26_62 BM_62_26 -#define BM_63_26 0xfffffffffc000000 -#define BM_26_63 BM_63_26 -#define BM_27_27 0x0000000008000000 -#define BM_28_27 0x0000000018000000 -#define BM_27_28 BM_28_27 -#define BM_29_27 0x0000000038000000 -#define BM_27_29 BM_29_27 -#define BM_30_27 0x0000000078000000 -#define BM_27_30 BM_30_27 -#define BM_31_27 0x00000000f8000000 -#define BM_27_31 BM_31_27 -#define BM_32_27 0x00000001f8000000 -#define BM_27_32 BM_32_27 -#define BM_33_27 0x00000003f8000000 -#define BM_27_33 BM_33_27 -#define BM_34_27 0x00000007f8000000 -#define BM_27_34 BM_34_27 -#define BM_35_27 0x0000000ff8000000 -#define BM_27_35 BM_35_27 -#define BM_36_27 0x0000001ff8000000 -#define BM_27_36 BM_36_27 -#define BM_37_27 0x0000003ff8000000 -#define BM_27_37 BM_37_27 -#define BM_38_27 0x0000007ff8000000 -#define BM_27_38 BM_38_27 -#define BM_39_27 0x000000fff8000000 -#define BM_27_39 BM_39_27 -#define BM_40_27 0x000001fff8000000 -#define BM_27_40 BM_40_27 -#define BM_41_27 0x000003fff8000000 -#define BM_27_41 BM_41_27 -#define BM_42_27 0x000007fff8000000 -#define BM_27_42 BM_42_27 -#define BM_43_27 0x00000ffff8000000 -#define BM_27_43 BM_43_27 -#define BM_44_27 0x00001ffff8000000 -#define BM_27_44 BM_44_27 -#define BM_45_27 0x00003ffff8000000 -#define BM_27_45 BM_45_27 -#define BM_46_27 0x00007ffff8000000 -#define BM_27_46 BM_46_27 -#define BM_47_27 0x0000fffff8000000 -#define BM_27_47 BM_47_27 -#define BM_48_27 0x0001fffff8000000 -#define BM_27_48 BM_48_27 -#define BM_49_27 0x0003fffff8000000 -#define BM_27_49 BM_49_27 -#define BM_50_27 0x0007fffff8000000 -#define BM_27_50 BM_50_27 -#define BM_51_27 0x000ffffff8000000 -#define BM_27_51 BM_51_27 -#define BM_52_27 0x001ffffff8000000 -#define BM_27_52 BM_52_27 -#define BM_53_27 0x003ffffff8000000 -#define BM_27_53 BM_53_27 -#define BM_54_27 0x007ffffff8000000 -#define BM_27_54 BM_54_27 -#define BM_55_27 0x00fffffff8000000 -#define BM_27_55 BM_55_27 -#define BM_56_27 0x01fffffff8000000 -#define BM_27_56 BM_56_27 -#define BM_57_27 0x03fffffff8000000 -#define BM_27_57 BM_57_27 -#define BM_58_27 0x07fffffff8000000 -#define BM_27_58 BM_58_27 -#define BM_59_27 0x0ffffffff8000000 -#define BM_27_59 BM_59_27 -#define BM_60_27 0x1ffffffff8000000 -#define BM_27_60 BM_60_27 -#define BM_61_27 0x3ffffffff8000000 -#define BM_27_61 BM_61_27 -#define BM_62_27 0x7ffffffff8000000 -#define BM_27_62 BM_62_27 -#define BM_63_27 0xfffffffff8000000 -#define BM_27_63 BM_63_27 -#define BM_28_28 0x0000000010000000 -#define BM_29_28 0x0000000030000000 -#define BM_28_29 BM_29_28 -#define BM_30_28 0x0000000070000000 -#define BM_28_30 BM_30_28 -#define BM_31_28 0x00000000f0000000 -#define BM_28_31 BM_31_28 -#define BM_32_28 0x00000001f0000000 -#define BM_28_32 BM_32_28 -#define BM_33_28 0x00000003f0000000 -#define BM_28_33 BM_33_28 -#define BM_34_28 0x00000007f0000000 -#define BM_28_34 BM_34_28 -#define BM_35_28 0x0000000ff0000000 -#define BM_28_35 BM_35_28 -#define BM_36_28 0x0000001ff0000000 -#define BM_28_36 BM_36_28 -#define BM_37_28 0x0000003ff0000000 -#define BM_28_37 BM_37_28 -#define BM_38_28 0x0000007ff0000000 -#define BM_28_38 BM_38_28 -#define BM_39_28 0x000000fff0000000 -#define BM_28_39 BM_39_28 -#define BM_40_28 0x000001fff0000000 -#define BM_28_40 BM_40_28 -#define BM_41_28 0x000003fff0000000 -#define BM_28_41 BM_41_28 -#define BM_42_28 0x000007fff0000000 -#define BM_28_42 BM_42_28 -#define BM_43_28 0x00000ffff0000000 -#define BM_28_43 BM_43_28 -#define BM_44_28 0x00001ffff0000000 -#define BM_28_44 BM_44_28 -#define BM_45_28 0x00003ffff0000000 -#define BM_28_45 BM_45_28 -#define BM_46_28 0x00007ffff0000000 -#define BM_28_46 BM_46_28 -#define BM_47_28 0x0000fffff0000000 -#define BM_28_47 BM_47_28 -#define BM_48_28 0x0001fffff0000000 -#define BM_28_48 BM_48_28 -#define BM_49_28 0x0003fffff0000000 -#define BM_28_49 BM_49_28 -#define BM_50_28 0x0007fffff0000000 -#define BM_28_50 BM_50_28 -#define BM_51_28 0x000ffffff0000000 -#define BM_28_51 BM_51_28 -#define BM_52_28 0x001ffffff0000000 -#define BM_28_52 BM_52_28 -#define BM_53_28 0x003ffffff0000000 -#define BM_28_53 BM_53_28 -#define BM_54_28 0x007ffffff0000000 -#define BM_28_54 BM_54_28 -#define BM_55_28 0x00fffffff0000000 -#define BM_28_55 BM_55_28 -#define BM_56_28 0x01fffffff0000000 -#define BM_28_56 BM_56_28 -#define BM_57_28 0x03fffffff0000000 -#define BM_28_57 BM_57_28 -#define BM_58_28 0x07fffffff0000000 -#define BM_28_58 BM_58_28 -#define BM_59_28 0x0ffffffff0000000 -#define BM_28_59 BM_59_28 -#define BM_60_28 0x1ffffffff0000000 -#define BM_28_60 BM_60_28 -#define BM_61_28 0x3ffffffff0000000 -#define BM_28_61 BM_61_28 -#define BM_62_28 0x7ffffffff0000000 -#define BM_28_62 BM_62_28 -#define BM_63_28 0xfffffffff0000000 -#define BM_28_63 BM_63_28 -#define BM_29_29 0x0000000020000000 -#define BM_30_29 0x0000000060000000 -#define BM_29_30 BM_30_29 -#define BM_31_29 0x00000000e0000000 -#define BM_29_31 BM_31_29 -#define BM_32_29 0x00000001e0000000 -#define BM_29_32 BM_32_29 -#define BM_33_29 0x00000003e0000000 -#define BM_29_33 BM_33_29 -#define BM_34_29 0x00000007e0000000 -#define BM_29_34 BM_34_29 -#define BM_35_29 0x0000000fe0000000 -#define BM_29_35 BM_35_29 -#define BM_36_29 0x0000001fe0000000 -#define BM_29_36 BM_36_29 -#define BM_37_29 0x0000003fe0000000 -#define BM_29_37 BM_37_29 -#define BM_38_29 0x0000007fe0000000 -#define BM_29_38 BM_38_29 -#define BM_39_29 0x000000ffe0000000 -#define BM_29_39 BM_39_29 -#define BM_40_29 0x000001ffe0000000 -#define BM_29_40 BM_40_29 -#define BM_41_29 0x000003ffe0000000 -#define BM_29_41 BM_41_29 -#define BM_42_29 0x000007ffe0000000 -#define BM_29_42 BM_42_29 -#define BM_43_29 0x00000fffe0000000 -#define BM_29_43 BM_43_29 -#define BM_44_29 0x00001fffe0000000 -#define BM_29_44 BM_44_29 -#define BM_45_29 0x00003fffe0000000 -#define BM_29_45 BM_45_29 -#define BM_46_29 0x00007fffe0000000 -#define BM_29_46 BM_46_29 -#define BM_47_29 0x0000ffffe0000000 -#define BM_29_47 BM_47_29 -#define BM_48_29 0x0001ffffe0000000 -#define BM_29_48 BM_48_29 -#define BM_49_29 0x0003ffffe0000000 -#define BM_29_49 BM_49_29 -#define BM_50_29 0x0007ffffe0000000 -#define BM_29_50 BM_50_29 -#define BM_51_29 0x000fffffe0000000 -#define BM_29_51 BM_51_29 -#define BM_52_29 0x001fffffe0000000 -#define BM_29_52 BM_52_29 -#define BM_53_29 0x003fffffe0000000 -#define BM_29_53 BM_53_29 -#define BM_54_29 0x007fffffe0000000 -#define BM_29_54 BM_54_29 -#define BM_55_29 0x00ffffffe0000000 -#define BM_29_55 BM_55_29 -#define BM_56_29 0x01ffffffe0000000 -#define BM_29_56 BM_56_29 -#define BM_57_29 0x03ffffffe0000000 -#define BM_29_57 BM_57_29 -#define BM_58_29 0x07ffffffe0000000 -#define BM_29_58 BM_58_29 -#define BM_59_29 0x0fffffffe0000000 -#define BM_29_59 BM_59_29 -#define BM_60_29 0x1fffffffe0000000 -#define BM_29_60 BM_60_29 -#define BM_61_29 0x3fffffffe0000000 -#define BM_29_61 BM_61_29 -#define BM_62_29 0x7fffffffe0000000 -#define BM_29_62 BM_62_29 -#define BM_63_29 0xffffffffe0000000 -#define BM_29_63 BM_63_29 -#define BM_30_30 0x0000000040000000 -#define BM_31_30 0x00000000c0000000 -#define BM_30_31 BM_31_30 -#define BM_32_30 0x00000001c0000000 -#define BM_30_32 BM_32_30 -#define BM_33_30 0x00000003c0000000 -#define BM_30_33 BM_33_30 -#define BM_34_30 0x00000007c0000000 -#define BM_30_34 BM_34_30 -#define BM_35_30 0x0000000fc0000000 -#define BM_30_35 BM_35_30 -#define BM_36_30 0x0000001fc0000000 -#define BM_30_36 BM_36_30 -#define BM_37_30 0x0000003fc0000000 -#define BM_30_37 BM_37_30 -#define BM_38_30 0x0000007fc0000000 -#define BM_30_38 BM_38_30 -#define BM_39_30 0x000000ffc0000000 -#define BM_30_39 BM_39_30 -#define BM_40_30 0x000001ffc0000000 -#define BM_30_40 BM_40_30 -#define BM_41_30 0x000003ffc0000000 -#define BM_30_41 BM_41_30 -#define BM_42_30 0x000007ffc0000000 -#define BM_30_42 BM_42_30 -#define BM_43_30 0x00000fffc0000000 -#define BM_30_43 BM_43_30 -#define BM_44_30 0x00001fffc0000000 -#define BM_30_44 BM_44_30 -#define BM_45_30 0x00003fffc0000000 -#define BM_30_45 BM_45_30 -#define BM_46_30 0x00007fffc0000000 -#define BM_30_46 BM_46_30 -#define BM_47_30 0x0000ffffc0000000 -#define BM_30_47 BM_47_30 -#define BM_48_30 0x0001ffffc0000000 -#define BM_30_48 BM_48_30 -#define BM_49_30 0x0003ffffc0000000 -#define BM_30_49 BM_49_30 -#define BM_50_30 0x0007ffffc0000000 -#define BM_30_50 BM_50_30 -#define BM_51_30 0x000fffffc0000000 -#define BM_30_51 BM_51_30 -#define BM_52_30 0x001fffffc0000000 -#define BM_30_52 BM_52_30 -#define BM_53_30 0x003fffffc0000000 -#define BM_30_53 BM_53_30 -#define BM_54_30 0x007fffffc0000000 -#define BM_30_54 BM_54_30 -#define BM_55_30 0x00ffffffc0000000 -#define BM_30_55 BM_55_30 -#define BM_56_30 0x01ffffffc0000000 -#define BM_30_56 BM_56_30 -#define BM_57_30 0x03ffffffc0000000 -#define BM_30_57 BM_57_30 -#define BM_58_30 0x07ffffffc0000000 -#define BM_30_58 BM_58_30 -#define BM_59_30 0x0fffffffc0000000 -#define BM_30_59 BM_59_30 -#define BM_60_30 0x1fffffffc0000000 -#define BM_30_60 BM_60_30 -#define BM_61_30 0x3fffffffc0000000 -#define BM_30_61 BM_61_30 -#define BM_62_30 0x7fffffffc0000000 -#define BM_30_62 BM_62_30 -#define BM_63_30 0xffffffffc0000000 -#define BM_30_63 BM_63_30 -#define BM_31_31 0x0000000080000000 -#define BM_32_31 0x0000000180000000 -#define BM_31_32 BM_32_31 -#define BM_33_31 0x0000000380000000 -#define BM_31_33 BM_33_31 -#define BM_34_31 0x0000000780000000 -#define BM_31_34 BM_34_31 -#define BM_35_31 0x0000000f80000000 -#define BM_31_35 BM_35_31 -#define BM_36_31 0x0000001f80000000 -#define BM_31_36 BM_36_31 -#define BM_37_31 0x0000003f80000000 -#define BM_31_37 BM_37_31 -#define BM_38_31 0x0000007f80000000 -#define BM_31_38 BM_38_31 -#define BM_39_31 0x000000ff80000000 -#define BM_31_39 BM_39_31 -#define BM_40_31 0x000001ff80000000 -#define BM_31_40 BM_40_31 -#define BM_41_31 0x000003ff80000000 -#define BM_31_41 BM_41_31 -#define BM_42_31 0x000007ff80000000 -#define BM_31_42 BM_42_31 -#define BM_43_31 0x00000fff80000000 -#define BM_31_43 BM_43_31 -#define BM_44_31 0x00001fff80000000 -#define BM_31_44 BM_44_31 -#define BM_45_31 0x00003fff80000000 -#define BM_31_45 BM_45_31 -#define BM_46_31 0x00007fff80000000 -#define BM_31_46 BM_46_31 -#define BM_47_31 0x0000ffff80000000 -#define BM_31_47 BM_47_31 -#define BM_48_31 0x0001ffff80000000 -#define BM_31_48 BM_48_31 -#define BM_49_31 0x0003ffff80000000 -#define BM_31_49 BM_49_31 -#define BM_50_31 0x0007ffff80000000 -#define BM_31_50 BM_50_31 -#define BM_51_31 0x000fffff80000000 -#define BM_31_51 BM_51_31 -#define BM_52_31 0x001fffff80000000 -#define BM_31_52 BM_52_31 -#define BM_53_31 0x003fffff80000000 -#define BM_31_53 BM_53_31 -#define BM_54_31 0x007fffff80000000 -#define BM_31_54 BM_54_31 -#define BM_55_31 0x00ffffff80000000 -#define BM_31_55 BM_55_31 -#define BM_56_31 0x01ffffff80000000 -#define BM_31_56 BM_56_31 -#define BM_57_31 0x03ffffff80000000 -#define BM_31_57 BM_57_31 -#define BM_58_31 0x07ffffff80000000 -#define BM_31_58 BM_58_31 -#define BM_59_31 0x0fffffff80000000 -#define BM_31_59 BM_59_31 -#define BM_60_31 0x1fffffff80000000 -#define BM_31_60 BM_60_31 -#define BM_61_31 0x3fffffff80000000 -#define BM_31_61 BM_61_31 -#define BM_62_31 0x7fffffff80000000 -#define BM_31_62 BM_62_31 -#define BM_63_31 0xffffffff80000000 -#define BM_31_63 BM_63_31 -#define BM_32_32 0x0000000100000000 -#define BM_33_32 0x0000000300000000 -#define BM_32_33 BM_33_32 -#define BM_34_32 0x0000000700000000 -#define BM_32_34 BM_34_32 -#define BM_35_32 0x0000000f00000000 -#define BM_32_35 BM_35_32 -#define BM_36_32 0x0000001f00000000 -#define BM_32_36 BM_36_32 -#define BM_37_32 0x0000003f00000000 -#define BM_32_37 BM_37_32 -#define BM_38_32 0x0000007f00000000 -#define BM_32_38 BM_38_32 -#define BM_39_32 0x000000ff00000000 -#define BM_32_39 BM_39_32 -#define BM_40_32 0x000001ff00000000 -#define BM_32_40 BM_40_32 -#define BM_41_32 0x000003ff00000000 -#define BM_32_41 BM_41_32 -#define BM_42_32 0x000007ff00000000 -#define BM_32_42 BM_42_32 -#define BM_43_32 0x00000fff00000000 -#define BM_32_43 BM_43_32 -#define BM_44_32 0x00001fff00000000 -#define BM_32_44 BM_44_32 -#define BM_45_32 0x00003fff00000000 -#define BM_32_45 BM_45_32 -#define BM_46_32 0x00007fff00000000 -#define BM_32_46 BM_46_32 -#define BM_47_32 0x0000ffff00000000 -#define BM_32_47 BM_47_32 -#define BM_48_32 0x0001ffff00000000 -#define BM_32_48 BM_48_32 -#define BM_49_32 0x0003ffff00000000 -#define BM_32_49 BM_49_32 -#define BM_50_32 0x0007ffff00000000 -#define BM_32_50 BM_50_32 -#define BM_51_32 0x000fffff00000000 -#define BM_32_51 BM_51_32 -#define BM_52_32 0x001fffff00000000 -#define BM_32_52 BM_52_32 -#define BM_53_32 0x003fffff00000000 -#define BM_32_53 BM_53_32 -#define BM_54_32 0x007fffff00000000 -#define BM_32_54 BM_54_32 -#define BM_55_32 0x00ffffff00000000 -#define BM_32_55 BM_55_32 -#define BM_56_32 0x01ffffff00000000 -#define BM_32_56 BM_56_32 -#define BM_57_32 0x03ffffff00000000 -#define BM_32_57 BM_57_32 -#define BM_58_32 0x07ffffff00000000 -#define BM_32_58 BM_58_32 -#define BM_59_32 0x0fffffff00000000 -#define BM_32_59 BM_59_32 -#define BM_60_32 0x1fffffff00000000 -#define BM_32_60 BM_60_32 -#define BM_61_32 0x3fffffff00000000 -#define BM_32_61 BM_61_32 -#define BM_62_32 0x7fffffff00000000 -#define BM_32_62 BM_62_32 -#define BM_63_32 0xffffffff00000000 -#define BM_32_63 BM_63_32 -#define BM_33_33 0x0000000200000000 -#define BM_34_33 0x0000000600000000 -#define BM_33_34 BM_34_33 -#define BM_35_33 0x0000000e00000000 -#define BM_33_35 BM_35_33 -#define BM_36_33 0x0000001e00000000 -#define BM_33_36 BM_36_33 -#define BM_37_33 0x0000003e00000000 -#define BM_33_37 BM_37_33 -#define BM_38_33 0x0000007e00000000 -#define BM_33_38 BM_38_33 -#define BM_39_33 0x000000fe00000000 -#define BM_33_39 BM_39_33 -#define BM_40_33 0x000001fe00000000 -#define BM_33_40 BM_40_33 -#define BM_41_33 0x000003fe00000000 -#define BM_33_41 BM_41_33 -#define BM_42_33 0x000007fe00000000 -#define BM_33_42 BM_42_33 -#define BM_43_33 0x00000ffe00000000 -#define BM_33_43 BM_43_33 -#define BM_44_33 0x00001ffe00000000 -#define BM_33_44 BM_44_33 -#define BM_45_33 0x00003ffe00000000 -#define BM_33_45 BM_45_33 -#define BM_46_33 0x00007ffe00000000 -#define BM_33_46 BM_46_33 -#define BM_47_33 0x0000fffe00000000 -#define BM_33_47 BM_47_33 -#define BM_48_33 0x0001fffe00000000 -#define BM_33_48 BM_48_33 -#define BM_49_33 0x0003fffe00000000 -#define BM_33_49 BM_49_33 -#define BM_50_33 0x0007fffe00000000 -#define BM_33_50 BM_50_33 -#define BM_51_33 0x000ffffe00000000 -#define BM_33_51 BM_51_33 -#define BM_52_33 0x001ffffe00000000 -#define BM_33_52 BM_52_33 -#define BM_53_33 0x003ffffe00000000 -#define BM_33_53 BM_53_33 -#define BM_54_33 0x007ffffe00000000 -#define BM_33_54 BM_54_33 -#define BM_55_33 0x00fffffe00000000 -#define BM_33_55 BM_55_33 -#define BM_56_33 0x01fffffe00000000 -#define BM_33_56 BM_56_33 -#define BM_57_33 0x03fffffe00000000 -#define BM_33_57 BM_57_33 -#define BM_58_33 0x07fffffe00000000 -#define BM_33_58 BM_58_33 -#define BM_59_33 0x0ffffffe00000000 -#define BM_33_59 BM_59_33 -#define BM_60_33 0x1ffffffe00000000 -#define BM_33_60 BM_60_33 -#define BM_61_33 0x3ffffffe00000000 -#define BM_33_61 BM_61_33 -#define BM_62_33 0x7ffffffe00000000 -#define BM_33_62 BM_62_33 -#define BM_63_33 0xfffffffe00000000 -#define BM_33_63 BM_63_33 -#define BM_34_34 0x0000000400000000 -#define BM_35_34 0x0000000c00000000 -#define BM_34_35 BM_35_34 -#define BM_36_34 0x0000001c00000000 -#define BM_34_36 BM_36_34 -#define BM_37_34 0x0000003c00000000 -#define BM_34_37 BM_37_34 -#define BM_38_34 0x0000007c00000000 -#define BM_34_38 BM_38_34 -#define BM_39_34 0x000000fc00000000 -#define BM_34_39 BM_39_34 -#define BM_40_34 0x000001fc00000000 -#define BM_34_40 BM_40_34 -#define BM_41_34 0x000003fc00000000 -#define BM_34_41 BM_41_34 -#define BM_42_34 0x000007fc00000000 -#define BM_34_42 BM_42_34 -#define BM_43_34 0x00000ffc00000000 -#define BM_34_43 BM_43_34 -#define BM_44_34 0x00001ffc00000000 -#define BM_34_44 BM_44_34 -#define BM_45_34 0x00003ffc00000000 -#define BM_34_45 BM_45_34 -#define BM_46_34 0x00007ffc00000000 -#define BM_34_46 BM_46_34 -#define BM_47_34 0x0000fffc00000000 -#define BM_34_47 BM_47_34 -#define BM_48_34 0x0001fffc00000000 -#define BM_34_48 BM_48_34 -#define BM_49_34 0x0003fffc00000000 -#define BM_34_49 BM_49_34 -#define BM_50_34 0x0007fffc00000000 -#define BM_34_50 BM_50_34 -#define BM_51_34 0x000ffffc00000000 -#define BM_34_51 BM_51_34 -#define BM_52_34 0x001ffffc00000000 -#define BM_34_52 BM_52_34 -#define BM_53_34 0x003ffffc00000000 -#define BM_34_53 BM_53_34 -#define BM_54_34 0x007ffffc00000000 -#define BM_34_54 BM_54_34 -#define BM_55_34 0x00fffffc00000000 -#define BM_34_55 BM_55_34 -#define BM_56_34 0x01fffffc00000000 -#define BM_34_56 BM_56_34 -#define BM_57_34 0x03fffffc00000000 -#define BM_34_57 BM_57_34 -#define BM_58_34 0x07fffffc00000000 -#define BM_34_58 BM_58_34 -#define BM_59_34 0x0ffffffc00000000 -#define BM_34_59 BM_59_34 -#define BM_60_34 0x1ffffffc00000000 -#define BM_34_60 BM_60_34 -#define BM_61_34 0x3ffffffc00000000 -#define BM_34_61 BM_61_34 -#define BM_62_34 0x7ffffffc00000000 -#define BM_34_62 BM_62_34 -#define BM_63_34 0xfffffffc00000000 -#define BM_34_63 BM_63_34 -#define BM_35_35 0x0000000800000000 -#define BM_36_35 0x0000001800000000 -#define BM_35_36 BM_36_35 -#define BM_37_35 0x0000003800000000 -#define BM_35_37 BM_37_35 -#define BM_38_35 0x0000007800000000 -#define BM_35_38 BM_38_35 -#define BM_39_35 0x000000f800000000 -#define BM_35_39 BM_39_35 -#define BM_40_35 0x000001f800000000 -#define BM_35_40 BM_40_35 -#define BM_41_35 0x000003f800000000 -#define BM_35_41 BM_41_35 -#define BM_42_35 0x000007f800000000 -#define BM_35_42 BM_42_35 -#define BM_43_35 0x00000ff800000000 -#define BM_35_43 BM_43_35 -#define BM_44_35 0x00001ff800000000 -#define BM_35_44 BM_44_35 -#define BM_45_35 0x00003ff800000000 -#define BM_35_45 BM_45_35 -#define BM_46_35 0x00007ff800000000 -#define BM_35_46 BM_46_35 -#define BM_47_35 0x0000fff800000000 -#define BM_35_47 BM_47_35 -#define BM_48_35 0x0001fff800000000 -#define BM_35_48 BM_48_35 -#define BM_49_35 0x0003fff800000000 -#define BM_35_49 BM_49_35 -#define BM_50_35 0x0007fff800000000 -#define BM_35_50 BM_50_35 -#define BM_51_35 0x000ffff800000000 -#define BM_35_51 BM_51_35 -#define BM_52_35 0x001ffff800000000 -#define BM_35_52 BM_52_35 -#define BM_53_35 0x003ffff800000000 -#define BM_35_53 BM_53_35 -#define BM_54_35 0x007ffff800000000 -#define BM_35_54 BM_54_35 -#define BM_55_35 0x00fffff800000000 -#define BM_35_55 BM_55_35 -#define BM_56_35 0x01fffff800000000 -#define BM_35_56 BM_56_35 -#define BM_57_35 0x03fffff800000000 -#define BM_35_57 BM_57_35 -#define BM_58_35 0x07fffff800000000 -#define BM_35_58 BM_58_35 -#define BM_59_35 0x0ffffff800000000 -#define BM_35_59 BM_59_35 -#define BM_60_35 0x1ffffff800000000 -#define BM_35_60 BM_60_35 -#define BM_61_35 0x3ffffff800000000 -#define BM_35_61 BM_61_35 -#define BM_62_35 0x7ffffff800000000 -#define BM_35_62 BM_62_35 -#define BM_63_35 0xfffffff800000000 -#define BM_35_63 BM_63_35 -#define BM_36_36 0x0000001000000000 -#define BM_37_36 0x0000003000000000 -#define BM_36_37 BM_37_36 -#define BM_38_36 0x0000007000000000 -#define BM_36_38 BM_38_36 -#define BM_39_36 0x000000f000000000 -#define BM_36_39 BM_39_36 -#define BM_40_36 0x000001f000000000 -#define BM_36_40 BM_40_36 -#define BM_41_36 0x000003f000000000 -#define BM_36_41 BM_41_36 -#define BM_42_36 0x000007f000000000 -#define BM_36_42 BM_42_36 -#define BM_43_36 0x00000ff000000000 -#define BM_36_43 BM_43_36 -#define BM_44_36 0x00001ff000000000 -#define BM_36_44 BM_44_36 -#define BM_45_36 0x00003ff000000000 -#define BM_36_45 BM_45_36 -#define BM_46_36 0x00007ff000000000 -#define BM_36_46 BM_46_36 -#define BM_47_36 0x0000fff000000000 -#define BM_36_47 BM_47_36 -#define BM_48_36 0x0001fff000000000 -#define BM_36_48 BM_48_36 -#define BM_49_36 0x0003fff000000000 -#define BM_36_49 BM_49_36 -#define BM_50_36 0x0007fff000000000 -#define BM_36_50 BM_50_36 -#define BM_51_36 0x000ffff000000000 -#define BM_36_51 BM_51_36 -#define BM_52_36 0x001ffff000000000 -#define BM_36_52 BM_52_36 -#define BM_53_36 0x003ffff000000000 -#define BM_36_53 BM_53_36 -#define BM_54_36 0x007ffff000000000 -#define BM_36_54 BM_54_36 -#define BM_55_36 0x00fffff000000000 -#define BM_36_55 BM_55_36 -#define BM_56_36 0x01fffff000000000 -#define BM_36_56 BM_56_36 -#define BM_57_36 0x03fffff000000000 -#define BM_36_57 BM_57_36 -#define BM_58_36 0x07fffff000000000 -#define BM_36_58 BM_58_36 -#define BM_59_36 0x0ffffff000000000 -#define BM_36_59 BM_59_36 -#define BM_60_36 0x1ffffff000000000 -#define BM_36_60 BM_60_36 -#define BM_61_36 0x3ffffff000000000 -#define BM_36_61 BM_61_36 -#define BM_62_36 0x7ffffff000000000 -#define BM_36_62 BM_62_36 -#define BM_63_36 0xfffffff000000000 -#define BM_36_63 BM_63_36 -#define BM_37_37 0x0000002000000000 -#define BM_38_37 0x0000006000000000 -#define BM_37_38 BM_38_37 -#define BM_39_37 0x000000e000000000 -#define BM_37_39 BM_39_37 -#define BM_40_37 0x000001e000000000 -#define BM_37_40 BM_40_37 -#define BM_41_37 0x000003e000000000 -#define BM_37_41 BM_41_37 -#define BM_42_37 0x000007e000000000 -#define BM_37_42 BM_42_37 -#define BM_43_37 0x00000fe000000000 -#define BM_37_43 BM_43_37 -#define BM_44_37 0x00001fe000000000 -#define BM_37_44 BM_44_37 -#define BM_45_37 0x00003fe000000000 -#define BM_37_45 BM_45_37 -#define BM_46_37 0x00007fe000000000 -#define BM_37_46 BM_46_37 -#define BM_47_37 0x0000ffe000000000 -#define BM_37_47 BM_47_37 -#define BM_48_37 0x0001ffe000000000 -#define BM_37_48 BM_48_37 -#define BM_49_37 0x0003ffe000000000 -#define BM_37_49 BM_49_37 -#define BM_50_37 0x0007ffe000000000 -#define BM_37_50 BM_50_37 -#define BM_51_37 0x000fffe000000000 -#define BM_37_51 BM_51_37 -#define BM_52_37 0x001fffe000000000 -#define BM_37_52 BM_52_37 -#define BM_53_37 0x003fffe000000000 -#define BM_37_53 BM_53_37 -#define BM_54_37 0x007fffe000000000 -#define BM_37_54 BM_54_37 -#define BM_55_37 0x00ffffe000000000 -#define BM_37_55 BM_55_37 -#define BM_56_37 0x01ffffe000000000 -#define BM_37_56 BM_56_37 -#define BM_57_37 0x03ffffe000000000 -#define BM_37_57 BM_57_37 -#define BM_58_37 0x07ffffe000000000 -#define BM_37_58 BM_58_37 -#define BM_59_37 0x0fffffe000000000 -#define BM_37_59 BM_59_37 -#define BM_60_37 0x1fffffe000000000 -#define BM_37_60 BM_60_37 -#define BM_61_37 0x3fffffe000000000 -#define BM_37_61 BM_61_37 -#define BM_62_37 0x7fffffe000000000 -#define BM_37_62 BM_62_37 -#define BM_63_37 0xffffffe000000000 -#define BM_37_63 BM_63_37 -#define BM_38_38 0x0000004000000000 -#define BM_39_38 0x000000c000000000 -#define BM_38_39 BM_39_38 -#define BM_40_38 0x000001c000000000 -#define BM_38_40 BM_40_38 -#define BM_41_38 0x000003c000000000 -#define BM_38_41 BM_41_38 -#define BM_42_38 0x000007c000000000 -#define BM_38_42 BM_42_38 -#define BM_43_38 0x00000fc000000000 -#define BM_38_43 BM_43_38 -#define BM_44_38 0x00001fc000000000 -#define BM_38_44 BM_44_38 -#define BM_45_38 0x00003fc000000000 -#define BM_38_45 BM_45_38 -#define BM_46_38 0x00007fc000000000 -#define BM_38_46 BM_46_38 -#define BM_47_38 0x0000ffc000000000 -#define BM_38_47 BM_47_38 -#define BM_48_38 0x0001ffc000000000 -#define BM_38_48 BM_48_38 -#define BM_49_38 0x0003ffc000000000 -#define BM_38_49 BM_49_38 -#define BM_50_38 0x0007ffc000000000 -#define BM_38_50 BM_50_38 -#define BM_51_38 0x000fffc000000000 -#define BM_38_51 BM_51_38 -#define BM_52_38 0x001fffc000000000 -#define BM_38_52 BM_52_38 -#define BM_53_38 0x003fffc000000000 -#define BM_38_53 BM_53_38 -#define BM_54_38 0x007fffc000000000 -#define BM_38_54 BM_54_38 -#define BM_55_38 0x00ffffc000000000 -#define BM_38_55 BM_55_38 -#define BM_56_38 0x01ffffc000000000 -#define BM_38_56 BM_56_38 -#define BM_57_38 0x03ffffc000000000 -#define BM_38_57 BM_57_38 -#define BM_58_38 0x07ffffc000000000 -#define BM_38_58 BM_58_38 -#define BM_59_38 0x0fffffc000000000 -#define BM_38_59 BM_59_38 -#define BM_60_38 0x1fffffc000000000 -#define BM_38_60 BM_60_38 -#define BM_61_38 0x3fffffc000000000 -#define BM_38_61 BM_61_38 -#define BM_62_38 0x7fffffc000000000 -#define BM_38_62 BM_62_38 -#define BM_63_38 0xffffffc000000000 -#define BM_38_63 BM_63_38 -#define BM_39_39 0x0000008000000000 -#define BM_40_39 0x0000018000000000 -#define BM_39_40 BM_40_39 -#define BM_41_39 0x0000038000000000 -#define BM_39_41 BM_41_39 -#define BM_42_39 0x0000078000000000 -#define BM_39_42 BM_42_39 -#define BM_43_39 0x00000f8000000000 -#define BM_39_43 BM_43_39 -#define BM_44_39 0x00001f8000000000 -#define BM_39_44 BM_44_39 -#define BM_45_39 0x00003f8000000000 -#define BM_39_45 BM_45_39 -#define BM_46_39 0x00007f8000000000 -#define BM_39_46 BM_46_39 -#define BM_47_39 0x0000ff8000000000 -#define BM_39_47 BM_47_39 -#define BM_48_39 0x0001ff8000000000 -#define BM_39_48 BM_48_39 -#define BM_49_39 0x0003ff8000000000 -#define BM_39_49 BM_49_39 -#define BM_50_39 0x0007ff8000000000 -#define BM_39_50 BM_50_39 -#define BM_51_39 0x000fff8000000000 -#define BM_39_51 BM_51_39 -#define BM_52_39 0x001fff8000000000 -#define BM_39_52 BM_52_39 -#define BM_53_39 0x003fff8000000000 -#define BM_39_53 BM_53_39 -#define BM_54_39 0x007fff8000000000 -#define BM_39_54 BM_54_39 -#define BM_55_39 0x00ffff8000000000 -#define BM_39_55 BM_55_39 -#define BM_56_39 0x01ffff8000000000 -#define BM_39_56 BM_56_39 -#define BM_57_39 0x03ffff8000000000 -#define BM_39_57 BM_57_39 -#define BM_58_39 0x07ffff8000000000 -#define BM_39_58 BM_58_39 -#define BM_59_39 0x0fffff8000000000 -#define BM_39_59 BM_59_39 -#define BM_60_39 0x1fffff8000000000 -#define BM_39_60 BM_60_39 -#define BM_61_39 0x3fffff8000000000 -#define BM_39_61 BM_61_39 -#define BM_62_39 0x7fffff8000000000 -#define BM_39_62 BM_62_39 -#define BM_63_39 0xffffff8000000000 -#define BM_39_63 BM_63_39 -#define BM_40_40 0x0000010000000000 -#define BM_41_40 0x0000030000000000 -#define BM_40_41 BM_41_40 -#define BM_42_40 0x0000070000000000 -#define BM_40_42 BM_42_40 -#define BM_43_40 0x00000f0000000000 -#define BM_40_43 BM_43_40 -#define BM_44_40 0x00001f0000000000 -#define BM_40_44 BM_44_40 -#define BM_45_40 0x00003f0000000000 -#define BM_40_45 BM_45_40 -#define BM_46_40 0x00007f0000000000 -#define BM_40_46 BM_46_40 -#define BM_47_40 0x0000ff0000000000 -#define BM_40_47 BM_47_40 -#define BM_48_40 0x0001ff0000000000 -#define BM_40_48 BM_48_40 -#define BM_49_40 0x0003ff0000000000 -#define BM_40_49 BM_49_40 -#define BM_50_40 0x0007ff0000000000 -#define BM_40_50 BM_50_40 -#define BM_51_40 0x000fff0000000000 -#define BM_40_51 BM_51_40 -#define BM_52_40 0x001fff0000000000 -#define BM_40_52 BM_52_40 -#define BM_53_40 0x003fff0000000000 -#define BM_40_53 BM_53_40 -#define BM_54_40 0x007fff0000000000 -#define BM_40_54 BM_54_40 -#define BM_55_40 0x00ffff0000000000 -#define BM_40_55 BM_55_40 -#define BM_56_40 0x01ffff0000000000 -#define BM_40_56 BM_56_40 -#define BM_57_40 0x03ffff0000000000 -#define BM_40_57 BM_57_40 -#define BM_58_40 0x07ffff0000000000 -#define BM_40_58 BM_58_40 -#define BM_59_40 0x0fffff0000000000 -#define BM_40_59 BM_59_40 -#define BM_60_40 0x1fffff0000000000 -#define BM_40_60 BM_60_40 -#define BM_61_40 0x3fffff0000000000 -#define BM_40_61 BM_61_40 -#define BM_62_40 0x7fffff0000000000 -#define BM_40_62 BM_62_40 -#define BM_63_40 0xffffff0000000000 -#define BM_40_63 BM_63_40 -#define BM_41_41 0x0000020000000000 -#define BM_42_41 0x0000060000000000 -#define BM_41_42 BM_42_41 -#define BM_43_41 0x00000e0000000000 -#define BM_41_43 BM_43_41 -#define BM_44_41 0x00001e0000000000 -#define BM_41_44 BM_44_41 -#define BM_45_41 0x00003e0000000000 -#define BM_41_45 BM_45_41 -#define BM_46_41 0x00007e0000000000 -#define BM_41_46 BM_46_41 -#define BM_47_41 0x0000fe0000000000 -#define BM_41_47 BM_47_41 -#define BM_48_41 0x0001fe0000000000 -#define BM_41_48 BM_48_41 -#define BM_49_41 0x0003fe0000000000 -#define BM_41_49 BM_49_41 -#define BM_50_41 0x0007fe0000000000 -#define BM_41_50 BM_50_41 -#define BM_51_41 0x000ffe0000000000 -#define BM_41_51 BM_51_41 -#define BM_52_41 0x001ffe0000000000 -#define BM_41_52 BM_52_41 -#define BM_53_41 0x003ffe0000000000 -#define BM_41_53 BM_53_41 -#define BM_54_41 0x007ffe0000000000 -#define BM_41_54 BM_54_41 -#define BM_55_41 0x00fffe0000000000 -#define BM_41_55 BM_55_41 -#define BM_56_41 0x01fffe0000000000 -#define BM_41_56 BM_56_41 -#define BM_57_41 0x03fffe0000000000 -#define BM_41_57 BM_57_41 -#define BM_58_41 0x07fffe0000000000 -#define BM_41_58 BM_58_41 -#define BM_59_41 0x0ffffe0000000000 -#define BM_41_59 BM_59_41 -#define BM_60_41 0x1ffffe0000000000 -#define BM_41_60 BM_60_41 -#define BM_61_41 0x3ffffe0000000000 -#define BM_41_61 BM_61_41 -#define BM_62_41 0x7ffffe0000000000 -#define BM_41_62 BM_62_41 -#define BM_63_41 0xfffffe0000000000 -#define BM_41_63 BM_63_41 -#define BM_42_42 0x0000040000000000 -#define BM_43_42 0x00000c0000000000 -#define BM_42_43 BM_43_42 -#define BM_44_42 0x00001c0000000000 -#define BM_42_44 BM_44_42 -#define BM_45_42 0x00003c0000000000 -#define BM_42_45 BM_45_42 -#define BM_46_42 0x00007c0000000000 -#define BM_42_46 BM_46_42 -#define BM_47_42 0x0000fc0000000000 -#define BM_42_47 BM_47_42 -#define BM_48_42 0x0001fc0000000000 -#define BM_42_48 BM_48_42 -#define BM_49_42 0x0003fc0000000000 -#define BM_42_49 BM_49_42 -#define BM_50_42 0x0007fc0000000000 -#define BM_42_50 BM_50_42 -#define BM_51_42 0x000ffc0000000000 -#define BM_42_51 BM_51_42 -#define BM_52_42 0x001ffc0000000000 -#define BM_42_52 BM_52_42 -#define BM_53_42 0x003ffc0000000000 -#define BM_42_53 BM_53_42 -#define BM_54_42 0x007ffc0000000000 -#define BM_42_54 BM_54_42 -#define BM_55_42 0x00fffc0000000000 -#define BM_42_55 BM_55_42 -#define BM_56_42 0x01fffc0000000000 -#define BM_42_56 BM_56_42 -#define BM_57_42 0x03fffc0000000000 -#define BM_42_57 BM_57_42 -#define BM_58_42 0x07fffc0000000000 -#define BM_42_58 BM_58_42 -#define BM_59_42 0x0ffffc0000000000 -#define BM_42_59 BM_59_42 -#define BM_60_42 0x1ffffc0000000000 -#define BM_42_60 BM_60_42 -#define BM_61_42 0x3ffffc0000000000 -#define BM_42_61 BM_61_42 -#define BM_62_42 0x7ffffc0000000000 -#define BM_42_62 BM_62_42 -#define BM_63_42 0xfffffc0000000000 -#define BM_42_63 BM_63_42 -#define BM_43_43 0x0000080000000000 -#define BM_44_43 0x0000180000000000 -#define BM_43_44 BM_44_43 -#define BM_45_43 0x0000380000000000 -#define BM_43_45 BM_45_43 -#define BM_46_43 0x0000780000000000 -#define BM_43_46 BM_46_43 -#define BM_47_43 0x0000f80000000000 -#define BM_43_47 BM_47_43 -#define BM_48_43 0x0001f80000000000 -#define BM_43_48 BM_48_43 -#define BM_49_43 0x0003f80000000000 -#define BM_43_49 BM_49_43 -#define BM_50_43 0x0007f80000000000 -#define BM_43_50 BM_50_43 -#define BM_51_43 0x000ff80000000000 -#define BM_43_51 BM_51_43 -#define BM_52_43 0x001ff80000000000 -#define BM_43_52 BM_52_43 -#define BM_53_43 0x003ff80000000000 -#define BM_43_53 BM_53_43 -#define BM_54_43 0x007ff80000000000 -#define BM_43_54 BM_54_43 -#define BM_55_43 0x00fff80000000000 -#define BM_43_55 BM_55_43 -#define BM_56_43 0x01fff80000000000 -#define BM_43_56 BM_56_43 -#define BM_57_43 0x03fff80000000000 -#define BM_43_57 BM_57_43 -#define BM_58_43 0x07fff80000000000 -#define BM_43_58 BM_58_43 -#define BM_59_43 0x0ffff80000000000 -#define BM_43_59 BM_59_43 -#define BM_60_43 0x1ffff80000000000 -#define BM_43_60 BM_60_43 -#define BM_61_43 0x3ffff80000000000 -#define BM_43_61 BM_61_43 -#define BM_62_43 0x7ffff80000000000 -#define BM_43_62 BM_62_43 -#define BM_63_43 0xfffff80000000000 -#define BM_43_63 BM_63_43 -#define BM_44_44 0x0000100000000000 -#define BM_45_44 0x0000300000000000 -#define BM_44_45 BM_45_44 -#define BM_46_44 0x0000700000000000 -#define BM_44_46 BM_46_44 -#define BM_47_44 0x0000f00000000000 -#define BM_44_47 BM_47_44 -#define BM_48_44 0x0001f00000000000 -#define BM_44_48 BM_48_44 -#define BM_49_44 0x0003f00000000000 -#define BM_44_49 BM_49_44 -#define BM_50_44 0x0007f00000000000 -#define BM_44_50 BM_50_44 -#define BM_51_44 0x000ff00000000000 -#define BM_44_51 BM_51_44 -#define BM_52_44 0x001ff00000000000 -#define BM_44_52 BM_52_44 -#define BM_53_44 0x003ff00000000000 -#define BM_44_53 BM_53_44 -#define BM_54_44 0x007ff00000000000 -#define BM_44_54 BM_54_44 -#define BM_55_44 0x00fff00000000000 -#define BM_44_55 BM_55_44 -#define BM_56_44 0x01fff00000000000 -#define BM_44_56 BM_56_44 -#define BM_57_44 0x03fff00000000000 -#define BM_44_57 BM_57_44 -#define BM_58_44 0x07fff00000000000 -#define BM_44_58 BM_58_44 -#define BM_59_44 0x0ffff00000000000 -#define BM_44_59 BM_59_44 -#define BM_60_44 0x1ffff00000000000 -#define BM_44_60 BM_60_44 -#define BM_61_44 0x3ffff00000000000 -#define BM_44_61 BM_61_44 -#define BM_62_44 0x7ffff00000000000 -#define BM_44_62 BM_62_44 -#define BM_63_44 0xfffff00000000000 -#define BM_44_63 BM_63_44 -#define BM_45_45 0x0000200000000000 -#define BM_46_45 0x0000600000000000 -#define BM_45_46 BM_46_45 -#define BM_47_45 0x0000e00000000000 -#define BM_45_47 BM_47_45 -#define BM_48_45 0x0001e00000000000 -#define BM_45_48 BM_48_45 -#define BM_49_45 0x0003e00000000000 -#define BM_45_49 BM_49_45 -#define BM_50_45 0x0007e00000000000 -#define BM_45_50 BM_50_45 -#define BM_51_45 0x000fe00000000000 -#define BM_45_51 BM_51_45 -#define BM_52_45 0x001fe00000000000 -#define BM_45_52 BM_52_45 -#define BM_53_45 0x003fe00000000000 -#define BM_45_53 BM_53_45 -#define BM_54_45 0x007fe00000000000 -#define BM_45_54 BM_54_45 -#define BM_55_45 0x00ffe00000000000 -#define BM_45_55 BM_55_45 -#define BM_56_45 0x01ffe00000000000 -#define BM_45_56 BM_56_45 -#define BM_57_45 0x03ffe00000000000 -#define BM_45_57 BM_57_45 -#define BM_58_45 0x07ffe00000000000 -#define BM_45_58 BM_58_45 -#define BM_59_45 0x0fffe00000000000 -#define BM_45_59 BM_59_45 -#define BM_60_45 0x1fffe00000000000 -#define BM_45_60 BM_60_45 -#define BM_61_45 0x3fffe00000000000 -#define BM_45_61 BM_61_45 -#define BM_62_45 0x7fffe00000000000 -#define BM_45_62 BM_62_45 -#define BM_63_45 0xffffe00000000000 -#define BM_45_63 BM_63_45 -#define BM_46_46 0x0000400000000000 -#define BM_47_46 0x0000c00000000000 -#define BM_46_47 BM_47_46 -#define BM_48_46 0x0001c00000000000 -#define BM_46_48 BM_48_46 -#define BM_49_46 0x0003c00000000000 -#define BM_46_49 BM_49_46 -#define BM_50_46 0x0007c00000000000 -#define BM_46_50 BM_50_46 -#define BM_51_46 0x000fc00000000000 -#define BM_46_51 BM_51_46 -#define BM_52_46 0x001fc00000000000 -#define BM_46_52 BM_52_46 -#define BM_53_46 0x003fc00000000000 -#define BM_46_53 BM_53_46 -#define BM_54_46 0x007fc00000000000 -#define BM_46_54 BM_54_46 -#define BM_55_46 0x00ffc00000000000 -#define BM_46_55 BM_55_46 -#define BM_56_46 0x01ffc00000000000 -#define BM_46_56 BM_56_46 -#define BM_57_46 0x03ffc00000000000 -#define BM_46_57 BM_57_46 -#define BM_58_46 0x07ffc00000000000 -#define BM_46_58 BM_58_46 -#define BM_59_46 0x0fffc00000000000 -#define BM_46_59 BM_59_46 -#define BM_60_46 0x1fffc00000000000 -#define BM_46_60 BM_60_46 -#define BM_61_46 0x3fffc00000000000 -#define BM_46_61 BM_61_46 -#define BM_62_46 0x7fffc00000000000 -#define BM_46_62 BM_62_46 -#define BM_63_46 0xffffc00000000000 -#define BM_46_63 BM_63_46 -#define BM_47_47 0x0000800000000000 -#define BM_48_47 0x0001800000000000 -#define BM_47_48 BM_48_47 -#define BM_49_47 0x0003800000000000 -#define BM_47_49 BM_49_47 -#define BM_50_47 0x0007800000000000 -#define BM_47_50 BM_50_47 -#define BM_51_47 0x000f800000000000 -#define BM_47_51 BM_51_47 -#define BM_52_47 0x001f800000000000 -#define BM_47_52 BM_52_47 -#define BM_53_47 0x003f800000000000 -#define BM_47_53 BM_53_47 -#define BM_54_47 0x007f800000000000 -#define BM_47_54 BM_54_47 -#define BM_55_47 0x00ff800000000000 -#define BM_47_55 BM_55_47 -#define BM_56_47 0x01ff800000000000 -#define BM_47_56 BM_56_47 -#define BM_57_47 0x03ff800000000000 -#define BM_47_57 BM_57_47 -#define BM_58_47 0x07ff800000000000 -#define BM_47_58 BM_58_47 -#define BM_59_47 0x0fff800000000000 -#define BM_47_59 BM_59_47 -#define BM_60_47 0x1fff800000000000 -#define BM_47_60 BM_60_47 -#define BM_61_47 0x3fff800000000000 -#define BM_47_61 BM_61_47 -#define BM_62_47 0x7fff800000000000 -#define BM_47_62 BM_62_47 -#define BM_63_47 0xffff800000000000 -#define BM_47_63 BM_63_47 -#define BM_48_48 0x0001000000000000 -#define BM_49_48 0x0003000000000000 -#define BM_48_49 BM_49_48 -#define BM_50_48 0x0007000000000000 -#define BM_48_50 BM_50_48 -#define BM_51_48 0x000f000000000000 -#define BM_48_51 BM_51_48 -#define BM_52_48 0x001f000000000000 -#define BM_48_52 BM_52_48 -#define BM_53_48 0x003f000000000000 -#define BM_48_53 BM_53_48 -#define BM_54_48 0x007f000000000000 -#define BM_48_54 BM_54_48 -#define BM_55_48 0x00ff000000000000 -#define BM_48_55 BM_55_48 -#define BM_56_48 0x01ff000000000000 -#define BM_48_56 BM_56_48 -#define BM_57_48 0x03ff000000000000 -#define BM_48_57 BM_57_48 -#define BM_58_48 0x07ff000000000000 -#define BM_48_58 BM_58_48 -#define BM_59_48 0x0fff000000000000 -#define BM_48_59 BM_59_48 -#define BM_60_48 0x1fff000000000000 -#define BM_48_60 BM_60_48 -#define BM_61_48 0x3fff000000000000 -#define BM_48_61 BM_61_48 -#define BM_62_48 0x7fff000000000000 -#define BM_48_62 BM_62_48 -#define BM_63_48 0xffff000000000000 -#define BM_48_63 BM_63_48 -#define BM_49_49 0x0002000000000000 -#define BM_50_49 0x0006000000000000 -#define BM_49_50 BM_50_49 -#define BM_51_49 0x000e000000000000 -#define BM_49_51 BM_51_49 -#define BM_52_49 0x001e000000000000 -#define BM_49_52 BM_52_49 -#define BM_53_49 0x003e000000000000 -#define BM_49_53 BM_53_49 -#define BM_54_49 0x007e000000000000 -#define BM_49_54 BM_54_49 -#define BM_55_49 0x00fe000000000000 -#define BM_49_55 BM_55_49 -#define BM_56_49 0x01fe000000000000 -#define BM_49_56 BM_56_49 -#define BM_57_49 0x03fe000000000000 -#define BM_49_57 BM_57_49 -#define BM_58_49 0x07fe000000000000 -#define BM_49_58 BM_58_49 -#define BM_59_49 0x0ffe000000000000 -#define BM_49_59 BM_59_49 -#define BM_60_49 0x1ffe000000000000 -#define BM_49_60 BM_60_49 -#define BM_61_49 0x3ffe000000000000 -#define BM_49_61 BM_61_49 -#define BM_62_49 0x7ffe000000000000 -#define BM_49_62 BM_62_49 -#define BM_63_49 0xfffe000000000000 -#define BM_49_63 BM_63_49 -#define BM_50_50 0x0004000000000000 -#define BM_51_50 0x000c000000000000 -#define BM_50_51 BM_51_50 -#define BM_52_50 0x001c000000000000 -#define BM_50_52 BM_52_50 -#define BM_53_50 0x003c000000000000 -#define BM_50_53 BM_53_50 -#define BM_54_50 0x007c000000000000 -#define BM_50_54 BM_54_50 -#define BM_55_50 0x00fc000000000000 -#define BM_50_55 BM_55_50 -#define BM_56_50 0x01fc000000000000 -#define BM_50_56 BM_56_50 -#define BM_57_50 0x03fc000000000000 -#define BM_50_57 BM_57_50 -#define BM_58_50 0x07fc000000000000 -#define BM_50_58 BM_58_50 -#define BM_59_50 0x0ffc000000000000 -#define BM_50_59 BM_59_50 -#define BM_60_50 0x1ffc000000000000 -#define BM_50_60 BM_60_50 -#define BM_61_50 0x3ffc000000000000 -#define BM_50_61 BM_61_50 -#define BM_62_50 0x7ffc000000000000 -#define BM_50_62 BM_62_50 -#define BM_63_50 0xfffc000000000000 -#define BM_50_63 BM_63_50 -#define BM_51_51 0x0008000000000000 -#define BM_52_51 0x0018000000000000 -#define BM_51_52 BM_52_51 -#define BM_53_51 0x0038000000000000 -#define BM_51_53 BM_53_51 -#define BM_54_51 0x0078000000000000 -#define BM_51_54 BM_54_51 -#define BM_55_51 0x00f8000000000000 -#define BM_51_55 BM_55_51 -#define BM_56_51 0x01f8000000000000 -#define BM_51_56 BM_56_51 -#define BM_57_51 0x03f8000000000000 -#define BM_51_57 BM_57_51 -#define BM_58_51 0x07f8000000000000 -#define BM_51_58 BM_58_51 -#define BM_59_51 0x0ff8000000000000 -#define BM_51_59 BM_59_51 -#define BM_60_51 0x1ff8000000000000 -#define BM_51_60 BM_60_51 -#define BM_61_51 0x3ff8000000000000 -#define BM_51_61 BM_61_51 -#define BM_62_51 0x7ff8000000000000 -#define BM_51_62 BM_62_51 -#define BM_63_51 0xfff8000000000000 -#define BM_51_63 BM_63_51 -#define BM_52_52 0x0010000000000000 -#define BM_53_52 0x0030000000000000 -#define BM_52_53 BM_53_52 -#define BM_54_52 0x0070000000000000 -#define BM_52_54 BM_54_52 -#define BM_55_52 0x00f0000000000000 -#define BM_52_55 BM_55_52 -#define BM_56_52 0x01f0000000000000 -#define BM_52_56 BM_56_52 -#define BM_57_52 0x03f0000000000000 -#define BM_52_57 BM_57_52 -#define BM_58_52 0x07f0000000000000 -#define BM_52_58 BM_58_52 -#define BM_59_52 0x0ff0000000000000 -#define BM_52_59 BM_59_52 -#define BM_60_52 0x1ff0000000000000 -#define BM_52_60 BM_60_52 -#define BM_61_52 0x3ff0000000000000 -#define BM_52_61 BM_61_52 -#define BM_62_52 0x7ff0000000000000 -#define BM_52_62 BM_62_52 -#define BM_63_52 0xfff0000000000000 -#define BM_52_63 BM_63_52 -#define BM_53_53 0x0020000000000000 -#define BM_54_53 0x0060000000000000 -#define BM_53_54 BM_54_53 -#define BM_55_53 0x00e0000000000000 -#define BM_53_55 BM_55_53 -#define BM_56_53 0x01e0000000000000 -#define BM_53_56 BM_56_53 -#define BM_57_53 0x03e0000000000000 -#define BM_53_57 BM_57_53 -#define BM_58_53 0x07e0000000000000 -#define BM_53_58 BM_58_53 -#define BM_59_53 0x0fe0000000000000 -#define BM_53_59 BM_59_53 -#define BM_60_53 0x1fe0000000000000 -#define BM_53_60 BM_60_53 -#define BM_61_53 0x3fe0000000000000 -#define BM_53_61 BM_61_53 -#define BM_62_53 0x7fe0000000000000 -#define BM_53_62 BM_62_53 -#define BM_63_53 0xffe0000000000000 -#define BM_53_63 BM_63_53 -#define BM_54_54 0x0040000000000000 -#define BM_55_54 0x00c0000000000000 -#define BM_54_55 BM_55_54 -#define BM_56_54 0x01c0000000000000 -#define BM_54_56 BM_56_54 -#define BM_57_54 0x03c0000000000000 -#define BM_54_57 BM_57_54 -#define BM_58_54 0x07c0000000000000 -#define BM_54_58 BM_58_54 -#define BM_59_54 0x0fc0000000000000 -#define BM_54_59 BM_59_54 -#define BM_60_54 0x1fc0000000000000 -#define BM_54_60 BM_60_54 -#define BM_61_54 0x3fc0000000000000 -#define BM_54_61 BM_61_54 -#define BM_62_54 0x7fc0000000000000 -#define BM_54_62 BM_62_54 -#define BM_63_54 0xffc0000000000000 -#define BM_54_63 BM_63_54 -#define BM_55_55 0x0080000000000000 -#define BM_56_55 0x0180000000000000 -#define BM_55_56 BM_56_55 -#define BM_57_55 0x0380000000000000 -#define BM_55_57 BM_57_55 -#define BM_58_55 0x0780000000000000 -#define BM_55_58 BM_58_55 -#define BM_59_55 0x0f80000000000000 -#define BM_55_59 BM_59_55 -#define BM_60_55 0x1f80000000000000 -#define BM_55_60 BM_60_55 -#define BM_61_55 0x3f80000000000000 -#define BM_55_61 BM_61_55 -#define BM_62_55 0x7f80000000000000 -#define BM_55_62 BM_62_55 -#define BM_63_55 0xff80000000000000 -#define BM_55_63 BM_63_55 -#define BM_56_56 0x0100000000000000 -#define BM_57_56 0x0300000000000000 -#define BM_56_57 BM_57_56 -#define BM_58_56 0x0700000000000000 -#define BM_56_58 BM_58_56 -#define BM_59_56 0x0f00000000000000 -#define BM_56_59 BM_59_56 -#define BM_60_56 0x1f00000000000000 -#define BM_56_60 BM_60_56 -#define BM_61_56 0x3f00000000000000 -#define BM_56_61 BM_61_56 -#define BM_62_56 0x7f00000000000000 -#define BM_56_62 BM_62_56 -#define BM_63_56 0xff00000000000000 -#define BM_56_63 BM_63_56 -#define BM_57_57 0x0200000000000000 -#define BM_58_57 0x0600000000000000 -#define BM_57_58 BM_58_57 -#define BM_59_57 0x0e00000000000000 -#define BM_57_59 BM_59_57 -#define BM_60_57 0x1e00000000000000 -#define BM_57_60 BM_60_57 -#define BM_61_57 0x3e00000000000000 -#define BM_57_61 BM_61_57 -#define BM_62_57 0x7e00000000000000 -#define BM_57_62 BM_62_57 -#define BM_63_57 0xfe00000000000000 -#define BM_57_63 BM_63_57 -#define BM_58_58 0x0400000000000000 -#define BM_59_58 0x0c00000000000000 -#define BM_58_59 BM_59_58 -#define BM_60_58 0x1c00000000000000 -#define BM_58_60 BM_60_58 -#define BM_61_58 0x3c00000000000000 -#define BM_58_61 BM_61_58 -#define BM_62_58 0x7c00000000000000 -#define BM_58_62 BM_62_58 -#define BM_63_58 0xfc00000000000000 -#define BM_58_63 BM_63_58 -#define BM_59_59 0x0800000000000000 -#define BM_60_59 0x1800000000000000 -#define BM_59_60 BM_60_59 -#define BM_61_59 0x3800000000000000 -#define BM_59_61 BM_61_59 -#define BM_62_59 0x7800000000000000 -#define BM_59_62 BM_62_59 -#define BM_63_59 0xf800000000000000 -#define BM_59_63 BM_63_59 -#define BM_60_60 0x1000000000000000 -#define BM_61_60 0x3000000000000000 -#define BM_60_61 BM_61_60 -#define BM_62_60 0x7000000000000000 -#define BM_60_62 BM_62_60 -#define BM_63_60 0xf000000000000000 -#define BM_60_63 BM_63_60 -#define BM_61_61 0x2000000000000000 -#define BM_62_61 0x6000000000000000 -#define BM_61_62 BM_62_61 -#define BM_63_61 0xe000000000000000 -#define BM_61_63 BM_63_61 -#define BM_62_62 0x4000000000000000 -#define BM_63_62 0xc000000000000000 -#define BM_62_63 BM_63_62 -#define BM_63_63 0x8000000000000000 - -#endif - -#endif /* __ASM_TX4927_TX4927_MIPS_H */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 66c064690f41..f98b2bb719d5 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -48,7 +48,7 @@ #define TX4927_PCI_CLK_ACK 0x04 #define TX4927_PCI_CLK_ACE 0x02 #define TX4927_PCI_CLK_ENDIAN 0x01 -#define TX4927_NR_IRQ_LOCAL (8+16) +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG #define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ #define TX4927_IR_PCIC 16 @@ -99,21 +99,6 @@ struct tx4927_ccfg_reg { volatile unsigned long long ramp; }; -struct tx4927_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; - struct tx4927_pcic_reg { volatile unsigned long pciid; volatile unsigned long pcistatus; @@ -182,11 +167,6 @@ struct tx4927_pcic_reg { #endif /* _LANGUAGE_ASSEMBLY */ -/* IRCSR : Int. Current Status */ -#define TX4927_IRCSR_IF 0x00010000 -#define TX4927_IRCSR_ILV_MASK 0x00000700 -#define TX4927_IRCSR_IVL_MASK 0x0000001f - /* * PCIC */ @@ -278,7 +258,6 @@ struct tx4927_pcic_reg { #define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) #define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) -#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG) #endif /* _LANGUAGE_ASSEMBLY */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 74e7d8061e58..b180488dcdc4 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -14,6 +14,7 @@ #include <asm/addrspace.h> #include <asm/tx4938/tx4938.h> +#include <asm/txx9irq.h> /* CS */ #define RBTX4938_CE0 0x1c000000 /* 64M */ @@ -123,21 +124,11 @@ #define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ #define RBTX4938_NR_IRQ_IOC 8 -#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ -#define MI8259_IRQ_ISA_RAW_END 15 -#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */ -#define TX4938_IRQ_CP0_RAW_END 7 -#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */ -#define TX4938_IRQ_PIC_RAW_END 31 +#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) -#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ -#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ - -#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */ -#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */ - -#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */ -#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */ +#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) #define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) #define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) #define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) @@ -162,7 +153,7 @@ #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) #define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) #define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) #define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) @@ -192,10 +183,4 @@ #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) -/* IRCR : Int. Control */ -#define TX4938_IRCR_LOW 0x00000000 -#define TX4938_IRCR_HIGH 0x00000001 -#define TX4938_IRCR_DOWN 0x00000002 -#define TX4938_IRCR_UP 0x00000003 - #endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index e25b1a0975cb..650b010761f9 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -16,7 +16,7 @@ #include <asm/tx4938/tx4938_mips.h> #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) #define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG @@ -84,27 +84,27 @@ #include <asm/byteorder.h> #ifdef __BIG_ENDIAN -#define endian_def_l2(e1,e2) \ - volatile unsigned long e1,e2 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e1,e2 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned short e1;volatile unsigned char e2,e3 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned char e1,e2;volatile unsigned short e3 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e1,e2,e3,e4 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 #else -#define endian_def_l2(e1,e2) \ - volatile unsigned long e2,e1 -#define endian_def_s2(e1,e2) \ - volatile unsigned short e2,e1 -#define endian_def_sb2(e1,e2,e3) \ - volatile unsigned char e3,e2;volatile unsigned short e1 -#define endian_def_b2s(e1,e2,e3) \ - volatile unsigned short e3;volatile unsigned char e2,e1 -#define endian_def_b4(e1,e2,e3,e4) \ - volatile unsigned char e4,e3,e2,e1 +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 #endif @@ -272,20 +272,6 @@ struct tx4938_pio_reg { volatile unsigned long maskcpu; volatile unsigned long maskext; }; -struct tx4938_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; struct tx4938_ndfmc_reg { endian_def_l2(unused0, dtr); @@ -368,7 +354,7 @@ struct tx4938_ccfg_reg { #define TX4938_NUM_IR_SIO 2 #define TX4938_IR_SIO(n) (8 + (n)) #define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ #define TX4938_IR_PIO 14 #define TX4938_IR_PDMAC 15 #define TX4938_IR_PCIC 16 @@ -646,39 +632,12 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CSR_DESERR 0x00000002 #define TX4938_DMA_CSR_SORERR 0x00000001 -/* TX4938 Interrupt Controller (32-bit registers) */ -#define TX4938_IRC_BASE 0xf510 -#define TX4938_IRC_IRFLAG0 0xf510 -#define TX4938_IRC_IRFLAG1 0xf514 -#define TX4938_IRC_IRPOL 0xf518 -#define TX4938_IRC_IRRCNT 0xf51c -#define TX4938_IRC_IRMASKINT 0xf520 -#define TX4938_IRC_IRMASKEXT 0xf524 -#define TX4938_IRC_IRDEN 0xf600 -#define TX4938_IRC_IRDM0 0xf604 -#define TX4938_IRC_IRDM1 0xf608 -#define TX4938_IRC_IRLVL0 0xf610 -#define TX4938_IRC_IRLVL1 0xf614 -#define TX4938_IRC_IRLVL2 0xf618 -#define TX4938_IRC_IRLVL3 0xf61c -#define TX4938_IRC_IRLVL4 0xf620 -#define TX4938_IRC_IRLVL5 0xf624 -#define TX4938_IRC_IRLVL6 0xf628 -#define TX4938_IRC_IRLVL7 0xf62c -#define TX4938_IRC_IRMSK 0xf640 -#define TX4938_IRC_IREDC 0xf660 -#define TX4938_IRC_IRPND 0xf680 -#define TX4938_IRC_IRCS 0xf6a0 -#define TX4938_IRC_LIMIT 0xf6ff - - #ifndef __ASSEMBLY__ #define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) #define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) #define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) #define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG) #define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) #define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) #define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h index 5f8498fef005..f346ff58b947 100644 --- a/include/asm-mips/tx4938/tx4938_mips.h +++ b/include/asm-mips/tx4938/tx4938_mips.h @@ -19,10 +19,10 @@ #define reg_rd32(r) ((u32)(*((vu32*)(r)))) #define reg_rd64(r) ((u64)(*((vu64*)(r)))) -#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) -#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) -#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) -#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) +#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v))) +#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v))) +#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v))) +#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v))) typedef volatile __signed char vs8; typedef volatile unsigned char vu8; diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h new file mode 100644 index 000000000000..1c439e51b875 --- /dev/null +++ b/include/asm-mips/txx9irq.h @@ -0,0 +1,30 @@ +/* + * include/asm-mips/txx9irq.h + * TX39/TX49 interrupt controller definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9IRQ_H +#define __ASM_TXX9IRQ_H + +#include <irq.h> + +#ifdef CONFIG_IRQ_CPU +#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) +#else +#define TXX9_IRQ_BASE 0 +#endif + +#ifdef CONFIG_CPU_TX39XX +#define TXx9_MAX_IR 16 +#else +#define TXx9_MAX_IR 32 +#endif + +void txx9_irq_init(unsigned long baseaddr); +int txx9_irq(void); +int txx9_irq_set_pri(int irc_irq, int new_pri); + +#endif /* __ASM_TXX9IRQ_H */ diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index b25511787ee0..c30c718994c9 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -63,7 +63,7 @@ #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) -#define segment_eq(a,b) ((a).seg == (b).seg) +#define segment_eq(a, b) ((a).seg == (b).seg) /* @@ -108,7 +108,7 @@ (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) #define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size),__access_mask)) + likely(__access_ok((unsigned long)(addr), (size), __access_mask)) /* * put_user: - Write a simple value into user space. @@ -127,7 +127,7 @@ * Returns zero on success, or -EFAULT on error. */ #define put_user(x,ptr) \ - __put_user_check((x),(ptr),sizeof(*(ptr))) + __put_user_check((x), (ptr), sizeof(*(ptr))) /* * get_user: - Get a simple variable from user space. @@ -147,7 +147,7 @@ * On error, the variable @x is set to zero. */ #define get_user(x,ptr) \ - __get_user_check((x),(ptr),sizeof(*(ptr))) + __get_user_check((x), (ptr), sizeof(*(ptr))) /* * __put_user: - Write a simple value into user space, with less checking. @@ -169,7 +169,7 @@ * Returns zero on success, or -EFAULT on error. */ #define __put_user(x,ptr) \ - __put_user_nocheck((x),(ptr),sizeof(*(ptr))) + __put_user_nocheck((x), (ptr), sizeof(*(ptr))) /* * __get_user: - Get a simple variable from user space, with less checking. @@ -192,7 +192,7 @@ * On error, the variable @x is set to zero. */ #define __get_user(x,ptr) \ - __get_user_nocheck((x),(ptr),sizeof(*(ptr))) + __get_user_nocheck((x), (ptr), sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct __user *)(x)) @@ -221,7 +221,7 @@ do { \ } \ } while (0) -#define __get_user_nocheck(x,ptr,size) \ +#define __get_user_nocheck(x, ptr, size) \ ({ \ long __gu_err; \ \ @@ -229,7 +229,7 @@ do { \ __gu_err; \ }) -#define __get_user_check(x,ptr,size) \ +#define __get_user_check(x, ptr, size) \ ({ \ long __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ @@ -300,7 +300,7 @@ do { \ #define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) #endif -#define __put_user_nocheck(x,ptr,size) \ +#define __put_user_nocheck(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ long __pu_err = 0; \ @@ -316,7 +316,7 @@ do { \ __pu_err; \ }) -#define __put_user_check(x,ptr,size) \ +#define __put_user_check(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ __typeof__(*(ptr)) __pu_val = (x); \ @@ -389,11 +389,11 @@ extern void __put_user_unknown(void); extern size_t __copy_user(void *__to, const void *__from, size_t __n); -#define __invoke_copy_to_user(to,from,n) \ +#define __invoke_copy_to_user(to, from, n) \ ({ \ - register void __user *__cu_to_r __asm__ ("$4"); \ - register const void *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void __user *__cu_to_r __asm__("$4"); \ + register const void *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -421,7 +421,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define __copy_to_user(to,from,n) \ +#define __copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -437,7 +437,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); -#define __copy_to_user_inatomic(to,from,n) \ +#define __copy_to_user_inatomic(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -450,7 +450,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __copy_from_user_inatomic(to,from,n) \ +#define __copy_from_user_inatomic(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -477,7 +477,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * Returns number of bytes that could not be copied. * On success, this will be zero. */ -#define copy_to_user(to,from,n) \ +#define copy_to_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void *__cu_from; \ @@ -493,11 +493,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len; \ }) -#define __invoke_copy_from_user(to,from,n) \ +#define __invoke_copy_from_user(to, from, n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -516,11 +516,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) -#define __invoke_copy_from_user_inatomic(to,from,n) \ +#define __invoke_copy_from_user_inatomic(to, from, n) \ ({ \ - register void *__cu_to_r __asm__ ("$4"); \ - register const void __user *__cu_from_r __asm__ ("$5"); \ - register long __cu_len_r __asm__ ("$6"); \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ \ __cu_to_r = (to); \ __cu_from_r = (from); \ @@ -556,7 +556,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define __copy_from_user(to,from,n) \ +#define __copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -587,7 +587,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); * If some data could not be copied, this function will pad the copied * data to the requested size using zero bytes. */ -#define copy_from_user(to,from,n) \ +#define copy_from_user(to, from, n) \ ({ \ void *__cu_to; \ const void __user *__cu_from; \ @@ -605,7 +605,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); #define __copy_in_user(to, from, n) __copy_from_user(to, from, n) -#define copy_in_user(to,from,n) \ +#define copy_in_user(to, from, n) \ ({ \ void __user *__cu_to; \ const void __user *__cu_from; \ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h index a0042563838a..3249049e93aa 100644 --- a/include/asm-mips/unaligned.h +++ b/include/asm-mips/unaligned.h @@ -3,12 +3,27 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef _ASM_UNALIGNED_H -#define _ASM_UNALIGNED_H +#ifndef __ASM_GENERIC_UNALIGNED_H +#define __ASM_GENERIC_UNALIGNED_H -#include <asm-generic/unaligned.h> +#include <linux/compiler.h> -#endif /* _ASM_UNALIGNED_H */ +#define get_unaligned(ptr) \ +({ \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v; \ +}) + +#define put_unaligned(val, ptr) \ +do { \ + struct __packed { \ + typeof(*(ptr)) __v; \ + } *__p = (void *) (ptr); \ + __p->__v = (val); \ +} while(0) + +#endif /* __ASM_GENERIC_UNALIGNED_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index ed16de0a6398..fa9a587b3bf1 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -340,16 +340,17 @@ #define __NR_signalfd (__NR_Linux + 317) #define __NR_timerfd (__NR_Linux + 318) #define __NR_eventfd (__NR_Linux + 319) +#define __NR_fallocate (__NR_Linux + 320) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 319 +#define __NR_Linux_syscalls 320 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 319 +#define __NR_O32_Linux_syscalls 320 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -636,16 +637,17 @@ #define __NR_signalfd (__NR_Linux + 276) #define __NR_timerfd (__NR_Linux + 277) #define __NR_eventfd (__NR_Linux + 278) +#define __NR_fallocate (__NR_Linux + 279) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 278 +#define __NR_Linux_syscalls 279 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 278 +#define __NR_64_Linux_syscalls 279 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -936,16 +938,17 @@ #define __NR_signalfd (__NR_Linux + 280) #define __NR_timerfd (__NR_Linux + 281) #define __NR_eventfd (__NR_Linux + 282) +#define __NR_fallocate (__NR_Linux + 283) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 282 +#define __NR_Linux_syscalls 283 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 282 +#define __NR_N32_Linux_syscalls 283 #ifdef __KERNEL__ diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h index c1dd0b10bc27..f4cff7e4fa8a 100644 --- a/include/asm-mips/vga.h +++ b/include/asm-mips/vga.h @@ -13,10 +13,10 @@ * access the videoram directly without any black magic. */ -#define VGA_MAP_MEM(x,s) (0xb0000000L + (unsigned long)(x)) +#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) #define vga_readb(x) (*(x)) -#define vga_writeb(x,y) (*(y) = (x)) +#define vga_writeb(x, y) (*(y) = (x)) #define VT_BUF_HAVE_RW /* diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 9de52a5b0f3d..d2808edfd4e9 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -3,20 +3,22 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002, 2004 by Ralf Baechle + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle */ #ifndef _ASM_WAR_H #define _ASM_WAR_H +#include <war.h> /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. - * - * #define R4600_V1_INDEX_ICACHEOP_WAR 1 */ +#ifndef R4600_V1_INDEX_ICACHEOP_WAR +#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform +#endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: @@ -43,9 +45,10 @@ * nop * nop * cache Hit_Writeback_Invalidate_D - * - * #define R4600_V1_HIT_CACHEOP_WAR 1 */ +#ifndef R4600_V1_HIT_CACHEOP_WAR +#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform +#endif /* @@ -58,32 +61,11 @@ * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) - * - * #define R4600_V2_HIT_CACHEOP_WAR 1 - */ - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ -#ifdef CONFIG_SGI_IP22 - -#define R4600_V1_INDEX_ICACHEOP_WAR 1 -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -/* - * But the RM200C seems to have been shipped only with V2.0 R4600s */ -#ifdef CONFIG_SNI_RM - -#define R4600_V2_HIT_CACHEOP_WAR 1 - +#ifndef R4600_V2_HIT_CACHEOP_WAR +#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif -#ifdef CONFIG_CPU_R5432 - /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters @@ -93,13 +75,10 @@ * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ -#define R5432_CP0_INTERRUPT_WAR 1 - +#ifndef R5432_CP0_INTERRUPT_WAR +#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - /* * Workaround for the Sibyte M3 errata the text of which can be found at * @@ -110,13 +89,15 @@ * will just return and take the exception again if the information was * found to be inconsistent. */ -#define BCM1250_M3_WAR 1 +#ifndef BCM1250_M3_WAR +#error Check setting of BCM1250_M3_WAR for your platform +#endif /* * This is a DUART workaround related to glitches around register accesses */ -#define SIBYTE_1956_WAR 1 - +#ifndef SIBYTE_1956_WAR +#error Check setting of SIBYTE_1956_WAR for your platform #endif /* @@ -131,9 +112,8 @@ * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS4K_ICACHE_REFILL_WAR 1 +#ifndef MIPS4K_ICACHE_REFILL_WAR +#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* @@ -151,9 +131,8 @@ * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision <? */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS_CACHE_SYNC_WAR 1 +#ifndef MIPS_CACHE_SYNC_WAR +#error Check setting of MIPS_CACHE_SYNC_WAR for your platform #endif /* @@ -163,16 +142,16 @@ * * Workaround: do two phase flushing for Index_Invalidate_I */ -#ifdef CONFIG_CPU_TX49XX -#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#ifndef TX49XX_ICACHE_INDEX_INV_WAR +#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform #endif /* * On the RM9000 there is a problem which makes the CreateDirtyExclusive * eache operation unusable on SMP systems. */ -#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) -#define RM9000_CDEX_SMP_WAR 1 +#ifndef RM9000_CDEX_SMP_WAR +#error Check setting of RM9000_CDEX_SMP_WAR for your platform #endif /* @@ -181,71 +160,23 @@ * I-cache line worth of instructions being fetched may case spurious * exceptions. */ -#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \ - defined(CONFIG_WR_PPMC) -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform #endif - /* * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ -#ifdef CONFIG_SGI_IP27 -#define R10000_LLSC_WAR 1 +#ifndef R10000_LLSC_WAR +#error Check setting of R10000_LLSC_WAR for your platform #endif /* * 34K core erratum: "Problems Executing the TLBR Instruction" */ -#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ - defined(CONFIG_PMC_MSP7120_FPGA) -#define MIPS34K_MISSED_ITLB_WAR 1 -#endif - -/* - * Workarounds default to off - */ -#ifndef ICACHE_REFILLS_WORKAROUND_WAR -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#endif -#ifndef R4600_V1_INDEX_ICACHEOP_WAR -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#endif -#ifndef R4600_V1_HIT_CACHEOP_WAR -#define R4600_V1_HIT_CACHEOP_WAR 0 -#endif -#ifndef R4600_V2_HIT_CACHEOP_WAR -#define R4600_V2_HIT_CACHEOP_WAR 0 -#endif -#ifndef R5432_CP0_INTERRUPT_WAR -#define R5432_CP0_INTERRUPT_WAR 0 -#endif -#ifndef BCM1250_M3_WAR -#define BCM1250_M3_WAR 0 -#endif -#ifndef SIBYTE_1956_WAR -#define SIBYTE_1956_WAR 0 -#endif -#ifndef MIPS4K_ICACHE_REFILL_WAR -#define MIPS4K_ICACHE_REFILL_WAR 0 -#endif -#ifndef MIPS_CACHE_SYNC_WAR -#define MIPS_CACHE_SYNC_WAR 0 -#endif -#ifndef TX49XX_ICACHE_INDEX_INV_WAR -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#endif -#ifndef RM9000_CDEX_SMP_WAR -#define RM9000_CDEX_SMP_WAR 0 -#endif -#ifndef R10000_LLSC_WAR -#define R10000_LLSC_WAR 0 -#endif #ifndef MIPS34K_MISSED_ITLB_WAR -#define MIPS34K_MISSED_ITLB_WAR 0 +#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform #endif #endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h index 4a60f27c8817..79bac882a739 100644 --- a/include/asm-mips/xtalk/xtalk.h +++ b/include/asm-mips/xtalk/xtalk.h @@ -45,7 +45,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; #define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) #define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p,o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) +#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-parisc/a.out.h b/include/asm-parisc/a.out.h index 2a490cc9ec91..23e2c90943e5 100644 --- a/include/asm-parisc/a.out.h +++ b/include/asm-parisc/a.out.h @@ -23,6 +23,7 @@ struct exec * prumpf */ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX DEFAULT_TASK_SIZE #endif diff --git a/include/asm-parisc/bug.h b/include/asm-parisc/bug.h index 83ba510ed5d8..8cfc553fc837 100644 --- a/include/asm-parisc/bug.h +++ b/include/asm-parisc/bug.h @@ -74,7 +74,7 @@ #define WARN_ON(x) ({ \ - typeof(x) __ret_warn_on = (x); \ + int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ __WARN(); \ diff --git a/include/asm-parisc/io.h b/include/asm-parisc/io.h index c0fed91da3a2..4cc9bcec0564 100644 --- a/include/asm-parisc/io.h +++ b/include/asm-parisc/io.h @@ -15,6 +15,16 @@ extern unsigned long parisc_vmerge_max_size; #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt +static inline unsigned long isa_bus_to_virt(unsigned long addr) { + BUG(); + return 0; +} + +static inline unsigned long isa_virt_to_bus(void *addr) { + BUG(); + return 0; +} + /* * Memory mapped I/O * diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h index 21fbfc5afd02..ee80c920b464 100644 --- a/include/asm-parisc/system.h +++ b/include/asm-parisc/system.h @@ -48,17 +48,6 @@ extern struct task_struct *_switch_to(struct task_struct *, struct task_struct * (last) = _switch_to(prev, next); \ } while(0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - - /* interrupt control */ #define local_save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory") #define local_irq_disable() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) diff --git a/include/asm-parisc/thread_info.h b/include/asm-parisc/thread_info.h index 949314cf6188..2d9c7500867b 100644 --- a/include/asm-parisc/thread_info.h +++ b/include/asm-parisc/thread_info.h @@ -56,23 +56,21 @@ struct thread_info { * thread information flags */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_32BIT 5 /* 32 bit binary */ -#define TIF_MEMDIE 6 -#define TIF_RESTORE_SIGMASK 7 /* restore saved signal mask */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ +#define TIF_32BIT 4 /* 32 bit binary */ +#define TIF_MEMDIE 5 +#define TIF_RESTORE_SIGMASK 6 /* restore saved signal mask */ #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) #define _TIF_32BIT (1 << TIF_32BIT) #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) -#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \ +#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | \ _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK) #endif /* __KERNEL__ */ diff --git a/include/asm-parisc/vga.h b/include/asm-parisc/vga.h new file mode 100644 index 000000000000..154a84c843a7 --- /dev/null +++ b/include/asm-parisc/vga.h @@ -0,0 +1,6 @@ +#ifndef __ASM_PARISC_VGA_H__ +#define __ASM_PARISC_VGA_H__ + +/* nothing */ + +#endif __ASM_PARISC_VGA_H__ diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h new file mode 100644 index 000000000000..1311cefdfd30 --- /dev/null +++ b/include/asm-powerpc/8xx_immap.h @@ -0,0 +1,564 @@ +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifdef __KERNEL__ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + uint sc_swt; + char res1[2]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + char res2[0xc]; + uint sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + uint pcmc_pbr0; + uint pcmc_por0; + uint pcmc_pbr1; + uint pcmc_por1; + uint pcmc_pbr2; + uint pcmc_por2; + uint pcmc_pbr3; + uint pcmc_por3; + uint pcmc_pbr4; + uint pcmc_por4; + uint pcmc_pbr5; + uint pcmc_por5; + uint pcmc_pbr6; + uint pcmc_por6; + uint pcmc_pbr7; + uint pcmc_por7; + char res1[0x20]; + uint pcmc_pgcra; + uint pcmc_pgcrb; + uint pcmc_pscr; + char res2[4]; + uint pcmc_pipr; + char res3[4]; + uint pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + uint memc_br4; + uint memc_or4; + uint memc_br5; + uint memc_or5; + uint memc_br6; + uint memc_or6; + uint memc_br7; + uint memc_or7; + char res1[0x24]; + uint memc_mar; + uint memc_mcr; + char res2[4]; + uint memc_mamr; + uint memc_mbmr; + ushort memc_mstat; + ushort memc_mptpr; + uint memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/*----------------------------------------------------------------------- + * BR - Memory Controler: Base Register 16-9 + */ +#define BR_BA_MSK 0xffff8000 /* Base Address Mask */ +#define BR_AT_MSK 0x00007000 /* Address Type Mask */ +#define BR_PS_MSK 0x00000c00 /* Port Size Mask */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PARE 0x00000200 /* Parity Enable */ +#define BR_WP 0x00000100 /* Write Protect */ +#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ +#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ +#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ +#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ +#define BR_V 0x00000001 /* Bank Valid */ + +/*----------------------------------------------------------------------- + * OR - Memory Controler: Option Register 16-11 + */ +#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ +#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ +#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ + /* Address Multiplex */ +#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ +#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ +#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ +#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ +#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ +#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ +#define OR_BI 0x00000100 /* Burst inhibit */ +#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ +#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ +#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ +#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ +#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ +#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ +#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ +#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ +#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ +#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ +#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ +#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ +#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ +#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ +#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ +#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ +#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ +#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ +#define OR_TRLX 0x00000004 /* Timing Relaxed */ +#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + ushort sit_tbscr; + char res0[0x02]; + uint sit_tbreff0; + uint sit_tbreff1; + char res1[0x14]; + ushort sit_rtcsc; + char res2[0x02]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res3[0x10]; + ushort sit_piscr; + char res4[2]; + uint sit_pitc; + uint sit_pitr; + char res5[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((ushort)0xff00) +#define TBSCR_REFA ((ushort)0x0080) +#define TBSCR_REFB ((ushort)0x0040) +#define TBSCR_REFAE ((ushort)0x0008) +#define TBSCR_REFBE ((ushort)0x0004) +#define TBSCR_TBF ((ushort)0x0002) +#define TBSCR_TBE ((ushort)0x0001) + +#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) +#define RTCSC_SEC ((ushort)0x0080) +#define RTCSC_ALR ((ushort)0x0040) +#define RTCSC_38K ((ushort)0x0010) +#define RTCSC_SIE ((ushort)0x0008) +#define RTCSC_ALE ((ushort)0x0004) +#define RTCSC_RTF ((ushort)0x0002) +#define RTCSC_RTE ((ushort)0x0001) + +#define PISCR_PIRQ_MASK ((ushort)0xff00) +#define PISCR_PS ((ushort)0x0080) +#define PISCR_PIE ((ushort)0x0004) +#define PISCR_PTF ((ushort)0x0002) +#define PISCR_PTE ((ushort)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + uint car_sccr; + uint car_plprcr; + uint car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + uint sitk_tbscrk; + uint sitk_tbreff0k; + uint sitk_tbreff1k; + uint sitk_tbk; + char res1[0x10]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[0x10]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + uint cark_sccrk; + uint cark_plprcrk; + uint cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* Video interface. MPC823 Only. +*/ +typedef struct vid823 { + ushort vid_vccr; + ushort res1; + u_char vid_vsr; + u_char res2; + u_char vid_vcmr; + u_char res3; + uint vid_vbcb; + uint res4; + uint vid_vfcr0; + uint vid_vfaa0; + uint vid_vfba0; + uint vid_vfcr1; + uint vid_vfaa1; + uint vid_vfba1; + u_char res5[0x18]; +} vid823_t; + +/* LCD interface. 823 Only. +*/ +typedef struct lcd { + uint lcd_lccr; + uint lcd_lchcr; + uint lcd_lcvcr; + char res1[4]; + uint lcd_lcfaa; + uint lcd_lcfba; + char lcd_lcsr; + char res2[0x7]; +} lcd823_t; + +/* I2C +*/ +typedef struct i2c { + u_char i2c_i2mod; + char res1[3]; + u_char i2c_i2add; + char res2[3]; + u_char i2c_i2brg; + char res3[3]; + u_char i2c_i2com; + char res4[3]; + u_char i2c_i2cer; + char res5[3]; + u_char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + uint sdma_sdar; + u_char sdma_sdsr; + char res3[3]; + u_char sdma_sdmr; + char res4[3]; + u_char sdma_idsr1; + char res5[3]; + u_char sdma_idmr1; + char res6[3]; + u_char sdma_idsr2; + char res7[3]; + u_char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + ushort cpic_civr; + char res[0xe]; + uint cpic_cicr; + uint cpic_cipr; + uint cpic_cimr; + uint cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + ushort iop_padir; + ushort iop_papar; + ushort iop_paodr; + ushort iop_padat; + char res1[8]; + ushort iop_pcdir; + ushort iop_pcpar; + ushort iop_pcso; + ushort iop_pcdat; + ushort iop_pcint; + char res2[6]; + ushort iop_pddir; + ushort iop_pdpar; + char res3[2]; + ushort iop_pddat; + uint utmode; + char res4[4]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + ushort cpmt_tgcr; + char res1[0xe]; + ushort cpmt_tmr1; + ushort cpmt_tmr2; + ushort cpmt_trr1; + ushort cpmt_trr2; + ushort cpmt_tcr1; + ushort cpmt_tcr2; + ushort cpmt_tcn1; + ushort cpmt_tcn2; + ushort cpmt_tmr3; + ushort cpmt_tmr4; + ushort cpmt_trr3; + ushort cpmt_trr4; + ushort cpmt_tcr3; + ushort cpmt_tcr4; + ushort cpmt_tcn3; + ushort cpmt_tcn4; + ushort cpmt_ter1; + ushort cpmt_ter2; + ushort cpmt_ter3; + ushort cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + uint scc_gsmrl; + uint scc_gsmrh; + ushort scc_psmr; + char res1[2]; + ushort scc_todr; + ushort scc_dsr; + ushort scc_scce; + char res2[2]; + ushort scc_sccm; + char res3; + u_char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + ushort smc_smcmr; + char res2[2]; + u_char smc_smce; + char res3[3]; + u_char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ + +typedef struct fec { + uint fec_addr_low; /* lower 32 bits of station address */ + ushort fec_addr_high; /* upper 16 bits of station address */ + ushort res1; /* reserved */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res6[17]; /* reserved */ + uint fec_fun_code; /* fec SDMA function code */ + uint res7[3]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x1e]; /* reserved */ +} fec_t; + +/* The FEC and LCD color map share the same address space.... + * I guess we will never see an 823T :-). + */ +union fec_lcd { + fec_t fl_un_fec; + u_char fl_un_cmap[0x200]; +}; + +typedef struct comm_proc { + /* General control and status registers. + */ + ushort cp_cpcr; + u_char res1[2]; + ushort cp_rccr; + u_char res2; + u_char cp_rmds; + u_char res3[4]; + ushort cp_cpmcr1; + ushort cp_cpmcr2; + ushort cp_cpmcr3; + ushort cp_cpmcr4; + u_char res4[2]; + ushort cp_rter; + u_char res5[2]; + ushort cp_rtmr; + u_char res6[0x14]; + + /* Baud rate generators. + */ + uint cp_brgc1; + uint cp_brgc2; + uint cp_brgc3; + uint cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + ushort cp_spmode; + u_char res7[4]; + u_char cp_spie; + u_char res8[3]; + u_char cp_spim; + u_char res9[2]; + u_char cp_spcom; + u_char res10[2]; + + /* Parallel Interface Port. + */ + u_char res11[2]; + ushort cp_pipc; + u_char res12[2]; + ushort cp_ptpr; + uint cp_pbdir; + uint cp_pbpar; + u_char res13[2]; + ushort cp_pbodr; + uint cp_pbdat; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; + + /* Serial Interface and Time Slot Assignment. + */ + uint cp_simode; + u_char cp_sigmr; + u_char res15; + u_char cp_sistr; + u_char cp_sicmr; + u_char res16[4]; + uint cp_sicr; + uint cp_sirp; + u_char res17[0xc]; + + /* 256 bytes of MPC823 video controller RAM array. + */ + u_char cp_vcram[0x100]; + u_char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + * The LCD color map is also here. + */ + union fec_lcd fl_un; +#define cp_fec fl_un.fl_un_fec +#define lcd_cmap fl_un.fl_un_cmap + char res18[0xE00]; + + /* The DUET family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + * Some processors don't have all of it populated. + */ + u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ + u_char cp_dparam[0x400]; /* Parameter RAM */ +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + vid823_t im_vid; /* Video (823 only) */ + lcd823_t im_lcd; /* LCD (823 only) */ + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/a.out.h b/include/asm-powerpc/a.out.h index c7393a977364..5c5ea83f9349 100644 --- a/include/asm-powerpc/a.out.h +++ b/include/asm-powerpc/a.out.h @@ -26,9 +26,12 @@ struct exec #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ STACK_TOP_USER32 : STACK_TOP_USER64) +#define STACK_TOP_MAX STACK_TOP_USER64 + #else /* __powerpc64__ */ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif /* __powerpc64__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h index c44810b9d322..f3fc733758f5 100644 --- a/include/asm-powerpc/atomic.h +++ b/include/asm-powerpc/atomic.h @@ -5,7 +5,7 @@ * PowerPC atomic operations */ -typedef struct { volatile int counter; } atomic_t; +typedef struct { int counter; } atomic_t; #ifdef __KERNEL__ #include <linux/compiler.h> @@ -15,8 +15,19 @@ typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) +static __inline__ int atomic_read(const atomic_t *v) +{ + int t; + + __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); + + return t; +} + +static __inline__ void atomic_set(atomic_t *v, int i) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); +} static __inline__ void atomic_add(int a, atomic_t *v) { @@ -240,12 +251,23 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v) #ifdef __powerpc64__ -typedef struct { volatile long counter; } atomic64_t; +typedef struct { long counter; } atomic64_t; #define ATOMIC64_INIT(i) { (i) } -#define atomic64_read(v) ((v)->counter) -#define atomic64_set(v,i) (((v)->counter) = (i)) +static __inline__ long atomic64_read(const atomic64_t *v) +{ + long t; + + __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter)); + + return t; +} + +static __inline__ void atomic64_set(atomic64_t *v, long i) +{ + __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i)); +} static __inline__ void atomic64_add(long a, atomic64_t *v) { diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h index f6fa39474846..e55d1f66b86f 100644 --- a/include/asm-powerpc/bug.h +++ b/include/asm-powerpc/bug.h @@ -79,7 +79,7 @@ _EMIT_BUG_ENTRY \ : : "i" (__FILE__), "i" (__LINE__), "i" (0), \ "i" (sizeof(struct bug_entry)), \ - "r" ((long)(x))); \ + "r" ((__force long)(x))); \ } \ } while (0) @@ -93,7 +93,7 @@ } while (0) #define WARN_ON(x) ({ \ - typeof(x) __ret_warn_on = (x); \ + int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ __WARN(); \ diff --git a/include/asm-powerpc/cell-regs.h b/include/asm-powerpc/cell-regs.h new file mode 100644 index 000000000000..fd6fd00434ef --- /dev/null +++ b/include/asm-powerpc/cell-regs.h @@ -0,0 +1,315 @@ +/* + * cbe_regs.h + * + * This file is intended to hold the various register definitions for CBE + * on-chip system devices (memory controller, IO controller, etc...) + * + * (C) Copyright IBM Corporation 2001,2006 + * + * Authors: Maximino Aguilar (maguilar@us.ibm.com) + * David J. Erb (djerb@us.ibm.com) + * + * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. + */ + +#ifndef CBE_REGS_H +#define CBE_REGS_H + +#include <asm/cell-pmu.h> + +/* + * + * Some HID register definitions + * + */ + +/* CBE specific HID0 bits */ +#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul +#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul +#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul +#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul + +#define MAX_CBE 2 + +/* + * + * Pervasive unit register definitions + * + */ + +union spe_reg { + u64 val; + u8 spe[8]; +}; + +union ppe_spe_reg { + u64 val; + struct { + u32 ppe; + u32 spe; + }; +}; + + +struct cbe_pmd_regs { + /* Debug Bus Control */ + u64 pad_0x0000; /* 0x0000 */ + + u64 group_control; /* 0x0008 */ + + u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */ + + u64 debug_bus_control; /* 0x00a8 */ + + u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */ + + u64 trace_aux_data; /* 0x0100 */ + u64 trace_buffer_0_63; /* 0x0108 */ + u64 trace_buffer_64_127; /* 0x0110 */ + u64 trace_address; /* 0x0118 */ + u64 ext_tr_timer; /* 0x0120 */ + + u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */ + + /* Performance Monitor */ + u64 pm_status; /* 0x0400 */ + u64 pm_control; /* 0x0408 */ + u64 pm_interval; /* 0x0410 */ + u64 pm_ctr[4]; /* 0x0418 */ + u64 pm_start_stop; /* 0x0438 */ + u64 pm07_control[8]; /* 0x0440 */ + + u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */ + + /* Thermal Sensor Registers */ + union spe_reg ts_ctsr1; /* 0x0800 */ + u64 ts_ctsr2; /* 0x0808 */ + union spe_reg ts_mtsr1; /* 0x0810 */ + u64 ts_mtsr2; /* 0x0818 */ + union spe_reg ts_itr1; /* 0x0820 */ + u64 ts_itr2; /* 0x0828 */ + u64 ts_gitr; /* 0x0830 */ + u64 ts_isr; /* 0x0838 */ + u64 ts_imr; /* 0x0840 */ + union spe_reg tm_cr1; /* 0x0848 */ + u64 tm_cr2; /* 0x0850 */ + u64 tm_simr; /* 0x0858 */ + union ppe_spe_reg tm_tpr; /* 0x0860 */ + union spe_reg tm_str1; /* 0x0868 */ + u64 tm_str2; /* 0x0870 */ + union ppe_spe_reg tm_tsr; /* 0x0878 */ + + /* Power Management */ + u64 pmcr; /* 0x0880 */ +#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000 + u64 pmsr; /* 0x0888 */ + + /* Time Base Register */ + u64 tbr; /* 0x0890 */ + + u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */ + + /* Fault Isolation Registers */ + u64 checkstop_fir; /* 0x0c00 */ + u64 recoverable_fir; /* 0x0c08 */ + u64 spec_att_mchk_fir; /* 0x0c10 */ + u32 fir_mode_reg; /* 0x0c18 */ + u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */ +#define CBE_PMD_FIR_MODE_M8 0x00800 + u64 fir_enable_mask; /* 0x0c20 */ + + u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */ + u64 ras_esc_0; /* 0x0ca8 */ + u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */ +}; + +extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np); +extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu); + +/* + * PMU shadow registers + * + * Many of the registers in the performance monitoring unit are write-only, + * so we need to save a copy of what we write to those registers. + * + * The actual data counters are read/write. However, writing to the counters + * only takes effect if the PMU is enabled. Otherwise the value is stored in + * a hardware latch until the next time the PMU is enabled. So we save a copy + * of the counter values if we need to read them back while the PMU is + * disabled. The counter_value_in_latch field is a bitmap indicating which + * counters currently have a value waiting to be written. + */ + +struct cbe_pmd_shadow_regs { + u32 group_control; + u32 debug_bus_control; + u32 trace_address; + u32 ext_tr_timer; + u32 pm_status; + u32 pm_control; + u32 pm_interval; + u32 pm_start_stop; + u32 pm07_control[NR_CTRS]; + + u32 pm_ctr[NR_PHYS_CTRS]; + u32 counter_value_in_latch; +}; + +extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np); +extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu); + +/* + * + * IIC unit register definitions + * + */ + +struct cbe_iic_pending_bits { + u32 data; + u8 flags; + u8 class; + u8 source; + u8 prio; +}; + +#define CBE_IIC_IRQ_VALID 0x80 +#define CBE_IIC_IRQ_IPI 0x40 + +struct cbe_iic_thread_regs { + struct cbe_iic_pending_bits pending; + struct cbe_iic_pending_bits pending_destr; + u64 generate; + u64 prio; +}; + +struct cbe_iic_regs { + u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */ + + /* IIC interrupt registers */ + struct cbe_iic_thread_regs thread[2]; /* 0x0400 */ + + u64 iic_ir; /* 0x0440 */ +#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12) +#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4) +#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf) +#define CBE_IIC_IR_IOC_0 0x0 +#define CBE_IIC_IR_IOC_1S 0xb +#define CBE_IIC_IR_PT_0 0xe +#define CBE_IIC_IR_PT_1 0xf + + u64 iic_is; /* 0x0448 */ +#define CBE_IIC_IS_PMI 0x2 + + u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */ + + /* IOC FIR */ + u64 ioc_fir_reset; /* 0x0500 */ + u64 ioc_fir_set; /* 0x0508 */ + u64 ioc_checkstop_enable; /* 0x0510 */ + u64 ioc_fir_error_mask; /* 0x0518 */ + u64 ioc_syserr_enable; /* 0x0520 */ + u64 ioc_fir; /* 0x0528 */ + + u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */ +}; + +extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np); +extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu); + + +struct cbe_mic_tm_regs { + u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */ + + u64 mic_ctl_cnfg2; /* 0x0040 */ +#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL +#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL +#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL +#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL + + u64 pad_0x0048; /* 0x0048 */ + + u64 mic_aux_trc_base; /* 0x0050 */ + u64 mic_aux_trc_max_addr; /* 0x0058 */ + u64 mic_aux_trc_cur_addr; /* 0x0060 */ + u64 mic_aux_trc_grf_addr; /* 0x0068 */ + u64 mic_aux_trc_grf_data; /* 0x0070 */ + + u64 pad_0x0078; /* 0x0078 */ + + u64 mic_ctl_cnfg_0; /* 0x0080 */ +#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL + + u64 pad_0x0088; /* 0x0088 */ + + u64 slow_fast_timer_0; /* 0x0090 */ + u64 slow_next_timer_0; /* 0x0098 */ + + u8 pad_0x00a0_0x00f8[0x00f8 - 0x00a0]; /* 0x00a0 */ + u64 mic_df_ecc_address_0; /* 0x00f8 */ + + u8 pad_0x0100_0x01b8[0x01b8 - 0x0100]; /* 0x0100 */ + u64 mic_df_ecc_address_1; /* 0x01b8 */ + + u64 mic_ctl_cnfg_1; /* 0x01c0 */ +#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL + + u64 pad_0x01c8; /* 0x01c8 */ + + u64 slow_fast_timer_1; /* 0x01d0 */ + u64 slow_next_timer_1; /* 0x01d8 */ + + u8 pad_0x01e0_0x0208[0x0208 - 0x01e0]; /* 0x01e0 */ + u64 mic_exc; /* 0x0208 */ +#define CBE_MIC_EXC_BLOCK_SCRUB 0x0800000000000000ULL +#define CBE_MIC_EXC_FAST_SCRUB 0x0100000000000000ULL + + u64 mic_mnt_cfg; /* 0x0210 */ +#define CBE_MIC_MNT_CFG_CHAN_0_POP 0x0002000000000000ULL +#define CBE_MIC_MNT_CFG_CHAN_1_POP 0x0004000000000000ULL + + u64 mic_df_config; /* 0x0218 */ +#define CBE_MIC_ECC_DISABLE_0 0x4000000000000000ULL +#define CBE_MIC_ECC_REP_SINGLE_0 0x2000000000000000ULL +#define CBE_MIC_ECC_DISABLE_1 0x0080000000000000ULL +#define CBE_MIC_ECC_REP_SINGLE_1 0x0040000000000000ULL + + u8 pad_0x0220_0x0230[0x0230 - 0x0220]; /* 0x0220 */ + u64 mic_fir; /* 0x0230 */ +#define CBE_MIC_FIR_ECC_SINGLE_0_ERR 0x0200000000000000ULL +#define CBE_MIC_FIR_ECC_MULTI_0_ERR 0x0100000000000000ULL +#define CBE_MIC_FIR_ECC_SINGLE_1_ERR 0x0080000000000000ULL +#define CBE_MIC_FIR_ECC_MULTI_1_ERR 0x0040000000000000ULL +#define CBE_MIC_FIR_ECC_ERR_MASK 0xffff000000000000ULL +#define CBE_MIC_FIR_ECC_SINGLE_0_CTE 0x0000020000000000ULL +#define CBE_MIC_FIR_ECC_MULTI_0_CTE 0x0000010000000000ULL +#define CBE_MIC_FIR_ECC_SINGLE_1_CTE 0x0000008000000000ULL +#define CBE_MIC_FIR_ECC_MULTI_1_CTE 0x0000004000000000ULL +#define CBE_MIC_FIR_ECC_CTE_MASK 0x0000ffff00000000ULL +#define CBE_MIC_FIR_ECC_SINGLE_0_RESET 0x0000000002000000ULL +#define CBE_MIC_FIR_ECC_MULTI_0_RESET 0x0000000001000000ULL +#define CBE_MIC_FIR_ECC_SINGLE_1_RESET 0x0000000000800000ULL +#define CBE_MIC_FIR_ECC_MULTI_1_RESET 0x0000000000400000ULL +#define CBE_MIC_FIR_ECC_RESET_MASK 0x00000000ffff0000ULL +#define CBE_MIC_FIR_ECC_SINGLE_0_SET 0x0000000000000200ULL +#define CBE_MIC_FIR_ECC_MULTI_0_SET 0x0000000000000100ULL +#define CBE_MIC_FIR_ECC_SINGLE_1_SET 0x0000000000000080ULL +#define CBE_MIC_FIR_ECC_MULTI_1_SET 0x0000000000000040ULL +#define CBE_MIC_FIR_ECC_SET_MASK 0x000000000000ffffULL + u64 mic_fir_debug; /* 0x0238 */ + + u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */ +}; + +extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np); +extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu); + +/* some utility functions to deal with SMT */ +extern u32 cbe_get_hw_thread_id(int cpu); +extern u32 cbe_cpu_to_node(int cpu); +extern u32 cbe_node_to_cpu(int node); + +/* Init this module early */ +extern void cbe_regs_init(void); + + +#endif /* CBE_REGS_H */ diff --git a/include/asm-powerpc/clk_interface.h b/include/asm-powerpc/clk_interface.h new file mode 100644 index 000000000000..ab1882c1e176 --- /dev/null +++ b/include/asm-powerpc/clk_interface.h @@ -0,0 +1,20 @@ +#ifndef __ASM_POWERPC_CLK_INTERFACE_H +#define __ASM_POWERPC_CLK_INTERFACE_H + +#include <linux/clk.h> + +struct clk_interface { + struct clk* (*clk_get) (struct device *dev, const char *id); + int (*clk_enable) (struct clk *clk); + void (*clk_disable) (struct clk *clk); + unsigned long (*clk_get_rate) (struct clk *clk); + void (*clk_put) (struct clk *clk); + long (*clk_round_rate) (struct clk *clk, unsigned long rate); + int (*clk_set_rate) (struct clk *clk, unsigned long rate); + int (*clk_set_parent) (struct clk *clk, struct clk *parent); + struct clk* (*clk_get_parent) (struct clk *clk); +}; + +extern struct clk_interface clk_functions; + +#endif /* __ASM_POWERPC_CLK_INTERFACE_H */ diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/commproc.h new file mode 100644 index 000000000000..0307c84a5c1d --- /dev/null +++ b/include/asm-powerpc/commproc.h @@ -0,0 +1,755 @@ +/* + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * This file contains structures and information for the communication + * processor channels. Some CPM control and status is available + * throught the MPC8xx internal memory map. See immap.h for details. + * This file only contains what I need for the moment, not the total + * CPM capabilities. I (or someone else) will add definitions as they + * are needed. -- Dan + * + * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 + * bytes of the DP RAM and relocates the I2C parameter area to the + * IDMA1 space. The remaining DP RAM is available for buffer descriptors + * or other use. + */ +#ifndef __CPM_8XX__ +#define __CPM_8XX__ + +#include <asm/8xx_immap.h> +#include <asm/ptrace.h> +#include <asm/cpm.h> + +/* CPM Command register. +*/ +#define CPM_CR_RST ((ushort)0x8000) +#define CPM_CR_OPCODE ((ushort)0x0f00) +#define CPM_CR_CHAN ((ushort)0x00f0) +#define CPM_CR_FLG ((ushort)0x0001) + +/* Some commands (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) +#define CPM_CR_SET_GADDR ((ushort)0x0008) +#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR + +/* Channel numbers. +*/ +#define CPM_CR_CH_SCC1 ((ushort)0x0000) +#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ +#define CPM_CR_CH_SCC2 ((ushort)0x0004) +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ +#define CPM_CR_CH_TIMER CPM_CR_CH_SPI +#define CPM_CR_CH_SCC3 ((ushort)0x0008) +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ +#define CPM_CR_CH_SCC4 ((ushort)0x000c) +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ + +#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) + +#ifndef CONFIG_PPC_CPM_NEW_BINDING +/* The dual ported RAM is multi-functional. Some areas can be (and are + * being) used for microcode. There is an area that can only be used + * as data ram for buffer descriptors, which is all we use right now. + * Currently the first 512 and last 256 bytes are used for microcode. + */ +#define CPM_DATAONLY_BASE ((uint)0x0800) +#define CPM_DATAONLY_SIZE ((uint)0x0700) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) +#endif + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */ + +#ifdef CONFIG_PPC_CPM_NEW_BINDING +#define cpm_dpalloc cpm_muram_alloc +#define cpm_dpfree cpm_muram_free +#define cpm_dpram_addr cpm_muram_addr +#define cpm_dpram_phys cpm_muram_dma +#else +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); +extern void cpm_dpdump(void); +extern void *cpm_dpram_addr(unsigned long offset); +extern uint cpm_dpram_phys(u8* addr); +#endif + +extern void cpm_setbrg(uint brg, uint rate); + +extern uint m8xx_cpm_hostalloc(uint size); +extern int m8xx_cpm_hostfree(uint start); +extern void m8xx_cpm_hostdump(void); + +extern void cpm_load_patch(volatile immap_t *immr); + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_UN ((ushort)0x0002) /* Underrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ +#define BD_SC_CL ((ushort)0x0001) /* Collision */ + +/* Parameter RAM offsets. +*/ +#define PROFF_SCC1 ((uint)0x0000) +#define PROFF_IIC ((uint)0x0080) +#define PROFF_SCC2 ((uint)0x0100) +#define PROFF_SPI ((uint)0x0180) +#define PROFF_SCC3 ((uint)0x0200) +#define PROFF_SMC1 ((uint)0x0280) +#define PROFF_SCC4 ((uint)0x0300) +#define PROFF_SMC2 ((uint)0x0380) + +/* Define enough so I can at least use the serial port as a UART. + * The MBX uses SMC1 as the host serial port. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + char res1[8]; /* Reserved */ + ushort smc_rpbase; /* Relocation pointer */ +} smc_uart_t; + +/* Function code bits. +*/ +#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* SMC uart mode register. +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC2 as Centronics parallel printer. It is half duplex, in that + * it can only receive or transmit. The parameter ram values for + * each direction are either unique or properly overlap, so we can + * include them in one structure. + */ +typedef struct smc_centronics { + ushort scent_rbase; + ushort scent_tbase; + u_char scent_cfcr; + u_char scent_smask; + ushort scent_mrblr; + uint scent_rstate; + uint scent_r_ptr; + ushort scent_rbptr; + ushort scent_r_cnt; + uint scent_rtemp; + uint scent_tstate; + uint scent_t_ptr; + ushort scent_tbptr; + ushort scent_t_cnt; + uint scent_ttemp; + ushort scent_max_sl; + ushort scent_sl_cnt; + ushort scent_character1; + ushort scent_character2; + ushort scent_character3; + ushort scent_character4; + ushort scent_character5; + ushort scent_character6; + ushort scent_character7; + ushort scent_character8; + ushort scent_rccm; + ushort scent_rccr; +} smc_cent_t; + +/* Centronics Status Mask Register. +*/ +#define SMC_CENT_F ((u_char)0x08) +#define SMC_CENT_PE ((u_char)0x04) +#define SMC_CENT_S ((u_char)0x02) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SI Clock Route Register +*/ +#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) +#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) +#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) +#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) +#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) +#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* Function code bits. +*/ +#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* CPM Ethernet through SCCx. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PMSR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + char res1[8]; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PMSR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0002) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ + char res1[4]; /* Reserved */ + ushort iic_rpbase; /* Relocation pointer */ + char res2[2]; /* Reserved */ +} iic_t; + +#define BD_IIC_START ((ushort)0x0400) + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; + ushort spi_rpbase; /* Relocation pointer */ + ushort spi_res2; +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ +#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ +#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +/* SPIE fields */ +#define SPIE_MME 0x20 +#define SPIE_TXE 0x10 +#define SPIE_BSY 0x04 +#define SPIE_TXB 0x02 +#define SPIE_RXB 0x01 + +/* + * RISC Controller Configuration Register definitons + */ +#define RCCR_TIME 0x8000 /* RISC Timer Enable */ +#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ +#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ + +/* RISC Timer Parameter RAM offset */ +#define PROFF_RTMR ((uint)0x01B0) + +typedef struct risc_timer_pram { + unsigned short tm_base; /* RISC Timer Table Base Address */ + unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ + unsigned short r_tmr; /* RISC Timer Mode Register */ + unsigned short r_tmv; /* RISC Timer Valid Register */ + unsigned long tm_cmd; /* RISC Timer Command Register */ + unsigned long tm_cnt; /* RISC Timer Internal Count */ +} rt_pram_t; + +/* Bits in RISC Timer Command Register */ +#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ +#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ +#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ +#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ +#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ + +/* CPM interrupts. There are nearly 32 interrupts generated by CPM + * channels or devices. All of these are presented to the PPC core + * as a single interrupt. The CPM interrupt handler dispatches its + * own handlers, in a similar fashion to the PPC core handler. We + * use the table as defined in the manuals (i.e. no special high + * priority and SCC1 == SCCa, etc...). + */ +#define CPMVEC_NR 32 +#define CPMVEC_PIO_PC15 ((ushort)0x1f) +#define CPMVEC_SCC1 ((ushort)0x1e) +#define CPMVEC_SCC2 ((ushort)0x1d) +#define CPMVEC_SCC3 ((ushort)0x1c) +#define CPMVEC_SCC4 ((ushort)0x1b) +#define CPMVEC_PIO_PC14 ((ushort)0x1a) +#define CPMVEC_TIMER1 ((ushort)0x19) +#define CPMVEC_PIO_PC13 ((ushort)0x18) +#define CPMVEC_PIO_PC12 ((ushort)0x17) +#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) +#define CPMVEC_IDMA1 ((ushort)0x15) +#define CPMVEC_IDMA2 ((ushort)0x14) +#define CPMVEC_TIMER2 ((ushort)0x12) +#define CPMVEC_RISCTIMER ((ushort)0x11) +#define CPMVEC_I2C ((ushort)0x10) +#define CPMVEC_PIO_PC11 ((ushort)0x0f) +#define CPMVEC_PIO_PC10 ((ushort)0x0e) +#define CPMVEC_TIMER3 ((ushort)0x0c) +#define CPMVEC_PIO_PC9 ((ushort)0x0b) +#define CPMVEC_PIO_PC8 ((ushort)0x0a) +#define CPMVEC_PIO_PC7 ((ushort)0x09) +#define CPMVEC_TIMER4 ((ushort)0x07) +#define CPMVEC_PIO_PC6 ((ushort)0x06) +#define CPMVEC_SPI ((ushort)0x05) +#define CPMVEC_SMC1 ((ushort)0x04) +#define CPMVEC_SMC2 ((ushort)0x03) +#define CPMVEC_PIO_PC5 ((ushort)0x02) +#define CPMVEC_PIO_PC4 ((ushort)0x01) +#define CPMVEC_ERROR ((ushort)0x00) + +/* CPM interrupt configuration vector. +*/ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_IEN ((uint)0x00000080) /* Int. enable */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ + +extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); +extern void cpm_free_handler(int vec); + +#define IMAP_ADDR (get_immrbase()) + +#define CPM_PIN_INPUT 0 +#define CPM_PIN_OUTPUT 1 +#define CPM_PIN_PRIMARY 0 +#define CPM_PIN_SECONDARY 2 +#define CPM_PIN_GPIO 4 +#define CPM_PIN_OPENDRAIN 8 + +enum cpm_port { + CPM_PORTA, + CPM_PORTB, + CPM_PORTC, + CPM_PORTD, + CPM_PORTE, +}; + +void cpm1_set_pin(enum cpm_port port, int pin, int flags); + +enum cpm_clk_dir { + CPM_CLK_RX, + CPM_CLK_TX, + CPM_CLK_RTX +}; + +enum cpm_clk_target { + CPM_CLK_SCC1, + CPM_CLK_SCC2, + CPM_CLK_SCC3, + CPM_CLK_SCC4, + CPM_CLK_SMC1, + CPM_CLK_SMC2, +}; + +enum cpm_clk { + CPM_BRG1, /* Baud Rate Generator 1 */ + CPM_BRG2, /* Baud Rate Generator 2 */ + CPM_BRG3, /* Baud Rate Generator 3 */ + CPM_BRG4, /* Baud Rate Generator 4 */ + CPM_CLK1, /* Clock 1 */ + CPM_CLK2, /* Clock 2 */ + CPM_CLK3, /* Clock 3 */ + CPM_CLK4, /* Clock 4 */ + CPM_CLK5, /* Clock 5 */ + CPM_CLK6, /* Clock 6 */ + CPM_CLK7, /* Clock 7 */ + CPM_CLK8, /* Clock 8 */ +}; + +int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); + +#endif /* __CPM_8XX__ */ diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h new file mode 100644 index 000000000000..48df9f330e76 --- /dev/null +++ b/include/asm-powerpc/cpm.h @@ -0,0 +1,14 @@ +#ifndef __CPM_H +#define __CPM_H + +#include <linux/compiler.h> +#include <linux/types.h> + +int cpm_muram_init(void); +unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); +int cpm_muram_free(unsigned long offset); +unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); +void __iomem *cpm_muram_addr(unsigned long offset); +dma_addr_t cpm_muram_dma(void __iomem *addr); + +#endif diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h new file mode 100644 index 000000000000..f1112c15ef96 --- /dev/null +++ b/include/asm-powerpc/cpm2.h @@ -0,0 +1,1274 @@ +/* + * Communication Processor Module v2. + * + * This file contains structures and information for the communication + * processor channels found in the dual port RAM or parameter RAM. + * All CPM control and status is available through the CPM2 internal + * memory map. See immap_cpm2.h for details. + */ +#ifdef __KERNEL__ +#ifndef __CPM2__ +#define __CPM2__ + +#include <asm/immap_cpm2.h> +#include <asm/cpm.h> + +#ifdef CONFIG_PPC_85xx +#define CPM_MAP_ADDR (get_immrbase() + 0x80000) +#endif + +/* CPM Command register. +*/ +#define CPM_CR_RST ((uint)0x80000000) +#define CPM_CR_PAGE ((uint)0x7c000000) +#define CPM_CR_SBLOCK ((uint)0x03e00000) +#define CPM_CR_FLG ((uint)0x00010000) +#define CPM_CR_MCN ((uint)0x00003fc0) +#define CPM_CR_OPCODE ((uint)0x0000000f) + +/* Device sub-block and page codes. +*/ +#define CPM_CR_SCC1_SBLOCK (0x04) +#define CPM_CR_SCC2_SBLOCK (0x05) +#define CPM_CR_SCC3_SBLOCK (0x06) +#define CPM_CR_SCC4_SBLOCK (0x07) +#define CPM_CR_SMC1_SBLOCK (0x08) +#define CPM_CR_SMC2_SBLOCK (0x09) +#define CPM_CR_SPI_SBLOCK (0x0a) +#define CPM_CR_I2C_SBLOCK (0x0b) +#define CPM_CR_TIMER_SBLOCK (0x0f) +#define CPM_CR_RAND_SBLOCK (0x0e) +#define CPM_CR_FCC1_SBLOCK (0x10) +#define CPM_CR_FCC2_SBLOCK (0x11) +#define CPM_CR_FCC3_SBLOCK (0x12) +#define CPM_CR_IDMA1_SBLOCK (0x14) +#define CPM_CR_IDMA2_SBLOCK (0x15) +#define CPM_CR_IDMA3_SBLOCK (0x16) +#define CPM_CR_IDMA4_SBLOCK (0x17) +#define CPM_CR_MCC1_SBLOCK (0x1c) + +#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) + +#define CPM_CR_SCC1_PAGE (0x00) +#define CPM_CR_SCC2_PAGE (0x01) +#define CPM_CR_SCC3_PAGE (0x02) +#define CPM_CR_SCC4_PAGE (0x03) +#define CPM_CR_SMC1_PAGE (0x07) +#define CPM_CR_SMC2_PAGE (0x08) +#define CPM_CR_SPI_PAGE (0x09) +#define CPM_CR_I2C_PAGE (0x0a) +#define CPM_CR_TIMER_PAGE (0x0a) +#define CPM_CR_RAND_PAGE (0x0a) +#define CPM_CR_FCC1_PAGE (0x04) +#define CPM_CR_FCC2_PAGE (0x05) +#define CPM_CR_FCC3_PAGE (0x06) +#define CPM_CR_IDMA1_PAGE (0x07) +#define CPM_CR_IDMA2_PAGE (0x08) +#define CPM_CR_IDMA3_PAGE (0x09) +#define CPM_CR_IDMA4_PAGE (0x0a) +#define CPM_CR_MCC1_PAGE (0x07) +#define CPM_CR_MCC2_PAGE (0x08) + +#define CPM_CR_FCC_PAGE(x) (x + 0x04) + +/* Some opcodes (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) +#define CPM_CR_START_IDMA ((ushort)0x0009) +#define CPM_CR_STOP_IDMA ((ushort)0x000b) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + +#ifndef CONFIG_PPC_CPM_NEW_BINDING +/* Dual Port RAM addresses. The first 16K is available for almost + * any CPM use, so we put the BDs there. The first 128 bytes are + * used for SMC1 and SMC2 parameter RAM, so we start allocating + * BDs above that. All of this must change when we start + * downloading RAM microcode. + */ +#define CPM_DATAONLY_BASE ((uint)128) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) +#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) +#else +#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) +#endif +#endif + +/* The number of pages of host memory we allocate for CPM. This is + * done early in kernel initialization to get physically contiguous + * pages. + */ +#define NUM_CPM_HOST_PAGES 2 + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */ + +#ifdef CONFIG_PPC_CPM_NEW_BINDING +#define cpm_dpalloc cpm_muram_alloc +#define cpm_dpfree cpm_muram_free +#define cpm_dpram_addr cpm_muram_addr +#else +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); +extern void cpm_dpdump(void); +extern void *cpm_dpram_addr(unsigned long offset); +#endif + +extern void cpm_setbrg(uint brg, uint rate); +extern void cpm2_fastbrg(uint brg, uint rate, int div16); +extern void cpm2_reset(void); + + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ + +/* Function code bits, usually generic to devices. +*/ +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ + +/* Parameter RAM offsets from the base. +*/ +#define PROFF_SCC1 ((uint)0x8000) +#define PROFF_SCC2 ((uint)0x8100) +#define PROFF_SCC3 ((uint)0x8200) +#define PROFF_SCC4 ((uint)0x8300) +#define PROFF_FCC1 ((uint)0x8400) +#define PROFF_FCC2 ((uint)0x8500) +#define PROFF_FCC3 ((uint)0x8600) +#define PROFF_MCC1 ((uint)0x8700) +#define PROFF_SMC1_BASE ((uint)0x87fc) +#define PROFF_IDMA1_BASE ((uint)0x87fe) +#define PROFF_MCC2 ((uint)0x8800) +#define PROFF_SMC2_BASE ((uint)0x88fc) +#define PROFF_IDMA2_BASE ((uint)0x88fe) +#define PROFF_SPI_BASE ((uint)0x89fc) +#define PROFF_IDMA3_BASE ((uint)0x89fe) +#define PROFF_TIMERS ((uint)0x8ae0) +#define PROFF_REVNUM ((uint)0x8af0) +#define PROFF_RAND ((uint)0x8af8) +#define PROFF_I2C_BASE ((uint)0x8afc) +#define PROFF_IDMA4_BASE ((uint)0x8afe) + +#define PROFF_SCC_SIZE ((uint)0x100) +#define PROFF_FCC_SIZE ((uint)0x100) +#define PROFF_SMC_SIZE ((uint)64) + +/* The SMCs are relocated to any of the first eight DPRAM pages. + * We will fix these at the first locations of DPRAM, until we + * get some microcode patches :-). + * The parameter ram space for the SMCs is fifty-some bytes, and + * they are required to start on a 64 byte boundary. + */ +#define PROFF_SMC1 (0) +#define PROFF_SMC2 (64) + + +/* Define enough so I can at least use the serial port as a UART. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + uint smc_stmp; /* SDMA Temp */ +} smc_uart_t; + +/* SMC uart mode register (Internal memory map). +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* CPM Ethernet through SCC1. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0002) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* How about some FCCs..... +*/ +#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) +#define FCC_GFMR_DIAG_LE ((uint)0x40000000) +#define FCC_GFMR_DIAG_AE ((uint)0x80000000) +#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) +#define FCC_GFMR_TCI ((uint)0x20000000) +#define FCC_GFMR_TRX ((uint)0x10000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_CDP ((uint)0x04000000) +#define FCC_GFMR_CTSP ((uint)0x02000000) +#define FCC_GFMR_CDS ((uint)0x01000000) +#define FCC_GFMR_CTSS ((uint)0x00800000) +#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) +#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) +#define FCC_GFMR_SYNL_8 ((uint)0x00008000) +#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) +#define FCC_GFMR_RTSM ((uint)0x00002000) +#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) +#define FCC_GFMR_REVD ((uint)0x00000400) +#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) +#define FCC_GFMR_TCRC_16 ((uint)0x00000000) +#define FCC_GFMR_TCRC_32 ((uint)0x00000080) +#define FCC_GFMR_ENR ((uint)0x00000020) +#define FCC_GFMR_ENT ((uint)0x00000010) +#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) +#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) +#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) + +/* Generic FCC parameter ram. +*/ +typedef struct fcc_param { + ushort fcc_riptr; /* Rx Internal temp pointer */ + ushort fcc_tiptr; /* Tx Internal temp pointer */ + ushort fcc_res1; + ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ + uint fcc_rstate; /* Upper byte is Func code, must be set */ + uint fcc_rbase; /* Receive BD base */ + ushort fcc_rbdstat; /* RxBD status */ + ushort fcc_rbdlen; /* RxBD down counter */ + uint fcc_rdptr; /* RxBD internal data pointer */ + uint fcc_tstate; /* Upper byte is Func code, must be set */ + uint fcc_tbase; /* Transmit BD base */ + ushort fcc_tbdstat; /* TxBD status */ + ushort fcc_tbdlen; /* TxBD down counter */ + uint fcc_tdptr; /* TxBD internal data pointer */ + uint fcc_rbptr; /* Rx BD Internal buf pointer */ + uint fcc_tbptr; /* Tx BD Internal buf pointer */ + uint fcc_rcrc; /* Rx temp CRC */ + uint fcc_res2; + uint fcc_tcrc; /* Tx temp CRC */ +} fccp_t; + + +/* Ethernet controller through FCC. +*/ +typedef struct fcc_enet { + fccp_t fen_genfcc; + uint fen_statbuf; /* Internal status buffer */ + uint fen_camptr; /* CAM address */ + uint fen_cmask; /* Constant mask for CRC */ + uint fen_cpres; /* Preset CRC */ + uint fen_crcec; /* CRC Error counter */ + uint fen_alec; /* alignment error counter */ + uint fen_disfc; /* discard frame counter */ + ushort fen_retlim; /* Retry limit */ + ushort fen_retcnt; /* Retry counter */ + ushort fen_pper; /* Persistence */ + ushort fen_boffcnt; /* backoff counter */ + uint fen_gaddrh; /* Group address filter, high 32-bits */ + uint fen_gaddrl; /* Group address filter, low 32-bits */ + ushort fen_tfcstat; /* out of sequence TxBD */ + ushort fen_tfclen; + uint fen_tfcptr; + ushort fen_mflr; /* Maximum frame length (1518) */ + ushort fen_paddrh; /* MAC address */ + ushort fen_paddrm; + ushort fen_paddrl; + ushort fen_ibdcount; /* Internal BD counter */ + ushort fen_ibdstart; /* Internal BD start pointer */ + ushort fen_ibdend; /* Internal BD end pointer */ + ushort fen_txlen; /* Internal Tx frame length counter */ + uint fen_ibdbase[8]; /* Internal use */ + uint fen_iaddrh; /* Individual address filter */ + uint fen_iaddrl; + ushort fen_minflr; /* Minimum frame length (64) */ + ushort fen_taddrh; /* Filter transfer MAC address */ + ushort fen_taddrm; + ushort fen_taddrl; + ushort fen_padptr; /* Pointer to pad byte buffer */ + ushort fen_cftype; /* control frame type */ + ushort fen_cfrange; /* control frame range */ + ushort fen_maxb; /* maximum BD count */ + ushort fen_maxd1; /* Max DMA1 length (1520) */ + ushort fen_maxd2; /* Max DMA2 length (1520) */ + ushort fen_maxd; /* internal max DMA count */ + ushort fen_dmacnt; /* internal DMA counter */ + uint fen_octc; /* Total octect counter */ + uint fen_colc; /* Total collision counter */ + uint fen_broc; /* Total broadcast packet counter */ + uint fen_mulc; /* Total multicast packet count */ + uint fen_uspc; /* Total packets < 64 bytes */ + uint fen_frgc; /* Total packets < 64 bytes with errors */ + uint fen_ospc; /* Total packets > 1518 */ + uint fen_jbrc; /* Total packets > 1518 with errors */ + uint fen_p64c; /* Total packets == 64 bytes */ + uint fen_p65c; /* Total packets 64 < bytes <= 127 */ + uint fen_p128c; /* Total packets 127 < bytes <= 255 */ + uint fen_p256c; /* Total packets 256 < bytes <= 511 */ + uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ + uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ + uint fen_cambuf; /* Internal CAM buffer poiner */ + ushort fen_rfthr; /* Received frames threshold */ + ushort fen_rfcnt; /* Received frames count */ +} fcc_enet_t; + +/* FCC Event/Mask register as used by Ethernet. +*/ +#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ +#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ +#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ +#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* FCC Mode Register (FPSMR) as used by Ethernet. +*/ +#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ +#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ +#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ +#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ +#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ +#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ +#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ +#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ +#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ +#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ +#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ +#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ +#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; /* Tx temp. */ + uint spi_res1[4]; /* SDMA temp. */ +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +#define SPI_EB ((u_char)0x10) /* big endian byte order */ + +#define BD_IIC_START ((ushort)0x0400) + +/* IDMA parameter RAM +*/ +typedef struct idma { + ushort ibase; /* IDMA buffer descriptor table base address */ + ushort dcm; /* DMA channel mode */ + ushort ibdptr; /* IDMA current buffer descriptor pointer */ + ushort dpr_buf; /* IDMA transfer buffer base address */ + ushort buf_inv; /* internal buffer inventory */ + ushort ss_max; /* steady-state maximum transfer size */ + ushort dpr_in_ptr; /* write pointer inside the internal buffer */ + ushort sts; /* source transfer size */ + ushort dpr_out_ptr; /* read pointer inside the internal buffer */ + ushort seob; /* source end of burst */ + ushort deob; /* destination end of burst */ + ushort dts; /* destination transfer size */ + ushort ret_add; /* return address when working in ERM=1 mode */ + ushort res0; /* reserved */ + uint bd_cnt; /* internal byte count */ + uint s_ptr; /* source internal data pointer */ + uint d_ptr; /* destination internal data pointer */ + uint istate; /* internal state */ + u_char res1[20]; /* pad to 64-byte length */ +} idma_t; + +/* DMA channel mode bit fields +*/ +#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ +#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ +#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ +#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ +#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ +#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ +#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ +#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ +#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ +#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ +#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ +#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ +#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ +#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ + +/* IDMA Buffer Descriptors +*/ +typedef struct idma_bd { + uint flags; + uint len; /* data length */ + uint src; /* source data buffer pointer */ + uint dst; /* destination data buffer pointer */ +} idma_bd_t; + +/* IDMA buffer descriptor flag bit fields +*/ +#define IDMA_BD_V ((uint)0x80000000) /* valid */ +#define IDMA_BD_W ((uint)0x20000000) /* wrap */ +#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ +#define IDMA_BD_L ((uint)0x08000000) /* last */ +#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ +#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ +#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ +#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ +#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ +#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ +#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ +#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ +#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ +#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ +#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ + +/* per-channel IDMA registers +*/ +typedef struct im_idma { + u_char idsr; /* IDMAn event status register */ + u_char res0[3]; + u_char idmr; /* IDMAn event mask register */ + u_char res1[3]; +} im_idma_t; + +/* IDMA event register bit fields +*/ +#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ +#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ +#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ +#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ + +/* RISC Controller Configuration Register (RCCR) bit fields +*/ +#define RCCR_TIME ((uint)0x80000000) /* timer enable */ +#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ +#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ +#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ +#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ +#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ +#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ +#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ +#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ +#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ +#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ +#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ +#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ +#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ +#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ +#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ +#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ +#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ +#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ +#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ +#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ +#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ +#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ +#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ +#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ +#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ +#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ +#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ +#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ +#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ +#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ +#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ +#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ +#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ +#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ +#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ +#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ +#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ + +/*----------------------------------------------------------------------- + * CMXFCR - CMX FCC Clock Route Register + */ +#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ +#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ +#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ +#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ +#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ +#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ +#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ +#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ +#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ + +#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ +#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ +#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ +#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ +#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ +#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ +#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ +#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ + +#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ +#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ +#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ +#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ +#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ +#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ +#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ +#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ + +#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ +#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ +#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ +#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ +#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ +#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ +#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ +#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ + +#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ +#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ +#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ +#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ +#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ +#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ +#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ +#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ + +#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ +#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ +#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ +#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ +#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ +#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ +#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ +#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ + +#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ +#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ +#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ +#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ +#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ +#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ +#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ +#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ + +/*----------------------------------------------------------------------- + * CMXSCR - CMX SCC Clock Route Register + */ +#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ +#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ +#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ +#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ +#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ +#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ +#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ +#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ +#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ +#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ +#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ +#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ +#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ +#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ +#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ +#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ + +#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ +#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ +#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ +#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ +#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ +#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ +#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ +#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ +#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ +#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ +#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ +#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ +#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ +#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ +#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ +#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ +#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ +#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ +#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ +#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ +#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ +#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ +#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ +#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ +#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ +#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ +#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ +#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ +#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ +#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ +#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ +#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ +#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ +#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ +#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ +#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ +#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ +#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ +#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ +#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ +#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ +#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ +#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ + +#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ +#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ +#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ +#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ +#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ +#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ +#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ +#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ +#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ +#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ +#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ +#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ +#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ +#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ +#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration Register 4-31 + */ +#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ +#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ +#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ +#define SIUMCR_CDIS 0x10000000 /* Core Disable */ +#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ +#define SIUMCR_DPPC01 0x04000000 /* - " - */ +#define SIUMCR_DPPC10 0x08000000 /* - " - */ +#define SIUMCR_DPPC11 0x0c000000 /* - " - */ +#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ +#define SIUMCR_L2CPC01 0x01000000 /* - " - */ +#define SIUMCR_L2CPC10 0x02000000 /* - " - */ +#define SIUMCR_L2CPC11 0x03000000 /* - " - */ +#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ +#define SIUMCR_LBPC01 0x00400000 /* - " - */ +#define SIUMCR_LBPC10 0x00800000 /* - " - */ +#define SIUMCR_LBPC11 0x00c00000 /* - " - */ +#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ +#define SIUMCR_APPC01 0x00100000 /* - " - */ +#define SIUMCR_APPC10 0x00200000 /* - " - */ +#define SIUMCR_APPC11 0x00300000 /* - " - */ +#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ +#define SIUMCR_CS10PC01 0x00040000 /* - " - */ +#define SIUMCR_CS10PC10 0x00080000 /* - " - */ +#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ +#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ +#define SIUMCR_BCTLC01 0x00010000 /* - " - */ +#define SIUMCR_BCTLC10 0x00020000 /* - " - */ +#define SIUMCR_BCTLC11 0x00030000 /* - " - */ +#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ +#define SIUMCR_MMR01 0x00004000 /* - " - */ +#define SIUMCR_MMR10 0x00008000 /* - " - */ +#define SIUMCR_MMR11 0x0000c000 /* - " - */ +#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control Register 9-8 +*/ +#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ +#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ +#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ +#define SCCR_PCIDF_SHIFT 3 + +#ifndef CPM_IMMR_OFFSET +#define CPM_IMMR_OFFSET 0x101a8 +#endif + +#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ + +/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK + * in order to use clock-computing stuff below for the FCC x + */ + +/* Automatically generates register configurations */ +#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ + +#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ +#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ +#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ +#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ +#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ +#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ + +#define PC_F1RXCLK PC_CLK(F1_RXCLK) +#define PC_F1TXCLK PC_CLK(F1_TXCLK) +#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) +#define CMX1_CLK_MASK ((uint)0xff000000) + +#define PC_F2RXCLK PC_CLK(F2_RXCLK) +#define PC_F2TXCLK PC_CLK(F2_TXCLK) +#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) +#define CMX2_CLK_MASK ((uint)0x00ff0000) + +#define PC_F3RXCLK PC_CLK(F3_RXCLK) +#define PC_F3TXCLK PC_CLK(F3_TXCLK) +#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) +#define CMX3_CLK_MASK ((uint)0x0000ff00) + +#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) +#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) + +#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) + +/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PA1_COL 0x00000001U +#define PA1_CRS 0x00000002U +#define PA1_TXER 0x00000004U +#define PA1_TXEN 0x00000008U +#define PA1_RXDV 0x00000010U +#define PA1_RXER 0x00000020U +#define PA1_TXDAT 0x00003c00U +#define PA1_RXDAT 0x0003c000U +#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) +#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ + PA1_RXDV | PA1_RXER) +#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) +#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) + + +/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB2_TXER 0x00000001U +#define PB2_RXDV 0x00000002U +#define PB2_TXEN 0x00000004U +#define PB2_RXER 0x00000008U +#define PB2_COL 0x00000010U +#define PB2_CRS 0x00000020U +#define PB2_TXDAT 0x000003c0U +#define PB2_RXDAT 0x00003c00U +#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ + PB2_RXER | PB2_RXDV | PB2_TXER) +#define PB2_PSORB1 (PB2_TXEN) +#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) +#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) + + +/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB3_RXDV 0x00004000U +#define PB3_RXER 0x00008000U +#define PB3_TXER 0x00010000U +#define PB3_TXEN 0x00020000U +#define PB3_COL 0x00040000U +#define PB3_CRS 0x00080000U +#define PB3_TXDAT 0x0f000000U +#define PC3_TXDAT 0x00000010U +#define PB3_RXDAT 0x00f00000U +#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ + PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) +#define PB3_PSORB1 0 +#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) +#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) +#define PC3_DIRC1 (PC3_TXDAT) + +/* Handy macro to specify mem for FCCs*/ +#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) +#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) +#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) +#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) + +/* Clocks and GRG's */ + +enum cpm_clk_dir { + CPM_CLK_RX, + CPM_CLK_TX, + CPM_CLK_RTX +}; + +enum cpm_clk_target { + CPM_CLK_SCC1, + CPM_CLK_SCC2, + CPM_CLK_SCC3, + CPM_CLK_SCC4, + CPM_CLK_FCC1, + CPM_CLK_FCC2, + CPM_CLK_FCC3, + CPM_CLK_SMC1, + CPM_CLK_SMC2, +}; + +enum cpm_clk { + CPM_CLK_NONE = 0, + CPM_BRG1, /* Baud Rate Generator 1 */ + CPM_BRG2, /* Baud Rate Generator 2 */ + CPM_BRG3, /* Baud Rate Generator 3 */ + CPM_BRG4, /* Baud Rate Generator 4 */ + CPM_BRG5, /* Baud Rate Generator 5 */ + CPM_BRG6, /* Baud Rate Generator 6 */ + CPM_BRG7, /* Baud Rate Generator 7 */ + CPM_BRG8, /* Baud Rate Generator 8 */ + CPM_CLK1, /* Clock 1 */ + CPM_CLK2, /* Clock 2 */ + CPM_CLK3, /* Clock 3 */ + CPM_CLK4, /* Clock 4 */ + CPM_CLK5, /* Clock 5 */ + CPM_CLK6, /* Clock 6 */ + CPM_CLK7, /* Clock 7 */ + CPM_CLK8, /* Clock 8 */ + CPM_CLK9, /* Clock 9 */ + CPM_CLK10, /* Clock 10 */ + CPM_CLK11, /* Clock 11 */ + CPM_CLK12, /* Clock 12 */ + CPM_CLK13, /* Clock 13 */ + CPM_CLK14, /* Clock 14 */ + CPM_CLK15, /* Clock 15 */ + CPM_CLK16, /* Clock 16 */ + CPM_CLK17, /* Clock 17 */ + CPM_CLK18, /* Clock 18 */ + CPM_CLK19, /* Clock 19 */ + CPM_CLK20, /* Clock 20 */ + CPM_CLK_DUMMY +}; + +extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); +extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock); + +#define CPM_PIN_INPUT 0 +#define CPM_PIN_OUTPUT 1 +#define CPM_PIN_PRIMARY 0 +#define CPM_PIN_SECONDARY 2 +#define CPM_PIN_GPIO 4 +#define CPM_PIN_OPENDRAIN 8 + +void cpm2_set_pin(int port, int pin, int flags); + +#endif /* __CPM2__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 3dc8e2dfca84..ae093ef68363 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -57,6 +57,7 @@ enum powerpc_pmc_type { PPC_PMC_PA6T = 2, }; +/* NOTE WELL: Update identify_cpu() if fields are added or removed! */ struct cpu_spec { /* CPU is matched via (PVR & pvr_mask) == pvr_value */ unsigned int pvr_mask; @@ -136,6 +137,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) +#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) /* * Add the 64-bit processor unique features in the top half of the word; @@ -162,6 +164,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) +#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) #ifndef __ASSEMBLY__ @@ -180,12 +183,27 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 #endif -/* We need to mark all pages as being coherent if we're SMP or we - * have a 74[45]x and an MPC107 host bridge. Also 83xx requires - * it for PCI "streaming/prefetch" to work properly. +/* We only set the spe features if the kernel was compiled with spe + * support + */ +#ifdef CONFIG_SPE +#define CPU_FTR_SPE_COMP CPU_FTR_SPE +#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE +#else +#define CPU_FTR_SPE_COMP 0 +#define PPC_FEATURE_HAS_SPE_COMP 0 +#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 +#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 +#endif + +/* We need to mark all pages as being coherent if we're SMP or we have a + * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II + * require it for PCI "streaming/prefetch" to work properly. */ #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ - || defined(CONFIG_PPC_83xx) + || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT #else #define CPU_FTR_COMMON 0 @@ -297,7 +315,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, CPU_FTR_PPC_LE) #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) -#define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE | \ +#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ @@ -310,10 +328,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_8XX (CPU_FTR_USE_TB) #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ - CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) -#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) -#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \ +#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ + CPU_FTR_UNIFIED_ID_CACHE) +#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ + CPU_FTR_NODSISRALIGN) +#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) @@ -355,7 +375,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_POSSIBLE \ (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ - CPU_FTRS_CELL | CPU_FTRS_PA6T) + CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT) #else enum { CPU_FTRS_POSSIBLE = diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h index 5dbfca8dde36..6b82c3ba495a 100644 --- a/include/asm-powerpc/dcr-mmio.h +++ b/include/asm-powerpc/dcr-mmio.h @@ -23,7 +23,11 @@ #include <asm/io.h> -typedef struct { void __iomem *token; unsigned int stride; } dcr_host_t; +typedef struct { + void __iomem *token; + unsigned int stride; + unsigned int base; +} dcr_host_t; #define DCR_MAP_OK(host) ((host).token != NULL) diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index 05af081222f6..f41058c0f6cb 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h @@ -22,11 +22,13 @@ #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -typedef struct {} dcr_host_t; +typedef struct { + unsigned int base; +} dcr_host_t; #define DCR_MAP_OK(host) (1) -#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){}) +#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) #define dcr_unmap(host, dcr_n, dcr_c) do {} while (0) #define dcr_read(host, dcr_n) mfdcr(dcr_n) #define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value) diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index f6bd804d9090..d05891608f74 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -95,7 +95,7 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask) return -EIO; if (dma_ops->set_dma_mask != NULL) return dma_ops->set_dma_mask(dev, dma_mask); - if (!dev->dma_mask || !dma_supported(dev, *dev->dma_mask)) + if (!dev->dma_mask || !dma_supported(dev, dma_mask)) return -EIO; *dev->dma_mask = dma_mask; return 0; @@ -249,8 +249,12 @@ dma_map_single(struct device *dev, void *ptr, size_t size, return virt_to_bus(ptr); } -/* We do nothing. */ -#define dma_unmap_single(dev, addr, size, dir) ((void)0) +static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction) +{ + /* We do nothing. */ +} static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, @@ -264,8 +268,12 @@ dma_map_page(struct device *dev, struct page *page, return page_to_bus(page) + offset; } -/* We do nothing. */ -#define dma_unmap_page(dev, handle, size, dir) ((void)0) +static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, + enum dma_data_direction direction) +{ + /* We do nothing. */ +} static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, @@ -284,8 +292,12 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, return nents; } -/* We don't do anything here. */ -#define dma_unmap_sg(dev, sg, nents, dir) ((void)0) +static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, + enum dma_data_direction direction) +{ + /* We don't do anything here. */ +} #endif /* CONFIG_PPC64 */ diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index de507995c7b1..e42820d6d25b 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -413,13 +413,8 @@ do { \ /* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */ #define NT_SPU 1 -extern int arch_notes_size(void); -extern void arch_write_notes(struct file *file); - -#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size() -#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file) - #define ARCH_HAVE_EXTRA_ELF_NOTES -#endif /* CONFIG_PPC_CELL */ + +#endif /* CONFIG_SPU_BASE */ #endif /* _ASM_POWERPC_ELF_H */ diff --git a/include/asm-powerpc/exception.h b/include/asm-powerpc/exception.h new file mode 100644 index 000000000000..39abdb02fdef --- /dev/null +++ b/include/asm-powerpc/exception.h @@ -0,0 +1,311 @@ +#ifndef _ASM_POWERPC_EXCEPTION_H +#define _ASM_POWERPC_EXCEPTION_H +/* + * Extracted from head_64.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and + * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com + * + * This file contains the low-level support and setup for the + * PowerPC-64 platform, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +/* + * The following macros define the code that appears as + * the prologue to each of the exception handlers. They + * are split into two parts to allow a single kernel binary + * to be used for pSeries and iSeries. + * + * We make as much of the exception code common between native + * exception handlers (including pSeries LPAR) and iSeries LPAR + * implementations as possible. + */ + +#define EX_R9 0 +#define EX_R10 8 +#define EX_R11 16 +#define EX_R12 24 +#define EX_R13 32 +#define EX_SRR0 40 +#define EX_DAR 48 +#define EX_DSISR 56 +#define EX_CCR 60 +#define EX_R3 64 +#define EX_LR 72 + +/* + * We're short on space and time in the exception prolog, so we can't + * use the normal SET_REG_IMMEDIATE macro. Normally we just need the + * low halfword of the address, but for Kdump we need the whole low + * word. + */ +#ifdef CONFIG_CRASH_DUMP +#define LOAD_HANDLER(reg, label) \ + oris reg,reg,(label)@h; /* virt addr of handler ... */ \ + ori reg,reg,(label)@l; /* .. and the rest */ +#else +#define LOAD_HANDLER(reg, label) \ + ori reg,reg,(label)@l; /* virt addr of handler ... */ +#endif + +#define EXCEPTION_PROLOG_1(area) \ + mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ + std r9,area+EX_R9(r13); /* save r9 - r12 */ \ + std r10,area+EX_R10(r13); \ + std r11,area+EX_R11(r13); \ + std r12,area+EX_R12(r13); \ + mfspr r9,SPRN_SPRG1; \ + std r9,area+EX_R13(r13); \ + mfcr r9 + +/* + * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. + * The firmware calls the registered system_reset_fwnmi and + * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run + * a 32bit application at the time of the event. + * This firmware bug is present on POWER4 and JS20. + */ +#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ + EXCEPTION_PROLOG_1(area); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + /* force 64bit mode */ \ + li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ + rldimi r10,r11,61,0; /* insert into top 3 bits */ \ + /* done 64bit mode */ \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +#define EXCEPTION_PROLOG_PSERIES(area, label) \ + EXCEPTION_PROLOG_1(area); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +/* + * The common exception prolog is used for all except a few exceptions + * such as a segment miss on a kernel address. We have to be prepared + * to take another exception from the point where we first touch the + * kernel stack onwards. + * + * On entry r13 points to the paca, r9-r13 are saved in the paca, + * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and + * SRR1, and relocation is on. + */ +#define EXCEPTION_PROLOG_COMMON(n, area) \ + andi. r10,r12,MSR_PR; /* See if coming from user */ \ + mr r10,r1; /* Save r1 */ \ + subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ + beq- 1f; \ + ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ +1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ + bge- cr1,2f; /* abort if it is */ \ + b 3f; \ +2: li r1,(n); /* will be reloaded later */ \ + sth r1,PACA_TRAP_SAVE(r13); \ + b bad_stack; \ +3: std r9,_CCR(r1); /* save CR in stackframe */ \ + std r11,_NIP(r1); /* save SRR0 in stackframe */ \ + std r12,_MSR(r1); /* save SRR1 in stackframe */ \ + std r10,0(r1); /* make stack chain pointer */ \ + std r0,GPR0(r1); /* save r0 in stackframe */ \ + std r10,GPR1(r1); /* save r1 in stackframe */ \ + ACCOUNT_CPU_USER_ENTRY(r9, r10); \ + std r2,GPR2(r1); /* save r2 in stackframe */ \ + SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ + SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ + ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ + ld r10,area+EX_R10(r13); \ + std r9,GPR9(r1); \ + std r10,GPR10(r1); \ + ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ + ld r10,area+EX_R12(r13); \ + ld r11,area+EX_R13(r13); \ + std r9,GPR11(r1); \ + std r10,GPR12(r1); \ + std r11,GPR13(r1); \ + ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ + mflr r9; /* save LR in stackframe */ \ + std r9,_LINK(r1); \ + mfctr r10; /* save CTR in stackframe */ \ + std r10,_CTR(r1); \ + lbz r10,PACASOFTIRQEN(r13); \ + mfspr r11,SPRN_XER; /* save XER in stackframe */ \ + std r10,SOFTE(r1); \ + std r11,_XER(r1); \ + li r9,(n)+1; \ + std r9,_TRAP(r1); /* set trap number */ \ + li r10,0; \ + ld r11,exception_marker@toc(r2); \ + std r10,RESULT(r1); /* clear regs->result */ \ + std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ + +/* + * Exception vectors. + */ +#define STD_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) + +#define HSTD_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r20; /* save r20 */ \ + mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ + mtspr SPRN_SRR0,r20; \ + mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \ + mtspr SPRN_SRR1,r20; \ + mfspr r20,SPRN_SPRG1; /* restore r20 */ \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) + + +#define MASKABLE_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRN_SPRG1,r13; /* save r13 */ \ + mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ + std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ + std r10,PACA_EXGEN+EX_R10(r13); \ + lbz r10,PACASOFTIRQEN(r13); \ + mfcr r9; \ + cmpwi r10,0; \ + beq masked_interrupt; \ + mfspr r10,SPRN_SPRG1; \ + std r10,PACA_EXGEN+EX_R13(r13); \ + std r11,PACA_EXGEN+EX_R11(r13); \ + std r12,PACA_EXGEN+EX_R12(r13); \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + mfspr r11,SPRN_SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label##_common) \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SPRN_SRR0,r12; \ + mfspr r12,SPRN_SRR1; /* and SRR1 */ \ + mtspr SPRN_SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +#ifdef CONFIG_PPC_ISERIES +#define DISABLE_INTS \ + li r11,0; \ + stb r11,PACASOFTIRQEN(r13); \ +BEGIN_FW_FTR_SECTION; \ + stb r11,PACAHARDIRQEN(r13); \ +END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ +BEGIN_FW_FTR_SECTION; \ + mfmsr r10; \ + ori r10,r10,MSR_EE; \ + mtmsrd r10,1; \ +END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) + +#else +#define DISABLE_INTS \ + li r11,0; \ + stb r11,PACASOFTIRQEN(r13); \ + stb r11,PACAHARDIRQEN(r13) + +#endif /* CONFIG_PPC_ISERIES */ + +#define ENABLE_INTS \ + ld r12,_MSR(r1); \ + mfmsr r11; \ + rlwimi r11,r12,0,MSR_EE; \ + mtmsrd r11,1 + +#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + DISABLE_INTS; \ + bl .save_nvgprs; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except + +/* + * Like STD_EXCEPTION_COMMON, but for exceptions that can occur + * in the idle task and therefore need the special idle handling. + */ +#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + FINISH_NAP; \ + DISABLE_INTS; \ + bl .save_nvgprs; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except + +#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + FINISH_NAP; \ + DISABLE_INTS; \ +BEGIN_FTR_SECTION \ + bl .ppc64_runlatch_on; \ +END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except_lite + +/* + * When the idle code in power4_idle puts the CPU into NAP mode, + * it has to do so in a loop, and relies on the external interrupt + * and decrementer interrupt entry code to get it out of the loop. + * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags + * to signal that it is in the loop and needs help to get out. + */ +#ifdef CONFIG_PPC_970_NAP +#define FINISH_NAP \ +BEGIN_FTR_SECTION \ + clrrdi r11,r1,THREAD_SHIFT; \ + ld r9,TI_LOCAL_FLAGS(r11); \ + andi. r10,r9,_TLF_NAPPING; \ + bnel power4_fixup_nap; \ +END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) +#else +#define FINISH_NAP +#endif + +#endif /* _ASM_POWERPC_EXCEPTION_H */ diff --git a/include/asm-powerpc/fs_pd.h b/include/asm-powerpc/fs_pd.h index c624915b757e..9361cd5342cc 100644 --- a/include/asm-powerpc/fs_pd.h +++ b/include/asm-powerpc/fs_pd.h @@ -19,48 +19,22 @@ #if defined(CONFIG_8260) #include <asm/mpc8260.h> -#elif defined(CONFIG_85xx) -#include <asm/mpc85xx.h> #endif -#define cpm2_map(member) \ -({ \ - u32 offset = offsetof(cpm2_map_t, member); \ - void *addr = ioremap (CPM_MAP_ADDR + offset, \ - sizeof( ((cpm2_map_t*)0)->member)); \ - addr; \ -}) - -#define cpm2_map_size(member, size) \ -({ \ - u32 offset = offsetof(cpm2_map_t, member); \ - void *addr = ioremap (CPM_MAP_ADDR + offset, size); \ - addr; \ -}) - -#define cpm2_unmap(addr) iounmap(addr) +#define cpm2_map(member) (&cpm2_immr->member) +#define cpm2_map_size(member, size) (&cpm2_immr->member) +#define cpm2_unmap(addr) do {} while(0) #endif #ifdef CONFIG_8xx #include <asm/8xx_immap.h> #include <asm/mpc8xx.h> -#define immr_map(member) \ -({ \ - u32 offset = offsetof(immap_t, member); \ - void *addr = ioremap (IMAP_ADDR + offset, \ - sizeof( ((immap_t*)0)->member)); \ - addr; \ -}) - -#define immr_map_size(member, size) \ -({ \ - u32 offset = offsetof(immap_t, member); \ - void *addr = ioremap (IMAP_ADDR + offset, size); \ - addr; \ -}) +extern immap_t __iomem *mpc8xx_immr; -#define immr_unmap(addr) iounmap(addr) +#define immr_map(member) (&mpc8xx_immr->member) +#define immr_map_size(member, size) (&mpc8xx_immr->member) +#define immr_unmap(addr) do {} while (0) #endif static inline int uart_baudrate(void) diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h new file mode 100644 index 000000000000..f7b21ee302b4 --- /dev/null +++ b/include/asm-powerpc/highmem.h @@ -0,0 +1,135 @@ +/* + * highmem.h: virtual kernel memory mappings for high memory + * + * PowerPC version, stolen from the i386 version. + * + * Used in CONFIG_HIGHMEM systems for memory pages which + * are not addressable by direct kernel virtual addresses. + * + * Copyright (C) 1999 Gerhard Wichert, Siemens AG + * Gerhard.Wichert@pdb.siemens.de + * + * + * Redesigned the x86 32-bit VM architecture to deal with + * up to 16 Terrabyte physical memory. With current x86 CPUs + * we now support up to 64 Gigabytes physical RAM. + * + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> + */ + +#ifndef _ASM_HIGHMEM_H +#define _ASM_HIGHMEM_H + +#ifdef __KERNEL__ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <asm/kmap_types.h> +#include <asm/tlbflush.h> +#include <asm/page.h> + +/* undef for production */ +#define HIGHMEM_DEBUG 1 + +extern pte_t *kmap_pte; +extern pgprot_t kmap_prot; +extern pte_t *pkmap_page_table; + +/* + * Right now we initialize only a single pte table. It can be extended + * easily, subsequent pte tables have to be allocated in one physical + * chunk of RAM. + */ +#define PKMAP_BASE CONFIG_HIGHMEM_START +#define LAST_PKMAP (1 << PTE_SHIFT) +#define LAST_PKMAP_MASK (LAST_PKMAP-1) +#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) + +#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) + +extern void *kmap_high(struct page *page); +extern void kunmap_high(struct page *page); + +static inline void *kmap(struct page *page) +{ + might_sleep(); + if (!PageHighMem(page)) + return page_address(page); + return kmap_high(page); +} + +static inline void kunmap(struct page *page) +{ + BUG_ON(in_interrupt()); + if (!PageHighMem(page)) + return; + kunmap_high(page); +} + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need + * it. + */ +static inline void *kmap_atomic(struct page *page, enum km_type type) +{ + unsigned int idx; + unsigned long vaddr; + + /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ + pagefault_disable(); + if (!PageHighMem(page)) + return page_address(page); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; +#ifdef HIGHMEM_DEBUG + BUG_ON(!pte_none(*(kmap_pte+idx))); +#endif + set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); + flush_tlb_page(NULL, vaddr); + + return (void*) vaddr; +} + +static inline void kunmap_atomic(void *kvaddr, enum km_type type) +{ +#ifdef HIGHMEM_DEBUG + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < KMAP_FIX_BEGIN) { // FIXME + pagefault_enable(); + return; + } + + BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(&init_mm, vaddr, kmap_pte+idx); + flush_tlb_page(NULL, vaddr); +#endif + pagefault_enable(); +} + +static inline struct page *kmap_atomic_to_page(void *ptr) +{ + unsigned long idx, vaddr = (unsigned long) ptr; + + if (vaddr < KMAP_FIX_BEGIN) + return virt_to_page(ptr); + + idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; + return pte_page(kmap_pte[idx]); +} + +#define flush_cache_kmaps() flush_cache_all() + +#endif /* __KERNEL__ */ + +#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-powerpc/hydra.h b/include/asm-powerpc/hydra.h new file mode 100644 index 000000000000..1ad4eed07fbe --- /dev/null +++ b/include/asm-powerpc/hydra.h @@ -0,0 +1,102 @@ +/* + * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * Macintosh Technology in the Common Hardware Reference Platform + * Apple Computer, Inc. + * + * © Copyright 1995 Apple Computer, Inc. All rights reserved. + * + * It's available online from http://chrp.apple.com/MacTech.pdf. + * You can obtain paper copies of this book from computer bookstores or by + * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San + * Francisco, CA 94104. Reference ISBN 1-55860-393-X. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _ASMPPC_HYDRA_H +#define _ASMPPC_HYDRA_H + +#ifdef __KERNEL__ + +struct Hydra { + /* DBDMA Controller Register Space */ + char Pad1[0x30]; + u_int CachePD; + u_int IDs; + u_int Feature_Control; + char Pad2[0x7fc4]; + /* DBDMA Channel Register Space */ + char SCSI_DMA[0x100]; + char Pad3[0x300]; + char SCCA_Tx_DMA[0x100]; + char SCCA_Rx_DMA[0x100]; + char SCCB_Tx_DMA[0x100]; + char SCCB_Rx_DMA[0x100]; + char Pad4[0x7800]; + /* Device Register Space */ + char SCSI[0x1000]; + char ADB[0x1000]; + char SCC_Legacy[0x1000]; + char SCC[0x1000]; + char Pad9[0x2000]; + char VIA[0x2000]; + char Pad10[0x28000]; + char OpenPIC[0x40000]; +}; + +extern volatile struct Hydra __iomem *Hydra; + + + /* + * Feature Control Register + */ + +#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ +#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ +#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ +#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ +#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ +#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ +#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ +#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ +#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ + + + /* + * OpenPIC Interrupt Sources + */ + +#define HYDRA_INT_SIO 0 +#define HYDRA_INT_SCSI_DMA 1 +#define HYDRA_INT_SCCA_TX_DMA 2 +#define HYDRA_INT_SCCA_RX_DMA 3 +#define HYDRA_INT_SCCB_TX_DMA 4 +#define HYDRA_INT_SCCB_RX_DMA 5 +#define HYDRA_INT_SCSI 6 +#define HYDRA_INT_SCCA 7 +#define HYDRA_INT_SCCB 8 +#define HYDRA_INT_VIA 9 +#define HYDRA_INT_ADB 10 +#define HYDRA_INT_ADB_NMI 11 +#define HYDRA_INT_EXT1 12 /* PCI IRQW */ +#define HYDRA_INT_EXT2 13 /* PCI IRQX */ +#define HYDRA_INT_EXT3 14 /* PCI IRQY */ +#define HYDRA_INT_EXT4 15 /* PCI IRQZ */ +#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ +#define HYDRA_INT_EXT6 17 /* IDE Secondary */ +#define HYDRA_INT_EXT7 18 /* Power Off Request */ +#define HYDRA_INT_SPARE 19 + +extern int hydra_init(void); +extern void macio_adb_init(void); + +#endif /* __KERNEL__ */ + +#endif /* _ASMPPC_HYDRA_H */ diff --git a/include/asm-powerpc/ide.h b/include/asm-powerpc/ide.h index 0f66f0f82c32..1644e44c8757 100644 --- a/include/asm-powerpc/ide.h +++ b/include/asm-powerpc/ide.h @@ -67,7 +67,7 @@ static __inline__ unsigned long ide_default_io_base(int index) #define ide_init_default_irq(base) ide_default_irq(base) #endif -#if (defined CONFIG_APUS || defined CONFIG_BLK_DEV_MPC8xx_IDE ) +#ifdef CONFIG_BLK_DEV_MPC8xx_IDE #define IDE_ARCH_ACK_INTR 1 #define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1) #endif diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h index 59b9e07b8e99..0ad4e653d464 100644 --- a/include/asm-powerpc/immap_86xx.h +++ b/include/asm-powerpc/immap_86xx.h @@ -1,124 +1,135 @@ -/* +/** * MPC86xx Internal Memory Map * - * Author: Jeff Brown + * Authors: Jeff Brown + * Timur Tabi <timur@freescale.com> * - * Copyright 2004 Freescale Semiconductor, Inc + * Copyright 2004,2007 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * + * This header file defines structures for various 86xx SOC devices that are + * used by multiple source files. */ #ifndef __ASM_POWERPC_IMMAP_86XX_H__ #define __ASM_POWERPC_IMMAP_86XX_H__ #ifdef __KERNEL__ -/* Eventually this should define all the IO block registers in 86xx */ +/* Global Utility Registers */ +struct ccsr_guts { + __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ + __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ + __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ + __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ + __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ + u8 res1[0x20 - 0x14]; + __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ + u8 res2[0x30 - 0x24]; + __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ + u8 res3[0x40 - 0x34]; + __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ + u8 res4[0x50 - 0x44]; + __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ + u8 res5[0x60 - 0x54]; + __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ + u8 res6[0x70 - 0x64]; + __be32 devdisr; /* 0x.0070 - Device Disable Control */ + __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ + u8 res7[0x80 - 0x78]; + __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ + u8 res8[0x90 - 0x84]; + __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ + __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ + u8 res9[0xA0 - 0x98]; + __be32 pvr; /* 0x.00a0 - Processor Version Register */ + __be32 svr; /* 0x.00a4 - System Version Register */ + u8 res10[0xB0 - 0xA8]; + __be32 rstcr; /* 0x.00b0 - Reset Control Register */ + u8 res11[0xC0 - 0xB4]; + __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */ + u8 res12[0x800 - 0xC4]; + __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ + u8 res13[0x900 - 0x804]; + __be32 ircr; /* 0x.0900 - Infrared Control Register */ + u8 res14[0x908 - 0x904]; + __be32 dmacr; /* 0x.0908 - DMA Control Register */ + u8 res15[0x914 - 0x90C]; + __be32 elbccr; /* 0x.0914 - eLBC Control Register */ + u8 res16[0xB20 - 0x918]; + __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ + __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ + __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ + u8 res17[0xE00 - 0xB2C]; + __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ + u8 res18[0xE10 - 0xE04]; + __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ + u8 res19[0xE20 - 0xE14]; + __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ + u8 res20[0xF04 - 0xE24]; + __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ + __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ + u8 res21[0xF40 - 0xF0C]; + __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ + __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ +} __attribute__ ((packed)); -/* PCI Registers */ -typedef struct ccsr_pci { - uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ - uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ - uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ - uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ - char res2[4]; - uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ - char res3[12]; - uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ - uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ - char res4[4]; - uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ - char res5[12]; - uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ - uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ - char res6[4]; - uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ - char res7[12]; - uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ - uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ - char res8[4]; - uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ - char res9[12]; - uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ - uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ - char res10[4]; - uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ - char res11[268]; - uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ - char res12[4]; - uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ - char res13[12]; - uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ - char res14[4]; - uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ - char res15[12]; - uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ - char res16[4]; - uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ - char res17[4]; - uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ - char res18[12]; - uint err_dr; /* 0x.e00 - PCI Error Detect Register */ - uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ - uint err_en; /* 0x.e08 - PCI Error Enable Register */ - uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ - uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ - uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ - uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ - uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ - uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ - uint pci_timr; /* 0x.e24 - PCI Timer Register */ - char res19[472]; -} ccsr_pci_t; +#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ +#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ -/* Global Utility Registers */ -typedef struct ccsr_guts { - uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ - uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - char res1[12]; - uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ - char res2[12]; - uint gpiocr; /* 0x.0030 - GPIO Control Register */ - char res3[12]; - uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ - char res4[12]; - uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ - char res5[12]; - uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - char res6[12]; - uint devdisr; /* 0x.0070 - Device Disable Control */ - char res7[12]; - uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - char res8[12]; - uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - char res9[12]; - uint pvr; /* 0x.00a0 - Processor Version Register */ - uint svr; /* 0x.00a4 - System Version Register */ - char res10[3416]; - uint clkocr; /* 0x.0e00 - Clock Out Select Register */ - char res11[12]; - uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ - char res12[12]; - uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - char res13[61916]; -} ccsr_guts_t; +/* + * Set the DMACR register in the GUTS + * + * The DMACR register determines the source of initiated transfers for each + * channel on each DMA controller. Rather than have a bunch of repetitive + * macros for the bit patterns, we just have a function that calculates + * them. + * + * guts: Pointer to GUTS structure + * co: The DMA controller (1 or 2) + * ch: The channel on the DMA controller (0, 1, 2, or 3) + * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) + */ +static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, + unsigned int co, unsigned int ch, unsigned int device) +{ + unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); + + clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); +} + +#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 +#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ +#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ +#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ +#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ +#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ +#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ +#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ +#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ +#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ +#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ +#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ +#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 +#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 +#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 +#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 + +#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 +#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 +#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 +#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 +#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 +#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ + (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) +#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 +#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 +#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) +#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF +#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/immap_cpm2.h b/include/asm-powerpc/immap_cpm2.h new file mode 100644 index 000000000000..4080bab0468c --- /dev/null +++ b/include/asm-powerpc/immap_cpm2.h @@ -0,0 +1,650 @@ +/* + * CPM2 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * + * The Internal Memory Map for devices with CPM2 on them. This + * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, + * 8560). + */ +#ifdef __KERNEL__ +#ifndef __IMMAP_CPM2__ +#define __IMMAP_CPM2__ + +#include <linux/types.h> + +/* System configuration registers. +*/ +typedef struct sys_82xx_conf { + u32 sc_siumcr; + u32 sc_sypcr; + u8 res1[6]; + u16 sc_swsr; + u8 res2[20]; + u32 sc_bcr; + u8 sc_ppc_acr; + u8 res3[3]; + u32 sc_ppc_alrh; + u32 sc_ppc_alrl; + u8 sc_lcl_acr; + u8 res4[3]; + u32 sc_lcl_alrh; + u32 sc_lcl_alrl; + u32 sc_tescr1; + u32 sc_tescr2; + u32 sc_ltescr1; + u32 sc_ltescr2; + u32 sc_pdtea; + u8 sc_pdtem; + u8 res5[3]; + u32 sc_ldtea; + u8 sc_ldtem; + u8 res6[163]; +} sysconf_82xx_cpm2_t; + +typedef struct sys_85xx_conf { + u32 sc_cear; + u16 sc_ceer; + u16 sc_cemr; + u8 res1[70]; + u32 sc_smaer; + u8 res2[4]; + u32 sc_smevr; + u32 sc_smctr; + u32 sc_lmaer; + u8 res3[4]; + u32 sc_lmevr; + u32 sc_lmctr; + u8 res4[144]; +} sysconf_85xx_cpm2_t; + +typedef union sys_conf { + sysconf_82xx_cpm2_t siu_82xx; + sysconf_85xx_cpm2_t siu_85xx; +} sysconf_cpm2_t; + + + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + u32 memc_br0; + u32 memc_or0; + u32 memc_br1; + u32 memc_or1; + u32 memc_br2; + u32 memc_or2; + u32 memc_br3; + u32 memc_or3; + u32 memc_br4; + u32 memc_or4; + u32 memc_br5; + u32 memc_or5; + u32 memc_br6; + u32 memc_or6; + u32 memc_br7; + u32 memc_or7; + u32 memc_br8; + u32 memc_or8; + u32 memc_br9; + u32 memc_or9; + u32 memc_br10; + u32 memc_or10; + u32 memc_br11; + u32 memc_or11; + u8 res1[8]; + u32 memc_mar; + u8 res2[4]; + u32 memc_mamr; + u32 memc_mbmr; + u32 memc_mcmr; + u8 res3[8]; + u16 memc_mptpr; + u8 res4[2]; + u32 memc_mdr; + u8 res5[4]; + u32 memc_psdmr; + u32 memc_lsdmr; + u8 memc_purt; + u8 res6[3]; + u8 memc_psrt; + u8 res7[3]; + u8 memc_lurt; + u8 res8[3]; + u8 memc_lsrt; + u8 res9[3]; + u32 memc_immr; + u32 memc_pcibr0; + u32 memc_pcibr1; + u8 res10[16]; + u32 memc_pcimsk0; + u32 memc_pcimsk1; + u8 res11[52]; +} memctl_cpm2_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + u8 res1[32]; + u16 sit_tmcntsc; + u8 res2[2]; + u32 sit_tmcnt; + u8 res3[4]; + u32 sit_tmcntal; + u8 res4[16]; + u16 sit_piscr; + u8 res5[2]; + u32 sit_pitc; + u32 sit_pitr; + u8 res6[94]; + u8 res7[390]; +} sit_cpm2_t; + +#define PISCR_PIRQ_MASK ((u16)0xff00) +#define PISCR_PS ((u16)0x0080) +#define PISCR_PIE ((u16)0x0004) +#define PISCR_PTF ((u16)0x0002) +#define PISCR_PTE ((u16)0x0001) + +/* PCI Controller. +*/ +typedef struct pci_ctlr { + u32 pci_omisr; + u32 pci_omimr; + u8 res1[8]; + u32 pci_ifqpr; + u32 pci_ofqpr; + u8 res2[8]; + u32 pci_imr0; + u32 pci_imr1; + u32 pci_omr0; + u32 pci_omr1; + u32 pci_odr; + u8 res3[4]; + u32 pci_idr; + u8 res4[20]; + u32 pci_imisr; + u32 pci_imimr; + u8 res5[24]; + u32 pci_ifhpr; + u8 res6[4]; + u32 pci_iftpr; + u8 res7[4]; + u32 pci_iphpr; + u8 res8[4]; + u32 pci_iptpr; + u8 res9[4]; + u32 pci_ofhpr; + u8 res10[4]; + u32 pci_oftpr; + u8 res11[4]; + u32 pci_ophpr; + u8 res12[4]; + u32 pci_optpr; + u8 res13[8]; + u32 pci_mucr; + u8 res14[8]; + u32 pci_qbar; + u8 res15[12]; + u32 pci_dmamr0; + u32 pci_dmasr0; + u32 pci_dmacdar0; + u8 res16[4]; + u32 pci_dmasar0; + u8 res17[4]; + u32 pci_dmadar0; + u8 res18[4]; + u32 pci_dmabcr0; + u32 pci_dmandar0; + u8 res19[86]; + u32 pci_dmamr1; + u32 pci_dmasr1; + u32 pci_dmacdar1; + u8 res20[4]; + u32 pci_dmasar1; + u8 res21[4]; + u32 pci_dmadar1; + u8 res22[4]; + u32 pci_dmabcr1; + u32 pci_dmandar1; + u8 res23[88]; + u32 pci_dmamr2; + u32 pci_dmasr2; + u32 pci_dmacdar2; + u8 res24[4]; + u32 pci_dmasar2; + u8 res25[4]; + u32 pci_dmadar2; + u8 res26[4]; + u32 pci_dmabcr2; + u32 pci_dmandar2; + u8 res27[88]; + u32 pci_dmamr3; + u32 pci_dmasr3; + u32 pci_dmacdar3; + u8 res28[4]; + u32 pci_dmasar3; + u8 res29[4]; + u32 pci_dmadar3; + u8 res30[4]; + u32 pci_dmabcr3; + u32 pci_dmandar3; + u8 res31[344]; + u32 pci_potar0; + u8 res32[4]; + u32 pci_pobar0; + u8 res33[4]; + u32 pci_pocmr0; + u8 res34[4]; + u32 pci_potar1; + u8 res35[4]; + u32 pci_pobar1; + u8 res36[4]; + u32 pci_pocmr1; + u8 res37[4]; + u32 pci_potar2; + u8 res38[4]; + u32 pci_pobar2; + u8 res39[4]; + u32 pci_pocmr2; + u8 res40[50]; + u32 pci_ptcr; + u32 pci_gpcr; + u32 pci_gcr; + u32 pci_esr; + u32 pci_emr; + u32 pci_ecr; + u32 pci_eacr; + u8 res41[4]; + u32 pci_edcr; + u8 res42[4]; + u32 pci_eccr; + u8 res43[44]; + u32 pci_pitar1; + u8 res44[4]; + u32 pci_pibar1; + u8 res45[4]; + u32 pci_picmr1; + u8 res46[4]; + u32 pci_pitar0; + u8 res47[4]; + u32 pci_pibar0; + u8 res48[4]; + u32 pci_picmr0; + u8 res49[4]; + u32 pci_cfg_addr; + u32 pci_cfg_data; + u32 pci_int_ack; + u8 res50[756]; +} pci_cpm2_t; + +/* Interrupt Controller. +*/ +typedef struct interrupt_controller { + u16 ic_sicr; + u8 res1[2]; + u32 ic_sivec; + u32 ic_sipnrh; + u32 ic_sipnrl; + u32 ic_siprr; + u32 ic_scprrh; + u32 ic_scprrl; + u32 ic_simrh; + u32 ic_simrl; + u32 ic_siexr; + u8 res2[88]; +} intctl_cpm2_t; + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + u32 car_sccr; + u8 res1[4]; + u32 car_scmr; + u8 res2[4]; + u32 car_rsr; + u32 car_rmr; + u8 res[104]; +} car_cpm2_t; + +/* Input/Output Port control/status registers. + * Names consistent with processor manual, although they are different + * from the original 8xx names....... + */ +typedef struct io_port { + u32 iop_pdira; + u32 iop_ppara; + u32 iop_psora; + u32 iop_podra; + u32 iop_pdata; + u8 res1[12]; + u32 iop_pdirb; + u32 iop_pparb; + u32 iop_psorb; + u32 iop_podrb; + u32 iop_pdatb; + u8 res2[12]; + u32 iop_pdirc; + u32 iop_pparc; + u32 iop_psorc; + u32 iop_podrc; + u32 iop_pdatc; + u8 res3[12]; + u32 iop_pdird; + u32 iop_ppard; + u32 iop_psord; + u32 iop_podrd; + u32 iop_pdatd; + u8 res4[12]; +} iop_cpm2_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + u8 cpmt_tgcr1; + u8 res1[3]; + u8 cpmt_tgcr2; + u8 res2[11]; + u16 cpmt_tmr1; + u16 cpmt_tmr2; + u16 cpmt_trr1; + u16 cpmt_trr2; + u16 cpmt_tcr1; + u16 cpmt_tcr2; + u16 cpmt_tcn1; + u16 cpmt_tcn2; + u16 cpmt_tmr3; + u16 cpmt_tmr4; + u16 cpmt_trr3; + u16 cpmt_trr4; + u16 cpmt_tcr3; + u16 cpmt_tcr4; + u16 cpmt_tcn3; + u16 cpmt_tcn4; + u16 cpmt_ter1; + u16 cpmt_ter2; + u16 cpmt_ter3; + u16 cpmt_ter4; + u8 res3[584]; +} cpmtimer_cpm2_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + u8 res0[24]; + u8 sdma_sdsr; + u8 res1[3]; + u8 sdma_sdmr; + u8 res2[3]; + u8 sdma_idsr1; + u8 res3[3]; + u8 sdma_idmr1; + u8 res4[3]; + u8 sdma_idsr2; + u8 res5[3]; + u8 sdma_idmr2; + u8 res6[3]; + u8 sdma_idsr3; + u8 res7[3]; + u8 sdma_idmr3; + u8 res8[3]; + u8 sdma_idsr4; + u8 res9[3]; + u8 sdma_idmr4; + u8 res10[707]; +} sdma_cpm2_t; + +/* Fast controllers +*/ +typedef struct fcc { + u32 fcc_gfmr; + u32 fcc_fpsmr; + u16 fcc_ftodr; + u8 res1[2]; + u16 fcc_fdsr; + u8 res2[2]; + u16 fcc_fcce; + u8 res3[2]; + u16 fcc_fccm; + u8 res4[2]; + u8 fcc_fccs; + u8 res5[3]; + u8 fcc_ftirr_phy[4]; +} fcc_t; + +/* Fast controllers continued + */ +typedef struct fcc_c { + u32 fcc_firper; + u32 fcc_firer; + u32 fcc_firsr_hi; + u32 fcc_firsr_lo; + u8 fcc_gfemr; + u8 res1[15]; +} fcc_c_t; + +/* TC Layer + */ +typedef struct tclayer { + u16 tc_tcmode; + u16 tc_cdsmr; + u16 tc_tcer; + u16 tc_rcc; + u16 tc_tcmr; + u16 tc_fcc; + u16 tc_ccc; + u16 tc_icc; + u16 tc_tcc; + u16 tc_ecc; + u8 res1[12]; +} tclayer_t; + + +/* I2C +*/ +typedef struct i2c { + u8 i2c_i2mod; + u8 res1[3]; + u8 i2c_i2add; + u8 res2[3]; + u8 i2c_i2brg; + u8 res3[3]; + u8 i2c_i2com; + u8 res4[3]; + u8 i2c_i2cer; + u8 res5[3]; + u8 i2c_i2cmr; + u8 res6[331]; +} i2c_cpm2_t; + +typedef struct scc { /* Serial communication channels */ + u32 scc_gsmrl; + u32 scc_gsmrh; + u16 scc_psmr; + u8 res1[2]; + u16 scc_todr; + u16 scc_dsr; + u16 scc_scce; + u8 res2[2]; + u16 scc_sccm; + u8 res3; + u8 scc_sccs; + u8 res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + u8 res1[2]; + u16 smc_smcmr; + u8 res2[2]; + u8 smc_smce; + u8 res3[3]; + u8 smc_smcm; + u8 res4[5]; +} smc_t; + +/* Serial Peripheral Interface. +*/ +typedef struct spi_ctrl { + u16 spi_spmode; + u8 res1[4]; + u8 spi_spie; + u8 res2[3]; + u8 spi_spim; + u8 res3[2]; + u8 spi_spcom; + u8 res4[82]; +} spictl_cpm2_t; + +/* CPM Mux. +*/ +typedef struct cpmux { + u8 cmx_si1cr; + u8 res1; + u8 cmx_si2cr; + u8 res2; + u32 cmx_fcr; + u32 cmx_scr; + u8 cmx_smr; + u8 res3; + u16 cmx_uar; + u8 res4[16]; +} cpmux_t; + +/* SIRAM control +*/ +typedef struct siram { + u16 si_amr; + u16 si_bmr; + u16 si_cmr; + u16 si_dmr; + u8 si_gmr; + u8 res1; + u8 si_cmdr; + u8 res2; + u8 si_str; + u8 res3; + u16 si_rsr; +} siramctl_t; + +typedef struct mcc { + u16 mcc_mcce; + u8 res1[2]; + u16 mcc_mccm; + u8 res2[2]; + u8 mcc_mccf; + u8 res3[7]; +} mcc_t; + +typedef struct comm_proc { + u32 cp_cpcr; + u32 cp_rccr; + u8 res1[14]; + u16 cp_rter; + u8 res2[2]; + u16 cp_rtmr; + u16 cp_rtscr; + u8 res3[2]; + u32 cp_rtsr; + u8 res4[12]; +} cpm_cpm2_t; + +/* USB Controller. +*/ +typedef struct usb_ctlr { + u8 usb_usmod; + u8 usb_usadr; + u8 usb_uscom; + u8 res1[1]; + u16 usb_usep1; + u16 usb_usep2; + u16 usb_usep3; + u16 usb_usep4; + u8 res2[4]; + u16 usb_usber; + u8 res3[2]; + u16 usb_usbmr; + u8 usb_usbs; + u8 res4[7]; +} usb_cpm2_t; + +/* ...and the whole thing wrapped up.... +*/ + +typedef struct immap { + /* Some references are into the unique and known dpram spaces, + * others are from the generic base. + */ +#define im_dprambase im_dpram1 + u8 im_dpram1[16*1024]; + u8 res1[16*1024]; + u8 im_dpram2[4*1024]; + u8 res2[8*1024]; + u8 im_dpram3[4*1024]; + u8 res3[16*1024]; + + sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ + memctl_cpm2_t im_memctl; /* Memory Controller */ + sit_cpm2_t im_sit; /* System Integration Timers */ + pci_cpm2_t im_pci; /* PCI Controller */ + intctl_cpm2_t im_intctl; /* Interrupt Controller */ + car_cpm2_t im_clkrst; /* Clocks and reset */ + iop_cpm2_t im_ioport; /* IO Port control/status */ + cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ + sdma_cpm2_t im_sdma; /* SDMA control/status */ + + fcc_t im_fcc[3]; /* Three FCCs */ + u8 res4z[32]; + fcc_c_t im_fcc_c[3]; /* Continued FCCs */ + + u8 res4[32]; + + tclayer_t im_tclayer[8]; /* Eight TCLayers */ + u16 tc_tcgsr; + u16 tc_tcger; + + /* First set of baud rate generators. + */ + u8 res[236]; + u32 im_brgc5; + u32 im_brgc6; + u32 im_brgc7; + u32 im_brgc8; + + u8 res5[608]; + + i2c_cpm2_t im_i2c; /* I2C control/status */ + cpm_cpm2_t im_cpm; /* Communication processor */ + + /* Second set of baud rate generators. + */ + u32 im_brgc1; + u32 im_brgc2; + u32 im_brgc3; + u32 im_brgc4; + + scc_t im_scc[4]; /* Four SCCs */ + smc_t im_smc[2]; /* Couple of SMCs */ + spictl_cpm2_t im_spi; /* A SPI */ + cpmux_t im_cpmux; /* CPM clock route mux */ + siramctl_t im_siramctl1; /* First SI RAM Control */ + mcc_t im_mcc1; /* First MCC */ + siramctl_t im_siramctl2; /* Second SI RAM Control */ + mcc_t im_mcc2; /* Second MCC */ + usb_cpm2_t im_usb; /* USB Controller */ + + u8 res6[1153]; + + u16 im_si1txram[256]; + u8 res7[512]; + u16 im_si1rxram[256]; + u8 res8[512]; + u16 im_si2txram[256]; + u8 res9[512]; + u16 im_si2rxram[256]; + u8 res10[512]; + u8 res11[4096]; +} cpm2_map_t; + +extern cpm2_map_t __iomem *cpm2_immr; + +#endif /* __IMMAP_CPM2__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h index 1020b7fc0129..aba9806b31c9 100644 --- a/include/asm-powerpc/immap_qe.h +++ b/include/asm-powerpc/immap_qe.h @@ -86,8 +86,9 @@ struct cp_qe { __be16 ceexe4; /* QE external request 4 event register */ u8 res11[0x2]; __be16 ceexm4; /* QE external request 4 mask register */ - u8 res12[0x2]; - u8 res13[0x280]; + u8 res12[0x3A]; + __be32 ceurnr; /* QE microcode revision number register */ + u8 res13[0x244]; } __attribute__ ((packed)); /* QE Multiplexer */ @@ -96,10 +97,7 @@ struct qe_mux { __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ - __be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ - __be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ - __be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ - __be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ + __be32 cmxucr[4]; /* CMX UCCx clock route registers */ __be32 cmxupcr; /* CMX UPC clock route register */ u8 res0[0x1C]; } __attribute__ ((packed)); @@ -260,7 +258,6 @@ struct ucc_slow { __be16 utpt; u8 res4[0x52]; u8 guemr; /* UCC general extended mode register */ - u8 res5[0x200 - 0x091]; } __attribute__ ((packed)); /* QE UCC Fast */ @@ -293,21 +290,13 @@ struct ucc_fast { __be32 urtry; /* UCC retry counter register */ u8 res8[0x4C]; u8 guemr; /* UCC general extended mode register */ - u8 res9[0x100 - 0x091]; -} __attribute__ ((packed)); - -/* QE UCC */ -struct ucc_common { - u8 res1[0x90]; - u8 guemr; - u8 res2[0x200 - 0x091]; } __attribute__ ((packed)); struct ucc { union { struct ucc_slow slow; struct ucc_fast fast; - struct ucc_common common; + u8 res[0x200]; /* UCC blocks are 512 bytes each */ }; } __attribute__ ((packed)); @@ -406,7 +395,7 @@ struct dbg { /* RISC Special Registers (Trap and Breakpoint) */ struct rsp { - u8 fixme[0x100]; + u32 reg[0x40]; /* 64 32-bit registers */ } __attribute__ ((packed)); struct qe_immap { @@ -435,11 +424,13 @@ struct qe_immap { u8 res13[0x600]; struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ struct sdma sdma; /* SDMA */ - struct dbg dbg; /* Debug Space */ - struct rsp rsp[0x2]; /* RISC Special Registers + struct dbg dbg; /* 0x104080 - 0x1040FF + Debug Space */ + struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF + RISC Special Registers (Trap and Breakpoint) */ - u8 res14[0x300]; - u8 res15[0x3A00]; + u8 res14[0x300]; /* 0x104300 - 0x1045FF */ + u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ u8 res16[0x8000]; /* 0x108000 - 0x110000 */ u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ @@ -450,7 +441,7 @@ struct qe_immap { extern struct qe_immap *qe_immr; extern phys_addr_t get_qe_base(void); -static inline unsigned long immrbar_virt_to_phys(volatile void * address) +static inline unsigned long immrbar_virt_to_phys(void *address) { if ( ((u32)address >= (u32)qe_immr) && ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) ) diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h index bb8d965f96c6..affba7052fb6 100644 --- a/include/asm-powerpc/io.h +++ b/include/asm-powerpc/io.h @@ -86,7 +86,7 @@ extern unsigned long pci_dram_offset; */ #ifdef CONFIG_PPC64 -#define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0) +#define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) #else #define IO_SET_SYNC_FLAG() #endif @@ -734,6 +734,32 @@ static inline void * bus_to_virt(unsigned long address) #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#ifdef __powerpc64__ +#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) +#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) +#endif + +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_IO_H */ diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 0485c53db2b5..1392db456523 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -124,6 +124,9 @@ struct irq_host { struct irq_host_ops *ops; void *host_data; irq_hw_number_t inval_irq; + + /* Optional device node pointer */ + struct device_node *of_node; }; /* The main irq map itself is an array of NR_IRQ entries containing the @@ -142,7 +145,7 @@ extern irq_hw_number_t virq_to_hw(unsigned int virq); /** * irq_alloc_host - Allocate a new irq_host data structure - * @node: device-tree node of the interrupt controller + * @of_node: optional device-tree node of the interrupt controller * @revmap_type: type of reverse mapping to use * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map * @ops: map/unmap host callbacks @@ -156,7 +159,8 @@ extern irq_hw_number_t virq_to_hw(unsigned int virq); * later during boot automatically (the reverse mapping will use the slow path * until that happens). */ -extern struct irq_host *irq_alloc_host(unsigned int revmap_type, +extern struct irq_host *irq_alloc_host(struct device_node *of_node, + unsigned int revmap_type, unsigned int revmap_arg, struct irq_host_ops *ops, irq_hw_number_t inval_irq); diff --git a/include/asm-powerpc/iseries/hv_call_event.h b/include/asm-powerpc/iseries/hv_call_event.h index 4cec4762076d..cc029d388e11 100644 --- a/include/asm-powerpc/iseries/hv_call_event.h +++ b/include/asm-powerpc/iseries/hv_call_event.h @@ -21,6 +21,9 @@ #ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H #define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H +#include <linux/types.h> +#include <linux/dma-mapping.h> + #include <asm/iseries/hv_call_sc.h> #include <asm/iseries/hv_types.h> #include <asm/abs_addr.h> @@ -113,6 +116,13 @@ static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp, eventData3, eventData4, eventData5); } +extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag); +extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle); +extern dma_addr_t iseries_hv_map(void *vaddr, size_t size, + enum dma_data_direction direction); +extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction); + static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event) { return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event)); diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h index 6e323a13ac30..c59ee7e4bed1 100644 --- a/include/asm-powerpc/iseries/iommu.h +++ b/include/asm-powerpc/iseries/iommu.h @@ -22,6 +22,7 @@ */ struct pci_dev; +struct vio_dev; struct device_node; struct iommu_table; @@ -34,4 +35,7 @@ extern void iommu_table_getparms_iSeries(unsigned long busno, unsigned char slotno, unsigned char virtbus, struct iommu_table *tbl); +extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev); +extern void iommu_vio_init(void); + #endif /* _ASM_POWERPC_ISERIES_IOMMU_H */ diff --git a/include/asm-powerpc/iseries/lpar_map.h b/include/asm-powerpc/iseries/lpar_map.h index 2ec384d66abb..5e9f3e128ee2 100644 --- a/include/asm-powerpc/iseries/lpar_map.h +++ b/include/asm-powerpc/iseries/lpar_map.h @@ -22,6 +22,8 @@ #include <asm/types.h> +#endif + /* * The iSeries hypervisor will set up mapping for one or more * ESID/VSID pairs (in SLB/segment registers) and will set up @@ -56,6 +58,7 @@ /* Hypervisor initially maps 32MB of the load area */ #define HvPagesToMap 8192 +#ifndef __ASSEMBLY__ struct LparMap { u64 xNumberEsids; // Number of ESID/VSID pairs u64 xNumberRanges; // Number of VA ranges to map diff --git a/include/asm-powerpc/iseries/vio.h b/include/asm-powerpc/iseries/vio.h index 7a95d296abd1..f9ac0d00b951 100644 --- a/include/asm-powerpc/iseries/vio.h +++ b/include/asm-powerpc/iseries/vio.h @@ -51,6 +51,116 @@ */ #define VIO_MAX_SUBTYPES 8 +#define VIOMAXBLOCKDMA 12 + +struct open_data { + u64 disk_size; + u16 max_disk; + u16 cylinders; + u16 tracks; + u16 sectors; + u16 bytes_per_sector; +}; + +struct rw_data { + u64 offset; + struct { + u32 token; + u32 reserved; + u64 len; + } dma_info[VIOMAXBLOCKDMA]; +}; + +struct vioblocklpevent { + struct HvLpEvent event; + u32 reserved; + u16 version; + u16 sub_result; + u16 disk; + u16 flags; + union { + struct open_data open_data; + struct rw_data rw_data; + u64 changed; + } u; +}; + +#define vioblockflags_ro 0x0001 + +enum vioblocksubtype { + vioblockopen = 0x0001, + vioblockclose = 0x0002, + vioblockread = 0x0003, + vioblockwrite = 0x0004, + vioblockflush = 0x0005, + vioblockcheck = 0x0007 +}; + +struct viocdlpevent { + struct HvLpEvent event; + u32 reserved; + u16 version; + u16 sub_result; + u16 disk; + u16 flags; + u32 token; + u64 offset; /* On open, max number of disks */ + u64 len; /* On open, size of the disk */ + u32 block_size; /* Only set on open */ + u32 media_size; /* Only set on open */ +}; + +enum viocdsubtype { + viocdopen = 0x0001, + viocdclose = 0x0002, + viocdread = 0x0003, + viocdwrite = 0x0004, + viocdlockdoor = 0x0005, + viocdgetinfo = 0x0006, + viocdcheck = 0x0007 +}; + +struct viotapelpevent { + struct HvLpEvent event; + u32 reserved; + u16 version; + u16 sub_type_result; + u16 tape; + u16 flags; + u32 token; + u64 len; + union { + struct { + u32 tape_op; + u32 count; + } op; + struct { + u32 type; + u32 resid; + u32 dsreg; + u32 gstat; + u32 erreg; + u32 file_no; + u32 block_no; + } get_status; + struct { + u32 block_no; + } get_pos; + } u; +}; + +enum viotapesubtype { + viotapeopen = 0x0001, + viotapeclose = 0x0002, + viotaperead = 0x0003, + viotapewrite = 0x0004, + viotapegetinfo = 0x0005, + viotapeop = 0x0006, + viotapegetpos = 0x0007, + viotapesetpos = 0x0008, + viotapegetstatus = 0x0009 +}; + /* * Each subtype can register a handler to process their events. * The handler must have this interface. @@ -68,6 +178,8 @@ extern void vio_set_hostlp(void); extern void *vio_get_event_buffer(int subtype); extern void vio_free_event_buffer(int subtype, void *buffer); +extern struct vio_dev *vio_create_viodasd(u32 unit); + extern HvLpIndex viopath_hostLp; extern HvLpIndex viopath_ourLp; @@ -150,8 +262,4 @@ enum viochar_rc { viochar_rc_ebusy = 1 }; -struct device; - -extern struct device *iSeries_vio_dev; - #endif /* _ASM_POWERPC_ISERIES_VIO_H */ diff --git a/include/asm-powerpc/kgdb.h b/include/asm-powerpc/kgdb.h new file mode 100644 index 000000000000..b617dac82969 --- /dev/null +++ b/include/asm-powerpc/kgdb.h @@ -0,0 +1,57 @@ +/* + * kgdb.h: Defines and declarations for serial line source level + * remote debugging of the Linux kernel using gdb. + * + * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) + * + * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + */ +#ifdef __KERNEL__ +#ifndef _PPC_KGDB_H +#define _PPC_KGDB_H + +#ifndef __ASSEMBLY__ + +/* Things specific to the gen550 backend. */ +struct uart_port; + +extern void gen550_progress(char *, unsigned short); +extern void gen550_kgdb_map_scc(void); +extern void gen550_init(int, struct uart_port *); + +/* Things specific to the pmac backend. */ +extern void zs_kgdb_hook(int tty_num); + +/* To init the kgdb engine. (called by serial hook)*/ +extern void set_debug_traps(void); + +/* To enter the debugger explicitly. */ +extern void breakpoint(void); + +/* For taking exceptions + * these are defined in traps.c + */ +extern int (*debugger)(struct pt_regs *regs); +extern int (*debugger_bpt)(struct pt_regs *regs); +extern int (*debugger_sstep)(struct pt_regs *regs); +extern int (*debugger_iabr_match)(struct pt_regs *regs); +extern int (*debugger_dabr_match)(struct pt_regs *regs); +extern void (*debugger_fault_handler)(struct pt_regs *regs); + +/* What we bring to the party */ +int kgdb_bpt(struct pt_regs *regs); +int kgdb_sstep(struct pt_regs *regs); +void kgdb(struct pt_regs *regs); +int kgdb_iabr_match(struct pt_regs *regs); +int kgdb_dabr_match(struct pt_regs *regs); + +/* + * external low-level support routines (ie macserial.c) + */ +extern void kgdb_interruptible(int); /* control interrupts from serial */ +extern void putDebugChar(char); /* write a single character */ +extern char getDebugChar(void); /* read and return a single char */ + +#endif /* !(__ASSEMBLY__) */ +#endif /* !(_PPC_KGDB_H) */ +#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h index 9537fda238b8..8b08b447d6f3 100644 --- a/include/asm-powerpc/kprobes.h +++ b/include/asm-powerpc/kprobes.h @@ -73,12 +73,10 @@ typedef unsigned int kprobe_opcode_t; } \ } -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)((func_descr_t *)pentry) #define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \ IS_TWI(instr) || IS_TDI(instr)) #else /* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */ -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)(pentry) #define is_trap(instr) (IS_TW(instr) || IS_TWI(instr)) #endif diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h index 0c5880f70225..b5f9f4c9c294 100644 --- a/include/asm-powerpc/lmb.h +++ b/include/asm-powerpc/lmb.h @@ -1,5 +1,5 @@ -#ifndef _PPC64_LMB_H -#define _PPC64_LMB_H +#ifndef _ASM_POWERPC_LMB_H +#define _ASM_POWERPC_LMB_H #ifdef __KERNEL__ /* @@ -77,4 +77,4 @@ lmb_end_pfn(struct lmb_region *type, unsigned long region_nr) } #endif /* __KERNEL__ */ -#endif /* _PPC64_LMB_H */ +#endif /* _ASM_POWERPC_LMB_H */ diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h index 71c6e7eb2a26..6968f4300dca 100644 --- a/include/asm-powerpc/machdep.h +++ b/include/asm-powerpc/machdep.h @@ -51,22 +51,22 @@ struct machdep_calls { #ifdef CONFIG_PPC64 void (*hpte_invalidate)(unsigned long slot, unsigned long va, - int psize, + int psize, int ssize, int local); long (*hpte_updatepp)(unsigned long slot, unsigned long newpp, unsigned long va, - int pize, + int psize, int ssize, int local); void (*hpte_updateboltedpp)(unsigned long newpp, unsigned long ea, - int psize); + int psize, int ssize); long (*hpte_insert)(unsigned long hpte_group, unsigned long va, unsigned long prpn, unsigned long rflags, unsigned long vflags, - int psize); + int psize, int ssize); long (*hpte_remove)(unsigned long hpte_group); void (*flush_hash_range)(unsigned long number, int local); @@ -99,7 +99,7 @@ struct machdep_calls { #endif /* CONFIG_PPC64 */ int (*probe)(void); - void (*setup_arch)(void); + void (*setup_arch)(void); /* Optional, may be NULL */ void (*init_early)(void); /* Optional, may be NULL. */ void (*show_cpuinfo)(struct seq_file *m); diff --git a/include/asm-powerpc/mmu-40x.h b/include/asm-powerpc/mmu-40x.h new file mode 100644 index 000000000000..7d37f77043ac --- /dev/null +++ b/include/asm-powerpc/mmu-40x.h @@ -0,0 +1,65 @@ +#ifndef _ASM_POWERPC_MMU_40X_H_ +#define _ASM_POWERPC_MMU_40X_H_ + +/* + * PPC40x support + */ + +#define PPC40X_TLB_SIZE 64 + +/* + * TLB entries are defined by a "high" tag portion and a "low" data + * portion. On all architectures, the data portion is 32-bits. + * + * TLB entries are managed entirely under software control by reading, + * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx + * instructions. + */ + +#define TLB_LO 1 +#define TLB_HI 0 + +#define TLB_DATA TLB_LO +#define TLB_TAG TLB_HI + +/* Tag portion */ + +#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_PAGESZ_MASK 0x00000380 +#define TLB_PAGESZ(x) (((x) & 0x7) << 7) +#define PAGESZ_1K 0 +#define PAGESZ_4K 1 +#define PAGESZ_16K 2 +#define PAGESZ_64K 3 +#define PAGESZ_256K 4 +#define PAGESZ_1M 5 +#define PAGESZ_4M 6 +#define PAGESZ_16M 7 +#define TLB_VALID 0x00000040 /* Entry is valid */ + +/* Data portion */ + +#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_PERM_MASK 0x00000300 +#define TLB_EX 0x00000200 /* Instruction execution allowed */ +#define TLB_WR 0x00000100 /* Writes permitted */ +#define TLB_ZSEL_MASK 0x000000F0 +#define TLB_ZSEL(x) (((x) & 0xF) << 4) +#define TLB_ATTR_MASK 0x0000000F +#define TLB_W 0x00000008 /* Caching is write-through */ +#define TLB_I 0x00000004 /* Caching is inhibited */ +#define TLB_M 0x00000002 /* Memory is coherent */ +#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ + +#ifndef __ASSEMBLY__ + +typedef unsigned long phys_addr_t; + +typedef struct { + unsigned long id; + unsigned long vdso_base; +} mm_context_t; + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_POWERPC_MMU_40X_H_ */ diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index 695962f02059..82328dec2b52 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -47,6 +47,8 @@ extern char initial_stab[]; /* Bits in the SLB VSID word */ #define SLB_VSID_SHIFT 12 +#define SLB_VSID_SHIFT_1T 24 +#define SLB_VSID_SSIZE_SHIFT 62 #define SLB_VSID_B ASM_CONST(0xc000000000000000) #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) @@ -66,6 +68,7 @@ extern char initial_stab[]; #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) #define SLBIE_C (0x08000000) +#define SLBIE_SSIZE_SHIFT 25 /* * Hash table @@ -77,7 +80,7 @@ extern char initial_stab[]; #define HPTE_V_AVPN_SHIFT 7 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) -#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN)) +#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80)) #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) @@ -164,16 +167,19 @@ struct mmu_psize_def #define MMU_SEGSIZE_256M 0 #define MMU_SEGSIZE_1T 1 + #ifndef __ASSEMBLY__ /* - * The current system page sizes + * The current system page and segment sizes */ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; extern int mmu_linear_psize; extern int mmu_virtual_psize; extern int mmu_vmalloc_psize; extern int mmu_io_psize; +extern int mmu_kernel_ssize; +extern int mmu_highuser_ssize; /* * If the processor supports 64k normal pages but not 64k cache @@ -195,13 +201,15 @@ extern int mmu_huge_psize; * This function sets the AVPN and L fields of the HPTE appropriately * for the page size */ -static inline unsigned long hpte_encode_v(unsigned long va, int psize) +static inline unsigned long hpte_encode_v(unsigned long va, int psize, + int ssize) { - unsigned long v = + unsigned long v; v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm); v <<= HPTE_V_AVPN_SHIFT; if (psize != MMU_PAGE_4K) v |= HPTE_V_LARGE; + v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; return v; } @@ -226,20 +234,40 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize) } /* - * This hashes a virtual address for a 256Mb segment only for now + * Build a VA given VSID, EA and segment size */ +static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid, + int ssize) +{ + if (ssize == MMU_SEGSIZE_256M) + return (vsid << 28) | (ea & 0xfffffffUL); + return (vsid << 40) | (ea & 0xffffffffffUL); +} -static inline unsigned long hpt_hash(unsigned long va, unsigned int shift) +/* + * This hashes a virtual address + */ + +static inline unsigned long hpt_hash(unsigned long va, unsigned int shift, + int ssize) { - return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift); + unsigned long hash, vsid; + + if (ssize == MMU_SEGSIZE_256M) { + hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift); + } else { + vsid = va >> 40; + hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift); + } + return hash & 0x7fffffffffUL; } extern int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid, pte_t *ptep, unsigned long trap, - unsigned int local); + unsigned int local, int ssize); extern int __hash_page_64K(unsigned long ea, unsigned long access, unsigned long vsid, pte_t *ptep, unsigned long trap, - unsigned int local); + unsigned int local, int ssize); struct mm_struct; extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); extern int hash_huge_page(struct mm_struct *mm, unsigned long access, @@ -248,7 +276,7 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access, extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, unsigned long pstart, unsigned long mode, - int psize); + int psize, int ssize); extern void htab_initialize(void); extern void htab_initialize_secondary(void); @@ -256,12 +284,14 @@ extern void hpte_init_native(void); extern void hpte_init_lpar(void); extern void hpte_init_iSeries(void); extern void hpte_init_beat(void); +extern void hpte_init_beat_v3(void); extern void stabs_alloc(void); extern void slb_initialize(void); extern void slb_flush_and_rebolt(void); extern void stab_initialize(unsigned long stab); +extern void slb_vmalloc_update(void); #endif /* __ASSEMBLY__ */ /* @@ -315,12 +345,17 @@ extern void stab_initialize(unsigned long stab); * which are used by the iSeries firmware. */ -#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */ -#define VSID_BITS 36 -#define VSID_MODULUS ((1UL<<VSID_BITS)-1) +#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */ +#define VSID_BITS_256M 36 +#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) -#define CONTEXT_BITS 19 -#define USER_ESID_BITS 16 +#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ +#define VSID_BITS_1T 24 +#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) + +#define CONTEXT_BITS 19 +#define USER_ESID_BITS 16 +#define USER_ESID_BITS_1T 4 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT)) @@ -334,17 +369,17 @@ extern void stab_initialize(unsigned long stab); * rx = scratch register (clobbered) * * - rt and rx must be different registers - * - The answer will end up in the low 36 bits of rt. The higher + * - The answer will end up in the low VSID_BITS bits of rt. The higher * bits may contain other garbage, so you may need to mask the * result. */ -#define ASM_VSID_SCRAMBLE(rt, rx) \ - lis rx,VSID_MULTIPLIER@h; \ - ori rx,rx,VSID_MULTIPLIER@l; \ +#define ASM_VSID_SCRAMBLE(rt, rx, size) \ + lis rx,VSID_MULTIPLIER_##size@h; \ + ori rx,rx,VSID_MULTIPLIER_##size@l; \ mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ \ - srdi rx,rt,VSID_BITS; \ - clrldi rt,rt,(64-VSID_BITS); \ + srdi rx,rt,VSID_BITS_##size; \ + clrldi rt,rt,(64-VSID_BITS_##size); \ add rt,rt,rx; /* add high and low bits */ \ /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ * 2^36-1+2^28-1. That in particular means that if r3 >= \ @@ -353,7 +388,7 @@ extern void stab_initialize(unsigned long stab); * doesn't, the answer is the low 36 bits of r3+1. So in all \ * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ addi rx,rt,1; \ - srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \ + srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ add rt,rt,rx @@ -375,37 +410,60 @@ typedef struct { } mm_context_t; -static inline unsigned long vsid_scramble(unsigned long protovsid) -{ #if 0 - /* The code below is equivalent to this function for arguments - * < 2^VSID_BITS, which is all this should ever be called - * with. However gcc is not clever enough to compute the - * modulus (2^n-1) without a second multiply. */ - return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); -#else /* 1 */ - unsigned long x; +/* + * The code below is equivalent to this function for arguments + * < 2^VSID_BITS, which is all this should ever be called + * with. However gcc is not clever enough to compute the + * modulus (2^n-1) without a second multiply. + */ +#define vsid_scrample(protovsid, size) \ + ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) - x = protovsid * VSID_MULTIPLIER; - x = (x >> VSID_BITS) + (x & VSID_MODULUS); - return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; +#else /* 1 */ +#define vsid_scramble(protovsid, size) \ + ({ \ + unsigned long x; \ + x = (protovsid) * VSID_MULTIPLIER_##size; \ + x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ + (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ + }) #endif /* 1 */ -} /* This is only valid for addresses >= KERNELBASE */ -static inline unsigned long get_kernel_vsid(unsigned long ea) +static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) { - return vsid_scramble(ea >> SID_SHIFT); + if (ssize == MMU_SEGSIZE_256M) + return vsid_scramble(ea >> SID_SHIFT, 256M); + return vsid_scramble(ea >> SID_SHIFT_1T, 1T); } -/* This is only valid for user addresses (which are below 2^41) */ -static inline unsigned long get_vsid(unsigned long context, unsigned long ea) +/* Returns the segment size indicator for a user address */ +static inline int user_segment_size(unsigned long addr) { - return vsid_scramble((context << USER_ESID_BITS) - | (ea >> SID_SHIFT)); + /* Use 1T segments if possible for addresses >= 1T */ + if (addr >= (1UL << SID_SHIFT_1T)) + return mmu_highuser_ssize; + return MMU_SEGSIZE_256M; } -#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS) +/* This is only valid for user addresses (which are below 2^44) */ +static inline unsigned long get_vsid(unsigned long context, unsigned long ea, + int ssize) +{ + if (ssize == MMU_SEGSIZE_256M) + return vsid_scramble((context << USER_ESID_BITS) + | (ea >> SID_SHIFT), 256M); + return vsid_scramble((context << USER_ESID_BITS_1T) + | (ea >> SID_SHIFT_1T), 1T); +} + +/* + * This is only used on legacy iSeries in lparmap.c, + * hence the 256MB segment assumption. + */ +#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \ + VSID_MODULUS_256M) #define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) /* Physical address used by some IO functions */ diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h index d44d211e7588..4c0e1b4f975c 100644 --- a/include/asm-powerpc/mmu.h +++ b/include/asm-powerpc/mmu.h @@ -8,6 +8,9 @@ #elif defined(CONFIG_PPC_STD_MMU) /* 32-bit classic hash table MMU */ # include <asm/mmu-hash32.h> +#elif defined(CONFIG_40x) +/* 40x-style software loaded TLB */ +# include <asm/mmu-40x.h> #elif defined(CONFIG_44x) /* 44x-style software loaded TLB */ # include <asm/mmu-44x.h> diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h index c4631f6dd4f9..24751df791ac 100644 --- a/include/asm-powerpc/mpc52xx.h +++ b/include/asm-powerpc/mpc52xx.h @@ -243,7 +243,7 @@ struct mpc52xx_cdm { extern void __iomem * mpc52xx_find_and_map(const char *); extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node); -extern void mpc52xx_setup_cpu(void); +extern void mpc5200_setup_xlb_arbiter(void); extern void mpc52xx_declare_of_platform_devices(void); extern void mpc52xx_init_irq(void); @@ -262,6 +262,16 @@ struct mpc52xx_suspend { extern struct mpc52xx_suspend mpc52xx_suspend; extern int __init mpc52xx_pm_init(void); extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level); + +#ifdef CONFIG_PPC_LITE5200 +extern int __init lite5200_pm_init(void); + +/* lite5200 calls mpc5200 suspend functions, so here they are */ +extern int mpc52xx_pm_prepare(suspend_state_t); +extern int mpc52xx_pm_enter(suspend_state_t); +extern int mpc52xx_pm_finish(suspend_state_t); +extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */ +#endif #endif /* CONFIG_PM */ #endif /* __ASM_POWERPC_MPC52xx_H__ */ diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h new file mode 100644 index 000000000000..26690d2b32f5 --- /dev/null +++ b/include/asm-powerpc/mpc52xx_psc.h @@ -0,0 +1,191 @@ +/* + * include/asm-ppc/mpc52xx_psc.h + * + * Definitions of consts/structs to drive the Freescale MPC52xx OnChip + * PSCs. Theses are shared between multiple drivers since a PSC can be + * UART, AC97, IR, I2S, ... So this header is in asm-ppc. + * + * + * Maintainer : Sylvain Munaut <tnt@246tNt.com> + * + * Based/Extracted from some header of the 2.4 originally written by + * Dale Farnsworth <dfarnsworth@mvista.com> + * + * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> + * Copyright (C) 2003 MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __ASM_MPC52xx_PSC_H__ +#define __ASM_MPC52xx_PSC_H__ + +#include <asm/types.h> + +/* Max number of PSCs */ +#define MPC52xx_PSC_MAXNUM 6 + +/* Programmable Serial Controller (PSC) status register bits */ +#define MPC52xx_PSC_SR_CDE 0x0080 +#define MPC52xx_PSC_SR_RXRDY 0x0100 +#define MPC52xx_PSC_SR_RXFULL 0x0200 +#define MPC52xx_PSC_SR_TXRDY 0x0400 +#define MPC52xx_PSC_SR_TXEMP 0x0800 +#define MPC52xx_PSC_SR_OE 0x1000 +#define MPC52xx_PSC_SR_PE 0x2000 +#define MPC52xx_PSC_SR_FE 0x4000 +#define MPC52xx_PSC_SR_RB 0x8000 + +/* PSC Command values */ +#define MPC52xx_PSC_RX_ENABLE 0x0001 +#define MPC52xx_PSC_RX_DISABLE 0x0002 +#define MPC52xx_PSC_TX_ENABLE 0x0004 +#define MPC52xx_PSC_TX_DISABLE 0x0008 +#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 +#define MPC52xx_PSC_RST_RX 0x0020 +#define MPC52xx_PSC_RST_TX 0x0030 +#define MPC52xx_PSC_RST_ERR_STAT 0x0040 +#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 +#define MPC52xx_PSC_START_BRK 0x0060 +#define MPC52xx_PSC_STOP_BRK 0x0070 + +/* PSC TxRx FIFO status bits */ +#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 +#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 +#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 +#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 +#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 +#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 +#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 + +/* PSC interrupt mask bits */ +#define MPC52xx_PSC_IMR_TXRDY 0x0100 +#define MPC52xx_PSC_IMR_RXRDY 0x0200 +#define MPC52xx_PSC_IMR_DB 0x0400 +#define MPC52xx_PSC_IMR_IPC 0x8000 + +/* PSC input port change bit */ +#define MPC52xx_PSC_CTS 0x01 +#define MPC52xx_PSC_DCD 0x02 +#define MPC52xx_PSC_D_CTS 0x10 +#define MPC52xx_PSC_D_DCD 0x20 + +/* PSC mode fields */ +#define MPC52xx_PSC_MODE_5_BITS 0x00 +#define MPC52xx_PSC_MODE_6_BITS 0x01 +#define MPC52xx_PSC_MODE_7_BITS 0x02 +#define MPC52xx_PSC_MODE_8_BITS 0x03 +#define MPC52xx_PSC_MODE_BITS_MASK 0x03 +#define MPC52xx_PSC_MODE_PAREVEN 0x00 +#define MPC52xx_PSC_MODE_PARODD 0x04 +#define MPC52xx_PSC_MODE_PARFORCE 0x08 +#define MPC52xx_PSC_MODE_PARNONE 0x10 +#define MPC52xx_PSC_MODE_ERR 0x20 +#define MPC52xx_PSC_MODE_FFULL 0x40 +#define MPC52xx_PSC_MODE_RXRTS 0x80 + +#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 +#define MPC52xx_PSC_MODE_ONE_STOP 0x07 +#define MPC52xx_PSC_MODE_TWO_STOP 0x0f + +#define MPC52xx_PSC_RFNUM_MASK 0x01ff + + +/* Structure of the hardware registers */ +struct mpc52xx_psc { + u8 mode; /* PSC + 0x00 */ + u8 reserved0[3]; + union { /* PSC + 0x04 */ + u16 status; + u16 clock_select; + } sr_csr; +#define mpc52xx_psc_status sr_csr.status +#define mpc52xx_psc_clock_select sr_csr.clock_select + u16 reserved1; + u8 command; /* PSC + 0x08 */ + u8 reserved2[3]; + union { /* PSC + 0x0c */ + u8 buffer_8; + u16 buffer_16; + u32 buffer_32; + } buffer; +#define mpc52xx_psc_buffer_8 buffer.buffer_8 +#define mpc52xx_psc_buffer_16 buffer.buffer_16 +#define mpc52xx_psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + u8 ipcr; + u8 acr; + } ipcr_acr; +#define mpc52xx_psc_ipcr ipcr_acr.ipcr +#define mpc52xx_psc_acr ipcr_acr.acr + u8 reserved3[3]; + union { /* PSC + 0x14 */ + u16 isr; + u16 imr; + } isr_imr; +#define mpc52xx_psc_isr isr_imr.isr +#define mpc52xx_psc_imr isr_imr.imr + u16 reserved4; + u8 ctur; /* PSC + 0x18 */ + u8 reserved5[3]; + u8 ctlr; /* PSC + 0x1c */ + u8 reserved6[3]; + u16 ccr; /* PSC + 0x20 */ + u8 reserved7[14]; + u8 ivr; /* PSC + 0x30 */ + u8 reserved8[3]; + u8 ip; /* PSC + 0x34 */ + u8 reserved9[3]; + u8 op1; /* PSC + 0x38 */ + u8 reserved10[3]; + u8 op0; /* PSC + 0x3c */ + u8 reserved11[3]; + u32 sicr; /* PSC + 0x40 */ + u8 ircr1; /* PSC + 0x44 */ + u8 reserved13[3]; + u8 ircr2; /* PSC + 0x44 */ + u8 reserved14[3]; + u8 irsdr; /* PSC + 0x4c */ + u8 reserved15[3]; + u8 irmdr; /* PSC + 0x50 */ + u8 reserved16[3]; + u8 irfdr; /* PSC + 0x54 */ + u8 reserved17[3]; + u16 rfnum; /* PSC + 0x58 */ + u16 reserved18; + u16 tfnum; /* PSC + 0x5c */ + u16 reserved19; + u32 rfdata; /* PSC + 0x60 */ + u16 rfstat; /* PSC + 0x64 */ + u16 reserved20; + u8 rfcntl; /* PSC + 0x68 */ + u8 reserved21[5]; + u16 rfalarm; /* PSC + 0x6e */ + u16 reserved22; + u16 rfrptr; /* PSC + 0x72 */ + u16 reserved23; + u16 rfwptr; /* PSC + 0x76 */ + u16 reserved24; + u16 rflrfptr; /* PSC + 0x7a */ + u16 reserved25; + u16 rflwfptr; /* PSC + 0x7e */ + u32 tfdata; /* PSC + 0x80 */ + u16 tfstat; /* PSC + 0x84 */ + u16 reserved26; + u8 tfcntl; /* PSC + 0x88 */ + u8 reserved27[5]; + u16 tfalarm; /* PSC + 0x8e */ + u16 reserved28; + u16 tfrptr; /* PSC + 0x92 */ + u16 reserved29; + u16 tfwptr; /* PSC + 0x96 */ + u16 reserved30; + u16 tflrfptr; /* PSC + 0x9a */ + u16 reserved31; + u16 tflwfptr; /* PSC + 0x9e */ +}; + + +#endif /* __ASM_MPC52xx_PSC_H__ */ diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h deleted file mode 100644 index 54142997a584..000000000000 --- a/include/asm-powerpc/mpc85xx.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * include/asm-powerpc/mpc85xx.h - * - * MPC85xx definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MPC85xx_H__ -#define __ASM_MPC85xx_H__ - -#include <asm/mmu.h> - -#ifdef CONFIG_85xx - -#if defined(CONFIG_MPC8540_ADS) || defined(CONFIG_MPC8560_ADS) -#include <platforms/85xx/mpc85xx_ads.h> -#endif -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) -#include <platforms/85xx/mpc8555_cds.h> -#endif -#ifdef CONFIG_MPC85xx_CDS -#include <platforms/85xx/mpc85xx_cds.h> -#endif - -/* Let modules/drivers get at CCSRBAR */ -extern phys_addr_t get_ccsrbar(void); - -#ifdef MODULE -#define CCSRBAR get_ccsrbar() -#else -#define CCSRBAR BOARD_CCSRBAR -#endif - -#endif /* CONFIG_85xx */ -#endif /* __ASM_MPC85xx_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index 2ffb06abe881..ae84dde3bc7f 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -224,8 +224,6 @@ struct mpic_reg_bank { u32 __iomem *base; #ifdef CONFIG_PPC_DCR dcr_host_t dhost; - unsigned int dbase; - unsigned int doff; #endif /* CONFIG_PPC_DCR */ }; @@ -240,9 +238,6 @@ struct mpic_irq_save { /* The instance data of a given MPIC */ struct mpic { - /* The device node of the interrupt controller */ - struct device_node *of_node; - /* The remapper for this MPIC */ struct irq_host *irqhost; @@ -292,9 +287,8 @@ struct mpic struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; struct mpic_reg_bank isus[MPIC_MAX_ISU]; -#ifdef CONFIG_PPC_DCR - unsigned int dcr_base; -#endif + /* Protected sources */ + unsigned long *protected; #ifdef CONFIG_MPIC_WEIRD /* Pointer to HW info array */ @@ -306,6 +300,10 @@ struct mpic unsigned long *hwirq_bitmap; #endif +#ifdef CONFIG_MPIC_BROKEN_REGREAD + u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; +#endif + /* link */ struct mpic *next; diff --git a/include/asm-powerpc/nvram.h b/include/asm-powerpc/nvram.h index f3563e11e260..9877982508bf 100644 --- a/include/asm-powerpc/nvram.h +++ b/include/asm-powerpc/nvram.h @@ -63,8 +63,10 @@ struct nvram_partition { }; -extern int nvram_write_error_log(char * buff, int length, unsigned int err_type); -extern int nvram_read_error_log(char * buff, int length, unsigned int * err_type); +extern int nvram_write_error_log(char * buff, int length, + unsigned int err_type, unsigned int err_seq); +extern int nvram_read_error_log(char * buff, int length, + unsigned int * err_type, unsigned int *err_seq); extern int nvram_clear_error_log(void); extern struct nvram_partition *nvram_find_partition(int sig, const char *name); diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h index e9af49eb1aa8..93262f2546ad 100644 --- a/include/asm-powerpc/of_device.h +++ b/include/asm-powerpc/of_device.h @@ -3,14 +3,12 @@ #ifdef __KERNEL__ #include <linux/device.h> -#include <linux/mod_devicetable.h> -#include <asm/prom.h> - +#include <linux/of.h> /* * The of_device is a kind of "base class" that is a superset of * struct device for use by devices attached to an OF node and - * probed using OF properties + * probed using OF properties. */ struct of_device { @@ -18,24 +16,14 @@ struct of_device u64 dma_mask; /* DMA mask */ struct device dev; /* Generic device interface */ }; -#define to_of_device(d) container_of(d, struct of_device, dev) - -extern const struct of_device_id *of_match_node( - const struct of_device_id *matches, const struct device_node *node); -extern const struct of_device_id *of_match_device( - const struct of_device_id *matches, const struct of_device *dev); - -extern struct of_device *of_dev_get(struct of_device *dev); -extern void of_dev_put(struct of_device *dev); - -extern int of_device_register(struct of_device *ofdev); -extern void of_device_unregister(struct of_device *ofdev); -extern void of_release_dev(struct device *dev); extern ssize_t of_device_get_modalias(struct of_device *ofdev, char *str, ssize_t len); extern int of_device_uevent(struct device *dev, - char **envp, int num_envp, char *buffer, int buffer_size); + struct kobj_uevent_env *env); + +/* This is just here during the transition */ +#include <linux/of_device.h> #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_OF_DEVICE_H */ diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h index 217eafb167e9..80e6fad28b4f 100644 --- a/include/asm-powerpc/of_platform.h +++ b/include/asm-powerpc/of_platform.h @@ -1,3 +1,5 @@ +#ifndef _ASM_POWERPC_OF_PLATFORM_H +#define _ASM_POWERPC_OF_PLATFORM_H /* * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp. * <benh@kernel.crashing.org> @@ -9,37 +11,8 @@ * */ -#include <asm/of_device.h> - -/* - * The of_platform_bus_type is a bus type used by drivers that do not - * attach to a macio or similar bus but still use OF probing - * mechanism - */ -extern struct bus_type of_platform_bus_type; - -/* - * An of_platform_driver driver is attached to a basic of_device on - * the "platform bus" (of_platform_bus_type) - */ -struct of_platform_driver -{ - char *name; - struct of_device_id *match_table; - struct module *owner; - - int (*probe)(struct of_device* dev, - const struct of_device_id *match); - int (*remove)(struct of_device* dev); - - int (*suspend)(struct of_device* dev, pm_message_t state); - int (*resume)(struct of_device* dev); - int (*shutdown)(struct of_device* dev); - - struct device_driver driver; -}; -#define to_of_platform_driver(drv) \ - container_of(drv,struct of_platform_driver, driver) +/* This is just here during the transition */ +#include <linux/of_platform.h> /* Platform drivers register/unregister */ extern int of_register_platform_driver(struct of_platform_driver *drv); @@ -56,5 +29,6 @@ extern int of_platform_bus_probe(struct device_node *root, struct of_device_id *matches, struct device *parent); -extern struct of_device *of_find_device_by_node(struct device_node *np); extern struct of_device *of_find_device_by_phandle(phandle ph); + +#endif /* _ASM_POWERPC_OF_PLATFORM_H */ diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h index 8d6b47f7b300..938fefb4c4bc 100644 --- a/include/asm-powerpc/oprofile_impl.h +++ b/include/asm-powerpc/oprofile_impl.h @@ -39,14 +39,16 @@ struct op_system_config { /* Per-arch configuration */ struct op_powerpc_model { - void (*reg_setup) (struct op_counter_config *, + int (*reg_setup) (struct op_counter_config *, struct op_system_config *, int num_counters); - void (*cpu_setup) (struct op_counter_config *); - void (*start) (struct op_counter_config *); - void (*global_start) (struct op_counter_config *); + int (*cpu_setup) (struct op_counter_config *); + int (*start) (struct op_counter_config *); + int (*global_start) (struct op_counter_config *); void (*stop) (void); void (*global_stop) (void); + int (*sync_start)(void); + int (*sync_stop)(void); void (*handle_interrupt) (struct pt_regs *, struct op_counter_config *); int num_counters; diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h index c6a5b1735666..fcd7b428ed0b 100644 --- a/include/asm-powerpc/paca.h +++ b/include/asm-powerpc/paca.h @@ -21,7 +21,18 @@ #include <asm/mmu.h> register struct paca_struct *local_paca asm("r13"); + +#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP) +extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */ +/* + * Add standard checks that preemption cannot occur when using get_paca(): + * otherwise the paca_struct it points to may be the wrong one just after. + */ +#define get_paca() ((void) debug_smp_processor_id(), local_paca) +#else #define get_paca() local_paca +#endif + #define get_lppaca() (get_paca()->lppaca_ptr) #define get_slb_shadow() (get_paca()->slb_shadow_ptr) diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h index 10c51f457d48..236a9210e5fc 100644 --- a/include/asm-powerpc/page.h +++ b/include/asm-powerpc/page.h @@ -190,7 +190,6 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr, extern int page_is_ram(unsigned long pfn); struct vm_area_struct; -extern const char *arch_vma_name(struct vm_area_struct *vma); #include <asm-generic/memory_model.h> #endif /* __ASSEMBLY__ */ diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h index 3448a3d4bc64..4ee82c61e4d7 100644 --- a/include/asm-powerpc/page_64.h +++ b/include/asm-powerpc/page_64.h @@ -26,12 +26,18 @@ */ #define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT) -/* Segment size */ +/* Segment size; normal 256M segments */ #define SID_SHIFT 28 -#define SID_MASK 0xfffffffffUL +#define SID_MASK ASM_CONST(0xfffffffff) #define ESID_MASK 0xfffffffff0000000UL #define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK) +/* 1T segments */ +#define SID_SHIFT_1T 40 +#define SID_MASK_1T 0xffffffUL +#define ESID_MASK_1T 0xffffff0000000000UL +#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T) + #ifndef __ASSEMBLY__ #include <asm/cache.h> @@ -121,6 +127,7 @@ extern unsigned int get_slice_psize(struct mm_struct *mm, extern void slice_init_context(struct mm_struct *mm, unsigned int psize); extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize); +#define slice_mm_new_context(mm) ((mm)->context.id == 0) #define ARCH_HAS_HUGEPAGE_ONLY_RANGE extern int is_hugepage_only_range(struct mm_struct *m, @@ -130,6 +137,12 @@ extern int is_hugepage_only_range(struct mm_struct *m, #endif /* __ASSEMBLY__ */ #else #define slice_init() +#define slice_set_user_psize(mm, psize) \ +do { \ + (mm)->context.user_psize = (psize); \ + (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \ +} while (0) +#define slice_mm_new_context(mm) 1 #endif /* CONFIG_PPC_MM_SLICES */ #ifdef CONFIG_HUGETLB_PAGE diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index e72c2a60853c..dc318458b5fe 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -45,10 +45,17 @@ struct pci_controller { * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS * to determine which bus number to match on when generating type0 * config cycles + * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with + * hanging if we don't have link and try to do config cycles to + * anything but the PHB. Only allow talking to the PHB if this is + * set. + * BIG_ENDIAN - cfg_addr is a big endian register */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) +#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) +#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) u32 indirect_type; /* Currently, we limit ourselves to 1 IO range and 3 mem @@ -64,6 +71,14 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) return bus->sysdata; } +static inline int isa_vaddr_is_ioport(void __iomem *address) +{ + /* No specific ISA handling on ppc32 at this stage, it + * all goes through PCI + */ + return 0; +} + /* These are used for config access before all the PCI probing has been done. */ int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, @@ -79,11 +94,15 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 val); -extern void setup_indirect_pci_nomap(struct pci_controller* hose, - void __iomem *cfg_addr, void __iomem *cfg_data); +extern int early_find_capability(struct pci_controller *hose, int bus, + int dev_fn, int cap); + extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); +extern void __init update_bridge_resource(struct pci_dev *dev, + struct resource *res); #else @@ -231,6 +250,13 @@ extern void pcibios_free_controller(struct pci_controller *phb); extern void isa_bridge_find_early(struct pci_controller *hose); +static inline int isa_vaddr_is_ioport(void __iomem *address) +{ + /* Check if address hits the reserved legacy IO range */ + unsigned long ea = (unsigned long)address; + return ea >= ISA_IO_BASE && ea < ISA_IO_END; +} + extern int pcibios_unmap_io_space(struct pci_bus *bus); extern int pcibios_map_io_space(struct pci_bus *bus); @@ -261,11 +287,16 @@ extern struct pci_controller * pcibios_alloc_controller(struct device_node *dev); #ifdef CONFIG_PCI extern unsigned long pci_address_to_pio(phys_addr_t address); +extern int pcibios_vaddr_is_ioport(void __iomem *address); #else static inline unsigned long pci_address_to_pio(phys_addr_t address) { return (unsigned long)-1; } +static inline int pcibios_vaddr_is_ioport(void __iomem *address) +{ + return 0; +} #endif diff --git a/include/asm-powerpc/percpu.h b/include/asm-powerpc/percpu.h index 2f2e3024fa61..6b229626d3ff 100644 --- a/include/asm-powerpc/percpu.h +++ b/include/asm-powerpc/percpu.h @@ -20,10 +20,15 @@ #define DEFINE_PER_CPU(type, name) \ __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp + /* var is in discarded region: offset to particular copy we want */ #define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu))) #define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset())) -#define __raw_get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset())) +#define __raw_get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, local_paca->data_offset)) /* A macro to avoid #include hell... */ #define percpu_modcopy(pcpudst, src, size) \ @@ -40,6 +45,8 @@ extern void setup_per_cpu_areas(void); #define DEFINE_PER_CPU(type, name) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) #define per_cpu(var, cpu) (*((void)(cpu), &per_cpu__##var)) #define __get_cpu_var(var) per_cpu__##var diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h index add5481fd7c7..818e2abc81e2 100644 --- a/include/asm-powerpc/pgtable-4k.h +++ b/include/asm-powerpc/pgtable-4k.h @@ -10,10 +10,12 @@ #define PUD_INDEX_SIZE 7 #define PGD_INDEX_SIZE 9 +#ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) +#endif /* __ASSEMBLY__ */ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h index 31cbd3d7fce8..bd54b772fbc6 100644 --- a/include/asm-powerpc/pgtable-64k.h +++ b/include/asm-powerpc/pgtable-64k.h @@ -9,9 +9,11 @@ #define PUD_INDEX_SIZE 0 #define PGD_INDEX_SIZE 4 +#ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) +#endif /* __ASSEMBLY__ */ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) @@ -49,12 +51,10 @@ /* Shift to put page number into pte. * - * That gives us a max RPN of 32 bits, which means a max of 48 bits - * of addressable physical space. - * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but - * 32 makes PTEs more readable for debugging for now :) + * That gives us a max RPN of 34 bits, which means a max of 50 bits + * of addressable physical space, or 46 bits for the special 4k PFNs. */ -#define PTE_RPN_SHIFT (32) +#define PTE_RPN_SHIFT (30) #define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT)) #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1)) diff --git a/include/asm-powerpc/pmi.h b/include/asm-powerpc/pmi.h index cb0f8aa43088..2259d4ce3846 100644 --- a/include/asm-powerpc/pmi.h +++ b/include/asm-powerpc/pmi.h @@ -55,13 +55,13 @@ typedef struct { struct pmi_handler { struct list_head node; u8 type; - void (*handle_pmi_message) (struct of_device *, pmi_message_t); + void (*handle_pmi_message) (pmi_message_t); }; -void pmi_register_handler(struct of_device *, struct pmi_handler *); -void pmi_unregister_handler(struct of_device *, struct pmi_handler *); +int pmi_register_handler(struct pmi_handler *); +void pmi_unregister_handler(struct pmi_handler *); -void pmi_send_message(struct of_device *, pmi_message_t); +int pmi_send_message(pmi_message_t); #endif /* __KERNEL__ */ #endif /* _POWERPC_PMI_H */ diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index fa083d8e4663..2dbd4e7884fa 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -155,6 +155,20 @@ name: \ .type GLUE(.,name),@function; \ GLUE(.,name): +#define _INIT_GLOBAL(name) \ + .section ".text.init.refok"; \ + .align 2 ; \ + .globl name; \ + .globl GLUE(.,name); \ + .section ".opd","aw"; \ +name: \ + .quad GLUE(.,name); \ + .quad .TOC.@tocbase; \ + .quad 0; \ + .previous; \ + .type GLUE(.,name),@function; \ +GLUE(.,name): + #define _KPROBE(name) \ .section ".kprobes.text","a"; \ .align 2 ; \ @@ -181,8 +195,24 @@ name: \ .type GLUE(.,name),@function; \ GLUE(.,name): +#define _INIT_STATIC(name) \ + .section ".text.init.refok"; \ + .align 2 ; \ + .section ".opd","aw"; \ +name: \ + .quad GLUE(.,name); \ + .quad .TOC.@tocbase; \ + .quad 0; \ + .previous; \ + .type GLUE(.,name),@function; \ +GLUE(.,name): + #else /* 32-bit */ +#define _ENTRY(n) \ + .globl n; \ +n: + #define _GLOBAL(n) \ .text; \ .stabs __stringify(n:F-1),N_FUN,0,0,n;\ diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index e28b10805159..dba7c948189d 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -145,9 +145,9 @@ struct thread_struct { unsigned long dabr; /* Data address breakpoint register */ #ifdef CONFIG_ALTIVEC /* Complete AltiVec register set */ - vector128 vr[32] __attribute((aligned(16))); + vector128 vr[32] __attribute__((aligned(16))); /* AltiVec status */ - vector128 vscr __attribute((aligned(16))); + vector128 vscr __attribute__((aligned(16))); unsigned long vrsave; int used_vr; /* set if process has used altivec */ #endif /* CONFIG_ALTIVEC */ diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h index 1632baa17dc6..925e2d384bb3 100644 --- a/include/asm-powerpc/prom.h +++ b/include/asm-powerpc/prom.h @@ -21,6 +21,13 @@ #include <asm/irq.h> #include <asm/atomic.h> +#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1 +#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 + +#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2)) +#define of_prop_cmp(s1, s2) strcmp((s1), (s2)) +#define of_node_cmp(s1, s2) strcasecmp((s1), (s2)) + /* Definitions used by the flattened device tree */ #define OF_DT_HEADER 0xd00dfeed /* marker */ #define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ @@ -97,10 +104,6 @@ struct device_node { extern struct device_node *of_chosen; -/* flag descriptions */ -#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ -#define OF_DETACHED 2 /* node has been detached from the device tree */ - static inline int of_node_check_flag(struct device_node *n, unsigned long flag) { return test_bit(flag, &n->_flags); @@ -120,31 +123,7 @@ static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_e } -/* New style node lookup */ -extern struct device_node *of_find_node_by_name(struct device_node *from, - const char *name); -#define for_each_node_by_name(dn, name) \ - for (dn = of_find_node_by_name(NULL, name); dn; \ - dn = of_find_node_by_name(dn, name)) -extern struct device_node *of_find_node_by_type(struct device_node *from, - const char *type); -#define for_each_node_by_type(dn, type) \ - for (dn = of_find_node_by_type(NULL, type); dn; \ - dn = of_find_node_by_type(dn, type)) -extern struct device_node *of_find_compatible_node(struct device_node *from, - const char *type, const char *compat); -#define for_each_compatible_node(dn, type, compatible) \ - for (dn = of_find_compatible_node(NULL, type, compatible); dn; \ - dn = of_find_compatible_node(dn, type, compatible)) -extern struct device_node *of_find_node_by_path(const char *path); -extern struct device_node *of_find_node_by_phandle(phandle handle); extern struct device_node *of_find_all_nodes(struct device_node *prev); -extern struct device_node *of_get_parent(const struct device_node *node); -extern struct device_node *of_get_next_child(const struct device_node *node, - struct device_node *prev); -extern struct property *of_find_property(const struct device_node *np, - const char *name, - int *lenp); extern struct device_node *of_node_get(struct device_node *node); extern void of_node_put(struct device_node *node); @@ -160,23 +139,14 @@ extern unsigned long __init of_get_flat_dt_root(void); /* For updating the device tree at runtime */ extern void of_attach_node(struct device_node *); -extern void of_detach_node(const struct device_node *); +extern void of_detach_node(struct device_node *); /* Other Prototypes */ extern void finish_device_tree(void); extern void unflatten_device_tree(void); extern void early_init_devtree(void *); -extern int of_device_is_compatible(const struct device_node *device, - const char *); -#define device_is_compatible(d, c) of_device_is_compatible((d), (c)) extern int machine_is_compatible(const char *compat); -extern const void *of_get_property(const struct device_node *node, - const char *name, - int *lenp); -#define get_property(a, b, c) of_get_property((a), (b), (c)) extern void print_properties(struct device_node *node); -extern int of_n_addr_cells(struct device_node* np); -extern int of_n_size_cells(struct device_node* np); extern int prom_n_intr_cells(struct device_node* np); extern void prom_get_irq_senses(unsigned char *senses, int off, int max); extern int prom_add_property(struct device_node* np, struct property* prop); @@ -230,7 +200,6 @@ static inline unsigned long of_read_ulong(const u32 *cell, int size) /* Translate an OF address block into a CPU physical address */ -#define OF_BAD_ADDR ((u64)-1) extern u64 of_translate_address(struct device_node *np, const u32 *addr); /* Extract an address from a device, returns the region size and @@ -357,5 +326,11 @@ extern int of_irq_to_resource(struct device_node *dev, int index, */ extern void __iomem *of_iomap(struct device_node *device, int index); +/* + * NB: This is here while we transition from using asm/prom.h + * to linux/of.h + */ +#include <linux/of.h> + #endif /* __KERNEL__ */ #endif /* _POWERPC_PROM_H */ diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h index a6f3f5ee7ca7..f577a16c6728 100644 --- a/include/asm-powerpc/ps3.h +++ b/include/asm-powerpc/ps3.h @@ -229,6 +229,9 @@ enum lv1_result { LV1_INVALID_CLASS_ID = -21, LV1_CONSTRAINT_NOT_SATISFIED = -22, LV1_ALIGNMENT_ERROR = -23, + LV1_HARDWARE_ERROR = -24, + LV1_INVALID_DATA_FORMAT = -25, + LV1_INVALID_OPERATION = -26, LV1_INTERNAL_ERROR = -32768, }; @@ -284,6 +287,12 @@ static inline const char* ps3_result(int result) return "LV1_CONSTRAINT_NOT_SATISFIED (-22)"; case LV1_ALIGNMENT_ERROR: return "LV1_ALIGNMENT_ERROR (-23)"; + case LV1_HARDWARE_ERROR: + return "LV1_HARDWARE_ERROR (-24)"; + case LV1_INVALID_DATA_FORMAT: + return "LV1_INVALID_DATA_FORMAT (-25)"; + case LV1_INVALID_OPERATION: + return "LV1_INVALID_OPERATION (-26)"; case LV1_INTERNAL_ERROR: return "LV1_INTERNAL_ERROR (-32768)"; default: diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index 9d304b1f1608..0dabe46a29d2 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -32,10 +32,13 @@ extern void qe_reset(void); extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, + int assignment, int has_irq); +extern int par_io_data_set(u8 port, u8 pin, u8 val); /* QE internal API */ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); -void qe_setbrg(u32 brg, u32 rate); +void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); unsigned long qe_muram_alloc(int size, int align); @@ -46,14 +49,28 @@ void *qe_muram_addr(unsigned long offset); /* Buffer descriptors */ struct qe_bd { - u16 status; - u16 length; - u32 buf; + __be16 status; + __be16 length; + __be32 buf; } __attribute__ ((packed)); #define BD_STATUS_MASK 0xffff0000 #define BD_LENGTH_MASK 0x0000ffff +#define BD_SC_EMPTY 0x8000 /* Receive is empty */ +#define BD_SC_READY 0x8000 /* Transmit is ready */ +#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ +#define BD_SC_INTRPT 0x1000 /* Interrupt on change */ +#define BD_SC_LAST 0x0800 /* Last buffer in frame */ +#define BD_SC_CM 0x0200 /* Continous mode */ +#define BD_SC_ID 0x0100 /* Rec'd too many idles */ +#define BD_SC_P 0x0100 /* xmt preamble */ +#define BD_SC_BR 0x0020 /* Break received */ +#define BD_SC_FR 0x0010 /* Framing error */ +#define BD_SC_PR 0x0008 /* Parity error */ +#define BD_SC_OV 0x0002 /* Overrun */ +#define BD_SC_CD 0x0001 /* ?? */ + /* Alignment */ #define QE_INTR_TABLE_ALIGN 16 /* ??? */ #define QE_ALIGNMENT_OF_BD 8 @@ -266,15 +283,12 @@ enum qe_clock { /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_QMC 0x02 +#define QE_CR_PROTOCOL_UART 0x04 #define QE_CR_PROTOCOL_ATM_POS 0x0A #define QE_CR_PROTOCOL_ETHERNET 0x0C #define QE_CR_PROTOCOL_L2_SWITCH 0x0D -/* BMR byte order */ -#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */ -#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */ -#define QE_BMR_BYTE_ORDER_BO_MAX 0x18 - /* BRG configuration register */ #define QE_BRGC_ENABLE 0x00010000 #define QE_BRGC_DIVISOR_SHIFT 1 @@ -321,41 +335,41 @@ enum qe_clock { #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ -/* UCC */ +/* UCC GUEMR register */ #define UCC_GUEMR_MODE_MASK_RX 0x02 -#define UCC_GUEMR_MODE_MASK_TX 0x01 #define UCC_GUEMR_MODE_FAST_RX 0x02 -#define UCC_GUEMR_MODE_FAST_TX 0x01 #define UCC_GUEMR_MODE_SLOW_RX 0x00 +#define UCC_GUEMR_MODE_MASK_TX 0x01 +#define UCC_GUEMR_MODE_FAST_TX 0x01 #define UCC_GUEMR_MODE_SLOW_TX 0x00 +#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but must be set 1 */ /* structure representing UCC SLOW parameter RAM */ struct ucc_slow_pram { - u16 rbase; /* RX BD base address */ - u16 tbase; /* TX BD base address */ - u8 rfcr; /* Rx function code */ - u8 tfcr; /* Tx function code */ - u16 mrblr; /* Rx buffer length */ - u32 rstate; /* Rx internal state */ - u32 rptr; /* Rx internal data pointer */ - u16 rbptr; /* rb BD Pointer */ - u16 rcount; /* Rx internal byte count */ - u32 rtemp; /* Rx temp */ - u32 tstate; /* Tx internal state */ - u32 tptr; /* Tx internal data pointer */ - u16 tbptr; /* Tx BD pointer */ - u16 tcount; /* Tx byte count */ - u32 ttemp; /* Tx temp */ - u32 rcrc; /* temp receive CRC */ - u32 tcrc; /* temp transmit CRC */ + __be16 rbase; /* RX BD base address */ + __be16 tbase; /* TX BD base address */ + u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ + u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ + __be16 mrblr; /* Rx buffer length */ + __be32 rstate; /* Rx internal state */ + __be32 rptr; /* Rx internal data pointer */ + __be16 rbptr; /* rb BD Pointer */ + __be16 rcount; /* Rx internal byte count */ + __be32 rtemp; /* Rx temp */ + __be32 tstate; /* Tx internal state */ + __be32 tptr; /* Tx internal data pointer */ + __be16 tbptr; /* Tx BD pointer */ + __be16 tcount; /* Tx byte count */ + __be32 ttemp; /* Tx temp */ + __be32 rcrc; /* temp receive CRC */ + __be32 tcrc; /* temp transmit CRC */ } __attribute__ ((packed)); /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ -#define UCC_SLOW_GUMR_H_CRC16 0x00004000 -#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000 -#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000 +#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 +#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 #define UCC_SLOW_GUMR_H_REVD 0x00002000 #define UCC_SLOW_GUMR_H_TRX 0x00001000 #define UCC_SLOW_GUMR_H_TTX 0x00000800 @@ -375,9 +389,33 @@ struct ucc_slow_pram { #define UCC_SLOW_GUMR_L_TCI 0x10000000 #define UCC_SLOW_GUMR_L_RINV 0x02000000 #define UCC_SLOW_GUMR_L_TINV 0x01000000 -#define UCC_SLOW_GUMR_L_TEND 0x00020000 +#define UCC_SLOW_GUMR_L_TEND 0x00040000 +#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 +#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 +#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 +#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 +#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 +#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 +#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 +#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 +#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 +#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 +#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 +#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 +#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 +#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 +#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 +#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 +#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 +#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 +#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 #define UCC_SLOW_GUMR_L_ENR 0x00000020 #define UCC_SLOW_GUMR_L_ENT 0x00000010 +#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F +#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 +#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 +#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 +#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 /* General UCC FAST Mode Register */ #define UCC_FAST_GUMR_TCI 0x20000000 @@ -394,53 +432,111 @@ struct ucc_slow_pram { #define UCC_FAST_GUMR_ENR 0x00000020 #define UCC_FAST_GUMR_ENT 0x00000010 -/* Slow UCC Event Register (UCCE) */ -#define UCC_SLOW_UCCE_GLR 0x1000 -#define UCC_SLOW_UCCE_GLT 0x0800 -#define UCC_SLOW_UCCE_DCC 0x0400 -#define UCC_SLOW_UCCE_FLG 0x0200 -#define UCC_SLOW_UCCE_AB 0x0200 -#define UCC_SLOW_UCCE_IDLE 0x0100 -#define UCC_SLOW_UCCE_GRA 0x0080 -#define UCC_SLOW_UCCE_TXE 0x0010 -#define UCC_SLOW_UCCE_RXF 0x0008 -#define UCC_SLOW_UCCE_CCR 0x0008 -#define UCC_SLOW_UCCE_RCH 0x0008 -#define UCC_SLOW_UCCE_BSY 0x0004 -#define UCC_SLOW_UCCE_TXB 0x0002 -#define UCC_SLOW_UCCE_TX 0x0002 -#define UCC_SLOW_UCCE_RX 0x0001 -#define UCC_SLOW_UCCE_GOV 0x0001 -#define UCC_SLOW_UCCE_GUN 0x0002 -#define UCC_SLOW_UCCE_GINT 0x0004 -#define UCC_SLOW_UCCE_IQOV 0x0008 - -#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ - UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \ - UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) -#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ - UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF) -#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ - UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ - UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) -#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \ - UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ - UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) -#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \ - UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV) - -#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ - UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \ - UCC_SLOW_UCCE_GLR) - -#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB -#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX) -#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX) +/* UART Slow UCC Event Register (UCCE) */ +#define UCC_UART_UCCE_AB 0x0200 +#define UCC_UART_UCCE_IDLE 0x0100 +#define UCC_UART_UCCE_GRA 0x0080 +#define UCC_UART_UCCE_BRKE 0x0040 +#define UCC_UART_UCCE_BRKS 0x0020 +#define UCC_UART_UCCE_CCR 0x0008 +#define UCC_UART_UCCE_BSY 0x0004 +#define UCC_UART_UCCE_TX 0x0002 +#define UCC_UART_UCCE_RX 0x0001 + +/* HDLC Slow UCC Event Register (UCCE) */ +#define UCC_HDLC_UCCE_GLR 0x1000 +#define UCC_HDLC_UCCE_GLT 0x0800 +#define UCC_HDLC_UCCE_IDLE 0x0100 +#define UCC_HDLC_UCCE_BRKE 0x0040 +#define UCC_HDLC_UCCE_BRKS 0x0020 +#define UCC_HDLC_UCCE_TXE 0x0010 +#define UCC_HDLC_UCCE_RXF 0x0008 +#define UCC_HDLC_UCCE_BSY 0x0004 +#define UCC_HDLC_UCCE_TXB 0x0002 +#define UCC_HDLC_UCCE_RXB 0x0001 + +/* BISYNC Slow UCC Event Register (UCCE) */ +#define UCC_BISYNC_UCCE_GRA 0x0080 +#define UCC_BISYNC_UCCE_TXE 0x0010 +#define UCC_BISYNC_UCCE_RCH 0x0008 +#define UCC_BISYNC_UCCE_BSY 0x0004 +#define UCC_BISYNC_UCCE_TXB 0x0002 +#define UCC_BISYNC_UCCE_RXB 0x0001 + +/* Gigabit Ethernet Fast UCC Event Register (UCCE) */ +#define UCC_GETH_UCCE_MPD 0x80000000 +#define UCC_GETH_UCCE_SCAR 0x40000000 +#define UCC_GETH_UCCE_GRA 0x20000000 +#define UCC_GETH_UCCE_CBPR 0x10000000 +#define UCC_GETH_UCCE_BSY 0x08000000 +#define UCC_GETH_UCCE_RXC 0x04000000 +#define UCC_GETH_UCCE_TXC 0x02000000 +#define UCC_GETH_UCCE_TXE 0x01000000 +#define UCC_GETH_UCCE_TXB7 0x00800000 +#define UCC_GETH_UCCE_TXB6 0x00400000 +#define UCC_GETH_UCCE_TXB5 0x00200000 +#define UCC_GETH_UCCE_TXB4 0x00100000 +#define UCC_GETH_UCCE_TXB3 0x00080000 +#define UCC_GETH_UCCE_TXB2 0x00040000 +#define UCC_GETH_UCCE_TXB1 0x00020000 +#define UCC_GETH_UCCE_TXB0 0x00010000 +#define UCC_GETH_UCCE_RXB7 0x00008000 +#define UCC_GETH_UCCE_RXB6 0x00004000 +#define UCC_GETH_UCCE_RXB5 0x00002000 +#define UCC_GETH_UCCE_RXB4 0x00001000 +#define UCC_GETH_UCCE_RXB3 0x00000800 +#define UCC_GETH_UCCE_RXB2 0x00000400 +#define UCC_GETH_UCCE_RXB1 0x00000200 +#define UCC_GETH_UCCE_RXB0 0x00000100 +#define UCC_GETH_UCCE_RXF7 0x00000080 +#define UCC_GETH_UCCE_RXF6 0x00000040 +#define UCC_GETH_UCCE_RXF5 0x00000020 +#define UCC_GETH_UCCE_RXF4 0x00000010 +#define UCC_GETH_UCCE_RXF3 0x00000008 +#define UCC_GETH_UCCE_RXF2 0x00000004 +#define UCC_GETH_UCCE_RXF1 0x00000002 +#define UCC_GETH_UCCE_RXF0 0x00000001 + +/* UPSMR, when used as a UART */ +#define UCC_UART_UPSMR_FLC 0x8000 +#define UCC_UART_UPSMR_SL 0x4000 +#define UCC_UART_UPSMR_CL_MASK 0x3000 +#define UCC_UART_UPSMR_CL_8 0x3000 +#define UCC_UART_UPSMR_CL_7 0x2000 +#define UCC_UART_UPSMR_CL_6 0x1000 +#define UCC_UART_UPSMR_CL_5 0x0000 +#define UCC_UART_UPSMR_UM_MASK 0x0c00 +#define UCC_UART_UPSMR_UM_NORMAL 0x0000 +#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 +#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 +#define UCC_UART_UPSMR_FRZ 0x0200 +#define UCC_UART_UPSMR_RZS 0x0100 +#define UCC_UART_UPSMR_SYN 0x0080 +#define UCC_UART_UPSMR_DRT 0x0040 +#define UCC_UART_UPSMR_PEN 0x0010 +#define UCC_UART_UPSMR_RPM_MASK 0x000c +#define UCC_UART_UPSMR_RPM_ODD 0x0000 +#define UCC_UART_UPSMR_RPM_LOW 0x0004 +#define UCC_UART_UPSMR_RPM_EVEN 0x0008 +#define UCC_UART_UPSMR_RPM_HIGH 0x000C +#define UCC_UART_UPSMR_TPM_MASK 0x0003 +#define UCC_UART_UPSMR_TPM_ODD 0x0000 +#define UCC_UART_UPSMR_TPM_LOW 0x0001 +#define UCC_UART_UPSMR_TPM_EVEN 0x0002 +#define UCC_UART_UPSMR_TPM_HIGH 0x0003 /* UCC Transmit On Demand Register (UTODR) */ #define UCC_SLOW_TOD 0x8000 #define UCC_FAST_TOD 0x8000 +/* UCC Bus Mode Register masks */ +/* Not to be confused with the Bundle Mode Register */ +#define UCC_BMR_GBL 0x20 +#define UCC_BMR_BO_BE 0x10 +#define UCC_BMR_CETM 0x04 +#define UCC_BMR_DTB 0x02 +#define UCC_BMR_BDB 0x01 + /* Function code masks */ #define FC_GBL 0x20 #define FC_DTB_LCL 0x02 diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h index e386fb7e44b0..a779b2c9eaf1 100644 --- a/include/asm-powerpc/qe_ic.h +++ b/include/asm-powerpc/qe_ic.h @@ -56,9 +56,75 @@ enum qe_ic_grp_id { QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ }; -void qe_ic_init(struct device_node *node, unsigned int flags); +void qe_ic_init(struct device_node *node, unsigned int flags, + void (*low_handler)(unsigned int irq, struct irq_desc *desc), + void (*high_handler)(unsigned int irq, struct irq_desc *desc)); void qe_ic_set_highest_priority(unsigned int virq, int high); int qe_ic_set_priority(unsigned int virq, unsigned int priority); int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); +struct qe_ic; +unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); +unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); + +static inline void qe_ic_cascade_low_ipic(unsigned int irq, + struct irq_desc *desc) +{ + struct qe_ic *qe_ic = desc->handler_data; + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); + + if (cascade_irq != NO_IRQ) + generic_handle_irq(cascade_irq); +} + +static inline void qe_ic_cascade_high_ipic(unsigned int irq, + struct irq_desc *desc) +{ + struct qe_ic *qe_ic = desc->handler_data; + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); + + if (cascade_irq != NO_IRQ) + generic_handle_irq(cascade_irq); +} + +static inline void qe_ic_cascade_low_mpic(unsigned int irq, + struct irq_desc *desc) +{ + struct qe_ic *qe_ic = desc->handler_data; + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); + + if (cascade_irq != NO_IRQ) + generic_handle_irq(cascade_irq); + + desc->chip->eoi(irq); +} + +static inline void qe_ic_cascade_high_mpic(unsigned int irq, + struct irq_desc *desc) +{ + struct qe_ic *qe_ic = desc->handler_data; + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); + + if (cascade_irq != NO_IRQ) + generic_handle_irq(cascade_irq); + + desc->chip->eoi(irq); +} + +static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, + struct irq_desc *desc) +{ + struct qe_ic *qe_ic = desc->handler_data; + unsigned int cascade_irq; + + cascade_irq = qe_ic_get_high_irq(qe_ic); + if (cascade_irq == NO_IRQ) + cascade_irq = qe_ic_get_low_irq(qe_ic); + + if (cascade_irq != NO_IRQ) + generic_handle_irq(cascade_irq); + + desc->chip->eoi(irq); +} + #endif /* _ASM_POWERPC_QE_IC_H */ diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 281011e953ec..e775ff1ca413 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -102,12 +102,8 @@ #else /* 32-bit */ /* Default MSR for kernel mode. */ #ifndef MSR_KERNEL /* reg_booke.h also defines this */ -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) -#else #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) #endif -#endif #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) #endif @@ -518,21 +514,47 @@ #define PA6T_MMCR1_ES4 0x0000000000ff0000UL #define PA6T_MMCR1_ES5 0x00000000ff000000UL -#define SPRN_PA6T_SIAR 780 -#define SPRN_PA6T_UPMC0 771 -#define SPRN_PA6T_UPMC1 772 +#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ +#define SPRN_PA6T_UPMC1 772 /* ... */ #define SPRN_PA6T_UPMC2 773 #define SPRN_PA6T_UPMC3 774 #define SPRN_PA6T_UPMC4 775 #define SPRN_PA6T_UPMC5 776 -#define SPRN_PA6T_UMMCR0 779 -#define SPRN_PA6T_UMMCR1 782 -#define SPRN_PA6T_PMC0 787 -#define SPRN_PA6T_PMC1 788 -#define SPRN_PA6T_PMC2 789 -#define SPRN_PA6T_PMC3 790 -#define SPRN_PA6T_PMC4 791 -#define SPRN_PA6T_PMC5 792 +#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ +#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ +#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ +#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ +#define SPRN_PA6T_PMC0 787 +#define SPRN_PA6T_PMC1 788 +#define SPRN_PA6T_PMC2 789 +#define SPRN_PA6T_PMC3 790 +#define SPRN_PA6T_PMC4 791 +#define SPRN_PA6T_PMC5 792 +#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ +#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ +#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ +#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ + +#define SPRN_PA6T_IER 981 /* Icache Error Register */ +#define SPRN_PA6T_DER 982 /* Dcache Error Register */ +#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ +#define SPRN_PA6T_MER 849 /* MMU Error Register */ + +#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ +#define SPRN_PA6T_IMA1 881 /* ... */ +#define SPRN_PA6T_IMA2 882 +#define SPRN_PA6T_IMA3 883 +#define SPRN_PA6T_IMA4 884 +#define SPRN_PA6T_IMA5 885 +#define SPRN_PA6T_IMA6 886 +#define SPRN_PA6T_IMA7 887 +#define SPRN_PA6T_IMA8 888 +#define SPRN_PA6T_IMA9 889 +#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ +#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ +#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ +#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ + #else /* 32-bit */ #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h index 064405c207bf..8fdc2b47afb9 100644 --- a/include/asm-powerpc/reg_booke.h +++ b/include/asm-powerpc/reg_booke.h @@ -223,7 +223,6 @@ #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ -#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ @@ -232,6 +231,12 @@ #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ + +/* e500 parts may set unused bits in MCSR; mask these off */ +#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \ + MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \ + MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \ + MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR) #endif #ifdef CONFIG_E200 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ @@ -243,6 +248,11 @@ #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered store or cache line push */ + +/* e200 parts may set unused bits in MCSR; mask these off */ +#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \ + MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \ + MCSR_BUS_WRERR) #endif /* Bit definitions for the DBSR. */ diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h index e929145e1e46..cefc14728cc5 100644 --- a/include/asm-powerpc/rwsem.h +++ b/include/asm-powerpc/rwsem.h @@ -1,6 +1,10 @@ #ifndef _ASM_POWERPC_RWSEM_H #define _ASM_POWERPC_RWSEM_H +#ifndef _LINUX_RWSEM_H +#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead." +#endif + #ifdef __KERNEL__ /* diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h index d037f50580e2..19102bfc14ca 100644 --- a/include/asm-powerpc/smp.h +++ b/include/asm-powerpc/smp.h @@ -45,7 +45,7 @@ void generic_mach_cpu_die(void); #endif #ifdef CONFIG_PPC64 -#define raw_smp_processor_id() (get_paca()->paca_index) +#define raw_smp_processor_id() (local_paca->paca_index) #define hard_smp_processor_id() (get_paca()->hw_cpu_id) #else /* 32-bit */ diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index eedc828cef2d..b1accce77bb5 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -107,10 +107,10 @@ struct spu_runqueue; struct device_node; enum spu_utilization_state { - SPU_UTIL_SYSTEM, SPU_UTIL_USER, + SPU_UTIL_SYSTEM, SPU_UTIL_IOWAIT, - SPU_UTIL_IDLE, + SPU_UTIL_IDLE_LOADED, SPU_UTIL_MAX }; @@ -121,15 +121,16 @@ struct spu { unsigned long problem_phys; struct spu_problem __iomem *problem; struct spu_priv2 __iomem *priv2; - struct list_head list; - struct list_head sched_list; + struct list_head cbe_list; struct list_head full_list; + enum { SPU_FREE, SPU_USED } alloc_state; int number; unsigned int irqs[3]; u32 node; u64 flags; u64 dar; u64 dsisr; + u64 class_0_pending; size_t ls_size; unsigned int slb_replace; struct mm_struct *mm; @@ -137,7 +138,7 @@ struct spu { struct spu_runqueue *rq; unsigned long long timestamp; pid_t pid; - int class_0_pending; + pid_t tgid; spinlock_t register_lock; void (* wbox_callback)(struct spu *spu); @@ -165,11 +166,14 @@ struct spu { struct sys_device sysdev; + int has_mem_affinity; + struct list_head aff_list; + struct { /* protected by interrupt reentrancy */ - enum spu_utilization_state utilization_state; - unsigned long tstamp; /* time of last ctx switch */ - unsigned long times[SPU_UTIL_MAX]; + enum spu_utilization_state util_state; + unsigned long long tstamp; + unsigned long long times[SPU_UTIL_MAX]; unsigned long long vol_ctx_switch; unsigned long long invol_ctx_switch; unsigned long long min_flt; @@ -181,13 +185,29 @@ struct spu { } stats; }; -struct spu *spu_alloc(void); -struct spu *spu_alloc_node(int node); -void spu_free(struct spu *spu); +struct cbe_spu_info { + struct mutex list_mutex; + struct list_head spus; + int n_spus; + int nr_active; + atomic_t reserved_spus; +}; + +extern struct cbe_spu_info cbe_spu_info[]; + +void spu_init_channels(struct spu *spu); int spu_irq_class_0_bottom(struct spu *spu); int spu_irq_class_1_bottom(struct spu *spu); void spu_irq_setaffinity(struct spu *spu, int cpu); +#ifdef CONFIG_KEXEC +void crash_register_spus(struct list_head *list); +#else +static inline void crash_register_spus(struct list_head *list) +{ +} +#endif + extern void spu_invalidate_slbs(struct spu *spu); extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); @@ -195,6 +215,20 @@ extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); struct mm_struct; extern void spu_flush_all_slbs(struct mm_struct *mm); +/* This interface allows a profiler (e.g., OProfile) to store a ref + * to spu context information that it creates. This caching technique + * avoids the need to recreate this information after a save/restore operation. + * + * Assumes the caller has already incremented the ref count to + * profile_info; then spu_context_destroy must call kref_put + * on prof_info_kref. + */ +void spu_set_profile_private_kref(struct spu_context *ctx, + struct kref *prof_info_kref, + void ( * prof_info_release) (struct kref *kref)); + +void *spu_get_profile_private_kref(struct spu_context *ctx); + /* system callbacks from the SPU */ struct spu_syscall_block { u64 nr_ret; @@ -204,18 +238,14 @@ extern long spu_sys_callback(struct spu_syscall_block *s); /* syscalls implemented in spufs */ struct file; -extern struct spufs_calls { - asmlinkage long (*create_thread)(const char __user *name, - unsigned int flags, mode_t mode); - asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc, +struct spufs_calls { + long (*create_thread)(const char __user *name, + unsigned int flags, mode_t mode, + struct file *neighbor); + long (*spu_run)(struct file *filp, __u32 __user *unpc, __u32 __user *ustatus); - struct module *owner; -} spufs_calls; - -/* coredump calls implemented in spufs */ -struct spu_coredump_calls { - asmlinkage int (*arch_notes_size)(void); - asmlinkage void (*arch_write_notes)(struct file *file); + int (*coredump_extra_notes_size)(void); + int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset); struct module *owner; }; @@ -233,25 +263,14 @@ struct spu_coredump_calls { #define SPU_CREATE_GANG 0x0002 #define SPU_CREATE_NOSCHED 0x0004 #define SPU_CREATE_ISOLATE 0x0008 +#define SPU_CREATE_AFFINITY_SPU 0x0010 +#define SPU_CREATE_AFFINITY_MEM 0x0020 -#define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */ +#define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */ -#ifdef CONFIG_SPU_FS_MODULE int register_spu_syscalls(struct spufs_calls *calls); void unregister_spu_syscalls(struct spufs_calls *calls); -#else -static inline int register_spu_syscalls(struct spufs_calls *calls) -{ - return 0; -} -static inline void unregister_spu_syscalls(struct spufs_calls *calls) -{ -} -#endif /* MODULE */ - -int register_arch_coredump_calls(struct spu_coredump_calls *calls); -void unregister_arch_coredump_calls(struct spu_coredump_calls *calls); int spu_add_sysdev_attr(struct sysdev_attribute *attr); void spu_remove_sysdev_attr(struct sysdev_attribute *attr); @@ -403,6 +422,7 @@ struct spu_priv2 { #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) +#define MFC_CNTL_SUSPEND_MASK (1ull << 4) #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h index c48ae185c874..e87794d5d4ea 100644 --- a/include/asm-powerpc/spu_csa.h +++ b/include/asm-powerpc/spu_csa.h @@ -50,6 +50,12 @@ #define SPU_STOPPED_STATUS_P_I 8 #define SPU_STOPPED_STATUS_R 9 +/* + * Definitions for software decrementer status flag. + */ +#define SPU_DECR_STATUS_RUNNING 0x1 +#define SPU_DECR_STATUS_WRAPPED 0x2 + #ifndef __ASSEMBLY__ /** * spu_reg128 - generic 128-bit register definition. @@ -63,7 +69,7 @@ struct spu_reg128 { * @gprs: Array of saved registers. * @fpcr: Saved floating point status control register. * @decr: Saved decrementer value. - * @decr_status: Indicates decrementer run status. + * @decr_status: Indicates software decrementer status flags. * @ppu_mb: Saved PPU mailbox data. * @ppuint_mb: Saved PPU interrupting mailbox data. * @tag_mask: Saved tag group mask. diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h index 7e78f6a1ab8b..0f37c7c90820 100644 --- a/include/asm-powerpc/spu_priv1.h +++ b/include/asm-powerpc/spu_priv1.h @@ -178,6 +178,7 @@ struct spu_management_ops { int (*enumerate_spus)(int (*fn)(void *data)); int (*create_spu)(struct spu *spu, void *data); int (*destroy_spu)(struct spu *spu); + int (*init_affinity)(void); }; extern const struct spu_management_ops* spu_management_ops; @@ -200,6 +201,12 @@ spu_destroy_spu (struct spu *spu) return spu_management_ops->destroy_spu(spu); } +static inline int +spu_init_affinity (void) +{ + return spu_management_ops->init_affinity(); +} + /* * The declarations folowing are put here for convenience * and only intended to be used by the platform setup code. diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h index 1cc3f9cb6f4e..cc6d87228258 100644 --- a/include/asm-powerpc/systbl.h +++ b/include/asm-powerpc/systbl.h @@ -308,6 +308,7 @@ COMPAT_SYS_SPU(move_pages) SYSCALL_SPU(getcpu) COMPAT_SYS(epoll_pwait) COMPAT_SYS_SPU(utimensat) +COMPAT_SYS(fallocate) COMPAT_SYS_SPU(signalfd) COMPAT_SYS_SPU(timerfd) SYSCALL_SPU(eventfd) diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 32aa42b748be..d10e99bf5001 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -184,21 +184,14 @@ struct thread_struct; extern struct task_struct *_switch(struct thread_struct *prev, struct thread_struct *next); -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - extern unsigned int rtas_data; extern int mem_init_done; /* set on boot once kmalloc can be called */ extern unsigned long memory_limit; extern unsigned long klimit; +extern void *alloc_maybe_bootmem(size_t size, gfp_t mask); +extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); + extern int powersave_nap; /* set if nap mode can be used in idle loop */ /* diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h index 9d9aeca8ad22..40d5f98c44fc 100644 --- a/include/asm-powerpc/thread_info.h +++ b/include/asm-powerpc/thread_info.h @@ -107,28 +107,26 @@ static inline struct thread_info *current_thread_info(void) * thread information flag bit numbers */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_32BIT 5 /* 32 bit binary */ -#define TIF_PERFMON_WORK 6 /* work for pfm_handle_work() */ -#define TIF_PERFMON_CTXSW 7 /* perfmon needs ctxsw calls */ -#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */ -#define TIF_SINGLESTEP 9 /* singlestepping active */ -#define TIF_MEMDIE 10 -#define TIF_SECCOMP 11 /* secure computing */ -#define TIF_RESTOREALL 12 /* Restore all regs (implies NOERROR) */ -#define TIF_NOERROR 14 /* Force successful syscall return */ -#define TIF_RESTORE_SIGMASK 15 /* Restore signal mask in do_signal */ -#define TIF_FREEZE 16 /* Freezing for suspend */ -#define TIF_RUNLATCH 17 /* Is the runlatch enabled? */ -#define TIF_ABI_PENDING 18 /* 32/64 bit switch needed */ +#define TIF_32BIT 4 /* 32 bit binary */ +#define TIF_PERFMON_WORK 5 /* work for pfm_handle_work() */ +#define TIF_PERFMON_CTXSW 6 /* perfmon needs ctxsw calls */ +#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ +#define TIF_SINGLESTEP 8 /* singlestepping active */ +#define TIF_MEMDIE 9 +#define TIF_SECCOMP 10 /* secure computing */ +#define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */ +#define TIF_NOERROR 12 /* Force successful syscall return */ +#define TIF_RESTORE_SIGMASK 13 /* Restore signal mask in do_signal */ +#define TIF_FREEZE 14 /* Freezing for suspend */ +#define TIF_RUNLATCH 15 /* Is the runlatch enabled? */ +#define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) @@ -146,7 +144,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) #define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP) -#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \ +#define _TIF_USER_WORK_MASK ( _TIF_SIGPENDING | \ _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK) #define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR) diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h index d7f5ddfbaac7..f05895522f7f 100644 --- a/include/asm-powerpc/time.h +++ b/include/asm-powerpc/time.h @@ -149,6 +149,11 @@ static inline u64 get_tb(void) } #endif /* !CONFIG_PPC64 */ +static inline u64 get_tb_or_rtc(void) +{ + return __USE_RTC() ? get_rtc() : get_tb(); +} + static inline void set_tb(unsigned int upper, unsigned int lower) { mtspr(SPRN_TBWL, 0); @@ -174,7 +179,7 @@ static inline unsigned int get_dec(void) static inline void set_dec(int val) { #if defined(CONFIG_40x) - return; /* Have to let it auto-reload */ + mtspr(SPRN_PIT, val); #elif defined(CONFIG_8xx_CPU6) set_dec_cpu6(val); #else @@ -240,6 +245,7 @@ extern void snapshot_timebases(void); #define snapshot_timebases() do { } while (0) #endif +extern void secondary_cpu_time_init(void); extern void iSeries_time_init_early(void); #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/tlb.h b/include/asm-powerpc/tlb.h index 66714042e438..e20ff7541f36 100644 --- a/include/asm-powerpc/tlb.h +++ b/include/asm-powerpc/tlb.h @@ -23,6 +23,8 @@ #include <asm/mmu.h> #endif +#include <linux/pagemap.h> + struct mmu_gather; #define tlb_start_vma(tlb, vma) do { } while (0) diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h index 99a0439baa50..a022f806bb21 100644 --- a/include/asm-powerpc/tlbflush.h +++ b/include/asm-powerpc/tlbflush.h @@ -97,6 +97,7 @@ struct ppc64_tlb_batch { real_pte_t pte[PPC64_TLB_BATCH_NR]; unsigned long vaddr[PPC64_TLB_BATCH_NR]; unsigned int psize; + int ssize; }; DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); @@ -127,7 +128,7 @@ static inline void arch_leave_lazy_mmu_mode(void) extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize, - int local); + int ssize, int local); extern void flush_hash_range(unsigned long number, int local); diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h index 3b363757a2bb..a584341c87e3 100644 --- a/include/asm-powerpc/types.h +++ b/include/asm-powerpc/types.h @@ -48,7 +48,7 @@ typedef unsigned long long __u64; typedef struct { __u32 u[4]; -} __attribute((aligned(16))) __vector128; +} __attribute__((aligned(16))) __vector128; #endif /* __ASSEMBLY__ */ diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h index afe3076bdc03..46b09ba6bead 100644 --- a/include/asm-powerpc/ucc.h +++ b/include/asm-powerpc/ucc.h @@ -25,58 +25,38 @@ /* Slow or fast type for UCCs. */ enum ucc_speed_type { - UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW -}; - -/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR). -*/ -enum ucc_pram_initial_offset { - UCC_PRAM_OFFSET_UCC1 = 0x8400, - UCC_PRAM_OFFSET_UCC2 = 0x8500, - UCC_PRAM_OFFSET_UCC3 = 0x8600, - UCC_PRAM_OFFSET_UCC4 = 0x9000, - UCC_PRAM_OFFSET_UCC5 = 0x8000, - UCC_PRAM_OFFSET_UCC6 = 0x8100, - UCC_PRAM_OFFSET_UCC7 = 0x8200, - UCC_PRAM_OFFSET_UCC8 = 0x8300 + UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX, + UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX }; /* ucc_set_type * Sets UCC to slow or fast mode. * * ucc_num - (In) number of UCC (0-7). - * regs - (In) pointer to registers base for the UCC. * speed - (In) slow or fast mode for UCC. */ -int ucc_set_type(int ucc_num, struct ucc_common *regs, - enum ucc_speed_type speed); - -/* ucc_init_guemr - * Init the Guemr register. - * - * regs - (In) pointer to registers base for the UCC. - */ -int ucc_init_guemr(struct ucc_common *regs); +int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed); -int ucc_set_qe_mux_mii_mng(int ucc_num); +int ucc_set_qe_mux_mii_mng(unsigned int ucc_num); -int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode); +int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, + enum comm_dir mode); -int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask); +int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask); /* QE MUX clock routing for UCC */ -static inline int ucc_set_qe_mux_grant(int ucc_num, int set) +static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set) { return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT); } -static inline int ucc_set_qe_mux_tsa(int ucc_num, int set) +static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set) { return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA); } -static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set) +static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set) { return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT); } diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h index fdaac9d762bb..0980e6ad335b 100644 --- a/include/asm-powerpc/ucc_slow.h +++ b/include/asm-powerpc/ucc_slow.h @@ -148,9 +148,10 @@ enum ucc_slow_diag_mode { struct ucc_slow_info { int ucc_num; + int protocol; /* QE_CR_PROTOCOL_xxx */ enum qe_clock rx_clock; enum qe_clock tx_clock; - u32 regs; + phys_addr_t regs; int irq; u16 uccm_mask; int data_mem_part; @@ -186,7 +187,7 @@ struct ucc_slow_info { struct ucc_slow_private { struct ucc_slow_info *us_info; - struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */ + struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */ struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */ u32 us_pram_offset; int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ @@ -277,12 +278,12 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs); */ void ucc_slow_stop_tx(struct ucc_slow_private * uccs); -/* ucc_slow_restart_x +/* ucc_slow_restart_tx * Restarts transmitting on a specified slow UCC. * * uccs - (In) pointer to the slow UCC structure. */ -void ucc_slow_restart_x(struct ucc_slow_private * uccs); +void ucc_slow_restart_tx(struct ucc_slow_private *uccs); u32 ucc_slow_get_qe_cr_subblock(int uccs_num); diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h index ce9d82fb7b68..a9e0b0ebcb0f 100644 --- a/include/asm-powerpc/udbg.h +++ b/include/asm-powerpc/udbg.h @@ -48,6 +48,7 @@ extern void __init udbg_init_rtas_console(void); extern void __init udbg_init_debug_beat(void); extern void __init udbg_init_btext(void); extern void __init udbg_init_44x_as1(void); +extern void __init udbg_init_cpm(void); #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_UDBG_H */ diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h index f71c6061f1ec..97d82b6a9406 100644 --- a/include/asm-powerpc/unistd.h +++ b/include/asm-powerpc/unistd.h @@ -331,10 +331,11 @@ #define __NR_timerfd 306 #define __NR_eventfd 307 #define __NR_sync_file_range2 308 +#define __NR_fallocate 309 #ifdef __KERNEL__ -#define __NR_syscalls 309 +#define __NR_syscalls 310 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h index 0117b544ecbc..9204c15839c5 100644 --- a/include/asm-powerpc/vio.h +++ b/include/asm-powerpc/vio.h @@ -53,18 +53,12 @@ struct vio_dev { }; struct vio_driver { - struct list_head node; const struct vio_device_id *id_table; int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); int (*remove)(struct vio_dev *dev); - void (*shutdown)(struct vio_dev *dev); - unsigned long driver_data; struct device_driver driver; }; -extern struct dma_mapping_ops vio_dma_ops; -extern struct bus_type vio_bus_type; - extern int vio_register_driver(struct vio_driver *drv); extern void vio_unregister_driver(struct vio_driver *drv); @@ -80,6 +74,11 @@ extern const void *vio_get_attribute(struct vio_dev *vdev, char *which, extern struct vio_dev *vio_find_node(struct device_node *vnode); extern int vio_enable_interrupts(struct vio_dev *dev); extern int vio_disable_interrupts(struct vio_dev *dev); +#else +static inline int vio_enable_interrupts(struct vio_dev *dev) +{ + return 0; +} #endif static inline struct vio_driver *to_vio_driver(struct device_driver *drv) diff --git a/include/asm-powerpc/xilinx_intc.h b/include/asm-powerpc/xilinx_intc.h new file mode 100644 index 000000000000..343612f8fece --- /dev/null +++ b/include/asm-powerpc/xilinx_intc.h @@ -0,0 +1,20 @@ +/* + * Xilinx intc external definitions + * + * Copyright 2007 Secret Lab Technologies Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ASM_POWERPC_XILINX_INTC_H +#define _ASM_POWERPC_XILINX_INTC_H + +#ifdef __KERNEL__ + +extern void __init xilinx_intc_init_tree(void); +extern unsigned int xilinx_intc_get_irq(void); + +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_XILINX_INTC_H */ diff --git a/include/asm-ppc/amigahw.h b/include/asm-ppc/amigahw.h deleted file mode 100644 index 90fd1274d727..000000000000 --- a/include/asm-ppc/amigahw.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifdef __KERNEL__ -#ifndef __ASMPPC_AMIGAHW_H -#define __ASMPPC_AMIGAHW_H - -#include <asm-m68k/amigahw.h> - -#undef CHIP_PHYSADDR -#ifdef CONFIG_APUS_FAST_EXCEPT -#define CHIP_PHYSADDR (0x000000) -#else -#define CHIP_PHYSADDR (0x004000) -#endif - - -#endif /* __ASMPPC_AMIGAHW_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/amigaints.h b/include/asm-ppc/amigaints.h deleted file mode 100644 index aa3ff6349e81..000000000000 --- a/include/asm-ppc/amigaints.h +++ /dev/null @@ -1,133 +0,0 @@ -/* -** amigaints.h -- Amiga Linux interrupt handling structs and prototypes -** -** Copyright 1992 by Greg Harp -** -** This file is subject to the terms and conditions of the GNU General Public -** License. See the file COPYING in the main directory of this archive -** for more details. -** -** Created 10/2/92 by Greg Harp -*/ - -#ifdef __KERNEL__ -#ifndef _ASMm68k_AMIGAINTS_H_ -#define _ASMm68k_AMIGAINTS_H_ - -/* -** Amiga Interrupt sources. -** -*/ - -#define AUTO_IRQS (8) -#define AMI_STD_IRQS (14) -#define CIA_IRQS (5) -#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */ - -/* vertical blanking interrupt */ -#define IRQ_AMIGA_VERTB 0 - -/* copper interrupt */ -#define IRQ_AMIGA_COPPER 1 - -/* Audio interrupts */ -#define IRQ_AMIGA_AUD0 2 -#define IRQ_AMIGA_AUD1 3 -#define IRQ_AMIGA_AUD2 4 -#define IRQ_AMIGA_AUD3 5 - -/* Blitter done interrupt */ -#define IRQ_AMIGA_BLIT 6 - -/* floppy disk interrupts */ -#define IRQ_AMIGA_DSKSYN 7 -#define IRQ_AMIGA_DSKBLK 8 - -/* builtin serial port interrupts */ -#define IRQ_AMIGA_RBF 9 -#define IRQ_AMIGA_TBE 10 - -/* software interrupts */ -#define IRQ_AMIGA_SOFT 11 - -/* interrupts from external hardware */ -#define IRQ_AMIGA_PORTS 12 -#define IRQ_AMIGA_EXTER 13 - -/* CIA interrupt sources */ -#define IRQ_AMIGA_CIAA 14 -#define IRQ_AMIGA_CIAA_TA 14 -#define IRQ_AMIGA_CIAA_TB 15 -#define IRQ_AMIGA_CIAA_ALRM 16 -#define IRQ_AMIGA_CIAA_SP 17 -#define IRQ_AMIGA_CIAA_FLG 18 -#define IRQ_AMIGA_CIAB 19 -#define IRQ_AMIGA_CIAB_TA 19 -#define IRQ_AMIGA_CIAB_TB 20 -#define IRQ_AMIGA_CIAB_ALRM 21 -#define IRQ_AMIGA_CIAB_SP 22 -#define IRQ_AMIGA_CIAB_FLG 23 - -/* auto-vector interrupts */ -#define IRQ_AMIGA_AUTO 24 -#define IRQ_AMIGA_AUTO_0 24 /* This is just a dummy */ -#define IRQ_AMIGA_AUTO_1 25 -#define IRQ_AMIGA_AUTO_2 26 -#define IRQ_AMIGA_AUTO_3 27 -#define IRQ_AMIGA_AUTO_4 28 -#define IRQ_AMIGA_AUTO_5 29 -#define IRQ_AMIGA_AUTO_6 30 -#define IRQ_AMIGA_AUTO_7 31 - -#define IRQ_FLOPPY IRQ_AMIGA_DSKBLK - -/* INTREQR masks */ -#define IRQ1_MASK 0x0007 /* INTREQR mask for IRQ 1 */ -#define IRQ2_MASK 0x0008 /* INTREQR mask for IRQ 2 */ -#define IRQ3_MASK 0x0070 /* INTREQR mask for IRQ 3 */ -#define IRQ4_MASK 0x0780 /* INTREQR mask for IRQ 4 */ -#define IRQ5_MASK 0x1800 /* INTREQR mask for IRQ 5 */ -#define IRQ6_MASK 0x2000 /* INTREQR mask for IRQ 6 */ -#define IRQ7_MASK 0x4000 /* INTREQR mask for IRQ 7 */ - -#define IF_SETCLR 0x8000 /* set/clr bit */ -#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */ -#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */ -#define IF_DSKSYN 0x1000 /* disk sync interrupt */ -#define IF_RBF 0x0800 /* serial receive buffer full interrupt */ -#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */ -#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */ -#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */ -#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */ -#define IF_BLIT 0x0040 /* blitter done interrupt */ -#define IF_VERTB 0x0020 /* vertical blanking interrupt */ -#define IF_COPER 0x0010 /* copper interrupt */ -#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */ -#define IF_SOFT 0x0004 /* software initiated interrupt */ -#define IF_DSKBLK 0x0002 /* diskblock DMA finished */ -#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */ - -extern void amiga_do_irq(int irq, struct pt_regs *fp); -extern void amiga_do_irq_list(int irq, struct pt_regs *fp); - -/* CIA interrupt control register bits */ - -#define CIA_ICR_TA 0x01 -#define CIA_ICR_TB 0x02 -#define CIA_ICR_ALRM 0x04 -#define CIA_ICR_SP 0x08 -#define CIA_ICR_FLG 0x10 -#define CIA_ICR_ALL 0x1f -#define CIA_ICR_SETCLR 0x80 - -/* to access the interrupt control registers of CIA's use only -** these functions, they behave exactly like the amiga os routines -*/ - -extern struct ciabase ciaa_base, ciab_base; - -extern unsigned char cia_set_irq(unsigned int irq, int set); -extern unsigned char cia_able_irq(unsigned int irq, int enable); - -#endif /* asm-m68k/amigaints.h */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h deleted file mode 100644 index 35114ce5135f..000000000000 --- a/include/asm-ppc/amigappc.h +++ /dev/null @@ -1,85 +0,0 @@ -/* -** asm-ppc/amigappc.h -- This header defines some values and pointers for -** the Phase 5 PowerUp card. -** -** Copyright 1997, 1998 by Phase5, Germany. -** -** This file is subject to the terms and conditions of the GNU General Public -** License. See the file COPYING in the main directory of this archive -** for more details. -** -** Created: 7/22/97 by Jesper Skov -*/ - -#ifdef __KERNEL__ -#ifndef _M68K_AMIGAPPC_H -#define _M68K_AMIGAPPC_H - -#ifndef __ASSEMBLY__ - -/* #include <asm/system.h> */ -#define mb() __asm__ __volatile__ ("sync" : : : "memory") - -#define APUS_WRITE(_a_, _v_) \ -do { \ - (*((volatile unsigned char *)(_a_)) = (_v_)); \ - mb(); \ -} while (0) - -#define APUS_READ(_a_, _v_) \ -do { \ - (_v_) = (*((volatile unsigned char *)(_a_))); \ - mb(); \ -} while (0) -#endif /* ndef __ASSEMBLY__ */ - -/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */ -#define zTwoBase (0x80000000) - -#define APUS_IPL_BASE (zTwoBase + 0x00f60000) -#define APUS_REG_RESET (APUS_IPL_BASE + 0x00) -#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10) -#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18) -#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20) -#define APUS_REG_INT (APUS_IPL_BASE + 0x28) -#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30) -#define APUS_INT_LVL (APUS_IPL_BASE + 0x38) - -#define REGSHADOW_SETRESET (0x80) -#define REGSHADOW_SELFRESET (0x40) - -#define REGLOCK_SETRESET (0x80) -#define REGLOCK_BLACKMAGICK1 (0x40) -#define REGLOCK_BLACKMAGICK2 (0x20) -#define REGLOCK_BLACKMAGICK3 (0x10) - -#define REGWAITSTATE_SETRESET (0x80) -#define REGWAITSTATE_PPCW (0x08) -#define REGWAITSTATE_PPCR (0x04) - -#define REGRESET_SETRESET (0x80) -#define REGRESET_PPCRESET (0x10) -#define REGRESET_M68KRESET (0x08) -#define REGRESET_AMIGARESET (0x04) -#define REGRESET_AUXRESET (0x02) -#define REGRESET_SCSIRESET (0x01) - -#define REGINT_SETRESET (0x80) -#define REGINT_ENABLEIPL (0x02) -#define REGINT_INTMASTER (0x01) - -#define IPLEMU_SETRESET (0x80) -#define IPLEMU_DISABLEINT (0x40) -#define IPLEMU_IPL2 (0x20) -#define IPLEMU_IPL1 (0x10) -#define IPLEMU_IPL0 (0x08) -#define IPLEMU_PPCIPL2 (0x04) -#define IPLEMU_PPCIPL1 (0x02) -#define IPLEMU_PPCIPL0 (0x01) -#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0) - -#define INTLVL_SETRESET (0x80) -#define INTLVL_MASK (0x7f) - -#endif /* _M68k_AMIGAPPC_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ans-lcd.h b/include/asm-ppc/ans-lcd.h deleted file mode 100644 index d795b9fd2db6..000000000000 --- a/include/asm-ppc/ans-lcd.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _PPC_ANS_LCD_H -#define _PPC_ANS_LCD_H - -#define ANSLCD_MINOR 156 - -#define ANSLCD_CLEAR 0x01 -#define ANSLCD_SENDCTRL 0x02 -#define ANSLCD_SETSHORTDELAY 0x03 -#define ANSLCD_SETLONGDELAY 0x04 - -#endif diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h index 2ace4a74f263..f6ed77aee328 100644 --- a/include/asm-ppc/bootinfo.h +++ b/include/asm-ppc/bootinfo.h @@ -11,10 +11,6 @@ #include <asm/page.h> -#if defined(CONFIG_APUS) && !defined(__BOOTER__) -#include <asm-m68k/bootinfo.h> -#else - struct bi_record { unsigned long tag; /* tag ID */ unsigned long size; /* size of record (in bytes) */ @@ -44,7 +40,6 @@ bootinfo_addr(unsigned long offset) return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, (1 << 20)); } -#endif /* CONFIG_APUS */ #endif /* _PPC_BOOTINFO_H */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 95d590423cf2..8f58231a8bc6 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -30,7 +30,7 @@ #include <asm/mpc8xx.h> #elif defined(CONFIG_8260) #include <asm/mpc8260.h> -#elif defined(CONFIG_APUS) || !defined(CONFIG_PCI) +#elif !defined(CONFIG_PCI) #define _IO_BASE 0 #define _ISA_MEM_BASE 0 #define PCI_DRAM_OFFSET 0 @@ -145,24 +145,7 @@ static inline void writeb(__u8 b, volatile void __iomem *addr) } #endif -#if defined(CONFIG_APUS) -static inline __u16 readw(const volatile void __iomem *addr) -{ - return *(__force volatile __u16 *)(addr); -} -static inline __u32 readl(const volatile void __iomem *addr) -{ - return *(__force volatile __u32 *)(addr); -} -static inline void writew(__u16 b, volatile void __iomem *addr) -{ - *(__force volatile __u16 *)(addr) = b; -} -static inline void writel(__u32 b, volatile void __iomem *addr) -{ - *(__force volatile __u32 *)(addr) = b; -} -#elif defined (CONFIG_8260_PCI9) +#if defined (CONFIG_8260_PCI9) /* Use macros if PCI9 workaround enabled */ #define readw(addr) in_le16((volatile u16 *)(addr)) #define readl(addr) in_le32((volatile u32 *)(addr)) @@ -185,7 +168,7 @@ static inline void writel(__u32 b, volatile void __iomem *addr) { out_le32(addr, b); } -#endif /* CONFIG_APUS */ +#endif /* CONFIG_8260_PCI9 */ #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) @@ -300,13 +283,7 @@ extern __inline__ void name(unsigned int val, unsigned int port) \ } __do_out_asm(outb, "stbx") -#ifdef CONFIG_APUS -__do_in_asm(inb, "lbzx") -__do_in_asm(inw, "lhz%U1%X1") -__do_in_asm(inl, "lwz%U1%X1") -__do_out_asm(outl,"stw%U0%X0") -__do_out_asm(outw, "sth%U0%X0") -#elif defined (CONFIG_8260_PCI9) +#if defined (CONFIG_8260_PCI9) /* in asm cannot be defined if PCI9 workaround is used */ #define inb(port) in_8((port)+___IO_BASE) #define inw(port) in_le16((port)+___IO_BASE) @@ -371,7 +348,6 @@ extern void __iomem *ioremap64(unsigned long long address, unsigned long size); #define ioremap_nocache(addr, size) ioremap((addr), (size)) extern void iounmap(volatile void __iomem *addr); extern unsigned long iopa(unsigned long addr); -extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; extern void io_block_mapping(unsigned long virt, phys_addr_t phys, unsigned int size, int flags); @@ -384,24 +360,16 @@ extern void io_block_mapping(unsigned long virt, phys_addr_t phys, */ extern inline unsigned long virt_to_bus(volatile void * address) { -#ifndef CONFIG_APUS if (address == (void *)0) return 0; return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; -#else - return iopa ((unsigned long) address); -#endif } extern inline void * bus_to_virt(unsigned long address) { -#ifndef CONFIG_APUS if (address == 0) return NULL; return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); -#else - return (void*) mm_ptov (address); -#endif } /* @@ -410,20 +378,12 @@ extern inline void * bus_to_virt(unsigned long address) */ extern inline unsigned long virt_to_phys(volatile void * address) { -#ifndef CONFIG_APUS return (unsigned long) address - KERNELBASE; -#else - return iopa ((unsigned long) address); -#endif } extern inline void * phys_to_virt(unsigned long address) { -#ifndef CONFIG_APUS return (void *) (address + KERNELBASE); -#else - return (void*) mm_ptov (address); -#endif } /* @@ -553,4 +513,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *); #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h index 293a444a1d77..a20b499b0186 100644 --- a/include/asm-ppc/machdep.h +++ b/include/asm-ppc/machdep.h @@ -8,10 +8,6 @@ #include <asm/setup.h> #include <asm/page.h> -#ifdef CONFIG_APUS -#include <asm-m68k/machdep.h> -#endif - struct pt_regs; struct pci_bus; struct pci_dev; diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h index db3776f18198..2963d6aa3ea5 100644 --- a/include/asm-ppc/mv64x60.h +++ b/include/asm-ppc/mv64x60.h @@ -120,14 +120,6 @@ extern spinlock_t mv64x60_lock; #define MV64x60_64BIT_WIN_COUNT 24 -/* Watchdog Platform Device, Driver Data */ -#define MV64x60_WDT_NAME "wdt" - -struct mv64x60_wdt_pdata { - int timeout; /* watchdog expiry in seconds, default 10 */ - int bus_clk; /* bus clock in MHz, default 133 */ -}; - /* * Define a structure that's used to pass in config information to the * core routines. diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h index 16dbc7d17450..1379a4f76de3 100644 --- a/include/asm-ppc/ocp.h +++ b/include/asm-ppc/ocp.h @@ -27,10 +27,10 @@ #include <linux/init.h> #include <linux/list.h> #include <linux/device.h> +#include <linux/rwsem.h> #include <asm/mmu.h> #include <asm/ocp_ids.h> -#include <asm/rwsem.h> #include <asm/semaphore.h> #ifdef CONFIG_PPC_OCP diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h index fe95c8258cf9..ad4c5a1bc9d6 100644 --- a/include/asm-ppc/page.h +++ b/include/asm-ppc/page.h @@ -97,62 +97,22 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *pg); -#ifndef CONFIG_APUS #define PPC_MEMSTART 0 -#define PPC_PGSTART 0 #define PPC_MEMOFFSET PAGE_OFFSET -#else -extern unsigned long ppc_memstart; -extern unsigned long ppc_pgstart; -extern unsigned long ppc_memoffset; -#define PPC_MEMSTART ppc_memstart -#define PPC_PGSTART ppc_pgstart -#define PPC_MEMOFFSET ppc_memoffset -#endif -#if defined(CONFIG_APUS) && !defined(MODULE) -/* map phys->virtual and virtual->phys for RAM pages */ -static inline unsigned long ___pa(unsigned long v) -{ - unsigned long p; - asm volatile ("1: addis %0, %1, %2;" - ".section \".vtop_fixup\",\"aw\";" - ".align 1;" - ".long 1b;" - ".previous;" - : "=r" (p) - : "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff)); - - return p; -} -static inline void* ___va(unsigned long p) -{ - unsigned long v; - asm volatile ("1: addis %0, %1, %2;" - ".section \".ptov_fixup\",\"aw\";" - ".align 1;" - ".long 1b;" - ".previous;" - : "=r" (v) - : "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff)); - - return (void*) v; -} -#else #define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) #define ___va(paddr) ((paddr)+PPC_MEMOFFSET) -#endif extern int page_is_ram(unsigned long pfn); #define __pa(x) ___pa((unsigned long)(x)) #define __va(x) ((void *)(___va((unsigned long)(x)))) -#define ARCH_PFN_OFFSET (PPC_PGSTART) +#define ARCH_PFN_OFFSET 0 #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) -#define pfn_valid(pfn) (((pfn) - PPC_PGSTART) < max_mapnr) +#define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) /* Pure 2^n version of get_order */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index c159315d2c8f..063ad91cbbcc 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -765,14 +765,6 @@ extern void paging_init(void); #define pte_to_pgoff(pte) (pte_val(pte) >> 3) #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) -/* CONFIG_APUS */ -/* For virtual address to physical address conversion */ -extern void cache_clear(__u32 addr, int length); -extern void cache_push(__u32 addr, int length); -extern int mm_end_of_chunk (unsigned long addr, int len); -extern unsigned long iopa(unsigned long addr); -extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; - /* Values for nocacheflag and cmode */ /* These are not used by the APUS kernel_map, but prevents compilation errors. */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h index 901f7fa8b2d7..71f4c996fe75 100644 --- a/include/asm-ppc/prom.h +++ b/include/asm-ppc/prom.h @@ -35,7 +35,6 @@ extern unsigned long sub_reloc_offset(unsigned long); #define machine_is_compatible(x) 0 #define of_find_compatible_node(f, t, c) NULL #define of_get_property(p, n, l) NULL -#define get_property(a, b, c) of_get_property((a), (b), (c)) #endif /* _PPC_PROM_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index d84a3cf4d033..cc45780421ca 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -54,6 +54,7 @@ extern void show_regs(struct pt_regs * regs); extern void flush_instruction_cache(void); extern void hard_reset_now(void); extern void poweroff_now(void); +extern int set_dabr(unsigned long dabr); #ifdef CONFIG_6xx extern long _get_L2CR(void); extern long _get_L3CR(void); @@ -129,16 +130,6 @@ extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - struct thread_struct; extern struct task_struct *_switch(struct thread_struct *prev, struct thread_struct *next); diff --git a/include/asm-s390/a.out.h b/include/asm-s390/a.out.h index 72adee6ef338..46158dcaf517 100644 --- a/include/asm-s390/a.out.h +++ b/include/asm-s390/a.out.h @@ -32,6 +32,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX DEFAULT_TASK_SIZE #endif diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h index ea486952f778..2d184655bc5d 100644 --- a/include/asm-s390/atomic.h +++ b/include/asm-s390/atomic.h @@ -67,8 +67,17 @@ typedef struct { #endif /* __GNUC__ */ -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) +static inline int atomic_read(const atomic_t *v) +{ + barrier(); + return v->counter; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + v->counter = i; + barrier(); +} static __inline__ int atomic_add_return(int i, atomic_t * v) { @@ -182,8 +191,17 @@ typedef struct { #endif /* __GNUC__ */ -#define atomic64_read(v) ((v)->counter) -#define atomic64_set(v,i) (((v)->counter) = (i)) +static inline long long atomic64_read(const atomic64_t *v) +{ + barrier(); + return v->counter; +} + +static inline void atomic64_set(atomic64_t *v, long long i) +{ + v->counter = i; + barrier(); +} static __inline__ long long atomic64_add_return(long long i, atomic64_t * v) { diff --git a/include/asm-s390/bug.h b/include/asm-s390/bug.h index 838684dc6d35..384e3621e341 100644 --- a/include/asm-s390/bug.h +++ b/include/asm-s390/bug.h @@ -50,7 +50,7 @@ #define BUG() __EMIT_BUG(0) #define WARN_ON(x) ({ \ - typeof(x) __ret_warn_on = (x); \ + int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ __EMIT_BUG(BUGFLAG_WARNING); \ diff --git a/include/asm-s390/cache.h b/include/asm-s390/cache.h index cdf431b061bb..9b866816863c 100644 --- a/include/asm-s390/cache.h +++ b/include/asm-s390/cache.h @@ -14,8 +14,6 @@ #define L1_CACHE_BYTES 256 #define L1_CACHE_SHIFT 8 -#define ARCH_KMALLOC_MINALIGN 8 - #define __read_mostly __attribute__((__section__(".data.read_mostly"))) #endif diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h index 4c2e1710f157..066aa70518ce 100644 --- a/include/asm-s390/ccwdev.h +++ b/include/asm-s390/ccwdev.h @@ -67,36 +67,55 @@ ccw_device_id_match(const struct ccw_device_id *array, return NULL; } -/* The struct ccw device is our replacement for the globally accessible - * ioinfo array. ioinfo will mutate into a subchannel device later. +/** + * struct ccw_device - channel attached device + * @ccwlock: pointer to device lock + * @id: id of this device + * @drv: ccw driver for this device + * @dev: embedded device structure + * @online: online status of device + * @handler: interrupt handler * - * Reference: Documentation/s390/driver-model.txt */ + * @handler is a member of the device rather than the driver since a driver + * can have different interrupt handlers for different ccw devices + * (multi-subchannel drivers). + */ struct ccw_device { spinlock_t *ccwlock; +/* private: */ struct ccw_device_private *private; /* cio private information */ - struct ccw_device_id id; /* id of this device, driver_info is - set by ccw_find_driver */ - struct ccw_driver *drv; /* */ - struct device dev; /* */ +/* public: */ + struct ccw_device_id id; + struct ccw_driver *drv; + struct device dev; int online; - /* This is sick, but a driver can have different interrupt handlers - for different ccw_devices (multi-subchannel drivers)... */ void (*handler) (struct ccw_device *, unsigned long, struct irb *); }; -/* Each ccw driver registers with the ccw root bus */ +/** + * struct ccw driver - device driver for channel attached devices + * @owner: owning module + * @ids: ids supported by this driver + * @probe: function called on probe + * @remove: function called on remove + * @set_online: called when setting device online + * @set_offline: called when setting device offline + * @notify: notify driver of device state changes + * @shutdown: called at device shutdown + * @driver: embedded device driver structure + * @name: device driver name + */ struct ccw_driver { - struct module *owner; /* for automatic MOD_INC_USE_COUNT */ - struct ccw_device_id *ids; /* probe driver with these devs */ - int (*probe) (struct ccw_device *); /* ask driver to probe dev */ + struct module *owner; + struct ccw_device_id *ids; + int (*probe) (struct ccw_device *); void (*remove) (struct ccw_device *); - /* device is no longer available */ int (*set_online) (struct ccw_device *); int (*set_offline) (struct ccw_device *); int (*notify) (struct ccw_device *, int); - struct device_driver driver; /* higher level structure, don't init - this from your driver */ + void (*shutdown) (struct ccw_device *); + struct device_driver driver; char *name; }; @@ -124,36 +143,10 @@ extern void ccw_device_clear_options(struct ccw_device *, unsigned long); /* Allow forced onlining of boxed devices. */ #define CCWDEV_ALLOW_FORCE 0x0008 -/* - * ccw_device_start() - * - * Start a S/390 channel program. When the interrupt arrives, the - * IRQ handler is called, either immediately, delayed (dev-end missing, - * or sense required) or never (no IRQ handler registered). - * Depending on the action taken, ccw_device_start() returns: - * 0 - Success - * -EBUSY - Device busy, or status pending - * -ENODEV - Device not operational - * -EINVAL - Device invalid for operation - */ extern int ccw_device_start(struct ccw_device *, struct ccw1 *, unsigned long, __u8, unsigned long); -/* - * ccw_device_start_timeout() - * - * This function notifies the device driver if the channel program has not - * completed during the specified time. If a timeout occurs, the channel - * program is terminated via xsch(), hsch() or csch(). - */ extern int ccw_device_start_timeout(struct ccw_device *, struct ccw1 *, unsigned long, __u8, unsigned long, int); -/* - * ccw_device_start_key() - * ccw_device_start_key_timeout() - * - * Same as ccw_device_start() and ccw_device_start_timeout(), except a - * storage key != default key can be provided for the I/O. - */ extern int ccw_device_start_key(struct ccw_device *, struct ccw1 *, unsigned long, __u8, __u8, unsigned long); extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *, @@ -165,11 +158,6 @@ extern int ccw_device_resume(struct ccw_device *); extern int ccw_device_halt(struct ccw_device *, unsigned long); extern int ccw_device_clear(struct ccw_device *, unsigned long); -extern int __deprecated read_dev_chars(struct ccw_device *cdev, void **buffer, int length); -extern int __deprecated read_conf_data(struct ccw_device *cdev, void **buffer, int *length); -extern int __deprecated read_conf_data_lpm(struct ccw_device *cdev, void **buffer, - int *length, __u8 lpm); - extern int ccw_device_set_online(struct ccw_device *cdev); extern int ccw_device_set_offline(struct ccw_device *cdev); diff --git a/include/asm-s390/ccwgroup.h b/include/asm-s390/ccwgroup.h index 925b3ddfa141..7109c7cab87e 100644 --- a/include/asm-s390/ccwgroup.h +++ b/include/asm-s390/ccwgroup.h @@ -4,19 +4,41 @@ struct ccw_device; struct ccw_driver; +/** + * struct ccwgroup_device - ccw group device + * @creator_id: unique number of the driver + * @state: online/offline state + * @count: number of attached slave devices + * @dev: embedded device structure + * @cdev: variable number of slave devices, allocated as needed + */ struct ccwgroup_device { - unsigned long creator_id; /* unique number of the driver */ + unsigned long creator_id; enum { CCWGROUP_OFFLINE, CCWGROUP_ONLINE, } state; +/* private: */ atomic_t onoff; struct mutex reg_mutex; - unsigned int count; /* number of attached slave devices */ - struct device dev; /* master device */ - struct ccw_device *cdev[0]; /* variable number, allocate as needed */ +/* public: */ + unsigned int count; + struct device dev; + struct ccw_device *cdev[0]; }; +/** + * struct ccwgroup_driver - driver for ccw group devices + * @owner: driver owner + * @name: driver name + * @max_slaves: maximum number of slave devices + * @driver_id: unique id + * @probe: function called on probe + * @remove: function called on remove + * @set_online: function called when device is set online + * @set_offline: function called when device is set offline + * @driver: embedded driver structure + */ struct ccwgroup_driver { struct module *owner; char *name; @@ -28,7 +50,7 @@ struct ccwgroup_driver { int (*set_online) (struct ccwgroup_device *); int (*set_offline) (struct ccwgroup_device *); - struct device_driver driver; /* this driver */ + struct device_driver driver; }; extern int ccwgroup_driver_register (struct ccwgroup_driver *cdriver); diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h index f738d2827582..2f08c16e44ad 100644 --- a/include/asm-s390/cio.h +++ b/include/asm-s390/cio.h @@ -15,30 +15,50 @@ #define LPM_ANYPATH 0xff #define __MAX_CSSID 0 -/* - * subchannel status word +/** + * struct scsw - subchannel status word + * @key: subchannel key + * @sctl: suspend control + * @eswf: esw format + * @cc: deferred condition code + * @fmt: format + * @pfch: prefetch + * @isic: initial-status interruption control + * @alcc: adress-limit checking control + * @ssi: supress-suspended interruption + * @zcc: zero condition code + * @ectl: extended control + * @pno: path not operational + * @res: reserved + * @fctl: function control + * @actl: activity control + * @stctl: status control + * @cpa: channel program address + * @dstat: device status + * @cstat: subchannel status + * @count: residual count */ struct scsw { - __u32 key : 4; /* subchannel key */ - __u32 sctl : 1; /* suspend control */ - __u32 eswf : 1; /* ESW format */ - __u32 cc : 2; /* deferred condition code */ - __u32 fmt : 1; /* format */ - __u32 pfch : 1; /* prefetch */ - __u32 isic : 1; /* initial-status interruption control */ - __u32 alcc : 1; /* address-limit checking control */ - __u32 ssi : 1; /* supress-suspended interruption */ - __u32 zcc : 1; /* zero condition code */ - __u32 ectl : 1; /* extended control */ - __u32 pno : 1; /* path not operational */ - __u32 res : 1; /* reserved */ - __u32 fctl : 3; /* function control */ - __u32 actl : 7; /* activity control */ - __u32 stctl : 5; /* status control */ - __u32 cpa; /* channel program address */ - __u32 dstat : 8; /* device status */ - __u32 cstat : 8; /* subchannel status */ - __u32 count : 16; /* residual count */ + __u32 key : 4; + __u32 sctl : 1; + __u32 eswf : 1; + __u32 cc : 2; + __u32 fmt : 1; + __u32 pfch : 1; + __u32 isic : 1; + __u32 alcc : 1; + __u32 ssi : 1; + __u32 zcc : 1; + __u32 ectl : 1; + __u32 pno : 1; + __u32 res : 1; + __u32 fctl : 3; + __u32 actl : 7; + __u32 stctl : 5; + __u32 cpa; + __u32 dstat : 8; + __u32 cstat : 8; + __u32 count : 16; } __attribute__ ((packed)); #define SCSW_FCTL_CLEAR_FUNC 0x1 @@ -110,11 +130,22 @@ struct scsw { #define SNS2_ENV_DATA_PRESENT 0x10 #define SNS2_INPRECISE_END 0x04 +/** + * struct ccw1 - channel command word + * @cmd_code: command code + * @flags: flags, like IDA adressing, etc. + * @count: byte count + * @cda: data address + * + * The ccw is the basic structure to build channel programs that perform + * operations with the device or the control unit. Only Format-1 channel + * command words are supported. + */ struct ccw1 { - __u8 cmd_code; /* command code */ - __u8 flags; /* flags, like IDA addressing, etc. */ - __u16 count; /* byte count */ - __u32 cda; /* data address */ + __u8 cmd_code; + __u8 flags; + __u16 count; + __u32 cda; } __attribute__ ((packed,aligned(8))); #define CCW_FLAG_DC 0x80 @@ -140,102 +171,162 @@ struct ccw1 { #define SENSE_MAX_COUNT 0x20 +/** + * struct erw - extended report word + * @res0: reserved + * @auth: authorization check + * @pvrf: path-verification-required flag + * @cpt: channel-path timeout + * @fsavf: failing storage address validity flag + * @cons: concurrent sense + * @scavf: secondary ccw address validity flag + * @fsaf: failing storage address format + * @scnt: sense count, if @cons == %1 + * @res16: reserved + */ struct erw { - __u32 res0 : 3; /* reserved */ - __u32 auth : 1; /* Authorization check */ - __u32 pvrf : 1; /* path-verification-required flag */ - __u32 cpt : 1; /* channel-path timeout */ - __u32 fsavf : 1; /* Failing storage address validity flag */ - __u32 cons : 1; /* concurrent-sense */ - __u32 scavf : 1; /* Secondary ccw address validity flag */ - __u32 fsaf : 1; /* Failing storage address format */ - __u32 scnt : 6; /* sense count if cons == 1 */ - __u32 res16 : 16; /* reserved */ + __u32 res0 : 3; + __u32 auth : 1; + __u32 pvrf : 1; + __u32 cpt : 1; + __u32 fsavf : 1; + __u32 cons : 1; + __u32 scavf : 1; + __u32 fsaf : 1; + __u32 scnt : 6; + __u32 res16 : 16; } __attribute__ ((packed)); -/* - * subchannel logout area +/** + * struct sublog - subchannel logout area + * @res0: reserved + * @esf: extended status flags + * @lpum: last path used mask + * @arep: ancillary report + * @fvf: field-validity flags + * @sacc: storage access code + * @termc: termination code + * @devsc: device-status check + * @serr: secondary error + * @ioerr: i/o-error alert + * @seqc: sequence code */ struct sublog { - __u32 res0 : 1; /* reserved */ - __u32 esf : 7; /* extended status flags */ - __u32 lpum : 8; /* last path used mask */ - __u32 arep : 1; /* ancillary report */ - __u32 fvf : 5; /* field-validity flags */ - __u32 sacc : 2; /* storage access code */ - __u32 termc : 2; /* termination code */ - __u32 devsc : 1; /* device-status check */ - __u32 serr : 1; /* secondary error */ - __u32 ioerr : 1; /* i/o-error alert */ - __u32 seqc : 3; /* sequence code */ + __u32 res0 : 1; + __u32 esf : 7; + __u32 lpum : 8; + __u32 arep : 1; + __u32 fvf : 5; + __u32 sacc : 2; + __u32 termc : 2; + __u32 devsc : 1; + __u32 serr : 1; + __u32 ioerr : 1; + __u32 seqc : 3; } __attribute__ ((packed)); -/* - * Format 0 Extended Status Word (ESW) +/** + * struct esw0 - Format 0 Extended Status Word (ESW) + * @sublog: subchannel logout + * @erw: extended report word + * @faddr: failing storage address + * @saddr: secondary ccw address */ struct esw0 { - struct sublog sublog; /* subchannel logout */ - struct erw erw; /* extended report word */ - __u32 faddr[2]; /* failing storage address */ - __u32 saddr; /* secondary ccw address */ + struct sublog sublog; + struct erw erw; + __u32 faddr[2]; + __u32 saddr; } __attribute__ ((packed)); -/* - * Format 1 Extended Status Word (ESW) +/** + * struct esw1 - Format 1 Extended Status Word (ESW) + * @zero0: reserved zeros + * @lpum: last path used mask + * @zero16: reserved zeros + * @erw: extended report word + * @zeros: three fullwords of zeros */ struct esw1 { - __u8 zero0; /* reserved zeros */ - __u8 lpum; /* last path used mask */ - __u16 zero16; /* reserved zeros */ - struct erw erw; /* extended report word */ - __u32 zeros[3]; /* 2 fullwords of zeros */ + __u8 zero0; + __u8 lpum; + __u16 zero16; + struct erw erw; + __u32 zeros[3]; } __attribute__ ((packed)); -/* - * Format 2 Extended Status Word (ESW) +/** + * struct esw2 - Format 2 Extended Status Word (ESW) + * @zero0: reserved zeros + * @lpum: last path used mask + * @dcti: device-connect-time interval + * @erw: extended report word + * @zeros: three fullwords of zeros */ struct esw2 { - __u8 zero0; /* reserved zeros */ - __u8 lpum; /* last path used mask */ - __u16 dcti; /* device-connect-time interval */ - struct erw erw; /* extended report word */ - __u32 zeros[3]; /* 2 fullwords of zeros */ + __u8 zero0; + __u8 lpum; + __u16 dcti; + struct erw erw; + __u32 zeros[3]; } __attribute__ ((packed)); -/* - * Format 3 Extended Status Word (ESW) +/** + * struct esw3 - Format 3 Extended Status Word (ESW) + * @zero0: reserved zeros + * @lpum: last path used mask + * @res: reserved + * @erw: extended report word + * @zeros: three fullwords of zeros */ struct esw3 { - __u8 zero0; /* reserved zeros */ - __u8 lpum; /* last path used mask */ - __u16 res; /* reserved */ - struct erw erw; /* extended report word */ - __u32 zeros[3]; /* 2 fullwords of zeros */ + __u8 zero0; + __u8 lpum; + __u16 res; + struct erw erw; + __u32 zeros[3]; } __attribute__ ((packed)); -/* - * interruption response block +/** + * struct irb - interruption response block + * @scsw: subchannel status word + * @esw: extened status word, 4 formats + * @ecw: extended control word + * + * The irb that is handed to the device driver when an interrupt occurs. For + * solicited interrupts, the common I/O layer already performs checks whether + * a field is valid; a field not being valid is always passed as %0. + * If a unit check occured, @ecw may contain sense data; this is retrieved + * by the common I/O layer itself if the device doesn't support concurrent + * sense (so that the device driver never needs to perform basic sene itself). + * For unsolicited interrupts, the irb is passed as-is (expect for sense data, + * if applicable). */ struct irb { - struct scsw scsw; /* subchannel status word */ - union { /* extended status word, 4 formats */ + struct scsw scsw; + union { struct esw0 esw0; struct esw1 esw1; struct esw2 esw2; struct esw3 esw3; } esw; - __u8 ecw[32]; /* extended control word */ + __u8 ecw[32]; } __attribute__ ((packed,aligned(4))); -/* - * command information word (CIW) layout +/** + * struct ciw - command information word (CIW) layout + * @et: entry type + * @reserved: reserved bits + * @ct: command type + * @cmd: command code + * @count: command count */ struct ciw { - __u32 et : 2; /* entry type */ - __u32 reserved : 2; /* reserved */ - __u32 ct : 4; /* command type */ - __u32 cmd : 8; /* command */ - __u32 count : 16; /* coun */ + __u32 et : 2; + __u32 reserved : 2; + __u32 ct : 4; + __u32 cmd : 8; + __u32 count : 16; } __attribute__ ((packed)); #define CIW_TYPE_RCD 0x0 /* read configuration data */ @@ -258,24 +349,32 @@ struct ciw { /* Sick revalidation of device. */ #define CIO_REVALIDATE 0x0008 -struct diag210 { - __u16 vrdcdvno : 16; /* device number (input) */ - __u16 vrdclen : 16; /* data block length (input) */ - __u32 vrdcvcla : 8; /* virtual device class (output) */ - __u32 vrdcvtyp : 8; /* virtual device type (output) */ - __u32 vrdcvsta : 8; /* virtual device status (output) */ - __u32 vrdcvfla : 8; /* virtual device flags (output) */ - __u32 vrdcrccl : 8; /* real device class (output) */ - __u32 vrdccrty : 8; /* real device type (output) */ - __u32 vrdccrmd : 8; /* real device model (output) */ - __u32 vrdccrft : 8; /* real device feature (output) */ -} __attribute__ ((packed,aligned(4))); - +/** + * struct ccw_dev_id - unique identifier for ccw devices + * @ssid: subchannel set id + * @devno: device number + * + * This structure is not directly based on any hardware structure. The + * hardware identifies a device by its device number and its subchannel, + * which is in turn identified by its id. In order to get a unique identifier + * for ccw devices across subchannel sets, @struct ccw_dev_id has been + * introduced. + */ struct ccw_dev_id { u8 ssid; u16 devno; }; +/** + * ccw_device_id_is_equal() - compare two ccw_dev_ids + * @dev_id1: a ccw_dev_id + * @dev_id2: another ccw_dev_id + * Returns: + * %1 if the two structures are equal field-by-field, + * %0 if not. + * Context: + * any + */ static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1, struct ccw_dev_id *dev_id2) { @@ -285,8 +384,6 @@ static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1, return 0; } -extern int diag210(struct diag210 *addr); - extern void wait_cons_dev(void); extern void css_schedule_reprobe(void); diff --git a/include/asm-s390/cmb.h b/include/asm-s390/cmb.h index 021e7c3223ec..50196857d27a 100644 --- a/include/asm-s390/cmb.h +++ b/include/asm-s390/cmb.h @@ -1,29 +1,29 @@ #ifndef S390_CMB_H #define S390_CMB_H /** - * struct cmbdata -- channel measurement block data for user space + * struct cmbdata - channel measurement block data for user space + * @size: size of the stored data + * @elapsed_time: time since last sampling + * @ssch_rsch_count: number of ssch and rsch + * @sample_count: number of samples + * @device_connect_time: time of device connect + * @function_pending_time: time of function pending + * @device_disconnect_time: time of device disconnect + * @control_unit_queuing_time: time of control unit queuing + * @device_active_only_time: time of device active only + * @device_busy_time: time of device busy (ext. format) + * @initial_command_response_time: initial command response time (ext. format) * - * @size: size of the stored data - * @ssch_rsch_count: XXX - * @sample_count: - * @device_connect_time: - * @function_pending_time: - * @device_disconnect_time: - * @control_unit_queuing_time: - * @device_active_only_time: - * @device_busy_time: - * @initial_command_response_time: - * - * all values are stored as 64 bit for simplicity, especially + * All values are stored as 64 bit for simplicity, especially * in 32 bit emulation mode. All time values are normalized to * nanoseconds. * Currently, two formats are known, which differ by the size of * this structure, i.e. the last two members are only set when * the extended channel measurement facility (first shipped in * z990 machines) is activated. - * Potentially, more fields could be added, which results in a + * Potentially, more fields could be added, which would result in a * new ioctl number. - **/ + */ struct cmbdata { __u64 size; __u64 elapsed_time; @@ -41,53 +41,18 @@ struct cmbdata { }; /* enable channel measurement */ -#define BIODASDCMFENABLE _IO(DASD_IOCTL_LETTER,32) +#define BIODASDCMFENABLE _IO(DASD_IOCTL_LETTER, 32) /* enable channel measurement */ -#define BIODASDCMFDISABLE _IO(DASD_IOCTL_LETTER,33) +#define BIODASDCMFDISABLE _IO(DASD_IOCTL_LETTER, 33) /* read channel measurement data */ -#define BIODASDREADALLCMB _IOWR(DASD_IOCTL_LETTER,33,struct cmbdata) +#define BIODASDREADALLCMB _IOWR(DASD_IOCTL_LETTER, 33, struct cmbdata) #ifdef __KERNEL__ struct ccw_device; -/** - * enable_cmf() - switch on the channel measurement for a specific device - * @cdev: The ccw device to be enabled - * returns 0 for success or a negative error value. - * - * Context: - * non-atomic - **/ extern int enable_cmf(struct ccw_device *cdev); - -/** - * disable_cmf() - switch off the channel measurement for a specific device - * @cdev: The ccw device to be disabled - * returns 0 for success or a negative error value. - * - * Context: - * non-atomic - **/ extern int disable_cmf(struct ccw_device *cdev); - -/** - * cmf_read() - read one value from the current channel measurement block - * @cmf: the channel to be read - * @index: the name of the value that is read - * - * Context: - * any - **/ - extern u64 cmf_read(struct ccw_device *cdev, int index); -/** - * cmf_readall() - read one value from the current channel measurement block - * @cmf: the channel to be read - * @data: a pointer to a data block that will be filled - * - * Context: - * any - **/ -extern int cmf_readall(struct ccw_device *cdev, struct cmbdata*data); +extern int cmf_readall(struct ccw_device *cdev, struct cmbdata *data); #endif /* __KERNEL__ */ #endif /* S390_CMB_H */ diff --git a/include/asm-s390/diag.h b/include/asm-s390/diag.h new file mode 100644 index 000000000000..72b2e2f2d32d --- /dev/null +++ b/include/asm-s390/diag.h @@ -0,0 +1,39 @@ +/* + * s390 diagnose functions + * + * Copyright IBM Corp. 2007 + * Author(s): Michael Holzheu <holzheu@de.ibm.com> + */ + +#ifndef _ASM_S390_DIAG_H +#define _ASM_S390_DIAG_H + +/* + * Diagnose 10: Release pages + */ +extern void diag10(unsigned long addr); + +/* + * Diagnose 14: Input spool file manipulation + */ +extern int diag14(unsigned long rx, unsigned long ry1, unsigned long subcode); + +/* + * Diagnose 210: Get information about a virtual device + */ +struct diag210 { + u16 vrdcdvno; /* device number (input) */ + u16 vrdclen; /* data block length (input) */ + u8 vrdcvcla; /* virtual device class (output) */ + u8 vrdcvtyp; /* virtual device type (output) */ + u8 vrdcvsta; /* virtual device status (output) */ + u8 vrdcvfla; /* virtual device flags (output) */ + u8 vrdcrccl; /* real device class (output) */ + u8 vrdccrty; /* real device type (output) */ + u8 vrdccrmd; /* real device model (output) */ + u8 vrdccrft; /* real device feature (output) */ +} __attribute__((packed, aligned(4))); + +extern int diag210(struct diag210 *addr); + +#endif /* _ASM_S390_DIAG_H */ diff --git a/include/asm-s390/kprobes.h b/include/asm-s390/kprobes.h index 830fe4c4eea6..340ba10446ea 100644 --- a/include/asm-s390/kprobes.h +++ b/include/asm-s390/kprobes.h @@ -46,8 +46,6 @@ typedef u16 kprobe_opcode_t; ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)(pentry) - #define ARCH_SUPPORTS_KRETPROBES #define ARCH_INACTIVE_KPROBE_COUNT 0 diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h index f326451ed6ec..ceec3826a67c 100644 --- a/include/asm-s390/page.h +++ b/include/asm-s390/page.h @@ -9,11 +9,12 @@ #ifndef _S390_PAGE_H #define _S390_PAGE_H +#include <linux/const.h> #include <asm/types.h> /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #define PAGE_DEFAULT_ACC 0 #define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4) diff --git a/include/asm-s390/percpu.h b/include/asm-s390/percpu.h index 9ea7f1023e57..545857e64443 100644 --- a/include/asm-s390/percpu.h +++ b/include/asm-s390/percpu.h @@ -41,6 +41,11 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; __attribute__((__section__(".data.percpu"))) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp + #define __get_cpu_var(var) __reloc_hide(var,S390_lowcore.percpu_offset) #define __raw_get_cpu_var(var) __reloc_hide(var,S390_lowcore.percpu_offset) #define per_cpu(var,cpu) __reloc_hide(var,__per_cpu_offset[cpu]) @@ -59,6 +64,8 @@ do { \ #define DEFINE_PER_CPU(type, name) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) #define __get_cpu_var(var) __reloc_hide(var,0) #define __raw_get_cpu_var(var) __reloc_hide(var,0) diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h index 56c8a6c80e2e..e45d3c9a4b7e 100644 --- a/include/asm-s390/pgalloc.h +++ b/include/asm-s390/pgalloc.h @@ -19,8 +19,6 @@ #define check_pgt_cache() do {} while (0) -extern void diag10(unsigned long addr); - /* * Page allocation orders. */ diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h index 3208dc6c412c..39bb5192dc31 100644 --- a/include/asm-s390/pgtable.h +++ b/include/asm-s390/pgtable.h @@ -107,11 +107,18 @@ extern char empty_zero_page[PAGE_SIZE]; * any out-of-bounds memory accesses will hopefully be caught. * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) + * vmalloc area starts at 4GB to prevent syscall table entry exchanging + * from modules. */ extern unsigned long vmalloc_end; -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) \ - & ~(VMALLOC_OFFSET-1)) + +#ifdef CONFIG_64BIT +#define VMALLOC_ADDR (max(0x100000000UL, (unsigned long) high_memory)) +#else +#define VMALLOC_ADDR ((unsigned long) high_memory) +#endif +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START ((VMALLOC_ADDR + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END vmalloc_end /* diff --git a/include/asm-s390/s390_ext.h b/include/asm-s390/s390_ext.h index df9b1017b703..2afc060266a2 100644 --- a/include/asm-s390/s390_ext.h +++ b/include/asm-s390/s390_ext.h @@ -5,22 +5,20 @@ * include/asm-s390/s390_ext.h * * S390 version - * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation + * Copyright IBM Corp. 1999,2007 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com), * Martin Schwidefsky (schwidefsky@de.ibm.com) */ +#include <linux/types.h> + typedef void (*ext_int_handler_t)(__u16 code); -/* - * Warning: if you change ext_int_info_t you have to change the - * external interrupt handler in entry.S too. - */ typedef struct ext_int_info_t { struct ext_int_info_t *next; ext_int_handler_t handler; __u16 code; -} __attribute__ ((packed)) ext_int_info_t; +} ext_int_info_t; extern ext_int_info_t *ext_int_hash[]; diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h index 76e424f718c6..07708c07701e 100644 --- a/include/asm-s390/smp.h +++ b/include/asm-s390/smp.h @@ -36,8 +36,7 @@ extern void machine_halt_smp(void); extern void machine_power_off_smp(void); extern void smp_setup_cpu_possible_map(void); -extern int smp_call_function_on(void (*func) (void *info), void *info, - int nonatomic, int wait, int cpu); + #define NO_PROC_ID 0xFF /* No processor magic marker */ /* @@ -96,14 +95,6 @@ extern int __cpu_up (unsigned int cpu); #endif #ifndef CONFIG_SMP -static inline int -smp_call_function_on(void (*func) (void *info), void *info, - int nonatomic, int wait, int cpu) -{ - func(info); - return 0; -} - static inline void smp_send_stop(void) { /* Disable all interrupts/machine checks */ diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h index bbe137c3ed69..d866d3385556 100644 --- a/include/asm-s390/system.h +++ b/include/asm-s390/system.h @@ -97,16 +97,6 @@ static inline void restore_access_regs(unsigned int *acrs) prev = __switch_to(prev,next); \ } while (0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - #ifdef CONFIG_VIRT_CPU_ACCOUNTING extern void account_vtime(struct task_struct *); extern void account_tick_vtime(struct task_struct *); @@ -140,6 +130,8 @@ extern void pfault_fini(void); __ret; \ }) +extern void __xchg_called_with_bad_pointer(void); + static inline unsigned long __xchg(unsigned long x, void * ptr, int size) { unsigned long addr, old; @@ -160,8 +152,7 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) : "=&d" (old), "=m" (*(int *) addr) : "d" (x << shift), "d" (~(255 << shift)), "a" (addr), "m" (*(int *) addr) : "memory", "cc", "0"); - x = old >> shift; - break; + return old >> shift; case 2: addr = (unsigned long) ptr; shift = (2 ^ (addr & 2)) << 3; @@ -176,8 +167,7 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) : "=&d" (old), "=m" (*(int *) addr) : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr), "m" (*(int *) addr) : "memory", "cc", "0"); - x = old >> shift; - break; + return old >> shift; case 4: asm volatile( " l %0,0(%3)\n" @@ -186,8 +176,7 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) : "=&d" (old), "=m" (*(int *) ptr) : "d" (x), "a" (ptr), "m" (*(int *) ptr) : "memory", "cc"); - x = old; - break; + return old; #ifdef __s390x__ case 8: asm volatile( @@ -197,11 +186,11 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) : "=&d" (old), "=m" (*(long *) ptr) : "d" (x), "a" (ptr), "m" (*(long *) ptr) : "memory", "cc"); - x = old; - break; + return old; #endif /* __s390x__ */ - } - return x; + } + __xchg_called_with_bad_pointer(); + return x; } /* @@ -216,6 +205,8 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size) ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ (unsigned long)(n),sizeof(*(ptr)))) +extern void __cmpxchg_called_with_bad_pointer(void); + static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) { @@ -280,7 +271,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) return prev; #endif /* __s390x__ */ } - return old; + __cmpxchg_called_with_bad_pointer(); + return old; } /* diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h index 790c1c557417..f04acb2670a8 100644 --- a/include/asm-s390/unistd.h +++ b/include/asm-s390/unistd.h @@ -251,7 +251,7 @@ #define __NR_getcpu 311 #define __NR_epoll_pwait 312 #define __NR_utimes 313 -/* Number 314 is reserved for new sys_fallocate */ +#define __NR_fallocate 314 #define __NR_utimensat 315 #define __NR_signalfd 316 #define __NR_timerfd 317 diff --git a/include/asm-s390/zcrypt.h b/include/asm-s390/zcrypt.h index b90e55888a55..a5dada617751 100644 --- a/include/asm-s390/zcrypt.h +++ b/include/asm-s390/zcrypt.h @@ -91,7 +91,7 @@ struct ica_rsa_modexpo_crt { * VUD block * key block */ -struct ica_CPRBX { +struct CPRBX { unsigned short cprb_len; /* CPRB length 220 */ unsigned char cprb_ver_id; /* CPRB version id. 0x02 */ unsigned char pad_000[3]; /* Alignment pad bytes */ @@ -130,7 +130,7 @@ struct ica_CPRBX { unsigned char cntrl_domain[4];/* Control domain */ unsigned char S390enf_mask[4];/* S/390 enforcement mask */ unsigned char pad_004[36]; /* reserved */ -}; +} __attribute__((packed)); /** * xcRB diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h index 6e9fca9ee333..685d0f6125fa 100644 --- a/include/asm-sh/a.out.h +++ b/include/asm-sh/a.out.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h index 46f925c815ac..a78d482e8b2f 100644 --- a/include/asm-sh/bug.h +++ b/include/asm-sh/bug.h @@ -61,7 +61,7 @@ do { \ } while (0) #define WARN_ON(x) ({ \ - typeof(x) __ret_warn_on = (x); \ + int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ __WARN(); \ diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index aeee8da9c54f..b66139ff73fc 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -29,7 +29,7 @@ static void __init check_bugs(void) *p++ = '2'; *p++ = 'a'; break; - case CPU_SH7705 ... CPU_SH7300: + case CPU_SH7705 ... CPU_SH7729: *p++ = '3'; break; case CPU_SH7750 ... CPU_SH4_501: @@ -39,7 +39,7 @@ static void __init check_bugs(void) *p++ = '4'; *p++ = 'a'; break; - case CPU_SH73180 ... CPU_SH7722: + case CPU_SH7343 ... CPU_SH7722: *p++ = '4'; *p++ = 'a'; *p++ = 'l'; diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h index 386d797d86b7..b550a27a7042 100644 --- a/include/asm-sh/clock.h +++ b/include/asm-sh/clock.h @@ -14,6 +14,7 @@ struct clk_ops { void (*disable)(struct clk *clk); void (*recalc)(struct clk *clk); int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); + long (*round_rate)(struct clk *clk, unsigned long rate); }; struct clk { diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h index 273f3229785c..0a054b53b9de 100644 --- a/include/asm-sh/cpu-sh3/freq.h +++ b/include/asm-sh/cpu-sh3/freq.h @@ -10,11 +10,7 @@ #ifndef __ASM_CPU_SH3_FREQ_H #define __ASM_CPU_SH3_FREQ_H -#if defined(CONFIG_CPU_SUBTYPE_SH7300) -#define FRQCR 0xa415ff80 -#else #define FRQCR 0xffffff80 -#endif #define MIN_DIVISOR_NR 0 #define MAX_DIVISOR_NR 4 diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h index 4704e86dff5b..b20786d42d09 100644 --- a/include/asm-sh/cpu-sh3/mmu_context.h +++ b/include/asm-sh/cpu-sh3/mmu_context.h @@ -30,7 +30,6 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) || \ defined(CONFIG_CPU_SUBTYPE_SH7706) || \ - defined(CONFIG_CPU_SUBTYPE_SH7300) || \ defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index 4928b08f9d19..b6c2020a2ad3 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h @@ -19,7 +19,6 @@ * SH7729R * SH7710 * SH7720 - * SH7300 * SH7710 * --------------------------------------------------------------------------- */ @@ -28,7 +27,7 @@ #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif -#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7710) #define TMU_012_TSTR 0xa412fe92 /* Byte access */ #define TMU0_TCOR 0xa412fe94 /* Long access */ diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h index 026025b51cea..dc1d32a86374 100644 --- a/include/asm-sh/cpu-sh4/freq.h +++ b/include/asm-sh/cpu-sh4/freq.h @@ -10,7 +10,7 @@ #ifndef __ASM_CPU_SH4_FREQ_H #define __ASM_CPU_SH4_FREQ_H -#if defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7722) +#if defined(CONFIG_CPU_SUBTYPE_SH7722) #define FRQCR 0xa4150000 #define VCLKCR 0xa4150004 #define SCLKACR 0xa4150008 diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h index d3bc7818bbbe..84fefdaa01a5 100644 --- a/include/asm-sh/dma-mapping.h +++ b/include/asm-sh/dma-mapping.h @@ -69,11 +69,11 @@ static inline dma_addr_t dma_map_single(struct device *dev, { #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) if (dev->bus == &pci_bus_type) - return virt_to_bus(ptr); + return virt_to_phys(ptr); #endif dma_cache_sync(dev, ptr, size, dir); - return virt_to_bus(ptr); + return virt_to_phys(ptr); } #define dma_unmap_single(dev, addr, size, dir) do { } while (0) @@ -116,7 +116,7 @@ static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, if (dev->bus == &pci_bus_type) return; #endif - dma_cache_sync(dev, bus_to_virt(dma_handle), size, dir); + dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir); } static inline void dma_sync_single_range(struct device *dev, @@ -128,7 +128,7 @@ static inline void dma_sync_single_range(struct device *dev, if (dev->bus == &pci_bus_type) return; #endif - dma_cache_sync(dev, bus_to_virt(dma_handle) + offset, size, dir); + dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); } static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, @@ -160,6 +160,25 @@ static inline void dma_sync_single_for_device(struct device *dev, dma_sync_single(dev, dma_handle, size, dir); } +static inline void dma_sync_single_range_for_cpu(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) +{ + dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction); +} + +static inline void dma_sync_single_range_for_device(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) +{ + dma_sync_single_for_device(dev, dma_handle+offset, size, direction); +} + + static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h index 6034d4a29e73..4c75b70b6414 100644 --- a/include/asm-sh/dma.h +++ b/include/asm-sh/dma.h @@ -111,6 +111,7 @@ struct dma_info { struct list_head list; int first_channel_nr; + int first_vchannel_nr; }; struct dma_chan_caps { diff --git a/include/asm-sh/fixmap.h b/include/asm-sh/fixmap.h index 458e9fa59545..8a566177ad96 100644 --- a/include/asm-sh/fixmap.h +++ b/include/asm-sh/fixmap.h @@ -46,6 +46,9 @@ * fix-mapped? */ enum fixed_addresses { +#define FIX_N_COLOURS 16 + FIX_CMAP_BEGIN, + FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, #ifdef CONFIG_HIGHMEM FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, @@ -53,8 +56,8 @@ enum fixed_addresses { __end_of_fixed_addresses }; -extern void __set_fixmap (enum fixed_addresses idx, - unsigned long phys, pgprot_t flags); +extern void __set_fixmap(enum fixed_addresses idx, + unsigned long phys, pgprot_t flags); #define set_fixmap(idx, phys) \ __set_fixmap(idx, phys, PAGE_KERNEL) @@ -106,5 +109,4 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr) BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); return __virt_to_fix(vaddr); } - #endif diff --git a/include/asm-sh/flat.h b/include/asm-sh/flat.h index 0d5cc04ab005..dc4f5950dafa 100644 --- a/include/asm-sh/flat.h +++ b/include/asm-sh/flat.h @@ -16,8 +16,9 @@ #define flat_argvp_envp_on_stack() 0 #define flat_old_ram_flag(flags) (flags) #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp) +#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) +#define flat_set_persistent(relval, p) 0 #endif /* __ASM_SH_FLAT_H */ diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h index dc1ad464fa32..3b59b3af777b 100644 --- a/include/asm-sh/floppy.h +++ b/include/asm-sh/floppy.h @@ -181,7 +181,7 @@ static void _fd_chose_dma_mode(char *addr, unsigned long size) { if(can_use_virtual_dma == 2) { if((unsigned int) addr >= (unsigned int) high_memory || - virt_to_bus(addr) >= 0x10000000) + virt_to_phys(addr) >= 0x10000000) use_virtual_dma = 1; else use_virtual_dma = 0; @@ -219,7 +219,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) doing_pdma = 0; clear_dma_ff(FLOPPY_DMA); set_dma_mode(FLOPPY_DMA,mode); - set_dma_addr(FLOPPY_DMA,virt_to_bus(addr)); + set_dma_addr(FLOPPY_DMA,virt_to_phys(addr)); set_dma_count(FLOPPY_DMA,size); enable_dma(FLOPPY_DMA); return 0; diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 4ca3f765bacc..20d42959f52a 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h @@ -1,6 +1,7 @@ #ifndef __ASM_SH_HW_IRQ_H #define __ASM_SH_HW_IRQ_H +#include <linux/init.h> #include <asm/atomic.h> extern atomic_t irq_err_count; @@ -22,7 +23,6 @@ struct intc2_desc { }; void register_intc2_controller(struct intc2_desc *); -void init_IRQ_intc2(void); struct ipr_data { unsigned char irq; @@ -40,11 +40,82 @@ struct ipr_desc { }; void register_ipr_controller(struct ipr_desc *); -void init_IRQ_ipr(void); /* * Enable individual interrupt mode for external IPR IRQs. */ -void ipr_irq_enable_irlm(void); +void __init ipr_irq_enable_irlm(void); + +typedef unsigned char intc_enum; + +struct intc_vect { + intc_enum enum_id; + unsigned short vect; +}; + +#define INTC_VECT(enum_id, vect) { enum_id, vect } + +struct intc_prio { + intc_enum enum_id; + unsigned char priority; +}; + +#define INTC_PRIO(enum_id, prio) { enum_id, prio } + +struct intc_group { + intc_enum enum_id; + intc_enum *enum_ids; +}; + +#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } } + +struct intc_mask_reg { + unsigned long set_reg, clr_reg, reg_width; + intc_enum enum_ids[32]; +}; + +struct intc_prio_reg { + unsigned long reg, reg_width, field_width; + intc_enum enum_ids[16]; +}; + +struct intc_sense_reg { + unsigned long reg, reg_width, field_width; + intc_enum enum_ids[16]; +}; + +struct intc_desc { + struct intc_vect *vectors; + unsigned int nr_vectors; + struct intc_group *groups; + unsigned int nr_groups; + struct intc_prio *priorities; + unsigned int nr_priorities; + struct intc_mask_reg *mask_regs; + unsigned int nr_mask_regs; + struct intc_prio_reg *prio_regs; + unsigned int nr_prio_regs; + struct intc_sense_reg *sense_regs; + unsigned int nr_sense_regs; + struct irq_chip chip; +}; + +#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) +#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ + priorities, mask_regs, prio_regs, sense_regs) \ +struct intc_desc symbol = { \ + _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ + _INTC_ARRAY(priorities), \ + _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ + _INTC_ARRAY(sense_regs), \ + .chip.name = chipname, \ +} + +void __init register_intc_controller(struct intc_desc *desc); + +void __init plat_irq_setup(void); + +enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; +void __init plat_irq_setup_pins(int mode); #endif /* __ASM_SH_HW_IRQ_H */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index aa80930ce8e4..e6a1877dcb20 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -241,10 +241,6 @@ static inline void *phys_to_virt(unsigned long address) #define virt_to_phys(address) ((unsigned long)(address)) #endif -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt -#define page_to_bus page_to_phys - /* * readX/writeX() are used to access memory mapped devices. On some * architectures the memory mapped IO stuff needs to be accessed diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h index 0ec78f66cea4..e245f2a3cd78 100644 --- a/include/asm-sh/mpc1211/mc146818rtc.h +++ b/include/asm-sh/mpc1211/mc146818rtc.h @@ -1,6 +1,6 @@ /* * MPC1211 uses PC/AT style RTC definitions. */ -#include <asm-i386/mc146818rtc.h> +#include <asm-x86/mc146818rtc_32.h> diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index 22efffe45019..e3fae12c0e49 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -55,11 +55,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE) -/* - * First 1MB map is used by fixed purpose. - * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c) - */ -#define VMALLOC_START (P3SEG+0x00100000) +#define VMALLOC_START (P3SEG) #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) /* diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 2252e75daa26..26d52174f4b4 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -45,7 +45,7 @@ enum cpu_type { CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, - CPU_SH7729, CPU_SH7300, + CPU_SH7729, /* SH-4 types */ CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, @@ -55,7 +55,7 @@ enum cpu_type { CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, /* SH4AL-DSP types */ - CPU_SH73180, CPU_SH7343, CPU_SH7722, + CPU_SH7343, CPU_SH7722, /* Unknown subtype */ CPU_SH_NONE diff --git a/include/asm-sh/rts7751r2d.h b/include/asm-sh/rts7751r2d.h index 10565ac7966a..5d7800aa31b5 100644 --- a/include/asm-sh/rts7751r2d.h +++ b/include/asm-sh/rts7751r2d.h @@ -37,7 +37,7 @@ #define PA_VERREG 0xa4000032 /* FPGA Version Register */ #define PA_INPORT 0xa4000034 /* KEY Input Port control */ #define PA_OUTPORT 0xa4000036 /* LED control */ -#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */ +#define PA_BVERREG 0xa4000038 /* Board Revision Register */ #define PA_AX88796L 0xaa000400 /* AX88796L Area */ #define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ diff --git a/include/asm-sh/se7300.h b/include/asm-sh/se7300.h deleted file mode 100644 index 4e24edccb30d..000000000000 --- a/include/asm-sh/se7300.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE7300_H -#define __ASM_SH_HITACHI_SE7300_H - -/* - * linux/include/asm-sh/se/se7300.h - * - * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> - * - * SH-Mobile SolutionEngine 7300 support - */ - -/* Box specific addresses. */ - -/* Area 0 */ -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ -#define PA_FROM 0x00400000 /* Flash ROM */ -#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ -#define PA_SRAM 0x00800000 /* SRAM */ -#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ -/* Area 1 */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -/* Area 2 */ -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -/* Area 3 */ -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 -/* Area 4 */ -#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) -#define PA_LED 0xb0800000 /* LED */ -#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ -#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ -#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ -#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ -/* Area 5 */ -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -/* Area 6 */ -#define PA_LCD1 0xb8000000 -#define PA_LCD2 0xb8800000 - -#define __IO_PREFIX sh7300se -#include <asm/io_generic.h> - -#endif /* __ASM_SH_HITACHI_SE7300_H */ diff --git a/include/asm-sh/se73180.h b/include/asm-sh/se73180.h deleted file mode 100644 index 907c062b4c9a..000000000000 --- a/include/asm-sh/se73180.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __ASM_SH_SE73180_H -#define __ASM_SH_SE73180_H - -/* - * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> - * - * SH-Mobile SolutionEngine 73180 support - */ - -/* Box specific addresses. */ - -/* Area 0 */ -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ -#define PA_FROM 0x00400000 /* Flash ROM */ -#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ -#define PA_SRAM 0x00800000 /* SRAM */ -#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ -/* Area 1 */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -/* Area 2 */ -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -/* Area 3 */ -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 -/* Area 4 */ -#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) -#define PA_LED 0xb0C00000 /* LED */ -#define LED_SHIFT 0 -#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ -#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ -#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ -#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ -/* Area 5 */ -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -/* Area 6 */ -#define PA_LCD1 0xb8000000 -#define PA_LCD2 0xb8800000 - -#define __IO_PREFIX sh73180se -#include <asm/io_generic.h> - -/* arch/sh/boards/se/73180/irq.c */ -int shmse_irq_demux(int irq); - -#endif /* __ASM_SH_SE73180_H */ diff --git a/include/asm-sh/se7722.h b/include/asm-sh/se7722.h index b3b31e4725c6..e0e89fcb8388 100644 --- a/include/asm-sh/se7722.h +++ b/include/asm-sh/se7722.h @@ -81,36 +81,32 @@ /* IRQ */ #define IRQ0_IRQ 32 #define IRQ1_IRQ 33 -#define INTC_ICR0 0xA4140000UL -#define INTC_ICR1 0xA414001CUL - -#define INTMSK0 0xa4140044 -#define INTMSKCLR0 0xa4140064 -#define INTC_INTPRI0 0xa4140010 #define IRQ01_MODE 0xb1800000 #define IRQ01_STS 0xb1800004 #define IRQ01_MASK 0xb1800008 -#define EXT_BIT (0x3fc0) /* SH IRQ1 */ -#define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */ -#define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */ -#define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */ -#define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */ -#define SMC_BIT (0x0002) /* SH IRQ0 */ -#define USB_BIT (0x0001) /* SH IRQ0 */ - -#define MRSHPC_IRQ3 11 -#define MRSHPC_IRQ2 12 -#define MRSHPC_IRQ1 13 -#define MRSHPC_IRQ0 14 -#define SMC_IRQ 10 -#define EXT_IRQ 5 -#define USB_IRQ 6 +/* Bits in IRQ01_* registers */ + +#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ +#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ +#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ + +#define SE7722_FPGA_IRQ_NR 6 +#define SE7722_FPGA_IRQ_BASE 110 + +#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3) +#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2) +#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1) +#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0) +#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC) +#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB) /* arch/sh/boards/se/7722/irq.c */ void init_se7722_IRQ(void); -int se7722_irq_demux(int); #define __IO_PREFIX se7722 #include <asm/io_generic.h> diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 7c75045ae22b..245042537205 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -64,16 +64,6 @@ struct task_struct *__switch_to(struct task_struct *prev, last = __last; \ } while (0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - #ifdef CONFIG_CPU_SH4A #define __icbi() \ { \ diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h index 31d55e3782d5..1f7e1deb8d92 100644 --- a/include/asm-sh/thread_info.h +++ b/include/asm-sh/thread_info.h @@ -107,18 +107,16 @@ static inline struct thread_info *current_thread_info(void) * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */ -#define TIF_SINGLESTEP 5 /* singlestepping active */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_RESTORE_SIGMASK 3 /* restore signal mask in do_signal() */ +#define TIF_SINGLESTEP 4 /* singlestepping active */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h index 38d46e01b846..56f4e30dc49c 100644 --- a/include/asm-sh/ubc.h +++ b/include/asm-sh/ubc.h @@ -15,8 +15,7 @@ #include <asm/cpu/ubc.h> /* User Break Controller */ -#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ - defined(CONFIG_CPU_SUBTYPE_SH7300) +#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) #define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729) #else #define UBC_TYPE_SH7729 0 diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h index 77bcb09d6ac8..b182b1cb05fd 100644 --- a/include/asm-sh/unistd.h +++ b/include/asm-sh/unistd.h @@ -332,8 +332,9 @@ #define __NR_signalfd 321 #define __NR_timerfd 322 #define __NR_eventfd 323 +#define __NR_fallocate 324 -#define NR_syscalls 324 +#define NR_syscalls 325 #ifdef __KERNEL__ diff --git a/include/asm-sh64/a.out.h b/include/asm-sh64/a.out.h index e1995e86b663..237ee4e5b72a 100644 --- a/include/asm-sh64/a.out.h +++ b/include/asm-sh64/a.out.h @@ -31,6 +31,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-sh64/dma-mapping.h b/include/asm-sh64/dma-mapping.h index c7c0f059cdc4..de4309960207 100644 --- a/include/asm-sh64/dma-mapping.h +++ b/include/asm-sh64/dma-mapping.h @@ -51,11 +51,11 @@ static inline dma_addr_t dma_map_single(struct device *dev, { #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) if (dev->bus == &pci_bus_type) - return virt_to_bus(ptr); + return virt_to_phys(ptr); #endif dma_cache_sync(dev, ptr, size, dir); - return virt_to_bus(ptr); + return virt_to_phys(ptr); } #define dma_unmap_single(dev, addr, size, dir) do { } while (0) @@ -98,7 +98,7 @@ static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, if (dev->bus == &pci_bus_type) return; #endif - dma_cache_sync(dev, bus_to_virt(dma_handle), size, dir); + dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir); } static inline void dma_sync_single_range(struct device *dev, @@ -110,7 +110,7 @@ static inline void dma_sync_single_range(struct device *dev, if (dev->bus == &pci_bus_type) return; #endif - dma_cache_sync(dev, bus_to_virt(dma_handle) + offset, size, dir); + dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); } static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, @@ -141,6 +141,24 @@ static inline void dma_sync_single_for_device(struct device *dev, dma_sync_single(dev, dma_handle, size, dir); } +static inline void dma_sync_single_range_for_cpu(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) +{ + dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction); +} + +static inline void dma_sync_single_range_for_device(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) +{ + dma_sync_single_for_device(dev, dma_handle+offset, size, direction); +} + static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) diff --git a/include/asm-sh64/io.h b/include/asm-sh64/io.h index 14d8e7b4bf4b..1f37b6931922 100644 --- a/include/asm-sh64/io.h +++ b/include/asm-sh64/io.h @@ -31,10 +31,6 @@ #include <asm/page.h> #include <asm-generic/iomap.h> -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt -#define page_to_bus page_to_phys - /* * Nothing overly special here.. instead of doing the same thing * over and over again, we just define a set of sh64_in/out functions diff --git a/include/asm-sh64/irq.h b/include/asm-sh64/irq.h index 1ca49e29288a..5c9e6a873aeb 100644 --- a/include/asm-sh64/irq.h +++ b/include/asm-sh64/irq.h @@ -114,10 +114,6 @@ #define IRL0_PRIORITY 13 #define TOP_PRIORITY 15 -extern void disable_irq(unsigned int); -extern void disable_irq_nosync(unsigned int); -extern void enable_irq(unsigned int); - extern int intc_evt_to_irq[(0xE20/0x20)+1]; int intc_irq_describe(char* p, int irq); diff --git a/include/asm-sh64/unistd.h b/include/asm-sh64/unistd.h index ea3adc600b41..1a5197f369b2 100644 --- a/include/asm-sh64/unistd.h +++ b/include/asm-sh64/unistd.h @@ -374,10 +374,11 @@ #define __NR_signalfd 349 #define __NR_timerfd 350 #define __NR_eventfd 351 +#define __NR_fallocate 352 #ifdef __KERNEL__ -#define NR_syscalls 352 +#define NR_syscalls 353 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/include/asm-sparc/a.out.h b/include/asm-sparc/a.out.h index 9090060a23e6..917e04250696 100644 --- a/include/asm-sparc/a.out.h +++ b/include/asm-sparc/a.out.h @@ -92,6 +92,7 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ #include <asm/page.h> #define STACK_TOP (PAGE_OFFSET - PAGE_SIZE) +#define STACK_TOP_MAX STACK_TOP #endif /* __KERNEL__ */ diff --git a/include/asm-sparc/device.h b/include/asm-sparc/device.h index d8f9872b0e2d..c0a7786d65f7 100644 --- a/include/asm-sparc/device.h +++ b/include/asm-sparc/device.h @@ -3,5 +3,21 @@ * * This file is released under the GPLv2 */ -#include <asm-generic/device.h> +#ifndef _ASM_SPARC_DEVICE_H +#define _ASM_SPARC_DEVICE_H + +struct device_node; +struct of_device; + +struct dev_archdata { + void *iommu; + void *stc; + void *host_controller; + + struct device_node *prom_node; + struct of_device *op; +}; + +#endif /* _ASM_SPARC_DEVICE_H */ + diff --git a/include/asm-sparc/fb.h b/include/asm-sparc/fb.h index c7df38030992..c73ca081e1f5 100644 --- a/include/asm-sparc/fb.h +++ b/include/asm-sparc/fb.h @@ -1,11 +1,20 @@ #ifndef _ASM_FB_H_ #define _ASM_FB_H_ #include <linux/fb.h> +#include <asm/prom.h> #define fb_pgprotect(...) do {} while (0) static inline int fb_is_primary_device(struct fb_info *info) { + struct device *dev = info->device; + struct device_node *node; + + node = dev->archdata.prom_node; + if (node && + node == of_console_device) + return 1; + return 0; } diff --git a/include/asm-sparc/fcntl.h b/include/asm-sparc/fcntl.h index 5db60b5ae7b0..5ec546349fc8 100644 --- a/include/asm-sparc/fcntl.h +++ b/include/asm-sparc/fcntl.h @@ -16,6 +16,7 @@ #define O_LARGEFILE 0x40000 #define O_DIRECT 0x100000 /* direct disk access hint */ #define O_NOATIME 0x200000 +#define O_CLOEXEC 0x400000 #define F_GETOWN 5 /* for sockets. */ #define F_SETOWN 6 /* for sockets. */ diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h index 9073c84218ce..acd06d8ff70a 100644 --- a/include/asm-sparc/floppy.h +++ b/include/asm-sparc/floppy.h @@ -48,7 +48,7 @@ struct sun_flpy_controller { /* You'll only ever find one controller on a SparcStation anyways. */ static struct sun_flpy_controller *sun_fdc = NULL; -volatile unsigned char *fdc_status; +extern volatile unsigned char *fdc_status; struct sun_floppy_ops { unsigned char (*fd_inb)(int port); @@ -101,6 +101,29 @@ static struct sun_floppy_ops sun_fdops; #define CROSS_64KB(a,s) (0) /* Routines unique to each controller type on a Sun. */ +static void sun_set_dor(unsigned char value, int fdc_82077) +{ + if (sparc_cpu_model == sun4c) { + unsigned int bits = 0; + if (value & 0x10) + bits |= AUXIO_FLPY_DSEL; + if ((value & 0x80) == 0) + bits |= AUXIO_FLPY_EJCT; + set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT)); + } + if (fdc_82077) { + sun_fdc->dor_82077 = value; + } +} + +static unsigned char sun_read_dir(void) +{ + if (sparc_cpu_model == sun4c) + return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0; + else + return sun_fdc->dir_82077; +} + static unsigned char sun_82072_fd_inb(int port) { udelay(5); @@ -113,7 +136,7 @@ static unsigned char sun_82072_fd_inb(int port) case 5: /* FD_DATA */ return sun_fdc->data_82072; case 7: /* FD_DIR */ - return (get_auxio() & AUXIO_FLPY_DCHG)? 0x80: 0; + return sun_read_dir(); }; panic("sun_82072_fd_inb: How did I get here?"); } @@ -126,20 +149,7 @@ static void sun_82072_fd_outb(unsigned char value, int port) printk("floppy: Asked to write to unknown port %d\n", port); panic("floppy: Port bolixed."); case 2: /* FD_DOR */ - /* Oh geese, 82072 on the Sun has no DOR register, - * the functionality is implemented via the AUXIO - * I/O register. So we must emulate the behavior. - * - * ASSUMPTIONS: There will only ever be one floppy - * drive attached to a Sun controller - * and it will be at drive zero. - */ - { - unsigned bits = 0; - if (value & 0x10) bits |= AUXIO_FLPY_DSEL; - if ((value & 0x80) == 0) bits |= AUXIO_FLPY_EJCT; - set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT)); - } + sun_set_dor(value, 0); break; case 5: /* FD_DATA */ sun_fdc->data_82072 = value; @@ -161,15 +171,22 @@ static unsigned char sun_82077_fd_inb(int port) default: printk("floppy: Asked to read unknown port %d\n", port); panic("floppy: Port bolixed."); + case 0: /* FD_STATUS_0 */ + return sun_fdc->status1_82077; + case 1: /* FD_STATUS_1 */ + return sun_fdc->status2_82077; + case 2: /* FD_DOR */ + return sun_fdc->dor_82077; + case 3: /* FD_TDR */ + return sun_fdc->tapectl_82077; case 4: /* FD_STATUS */ return sun_fdc->status_82077 & ~STATUS_DMA; case 5: /* FD_DATA */ return sun_fdc->data_82077; case 7: /* FD_DIR */ - /* XXX: Is DCL on 0x80 in sun4m? */ - return sun_fdc->dir_82077; + return sun_read_dir(); }; - panic("sun_82072_fd_inb: How did I get here?"); + panic("sun_82077_fd_inb: How did I get here?"); } static void sun_82077_fd_outb(unsigned char value, int port) @@ -180,8 +197,7 @@ static void sun_82077_fd_outb(unsigned char value, int port) printk("floppy: Asked to write to unknown port %d\n", port); panic("floppy: Port bolixed."); case 2: /* FD_DOR */ - /* Happily, the 82077 has a real DOR register. */ - sun_fdc->dor_82077 = value; + sun_set_dor(value, 1); break; case 5: /* FD_DATA */ sun_fdc->data_82077 = value; @@ -192,6 +208,9 @@ static void sun_82077_fd_outb(unsigned char value, int port) case 4: /* FD_STATUS */ sun_fdc->status_82077 = value; break; + case 3: /* FD_TDR */ + sun_fdc->tapectl_82077 = value; + break; }; return; } @@ -206,13 +225,13 @@ static void sun_82077_fd_outb(unsigned char value, int port) * underruns. If non-zero, doing_pdma encodes the direction of * the transfer for debugging. 1=read 2=write */ -char *pdma_vaddr; -unsigned long pdma_size; -volatile int doing_pdma = 0; +extern char *pdma_vaddr; +extern unsigned long pdma_size; +extern volatile int doing_pdma; /* This is software state */ -char *pdma_base = NULL; -unsigned long pdma_areasize; +extern char *pdma_base; +extern unsigned long pdma_areasize; /* Common routines to all controller types on the Sparc. */ static __inline__ void virtual_dma_init(void) @@ -262,7 +281,8 @@ static __inline__ void sun_fd_enable_dma(void) } /* Our low-level entry point in arch/sparc/kernel/entry.S */ -irqreturn_t floppy_hardint(int irq, void *unused); +extern int sparc_floppy_request_irq(int irq, unsigned long flags, + irqreturn_t (*irq_handler)(int irq, void *)); static int sun_fd_request_irq(void) { @@ -271,8 +291,9 @@ static int sun_fd_request_irq(void) if(!once) { once = 1; - error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, - IRQF_DISABLED, "floppy"); + error = sparc_floppy_request_irq(FLOPPY_IRQ, + IRQF_DISABLED, + floppy_interrupt); return ((error == 0) ? 0 : -1); } else return 0; } @@ -332,16 +353,17 @@ static int sun_floppy_init(void) goto no_sun_fdc; } - if(sparc_cpu_model == sun4c) { - sun_fdops.fd_inb = sun_82072_fd_inb; - sun_fdops.fd_outb = sun_82072_fd_outb; - fdc_status = &sun_fdc->status_82072; - /* printk("AUXIO @0x%lx\n", auxio_register); */ /* P3 */ - } else { - sun_fdops.fd_inb = sun_82077_fd_inb; - sun_fdops.fd_outb = sun_82077_fd_outb; - fdc_status = &sun_fdc->status_82077; - /* printk("DOR @0x%p\n", &sun_fdc->dor_82077); */ /* P3 */ + sun_fdops.fd_inb = sun_82077_fd_inb; + sun_fdops.fd_outb = sun_82077_fd_outb; + fdc_status = &sun_fdc->status_82077; + + if (sun_fdc->dor_82077 == 0x80) { + sun_fdc->dor_82077 = 0x02; + if (sun_fdc->dor_82077 == 0x80) { + sun_fdops.fd_inb = sun_82072_fd_inb; + sun_fdops.fd_outb = sun_82072_fd_outb; + fdc_status = &sun_fdc->status_82072; + } } /* Success... */ diff --git a/include/asm-sparc/irq.h b/include/asm-sparc/irq.h index ff520ea97473..fe205cc444b8 100644 --- a/include/asm-sparc/irq.h +++ b/include/asm-sparc/irq.h @@ -1,184 +1,15 @@ -/* $Id: irq.h,v 1.32 2000/08/26 02:42:28 anton Exp $ - * irq.h: IRQ registers on the Sparc. +/* irq.h: IRQ registers on the Sparc. * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) */ #ifndef _SPARC_IRQ_H #define _SPARC_IRQ_H -#include <linux/linkage.h> -#include <linux/threads.h> /* For NR_CPUS */ #include <linux/interrupt.h> -#include <asm/system.h> /* For SUN4M_NCPUS */ -#include <asm/btfixup.h> - -#define __irq_ino(irq) irq -#define __irq_pil(irq) irq - #define NR_IRQS 16 #define irq_canonicalize(irq) (irq) -/* Dave Redman (djhr@tadpole.co.uk) - * changed these to function pointers.. it saves cycles and will allow - * the irq dependencies to be split into different files at a later date - * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size. - * Jakub Jelinek (jj@sunsite.mff.cuni.cz) - * Changed these to btfixup entities... It saves cycles :) - */ -BTFIXUPDEF_CALL(void, disable_irq, unsigned int) -BTFIXUPDEF_CALL(void, enable_irq, unsigned int) -BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int) -BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int) -BTFIXUPDEF_CALL(void, clear_clock_irq, void) -BTFIXUPDEF_CALL(void, clear_profile_irq, int) -BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int) - -static inline void disable_irq_nosync(unsigned int irq) -{ - BTFIXUP_CALL(disable_irq)(irq); -} - -static inline void disable_irq(unsigned int irq) -{ - BTFIXUP_CALL(disable_irq)(irq); -} - -static inline void enable_irq(unsigned int irq) -{ - BTFIXUP_CALL(enable_irq)(irq); -} - -static inline void disable_pil_irq(unsigned int irq) -{ - BTFIXUP_CALL(disable_pil_irq)(irq); -} - -static inline void enable_pil_irq(unsigned int irq) -{ - BTFIXUP_CALL(enable_pil_irq)(irq); -} - -static inline void clear_clock_irq(void) -{ - BTFIXUP_CALL(clear_clock_irq)(); -} - -static inline void clear_profile_irq(int irq) -{ - BTFIXUP_CALL(clear_profile_irq)(irq); -} - -static inline void load_profile_irq(int cpu, int limit) -{ - BTFIXUP_CALL(load_profile_irq)(cpu, limit); -} - -extern void (*sparc_init_timers)(irq_handler_t lvl10_irq); -extern void claim_ticker14(irq_handler_t irq_handler, - int irq, - unsigned int timeout); - -#ifdef CONFIG_SMP -BTFIXUPDEF_CALL(void, set_cpu_int, int, int) -BTFIXUPDEF_CALL(void, clear_cpu_int, int, int) -BTFIXUPDEF_CALL(void, set_irq_udt, int) - -#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level) -#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level) -#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu) -#endif - -extern int request_fast_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, __const__ char *devname); - -/* On the sun4m, just like the timers, we have both per-cpu and master - * interrupt registers. - */ - -/* These registers are used for sending/receiving irqs from/to - * different cpu's. - */ -struct sun4m_intreg_percpu { - unsigned int tbt; /* Interrupts still pending for this cpu. */ - - /* These next two registers are WRITE-ONLY and are only - * "on bit" sensitive, "off bits" written have NO affect. - */ - unsigned int clear; /* Clear this cpus irqs here. */ - unsigned int set; /* Set this cpus irqs here. */ - unsigned char space[PAGE_SIZE - 12]; -}; - -/* - * djhr - * Actually the clear and set fields in this struct are misleading.. - * according to the SLAVIO manual (and the same applies for the SEC) - * the clear field clears bits in the mask which will ENABLE that IRQ - * the set field sets bits in the mask to DISABLE the IRQ. - * - * Also the undirected_xx address in the SLAVIO is defined as - * RESERVED and write only.. - * - * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor - * sun4m machines, for MP the layout makes more sense. - */ -struct sun4m_intregs { - struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS]; - unsigned int tbt; /* IRQ's that are still pending. */ - unsigned int irqs; /* Master IRQ bits. */ - - /* Again, like the above, two these registers are WRITE-ONLY. */ - unsigned int clear; /* Clear master IRQ's by setting bits here. */ - unsigned int set; /* Set master IRQ's by setting bits here. */ - - /* This register is both READ and WRITE. */ - unsigned int undirected_target; /* Which cpu gets undirected irqs. */ -}; - -extern struct sun4m_intregs *sun4m_interrupts; - -/* - * Bit field defines for the interrupt registers on various - * Sparc machines. - */ - -/* The sun4c interrupt register. */ -#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */ -#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */ -#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */ -#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */ -#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */ -#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ -#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ - -/* Dave Redman (djhr@tadpole.co.uk) - * The sun4m interrupt registers. - */ -#define SUN4M_INT_ENABLE 0x80000000 -#define SUN4M_INT_E14 0x00000080 -#define SUN4M_INT_E10 0x00080000 - -#define SUN4M_HARD_INT(x) (0x000000001 << (x)) -#define SUN4M_SOFT_INT(x) (0x000010000 << (x)) - -#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ -#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ -#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */ -#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */ -#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ -#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ -#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ -#define SUN4M_INT_REALTIME 0x00080000 /* system timer */ -#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ -#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ -#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ -#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ -#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ -#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ - -#define SUN4M_INT_SBUS(x) (1 << (x+7)) -#define SUN4M_INT_VME(x) (1 << (x)) - #endif diff --git a/include/asm-sparc/of_device.h b/include/asm-sparc/of_device.h index 7cb00c1b09c6..e5f5aedc2293 100644 --- a/include/asm-sparc/of_device.h +++ b/include/asm-sparc/of_device.h @@ -3,13 +3,9 @@ #ifdef __KERNEL__ #include <linux/device.h> +#include <linux/of.h> #include <linux/mod_devicetable.h> #include <asm/openprom.h> -#include <asm/prom.h> - -extern struct bus_type ebus_bus_type; -extern struct bus_type sbus_bus_type; -extern struct bus_type of_bus_type; /* * The of_device is a kind of "base class" that is a superset of @@ -30,50 +26,13 @@ struct of_device int portid; int clock_freq; }; -#define to_of_device(d) container_of(d, struct of_device, dev) extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name); extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size); -extern struct of_device *of_find_device_by_node(struct device_node *); - -extern const struct of_device_id *of_match_device( - const struct of_device_id *matches, const struct of_device *dev); - -extern struct of_device *of_dev_get(struct of_device *dev); -extern void of_dev_put(struct of_device *dev); - -/* - * An of_platform_driver driver is attached to a basic of_device on - * the ISA, EBUS, and SBUS busses on sparc64. - */ -struct of_platform_driver -{ - char *name; - struct of_device_id *match_table; - struct module *owner; - - int (*probe)(struct of_device* dev, const struct of_device_id *match); - int (*remove)(struct of_device* dev); - - int (*suspend)(struct of_device* dev, pm_message_t state); - int (*resume)(struct of_device* dev); - int (*shutdown)(struct of_device* dev); - - struct device_driver driver; -}; -#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver) - -extern int of_register_driver(struct of_platform_driver *drv, - struct bus_type *bus); -extern void of_unregister_driver(struct of_platform_driver *drv); -extern int of_device_register(struct of_device *ofdev); -extern void of_device_unregister(struct of_device *ofdev); -extern struct of_device *of_platform_device_create(struct device_node *np, - const char *bus_id, - struct device *parent, - struct bus_type *bus); -extern void of_release_dev(struct device *dev); +/* These are just here during the transition */ +#include <linux/of_device.h> +#include <linux/of_platform.h> #endif /* __KERNEL__ */ #endif /* _ASM_SPARC_OF_DEVICE_H */ diff --git a/include/asm-sparc/of_platform.h b/include/asm-sparc/of_platform.h new file mode 100644 index 000000000000..64a230064ef2 --- /dev/null +++ b/include/asm-sparc/of_platform.h @@ -0,0 +1,32 @@ +#ifndef _ASM_SPARC_OF_PLATFORM_H +#define _ASM_SPARC_OF_PLATFORM_H +/* + * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp. + * <benh@kernel.crashing.org> + * Modified for Sparc by merging parts of asm-sparc/of_device.h + * by Stephen Rothwell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +/* This is just here during the transition */ +#include <linux/of_platform.h> + +extern struct bus_type ebus_bus_type; +extern struct bus_type sbus_bus_type; +extern struct bus_type of_platform_bus_type; +#define of_bus_type of_platform_bus_type /* for compatibility */ + +extern int of_register_driver(struct of_platform_driver *drv, + struct bus_type *bus); +extern void of_unregister_driver(struct of_platform_driver *drv); +extern struct of_device *of_platform_device_create(struct device_node *np, + const char *bus_id, + struct device *parent, + struct bus_type *bus); + +#endif /* _ASM_SPARC_OF_PLATFORM_H */ diff --git a/include/asm-sparc/oplib.h b/include/asm-sparc/oplib.h index 91691e52c058..17ba82ee220a 100644 --- a/include/asm-sparc/oplib.h +++ b/include/asm-sparc/oplib.h @@ -158,32 +158,6 @@ extern void prom_putchar(char character); extern void prom_printf(char *fmt, ...); extern void prom_write(const char *buf, unsigned int len); -/* Query for input device type */ - -enum prom_input_device { - PROMDEV_IKBD, /* input from keyboard */ - PROMDEV_ITTYA, /* input from ttya */ - PROMDEV_ITTYB, /* input from ttyb */ - PROMDEV_IRSC, /* input from rsc */ - PROMDEV_IVCONS, /* input from virtual-console */ - PROMDEV_I_UNK, -}; - -extern enum prom_input_device prom_query_input_device(void); - -/* Query for output device type */ - -enum prom_output_device { - PROMDEV_OSCREEN, /* to screen */ - PROMDEV_OTTYA, /* to ttya */ - PROMDEV_OTTYB, /* to ttyb */ - PROMDEV_ORSC, /* to rsc */ - PROMDEV_OVCONS, /* to virtual-console */ - PROMDEV_O_UNK, -}; - -extern enum prom_output_device prom_query_output_device(void); - /* Multiprocessor operations... */ /* Start the CPU with the given device tree node, context table, and context diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index a55f4c3488b0..2cc235b74d94 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -46,7 +46,6 @@ BTFIXUPDEF_SIMM13(user_ptrs_per_pgd) #define pgd_ERROR(e) __builtin_trap() BTFIXUPDEF_INT(page_none) -BTFIXUPDEF_INT(page_shared) BTFIXUPDEF_INT(page_copy) BTFIXUPDEF_INT(page_readonly) BTFIXUPDEF_INT(page_kernel) @@ -66,7 +65,7 @@ BTFIXUPDEF_INT(page_kernel) #define PTE_SIZE (PTRS_PER_PTE*4) #define PAGE_NONE __pgprot(BTFIXUP_INT(page_none)) -#define PAGE_SHARED __pgprot(BTFIXUP_INT(page_shared)) +extern pgprot_t PAGE_SHARED; #define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy)) #define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly)) diff --git a/include/asm-sparc/prom.h b/include/asm-sparc/prom.h index 9ea105ebe2ff..71f2a1998324 100644 --- a/include/asm-sparc/prom.h +++ b/include/asm-sparc/prom.h @@ -2,7 +2,6 @@ #define _SPARC_PROM_H #ifdef __KERNEL__ - /* * Definitions for talking to the Open Firmware PROM on * Power Macintosh computers. @@ -17,11 +16,17 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ - #include <linux/types.h> #include <linux/proc_fs.h> #include <asm/atomic.h> +#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2 +#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 + +#define of_compat_cmp(s1, s2, l) strncmp((s1), (s2), (l)) +#define of_prop_cmp(s1, s2) strcasecmp((s1), (s2)) +#define of_node_cmp(s1, s2) strcmp((s1), (s2)) + typedef u32 phandle; typedef u32 ihandle; @@ -55,53 +60,35 @@ struct device_node { unsigned int unique_id; }; -/* flag descriptions */ -#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ - #define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) #define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) -#define OF_BAD_ADDR ((u64)-1) - -static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de) -{ - dn->pde = de; -} - -extern struct device_node *of_find_node_by_name(struct device_node *from, - const char *name); -#define for_each_node_by_name(dn, name) \ - for (dn = of_find_node_by_name(NULL, name); dn; \ - dn = of_find_node_by_name(dn, name)) -extern struct device_node *of_find_node_by_type(struct device_node *from, - const char *type); -#define for_each_node_by_type(dn, type) \ - for (dn = of_find_node_by_type(NULL, type); dn; \ - dn = of_find_node_by_type(dn, type)) -extern struct device_node *of_find_compatible_node(struct device_node *from, - const char *type, const char *compat); -extern struct device_node *of_find_node_by_path(const char *path); -extern struct device_node *of_find_node_by_phandle(phandle handle); -extern struct device_node *of_get_parent(const struct device_node *node); -extern struct device_node *of_get_next_child(const struct device_node *node, - struct device_node *prev); -extern struct property *of_find_property(const struct device_node *np, - const char *name, - int *lenp); -extern int of_device_is_compatible(const struct device_node *device, - const char *); -extern const void *of_get_property(const struct device_node *node, - const char *name, - int *lenp); -#define get_property(node,name,lenp) of_get_property(node,name,lenp) extern int of_set_property(struct device_node *node, const char *name, void *val, int len); extern int of_getintprop_default(struct device_node *np, const char *name, int def); -extern int of_n_addr_cells(struct device_node *np); -extern int of_n_size_cells(struct device_node *np); +extern int of_find_in_proplist(const char *list, const char *match, int len); extern void prom_build_devicetree(void); +/* Dummy ref counting routines - to be implemented later */ +static inline struct device_node *of_node_get(struct device_node *node) +{ + return node; +} +static inline void of_node_put(struct device_node *node) +{ +} + +/* + * NB: This is here while we transition from using asm/prom.h + * to linux/of.h + */ +#include <linux/of.h> + +extern struct device_node *of_console_device; +extern char *of_console_path; +extern char *of_console_options; + #endif /* __KERNEL__ */ #endif /* _SPARC_PROM_H */ diff --git a/include/asm-sparc/sbus.h b/include/asm-sparc/sbus.h index d036e4419d79..27d076c46964 100644 --- a/include/asm-sparc/sbus.h +++ b/include/asm-sparc/sbus.h @@ -68,7 +68,6 @@ struct sbus_dev { /* This struct describes the SBus(s) found on this machine. */ struct sbus_bus { struct of_device ofdev; - void *iommu; /* Opaque IOMMU cookie */ struct sbus_dev *devices; /* Link to devices on this SBus */ struct sbus_bus *next; /* next SBus, if more than one SBus */ int prom_node; /* PROM device tree node for this SBus */ diff --git a/include/asm-sparc/sfp-machine.h b/include/asm-sparc/sfp-machine.h index ecfc86a4a725..266a42b8f99f 100644 --- a/include/asm-sparc/sfp-machine.h +++ b/include/asm-sparc/sfp-machine.h @@ -203,4 +203,10 @@ extern struct task_struct *last_task_used_math; #define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex) #endif +#ifdef CONFIG_SMP +#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f) +#else +#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f) +#endif + #endif diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h index 8b4e23b3bb38..d1a2572e3f55 100644 --- a/include/asm-sparc/system.h +++ b/include/asm-sparc/system.h @@ -165,16 +165,6 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr, } while(0) /* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - -/* * Changing the IRQ level on the Sparc. */ extern void local_irq_restore(unsigned long); diff --git a/include/asm-sparc/tlbflush.h b/include/asm-sparc/tlbflush.h index 4a3b66618e75..a619da5cfaa9 100644 --- a/include/asm-sparc/tlbflush.h +++ b/include/asm-sparc/tlbflush.h @@ -57,6 +57,10 @@ BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long) /* * This is a kludge, until I know better. --zaitcev XXX */ -#define flush_tlb_kernel_range(start, end) flush_tlb_all() +static inline void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + flush_tlb_all(); +} #endif /* _SPARC_TLBFLUSH_H */ diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h index 64471bcd96f9..029b3e0d5e4c 100644 --- a/include/asm-sparc/unistd.h +++ b/include/asm-sparc/unistd.h @@ -1,4 +1,3 @@ -/* $Id: unistd.h,v 1.74 2002/02/08 03:57:18 davem Exp $ */ #ifndef _SPARC_UNISTD_H #define _SPARC_UNISTD_H @@ -9,7 +8,7 @@ * think of right now to force the arguments into fixed registers * before the trap into the system call with gcc 'asm' statements. * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) * * SunOS compatibility based upon preliminary work which is: * @@ -330,8 +329,9 @@ #define __NR_signalfd 311 #define __NR_timerfd 312 #define __NR_eventfd 313 +#define __NR_fallocate 314 -#define NR_SYSCALLS 314 +#define NR_SYSCALLS 315 #ifdef __KERNEL__ #define __ARCH_WANT_IPC_PARSE_VERSION diff --git a/include/asm-sparc64/a.out.h b/include/asm-sparc64/a.out.h index eb3b8e90b279..902e07f89a42 100644 --- a/include/asm-sparc64/a.out.h +++ b/include/asm-sparc64/a.out.h @@ -101,6 +101,8 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ STACK_TOP32 : STACK_TOP64) +#define STACK_TOP_MAX STACK_TOP64 + #endif #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/device.h b/include/asm-sparc64/device.h index d5a4559b9555..5111e8717be3 100644 --- a/include/asm-sparc64/device.h +++ b/include/asm-sparc64/device.h @@ -16,8 +16,6 @@ struct dev_archdata { struct device_node *prom_node; struct of_device *op; - - unsigned int msi_num; }; #endif /* _ASM_SPARC64_DEVICE_H */ diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h index c58ec1661df8..1fc655452b81 100644 --- a/include/asm-sparc64/dma-mapping.h +++ b/include/asm-sparc64/dma-mapping.h @@ -1,307 +1,160 @@ #ifndef _ASM_SPARC64_DMA_MAPPING_H #define _ASM_SPARC64_DMA_MAPPING_H - -#ifdef CONFIG_PCI - -/* we implement the API below in terms of the existing PCI one, - * so include it */ -#include <linux/pci.h> -/* need struct page definitions */ +#include <linux/scatterlist.h> #include <linux/mm.h> -#include <asm/of_device.h> - -static inline int -dma_supported(struct device *dev, u64 mask) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_dma_supported(to_pci_dev(dev), mask); -} - -static inline int -dma_set_mask(struct device *dev, u64 dma_mask) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_set_dma_mask(to_pci_dev(dev), dma_mask); -} - -static inline void * -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - gfp_t flag) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_iommu_ops->alloc_consistent(to_pci_dev(dev), size, dma_handle, flag); -} - -static inline void -dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle); -} - -static inline dma_addr_t -dma_map_single(struct device *dev, void *cpu_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction); -} - -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction); -} - -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_map_page(to_pci_dev(dev), page, offset, size, (int)direction); -} - -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_unmap_page(to_pci_dev(dev), dma_address, size, (int)direction); -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction); -} - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction); -} - -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_dma_sync_single_for_cpu(to_pci_dev(dev), dma_handle, - size, (int)direction); -} - -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); +#define DMA_ERROR_CODE (~(dma_addr_t)0x0) + +struct dma_ops { + void *(*alloc_coherent)(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + void (*free_coherent)(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle); + dma_addr_t (*map_single)(struct device *dev, void *cpu_addr, + size_t size, + enum dma_data_direction direction); + void (*unmap_single)(struct device *dev, dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction); + int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction); + void (*unmap_sg)(struct device *dev, struct scatterlist *sg, + int nhwentries, + enum dma_data_direction direction); + void (*sync_single_for_cpu)(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction); + void (*sync_single_for_device)(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction); + void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg, + int nelems, + enum dma_data_direction direction); + void (*sync_sg_for_device)(struct device *dev, struct scatterlist *sg, + int nelems, + enum dma_data_direction direction); +}; +extern const struct dma_ops *dma_ops; + +extern int dma_supported(struct device *dev, u64 mask); +extern int dma_set_mask(struct device *dev, u64 dma_mask); - pci_dma_sync_single_for_device(to_pci_dev(dev), dma_handle, - size, (int)direction); -} - -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_dma_sync_sg_for_cpu(to_pci_dev(dev), sg, nelems, (int)direction); -} - -static inline void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ - BUG_ON(dev->bus != &pci_bus_type); - - pci_dma_sync_sg_for_device(to_pci_dev(dev), sg, nelems, (int)direction); -} - -static inline int -dma_mapping_error(dma_addr_t dma_addr) +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) { - return pci_dma_mapping_error(dma_addr); + return dma_ops->alloc_coherent(dev, size, dma_handle, flag); } -#else - -struct device; -struct page; -struct scatterlist; - -static inline int -dma_supported(struct device *dev, u64 mask) +static inline void dma_free_coherent(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) { - BUG(); - return 0; + dma_ops->free_coherent(dev, size, cpu_addr, dma_handle); } -static inline int -dma_set_mask(struct device *dev, u64 dma_mask) +static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, + size_t size, + enum dma_data_direction direction) { - BUG(); - return 0; + return dma_ops->map_single(dev, cpu_addr, size, direction); } -static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag) +static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, + size_t size, + enum dma_data_direction direction) { - BUG(); - return NULL; + dma_ops->unmap_single(dev, dma_addr, size, direction); } -static inline void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle) +static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction) { - BUG(); + return dma_ops->map_single(dev, page_address(page) + offset, + size, direction); } -static inline dma_addr_t -dma_map_single(struct device *dev, void *cpu_addr, size_t size, - enum dma_data_direction direction) +static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, + enum dma_data_direction direction) { - BUG(); - return 0; + dma_ops->unmap_single(dev, dma_address, size, direction); } -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) +static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction) { - BUG(); + return dma_ops->map_sg(dev, sg, nents, direction); } -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction direction) +static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction) { - BUG(); - return 0; + dma_ops->unmap_sg(dev, sg, nents, direction); } -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) +static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) { - BUG(); + dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction); } -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) +static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, + size_t size, + enum dma_data_direction direction) { - BUG(); - return 0; + dma_ops->sync_single_for_device(dev, dma_handle, size, direction); } -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) +static inline void dma_sync_single_range_for_cpu(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) { - BUG(); + dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction); } -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) +static inline void dma_sync_single_range_for_device(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) { - BUG(); + dma_sync_single_for_device(dev, dma_handle+offset, size, direction); } -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ - BUG(); -} -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction direction) { - BUG(); + dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction); } -static inline void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction direction) { - BUG(); + dma_ops->sync_sg_for_device(dev, sg, nelems, direction); } -static inline int -dma_mapping_error(dma_addr_t dma_addr) +static inline int dma_mapping_error(dma_addr_t dma_addr) { - BUG(); - return 0; + return (dma_addr == DMA_ERROR_CODE); } -#endif /* PCI */ - - -/* Now for the API extensions over the pci_ one */ - -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_is_consistent(d, h) (1) - -static inline int -dma_get_cache_alignment(void) +static inline int dma_get_cache_alignment(void) { /* no easy way to get cache size on all processors, so return * the maximum possible, to be safe */ return (1 << INTERNODE_CACHE_SHIFT); } -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ - /* just sync everything, that's all the pci API can do */ - dma_sync_single_for_cpu(dev, dma_handle, offset+size, direction); -} - -static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ - /* just sync everything, that's all the pci API can do */ - dma_sync_single_for_device(dev, dma_handle, offset+size, direction); -} - -static inline void -dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction) -{ - /* could define this in terms of the dma_cache ... operations, - * but if you get this on a platform, you should convert the platform - * to using the generic device DMA API */ - BUG(); -} +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_is_consistent(d, h) (1) #endif /* _ASM_SPARC64_DMA_MAPPING_H */ diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h index 303d85e2f82e..8653e8665009 100644 --- a/include/asm-sparc64/elf.h +++ b/include/asm-sparc64/elf.h @@ -70,6 +70,7 @@ #define HWCAP_SPARC_V9 16 #define HWCAP_SPARC_ULTRA3 32 #define HWCAP_SPARC_BLKINIT 64 +#define HWCAP_SPARC_N2 128 /* * These are used to set parameters in the core dumps. @@ -155,8 +156,13 @@ static inline unsigned int sparc64_elf_hwcap(void) if (tlb_type == cheetah || tlb_type == cheetah_plus) cap |= HWCAP_SPARC_ULTRA3; - else if (tlb_type == hypervisor) - cap |= HWCAP_SPARC_BLKINIT; + else if (tlb_type == hypervisor) { + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || + sun4v_chip_type == SUN4V_CHIP_NIAGARA2) + cap |= HWCAP_SPARC_BLKINIT; + if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2) + cap |= HWCAP_SPARC_N2; + } return cap; } diff --git a/include/asm-sparc64/fb.h b/include/asm-sparc64/fb.h index d6cd3a175fc3..389012e5fbad 100644 --- a/include/asm-sparc64/fb.h +++ b/include/asm-sparc64/fb.h @@ -3,6 +3,7 @@ #include <linux/fb.h> #include <linux/fs.h> #include <asm/page.h> +#include <asm/prom.h> static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, unsigned long off) @@ -12,6 +13,14 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, static inline int fb_is_primary_device(struct fb_info *info) { + struct device *dev = info->device; + struct device_node *node; + + node = dev->archdata.prom_node; + if (node && + node == of_console_device) + return 1; + return 0; } diff --git a/include/asm-sparc64/fbio.h b/include/asm-sparc64/fbio.h index 500026d9f6e1..b9215a0907d3 100644 --- a/include/asm-sparc64/fbio.h +++ b/include/asm-sparc64/fbio.h @@ -2,6 +2,7 @@ #define __LINUX_FBIO_H #include <linux/compiler.h> +#include <linux/types.h> /* Constants used for fbio SunOS compatibility */ /* (C) 1996 Miguel de Icaza */ @@ -299,4 +300,31 @@ struct fb_clut32 { #define LEO_LD_GBL_MAP 0x01009000 #define LEO_UNK2_MAP 0x0100a000 +#ifdef __KERNEL__ +struct fbcmap32 { + int index; /* first element (0 origin) */ + int count; + u32 red; + u32 green; + u32 blue; +}; + +#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32) +#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32) + +struct fbcursor32 { + short set; /* what to set, choose from the list above */ + short enable; /* cursor on/off */ + struct fbcurpos pos; /* cursor position */ + struct fbcurpos hot; /* cursor hot spot */ + struct fbcmap32 cmap; /* color map info */ + struct fbcurpos size; /* cursor bit map size */ + u32 image; /* cursor image bits */ + u32 mask; /* cursor mask bits */ +}; + +#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32) +#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32) +#endif + #endif /* __LINUX_FBIO_H */ diff --git a/include/asm-sparc64/fcntl.h b/include/asm-sparc64/fcntl.h index b2aecf0054bd..111f6b3b8925 100644 --- a/include/asm-sparc64/fcntl.h +++ b/include/asm-sparc64/fcntl.h @@ -16,7 +16,7 @@ #define O_LARGEFILE 0x40000 #define O_DIRECT 0x100000 /* direct disk access hint */ #define O_NOATIME 0x200000 - +#define O_CLOEXEC 0x400000 #define F_GETOWN 5 /* for sockets. */ #define F_SETOWN 6 /* for sockets. */ diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h index 4aa0925e1b1b..1783239c7b40 100644 --- a/include/asm-sparc64/floppy.h +++ b/include/asm-sparc64/floppy.h @@ -1,7 +1,6 @@ -/* $Id: floppy.h,v 1.32 2001/10/26 17:59:36 davem Exp $ - * asm-sparc64/floppy.h: Sparc specific parts of the Floppy driver. +/* floppy.h: Sparc specific parts of the Floppy driver. * - * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) * * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be) @@ -11,6 +10,7 @@ #define __ASM_SPARC64_FLOPPY_H #include <linux/init.h> +#include <linux/pci.h> #include <asm/page.h> #include <asm/pgtable.h> diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index ad595b679842..9565a892801e 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -14,11 +14,6 @@ #define __SLOW_DOWN_IO do { } while (0) #define SLOW_DOWN_IO do { } while (0) -extern unsigned long virt_to_bus_not_defined_use_pci_map(volatile void *addr); -#define virt_to_bus virt_to_bus_not_defined_use_pci_map -extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr); -#define bus_to_virt bus_to_virt_not_defined_use_pci_map - /* BIO layer definitions. */ extern unsigned long kern_base, kern_size; #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h index 0b1813f41045..9eac6676caf1 100644 --- a/include/asm-sparc64/iommu.h +++ b/include/asm-sparc64/iommu.h @@ -1,7 +1,6 @@ -/* $Id: iommu.h,v 1.10 2001/03/08 09:55:56 davem Exp $ - * iommu.h: Definitions for the sun5 IOMMU. +/* iommu.h: Definitions for the sun5 IOMMU. * - * Copyright (C) 1996, 1999 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net) */ #ifndef _SPARC64_IOMMU_H #define _SPARC64_IOMMU_H @@ -33,6 +32,7 @@ struct iommu { unsigned long iommu_tsbbase; unsigned long iommu_flush; unsigned long iommu_flushinv; + unsigned long iommu_tags; unsigned long iommu_ctxflush; unsigned long write_complete_reg; unsigned long dummy_page; @@ -54,4 +54,7 @@ struct strbuf { volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)]; }; -#endif /* !(_SPARC_IOMMU_H) */ +extern int iommu_table_init(struct iommu *iommu, int tsbsize, + u32 dma_offset, u32 dma_addr_mask); + +#endif /* !(_SPARC64_IOMMU_H) */ diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index e6c436ef9356..c00ad152771b 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -16,21 +16,21 @@ #include <asm/ptrace.h> /* IMAP/ICLR register defines */ -#define IMAP_VALID 0x80000000 /* IRQ Enabled */ -#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ -#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */ +#define IMAP_VALID 0x80000000UL /* IRQ Enabled */ +#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */ +#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */ #define IMAP_TID_SHIFT 26 -#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */ +#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */ #define IMAP_AID_SHIFT 26 -#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */ +#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */ #define IMAP_NID_SHIFT 21 -#define IMAP_IGN 0x000007c0 /* IRQ Group Number */ -#define IMAP_INO 0x0000003f /* IRQ Number */ -#define IMAP_INR 0x000007ff /* Full interrupt number*/ +#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */ +#define IMAP_INO 0x0000003fUL /* IRQ Number */ +#define IMAP_INR 0x000007ffUL /* Full interrupt number*/ -#define ICLR_IDLE 0x00000000 /* Idle state */ -#define ICLR_TRANSMIT 0x00000001 /* Transmit state */ -#define ICLR_PENDING 0x00000003 /* Pending state */ +#define ICLR_IDLE 0x00000000UL /* Idle state */ +#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */ +#define ICLR_PENDING 0x00000003UL /* Pending state */ /* The largest number of unique interrupt sources we support. * If this needs to ever be larger than 255, you need to change @@ -53,6 +53,9 @@ extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, extern void sun4v_destroy_msi(unsigned int virt_irq); extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); +extern void sparc64_set_msi(unsigned int virt_irq, u32 msi); +extern u32 sparc64_get_msi(unsigned int virt_irq); + extern void fixup_irqs(void); static __inline__ void set_softint(unsigned long bits) diff --git a/include/asm-sparc64/kprobes.h b/include/asm-sparc64/kprobes.h index a331b7b0dff2..7f6774dca5f4 100644 --- a/include/asm-sparc64/kprobes.h +++ b/include/asm-sparc64/kprobes.h @@ -10,7 +10,6 @@ typedef u32 kprobe_opcode_t; #define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */ #define MAX_INSN_SIZE 2 -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry #define arch_remove_kprobe(p) do {} while (0) #define ARCH_INACTIVE_KPROBE_COUNT 0 diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h index e97c43133752..1acc7272e537 100644 --- a/include/asm-sparc64/mdesc.h +++ b/include/asm-sparc64/mdesc.h @@ -61,6 +61,16 @@ extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc); extern void mdesc_update(void); +struct mdesc_notifier_client { + void (*add)(struct mdesc_handle *handle, u64 node); + void (*remove)(struct mdesc_handle *handle, u64 node); + + const char *node_name; + struct mdesc_notifier_client *next; +}; + +extern void mdesc_register_notifier(struct mdesc_notifier_client *client); + extern void mdesc_fill_in_cpu_data(cpumask_t mask); extern void sun4v_mdesc_init(void); diff --git a/include/asm-sparc64/of_device.h b/include/asm-sparc64/of_device.h index 60e9173c9acb..46d69b3223c5 100644 --- a/include/asm-sparc64/of_device.h +++ b/include/asm-sparc64/of_device.h @@ -3,14 +3,9 @@ #ifdef __KERNEL__ #include <linux/device.h> +#include <linux/of.h> #include <linux/mod_devicetable.h> #include <asm/openprom.h> -#include <asm/prom.h> - -extern struct bus_type isa_bus_type; -extern struct bus_type ebus_bus_type; -extern struct bus_type sbus_bus_type; -extern struct bus_type of_bus_type; /* * The of_device is a kind of "base class" that is a superset of @@ -31,50 +26,13 @@ struct of_device int portid; int clock_freq; }; -#define to_of_device(d) container_of(d, struct of_device, dev) extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name); extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size); -extern struct of_device *of_find_device_by_node(struct device_node *); - -extern const struct of_device_id *of_match_device( - const struct of_device_id *matches, const struct of_device *dev); - -extern struct of_device *of_dev_get(struct of_device *dev); -extern void of_dev_put(struct of_device *dev); - -/* - * An of_platform_driver driver is attached to a basic of_device on - * the ISA, EBUS, and SBUS busses on sparc64. - */ -struct of_platform_driver -{ - char *name; - struct of_device_id *match_table; - struct module *owner; - - int (*probe)(struct of_device* dev, const struct of_device_id *match); - int (*remove)(struct of_device* dev); - - int (*suspend)(struct of_device* dev, pm_message_t state); - int (*resume)(struct of_device* dev); - int (*shutdown)(struct of_device* dev); - - struct device_driver driver; -}; -#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver) - -extern int of_register_driver(struct of_platform_driver *drv, - struct bus_type *bus); -extern void of_unregister_driver(struct of_platform_driver *drv); -extern int of_device_register(struct of_device *ofdev); -extern void of_device_unregister(struct of_device *ofdev); -extern struct of_device *of_platform_device_create(struct device_node *np, - const char *bus_id, - struct device *parent, - struct bus_type *bus); -extern void of_release_dev(struct device *dev); +/* These are just here during the transition */ +#include <linux/of_device.h> +#include <linux/of_platform.h> #endif /* __KERNEL__ */ #endif /* _ASM_SPARC64_OF_DEVICE_H */ diff --git a/include/asm-sparc64/of_platform.h b/include/asm-sparc64/of_platform.h new file mode 100644 index 000000000000..f7c1f17c7d52 --- /dev/null +++ b/include/asm-sparc64/of_platform.h @@ -0,0 +1,33 @@ +#ifndef _ASM_SPARC64_OF_PLATFORM_H +#define _ASM_SPARC64_OF_PLATFORM_H +/* + * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp. + * <benh@kernel.crashing.org> + * Modified for Sparc by merging parts of asm-sparc/of_device.h + * by Stephen Rothwell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +/* This is just here during the transition */ +#include <linux/of_platform.h> + +extern struct bus_type isa_bus_type; +extern struct bus_type ebus_bus_type; +extern struct bus_type sbus_bus_type; +extern struct bus_type of_platform_bus_type; +#define of_bus_type of_platform_bus_type /* for compatibility */ + +extern int of_register_driver(struct of_platform_driver *drv, + struct bus_type *bus); +extern void of_unregister_driver(struct of_platform_driver *drv); +extern struct of_device *of_platform_device_create(struct device_node *np, + const char *bus_id, + struct device *parent, + struct bus_type *bus); + +#endif /* _ASM_SPARC64_OF_PLATFORM_H */ diff --git a/include/asm-sparc64/oplib.h b/include/asm-sparc64/oplib.h index 992f9f7a476c..55c5bb27e4da 100644 --- a/include/asm-sparc64/oplib.h +++ b/include/asm-sparc64/oplib.h @@ -1,8 +1,7 @@ -/* $Id: oplib.h,v 1.14 2001/12/19 00:29:51 davem Exp $ - * oplib.h: Describes the interface and available routines in the +/* oplib.h: Describes the interface and available routines in the * Linux Prom library. * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz) */ @@ -31,8 +30,10 @@ extern int prom_chosen_node; extern const char prom_peer_name[]; extern const char prom_compatible_name[]; extern const char prom_root_compatible[]; +extern const char prom_cpu_compatible[]; extern const char prom_finddev_name[]; extern const char prom_chosen_path[]; +extern const char prom_cpu_path[]; extern const char prom_getprop_name[]; extern const char prom_mmu_name[]; extern const char prom_callmethod_name[]; @@ -140,32 +141,6 @@ extern void prom_putchar(char character); extern void prom_printf(const char *fmt, ...); extern void prom_write(const char *buf, unsigned int len); -/* Query for input device type */ - -enum prom_input_device { - PROMDEV_IKBD, /* input from keyboard */ - PROMDEV_ITTYA, /* input from ttya */ - PROMDEV_ITTYB, /* input from ttyb */ - PROMDEV_IRSC, /* input from rsc */ - PROMDEV_IVCONS, /* input from virtual-console */ - PROMDEV_I_UNK, -}; - -extern enum prom_input_device prom_query_input_device(void); - -/* Query for output device type */ - -enum prom_output_device { - PROMDEV_OSCREEN, /* to screen */ - PROMDEV_OTTYA, /* to ttya */ - PROMDEV_OTTYB, /* to ttyb */ - PROMDEV_ORSC, /* to rsc */ - PROMDEV_OVCONS, /* to virtual-console */ - PROMDEV_O_UNK, -}; - -extern enum prom_output_device prom_query_output_device(void); - /* Multiprocessor operations... */ #ifdef CONFIG_SMP /* Start the CPU with the given device tree node at the passed program @@ -319,12 +294,10 @@ extern int prom_inst2pkg(int); extern int prom_service_exists(const char *service_name); extern void prom_sun4v_guest_soft_state(void); -/* Client interface level routines. */ -extern void prom_set_trap_table(unsigned long tba); -extern void prom_set_trap_table_sun4v(unsigned long tba, unsigned long mmfsa); +extern int prom_ihandle2path(int handle, char *buffer, int bufsize); +/* Client interface level routines. */ extern long p1275_cmd(const char *, long, ...); - #if 0 #define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x)) diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h index 23cc63f049a8..8116e8f6062c 100644 --- a/include/asm-sparc64/parport.h +++ b/include/asm-sparc64/parport.h @@ -8,8 +8,9 @@ #define _ASM_SPARC64_PARPORT_H 1 #include <asm/ebus.h> -#include <asm/isa.h> #include <asm/ns87303.h> +#include <asm/of_device.h> +#include <asm/prom.h> #define PARPORT_PC_MAX_PORTS PARPORT_MAX @@ -35,8 +36,12 @@ static struct sparc_ebus_info { unsigned int addr; unsigned int count; int lock; + + struct parport *port; } sparc_ebus_dmas[PARPORT_PC_MAX_PORTS]; +static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS); + static __inline__ int request_dma(unsigned int dmanr, const char *device_id) { if (dmanr >= PARPORT_PC_MAX_PORTS) @@ -98,117 +103,145 @@ static __inline__ unsigned int get_dma_residue(unsigned int dmanr) return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info); } -static int ebus_ecpp_p(struct linux_ebus_device *edev) +static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match) { - if (!strcmp(edev->prom_node->name, "ecpp")) - return 1; - if (!strcmp(edev->prom_node->name, "parallel")) { - const char *compat; - - compat = of_get_property(edev->prom_node, - "compatible", NULL); - if (compat && - (!strcmp(compat, "ecpp") || - !strcmp(compat, "ns87317-ecpp") || - !strcmp(compat + 13, "ecpp"))) - return 1; + unsigned long base = op->resource[0].start; + unsigned long config = op->resource[1].start; + unsigned long d_base = op->resource[2].start; + unsigned long d_len; + struct device_node *parent; + struct parport *p; + int slot, err; + + parent = op->node->parent; + if (!strcmp(parent->name, "dma")) { + p = parport_pc_probe_port(base, base + 0x400, + op->irqs[0], PARPORT_DMA_NOFIFO, + op->dev.parent->parent); + if (!p) + return -ENOMEM; + dev_set_drvdata(&op->dev, p); + return 0; } + + for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) { + if (!test_and_set_bit(slot, dma_slot_map)) + break; + } + err = -ENODEV; + if (slot >= PARPORT_PC_MAX_PORTS) + goto out_err; + + spin_lock_init(&sparc_ebus_dmas[slot].info.lock); + + d_len = (op->resource[2].end - d_base) + 1UL; + sparc_ebus_dmas[slot].info.regs = + of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA"); + + if (!sparc_ebus_dmas[slot].info.regs) + goto out_clear_map; + + sparc_ebus_dmas[slot].info.flags = 0; + sparc_ebus_dmas[slot].info.callback = NULL; + sparc_ebus_dmas[slot].info.client_cookie = NULL; + sparc_ebus_dmas[slot].info.irq = 0xdeadbeef; + strcpy(sparc_ebus_dmas[slot].info.name, "parport"); + if (ebus_dma_register(&sparc_ebus_dmas[slot].info)) + goto out_unmap_regs; + + ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1); + + /* Configure IRQ to Push Pull, Level Low */ + /* Enable ECP, set bit 2 of the CTR first */ + outb(0x04, base + 0x02); + ns87303_modify(config, PCR, + PCR_EPP_ENABLE | + PCR_IRQ_ODRAIN, + PCR_ECP_ENABLE | + PCR_ECP_CLK_ENA | + PCR_IRQ_POLAR); + + /* CTR bit 5 controls direction of port */ + ns87303_modify(config, PTR, + 0, PTR_LPT_REG_DIR); + + p = parport_pc_probe_port(base, base + 0x400, + op->irqs[0], + slot, + op->dev.parent); + err = -ENOMEM; + if (!p) + goto out_disable_irq; + + dev_set_drvdata(&op->dev, p); + return 0; + +out_disable_irq: + ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0); + ebus_dma_unregister(&sparc_ebus_dmas[slot].info); + +out_unmap_regs: + of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len); + +out_clear_map: + clear_bit(slot, dma_slot_map); + +out_err: + return err; } -static int parport_isa_probe(int count) +static int __devexit ecpp_remove(struct of_device *op) { - struct sparc_isa_bridge *isa_br; - struct sparc_isa_device *isa_dev; - - for_each_isa(isa_br) { - for_each_isadev(isa_dev, isa_br) { - struct sparc_isa_device *child; - unsigned long base; - - if (strcmp(isa_dev->prom_node->name, "dma")) - continue; - - child = isa_dev->child; - while (child) { - if (!strcmp(child->prom_node->name, "parallel")) - break; - child = child->next; - } - if (!child) - continue; - - base = child->resource.start; - - /* No DMA, see commentary in - * asm-sparc64/floppy.h:isa_floppy_init() - */ - if (parport_pc_probe_port(base, base + 0x400, - child->irq, PARPORT_DMA_NOFIFO, - &child->bus->self->dev)) - count++; - } + struct parport *p = dev_get_drvdata(&op->dev); + int slot = p->dma; + + parport_pc_unregister_port(p); + + if (slot != PARPORT_DMA_NOFIFO) { + unsigned long d_base = op->resource[2].start; + unsigned long d_len; + + d_len = (op->resource[2].end - d_base) + 1UL; + + ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0); + ebus_dma_unregister(&sparc_ebus_dmas[slot].info); + of_iounmap(&op->resource[2], + sparc_ebus_dmas[slot].info.regs, + d_len); + clear_bit(slot, dma_slot_map); } - return count; + return 0; } -static int parport_pc_find_nonpci_ports (int autoirq, int autodma) +static struct of_device_id ecpp_match[] = { + { + .name = "ecpp", + }, + { + .name = "parallel", + .compatible = "ecpp", + }, + { + .name = "parallel", + .compatible = "ns87317-ecpp", + }, + {}, +}; + +static struct of_platform_driver ecpp_driver = { + .name = "ecpp", + .match_table = ecpp_match, + .probe = ecpp_probe, + .remove = __devexit_p(ecpp_remove), +}; + +static int parport_pc_find_nonpci_ports(int autoirq, int autodma) { - struct linux_ebus *ebus; - struct linux_ebus_device *edev; - int count = 0; - - for_each_ebus(ebus) { - for_each_ebusdev(edev, ebus) { - if (ebus_ecpp_p(edev)) { - unsigned long base = edev->resource[0].start; - unsigned long config = edev->resource[1].start; - unsigned long d_base = edev->resource[2].start; - unsigned long d_len; - - spin_lock_init(&sparc_ebus_dmas[count].info.lock); - d_len = (edev->resource[2].end - - d_base) + 1; - sparc_ebus_dmas[count].info.regs = - ioremap(d_base, d_len); - if (!sparc_ebus_dmas[count].info.regs) - continue; - sparc_ebus_dmas[count].info.flags = 0; - sparc_ebus_dmas[count].info.callback = NULL; - sparc_ebus_dmas[count].info.client_cookie = NULL; - sparc_ebus_dmas[count].info.irq = 0xdeadbeef; - strcpy(sparc_ebus_dmas[count].info.name, "parport"); - if (ebus_dma_register(&sparc_ebus_dmas[count].info)) - continue; - ebus_dma_irq_enable(&sparc_ebus_dmas[count].info, 1); - - /* Configure IRQ to Push Pull, Level Low */ - /* Enable ECP, set bit 2 of the CTR first */ - outb(0x04, base + 0x02); - ns87303_modify(config, PCR, - PCR_EPP_ENABLE | - PCR_IRQ_ODRAIN, - PCR_ECP_ENABLE | - PCR_ECP_CLK_ENA | - PCR_IRQ_POLAR); - - /* CTR bit 5 controls direction of port */ - ns87303_modify(config, PTR, - 0, PTR_LPT_REG_DIR); - - if (parport_pc_probe_port(base, base + 0x400, - edev->irqs[0], - count, - &ebus->self->dev)) - count++; - } - } - } + of_register_driver(&ecpp_driver, &of_bus_type); - count = parport_isa_probe(count); - - return count; + return 0; } #endif /* !(_ASM_SPARC64_PARPORT_H */ diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index e11ac100f043..1393e57d50fb 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -3,8 +3,7 @@ #ifdef __KERNEL__ -#include <linux/fs.h> -#include <linux/mm.h> +#include <linux/dma-mapping.h> /* Can be used to override the logic in pci_scan_bus for skipping * already-configured bus numbers - to be used for buggy BIOSes @@ -30,80 +29,42 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) /* We don't do dynamic PCI IRQ allocation */ } -/* Dynamic DMA mapping stuff. - */ - /* The PCI address space does not equal the physical memory * address space. The networking and block device layers use * this boolean for bounce buffer decisions. */ #define PCI_DMA_BUS_IS_PHYS (0) -#include <asm/scatterlist.h> - -struct pci_dev; - -struct pci_iommu_ops { - void *(*alloc_consistent)(struct pci_dev *, size_t, dma_addr_t *, gfp_t); - void (*free_consistent)(struct pci_dev *, size_t, void *, dma_addr_t); - dma_addr_t (*map_single)(struct pci_dev *, void *, size_t, int); - void (*unmap_single)(struct pci_dev *, dma_addr_t, size_t, int); - int (*map_sg)(struct pci_dev *, struct scatterlist *, int, int); - void (*unmap_sg)(struct pci_dev *, struct scatterlist *, int, int); - void (*dma_sync_single_for_cpu)(struct pci_dev *, dma_addr_t, size_t, int); - void (*dma_sync_sg_for_cpu)(struct pci_dev *, struct scatterlist *, int, int); -}; - -extern const struct pci_iommu_ops *pci_iommu_ops; - -/* Allocate and map kernel buffer using consistent mode DMA for a device. - * hwdev should be valid struct pci_dev pointer for PCI devices. - */ -static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle) +static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, + dma_addr_t *dma_handle) { - return pci_iommu_ops->alloc_consistent(hwdev, size, dma_handle, GFP_ATOMIC); + return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC); } -/* Free and unmap a consistent DMA buffer. - * cpu_addr is what was returned from pci_alloc_consistent, - * size must be the same as what as passed into pci_alloc_consistent, - * and likewise dma_addr must be the same as what *dma_addrp was set to. - * - * References to the memory and mappings associated with cpu_addr/dma_addr - * past this call are illegal. - */ -static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) +static inline void pci_free_consistent(struct pci_dev *pdev, size_t size, + void *vaddr, dma_addr_t dma_handle) { - return pci_iommu_ops->free_consistent(hwdev, size, vaddr, dma_handle); + return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle); } -/* Map a single buffer of the indicated size for DMA in streaming mode. - * The 32-bit bus address to use is returned. - * - * Once the device is given the dma address, the device owns this memory - * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed. - */ -static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) +static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, + size_t size, int direction) { - return pci_iommu_ops->map_single(hwdev, ptr, size, direction); + return dma_map_single(&pdev->dev, ptr, size, + (enum dma_data_direction) direction); } -/* Unmap a single streaming mode DMA translation. The dma_addr and size - * must match what was provided for in a previous pci_map_single call. All - * other usages are undefined. - * - * After this call, reads by the cpu to the buffer are guaranteed to see - * whatever the device wrote there. - */ -static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction) +static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr, + size_t size, int direction) { - pci_iommu_ops->unmap_single(hwdev, dma_addr, size, direction); + dma_unmap_single(&pdev->dev, dma_addr, size, + (enum dma_data_direction) direction); } -/* No highmem on sparc64, plus we have an IOMMU, so mapping pages is easy. */ #define pci_map_page(dev, page, off, size, dir) \ pci_map_single(dev, (page_address(page) + (off)), size, dir) -#define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir) +#define pci_unmap_page(dev,addr,sz,dir) \ + pci_unmap_single(dev,addr,sz,dir) /* pci_unmap_{single,page} is not a nop, thus... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ @@ -119,75 +80,48 @@ static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ (((PTR)->LEN_NAME) = (VAL)) -/* Map a set of buffers described by scatterlist in streaming - * mode for DMA. This is the scatter-gather version of the - * above pci_map_single interface. Here the scatter gather list - * elements are each tagged with the appropriate dma address - * and length. They are obtained via sg_dma_{address,length}(SG). - * - * NOTE: An implementation may be able to use a smaller number of - * DMA address/length pairs than there are SG table elements. - * (for example via virtual mapping capabilities) - * The routine returns the number of addr/length pairs actually - * used, at most nents. - * - * Device ownership issues as mentioned above for pci_map_single are - * the same here. - */ -static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) +static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg, + int nents, int direction) { - return pci_iommu_ops->map_sg(hwdev, sg, nents, direction); + return dma_map_sg(&pdev->dev, sg, nents, + (enum dma_data_direction) direction); } -/* Unmap a set of streaming mode DMA translations. - * Again, cpu read rules concerning calls here are the same as for - * pci_unmap_single() above. - */ -static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction) +static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg, + int nents, int direction) { - pci_iommu_ops->unmap_sg(hwdev, sg, nhwents, direction); + dma_unmap_sg(&pdev->dev, sg, nents, + (enum dma_data_direction) direction); } -/* Make physical memory consistent for a single - * streaming mode DMA translation after a transfer. - * - * If you perform a pci_map_single() but wish to interrogate the - * buffer using the cpu, yet do not wish to teardown the PCI dma - * mapping, you must call this function before doing so. At the - * next point you give the PCI dma address back to the card, you - * must first perform a pci_dma_sync_for_device, and then the - * device again owns the buffer. - */ -static inline void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction) +static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, + dma_addr_t dma_handle, + size_t size, int direction) { - pci_iommu_ops->dma_sync_single_for_cpu(hwdev, dma_handle, size, direction); + dma_sync_single_for_cpu(&pdev->dev, dma_handle, size, + (enum dma_data_direction) direction); } -static inline void -pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, - size_t size, int direction) +static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev, + dma_addr_t dma_handle, + size_t size, int direction) { /* No flushing needed to sync cpu writes to the device. */ - BUG_ON(direction == PCI_DMA_NONE); } -/* Make physical memory consistent for a set of streaming - * mode DMA translations after a transfer. - * - * The same as pci_dma_sync_single_* but for a scatter-gather list, - * same rules and usage. - */ -static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction) +static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, + struct scatterlist *sg, + int nents, int direction) { - pci_iommu_ops->dma_sync_sg_for_cpu(hwdev, sg, nelems, direction); + dma_sync_sg_for_cpu(&pdev->dev, sg, nents, + (enum dma_data_direction) direction); } -static inline void -pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, - int nelems, int direction) +static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev, + struct scatterlist *sg, + int nelems, int direction) { /* No flushing needed to sync cpu writes to the device. */ - BUG_ON(direction == PCI_DMA_NONE); } /* Return whether the given PCI device DMA address mask can @@ -206,11 +140,9 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) #define PCI64_ADDR_BASE 0xfffc000000000000UL -#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) - static inline int pci_dma_mapping_error(dma_addr_t dma_addr) { - return (dma_addr == PCI_DMA_ERROR_CODE); + return dma_mapping_error(dma_addr); } #ifdef CONFIG_PCI diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h index 88db872ce2f8..a1f53a4da405 100644 --- a/include/asm-sparc64/percpu.h +++ b/include/asm-sparc64/percpu.h @@ -3,6 +3,8 @@ #include <linux/compiler.h> +register unsigned long __local_per_cpu_offset asm("g5"); + #ifdef CONFIG_SMP #define setup_per_cpu_areas() do { } while (0) @@ -18,7 +20,10 @@ extern unsigned long __per_cpu_shift; #define DEFINE_PER_CPU(type, name) \ __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name -register unsigned long __local_per_cpu_offset asm("g5"); +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp /* var is in discarded region: offset to particular copy we want */ #define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu))) @@ -38,6 +43,8 @@ do { \ #define real_setup_per_cpu_areas() do { } while (0) #define DEFINE_PER_CPU(type, name) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) #define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var)) #define __get_cpu_var(var) per_cpu__##var diff --git a/include/asm-sparc64/power.h b/include/asm-sparc64/power.h deleted file mode 100644 index 94495c1ac4f6..000000000000 --- a/include/asm-sparc64/power.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _SPARC64_POWER_H -#define _SPARC64_POWER_H - -extern void wake_up_powerd(void); -extern int start_powerd(void); - -#endif /* !(_SPARC64_POWER_H) */ diff --git a/include/asm-sparc64/prom.h b/include/asm-sparc64/prom.h index b4df3042add0..07843f9f05df 100644 --- a/include/asm-sparc64/prom.h +++ b/include/asm-sparc64/prom.h @@ -2,7 +2,6 @@ #define _SPARC64_PROM_H #ifdef __KERNEL__ - /* * Definitions for talking to the Open Firmware PROM on * Power Macintosh computers. @@ -17,11 +16,17 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ - #include <linux/types.h> #include <linux/proc_fs.h> #include <asm/atomic.h> +#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2 +#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 + +#define of_compat_cmp(s1, s2, l) strncmp((s1), (s2), (l)) +#define of_prop_cmp(s1, s2) strcasecmp((s1), (s2)) +#define of_node_cmp(s1, s2) strcmp((s1), (s2)) + typedef u32 phandle; typedef u32 ihandle; @@ -63,54 +68,36 @@ struct of_irq_controller { void *data; }; -/* flag descriptions */ -#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ - #define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) #define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) -#define OF_BAD_ADDR ((u64)-1) - -static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de) -{ - dn->pde = de; -} - -extern struct device_node *of_find_node_by_name(struct device_node *from, - const char *name); -#define for_each_node_by_name(dn, name) \ - for (dn = of_find_node_by_name(NULL, name); dn; \ - dn = of_find_node_by_name(dn, name)) -extern struct device_node *of_find_node_by_type(struct device_node *from, - const char *type); -#define for_each_node_by_type(dn, type) \ - for (dn = of_find_node_by_type(NULL, type); dn; \ - dn = of_find_node_by_type(dn, type)) -extern struct device_node *of_find_compatible_node(struct device_node *from, - const char *type, const char *compat); -extern struct device_node *of_find_node_by_path(const char *path); -extern struct device_node *of_find_node_by_phandle(phandle handle); extern struct device_node *of_find_node_by_cpuid(int cpuid); -extern struct device_node *of_get_parent(const struct device_node *node); -extern struct device_node *of_get_next_child(const struct device_node *node, - struct device_node *prev); -extern struct property *of_find_property(const struct device_node *np, - const char *name, - int *lenp); -extern int of_device_is_compatible(const struct device_node *device, - const char *); -extern const void *of_get_property(const struct device_node *node, - const char *name, - int *lenp); -#define get_property(node,name,lenp) of_get_property(node,name,lenp) extern int of_set_property(struct device_node *node, const char *name, void *val, int len); extern int of_getintprop_default(struct device_node *np, const char *name, int def); -extern int of_n_addr_cells(struct device_node *np); -extern int of_n_size_cells(struct device_node *np); +extern int of_find_in_proplist(const char *list, const char *match, int len); extern void prom_build_devicetree(void); +/* Dummy ref counting routines - to be implemented later */ +static inline struct device_node *of_node_get(struct device_node *node) +{ + return node; +} +static inline void of_node_put(struct device_node *node) +{ +} + +/* + * NB: This is here while we transition from using asm/prom.h + * to linux/of.h + */ +#include <linux/of.h> + +extern struct device_node *of_console_device; +extern char *of_console_path; +extern char *of_console_options; + #endif /* __KERNEL__ */ #endif /* _SPARC64_PROM_H */ diff --git a/include/asm-sparc64/sbus.h b/include/asm-sparc64/sbus.h index 7efd49d31bb8..0151cad486f3 100644 --- a/include/asm-sparc64/sbus.h +++ b/include/asm-sparc64/sbus.h @@ -1,7 +1,6 @@ -/* $Id: sbus.h,v 1.14 2000/02/18 13:50:55 davem Exp $ - * sbus.h: Defines for the Sun SBus. +/* sbus.h: Defines for the Sun SBus. * - * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com) + * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net) */ #ifndef _SPARC64_SBUS_H @@ -69,7 +68,6 @@ struct sbus_dev { /* This struct describes the SBus(s) found on this machine. */ struct sbus_bus { struct of_device ofdev; - void *iommu; /* Opaque IOMMU cookie */ struct sbus_dev *devices; /* Tree of SBUS devices */ struct sbus_bus *next; /* Next SBUS in system */ int prom_node; /* OBP node of SBUS */ @@ -102,9 +100,18 @@ extern struct sbus_bus *sbus_root; extern void sbus_set_sbus64(struct sbus_dev *, int); extern void sbus_fill_device_irq(struct sbus_dev *); -/* These yield IOMMU mappings in consistent mode. */ -extern void *sbus_alloc_consistent(struct sbus_dev *, size_t, dma_addr_t *dma_addrp); -extern void sbus_free_consistent(struct sbus_dev *, size_t, void *, dma_addr_t); +static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size, + dma_addr_t *dma_handle) +{ + return dma_alloc_coherent(&sdev->ofdev.dev, size, + dma_handle, GFP_ATOMIC); +} + +static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle); +} #define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL #define SBUS_DMA_TODEVICE DMA_TO_DEVICE @@ -112,18 +119,67 @@ extern void sbus_free_consistent(struct sbus_dev *, size_t, void *, dma_addr_t); #define SBUS_DMA_NONE DMA_NONE /* All the rest use streaming mode mappings. */ -extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int); -extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int); -extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int); -extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int); +static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, + size_t size, int direction) +{ + return dma_map_single(&sdev->ofdev.dev, ptr, size, + (enum dma_data_direction) direction); +} + +static inline void sbus_unmap_single(struct sbus_dev *sdev, + dma_addr_t dma_addr, size_t size, + int direction) +{ + dma_unmap_single(&sdev->ofdev.dev, dma_addr, size, + (enum dma_data_direction) direction); +} + +static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, + int nents, int direction) +{ + return dma_map_sg(&sdev->ofdev.dev, sg, nents, + (enum dma_data_direction) direction); +} + +static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, + int nents, int direction) +{ + dma_unmap_sg(&sdev->ofdev.dev, sg, nents, + (enum dma_data_direction) direction); +} /* Finally, allow explicit synchronization of streamable mappings. */ -extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int); +static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, + dma_addr_t dma_handle, + size_t size, int direction) +{ + dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size, + (enum dma_data_direction) direction); +} #define sbus_dma_sync_single sbus_dma_sync_single_for_cpu -extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int); -extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int); + +static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, + dma_addr_t dma_handle, + size_t size, int direction) +{ + /* No flushing needed to sync cpu writes to the device. */ +} + +static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, + struct scatterlist *sg, + int nents, int direction) +{ + dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents, + (enum dma_data_direction) direction); +} #define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu -extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int); + +static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, + struct scatterlist *sg, + int nents, int direction) +{ + /* No flushing needed to sync cpu writes to the device. */ +} extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *); extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *); diff --git a/include/asm-sparc64/sfp-machine.h b/include/asm-sparc64/sfp-machine.h index 89d42431efb5..c9331b02d9c8 100644 --- a/include/asm-sparc64/sfp-machine.h +++ b/include/asm-sparc64/sfp-machine.h @@ -88,4 +88,6 @@ #define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex) +#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f) + #endif diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 23ad8a7987ad..cf7807813e85 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -38,6 +38,11 @@ #define L1DCACHE_SIZE 0x4000 +#define SUN4V_CHIP_INVALID 0x00 +#define SUN4V_CHIP_NIAGARA1 0x01 +#define SUN4V_CHIP_NIAGARA2 0x02 +#define SUN4V_CHIP_UNKNOWN 0xff + #ifndef __ASSEMBLY__ enum ultra_tlb_layout { @@ -49,6 +54,8 @@ enum ultra_tlb_layout { extern enum ultra_tlb_layout tlb_type; +extern int sun4v_chip_type; + extern int cheetah_pcache_forced_on; extern void cheetah_enable_pcache(void); diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index 8ba380ec6daa..3f175fa7e6d2 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h @@ -115,14 +115,8 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ #ifndef __ASSEMBLY__ extern void sun_do_break(void); -extern int serial_console; extern int stop_a_enabled; -static __inline__ int con_is_present(void) -{ - return serial_console ? 0 : 1; -} - extern void synchronize_user_stack(void); extern void __flushw_user(void); @@ -147,7 +141,6 @@ do { \ * not preserve it's value. Hairy, but it lets us remove 2 loads * and 2 stores in this critical code path. -DaveM */ -#define EXTRA_CLOBBER ,"%l1" #define switch_to(prev, next, last) \ do { if (test_thread_flag(TIF_PERFCTR)) { \ unsigned long __tmp; \ @@ -170,33 +163,34 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ "rdpr %%wstate, %%o5\n\t" \ - "stx %%o6, [%%g6 + %3]\n\t" \ - "stb %%o5, [%%g6 + %2]\n\t" \ - "rdpr %%cwp, %%o5\n\t" \ + "stx %%o6, [%%g6 + %6]\n\t" \ "stb %%o5, [%%g6 + %5]\n\t" \ - "mov %1, %%g6\n\t" \ - "ldub [%1 + %5], %%g1\n\t" \ + "rdpr %%cwp, %%o5\n\t" \ + "stb %%o5, [%%g6 + %8]\n\t" \ + "mov %4, %%g6\n\t" \ + "ldub [%4 + %8], %%g1\n\t" \ "wrpr %%g1, %%cwp\n\t" \ - "ldx [%%g6 + %3], %%o6\n\t" \ - "ldub [%%g6 + %2], %%o5\n\t" \ - "ldub [%%g6 + %4], %%o7\n\t" \ + "ldx [%%g6 + %6], %%o6\n\t" \ + "ldub [%%g6 + %5], %%o5\n\t" \ + "ldub [%%g6 + %7], %%o7\n\t" \ "wrpr %%o5, 0x0, %%wstate\n\t" \ "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ - "ldx [%%g6 + %6], %%g4\n\t" \ + "ldx [%%g6 + %9], %%g4\n\t" \ "brz,pt %%o7, 1f\n\t" \ " mov %%g7, %0\n\t" \ "b,a ret_from_syscall\n\t" \ "1:\n\t" \ - : "=&r" (last) \ + : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \ + "=r" (__local_per_cpu_offset) \ : "0" (task_thread_info(next)), \ "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ "i" (TI_CWP), "i" (TI_TASK) \ : "cc", \ "g1", "g2", "g3", "g7", \ - "l2", "l3", "l4", "l5", "l6", "l7", \ + "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ "i0", "i1", "i2", "i3", "i4", "i5", \ - "o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\ + "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \ /* If you fuck with this, update ret_from_syscall code too. */ \ if (test_thread_flag(TIF_PERFCTR)) { \ write_pcr(current_thread_info()->pcr_reg); \ @@ -204,16 +198,6 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ } \ } while(0) -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) { unsigned long tmp1, tmp2; diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index 53e96ed9c024..cb751b4d0f56 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h @@ -1,4 +1,3 @@ -/* $Id: unistd.h,v 1.50 2002/02/08 03:57:18 davem Exp $ */ #ifndef _SPARC64_UNISTD_H #define _SPARC64_UNISTD_H @@ -9,7 +8,7 @@ * think of right now to force the arguments into fixed registers * before the trap into the system call with gcc 'asm' statements. * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net) * * SunOS compatibility based upon preliminary work which is: * @@ -332,8 +331,9 @@ #define __NR_signalfd 311 #define __NR_timerfd 312 #define __NR_eventfd 313 +#define __NR_fallocate 314 -#define NR_SYSCALLS 314 +#define NR_SYSCALLS 315 #ifdef __KERNEL__ /* sysconf options, for SunOS compatibility */ diff --git a/include/asm-sparc64/vio.h b/include/asm-sparc64/vio.h index 83c96422e9d6..f7417e91b170 100644 --- a/include/asm-sparc64/vio.h +++ b/include/asm-sparc64/vio.h @@ -264,7 +264,7 @@ static inline u32 vio_dring_avail(struct vio_dring_state *dr, ((dr->prod - dr->cons) & (ring_size - 1))); } -#define VIO_MAX_TYPE_LEN 64 +#define VIO_MAX_TYPE_LEN 32 #define VIO_MAX_COMPAT_LEN 64 struct vio_dev { @@ -275,6 +275,8 @@ struct vio_dev { char compat[VIO_MAX_COMPAT_LEN]; int compat_len; + u64 dev_no; + unsigned long channel_id; unsigned int tx_irq; diff --git a/include/asm-sparc64/xor.h b/include/asm-sparc64/xor.h index 8ce3f1813e28..a0233884fc94 100644 --- a/include/asm-sparc64/xor.h +++ b/include/asm-sparc64/xor.h @@ -63,4 +63,8 @@ static struct xor_block_template xor_block_niagara = { /* For VIS for everything except Niagara. */ #define XOR_SELECT_TEMPLATE(FASTEST) \ - (tlb_type == hypervisor ? &xor_block_niagara : &xor_block_VIS) + ((tlb_type == hypervisor && \ + (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \ + sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \ + &xor_block_niagara : \ + &xor_block_VIS) diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h index 7016b893ac9d..78bc9eed26b2 100644 --- a/include/asm-um/a.out.h +++ b/include/asm-um/a.out.h @@ -17,4 +17,6 @@ extern int honeypot; #define STACK_TOP \ CHOOSE_MODE((honeypot ? host_task_size : task_size), task_size) +#define STACK_TOP_MAX STACK_TOP + #endif diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S index e3f010bd12b3..cb0248616d49 100644 --- a/include/asm-um/common.lds.S +++ b/include/asm-um/common.lds.S @@ -16,82 +16,112 @@ . = ALIGN(4096); .note : { *(.note.*) } - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } BUG_TABLE - __uml_setup_start = .; - .uml.setup.init : { *(.uml.setup.init) } - __uml_setup_end = .; + .uml.setup.init : { + __uml_setup_start = .; + *(.uml.setup.init) + __uml_setup_end = .; + } - __uml_help_start = .; - .uml.help.init : { *(.uml.help.init) } - __uml_help_end = .; + .uml.help.init : { + __uml_help_start = .; + *(.uml.help.init) + __uml_help_end = .; + } - __uml_postsetup_start = .; - .uml.postsetup.init : { *(.uml.postsetup.init) } - __uml_postsetup_end = .; + .uml.postsetup.init : { + __uml_postsetup_start = .; + *(.uml.postsetup.init) + __uml_postsetup_end = .; + } - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; + .init.setup : { + __setup_start = .; + *(.init.setup) + __setup_end = .; + } . = ALIGN(32); - __per_cpu_start = . ; - .data.percpu : { *(.data.percpu) } - __per_cpu_end = . ; + .data.percpu : { + __per_cpu_start = . ; + *(.data.percpu) + __per_cpu_end = . ; + } - __initcall_start = .; .initcall.init : { + __initcall_start = .; INITCALLS + __initcall_end = .; } - __initcall_end = .; - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; + .con_initcall.init : { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } - __uml_initcall_start = .; - .uml.initcall.init : { *(.uml.initcall.init) } - __uml_initcall_end = .; + .uml.initcall.init : { + __uml_initcall_start = .; + *(.uml.initcall.init) + __uml_initcall_end = .; + } __init_end = .; SECURITY_INIT - __exitcall_begin = .; - .exitcall : { *(.exitcall.exit) } - __exitcall_end = .; + .exitcall : { + __exitcall_begin = .; + *(.exitcall.exit) + __exitcall_end = .; + } - __uml_exitcall_begin = .; - .uml.exitcall : { *(.uml.exitcall.exit) } - __uml_exitcall_end = .; + .uml.exitcall : { + __uml_exitcall_begin = .; + *(.uml.exitcall.exit) + __uml_exitcall_end = .; + } . = ALIGN(4); - __alt_instructions = .; - .altinstructions : { *(.altinstructions) } - __alt_instructions_end = .; + .altinstructions : { + __alt_instructions = .; + *(.altinstructions) + __alt_instructions_end = .; + } .altinstr_replacement : { *(.altinstr_replacement) } /* .exit.text is discard at runtime, not link time, to deal with references from .altinstructions and .eh_frame */ .exit.text : { *(.exit.text) } .exit.data : { *(.exit.data) } - __preinit_array_start = .; - .preinit_array : { *(.preinit_array) } - __preinit_array_end = .; - __init_array_start = .; - .init_array : { *(.init_array) } - __init_array_end = .; - __fini_array_start = .; - .fini_array : { *(.fini_array) } - __fini_array_end = .; + .preinit_array : { + __preinit_array_start = .; + *(.preinit_array) + __preinit_array_end = .; + } + .init_array : { + __init_array_start = .; + *(.init_array) + __init_array_end = .; + } + .fini_array : { + __fini_array_start = .; + *(.fini_array) + __fini_array_end = .; + } . = ALIGN(4096); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } /* Sections to be discarded */ /DISCARD/ : { diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h index 8a8246d03936..857471c49dac 100644 --- a/include/asm-um/elf-x86_64.h +++ b/include/asm-um/elf-x86_64.h @@ -6,7 +6,9 @@ #ifndef __UM_ELF_X86_64_H #define __UM_ELF_X86_64_H +#include <linux/sched.h> #include <asm/user.h> +#include "skas.h" /* x86-64 relocation types, taken from asm-x86_64/elf.h */ #define R_X86_64_NONE 0 /* No reloc */ @@ -64,6 +66,44 @@ typedef struct { } elf_fpregset_t; PT_REGS_R15(regs) = 0; \ } while (0) +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + (pr_reg)[0] = (regs)->regs.skas.regs[0]; \ + (pr_reg)[1] = (regs)->regs.skas.regs[1]; \ + (pr_reg)[2] = (regs)->regs.skas.regs[2]; \ + (pr_reg)[3] = (regs)->regs.skas.regs[3]; \ + (pr_reg)[4] = (regs)->regs.skas.regs[4]; \ + (pr_reg)[5] = (regs)->regs.skas.regs[5]; \ + (pr_reg)[6] = (regs)->regs.skas.regs[6]; \ + (pr_reg)[7] = (regs)->regs.skas.regs[7]; \ + (pr_reg)[8] = (regs)->regs.skas.regs[8]; \ + (pr_reg)[9] = (regs)->regs.skas.regs[9]; \ + (pr_reg)[10] = (regs)->regs.skas.regs[10]; \ + (pr_reg)[11] = (regs)->regs.skas.regs[11]; \ + (pr_reg)[12] = (regs)->regs.skas.regs[12]; \ + (pr_reg)[13] = (regs)->regs.skas.regs[13]; \ + (pr_reg)[14] = (regs)->regs.skas.regs[14]; \ + (pr_reg)[15] = (regs)->regs.skas.regs[15]; \ + (pr_reg)[16] = (regs)->regs.skas.regs[16]; \ + (pr_reg)[17] = (regs)->regs.skas.regs[17]; \ + (pr_reg)[18] = (regs)->regs.skas.regs[18]; \ + (pr_reg)[19] = (regs)->regs.skas.regs[19]; \ + (pr_reg)[20] = (regs)->regs.skas.regs[20]; \ + (pr_reg)[21] = current->thread.arch.fs; \ + (pr_reg)[22] = 0; \ + (pr_reg)[23] = 0; \ + (pr_reg)[24] = 0; \ + (pr_reg)[25] = 0; \ + (pr_reg)[26] = 0; + +static inline int elf_core_copy_fpregs(struct task_struct *t, + elf_fpregset_t *fpu) +{ + int cpu = current_thread->cpu; + return save_fp_registers(userspace_pid[cpu], (unsigned long *) fpu); +} + +#define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu) + #ifdef TIF_IA32 /* XXX */ #error XXX, indeed clear_thread_flag(TIF_IA32); diff --git a/include/asm-v850/flat.h b/include/asm-v850/flat.h index 3888f59d6881..17f0ea566611 100644 --- a/include/asm-v850/flat.h +++ b/include/asm-v850/flat.h @@ -25,6 +25,7 @@ #define flat_stack_align(sp) /* nothing needed */ #define flat_argvp_envp_on_stack() 0 #define flat_old_ram_flag(flags) (flags) +#define flat_set_persistent(relval, p) 0 /* We store the type of relocation in the top 4 bits of the `relval.' */ @@ -46,7 +47,8 @@ flat_get_relocate_addr (unsigned long relval) For the v850, RP should always be half-word aligned. */ static inline unsigned long flat_get_addr_from_rp (unsigned long *rp, unsigned long relval, - unsigned long flags) + unsigned long flags, + unsigned long *persistent) { short *srp = (short *)rp; diff --git a/include/asm-v850/irq.h b/include/asm-v850/irq.h index 88687c181f01..7d0d4cd1ce54 100644 --- a/include/asm-v850/irq.h +++ b/include/asm-v850/irq.h @@ -50,16 +50,6 @@ init_irq_handlers (int base_irq, int num, int interval, interrupt. */ extern unsigned int handle_irq (int irq, struct pt_regs *regs); - -/* Enable interrupt handling on an irq. */ -extern void enable_irq(unsigned int irq); - -/* Disable an irq and wait for completion. */ -extern void disable_irq (unsigned int irq); - -/* Disable an irq without waiting. */ -extern void disable_irq_nosync (unsigned int irq); - #endif /* !__ASSEMBLY__ */ #endif /* __V850_IRQ_H__ */ diff --git a/include/asm-v850/thread_info.h b/include/asm-v850/thread_info.h index 82b8f2846207..1a9e6ae0c5fd 100644 --- a/include/asm-v850/thread_info.h +++ b/include/asm-v850/thread_info.h @@ -77,16 +77,14 @@ struct thread_info { * thread information flag bit numbers */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 5 +#define TIF_MEMDIE 4 /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-x86/Kbuild b/include/asm-x86/Kbuild new file mode 100644 index 000000000000..c5e43cb39874 --- /dev/null +++ b/include/asm-x86/Kbuild @@ -0,0 +1,88 @@ +include include/asm-generic/Kbuild.asm + +header-y += boot.h +header-y += bootsetup.h +header-y += debugreg_32.h +header-y += debugreg_64.h +header-y += debugreg.h +header-y += ldt_32.h +header-y += ldt_64.h +header-y += ldt.h +header-y += msr-index.h +header-y += prctl.h +header-y += ptrace-abi_32.h +header-y += ptrace-abi_64.h +header-y += ptrace-abi.h +header-y += sigcontext32.h +header-y += ucontext_32.h +header-y += ucontext_64.h +header-y += ucontext.h +header-y += vsyscall32.h + +unifdef-y += a.out_32.h +unifdef-y += a.out_64.h +unifdef-y += auxvec_32.h +unifdef-y += auxvec_64.h +unifdef-y += byteorder_32.h +unifdef-y += byteorder_64.h +unifdef-y += elf_32.h +unifdef-y += elf_64.h +unifdef-y += errno_32.h +unifdef-y += errno_64.h +unifdef-y += ioctls_32.h +unifdef-y += ioctls_64.h +unifdef-y += ipcbuf_32.h +unifdef-y += ipcbuf_64.h +unifdef-y += mce.h +unifdef-y += mman_32.h +unifdef-y += mman_64.h +unifdef-y += msgbuf_32.h +unifdef-y += msgbuf_64.h +unifdef-y += msr_32.h +unifdef-y += msr_64.h +unifdef-y += msr.h +unifdef-y += mtrr_32.h +unifdef-y += mtrr_64.h +unifdef-y += mtrr.h +unifdef-y += page_32.h +unifdef-y += page_64.h +unifdef-y += param_32.h +unifdef-y += param_64.h +unifdef-y += posix_types_32.h +unifdef-y += posix_types_64.h +unifdef-y += ptrace_32.h +unifdef-y += ptrace_64.h +unifdef-y += resource_32.h +unifdef-y += resource_64.h +unifdef-y += sembuf_32.h +unifdef-y += sembuf_64.h +unifdef-y += setup_32.h +unifdef-y += setup_64.h +unifdef-y += shmbuf_32.h +unifdef-y += shmbuf_64.h +unifdef-y += shmparam_32.h +unifdef-y += shmparam_64.h +unifdef-y += sigcontext_32.h +unifdef-y += sigcontext_64.h +unifdef-y += siginfo_32.h +unifdef-y += siginfo_64.h +unifdef-y += signal_32.h +unifdef-y += signal_64.h +unifdef-y += sockios_32.h +unifdef-y += sockios_64.h +unifdef-y += stat_32.h +unifdef-y += stat_64.h +unifdef-y += statfs_32.h +unifdef-y += statfs_64.h +unifdef-y += termbits_32.h +unifdef-y += termbits_64.h +unifdef-y += termios_32.h +unifdef-y += termios_64.h +unifdef-y += types_32.h +unifdef-y += types_64.h +unifdef-y += unistd_32.h +unifdef-y += unistd_64.h +unifdef-y += user_32.h +unifdef-y += user_64.h +unifdef-y += vm86.h +unifdef-y += vsyscall.h diff --git a/include/asm-x86/a.out.h b/include/asm-x86/a.out.h new file mode 100644 index 000000000000..5bc9b1d3b227 --- /dev/null +++ b/include/asm-x86/a.out.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "a.out_32.h" +# else +# include "a.out_64.h" +# endif +#else +# ifdef __i386__ +# include "a.out_32.h" +# else +# include "a.out_64.h" +# endif +#endif diff --git a/include/asm-i386/a.out.h b/include/asm-x86/a.out_32.h index ab17bb8e5465..851a60f8258c 100644 --- a/include/asm-i386/a.out.h +++ b/include/asm-x86/a.out_32.h @@ -20,6 +20,7 @@ struct exec #ifdef __KERNEL__ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP #endif diff --git a/include/asm-x86_64/a.out.h b/include/asm-x86/a.out_64.h index 7255cde06538..e789300e41a5 100644 --- a/include/asm-x86_64/a.out.h +++ b/include/asm-x86/a.out_64.h @@ -21,7 +21,8 @@ struct exec #ifdef __KERNEL__ #include <linux/thread_info.h> -#define STACK_TOP TASK_SIZE +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX TASK_SIZE64 #endif #endif /* __A_OUT_GNU_H__ */ diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h new file mode 100644 index 000000000000..0693689d4146 --- /dev/null +++ b/include/asm-x86/acpi.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "acpi_32.h" +#else +# include "acpi_64.h" +#endif diff --git a/include/asm-i386/acpi.h b/include/asm-x86/acpi_32.h index 449f3f272e07..125179adf044 100644 --- a/include/asm-i386/acpi.h +++ b/include/asm-x86/acpi_32.h @@ -121,19 +121,6 @@ static inline void acpi_disable_pci(void) } extern int acpi_irq_balance_set(char *str); -#else /* !CONFIG_ACPI */ - -#define acpi_lapic 0 -#define acpi_ioapic 0 -static inline void acpi_noirq_set(void) { } -static inline void acpi_disable_pci(void) { } -static inline void disable_acpi(void) { } - -#endif /* !CONFIG_ACPI */ - - -#ifdef CONFIG_ACPI_SLEEP - /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); extern void acpi_restore_state_mem(void); @@ -143,7 +130,15 @@ extern unsigned long acpi_wakeup_address; /* early initialization routine */ extern void acpi_reserve_bootmem(void); -#endif /*CONFIG_ACPI_SLEEP*/ +#else /* !CONFIG_ACPI */ + +#define acpi_lapic 0 +#define acpi_ioapic 0 +static inline void acpi_noirq_set(void) { } +static inline void acpi_disable_pci(void) { } +static inline void disable_acpi(void) { } + +#endif /* !CONFIG_ACPI */ #define ARCH_HAS_POWER_INIT 1 diff --git a/include/asm-x86_64/acpi.h b/include/asm-x86/acpi_64.h index a29f05087a31..98173357dd89 100644 --- a/include/asm-x86_64/acpi.h +++ b/include/asm-x86/acpi_64.h @@ -29,6 +29,7 @@ #ifdef __KERNEL__ #include <acpi/pdc_intel.h> +#include <asm/numa.h> #define COMPILER_DEPENDENT_INT64 long long #define COMPILER_DEPENDENT_UINT64 unsigned long long @@ -107,6 +108,15 @@ static inline void acpi_disable_pci(void) } extern int acpi_irq_balance_set(char *str); +/* routines for saving/restoring kernel state */ +extern int acpi_save_state_mem(void); +extern void acpi_restore_state_mem(void); + +extern unsigned long acpi_wakeup_address; + +/* early initialization routine */ +extern void acpi_reserve_bootmem(void); + #else /* !CONFIG_ACPI */ #define acpi_lapic 0 @@ -120,19 +130,6 @@ extern int acpi_numa; extern int acpi_scan_nodes(unsigned long start, unsigned long end); #define NR_NODE_MEMBLKS (MAX_NUMNODES*2) -#ifdef CONFIG_ACPI_SLEEP - -/* routines for saving/restoring kernel state */ -extern int acpi_save_state_mem(void); -extern void acpi_restore_state_mem(void); - -extern unsigned long acpi_wakeup_address; - -/* early initialization routine */ -extern void acpi_reserve_bootmem(void); - -#endif /*CONFIG_ACPI_SLEEP*/ - extern int acpi_disabled; extern int acpi_pci_disabled; @@ -141,6 +138,16 @@ extern int acpi_pci_disabled; extern int acpi_skip_timer_override; extern int acpi_use_timer_override; +#ifdef CONFIG_ACPI_NUMA +extern void __init acpi_fake_nodes(const struct bootnode *fake_nodes, + int num_nodes); +#else +static inline void acpi_fake_nodes(const struct bootnode *fake_nodes, + int num_nodes) +{ +} +#endif + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ diff --git a/include/asm-x86/agp.h b/include/asm-x86/agp.h new file mode 100644 index 000000000000..9348f1e4f6f1 --- /dev/null +++ b/include/asm-x86/agp.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "agp_32.h" +#else +# include "agp_64.h" +#endif diff --git a/include/asm-i386/agp.h b/include/asm-x86/agp_32.h index 6af173dbf123..6af173dbf123 100644 --- a/include/asm-i386/agp.h +++ b/include/asm-x86/agp_32.h diff --git a/include/asm-x86_64/agp.h b/include/asm-x86/agp_64.h index de338666f3f9..de338666f3f9 100644 --- a/include/asm-x86_64/agp.h +++ b/include/asm-x86/agp_64.h diff --git a/include/asm-x86/alternative-asm.i b/include/asm-x86/alternative-asm.i new file mode 100644 index 000000000000..4f360cd3c888 --- /dev/null +++ b/include/asm-x86/alternative-asm.i @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "alternative-asm_32.i" +#else +# include "alternative-asm_64.i" +#endif diff --git a/include/asm-i386/alternative-asm.i b/include/asm-x86/alternative-asm_32.i index f0510209ccbe..f0510209ccbe 100644 --- a/include/asm-i386/alternative-asm.i +++ b/include/asm-x86/alternative-asm_32.i diff --git a/include/asm-x86_64/alternative-asm.i b/include/asm-x86/alternative-asm_64.i index 0b3f1a2bb2cb..0b3f1a2bb2cb 100644 --- a/include/asm-x86_64/alternative-asm.i +++ b/include/asm-x86/alternative-asm_64.i diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h new file mode 100644 index 000000000000..9eef6a32a130 --- /dev/null +++ b/include/asm-x86/alternative.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "alternative_32.h" +#else +# include "alternative_64.h" +#endif diff --git a/include/asm-i386/alternative.h b/include/asm-x86/alternative_32.h index eb7da5402bfa..bda6c810c0f4 100644 --- a/include/asm-i386/alternative.h +++ b/include/asm-x86/alternative_32.h @@ -149,4 +149,6 @@ apply_paravirt(struct paravirt_patch_site *start, #define __parainstructions_end NULL #endif +extern void text_poke(void *addr, unsigned char *opcode, int len); + #endif /* _I386_ALTERNATIVE_H */ diff --git a/include/asm-x86_64/alternative.h b/include/asm-x86/alternative_64.h index eea7aecfac78..ab161e810151 100644 --- a/include/asm-x86_64/alternative.h +++ b/include/asm-x86/alternative_64.h @@ -154,4 +154,6 @@ apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end) #define __parainstructions_end NULL #endif +extern void text_poke(void *addr, unsigned char *opcode, int len); + #endif /* _X86_64_ALTERNATIVE_H */ diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h new file mode 100644 index 000000000000..9fbcc0bd2ac4 --- /dev/null +++ b/include/asm-x86/apic.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "apic_32.h" +#else +# include "apic_64.h" +#endif diff --git a/include/asm-i386/apic.h b/include/asm-x86/apic_32.h index 1e8f6f252dd3..4091b33dcb10 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-x86/apic_32.h @@ -116,6 +116,8 @@ extern void enable_NMI_through_LVT0 (void * dummy); extern int timer_over_8254; extern int local_apic_timer_c2_ok; +extern int local_apic_timer_disabled; + #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } diff --git a/include/asm-x86_64/apic.h b/include/asm-x86/apic_64.h index 45e9fca1febc..3c8f21eef0be 100644 --- a/include/asm-x86_64/apic.h +++ b/include/asm-x86/apic_64.h @@ -19,7 +19,7 @@ extern int apic_verbosity; extern int apic_runs_main_timer; extern int ioapic_force; -extern int apic_mapped; +extern int disable_apic_timer; /* * Define the default level of output to be very little @@ -79,12 +79,12 @@ extern void smp_local_timer_interrupt (void); extern void setup_boot_APIC_clock (void); extern void setup_secondary_APIC_clock (void); extern int APIC_init_uniprocessor (void); -extern void disable_APIC_timer(void); -extern void enable_APIC_timer(void); extern void setup_apic_routing(void); -extern void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector, - unsigned char msg_type, unsigned char mask); +extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector, + unsigned char msg_type, unsigned char mask); + +extern int apic_is_clustered_box(void); #define K8_APIC_EXT_LVT_BASE 0x500 #define K8_APIC_EXT_INT_MSG_FIX 0x0 @@ -93,10 +93,6 @@ extern void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector, #define K8_APIC_EXT_INT_MSG_EXT 0x7 #define K8_APIC_EXT_LVT_ENTRY_THRESHOLD 0 -void smp_send_timer_broadcast_ipi(void); -void switch_APIC_timer_to_ipi(void *cpumask); -void switch_ipi_to_APIC_timer(void *cpumask); - #define ARCH_APICTIMER_STOPS_ON_C3 1 extern unsigned boot_cpu_id; diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h new file mode 100644 index 000000000000..4542c220bf4d --- /dev/null +++ b/include/asm-x86/apicdef.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "apicdef_32.h" +#else +# include "apicdef_64.h" +#endif diff --git a/include/asm-i386/apicdef.h b/include/asm-x86/apicdef_32.h index 9f6995341fdc..9f6995341fdc 100644 --- a/include/asm-i386/apicdef.h +++ b/include/asm-x86/apicdef_32.h diff --git a/include/asm-x86_64/apicdef.h b/include/asm-x86/apicdef_64.h index 1dd40067c67c..1dd40067c67c 100644 --- a/include/asm-x86_64/apicdef.h +++ b/include/asm-x86/apicdef_64.h diff --git a/include/asm-i386/arch_hooks.h b/include/asm-x86/arch_hooks.h index a8c1fca9726d..a8c1fca9726d 100644 --- a/include/asm-i386/arch_hooks.h +++ b/include/asm-x86/arch_hooks.h diff --git a/include/asm-x86/atomic.h b/include/asm-x86/atomic.h new file mode 100644 index 000000000000..4e1b8873c474 --- /dev/null +++ b/include/asm-x86/atomic.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "atomic_32.h" +#else +# include "atomic_64.h" +#endif diff --git a/include/asm-i386/atomic.h b/include/asm-x86/atomic_32.h index 437aac801711..437aac801711 100644 --- a/include/asm-i386/atomic.h +++ b/include/asm-x86/atomic_32.h diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86/atomic_64.h index f2e64634fa48..f2e64634fa48 100644 --- a/include/asm-x86_64/atomic.h +++ b/include/asm-x86/atomic_64.h diff --git a/include/asm-x86/auxvec.h b/include/asm-x86/auxvec.h new file mode 100644 index 000000000000..7ff866f829ca --- /dev/null +++ b/include/asm-x86/auxvec.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "auxvec_32.h" +# else +# include "auxvec_64.h" +# endif +#else +# ifdef __i386__ +# include "auxvec_32.h" +# else +# include "auxvec_64.h" +# endif +#endif diff --git a/include/asm-i386/auxvec.h b/include/asm-x86/auxvec_32.h index 395e13016bfb..395e13016bfb 100644 --- a/include/asm-i386/auxvec.h +++ b/include/asm-x86/auxvec_32.h diff --git a/include/asm-x86_64/auxvec.h b/include/asm-x86/auxvec_64.h index 2403c4cfced2..1d5ab0d03950 100644 --- a/include/asm-x86_64/auxvec.h +++ b/include/asm-x86/auxvec_64.h @@ -1,4 +1,6 @@ #ifndef __ASM_X86_64_AUXVEC_H #define __ASM_X86_64_AUXVEC_H +#define AT_SYSINFO_EHDR 33 + #endif diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h new file mode 100644 index 000000000000..07e3f6d4fe47 --- /dev/null +++ b/include/asm-x86/bitops.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "bitops_32.h" +#else +# include "bitops_64.h" +#endif diff --git a/include/asm-i386/bitops.h b/include/asm-x86/bitops_32.h index a20fe9822f60..a20fe9822f60 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-x86/bitops_32.h diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86/bitops_64.h index d4dbbe5f7bd9..d4dbbe5f7bd9 100644 --- a/include/asm-x86_64/bitops.h +++ b/include/asm-x86/bitops_64.h diff --git a/include/asm-i386/boot.h b/include/asm-x86/boot.h index ed8affbf96cb..ed8affbf96cb 100644 --- a/include/asm-i386/boot.h +++ b/include/asm-x86/boot.h diff --git a/include/asm-i386/bootparam.h b/include/asm-x86/bootparam.h index 427d8652bfde..b91b01783e4b 100644 --- a/include/asm-i386/bootparam.h +++ b/include/asm-x86/bootparam.h @@ -4,8 +4,9 @@ #include <linux/types.h> #include <linux/screen_info.h> #include <linux/apm_bios.h> -#include <asm/e820.h> #include <linux/edd.h> +#include <asm/e820.h> +#include <asm/ist.h> #include <video/edid.h> struct setup_header { @@ -48,9 +49,9 @@ struct efi_info { u32 _pad1; u32 efi_systab; u32 efi_memdesc_size; - u32 efi_memdec_version; + u32 efi_memdesc_version; u32 efi_memmap; - u32 fi_memmap_size; + u32 efi_memmap_size; u32 _pad2[2]; }; @@ -59,7 +60,7 @@ struct boot_params { struct screen_info screen_info; /* 0x000 */ struct apm_bios_info apm_bios_info; /* 0x040 */ u8 _pad2[12]; /* 0x054 */ - u32 speedstep_info[4]; /* 0x060 */ + struct ist_info ist_info; /* 0x060 */ u8 _pad3[16]; /* 0x070 */ u8 hd0_info[16]; /* obsolete! */ /* 0x080 */ u8 hd1_info[16]; /* obsolete! */ /* 0x090 */ diff --git a/include/asm-x86_64/bootsetup.h b/include/asm-x86/bootsetup.h index 7b1c3ad155fd..7b1c3ad155fd 100644 --- a/include/asm-x86_64/bootsetup.h +++ b/include/asm-x86/bootsetup.h diff --git a/include/asm-x86/bug.h b/include/asm-x86/bug.h new file mode 100644 index 000000000000..c655d7f3a5e0 --- /dev/null +++ b/include/asm-x86/bug.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "bug_32.h" +#else +# include "bug_64.h" +#endif diff --git a/include/asm-i386/bug.h b/include/asm-x86/bug_32.h index b0fd78ca2619..b0fd78ca2619 100644 --- a/include/asm-i386/bug.h +++ b/include/asm-x86/bug_32.h diff --git a/include/asm-x86_64/bug.h b/include/asm-x86/bug_64.h index 682606414913..682606414913 100644 --- a/include/asm-x86_64/bug.h +++ b/include/asm-x86/bug_64.h diff --git a/include/asm-x86/bugs.h b/include/asm-x86/bugs.h new file mode 100644 index 000000000000..ddf42d36dd50 --- /dev/null +++ b/include/asm-x86/bugs.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "bugs_32.h" +#else +# include "bugs_64.h" +#endif diff --git a/include/asm-i386/bugs.h b/include/asm-x86/bugs_32.h index d28979ff73be..d28979ff73be 100644 --- a/include/asm-i386/bugs.h +++ b/include/asm-x86/bugs_32.h diff --git a/include/asm-x86_64/bugs.h b/include/asm-x86/bugs_64.h index b33dc04d8f42..b33dc04d8f42 100644 --- a/include/asm-x86_64/bugs.h +++ b/include/asm-x86/bugs_64.h diff --git a/include/asm-x86/byteorder.h b/include/asm-x86/byteorder.h new file mode 100644 index 000000000000..eb14b1870ed7 --- /dev/null +++ b/include/asm-x86/byteorder.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "byteorder_32.h" +# else +# include "byteorder_64.h" +# endif +#else +# ifdef __i386__ +# include "byteorder_32.h" +# else +# include "byteorder_64.h" +# endif +#endif diff --git a/include/asm-i386/byteorder.h b/include/asm-x86/byteorder_32.h index a45470a8b74a..a45470a8b74a 100644 --- a/include/asm-i386/byteorder.h +++ b/include/asm-x86/byteorder_32.h diff --git a/include/asm-x86_64/byteorder.h b/include/asm-x86/byteorder_64.h index 5e86c868c75e..5e86c868c75e 100644 --- a/include/asm-x86_64/byteorder.h +++ b/include/asm-x86/byteorder_64.h diff --git a/include/asm-x86/cache.h b/include/asm-x86/cache.h new file mode 100644 index 000000000000..c36d190ac9d8 --- /dev/null +++ b/include/asm-x86/cache.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "cache_32.h" +#else +# include "cache_64.h" +#endif diff --git a/include/asm-i386/cache.h b/include/asm-x86/cache_32.h index 57c62f414158..57c62f414158 100644 --- a/include/asm-i386/cache.h +++ b/include/asm-x86/cache_32.h diff --git a/include/asm-x86_64/cache.h b/include/asm-x86/cache_64.h index 052df758ae61..052df758ae61 100644 --- a/include/asm-x86_64/cache.h +++ b/include/asm-x86/cache_64.h diff --git a/include/asm-x86/cacheflush.h b/include/asm-x86/cacheflush.h new file mode 100644 index 000000000000..e2df3b55034a --- /dev/null +++ b/include/asm-x86/cacheflush.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "cacheflush_32.h" +#else +# include "cacheflush_64.h" +#endif diff --git a/include/asm-i386/cacheflush.h b/include/asm-x86/cacheflush_32.h index 74e03c8f2e51..74e03c8f2e51 100644 --- a/include/asm-i386/cacheflush.h +++ b/include/asm-x86/cacheflush_32.h diff --git a/include/asm-x86_64/cacheflush.h b/include/asm-x86/cacheflush_64.h index ab1cb5c7dc92..ab1cb5c7dc92 100644 --- a/include/asm-x86_64/cacheflush.h +++ b/include/asm-x86/cacheflush_64.h diff --git a/include/asm-x86_64/calgary.h b/include/asm-x86/calgary.h index 4d5747a0923c..67f60406e2d8 100644 --- a/include/asm-x86_64/calgary.h +++ b/include/asm-x86/calgary.h @@ -1,7 +1,7 @@ /* * Derived from include/asm-powerpc/iommu.h * - * Copyright (C) IBM Corporation, 2006 + * Copyright IBM Corporation, 2006-2007 * * Author: Jon Mason <jdmason@us.ibm.com> * Author: Muli Ben-Yehuda <muli@il.ibm.com> @@ -31,6 +31,7 @@ #include <asm/types.h> struct iommu_table { + struct cal_chipset_ops *chip_ops; /* chipset specific funcs */ unsigned long it_base; /* mapped address of tce table */ unsigned long it_hint; /* Hint for next alloc */ unsigned long *it_map; /* A simple allocation bitmap for now */ @@ -42,6 +43,12 @@ struct iommu_table { unsigned char it_busno; /* Bus number this table belongs to */ }; +struct cal_chipset_ops { + void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev); + void (*tce_cache_blast)(struct iommu_table *tbl); + void (*dump_error_regs)(struct iommu_table *tbl); +}; + #define TCE_TABLE_SIZE_UNSPECIFIED ~0 #define TCE_TABLE_SIZE_64K 0 #define TCE_TABLE_SIZE_128K 1 diff --git a/include/asm-x86_64/calling.h b/include/asm-x86/calling.h index 6f4f63af96e1..6f4f63af96e1 100644 --- a/include/asm-x86_64/calling.h +++ b/include/asm-x86/calling.h diff --git a/include/asm-x86/checksum.h b/include/asm-x86/checksum.h new file mode 100644 index 000000000000..848850fd7d62 --- /dev/null +++ b/include/asm-x86/checksum.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "checksum_32.h" +#else +# include "checksum_64.h" +#endif diff --git a/include/asm-i386/checksum.h b/include/asm-x86/checksum_32.h index 75194abbe8ee..75194abbe8ee 100644 --- a/include/asm-i386/checksum.h +++ b/include/asm-x86/checksum_32.h diff --git a/include/asm-x86_64/checksum.h b/include/asm-x86/checksum_64.h index 419fe88a0342..419fe88a0342 100644 --- a/include/asm-x86_64/checksum.h +++ b/include/asm-x86/checksum_64.h diff --git a/include/asm-x86/cmpxchg.h b/include/asm-x86/cmpxchg.h new file mode 100644 index 000000000000..a460fa088d4c --- /dev/null +++ b/include/asm-x86/cmpxchg.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "cmpxchg_32.h" +#else +# include "cmpxchg_64.h" +#endif diff --git a/include/asm-i386/cmpxchg.h b/include/asm-x86/cmpxchg_32.h index 7adcef0cd53b..f86ede28f6dc 100644 --- a/include/asm-i386/cmpxchg.h +++ b/include/asm-x86/cmpxchg_32.h @@ -3,14 +3,16 @@ #include <linux/bitops.h> /* for LOCK_PREFIX */ +/* + * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you + * you need to test for the feature in boot_cpu_data. + */ + #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) struct __xchg_dummy { unsigned long a[100]; }; #define __xg(x) ((struct __xchg_dummy *)(x)) - -#ifdef CONFIG_X86_CMPXCHG64 - /* * The semantics of XCHGCMP8B are a bit strange, this is why * there is a loop and the loading of %%eax and %%edx has to @@ -32,7 +34,7 @@ static inline void __set_64bit (unsigned long long * ptr, "\n1:\t" "movl (%0), %%eax\n\t" "movl 4(%0), %%edx\n\t" - "lock cmpxchg8b (%0)\n\t" + LOCK_PREFIX "cmpxchg8b (%0)\n\t" "jnz 1b" : /* no outputs */ : "D"(ptr), @@ -65,8 +67,6 @@ static inline void __set_64bit_var (unsigned long long *ptr, __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \ __set_64bit(ptr, ll_low(value), ll_high(value)) ) -#endif - /* * Note: no "lock" prefix even on SMP: xchg always implies lock anyway * Note 2: xchg has side effect, so that attribute volatile is necessary, @@ -252,8 +252,6 @@ static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old, }) #endif -#ifdef CONFIG_X86_CMPXCHG64 - static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old, unsigned long long new) { @@ -289,5 +287,3 @@ static inline unsigned long long __cmpxchg64_local(volatile void *ptr, ((__typeof__(*(ptr)))__cmpxchg64_local((ptr),(unsigned long long)(o),\ (unsigned long long)(n))) #endif - -#endif diff --git a/include/asm-x86_64/cmpxchg.h b/include/asm-x86/cmpxchg_64.h index 09a6b6b6b74d..5e182062e6ec 100644 --- a/include/asm-x86_64/cmpxchg.h +++ b/include/asm-x86/cmpxchg_64.h @@ -128,7 +128,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ (unsigned long)(n),sizeof(*(ptr)))) #define cmpxchg_local(ptr,o,n)\ - ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ + ((__typeof__(*(ptr)))__cmpxchg_local((ptr),(unsigned long)(o),\ (unsigned long)(n),sizeof(*(ptr)))) #endif diff --git a/include/asm-x86_64/compat.h b/include/asm-x86/compat.h index 53cb96b68a62..53cb96b68a62 100644 --- a/include/asm-x86_64/compat.h +++ b/include/asm-x86/compat.h diff --git a/include/asm-i386/cpu.h b/include/asm-x86/cpu.h index 9d914e1e4aad..9d914e1e4aad 100644 --- a/include/asm-i386/cpu.h +++ b/include/asm-x86/cpu.h diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h new file mode 100644 index 000000000000..b7160a4598d7 --- /dev/null +++ b/include/asm-x86/cpufeature.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "cpufeature_32.h" +#else +# include "cpufeature_64.h" +#endif diff --git a/include/asm-i386/cpufeature.h b/include/asm-x86/cpufeature_32.h index c961c03cf1e2..7b3aa28ebc6e 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-x86/cpufeature_32.h @@ -79,7 +79,7 @@ #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ -#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ +/* 14 free */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86/cpufeature_64.h index 8baefc3beb2e..2983501e8b3e 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86/cpufeature_64.h @@ -1,5 +1,5 @@ /* - * cpufeature.h + * cpufeature_32.h * * Defines x86 CPU feature bits */ @@ -7,7 +7,7 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#include <asm-i386/cpufeature.h> +#include <asm/cpufeature_32.h> #undef cpu_has_vme #define cpu_has_vme 0 diff --git a/include/asm-x86/cputime.h b/include/asm-x86/cputime.h new file mode 100644 index 000000000000..87c37cf6b707 --- /dev/null +++ b/include/asm-x86/cputime.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "cputime_32.h" +#else +# include "cputime_64.h" +#endif diff --git a/include/asm-i386/cputime.h b/include/asm-x86/cputime_32.h index 398ed7cd171d..398ed7cd171d 100644 --- a/include/asm-i386/cputime.h +++ b/include/asm-x86/cputime_32.h diff --git a/include/asm-x86_64/cputime.h b/include/asm-x86/cputime_64.h index a07012dc5a3c..a07012dc5a3c 100644 --- a/include/asm-x86_64/cputime.h +++ b/include/asm-x86/cputime_64.h diff --git a/include/asm-x86/current.h b/include/asm-x86/current.h new file mode 100644 index 000000000000..d2526d3f7346 --- /dev/null +++ b/include/asm-x86/current.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "current_32.h" +#else +# include "current_64.h" +#endif diff --git a/include/asm-i386/current.h b/include/asm-x86/current_32.h index d35248539912..d35248539912 100644 --- a/include/asm-i386/current.h +++ b/include/asm-x86/current_32.h diff --git a/include/asm-x86_64/current.h b/include/asm-x86/current_64.h index bc8adecee66d..bc8adecee66d 100644 --- a/include/asm-x86_64/current.h +++ b/include/asm-x86/current_64.h diff --git a/include/asm-x86/debugreg.h b/include/asm-x86/debugreg.h new file mode 100644 index 000000000000..b6ce7e4fa002 --- /dev/null +++ b/include/asm-x86/debugreg.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "debugreg_32.h" +# else +# include "debugreg_64.h" +# endif +#else +# ifdef __i386__ +# include "debugreg_32.h" +# else +# include "debugreg_64.h" +# endif +#endif diff --git a/include/asm-i386/debugreg.h b/include/asm-x86/debugreg_32.h index f0b2b06ae0f7..f0b2b06ae0f7 100644 --- a/include/asm-i386/debugreg.h +++ b/include/asm-x86/debugreg_32.h diff --git a/include/asm-x86_64/debugreg.h b/include/asm-x86/debugreg_64.h index bd1aab1d8c4a..bd1aab1d8c4a 100644 --- a/include/asm-x86_64/debugreg.h +++ b/include/asm-x86/debugreg_64.h diff --git a/include/asm-x86/delay.h b/include/asm-x86/delay.h new file mode 100644 index 000000000000..10f2c71d622b --- /dev/null +++ b/include/asm-x86/delay.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "delay_32.h" +#else +# include "delay_64.h" +#endif diff --git a/include/asm-i386/delay.h b/include/asm-x86/delay_32.h index 9ae5e3782ed8..9ae5e3782ed8 100644 --- a/include/asm-i386/delay.h +++ b/include/asm-x86/delay_32.h diff --git a/include/asm-x86_64/delay.h b/include/asm-x86/delay_64.h index c2669f1f5529..c2669f1f5529 100644 --- a/include/asm-x86_64/delay.h +++ b/include/asm-x86/delay_64.h diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h new file mode 100644 index 000000000000..6065c5092265 --- /dev/null +++ b/include/asm-x86/desc.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "desc_32.h" +#else +# include "desc_64.h" +#endif diff --git a/include/asm-i386/desc.h b/include/asm-x86/desc_32.h index c547403f341d..c547403f341d 100644 --- a/include/asm-i386/desc.h +++ b/include/asm-x86/desc_32.h diff --git a/include/asm-x86_64/desc.h b/include/asm-x86/desc_64.h index ac991b5ca0fd..ac991b5ca0fd 100644 --- a/include/asm-x86_64/desc.h +++ b/include/asm-x86/desc_64.h diff --git a/include/asm-x86_64/desc_defs.h b/include/asm-x86/desc_defs.h index 089004070099..089004070099 100644 --- a/include/asm-x86_64/desc_defs.h +++ b/include/asm-x86/desc_defs.h diff --git a/include/asm-x86/device.h b/include/asm-x86/device.h new file mode 100644 index 000000000000..e2bcf7c7dcee --- /dev/null +++ b/include/asm-x86/device.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "device_32.h" +#else +# include "device_64.h" +#endif diff --git a/include/asm-i386/device.h b/include/asm-x86/device_32.h index 849604c70e6b..849604c70e6b 100644 --- a/include/asm-i386/device.h +++ b/include/asm-x86/device_32.h diff --git a/include/asm-x86_64/device.h b/include/asm-x86/device_64.h index 3afa03f33a36..3afa03f33a36 100644 --- a/include/asm-x86_64/device.h +++ b/include/asm-x86/device_64.h diff --git a/include/asm-x86/div64.h b/include/asm-x86/div64.h new file mode 100644 index 000000000000..8ac7da6ca284 --- /dev/null +++ b/include/asm-x86/div64.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "div64_32.h" +#else +# include "div64_64.h" +#endif diff --git a/include/asm-i386/div64.h b/include/asm-x86/div64_32.h index 438e980068bd..438e980068bd 100644 --- a/include/asm-i386/div64.h +++ b/include/asm-x86/div64_32.h diff --git a/include/asm-arm26/div64.h b/include/asm-x86/div64_64.h index 6cd978cefb28..6cd978cefb28 100644 --- a/include/asm-arm26/div64.h +++ b/include/asm-x86/div64_64.h diff --git a/include/asm-x86/dma-mapping.h b/include/asm-x86/dma-mapping.h new file mode 100644 index 000000000000..58f790f4df52 --- /dev/null +++ b/include/asm-x86/dma-mapping.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "dma-mapping_32.h" +#else +# include "dma-mapping_64.h" +#endif diff --git a/include/asm-i386/dma-mapping.h b/include/asm-x86/dma-mapping_32.h index f1d72d177f68..f1d72d177f68 100644 --- a/include/asm-i386/dma-mapping.h +++ b/include/asm-x86/dma-mapping_32.h diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86/dma-mapping_64.h index 6897e2a436e5..6897e2a436e5 100644 --- a/include/asm-x86_64/dma-mapping.h +++ b/include/asm-x86/dma-mapping_64.h diff --git a/include/asm-x86/dma.h b/include/asm-x86/dma.h new file mode 100644 index 000000000000..9f936c61a4e5 --- /dev/null +++ b/include/asm-x86/dma.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "dma_32.h" +#else +# include "dma_64.h" +#endif diff --git a/include/asm-i386/dma.h b/include/asm-x86/dma_32.h index d23aac8e1a50..d23aac8e1a50 100644 --- a/include/asm-i386/dma.h +++ b/include/asm-x86/dma_32.h diff --git a/include/asm-x86_64/dma.h b/include/asm-x86/dma_64.h index a37c16f06289..a37c16f06289 100644 --- a/include/asm-x86_64/dma.h +++ b/include/asm-x86/dma_64.h diff --git a/include/asm-x86/dmi.h b/include/asm-x86/dmi.h new file mode 100644 index 000000000000..c9e4e8ebc270 --- /dev/null +++ b/include/asm-x86/dmi.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "dmi_32.h" +#else +# include "dmi_64.h" +#endif diff --git a/include/asm-i386/dmi.h b/include/asm-x86/dmi_32.h index 38d4eeb7fc7e..38d4eeb7fc7e 100644 --- a/include/asm-i386/dmi.h +++ b/include/asm-x86/dmi_32.h diff --git a/include/asm-x86_64/dmi.h b/include/asm-x86/dmi_64.h index 93b2b15d4325..d02e32e3c3f0 100644 --- a/include/asm-x86_64/dmi.h +++ b/include/asm-x86/dmi_64.h @@ -3,15 +3,12 @@ #include <asm/io.h> -extern void *dmi_ioremap(unsigned long addr, unsigned long size); -extern void dmi_iounmap(void *addr, unsigned long size); - #define DMI_MAX_DATA 2048 extern int dmi_alloc_index; extern char dmi_alloc_data[DMI_MAX_DATA]; -/* This is so early that there is no good way to allocate dynamic memory. +/* This is so early that there is no good way to allocate dynamic memory. Allocate data in an BSS array. */ static inline void *dmi_alloc(unsigned len) { diff --git a/include/asm-x86/dwarf2.h b/include/asm-x86/dwarf2.h new file mode 100644 index 000000000000..b3cbb0ccae18 --- /dev/null +++ b/include/asm-x86/dwarf2.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "dwarf2_32.h" +#else +# include "dwarf2_64.h" +#endif diff --git a/include/asm-i386/dwarf2.h b/include/asm-x86/dwarf2_32.h index 6d66398a307d..6d66398a307d 100644 --- a/include/asm-i386/dwarf2.h +++ b/include/asm-x86/dwarf2_32.h diff --git a/include/asm-x86_64/dwarf2.h b/include/asm-x86/dwarf2_64.h index eedc08526b0b..eedc08526b0b 100644 --- a/include/asm-x86_64/dwarf2.h +++ b/include/asm-x86/dwarf2_64.h diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h new file mode 100644 index 000000000000..5d4d2183e5db --- /dev/null +++ b/include/asm-x86/e820.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "e820_32.h" +#else +# include "e820_64.h" +#endif diff --git a/include/asm-i386/e820.h b/include/asm-x86/e820_32.h index c03290ccecb2..cf67dbb1db79 100644 --- a/include/asm-i386/e820.h +++ b/include/asm-x86/e820_32.h @@ -47,6 +47,14 @@ extern void e820_register_memory(void); extern void limit_regions(unsigned long long size); extern void print_memory_map(char *who); +#if defined(CONFIG_PM) && defined(CONFIG_HIBERNATION) +extern void e820_mark_nosave_regions(void); +#else +static inline void e820_mark_nosave_regions(void) +{ +} +#endif + #endif/*!__ASSEMBLY__*/ #endif/*__E820_HEADER*/ diff --git a/include/asm-x86_64/e820.h b/include/asm-x86/e820_64.h index 3486e701bd86..3486e701bd86 100644 --- a/include/asm-x86_64/e820.h +++ b/include/asm-x86/e820_64.h diff --git a/include/asm-x86/edac.h b/include/asm-x86/edac.h new file mode 100644 index 000000000000..f8b888e140b0 --- /dev/null +++ b/include/asm-x86/edac.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "edac_32.h" +#else +# include "edac_64.h" +#endif diff --git a/include/asm-i386/edac.h b/include/asm-x86/edac_32.h index 3e7dd0ab68ce..3e7dd0ab68ce 100644 --- a/include/asm-i386/edac.h +++ b/include/asm-x86/edac_32.h diff --git a/include/asm-x86_64/edac.h b/include/asm-x86/edac_64.h index cad1cd42b4ee..cad1cd42b4ee 100644 --- a/include/asm-x86_64/edac.h +++ b/include/asm-x86/edac_64.h diff --git a/include/asm-x86/elf.h b/include/asm-x86/elf.h new file mode 100644 index 000000000000..ed6bb6e546b9 --- /dev/null +++ b/include/asm-x86/elf.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "elf_32.h" +# else +# include "elf_64.h" +# endif +#else +# ifdef __i386__ +# include "elf_32.h" +# else +# include "elf_64.h" +# endif +#endif diff --git a/include/asm-i386/elf.h b/include/asm-x86/elf_32.h index b32df3a332da..b32df3a332da 100644 --- a/include/asm-i386/elf.h +++ b/include/asm-x86/elf_32.h diff --git a/include/asm-x86_64/elf.h b/include/asm-x86/elf_64.h index 6d24ea7c4d9d..b4fbe47f6ccd 100644 --- a/include/asm-x86_64/elf.h +++ b/include/asm-x86/elf_64.h @@ -162,6 +162,19 @@ extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); /* 1GB for 64bit, 8MB for 32bit */ #define STACK_RND_MASK (test_thread_flag(TIF_IA32) ? 0x7ff : 0x3fffff) + +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 +struct linux_binprm; +extern int arch_setup_additional_pages(struct linux_binprm *bprm, + int executable_stack); + +extern int vdso_enabled; + +#define ARCH_DLINFO \ +do if (vdso_enabled) { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR,(unsigned long)current->mm->context.vdso);\ +} while (0) + #endif #endif diff --git a/include/asm-i386/emergency-restart.h b/include/asm-x86/emergency-restart.h index 680c39563345..680c39563345 100644 --- a/include/asm-i386/emergency-restart.h +++ b/include/asm-x86/emergency-restart.h diff --git a/include/asm-x86/errno.h b/include/asm-x86/errno.h new file mode 100644 index 000000000000..9d511be8e573 --- /dev/null +++ b/include/asm-x86/errno.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "errno_32.h" +# else +# include "errno_64.h" +# endif +#else +# ifdef __i386__ +# include "errno_32.h" +# else +# include "errno_64.h" +# endif +#endif diff --git a/include/asm-i386/errno.h b/include/asm-x86/errno_32.h index 969b34374728..969b34374728 100644 --- a/include/asm-i386/errno.h +++ b/include/asm-x86/errno_32.h diff --git a/include/asm-x86_64/errno.h b/include/asm-x86/errno_64.h index 311182129e32..311182129e32 100644 --- a/include/asm-x86_64/errno.h +++ b/include/asm-x86/errno_64.h diff --git a/include/asm-x86/fb.h b/include/asm-x86/fb.h new file mode 100644 index 000000000000..238c7ca45877 --- /dev/null +++ b/include/asm-x86/fb.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "fb_32.h" +#else +# include "fb_64.h" +#endif diff --git a/include/asm-i386/fb.h b/include/asm-x86/fb_32.h index d1c6297d4a61..d1c6297d4a61 100644 --- a/include/asm-i386/fb.h +++ b/include/asm-x86/fb_32.h diff --git a/include/asm-x86_64/fb.h b/include/asm-x86/fb_64.h index 60548e651d12..60548e651d12 100644 --- a/include/asm-x86_64/fb.h +++ b/include/asm-x86/fb_64.h diff --git a/include/asm-i386/fcntl.h b/include/asm-x86/fcntl.h index 46ab12db5739..46ab12db5739 100644 --- a/include/asm-i386/fcntl.h +++ b/include/asm-x86/fcntl.h diff --git a/include/asm-x86/fixmap.h b/include/asm-x86/fixmap.h new file mode 100644 index 000000000000..382eb271a892 --- /dev/null +++ b/include/asm-x86/fixmap.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "fixmap_32.h" +#else +# include "fixmap_64.h" +#endif diff --git a/include/asm-i386/fixmap.h b/include/asm-x86/fixmap_32.h index 249e753ac805..249e753ac805 100644 --- a/include/asm-i386/fixmap.h +++ b/include/asm-x86/fixmap_32.h diff --git a/include/asm-x86_64/fixmap.h b/include/asm-x86/fixmap_64.h index 2acb9b7f6418..cdfbe4a6ae6f 100644 --- a/include/asm-x86_64/fixmap.h +++ b/include/asm-x86/fixmap_64.h @@ -22,9 +22,9 @@ * compile time, but to set the physical address only * in the boot process. * - * these 'compile-time allocated' memory buffers are - * fixed-size 4k pages. (or larger if used with an increment - * highger than 1) use fixmap_set(idx,phys) to associate + * These 'compile-time allocated' memory buffers are + * fixed-size 4k pages (or larger if used with an increment + * higher than 1). Use set_fixmap(idx,phys) to associate * physical memory with fixmap indices. * * TLB entries of such buffers will not be flushed across diff --git a/include/asm-x86/floppy.h b/include/asm-x86/floppy.h new file mode 100644 index 000000000000..aecbb6dca21d --- /dev/null +++ b/include/asm-x86/floppy.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "floppy_32.h" +#else +# include "floppy_64.h" +#endif diff --git a/include/asm-i386/floppy.h b/include/asm-x86/floppy_32.h index 44ef2f55a8e9..44ef2f55a8e9 100644 --- a/include/asm-i386/floppy.h +++ b/include/asm-x86/floppy_32.h diff --git a/include/asm-x86_64/floppy.h b/include/asm-x86/floppy_64.h index 6ea13c3806f3..6ea13c3806f3 100644 --- a/include/asm-x86_64/floppy.h +++ b/include/asm-x86/floppy_64.h diff --git a/include/asm-x86_64/fpu32.h b/include/asm-x86/fpu32.h index 4153db5c0c31..4153db5c0c31 100644 --- a/include/asm-x86_64/fpu32.h +++ b/include/asm-x86/fpu32.h diff --git a/include/asm-i386/frame.i b/include/asm-x86/frame.i index 03620251ae17..03620251ae17 100644 --- a/include/asm-i386/frame.i +++ b/include/asm-x86/frame.i diff --git a/include/asm-x86/futex.h b/include/asm-x86/futex.h new file mode 100644 index 000000000000..1f4610e0c613 --- /dev/null +++ b/include/asm-x86/futex.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "futex_32.h" +#else +# include "futex_64.h" +#endif diff --git a/include/asm-i386/futex.h b/include/asm-x86/futex_32.h index 438ef0ec7101..438ef0ec7101 100644 --- a/include/asm-i386/futex.h +++ b/include/asm-x86/futex_32.h diff --git a/include/asm-x86_64/futex.h b/include/asm-x86/futex_64.h index 5cdfb08013c3..5cdfb08013c3 100644 --- a/include/asm-x86_64/futex.h +++ b/include/asm-x86/futex_64.h diff --git a/include/asm-x86/genapic.h b/include/asm-x86/genapic.h new file mode 100644 index 000000000000..d48bee663a6f --- /dev/null +++ b/include/asm-x86/genapic.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "genapic_32.h" +#else +# include "genapic_64.h" +#endif diff --git a/include/asm-i386/genapic.h b/include/asm-x86/genapic_32.h index 33e3ffe1766c..33e3ffe1766c 100644 --- a/include/asm-i386/genapic.h +++ b/include/asm-x86/genapic_32.h diff --git a/include/asm-x86_64/genapic.h b/include/asm-x86/genapic_64.h index d7e516ccbaa4..d7e516ccbaa4 100644 --- a/include/asm-x86_64/genapic.h +++ b/include/asm-x86/genapic_64.h diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h new file mode 100644 index 000000000000..d94898831bac --- /dev/null +++ b/include/asm-x86/geode.h @@ -0,0 +1,209 @@ +/* + * AMD Geode definitions + * Copyright (C) 2006, Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#ifndef _ASM_GEODE_H_ +#define _ASM_GEODE_H_ + +#include <asm/processor.h> +#include <linux/io.h> + +/* Generic southbridge functions */ + +#define GEODE_DEV_PMS 0 +#define GEODE_DEV_ACPI 1 +#define GEODE_DEV_GPIO 2 +#define GEODE_DEV_MFGPT 3 + +extern int geode_get_dev_base(unsigned int dev); + +/* Useful macros */ +#define geode_pms_base() geode_get_dev_base(GEODE_DEV_PMS) +#define geode_acpi_base() geode_get_dev_base(GEODE_DEV_ACPI) +#define geode_gpio_base() geode_get_dev_base(GEODE_DEV_GPIO) +#define geode_mfgpt_base() geode_get_dev_base(GEODE_DEV_MFGPT) + +/* MSRS */ + +#define GX_GLCP_SYS_RSTPLL 0x4C000014 + +#define MSR_LBAR_SMB 0x5140000B +#define MSR_LBAR_GPIO 0x5140000C +#define MSR_LBAR_MFGPT 0x5140000D +#define MSR_LBAR_ACPI 0x5140000E +#define MSR_LBAR_PMS 0x5140000F + +#define MSR_PIC_YSEL_LOW 0x51400020 +#define MSR_PIC_YSEL_HIGH 0x51400021 +#define MSR_PIC_ZSEL_LOW 0x51400022 +#define MSR_PIC_ZSEL_HIGH 0x51400023 + +#define MFGPT_IRQ_MSR 0x51400028 +#define MFGPT_NR_MSR 0x51400029 + +/* Resource Sizes */ + +#define LBAR_GPIO_SIZE 0xFF +#define LBAR_MFGPT_SIZE 0x40 +#define LBAR_ACPI_SIZE 0x40 +#define LBAR_PMS_SIZE 0x80 + +/* ACPI registers (PMS block) */ + +/* + * PM1_EN is only valid when VSA is enabled for 16 bit reads. + * When VSA is not enabled, *always* read both PM1_STS and PM1_EN + * with a 32 bit read at offset 0x0 + */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x08 +#define PM2_CNT 0x0C +#define PM_TMR 0x10 +#define PM_GPE0_STS 0x18 +#define PM_GPE0_EN 0x1C + +/* PMC registers (PMS block) */ + +#define PM_SSD 0x00 +#define PM_SCXA 0x04 +#define PM_SCYA 0x08 +#define PM_OUT_SLPCTL 0x0C +#define PM_SCLK 0x10 +#define PM_SED 0x1 +#define PM_SCXD 0x18 +#define PM_SCYD 0x1C +#define PM_IN_SLPCTL 0x20 +#define PM_WKD 0x30 +#define PM_WKXD 0x34 +#define PM_RD 0x38 +#define PM_WKXA 0x3C +#define PM_FSD 0x40 +#define PM_TSD 0x44 +#define PM_PSD 0x48 +#define PM_NWKD 0x4C +#define PM_AWKD 0x50 +#define PM_SSC 0x54 + +/* GPIO */ + +#define GPIO_OUTPUT_VAL 0x00 +#define GPIO_OUTPUT_ENABLE 0x04 +#define GPIO_OUTPUT_OPEN_DRAIN 0x08 +#define GPIO_OUTPUT_INVERT 0x0C +#define GPIO_OUTPUT_AUX1 0x10 +#define GPIO_OUTPUT_AUX2 0x14 +#define GPIO_PULL_UP 0x18 +#define GPIO_PULL_DOWN 0x1C +#define GPIO_INPUT_ENABLE 0x20 +#define GPIO_INPUT_INVERT 0x24 +#define GPIO_INPUT_FILTER 0x28 +#define GPIO_INPUT_EVENT_COUNT 0x2C +#define GPIO_READ_BACK 0x30 +#define GPIO_INPUT_AUX1 0x34 +#define GPIO_EVENTS_ENABLE 0x38 +#define GPIO_LOCK_ENABLE 0x3C +#define GPIO_POSITIVE_EDGE_EN 0x40 +#define GPIO_NEGATIVE_EDGE_EN 0x44 +#define GPIO_POSITIVE_EDGE_STS 0x48 +#define GPIO_NEGATIVE_EDGE_STS 0x4C + +#define GPIO_MAP_X 0xE0 +#define GPIO_MAP_Y 0xE4 +#define GPIO_MAP_Z 0xE8 +#define GPIO_MAP_W 0xEC + +extern void geode_gpio_set(unsigned int, unsigned int); +extern void geode_gpio_clear(unsigned int, unsigned int); +extern int geode_gpio_isset(unsigned int, unsigned int); +extern void geode_gpio_setup_event(unsigned int, int, int); +extern void geode_gpio_set_irq(unsigned int, unsigned int); + +static inline void geode_gpio_event_irq(unsigned int gpio, int pair) +{ + geode_gpio_setup_event(gpio, pair, 0); +} + +static inline void geode_gpio_event_pme(unsigned int gpio, int pair) +{ + geode_gpio_setup_event(gpio, pair, 1); +} + +/* Specific geode tests */ + +static inline int is_geode_gx(void) +{ + return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) && + (boot_cpu_data.x86 == 5) && + (boot_cpu_data.x86_model == 5)); +} + +static inline int is_geode_lx(void) +{ + return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && + (boot_cpu_data.x86 == 5) && + (boot_cpu_data.x86_model == 10)); +} + +static inline int is_geode(void) +{ + return (is_geode_gx() || is_geode_lx()); +} + +/* MFGPTs */ + +#define MFGPT_MAX_TIMERS 8 +#define MFGPT_TIMER_ANY -1 + +#define MFGPT_DOMAIN_WORKING 1 +#define MFGPT_DOMAIN_STANDBY 2 +#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY) + +#define MFGPT_CMP1 0 +#define MFGPT_CMP2 1 + +#define MFGPT_EVENT_IRQ 0 +#define MFGPT_EVENT_NMI 1 +#define MFGPT_EVENT_RESET 3 + +#define MFGPT_REG_CMP1 0 +#define MFGPT_REG_CMP2 2 +#define MFGPT_REG_COUNTER 4 +#define MFGPT_REG_SETUP 6 + +#define MFGPT_SETUP_CNTEN (1 << 15) +#define MFGPT_SETUP_CMP2 (1 << 14) +#define MFGPT_SETUP_CMP1 (1 << 13) +#define MFGPT_SETUP_SETUP (1 << 12) +#define MFGPT_SETUP_STOPEN (1 << 11) +#define MFGPT_SETUP_EXTEN (1 << 10) +#define MFGPT_SETUP_REVEN (1 << 5) +#define MFGPT_SETUP_CLKSEL (1 << 4) + +static inline void geode_mfgpt_write(int timer, u16 reg, u16 value) +{ + u32 base = geode_get_dev_base(GEODE_DEV_MFGPT); + outw(value, base + reg + (timer * 8)); +} + +static inline u16 geode_mfgpt_read(int timer, u16 reg) +{ + u32 base = geode_get_dev_base(GEODE_DEV_MFGPT); + return inw(base + reg + (timer * 8)); +} + +extern int __init geode_mfgpt_detect(void); +extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable); +extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable); +extern int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner); + +#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1) +#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0) + +#endif diff --git a/include/asm-x86/hardirq.h b/include/asm-x86/hardirq.h new file mode 100644 index 000000000000..314434d664e7 --- /dev/null +++ b/include/asm-x86/hardirq.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "hardirq_32.h" +#else +# include "hardirq_64.h" +#endif diff --git a/include/asm-i386/hardirq.h b/include/asm-x86/hardirq_32.h index 0e358dc405f8..34649585bb59 100644 --- a/include/asm-i386/hardirq.h +++ b/include/asm-x86/hardirq_32.h @@ -9,6 +9,7 @@ typedef struct { unsigned long idle_timestamp; unsigned int __nmi_count; /* arch dependent */ unsigned int apic_timer_irqs; /* arch dependent */ + unsigned int irq0_irqs; } ____cacheline_aligned irq_cpustat_t; DECLARE_PER_CPU(irq_cpustat_t, irq_stat); diff --git a/include/asm-x86_64/hardirq.h b/include/asm-x86/hardirq_64.h index 95d5e090ed89..95d5e090ed89 100644 --- a/include/asm-x86_64/hardirq.h +++ b/include/asm-x86/hardirq_64.h diff --git a/include/asm-i386/highmem.h b/include/asm-x86/highmem.h index 13cdcd66fff2..13cdcd66fff2 100644 --- a/include/asm-i386/highmem.h +++ b/include/asm-x86/highmem.h diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h new file mode 100644 index 000000000000..d4ab6db050b6 --- /dev/null +++ b/include/asm-x86/hpet.h @@ -0,0 +1,93 @@ +#ifndef ASM_X86_HPET_H +#define ASM_X86_HPET_H + +#ifdef CONFIG_HPET_TIMER + +/* + * Documentation on HPET can be found at: + * http://www.intel.com/ial/home/sp/pcmmspec.htm + * ftp://download.intel.com/ial/home/sp/mmts098.pdf + */ + +#define HPET_MMAP_SIZE 1024 + +#define HPET_ID 0x000 +#define HPET_PERIOD 0x004 +#define HPET_CFG 0x010 +#define HPET_STATUS 0x020 +#define HPET_COUNTER 0x0f0 +#define HPET_T0_CFG 0x100 +#define HPET_T0_CMP 0x108 +#define HPET_T0_ROUTE 0x110 +#define HPET_T1_CFG 0x120 +#define HPET_T1_CMP 0x128 +#define HPET_T1_ROUTE 0x130 +#define HPET_T2_CFG 0x140 +#define HPET_T2_CMP 0x148 +#define HPET_T2_ROUTE 0x150 + +#define HPET_ID_REV 0x000000ff +#define HPET_ID_NUMBER 0x00001f00 +#define HPET_ID_64BIT 0x00002000 +#define HPET_ID_LEGSUP 0x00008000 +#define HPET_ID_VENDOR 0xffff0000 +#define HPET_ID_NUMBER_SHIFT 8 +#define HPET_ID_VENDOR_SHIFT 16 + +#define HPET_ID_VENDOR_8086 0x8086 + +#define HPET_CFG_ENABLE 0x001 +#define HPET_CFG_LEGACY 0x002 +#define HPET_LEGACY_8254 2 +#define HPET_LEGACY_RTC 8 + +#define HPET_TN_LEVEL 0x0002 +#define HPET_TN_ENABLE 0x0004 +#define HPET_TN_PERIODIC 0x0008 +#define HPET_TN_PERIODIC_CAP 0x0010 +#define HPET_TN_64BIT_CAP 0x0020 +#define HPET_TN_SETVAL 0x0040 +#define HPET_TN_32BIT 0x0100 +#define HPET_TN_ROUTE 0x3e00 +#define HPET_TN_FSB 0x4000 +#define HPET_TN_FSB_CAP 0x8000 +#define HPET_TN_ROUTE_SHIFT 9 + +/* Max HPET Period is 10^8 femto sec as in HPET spec */ +#define HPET_MAX_PERIOD 100000000UL +/* + * Min HPET period is 10^5 femto sec just for safety. If it is less than this, + * then 32 bit HPET counter wrapsaround in less than 0.5 sec. + */ +#define HPET_MIN_PERIOD 100000UL + +/* hpet memory map physical address */ +extern unsigned long hpet_address; +extern unsigned long force_hpet_address; +extern int is_hpet_enabled(void); +extern int hpet_enable(void); +extern unsigned long hpet_readl(unsigned long a); +extern void force_hpet_resume(void); + +#ifdef CONFIG_HPET_EMULATE_RTC + +#include <linux/interrupt.h> + +extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask); +extern int hpet_set_rtc_irq_bit(unsigned long bit_mask); +extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min, + unsigned char sec); +extern int hpet_set_periodic_freq(unsigned long freq); +extern int hpet_rtc_dropped_irq(void); +extern int hpet_rtc_timer_init(void); +extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); + +#endif /* CONFIG_HPET_EMULATE_RTC */ + +#else + +static inline int hpet_enable(void) { return 0; } +static inline unsigned long hpet_readl(unsigned long a) { return 0; } + +#endif /* CONFIG_HPET_TIMER */ +#endif /* ASM_X86_HPET_H */ diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h new file mode 100644 index 000000000000..bf025399d939 --- /dev/null +++ b/include/asm-x86/hw_irq.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "hw_irq_32.h" +#else +# include "hw_irq_64.h" +#endif diff --git a/include/asm-i386/hw_irq.h b/include/asm-x86/hw_irq_32.h index 0bedbdf5e907..0bedbdf5e907 100644 --- a/include/asm-i386/hw_irq.h +++ b/include/asm-x86/hw_irq_32.h diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86/hw_irq_64.h index 6153ae5df2e8..09dfc18a6dd0 100644 --- a/include/asm-x86_64/hw_irq.h +++ b/include/asm-x86/hw_irq_64.h @@ -95,6 +95,26 @@ #ifndef __ASSEMBLY__ + +/* Interrupt handlers registered during init_IRQ */ +void apic_timer_interrupt(void); +void spurious_interrupt(void); +void error_interrupt(void); +void reschedule_interrupt(void); +void call_function_interrupt(void); +void irq_move_cleanup_interrupt(void); +void invalidate_interrupt0(void); +void invalidate_interrupt1(void); +void invalidate_interrupt2(void); +void invalidate_interrupt3(void); +void invalidate_interrupt4(void); +void invalidate_interrupt5(void); +void invalidate_interrupt6(void); +void invalidate_interrupt7(void); +void thermal_interrupt(void); +void threshold_interrupt(void); +void i8254_timer_resume(void); + typedef int vector_irq_t[NR_VECTORS]; DECLARE_PER_CPU(vector_irq_t, vector_irq); extern void __setup_vector_irq(int cpu); diff --git a/include/asm-i386/hypertransport.h b/include/asm-x86/hypertransport.h index c16c6ff4bdd7..c16c6ff4bdd7 100644 --- a/include/asm-i386/hypertransport.h +++ b/include/asm-x86/hypertransport.h diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h new file mode 100644 index 000000000000..a8bbed349664 --- /dev/null +++ b/include/asm-x86/i387.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "i387_32.h" +#else +# include "i387_64.h" +#endif diff --git a/include/asm-i386/i387.h b/include/asm-x86/i387_32.h index cdd1e248e3b4..cdd1e248e3b4 100644 --- a/include/asm-i386/i387.h +++ b/include/asm-x86/i387_32.h diff --git a/include/asm-x86_64/i387.h b/include/asm-x86/i387_64.h index 0217b74cc9fc..0217b74cc9fc 100644 --- a/include/asm-x86_64/i387.h +++ b/include/asm-x86/i387_64.h diff --git a/include/asm-x86/i8253.h b/include/asm-x86/i8253.h new file mode 100644 index 000000000000..747548ec5d1d --- /dev/null +++ b/include/asm-x86/i8253.h @@ -0,0 +1,15 @@ +#ifndef __ASM_I8253_H__ +#define __ASM_I8253_H__ + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 +#define PIT_CH2 0x42 + +extern spinlock_t i8253_lock; + +extern struct clock_event_device *global_clock_event; + +extern void setup_pit_timer(void); + +#endif /* __ASM_I8253_H__ */ diff --git a/include/asm-i386/i8259.h b/include/asm-x86/i8259.h index 29d8f9a6b3fc..29d8f9a6b3fc 100644 --- a/include/asm-i386/i8259.h +++ b/include/asm-x86/i8259.h diff --git a/include/asm-x86_64/ia32.h b/include/asm-x86/ia32.h index 0190b7c4e319..0190b7c4e319 100644 --- a/include/asm-x86_64/ia32.h +++ b/include/asm-x86/ia32.h diff --git a/include/asm-x86_64/ia32_unistd.h b/include/asm-x86/ia32_unistd.h index 5b52ce507338..5b52ce507338 100644 --- a/include/asm-x86_64/ia32_unistd.h +++ b/include/asm-x86/ia32_unistd.h diff --git a/include/asm-i386/ide.h b/include/asm-x86/ide.h index e7817a3d6578..e7817a3d6578 100644 --- a/include/asm-i386/ide.h +++ b/include/asm-x86/ide.h diff --git a/include/asm-x86_64/idle.h b/include/asm-x86/idle.h index 6bd47dcf2067..6bd47dcf2067 100644 --- a/include/asm-x86_64/idle.h +++ b/include/asm-x86/idle.h diff --git a/include/asm-x86/intel_arch_perfmon.h b/include/asm-x86/intel_arch_perfmon.h new file mode 100644 index 000000000000..4f6d4e6bf57e --- /dev/null +++ b/include/asm-x86/intel_arch_perfmon.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "intel_arch_perfmon_32.h" +#else +# include "intel_arch_perfmon_64.h" +#endif diff --git a/include/asm-i386/intel_arch_perfmon.h b/include/asm-x86/intel_arch_perfmon_32.h index b52cd60a075b..b52cd60a075b 100644 --- a/include/asm-i386/intel_arch_perfmon.h +++ b/include/asm-x86/intel_arch_perfmon_32.h diff --git a/include/asm-x86_64/intel_arch_perfmon.h b/include/asm-x86/intel_arch_perfmon_64.h index 8633331420ec..8633331420ec 100644 --- a/include/asm-x86_64/intel_arch_perfmon.h +++ b/include/asm-x86/intel_arch_perfmon_64.h diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h new file mode 100644 index 000000000000..5a58b176dd61 --- /dev/null +++ b/include/asm-x86/io.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "io_32.h" +#else +# include "io_64.h" +#endif diff --git a/include/asm-i386/io.h b/include/asm-x86/io_32.h index 7b65b5b00034..e8e0bd641120 100644 --- a/include/asm-i386/io.h +++ b/include/asm-x86/io_32.h @@ -112,6 +112,9 @@ extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsign * writew/writel functions and the other mmio helpers. The returned * address is not guaranteed to be usable directly as a virtual * address. + * + * If the area you are trying to map is a PCI BAR you should have a + * look at pci_iomap(). */ static inline void __iomem * ioremap(unsigned long offset, unsigned long size) diff --git a/include/asm-x86_64/io.h b/include/asm-x86/io_64.h index 7475095c5061..7475095c5061 100644 --- a/include/asm-x86_64/io.h +++ b/include/asm-x86/io_64.h diff --git a/include/asm-x86/io_apic.h b/include/asm-x86/io_apic.h new file mode 100644 index 000000000000..88494966beeb --- /dev/null +++ b/include/asm-x86/io_apic.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "io_apic_32.h" +#else +# include "io_apic_64.h" +#endif diff --git a/include/asm-i386/io_apic.h b/include/asm-x86/io_apic_32.h index 340764076d5f..dbe734ddf2af 100644 --- a/include/asm-i386/io_apic.h +++ b/include/asm-x86/io_apic_32.h @@ -150,7 +150,6 @@ extern int (*ioapic_renumber_irq)(int ioapic, int irq); #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 -static inline void disable_ioapic_setup(void) { } #endif #endif diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86/io_apic_64.h index 969d225a9350..d9f2e54324d5 100644 --- a/include/asm-x86_64/io_apic.h +++ b/include/asm-x86/io_apic_64.h @@ -109,6 +109,12 @@ extern int mpc_default_type; /* 1 if "noapic" boot option passed */ extern int skip_ioapic_setup; +static inline void disable_ioapic_setup(void) +{ + skip_ioapic_setup = 1; +} + + /* * If we use the IO-APIC for IRQ routing, disable automatic * assignment of PCI IRQ's. diff --git a/include/asm-arm26/ioctl.h b/include/asm-x86/ioctl.h index b279fe06dfe5..b279fe06dfe5 100644 --- a/include/asm-arm26/ioctl.h +++ b/include/asm-x86/ioctl.h diff --git a/include/asm-x86/ioctls.h b/include/asm-x86/ioctls.h new file mode 100644 index 000000000000..1e0fd48f18bc --- /dev/null +++ b/include/asm-x86/ioctls.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ioctls_32.h" +# else +# include "ioctls_64.h" +# endif +#else +# ifdef __i386__ +# include "ioctls_32.h" +# else +# include "ioctls_64.h" +# endif +#endif diff --git a/include/asm-i386/ioctls.h b/include/asm-x86/ioctls_32.h index ef5878762dc9..ef5878762dc9 100644 --- a/include/asm-i386/ioctls.h +++ b/include/asm-x86/ioctls_32.h diff --git a/include/asm-x86_64/ioctls.h b/include/asm-x86/ioctls_64.h index 3fc0b15a0d7e..3fc0b15a0d7e 100644 --- a/include/asm-x86_64/ioctls.h +++ b/include/asm-x86/ioctls_64.h diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h new file mode 100644 index 000000000000..5af471f228ee --- /dev/null +++ b/include/asm-x86/iommu.h @@ -0,0 +1,29 @@ +#ifndef _ASM_X8664_IOMMU_H +#define _ASM_X8664_IOMMU_H 1 + +extern void pci_iommu_shutdown(void); +extern void no_iommu_init(void); +extern int force_iommu, no_iommu; +extern int iommu_detected; +#ifdef CONFIG_IOMMU +extern void gart_iommu_init(void); +extern void gart_iommu_shutdown(void); +extern void __init gart_parse_options(char *); +extern void iommu_hole_init(void); +extern int fallback_aper_order; +extern int fallback_aper_force; +extern int iommu_aperture; +extern int iommu_aperture_allowed; +extern int iommu_aperture_disabled; +extern int fix_aperture; +#else +#define iommu_aperture 0 +#define iommu_aperture_allowed 0 + +static inline void gart_iommu_shutdown(void) +{ +} + +#endif + +#endif diff --git a/include/asm-arm26/ipc.h b/include/asm-x86/ipc.h index a46e3d9c2a3f..a46e3d9c2a3f 100644 --- a/include/asm-arm26/ipc.h +++ b/include/asm-x86/ipc.h diff --git a/include/asm-x86/ipcbuf.h b/include/asm-x86/ipcbuf.h new file mode 100644 index 000000000000..eb2e448c6e28 --- /dev/null +++ b/include/asm-x86/ipcbuf.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ipcbuf_32.h" +# else +# include "ipcbuf_64.h" +# endif +#else +# ifdef __i386__ +# include "ipcbuf_32.h" +# else +# include "ipcbuf_64.h" +# endif +#endif diff --git a/include/asm-i386/ipcbuf.h b/include/asm-x86/ipcbuf_32.h index 0dcad4f84c2a..0dcad4f84c2a 100644 --- a/include/asm-i386/ipcbuf.h +++ b/include/asm-x86/ipcbuf_32.h diff --git a/include/asm-x86_64/ipcbuf.h b/include/asm-x86/ipcbuf_64.h index 470cf85e3ba8..470cf85e3ba8 100644 --- a/include/asm-x86_64/ipcbuf.h +++ b/include/asm-x86/ipcbuf_64.h diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86/ipi.h index a7c75ea408a8..a7c75ea408a8 100644 --- a/include/asm-x86_64/ipi.h +++ b/include/asm-x86/ipi.h diff --git a/include/asm-x86/irq.h b/include/asm-x86/irq.h new file mode 100644 index 000000000000..7ba905465a53 --- /dev/null +++ b/include/asm-x86/irq.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "irq_32.h" +#else +# include "irq_64.h" +#endif diff --git a/include/asm-i386/irq.h b/include/asm-x86/irq_32.h index 9e15ce0006eb..36f310632c49 100644 --- a/include/asm-i386/irq.h +++ b/include/asm-x86/irq_32.h @@ -41,6 +41,7 @@ extern int irqbalance_disable(char *str); extern void fixup_irqs(cpumask_t map); #endif +unsigned int do_IRQ(struct pt_regs *regs); void init_IRQ(void); void __init native_init_IRQ(void); diff --git a/include/asm-x86_64/irq.h b/include/asm-x86/irq_64.h index 5006c6e75656..5006c6e75656 100644 --- a/include/asm-x86_64/irq.h +++ b/include/asm-x86/irq_64.h diff --git a/include/asm-x86/irq_regs.h b/include/asm-x86/irq_regs.h new file mode 100644 index 000000000000..89c898ab298b --- /dev/null +++ b/include/asm-x86/irq_regs.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "irq_regs_32.h" +#else +# include "irq_regs_64.h" +#endif diff --git a/include/asm-i386/irq_regs.h b/include/asm-x86/irq_regs_32.h index 3368b20c0b48..3368b20c0b48 100644 --- a/include/asm-i386/irq_regs.h +++ b/include/asm-x86/irq_regs_32.h diff --git a/include/asm-x86_64/irq_regs.h b/include/asm-x86/irq_regs_64.h index 3dd9c0b70270..3dd9c0b70270 100644 --- a/include/asm-x86_64/irq_regs.h +++ b/include/asm-x86/irq_regs_64.h diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h new file mode 100644 index 000000000000..1b695ff52687 --- /dev/null +++ b/include/asm-x86/irqflags.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "irqflags_32.h" +#else +# include "irqflags_64.h" +#endif diff --git a/include/asm-i386/irqflags.h b/include/asm-x86/irqflags_32.h index eff8585cb741..eff8585cb741 100644 --- a/include/asm-i386/irqflags.h +++ b/include/asm-x86/irqflags_32.h diff --git a/include/asm-x86_64/irqflags.h b/include/asm-x86/irqflags_64.h index 86e70fe23659..86e70fe23659 100644 --- a/include/asm-x86_64/irqflags.h +++ b/include/asm-x86/irqflags_64.h diff --git a/include/asm-i386/ist.h b/include/asm-x86/ist.h index d13d1e68afa9..ef2003ebc6f9 100644 --- a/include/asm-i386/ist.h +++ b/include/asm-x86/ist.h @@ -19,11 +19,13 @@ #ifdef __KERNEL__ +#include <linux/types.h> + struct ist_info { - unsigned long signature; - unsigned long command; - unsigned long event; - unsigned long perf_level; + u32 signature; + u32 command; + u32 event; + u32 perf_level; }; extern struct ist_info ist_info; diff --git a/include/asm-x86_64/k8.h b/include/asm-x86/k8.h index 699dd6961eda..699dd6961eda 100644 --- a/include/asm-x86_64/k8.h +++ b/include/asm-x86/k8.h diff --git a/include/asm-x86/kdebug.h b/include/asm-x86/kdebug.h new file mode 100644 index 000000000000..38479106c259 --- /dev/null +++ b/include/asm-x86/kdebug.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "kdebug_32.h" +#else +# include "kdebug_64.h" +#endif diff --git a/include/asm-i386/kdebug.h b/include/asm-x86/kdebug_32.h index a185b5f73e7f..a185b5f73e7f 100644 --- a/include/asm-i386/kdebug.h +++ b/include/asm-x86/kdebug_32.h diff --git a/include/asm-x86_64/kdebug.h b/include/asm-x86/kdebug_64.h index d7e2bcf49e4f..d7e2bcf49e4f 100644 --- a/include/asm-x86_64/kdebug.h +++ b/include/asm-x86/kdebug_64.h diff --git a/include/asm-x86/kexec.h b/include/asm-x86/kexec.h new file mode 100644 index 000000000000..718ddbfb9516 --- /dev/null +++ b/include/asm-x86/kexec.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "kexec_32.h" +#else +# include "kexec_64.h" +#endif diff --git a/include/asm-i386/kexec.h b/include/asm-x86/kexec_32.h index 4b9dc9e6b701..4b9dc9e6b701 100644 --- a/include/asm-i386/kexec.h +++ b/include/asm-x86/kexec_32.h diff --git a/include/asm-x86_64/kexec.h b/include/asm-x86/kexec_64.h index 738e581b67f8..738e581b67f8 100644 --- a/include/asm-x86_64/kexec.h +++ b/include/asm-x86/kexec_64.h diff --git a/include/asm-x86/kmap_types.h b/include/asm-x86/kmap_types.h new file mode 100644 index 000000000000..e4ec724b298e --- /dev/null +++ b/include/asm-x86/kmap_types.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "kmap_types_32.h" +#else +# include "kmap_types_64.h" +#endif diff --git a/include/asm-i386/kmap_types.h b/include/asm-x86/kmap_types_32.h index 806aae3c5338..806aae3c5338 100644 --- a/include/asm-i386/kmap_types.h +++ b/include/asm-x86/kmap_types_32.h diff --git a/include/asm-x86_64/kmap_types.h b/include/asm-x86/kmap_types_64.h index 7486338c6cea..7486338c6cea 100644 --- a/include/asm-x86_64/kmap_types.h +++ b/include/asm-x86/kmap_types_64.h diff --git a/include/asm-x86/kprobes.h b/include/asm-x86/kprobes.h new file mode 100644 index 000000000000..b7bbd25ba2a6 --- /dev/null +++ b/include/asm-x86/kprobes.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "kprobes_32.h" +#else +# include "kprobes_64.h" +#endif diff --git a/include/asm-i386/kprobes.h b/include/asm-x86/kprobes_32.h index 8774d06689da..06f7303c30ca 100644 --- a/include/asm-i386/kprobes.h +++ b/include/asm-x86/kprobes_32.h @@ -42,7 +42,6 @@ typedef u8 kprobe_opcode_t; ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry #define ARCH_SUPPORTS_KRETPROBES #define ARCH_INACTIVE_KPROBE_COUNT 0 #define flush_insn_slot(p) do { } while (0) diff --git a/include/asm-x86_64/kprobes.h b/include/asm-x86/kprobes_64.h index cf5317898fb0..7db825403e01 100644 --- a/include/asm-x86_64/kprobes.h +++ b/include/asm-x86/kprobes_64.h @@ -41,7 +41,6 @@ typedef u8 kprobe_opcode_t; ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) -#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)pentry #define ARCH_SUPPORTS_KRETPROBES #define ARCH_INACTIVE_KPROBE_COUNT 1 diff --git a/include/asm-x86/ldt.h b/include/asm-x86/ldt.h new file mode 100644 index 000000000000..3d9cc20d2ba4 --- /dev/null +++ b/include/asm-x86/ldt.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ldt_32.h" +# else +# include "ldt_64.h" +# endif +#else +# ifdef __i386__ +# include "ldt_32.h" +# else +# include "ldt_64.h" +# endif +#endif diff --git a/include/asm-i386/ldt.h b/include/asm-x86/ldt_32.h index e9d3de1dee6c..e9d3de1dee6c 100644 --- a/include/asm-i386/ldt.h +++ b/include/asm-x86/ldt_32.h diff --git a/include/asm-x86_64/ldt.h b/include/asm-x86/ldt_64.h index 9ef647b890d2..9ef647b890d2 100644 --- a/include/asm-x86_64/ldt.h +++ b/include/asm-x86/ldt_64.h diff --git a/include/asm-x86/linkage.h b/include/asm-x86/linkage.h new file mode 100644 index 000000000000..94b257fa8701 --- /dev/null +++ b/include/asm-x86/linkage.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "linkage_32.h" +#else +# include "linkage_64.h" +#endif diff --git a/include/asm-i386/linkage.h b/include/asm-x86/linkage_32.h index f4a6ebac0247..f4a6ebac0247 100644 --- a/include/asm-i386/linkage.h +++ b/include/asm-x86/linkage_32.h diff --git a/include/asm-x86_64/linkage.h b/include/asm-x86/linkage_64.h index b5f39d0189ce..b5f39d0189ce 100644 --- a/include/asm-x86_64/linkage.h +++ b/include/asm-x86/linkage_64.h diff --git a/include/asm-x86/local.h b/include/asm-x86/local.h new file mode 100644 index 000000000000..c7a1b1c66c96 --- /dev/null +++ b/include/asm-x86/local.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "local_32.h" +#else +# include "local_64.h" +#endif diff --git a/include/asm-i386/local.h b/include/asm-x86/local_32.h index 6e85975b9ed2..6e85975b9ed2 100644 --- a/include/asm-i386/local.h +++ b/include/asm-x86/local_32.h diff --git a/include/asm-x86_64/local.h b/include/asm-x86/local_64.h index e87492bb0693..e87492bb0693 100644 --- a/include/asm-x86_64/local.h +++ b/include/asm-x86/local_64.h diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-x86/mach-bigsmp/mach_apic.h index ebd319f838ab..ebd319f838ab 100644 --- a/include/asm-i386/mach-bigsmp/mach_apic.h +++ b/include/asm-x86/mach-bigsmp/mach_apic.h diff --git a/include/asm-i386/mach-bigsmp/mach_apicdef.h b/include/asm-x86/mach-bigsmp/mach_apicdef.h index a58ab5a75c8c..a58ab5a75c8c 100644 --- a/include/asm-i386/mach-bigsmp/mach_apicdef.h +++ b/include/asm-x86/mach-bigsmp/mach_apicdef.h diff --git a/include/asm-i386/mach-bigsmp/mach_ipi.h b/include/asm-x86/mach-bigsmp/mach_ipi.h index 9404c535b7ec..9404c535b7ec 100644 --- a/include/asm-i386/mach-bigsmp/mach_ipi.h +++ b/include/asm-x86/mach-bigsmp/mach_ipi.h diff --git a/include/asm-i386/mach-bigsmp/mach_mpspec.h b/include/asm-x86/mach-bigsmp/mach_mpspec.h index 6b5dadcf1d0e..6b5dadcf1d0e 100644 --- a/include/asm-i386/mach-bigsmp/mach_mpspec.h +++ b/include/asm-x86/mach-bigsmp/mach_mpspec.h diff --git a/include/asm-i386/mach-default/apm.h b/include/asm-x86/mach-default/apm.h index 1f730b8bd1fd..1f730b8bd1fd 100644 --- a/include/asm-i386/mach-default/apm.h +++ b/include/asm-x86/mach-default/apm.h diff --git a/include/asm-i386/mach-default/bios_ebda.h b/include/asm-x86/mach-default/bios_ebda.h index 9cbd9a668af8..9cbd9a668af8 100644 --- a/include/asm-i386/mach-default/bios_ebda.h +++ b/include/asm-x86/mach-default/bios_ebda.h diff --git a/include/asm-i386/mach-default/do_timer.h b/include/asm-x86/mach-default/do_timer.h index 56e5689863ae..23ecda0b28a0 100644 --- a/include/asm-i386/mach-default/do_timer.h +++ b/include/asm-x86/mach-default/do_timer.h @@ -12,5 +12,5 @@ static inline void do_timer_interrupt_hook(void) { - pit_interrupt_hook(); + global_clock_event->event_handler(global_clock_event); } diff --git a/include/asm-i386/mach-default/entry_arch.h b/include/asm-x86/mach-default/entry_arch.h index bc861469bdba..bc861469bdba 100644 --- a/include/asm-i386/mach-default/entry_arch.h +++ b/include/asm-x86/mach-default/entry_arch.h diff --git a/include/asm-i386/mach-default/io_ports.h b/include/asm-x86/mach-default/io_ports.h index a96d9f6604ee..48540ba97166 100644 --- a/include/asm-i386/mach-default/io_ports.h +++ b/include/asm-x86/mach-default/io_ports.h @@ -7,11 +7,6 @@ #ifndef _MACH_IO_PORTS_H #define _MACH_IO_PORTS_H -/* i8253A PIT registers */ -#define PIT_MODE 0x43 -#define PIT_CH0 0x40 -#define PIT_CH2 0x42 - /* i8259A PIC registers */ #define PIC_MASTER_CMD 0x20 #define PIC_MASTER_IMR 0x21 diff --git a/include/asm-i386/mach-default/irq_vectors.h b/include/asm-x86/mach-default/irq_vectors.h index 881c63ca61ad..881c63ca61ad 100644 --- a/include/asm-i386/mach-default/irq_vectors.h +++ b/include/asm-x86/mach-default/irq_vectors.h diff --git a/include/asm-i386/mach-default/irq_vectors_limits.h b/include/asm-x86/mach-default/irq_vectors_limits.h index 7f161e760be6..a90c7a60109f 100644 --- a/include/asm-i386/mach-default/irq_vectors_limits.h +++ b/include/asm-x86/mach-default/irq_vectors_limits.h @@ -1,7 +1,7 @@ #ifndef _ASM_IRQ_VECTORS_LIMITS_H #define _ASM_IRQ_VECTORS_LIMITS_H -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) #define NR_IRQS 224 # if (224 >= 32 * NR_CPUS) # define NR_IRQ_VECTORS NR_IRQS diff --git a/include/asm-i386/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h index 6db1c3babe9a..6db1c3babe9a 100644 --- a/include/asm-i386/mach-default/mach_apic.h +++ b/include/asm-x86/mach-default/mach_apic.h diff --git a/include/asm-i386/mach-default/mach_apicdef.h b/include/asm-x86/mach-default/mach_apicdef.h index 7bcb350c3ee8..7bcb350c3ee8 100644 --- a/include/asm-i386/mach-default/mach_apicdef.h +++ b/include/asm-x86/mach-default/mach_apicdef.h diff --git a/include/asm-i386/mach-default/mach_ipi.h b/include/asm-x86/mach-default/mach_ipi.h index 0dba244c86db..0dba244c86db 100644 --- a/include/asm-i386/mach-default/mach_ipi.h +++ b/include/asm-x86/mach-default/mach_ipi.h diff --git a/include/asm-i386/mach-default/mach_mpparse.h b/include/asm-x86/mach-default/mach_mpparse.h index 1d3832482580..1d3832482580 100644 --- a/include/asm-i386/mach-default/mach_mpparse.h +++ b/include/asm-x86/mach-default/mach_mpparse.h diff --git a/include/asm-i386/mach-default/mach_mpspec.h b/include/asm-x86/mach-default/mach_mpspec.h index 51c9a9775932..51c9a9775932 100644 --- a/include/asm-i386/mach-default/mach_mpspec.h +++ b/include/asm-x86/mach-default/mach_mpspec.h diff --git a/include/asm-i386/mach-default/mach_reboot.h b/include/asm-x86/mach-default/mach_reboot.h index a955e57ad016..e23fd9fbebb3 100644 --- a/include/asm-i386/mach-default/mach_reboot.h +++ b/include/asm-x86/mach-default/mach_reboot.h @@ -19,14 +19,37 @@ static inline void kb_wait(void) static inline void mach_reboot(void) { int i; + + /* old method, works on most machines */ for (i = 0; i < 10; i++) { kb_wait(); udelay(50); + outb(0xfe, 0x64); /* pulse reset low */ + udelay(50); + } + + /* New method: sets the "System flag" which, when set, indicates + * successful completion of the keyboard controller self-test (Basic + * Assurance Test, BAT). This is needed for some machines with no + * keyboard plugged in. This read-modify-write sequence sets only the + * system flag + */ + for (i = 0; i < 10; i++) { + int cmd; + + outb(0x20, 0x64); /* read Controller Command Byte */ + udelay(50); + kb_wait(); + udelay(50); + cmd = inb(0x60); + udelay(50); + kb_wait(); + udelay(50); outb(0x60, 0x64); /* write Controller Command Byte */ udelay(50); kb_wait(); udelay(50); - outb(0x14, 0x60); /* set "System flag" */ + outb(cmd | 0x04, 0x60); /* set "System flag" */ udelay(50); kb_wait(); udelay(50); diff --git a/include/asm-i386/mach-default/mach_time.h b/include/asm-x86/mach-default/mach_time.h index 31eb5de6f3dc..31eb5de6f3dc 100644 --- a/include/asm-i386/mach-default/mach_time.h +++ b/include/asm-x86/mach-default/mach_time.h diff --git a/include/asm-i386/mach-default/mach_timer.h b/include/asm-x86/mach-default/mach_timer.h index 807992fd4171..807992fd4171 100644 --- a/include/asm-i386/mach-default/mach_timer.h +++ b/include/asm-x86/mach-default/mach_timer.h diff --git a/include/asm-i386/mach-default/mach_traps.h b/include/asm-x86/mach-default/mach_traps.h index 625438b8a6eb..625438b8a6eb 100644 --- a/include/asm-i386/mach-default/mach_traps.h +++ b/include/asm-x86/mach-default/mach_traps.h diff --git a/include/asm-i386/mach-default/mach_wakecpu.h b/include/asm-x86/mach-default/mach_wakecpu.h index 673b85c9b273..3ebb17893aa5 100644 --- a/include/asm-i386/mach-default/mach_wakecpu.h +++ b/include/asm-x86/mach-default/mach_wakecpu.h @@ -15,7 +15,8 @@ static inline void wait_for_init_deassert(atomic_t *deassert) { - while (!atomic_read(deassert)); + while (!atomic_read(deassert)) + cpu_relax(); return; } diff --git a/include/asm-i386/mach-default/pci-functions.h b/include/asm-x86/mach-default/pci-functions.h index ed0bab427354..ed0bab427354 100644 --- a/include/asm-i386/mach-default/pci-functions.h +++ b/include/asm-x86/mach-default/pci-functions.h diff --git a/include/asm-i386/mach-default/setup_arch.h b/include/asm-x86/mach-default/setup_arch.h index 605e3ccb991b..605e3ccb991b 100644 --- a/include/asm-i386/mach-default/setup_arch.h +++ b/include/asm-x86/mach-default/setup_arch.h diff --git a/include/asm-i386/mach-default/smpboot_hooks.h b/include/asm-x86/mach-default/smpboot_hooks.h index 7f45f6311059..7f45f6311059 100644 --- a/include/asm-i386/mach-default/smpboot_hooks.h +++ b/include/asm-x86/mach-default/smpboot_hooks.h diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-x86/mach-es7000/mach_apic.h index caec64be516d..caec64be516d 100644 --- a/include/asm-i386/mach-es7000/mach_apic.h +++ b/include/asm-x86/mach-es7000/mach_apic.h diff --git a/include/asm-i386/mach-es7000/mach_apicdef.h b/include/asm-x86/mach-es7000/mach_apicdef.h index a58ab5a75c8c..a58ab5a75c8c 100644 --- a/include/asm-i386/mach-es7000/mach_apicdef.h +++ b/include/asm-x86/mach-es7000/mach_apicdef.h diff --git a/include/asm-i386/mach-es7000/mach_ipi.h b/include/asm-x86/mach-es7000/mach_ipi.h index 5e61bd220b06..5e61bd220b06 100644 --- a/include/asm-i386/mach-es7000/mach_ipi.h +++ b/include/asm-x86/mach-es7000/mach_ipi.h diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-x86/mach-es7000/mach_mpparse.h index 8aa10547b4b1..8aa10547b4b1 100644 --- a/include/asm-i386/mach-es7000/mach_mpparse.h +++ b/include/asm-x86/mach-es7000/mach_mpparse.h diff --git a/include/asm-i386/mach-es7000/mach_mpspec.h b/include/asm-x86/mach-es7000/mach_mpspec.h index b1f5039d4506..b1f5039d4506 100644 --- a/include/asm-i386/mach-es7000/mach_mpspec.h +++ b/include/asm-x86/mach-es7000/mach_mpspec.h diff --git a/include/asm-i386/mach-es7000/mach_wakecpu.h b/include/asm-x86/mach-es7000/mach_wakecpu.h index efc903b73486..84ff58314501 100644 --- a/include/asm-i386/mach-es7000/mach_wakecpu.h +++ b/include/asm-x86/mach-es7000/mach_wakecpu.h @@ -31,7 +31,8 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) static inline void wait_for_init_deassert(atomic_t *deassert) { #ifdef WAKE_SECONDARY_VIA_INIT - while (!atomic_read(deassert)); + while (!atomic_read(deassert)) + cpu_relax(); #endif return; } diff --git a/include/asm-i386/mach-generic/irq_vectors_limits.h b/include/asm-x86/mach-generic/irq_vectors_limits.h index 890ce3f5e09a..890ce3f5e09a 100644 --- a/include/asm-i386/mach-generic/irq_vectors_limits.h +++ b/include/asm-x86/mach-generic/irq_vectors_limits.h diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-x86/mach-generic/mach_apic.h index a236e7021528..a236e7021528 100644 --- a/include/asm-i386/mach-generic/mach_apic.h +++ b/include/asm-x86/mach-generic/mach_apic.h diff --git a/include/asm-i386/mach-generic/mach_apicdef.h b/include/asm-x86/mach-generic/mach_apicdef.h index 28ed98972ca8..28ed98972ca8 100644 --- a/include/asm-i386/mach-generic/mach_apicdef.h +++ b/include/asm-x86/mach-generic/mach_apicdef.h diff --git a/include/asm-i386/mach-generic/mach_ipi.h b/include/asm-x86/mach-generic/mach_ipi.h index 441b0fe3ed1d..441b0fe3ed1d 100644 --- a/include/asm-i386/mach-generic/mach_ipi.h +++ b/include/asm-x86/mach-generic/mach_ipi.h diff --git a/include/asm-i386/mach-generic/mach_mpparse.h b/include/asm-x86/mach-generic/mach_mpparse.h index dbd9fce54f4d..dbd9fce54f4d 100644 --- a/include/asm-i386/mach-generic/mach_mpparse.h +++ b/include/asm-x86/mach-generic/mach_mpparse.h diff --git a/include/asm-i386/mach-generic/mach_mpspec.h b/include/asm-x86/mach-generic/mach_mpspec.h index 9ef0b941bb22..9ef0b941bb22 100644 --- a/include/asm-i386/mach-generic/mach_mpspec.h +++ b/include/asm-x86/mach-generic/mach_mpspec.h diff --git a/include/asm-i386/mach-numaq/mach_apic.h b/include/asm-x86/mach-numaq/mach_apic.h index 5e5e7dd2692e..5e5e7dd2692e 100644 --- a/include/asm-i386/mach-numaq/mach_apic.h +++ b/include/asm-x86/mach-numaq/mach_apic.h diff --git a/include/asm-i386/mach-numaq/mach_apicdef.h b/include/asm-x86/mach-numaq/mach_apicdef.h index bf439d0690f5..bf439d0690f5 100644 --- a/include/asm-i386/mach-numaq/mach_apicdef.h +++ b/include/asm-x86/mach-numaq/mach_apicdef.h diff --git a/include/asm-i386/mach-numaq/mach_ipi.h b/include/asm-x86/mach-numaq/mach_ipi.h index c6044488e9e6..c6044488e9e6 100644 --- a/include/asm-i386/mach-numaq/mach_ipi.h +++ b/include/asm-x86/mach-numaq/mach_ipi.h diff --git a/include/asm-i386/mach-numaq/mach_mpparse.h b/include/asm-x86/mach-numaq/mach_mpparse.h index 51bbac8fc0c2..51bbac8fc0c2 100644 --- a/include/asm-i386/mach-numaq/mach_mpparse.h +++ b/include/asm-x86/mach-numaq/mach_mpparse.h diff --git a/include/asm-i386/mach-numaq/mach_mpspec.h b/include/asm-x86/mach-numaq/mach_mpspec.h index dffb09856f8f..dffb09856f8f 100644 --- a/include/asm-i386/mach-numaq/mach_mpspec.h +++ b/include/asm-x86/mach-numaq/mach_mpspec.h diff --git a/include/asm-i386/mach-numaq/mach_wakecpu.h b/include/asm-x86/mach-numaq/mach_wakecpu.h index 00530041a991..00530041a991 100644 --- a/include/asm-i386/mach-numaq/mach_wakecpu.h +++ b/include/asm-x86/mach-numaq/mach_wakecpu.h diff --git a/include/asm-i386/mach-summit/irq_vectors_limits.h b/include/asm-x86/mach-summit/irq_vectors_limits.h index 890ce3f5e09a..890ce3f5e09a 100644 --- a/include/asm-i386/mach-summit/irq_vectors_limits.h +++ b/include/asm-x86/mach-summit/irq_vectors_limits.h diff --git a/include/asm-i386/mach-summit/mach_apic.h b/include/asm-x86/mach-summit/mach_apic.h index 732f776aab8e..732f776aab8e 100644 --- a/include/asm-i386/mach-summit/mach_apic.h +++ b/include/asm-x86/mach-summit/mach_apic.h diff --git a/include/asm-i386/mach-summit/mach_apicdef.h b/include/asm-x86/mach-summit/mach_apicdef.h index a58ab5a75c8c..a58ab5a75c8c 100644 --- a/include/asm-i386/mach-summit/mach_apicdef.h +++ b/include/asm-x86/mach-summit/mach_apicdef.h diff --git a/include/asm-i386/mach-summit/mach_ipi.h b/include/asm-x86/mach-summit/mach_ipi.h index 9404c535b7ec..9404c535b7ec 100644 --- a/include/asm-i386/mach-summit/mach_ipi.h +++ b/include/asm-x86/mach-summit/mach_ipi.h diff --git a/include/asm-i386/mach-summit/mach_mpparse.h b/include/asm-x86/mach-summit/mach_mpparse.h index c2520539d934..c2520539d934 100644 --- a/include/asm-i386/mach-summit/mach_mpparse.h +++ b/include/asm-x86/mach-summit/mach_mpparse.h diff --git a/include/asm-i386/mach-summit/mach_mpspec.h b/include/asm-x86/mach-summit/mach_mpspec.h index bd765523511a..bd765523511a 100644 --- a/include/asm-i386/mach-summit/mach_mpspec.h +++ b/include/asm-x86/mach-summit/mach_mpspec.h diff --git a/include/asm-i386/mach-visws/cobalt.h b/include/asm-x86/mach-visws/cobalt.h index 33c36225a042..33c36225a042 100644 --- a/include/asm-i386/mach-visws/cobalt.h +++ b/include/asm-x86/mach-visws/cobalt.h diff --git a/include/asm-i386/mach-visws/entry_arch.h b/include/asm-x86/mach-visws/entry_arch.h index b183fa6d83d9..b183fa6d83d9 100644 --- a/include/asm-i386/mach-visws/entry_arch.h +++ b/include/asm-x86/mach-visws/entry_arch.h diff --git a/include/asm-i386/mach-visws/irq_vectors.h b/include/asm-x86/mach-visws/irq_vectors.h index cb572d8db505..cb572d8db505 100644 --- a/include/asm-i386/mach-visws/irq_vectors.h +++ b/include/asm-x86/mach-visws/irq_vectors.h diff --git a/include/asm-i386/mach-visws/lithium.h b/include/asm-x86/mach-visws/lithium.h index d443e68d0066..d443e68d0066 100644 --- a/include/asm-i386/mach-visws/lithium.h +++ b/include/asm-x86/mach-visws/lithium.h diff --git a/include/asm-i386/mach-visws/mach_apic.h b/include/asm-x86/mach-visws/mach_apic.h index efac6f0d139f..efac6f0d139f 100644 --- a/include/asm-i386/mach-visws/mach_apic.h +++ b/include/asm-x86/mach-visws/mach_apic.h diff --git a/include/asm-i386/mach-visws/mach_apicdef.h b/include/asm-x86/mach-visws/mach_apicdef.h index 826cfa97d778..826cfa97d778 100644 --- a/include/asm-i386/mach-visws/mach_apicdef.h +++ b/include/asm-x86/mach-visws/mach_apicdef.h diff --git a/include/asm-i386/mach-visws/piix4.h b/include/asm-x86/mach-visws/piix4.h index 83ea4f46e419..83ea4f46e419 100644 --- a/include/asm-i386/mach-visws/piix4.h +++ b/include/asm-x86/mach-visws/piix4.h diff --git a/include/asm-i386/mach-visws/setup_arch.h b/include/asm-x86/mach-visws/setup_arch.h index 33f700ef6831..33f700ef6831 100644 --- a/include/asm-i386/mach-visws/setup_arch.h +++ b/include/asm-x86/mach-visws/setup_arch.h diff --git a/include/asm-i386/mach-visws/smpboot_hooks.h b/include/asm-x86/mach-visws/smpboot_hooks.h index d926471fa359..d926471fa359 100644 --- a/include/asm-i386/mach-visws/smpboot_hooks.h +++ b/include/asm-x86/mach-visws/smpboot_hooks.h diff --git a/include/asm-i386/mach-voyager/do_timer.h b/include/asm-x86/mach-voyager/do_timer.h index 60f9dcc15d54..bc2b58926308 100644 --- a/include/asm-i386/mach-voyager/do_timer.h +++ b/include/asm-x86/mach-voyager/do_timer.h @@ -12,7 +12,7 @@ **/ static inline void do_timer_interrupt_hook(void) { - pit_interrupt_hook(); + global_clock_event->event_handler(global_clock_event); voyager_timer_interrupt(); } diff --git a/include/asm-i386/mach-voyager/entry_arch.h b/include/asm-x86/mach-voyager/entry_arch.h index 4a1e1e8c10b6..4a1e1e8c10b6 100644 --- a/include/asm-i386/mach-voyager/entry_arch.h +++ b/include/asm-x86/mach-voyager/entry_arch.h diff --git a/include/asm-i386/mach-voyager/irq_vectors.h b/include/asm-x86/mach-voyager/irq_vectors.h index 165421f5821c..165421f5821c 100644 --- a/include/asm-i386/mach-voyager/irq_vectors.h +++ b/include/asm-x86/mach-voyager/irq_vectors.h diff --git a/include/asm-i386/mach-voyager/setup_arch.h b/include/asm-x86/mach-voyager/setup_arch.h index 84d01ad33459..84d01ad33459 100644 --- a/include/asm-i386/mach-voyager/setup_arch.h +++ b/include/asm-x86/mach-voyager/setup_arch.h diff --git a/include/asm-x86_64/mach_apic.h b/include/asm-x86/mach_apic.h index 7b7115a0c1c9..7b7115a0c1c9 100644 --- a/include/asm-x86_64/mach_apic.h +++ b/include/asm-x86/mach_apic.h diff --git a/include/asm-i386/math_emu.h b/include/asm-x86/math_emu.h index a4b0aa3320e6..a4b0aa3320e6 100644 --- a/include/asm-i386/math_emu.h +++ b/include/asm-x86/math_emu.h diff --git a/include/asm-x86/mc146818rtc.h b/include/asm-x86/mc146818rtc.h new file mode 100644 index 000000000000..5c2bb66caf17 --- /dev/null +++ b/include/asm-x86/mc146818rtc.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mc146818rtc_32.h" +#else +# include "mc146818rtc_64.h" +#endif diff --git a/include/asm-i386/mc146818rtc.h b/include/asm-x86/mc146818rtc_32.h index 99a890047023..1613b42eaf58 100644 --- a/include/asm-i386/mc146818rtc.h +++ b/include/asm-x86/mc146818rtc_32.h @@ -6,6 +6,7 @@ #include <asm/io.h> #include <asm/system.h> +#include <asm/processor.h> #include <linux/mc146818rtc.h> #ifndef RTC_PORT @@ -43,8 +44,10 @@ static inline void lock_cmos(unsigned char reg) unsigned long new; new = ((smp_processor_id()+1) << 8) | reg; for (;;) { - if (cmos_lock) + if (cmos_lock) { + cpu_relax(); continue; + } if (__cmpxchg(&cmos_lock, 0, new, sizeof(cmos_lock)) == 0) return; } diff --git a/include/asm-x86_64/mc146818rtc.h b/include/asm-x86/mc146818rtc_64.h index d6e3009430c1..d6e3009430c1 100644 --- a/include/asm-x86_64/mc146818rtc.h +++ b/include/asm-x86/mc146818rtc_64.h diff --git a/include/asm-i386/mca.h b/include/asm-x86/mca.h index 09adf2eac4dc..09adf2eac4dc 100644 --- a/include/asm-i386/mca.h +++ b/include/asm-x86/mca.h diff --git a/include/asm-i386/mca_dma.h b/include/asm-x86/mca_dma.h index fbb1f3b71279..fbb1f3b71279 100644 --- a/include/asm-i386/mca_dma.h +++ b/include/asm-x86/mca_dma.h diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h new file mode 100644 index 000000000000..cc8ca389912e --- /dev/null +++ b/include/asm-x86/mce.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mce_32.h" +#else +# include "mce_64.h" +#endif diff --git a/include/asm-i386/mce.h b/include/asm-x86/mce_32.h index b0a02ee34ffd..d56d89742e8f 100644 --- a/include/asm-i386/mce.h +++ b/include/asm-x86/mce_32.h @@ -5,3 +5,7 @@ extern void mcheck_init(struct cpuinfo_x86 *c); #endif extern int mce_disabled; + +extern void stop_mce(void); +extern void restart_mce(void); + diff --git a/include/asm-x86_64/mce.h b/include/asm-x86/mce_64.h index 177e92b4019b..7bc030a1996d 100644 --- a/include/asm-x86_64/mce.h +++ b/include/asm-x86/mce_64.h @@ -105,6 +105,11 @@ extern atomic_t mce_entry; extern void do_machine_check(struct pt_regs *, long); +extern int mce_notify_user(void); + +extern void stop_mce(void); +extern void restart_mce(void); + #endif #endif diff --git a/include/asm-x86/mman.h b/include/asm-x86/mman.h new file mode 100644 index 000000000000..322db07e82c3 --- /dev/null +++ b/include/asm-x86/mman.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "mman_32.h" +# else +# include "mman_64.h" +# endif +#else +# ifdef __i386__ +# include "mman_32.h" +# else +# include "mman_64.h" +# endif +#endif diff --git a/include/asm-i386/mman.h b/include/asm-x86/mman_32.h index 8fd9d7ab7faf..8fd9d7ab7faf 100644 --- a/include/asm-i386/mman.h +++ b/include/asm-x86/mman_32.h diff --git a/include/asm-x86_64/mman.h b/include/asm-x86/mman_64.h index dd5cb0534d37..dd5cb0534d37 100644 --- a/include/asm-x86_64/mman.h +++ b/include/asm-x86/mman_64.h diff --git a/include/asm-x86_64/mmsegment.h b/include/asm-x86/mmsegment.h index d3f80c996330..d3f80c996330 100644 --- a/include/asm-x86_64/mmsegment.h +++ b/include/asm-x86/mmsegment.h diff --git a/include/asm-x86/mmu.h b/include/asm-x86/mmu.h new file mode 100644 index 000000000000..9c628cd70e23 --- /dev/null +++ b/include/asm-x86/mmu.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mmu_32.h" +#else +# include "mmu_64.h" +#endif diff --git a/include/asm-i386/mmu.h b/include/asm-x86/mmu_32.h index 8358dd3df7aa..8358dd3df7aa 100644 --- a/include/asm-i386/mmu.h +++ b/include/asm-x86/mmu_32.h diff --git a/include/asm-x86_64/mmu.h b/include/asm-x86/mmu_64.h index 5dc6ed79859a..d2cd4a9d984d 100644 --- a/include/asm-x86_64/mmu.h +++ b/include/asm-x86/mmu_64.h @@ -15,6 +15,7 @@ typedef struct { rwlock_t ldtlock; int size; struct semaphore sem; + void *vdso; } mm_context_t; #endif diff --git a/include/asm-x86/mmu_context.h b/include/asm-x86/mmu_context.h new file mode 100644 index 000000000000..6598450da6c6 --- /dev/null +++ b/include/asm-x86/mmu_context.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mmu_context_32.h" +#else +# include "mmu_context_64.h" +#endif diff --git a/include/asm-i386/mmu_context.h b/include/asm-x86/mmu_context_32.h index 8198d1cca1f3..7eb0b0b1fb3c 100644 --- a/include/asm-i386/mmu_context.h +++ b/include/asm-x86/mmu_context_32.h @@ -32,6 +32,8 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) #endif } +void leave_mm(unsigned long cpu); + static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) diff --git a/include/asm-x86_64/mmu_context.h b/include/asm-x86/mmu_context_64.h index 0cce83a78378..0cce83a78378 100644 --- a/include/asm-x86_64/mmu_context.h +++ b/include/asm-x86/mmu_context_64.h diff --git a/include/asm-i386/mmx.h b/include/asm-x86/mmx.h index 46b71da99869..46b71da99869 100644 --- a/include/asm-i386/mmx.h +++ b/include/asm-x86/mmx.h diff --git a/include/asm-x86/mmzone.h b/include/asm-x86/mmzone.h new file mode 100644 index 000000000000..64217ea16a36 --- /dev/null +++ b/include/asm-x86/mmzone.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mmzone_32.h" +#else +# include "mmzone_64.h" +#endif diff --git a/include/asm-i386/mmzone.h b/include/asm-x86/mmzone_32.h index 118e9812778f..118e9812778f 100644 --- a/include/asm-i386/mmzone.h +++ b/include/asm-x86/mmzone_32.h diff --git a/include/asm-x86_64/mmzone.h b/include/asm-x86/mmzone_64.h index 19a89377b123..19a89377b123 100644 --- a/include/asm-x86_64/mmzone.h +++ b/include/asm-x86/mmzone_64.h diff --git a/include/asm-x86/module.h b/include/asm-x86/module.h new file mode 100644 index 000000000000..2b2f18d8a531 --- /dev/null +++ b/include/asm-x86/module.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "module_32.h" +#else +# include "module_64.h" +#endif diff --git a/include/asm-i386/module.h b/include/asm-x86/module_32.h index 7e5fda6c3976..7e5fda6c3976 100644 --- a/include/asm-i386/module.h +++ b/include/asm-x86/module_32.h diff --git a/include/asm-x86_64/module.h b/include/asm-x86/module_64.h index 67f8f69fa7b1..67f8f69fa7b1 100644 --- a/include/asm-x86_64/module.h +++ b/include/asm-x86/module_64.h diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h new file mode 100644 index 000000000000..8f268e8fd2e9 --- /dev/null +++ b/include/asm-x86/mpspec.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mpspec_32.h" +#else +# include "mpspec_64.h" +#endif diff --git a/include/asm-i386/mpspec.h b/include/asm-x86/mpspec_32.h index f21349399d14..f21349399d14 100644 --- a/include/asm-i386/mpspec.h +++ b/include/asm-x86/mpspec_32.h diff --git a/include/asm-x86_64/mpspec.h b/include/asm-x86/mpspec_64.h index 017fddb61dc5..017fddb61dc5 100644 --- a/include/asm-x86_64/mpspec.h +++ b/include/asm-x86/mpspec_64.h diff --git a/include/asm-i386/mpspec_def.h b/include/asm-x86/mpspec_def.h index 13bafb16e7af..13bafb16e7af 100644 --- a/include/asm-i386/mpspec_def.h +++ b/include/asm-x86/mpspec_def.h diff --git a/include/asm-x86/msgbuf.h b/include/asm-x86/msgbuf.h new file mode 100644 index 000000000000..154f7d64e862 --- /dev/null +++ b/include/asm-x86/msgbuf.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "msgbuf_32.h" +# else +# include "msgbuf_64.h" +# endif +#else +# ifdef __i386__ +# include "msgbuf_32.h" +# else +# include "msgbuf_64.h" +# endif +#endif diff --git a/include/asm-i386/msgbuf.h b/include/asm-x86/msgbuf_32.h index b8d659c157ae..b8d659c157ae 100644 --- a/include/asm-i386/msgbuf.h +++ b/include/asm-x86/msgbuf_32.h diff --git a/include/asm-x86_64/msgbuf.h b/include/asm-x86/msgbuf_64.h index cd6f95dd54da..cd6f95dd54da 100644 --- a/include/asm-x86_64/msgbuf.h +++ b/include/asm-x86/msgbuf_64.h diff --git a/include/asm-i386/msidef.h b/include/asm-x86/msidef.h index 5b8acddb70fb..5b8acddb70fb 100644 --- a/include/asm-i386/msidef.h +++ b/include/asm-x86/msidef.h diff --git a/include/asm-i386/msr-index.h b/include/asm-x86/msr-index.h index a02eb2991349..a02eb2991349 100644 --- a/include/asm-i386/msr-index.h +++ b/include/asm-x86/msr-index.h diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h new file mode 100644 index 000000000000..2f87ce007002 --- /dev/null +++ b/include/asm-x86/msr.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "msr_32.h" +# else +# include "msr_64.h" +# endif +#else +# ifdef __i386__ +# include "msr_32.h" +# else +# include "msr_64.h" +# endif +#endif diff --git a/include/asm-i386/msr.h b/include/asm-x86/msr_32.h index df21ea049369..df21ea049369 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-x86/msr_32.h diff --git a/include/asm-x86_64/msr.h b/include/asm-x86/msr_64.h index d5c55b80da54..d5c55b80da54 100644 --- a/include/asm-x86_64/msr.h +++ b/include/asm-x86/msr_64.h diff --git a/include/asm-x86/mtrr.h b/include/asm-x86/mtrr.h new file mode 100644 index 000000000000..34f633b3e00c --- /dev/null +++ b/include/asm-x86/mtrr.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "mtrr_32.h" +# else +# include "mtrr_64.h" +# endif +#else +# ifdef __i386__ +# include "mtrr_32.h" +# else +# include "mtrr_64.h" +# endif +#endif diff --git a/include/asm-i386/mtrr.h b/include/asm-x86/mtrr_32.h index 7e9c7ccbdcfe..7e9c7ccbdcfe 100644 --- a/include/asm-i386/mtrr.h +++ b/include/asm-x86/mtrr_32.h diff --git a/include/asm-x86_64/mtrr.h b/include/asm-x86/mtrr_64.h index b557c486bef8..b557c486bef8 100644 --- a/include/asm-x86_64/mtrr.h +++ b/include/asm-x86/mtrr_64.h diff --git a/include/asm-x86/mutex.h b/include/asm-x86/mutex.h new file mode 100644 index 000000000000..a731b9c573a6 --- /dev/null +++ b/include/asm-x86/mutex.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "mutex_32.h" +#else +# include "mutex_64.h" +#endif diff --git a/include/asm-i386/mutex.h b/include/asm-x86/mutex_32.h index 7a17d9e58ad6..7a17d9e58ad6 100644 --- a/include/asm-i386/mutex.h +++ b/include/asm-x86/mutex_32.h diff --git a/include/asm-x86_64/mutex.h b/include/asm-x86/mutex_64.h index 6c2949a3c677..6c2949a3c677 100644 --- a/include/asm-x86_64/mutex.h +++ b/include/asm-x86/mutex_64.h diff --git a/include/asm-x86/namei.h b/include/asm-x86/namei.h new file mode 100644 index 000000000000..732f8f0b3dcd --- /dev/null +++ b/include/asm-x86/namei.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "namei_32.h" +#else +# include "namei_64.h" +#endif diff --git a/include/asm-i386/namei.h b/include/asm-x86/namei_32.h index 814865088617..814865088617 100644 --- a/include/asm-i386/namei.h +++ b/include/asm-x86/namei_32.h diff --git a/include/asm-x86_64/namei.h b/include/asm-x86/namei_64.h index bef239f5318f..bef239f5318f 100644 --- a/include/asm-x86_64/namei.h +++ b/include/asm-x86/namei_64.h diff --git a/include/asm-x86/nmi.h b/include/asm-x86/nmi.h new file mode 100644 index 000000000000..53ccac14cead --- /dev/null +++ b/include/asm-x86/nmi.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "nmi_32.h" +#else +# include "nmi_64.h" +#endif diff --git a/include/asm-i386/nmi.h b/include/asm-x86/nmi_32.h index fb1e133efd9f..70a958a8e381 100644 --- a/include/asm-i386/nmi.h +++ b/include/asm-x86/nmi_32.h @@ -33,11 +33,12 @@ extern int nmi_watchdog_tick (struct pt_regs * regs, unsigned reason); extern atomic_t nmi_active; extern unsigned int nmi_watchdog; -#define NMI_DEFAULT -1 +#define NMI_DISABLED -1 #define NMI_NONE 0 #define NMI_IO_APIC 1 #define NMI_LOCAL_APIC 2 #define NMI_INVALID 3 +#define NMI_DEFAULT NMI_DISABLED struct ctl_table; struct file; @@ -57,5 +58,7 @@ unsigned lapic_adjust_nmi_hz(unsigned hz); int lapic_watchdog_ok(void); void disable_lapic_nmi_watchdog(void); void enable_lapic_nmi_watchdog(void); +void stop_nmi(void); +void restart_nmi(void); #endif /* ASM_NMI_H */ diff --git a/include/asm-x86_64/nmi.h b/include/asm-x86/nmi_64.h index d0a7f53b1497..65b6acf3bb59 100644 --- a/include/asm-x86_64/nmi.h +++ b/include/asm-x86/nmi_64.h @@ -64,11 +64,12 @@ extern int setup_nmi_watchdog(char *); extern atomic_t nmi_active; extern unsigned int nmi_watchdog; -#define NMI_DEFAULT -1 +#define NMI_DISABLED -1 #define NMI_NONE 0 #define NMI_IO_APIC 1 #define NMI_LOCAL_APIC 2 #define NMI_INVALID 3 +#define NMI_DEFAULT NMI_DISABLED struct ctl_table; struct file; @@ -88,5 +89,7 @@ unsigned lapic_adjust_nmi_hz(unsigned hz); int lapic_watchdog_ok(void); void disable_lapic_nmi_watchdog(void); void enable_lapic_nmi_watchdog(void); +void stop_nmi(void); +void restart_nmi(void); #endif /* ASM_NMI_H */ diff --git a/include/asm-x86/numa.h b/include/asm-x86/numa.h new file mode 100644 index 000000000000..27da400d3138 --- /dev/null +++ b/include/asm-x86/numa.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "numa_32.h" +#else +# include "numa_64.h" +#endif diff --git a/include/asm-i386/numa.h b/include/asm-x86/numa_32.h index 96fcb157db1d..96fcb157db1d 100644 --- a/include/asm-i386/numa.h +++ b/include/asm-x86/numa_32.h diff --git a/include/asm-x86_64/numa.h b/include/asm-x86/numa_64.h index 933ff11ece15..933ff11ece15 100644 --- a/include/asm-x86_64/numa.h +++ b/include/asm-x86/numa_64.h diff --git a/include/asm-i386/numaq.h b/include/asm-x86/numaq.h index 38f710dc37f2..38f710dc37f2 100644 --- a/include/asm-i386/numaq.h +++ b/include/asm-x86/numaq.h diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h new file mode 100644 index 000000000000..a757eb26141d --- /dev/null +++ b/include/asm-x86/page.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "page_32.h" +# else +# include "page_64.h" +# endif +#else +# ifdef __i386__ +# include "page_32.h" +# else +# include "page_64.h" +# endif +#endif diff --git a/include/asm-i386/page.h b/include/asm-x86/page_32.h index 99cf5d3692a9..80ecc66b6d86 100644 --- a/include/asm-i386/page.h +++ b/include/asm-x86/page_32.h @@ -44,7 +44,6 @@ extern int nx_enabled; #ifdef CONFIG_X86_PAE -extern unsigned long long __supported_pte_mask; typedef struct { unsigned long pte_low, pte_high; } pte_t; typedef struct { unsigned long long pmd; } pmd_t; typedef struct { unsigned long long pgd; } pgd_t; diff --git a/include/asm-x86_64/page.h b/include/asm-x86/page_64.h index 88adf1afb0a2..88adf1afb0a2 100644 --- a/include/asm-x86_64/page.h +++ b/include/asm-x86/page_64.h diff --git a/include/asm-x86/param.h b/include/asm-x86/param.h new file mode 100644 index 000000000000..640851bab124 --- /dev/null +++ b/include/asm-x86/param.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "param_32.h" +# else +# include "param_64.h" +# endif +#else +# ifdef __i386__ +# include "param_32.h" +# else +# include "param_64.h" +# endif +#endif diff --git a/include/asm-i386/param.h b/include/asm-x86/param_32.h index 21b32466fcdc..21b32466fcdc 100644 --- a/include/asm-i386/param.h +++ b/include/asm-x86/param_32.h diff --git a/include/asm-x86_64/param.h b/include/asm-x86/param_64.h index a728786c3c7c..a728786c3c7c 100644 --- a/include/asm-x86_64/param.h +++ b/include/asm-x86/param_64.h diff --git a/include/asm-i386/paravirt.h b/include/asm-x86/paravirt.h index 7f846a7d6bcc..9fa3fa9e62d1 100644 --- a/include/asm-i386/paravirt.h +++ b/include/asm-x86/paravirt.h @@ -47,11 +47,14 @@ struct paravirt_ops * The patch function should return the number of bytes of code * generated, as we nop pad the rest in generic code. */ - unsigned (*patch)(u8 type, u16 clobber, void *firstinsn, unsigned len); + unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, + unsigned long addr, unsigned len); /* Basic arch-specific setup */ void (*arch_setup)(void); char *(*memory_setup)(void); + void (*post_allocator_init)(void); + void (*init_IRQ)(void); void (*time_init)(void); @@ -116,7 +119,7 @@ struct paravirt_ops u64 (*read_tsc)(void); u64 (*read_pmc)(void); - u64 (*get_scheduled_cycles)(void); + unsigned long long (*sched_clock)(void); unsigned long (*get_cpu_khz)(void); /* Segment descriptor handling */ @@ -173,7 +176,7 @@ struct paravirt_ops unsigned long va); /* Hooks for allocating/releasing pagetable pages */ - void (*alloc_pt)(u32 pfn); + void (*alloc_pt)(struct mm_struct *mm, u32 pfn); void (*alloc_pd)(u32 pfn); void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); void (*release_pt)(u32 pfn); @@ -251,15 +254,19 @@ extern struct paravirt_ops paravirt_ops; unsigned paravirt_patch_nop(void); unsigned paravirt_patch_ignore(unsigned len); -unsigned paravirt_patch_call(void *target, u16 tgt_clobbers, - void *site, u16 site_clobbers, +unsigned paravirt_patch_call(void *insnbuf, + const void *target, u16 tgt_clobbers, + unsigned long addr, u16 site_clobbers, unsigned len); -unsigned paravirt_patch_jmp(void *target, void *site, unsigned len); -unsigned paravirt_patch_default(u8 type, u16 clobbers, void *site, unsigned len); +unsigned paravirt_patch_jmp(const void *target, void *insnbuf, + unsigned long addr, unsigned len); +unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, + unsigned long addr, unsigned len); -unsigned paravirt_patch_insns(void *site, unsigned len, +unsigned paravirt_patch_insns(void *insnbuf, unsigned len, const char *start, const char *end); +int paravirt_disable_iospace(void); /* * This generates an indirect call based on the operation type number. @@ -563,7 +570,10 @@ static inline u64 paravirt_read_tsc(void) #define rdtscll(val) (val = paravirt_read_tsc()) -#define get_scheduled_cycles(val) (val = paravirt_ops.get_scheduled_cycles()) +static inline unsigned long long paravirt_sched_clock(void) +{ + return PVOP_CALL0(unsigned long long, sched_clock); +} #define calculate_cpu_khz() (paravirt_ops.get_cpu_khz()) #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) @@ -669,6 +679,12 @@ static inline void setup_secondary_clock(void) } #endif +static inline void paravirt_post_allocator_init(void) +{ + if (paravirt_ops.post_allocator_init) + (*paravirt_ops.post_allocator_init)(); +} + static inline void paravirt_pagetable_setup_start(pgd_t *base) { if (paravirt_ops.pagetable_setup_start) @@ -725,9 +741,9 @@ static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, PVOP_VCALL3(flush_tlb_others, &cpumask, mm, va); } -static inline void paravirt_alloc_pt(unsigned pfn) +static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn) { - PVOP_VCALL1(alloc_pt, pfn); + PVOP_VCALL2(alloc_pt, mm, pfn); } static inline void paravirt_release_pt(unsigned pfn) { diff --git a/include/asm-x86/parport.h b/include/asm-x86/parport.h new file mode 100644 index 000000000000..2a31157349c9 --- /dev/null +++ b/include/asm-x86/parport.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "parport_32.h" +#else +# include "parport_64.h" +#endif diff --git a/include/asm-i386/parport.h b/include/asm-x86/parport_32.h index fa0e321e498e..fa0e321e498e 100644 --- a/include/asm-i386/parport.h +++ b/include/asm-x86/parport_32.h diff --git a/include/asm-x86_64/parport.h b/include/asm-x86/parport_64.h index 7135ef977c96..7135ef977c96 100644 --- a/include/asm-x86_64/parport.h +++ b/include/asm-x86/parport_64.h diff --git a/include/asm-x86_64/pci-direct.h b/include/asm-x86/pci-direct.h index 6823fa4f1afa..6823fa4f1afa 100644 --- a/include/asm-x86_64/pci-direct.h +++ b/include/asm-x86/pci-direct.h diff --git a/include/asm-i386/pci.h b/include/asm-x86/pci.h index 392d3fe5d45e..e88361966347 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-x86/pci.h @@ -1,9 +1,38 @@ -#ifndef __i386_PCI_H -#define __i386_PCI_H +#ifndef __x86_PCI_H +#define __x86_PCI_H + +#include <linux/mm.h> /* for struct page */ +#include <linux/types.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <asm/scatterlist.h> +#include <asm/io.h> #ifdef __KERNEL__ -#include <linux/mm.h> /* for struct page */ + +struct pci_sysdata { + int domain; /* PCI domain */ + int node; /* NUMA node */ +#ifdef CONFIG_X86_64 + void* iommu; /* IOMMU private data */ +#endif +}; + +/* scan a bus after allocating a pci_sysdata for it */ +extern struct pci_bus *pci_scan_bus_with_sysdata(int busno); + +static inline int pci_domain_nr(struct pci_bus *bus) +{ + struct pci_sysdata *sd = bus->sysdata; + return sd->domain; +} + +static inline int pci_proc_domain(struct pci_bus *bus) +{ + return pci_domain_nr(bus); +} + /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes @@ -30,31 +59,6 @@ void pcibios_penalize_isa_irq(int irq, int active); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include <linux/types.h> -#include <linux/slab.h> -#include <asm/scatterlist.h> -#include <linux/string.h> -#include <asm/io.h> - -struct pci_dev; - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, @@ -71,7 +75,14 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -#endif /* __KERNEL__ */ + +#endif /* __KERNEL__ */ + +#ifdef CONFIG_X86_32 +# include "pci_32.h" +#else +# include "pci_64.h" +#endif /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include <asm-generic/pci-dma-compat.h> @@ -79,4 +90,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, /* generic pci stuff */ #include <asm-generic/pci.h> -#endif /* __i386_PCI_H */ + + +#endif diff --git a/include/asm-x86/pci_32.h b/include/asm-x86/pci_32.h new file mode 100644 index 000000000000..8c4c3a0368e2 --- /dev/null +++ b/include/asm-x86/pci_32.h @@ -0,0 +1,32 @@ +#ifndef __i386_PCI_H +#define __i386_PCI_H + + +#ifdef __KERNEL__ + + +/* Dynamic DMA mapping stuff. + * i386 has everything mapped statically. + */ + +struct pci_dev; + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + +/* pci_unmap_{page,single} is a nop so... */ +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) +#define pci_unmap_addr(PTR, ADDR_NAME) (0) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) +#define pci_unmap_len(PTR, LEN_NAME) (0) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) + + +#endif /* __KERNEL__ */ + + +#endif /* __i386_PCI_H */ diff --git a/include/asm-x86_64/pci.h b/include/asm-x86/pci_64.h index bda94fd5176f..9baa46d9f594 100644 --- a/include/asm-x86_64/pci.h +++ b/include/asm-x86/pci_64.h @@ -1,44 +1,29 @@ #ifndef __x8664_PCI_H #define __x8664_PCI_H -#include <asm/io.h> #ifdef __KERNEL__ -#include <linux/mm.h> /* for struct page */ -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#ifdef CONFIG_PCI -extern unsigned int pcibios_assign_all_busses(void); -#else -#define pcibios_assign_all_busses() 0 -#endif -#define pcibios_scan_all_fns(a, b) 0 +#ifdef CONFIG_CALGARY_IOMMU +static inline void* pci_iommu(struct pci_bus *bus) +{ + struct pci_sysdata *sd = bus->sysdata; + return sd->iommu; +} -extern unsigned long pci_mem_start; -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM (pci_mem_start) +static inline void set_pci_iommu(struct pci_bus *bus, void *val) +{ + struct pci_sysdata *sd = bus->sysdata; + sd->iommu = val; +} +#endif /* CONFIG_CALGARY_IOMMU */ -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 -void pcibios_config_init(void); -struct pci_bus * pcibios_scan_root(int bus); extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value); extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value); -void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq, int active); -struct irq_routing_table *pcibios_get_irq_routing_table(void); -int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); -#include <linux/types.h> -#include <linux/slab.h> -#include <asm/scatterlist.h> -#include <linux/string.h> -#include <asm/page.h> extern void pci_iommu_alloc(void); extern int iommu_setup(char *opt); @@ -79,27 +64,7 @@ extern int iommu_setup(char *opt); #endif -#include <asm-generic/pci-dma-compat.h> - -#ifdef CONFIG_PCI -static inline void pci_dma_burst_advice(struct pci_dev *pdev, - enum pci_dma_burst_strategy *strat, - unsigned long *strategy_parameter) -{ - *strat = PCI_DMA_BURST_INFINITY; - *strategy_parameter = ~0UL; -} -#endif - -#define HAVE_PCI_MMAP -extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - #endif /* __KERNEL__ */ -/* generic pci stuff */ -#ifdef CONFIG_PCI -#include <asm-generic/pci.h> -#endif #endif /* __x8664_PCI_H */ diff --git a/include/asm-x86_64/pda.h b/include/asm-x86/pda.h index 5642634843c4..fb49f80eb94f 100644 --- a/include/asm-x86_64/pda.h +++ b/include/asm-x86/pda.h @@ -29,6 +29,7 @@ struct x8664_pda { short isidle; struct mm_struct *active_mm; unsigned apic_timer_irqs; + unsigned irq0_irqs; } ____cacheline_aligned_in_smp; extern struct x8664_pda *_cpu_pda[]; diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h new file mode 100644 index 000000000000..a1aaad274cca --- /dev/null +++ b/include/asm-x86/percpu.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "percpu_32.h" +#else +# include "percpu_64.h" +#endif diff --git a/include/asm-i386/percpu.h b/include/asm-x86/percpu_32.h index f54830b5d5ac..a7ebd436f3cc 100644 --- a/include/asm-i386/percpu.h +++ b/include/asm-x86/percpu_32.h @@ -54,6 +54,11 @@ extern unsigned long __per_cpu_offset[]; #define DEFINE_PER_CPU(type, name) \ __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_aligned_in_smp + /* We can use this directly for local CPU (faster). */ DECLARE_PER_CPU(unsigned long, this_cpu_off); diff --git a/include/asm-x86_64/percpu.h b/include/asm-x86/percpu_64.h index c6fbb67eac90..5abd48270101 100644 --- a/include/asm-x86_64/percpu.h +++ b/include/asm-x86/percpu_64.h @@ -20,6 +20,11 @@ #define DEFINE_PER_CPU(type, name) \ __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.shared_aligned"))) \ + __typeof__(type) per_cpu__##name \ + ____cacheline_internodealigned_in_smp + /* var is in discarded region: offset to particular copy we want */ #define per_cpu(var, cpu) (*({ \ extern int simple_identifier_##var(void); \ @@ -46,6 +51,8 @@ extern void setup_per_cpu_areas(void); #define DEFINE_PER_CPU(type, name) \ __typeof__(type) per_cpu__##name +#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) #define per_cpu(var, cpu) (*((void)(cpu), &per_cpu__##var)) #define __get_cpu_var(var) per_cpu__##var diff --git a/include/asm-x86/pgalloc.h b/include/asm-x86/pgalloc.h new file mode 100644 index 000000000000..5886eed05886 --- /dev/null +++ b/include/asm-x86/pgalloc.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "pgalloc_32.h" +#else +# include "pgalloc_64.h" +#endif diff --git a/include/asm-i386/pgalloc.h b/include/asm-x86/pgalloc_32.h index d07b7afc2692..f2fc33ceb9f2 100644 --- a/include/asm-i386/pgalloc.h +++ b/include/asm-x86/pgalloc_32.h @@ -7,7 +7,7 @@ #ifdef CONFIG_PARAVIRT #include <asm/paravirt.h> #else -#define paravirt_alloc_pt(pfn) do { } while (0) +#define paravirt_alloc_pt(mm, pfn) do { } while (0) #define paravirt_alloc_pd(pfn) do { } while (0) #define paravirt_alloc_pd(pfn) do { } while (0) #define paravirt_alloc_pd_clone(pfn, clonepfn, start, count) do { } while (0) @@ -17,13 +17,13 @@ #define pmd_populate_kernel(mm, pmd, pte) \ do { \ - paravirt_alloc_pt(__pa(pte) >> PAGE_SHIFT); \ + paravirt_alloc_pt(mm, __pa(pte) >> PAGE_SHIFT); \ set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))); \ } while (0) #define pmd_populate(mm, pmd, pte) \ do { \ - paravirt_alloc_pt(page_to_pfn(pte)); \ + paravirt_alloc_pt(mm, page_to_pfn(pte)); \ set_pmd(pmd, __pmd(_PAGE_TABLE + \ ((unsigned long long)page_to_pfn(pte) << \ (unsigned long long) PAGE_SHIFT))); \ diff --git a/include/asm-x86_64/pgalloc.h b/include/asm-x86/pgalloc_64.h index 8bb564687860..8bb564687860 100644 --- a/include/asm-x86_64/pgalloc.h +++ b/include/asm-x86/pgalloc_64.h diff --git a/include/asm-i386/pgtable-2level-defs.h b/include/asm-x86/pgtable-2level-defs.h index 0f71c9f13da4..0f71c9f13da4 100644 --- a/include/asm-i386/pgtable-2level-defs.h +++ b/include/asm-x86/pgtable-2level-defs.h diff --git a/include/asm-i386/pgtable-2level.h b/include/asm-x86/pgtable-2level.h index 84b03cf56a79..84b03cf56a79 100644 --- a/include/asm-i386/pgtable-2level.h +++ b/include/asm-x86/pgtable-2level.h diff --git a/include/asm-i386/pgtable-3level-defs.h b/include/asm-x86/pgtable-3level-defs.h index c0df89f66e8b..c0df89f66e8b 100644 --- a/include/asm-i386/pgtable-3level-defs.h +++ b/include/asm-x86/pgtable-3level-defs.h diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-x86/pgtable-3level.h index 948a33414118..948a33414118 100644 --- a/include/asm-i386/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h new file mode 100644 index 000000000000..1039140652af --- /dev/null +++ b/include/asm-x86/pgtable.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "pgtable_32.h" +#else +# include "pgtable_64.h" +#endif diff --git a/include/asm-i386/pgtable.h b/include/asm-x86/pgtable_32.h index c7fefa6b12fd..c7fefa6b12fd 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-x86/pgtable_32.h diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86/pgtable_64.h index 3ba53099297d..57dd6b3107ea 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86/pgtable_64.h @@ -403,6 +403,8 @@ extern struct list_head pgd_list; extern int kern_addr_valid(unsigned long addr); +pte_t *lookup_address(unsigned long addr); + #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ remap_pfn_range(vma, vaddr, pfn, size, prot) diff --git a/include/asm-i386/poll.h b/include/asm-x86/poll.h index c98509d3149e..c98509d3149e 100644 --- a/include/asm-i386/poll.h +++ b/include/asm-x86/poll.h diff --git a/include/asm-x86/posix_types.h b/include/asm-x86/posix_types.h new file mode 100644 index 000000000000..bb7133dc155d --- /dev/null +++ b/include/asm-x86/posix_types.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "posix_types_32.h" +# else +# include "posix_types_64.h" +# endif +#else +# ifdef __i386__ +# include "posix_types_32.h" +# else +# include "posix_types_64.h" +# endif +#endif diff --git a/include/asm-i386/posix_types.h b/include/asm-x86/posix_types_32.h index 133e31e7dfde..133e31e7dfde 100644 --- a/include/asm-i386/posix_types.h +++ b/include/asm-x86/posix_types_32.h diff --git a/include/asm-x86_64/posix_types.h b/include/asm-x86/posix_types_64.h index 9926aa43775b..9926aa43775b 100644 --- a/include/asm-x86_64/posix_types.h +++ b/include/asm-x86/posix_types_64.h diff --git a/include/asm-x86_64/prctl.h b/include/asm-x86/prctl.h index 52952adef1ca..52952adef1ca 100644 --- a/include/asm-x86_64/prctl.h +++ b/include/asm-x86/prctl.h diff --git a/include/asm-x86/processor-cyrix.h b/include/asm-x86/processor-cyrix.h new file mode 100644 index 000000000000..97568ada1f97 --- /dev/null +++ b/include/asm-x86/processor-cyrix.h @@ -0,0 +1,30 @@ +/* + * NSC/Cyrix CPU indexed register access. Must be inlined instead of + * macros to ensure correct access ordering + * Access order is always 0x22 (=offset), 0x23 (=value) + * + * When using the old macros a line like + * setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); + * gets expanded to: + * do { + * outb((CX86_CCR2), 0x22); + * outb((({ + * outb((CX86_CCR2), 0x22); + * inb(0x23); + * }) | 0x88), 0x23); + * } while (0); + * + * which in fact violates the access order (= 0x22, 0x22, 0x23, 0x23). + */ + +static inline u8 getCx86(u8 reg) +{ + outb(reg, 0x22); + return inb(0x23); +} + +static inline void setCx86(u8 reg, u8 data) +{ + outb(reg, 0x22); + outb(data, 0x23); +} diff --git a/include/asm-i386/processor-flags.h b/include/asm-x86/processor-flags.h index 5404e90edd57..5404e90edd57 100644 --- a/include/asm-i386/processor-flags.h +++ b/include/asm-x86/processor-flags.h diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h new file mode 100644 index 000000000000..46e1c04e309c --- /dev/null +++ b/include/asm-x86/processor.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "processor_32.h" +#else +# include "processor_64.h" +#endif diff --git a/include/asm-i386/processor.h b/include/asm-x86/processor_32.h index 422cffef00c9..3845fe72383e 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-x86/processor_32.h @@ -88,7 +88,6 @@ struct cpuinfo_x86 { #define X86_VENDOR_UMC 3 #define X86_VENDOR_NEXGEN 4 #define X86_VENDOR_CENTAUR 5 -#define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 #define X86_VENDOR_NUM 9 @@ -169,17 +168,6 @@ static inline void clear_in_cr4 (unsigned long mask) write_cr4(cr4); } -/* - * NSC/Cyrix CPU indexed register access macros - */ - -#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) - -#define setCx86(reg, data) do { \ - outb((reg), 0x22); \ - outb((data), 0x23); \ -} while (0) - /* Stop speculative execution */ static inline void sync_core(void) { diff --git a/include/asm-x86_64/processor.h b/include/asm-x86/processor_64.h index efc87a5aff7f..31f579b828f2 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86/processor_64.h @@ -83,7 +83,6 @@ struct cpuinfo_x86 { #define X86_VENDOR_UMC 3 #define X86_VENDOR_NEXGEN 4 #define X86_VENDOR_CENTAUR 5 -#define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NUM 8 #define X86_VENDOR_UNKNOWN 0xff @@ -372,7 +371,7 @@ static inline void sync_core(void) #define ARCH_HAS_PREFETCH static inline void prefetch(void *x) { - asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); + asm volatile("prefetcht0 (%0)" :: "r" (x)); } #define ARCH_HAS_PREFETCHW 1 @@ -390,17 +389,6 @@ static inline void prefetchw(void *x) #define cpu_relax() rep_nop() -/* - * NSC/Cyrix CPU indexed register access macros - */ - -#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) - -#define setCx86(reg, data) do { \ - outb((reg), 0x22); \ - outb((data), 0x23); \ -} while (0) - static inline void serialize_cpu(void) { __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); diff --git a/include/asm-x86_64/proto.h b/include/asm-x86/proto.h index 85255db1e82d..c44a3a93b5a4 100644 --- a/include/asm-x86_64/proto.h +++ b/include/asm-x86/proto.h @@ -51,9 +51,6 @@ extern void reserve_bootmem_generic(unsigned long phys, unsigned len); extern void load_gs_index(unsigned gs); -extern void stop_timer_interrupt(void); -extern void main_timer_handler(void); - extern unsigned long end_pfn_map; extern void show_trace(struct task_struct *, struct pt_regs *, unsigned long * rsp); @@ -75,8 +72,6 @@ extern void setup_node_bootmem(int nodeid, unsigned long start, unsigned long en extern void early_quirks(void); extern void check_efer(void); -extern int unhandled_signal(struct task_struct *tsk, int sig); - extern void select_idle_routine(const struct cpuinfo_x86 *c); extern unsigned long table_start, table_end; @@ -85,24 +80,6 @@ extern int exception_trace; extern unsigned cpu_khz; extern unsigned tsc_khz; -extern void no_iommu_init(void); -extern int force_iommu, no_iommu; -extern int iommu_detected; -#ifdef CONFIG_IOMMU -extern void gart_iommu_init(void); -extern void __init gart_parse_options(char *); -extern void iommu_hole_init(void); -extern int fallback_aper_order; -extern int fallback_aper_force; -extern int iommu_aperture; -extern int iommu_aperture_allowed; -extern int iommu_aperture_disabled; -extern int fix_aperture; -#else -#define iommu_aperture 0 -#define iommu_aperture_allowed 0 -#endif - extern int reboot_force; extern int notsc_setup(char *); @@ -110,14 +87,10 @@ extern int timer_over_8254; extern int gsi_irq_sharing(int gsi); -extern void smp_local_timer_interrupt(void); - extern int force_mwait; long do_arch_prctl(struct task_struct *task, int code, unsigned long addr); -void i8254_timer_resume(void); - #define round_up(x,y) (((x) + (y) - 1) & ~((y)-1)) #define round_down(x,y) ((x) & ~((y)-1)) diff --git a/include/asm-x86/ptrace-abi.h b/include/asm-x86/ptrace-abi.h new file mode 100644 index 000000000000..6824c49def1c --- /dev/null +++ b/include/asm-x86/ptrace-abi.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ptrace-abi_32.h" +# else +# include "ptrace-abi_64.h" +# endif +#else +# ifdef __i386__ +# include "ptrace-abi_32.h" +# else +# include "ptrace-abi_64.h" +# endif +#endif diff --git a/include/asm-i386/ptrace-abi.h b/include/asm-x86/ptrace-abi_32.h index a44901817a26..a44901817a26 100644 --- a/include/asm-i386/ptrace-abi.h +++ b/include/asm-x86/ptrace-abi_32.h diff --git a/include/asm-x86_64/ptrace-abi.h b/include/asm-x86/ptrace-abi_64.h index 19184b0806b1..19184b0806b1 100644 --- a/include/asm-x86_64/ptrace-abi.h +++ b/include/asm-x86/ptrace-abi_64.h diff --git a/include/asm-x86/ptrace.h b/include/asm-x86/ptrace.h new file mode 100644 index 000000000000..bc4d64a87689 --- /dev/null +++ b/include/asm-x86/ptrace.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ptrace_32.h" +# else +# include "ptrace_64.h" +# endif +#else +# ifdef __i386__ +# include "ptrace_32.h" +# else +# include "ptrace_64.h" +# endif +#endif diff --git a/include/asm-i386/ptrace.h b/include/asm-x86/ptrace_32.h index 6002597b9e12..6002597b9e12 100644 --- a/include/asm-i386/ptrace.h +++ b/include/asm-x86/ptrace_32.h diff --git a/include/asm-x86_64/ptrace.h b/include/asm-x86/ptrace_64.h index 5ea84dbb1e9c..7f166ccb0606 100644 --- a/include/asm-x86_64/ptrace.h +++ b/include/asm-x86/ptrace_64.h @@ -1,6 +1,7 @@ #ifndef _X86_64_PTRACE_H #define _X86_64_PTRACE_H +#include <linux/compiler.h> /* For __user */ #include <asm/ptrace-abi.h> #ifndef __ASSEMBLY__ diff --git a/include/asm-i386/reboot.h b/include/asm-x86/reboot.h index e9e3ffc22c07..e9e3ffc22c07 100644 --- a/include/asm-i386/reboot.h +++ b/include/asm-x86/reboot.h diff --git a/include/asm-i386/reboot_fixups.h b/include/asm-x86/reboot_fixups.h index 0cb7d87c2b68..0cb7d87c2b68 100644 --- a/include/asm-i386/reboot_fixups.h +++ b/include/asm-x86/reboot_fixups.h diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h new file mode 100644 index 000000000000..8b64f3ea2b78 --- /dev/null +++ b/include/asm-x86/required-features.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "required-features_32.h" +#else +# include "required-features_64.h" +#endif diff --git a/include/asm-i386/required-features.h b/include/asm-x86/required-features_32.h index 65848a007050..618feb98f9f5 100644 --- a/include/asm-i386/required-features.h +++ b/include/asm-x86/required-features_32.h @@ -29,7 +29,7 @@ # define NEED_CMOV 0 #endif -#ifdef CONFIG_X86_CMPXCHG64 +#ifdef CONFIG_X86_PAE # define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) #else # define NEED_CX8 0 diff --git a/include/asm-x86_64/required-features.h b/include/asm-x86/required-features_64.h index e80d5761b00a..e80d5761b00a 100644 --- a/include/asm-x86_64/required-features.h +++ b/include/asm-x86/required-features_64.h diff --git a/include/asm-x86/resource.h b/include/asm-x86/resource.h new file mode 100644 index 000000000000..732410a8c02a --- /dev/null +++ b/include/asm-x86/resource.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "resource_32.h" +# else +# include "resource_64.h" +# endif +#else +# ifdef __i386__ +# include "resource_32.h" +# else +# include "resource_64.h" +# endif +#endif diff --git a/include/asm-i386/resource.h b/include/asm-x86/resource_32.h index 6c1ea37c7718..6c1ea37c7718 100644 --- a/include/asm-i386/resource.h +++ b/include/asm-x86/resource_32.h diff --git a/include/asm-x86_64/resource.h b/include/asm-x86/resource_64.h index f40b40623234..f40b40623234 100644 --- a/include/asm-x86_64/resource.h +++ b/include/asm-x86/resource_64.h diff --git a/include/asm-x86/resume-trace.h b/include/asm-x86/resume-trace.h new file mode 100644 index 000000000000..9b6dd093a9f7 --- /dev/null +++ b/include/asm-x86/resume-trace.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "resume-trace_32.h" +#else +# include "resume-trace_64.h" +#endif diff --git a/include/asm-x86/resume-trace_32.h b/include/asm-x86/resume-trace_32.h new file mode 100644 index 000000000000..ec9cfd656230 --- /dev/null +++ b/include/asm-x86/resume-trace_32.h @@ -0,0 +1,13 @@ +#define TRACE_RESUME(user) do { \ + if (pm_trace_enabled) { \ + void *tracedata; \ + asm volatile("movl $1f,%0\n" \ + ".section .tracedata,\"a\"\n" \ + "1:\t.word %c1\n" \ + "\t.long %c2\n" \ + ".previous" \ + :"=r" (tracedata) \ + : "i" (__LINE__), "i" (__FILE__)); \ + generate_resume_trace(tracedata, user); \ + } \ +} while (0) diff --git a/include/asm-x86/resume-trace_64.h b/include/asm-x86/resume-trace_64.h new file mode 100644 index 000000000000..34bf998fdf62 --- /dev/null +++ b/include/asm-x86/resume-trace_64.h @@ -0,0 +1,13 @@ +#define TRACE_RESUME(user) do { \ + if (pm_trace_enabled) { \ + void *tracedata; \ + asm volatile("movq $1f,%0\n" \ + ".section .tracedata,\"a\"\n" \ + "1:\t.word %c1\n" \ + "\t.quad %c2\n" \ + ".previous" \ + :"=r" (tracedata) \ + : "i" (__LINE__), "i" (__FILE__)); \ + generate_resume_trace(tracedata, user); \ + } \ +} while (0) diff --git a/include/asm-x86_64/rio.h b/include/asm-x86/rio.h index c7350f6d2015..c7350f6d2015 100644 --- a/include/asm-x86_64/rio.h +++ b/include/asm-x86/rio.h diff --git a/include/asm-x86/rtc.h b/include/asm-x86/rtc.h new file mode 100644 index 000000000000..1f0c98eb2e38 --- /dev/null +++ b/include/asm-x86/rtc.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "rtc_32.h" +#else +# include "rtc_64.h" +#endif diff --git a/include/asm-i386/rtc.h b/include/asm-x86/rtc_32.h index ffd02109a0e5..ffd02109a0e5 100644 --- a/include/asm-i386/rtc.h +++ b/include/asm-x86/rtc_32.h diff --git a/include/asm-x86_64/rtc.h b/include/asm-x86/rtc_64.h index 18ed713ac7de..18ed713ac7de 100644 --- a/include/asm-x86_64/rtc.h +++ b/include/asm-x86/rtc_64.h diff --git a/include/asm-x86/rwlock.h b/include/asm-x86/rwlock.h new file mode 100644 index 000000000000..a3be7d8364af --- /dev/null +++ b/include/asm-x86/rwlock.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "rwlock_32.h" +#else +# include "rwlock_64.h" +#endif diff --git a/include/asm-i386/rwlock.h b/include/asm-x86/rwlock_32.h index c3e5db32fa48..c3e5db32fa48 100644 --- a/include/asm-i386/rwlock.h +++ b/include/asm-x86/rwlock_32.h diff --git a/include/asm-x86_64/rwlock.h b/include/asm-x86/rwlock_64.h index 72aeebed920b..72aeebed920b 100644 --- a/include/asm-x86_64/rwlock.h +++ b/include/asm-x86/rwlock_64.h diff --git a/include/asm-i386/rwsem.h b/include/asm-x86/rwsem.h index 041906f3c6df..041906f3c6df 100644 --- a/include/asm-i386/rwsem.h +++ b/include/asm-x86/rwsem.h diff --git a/include/asm-x86/scatterlist.h b/include/asm-x86/scatterlist.h new file mode 100644 index 000000000000..3a1e76257a27 --- /dev/null +++ b/include/asm-x86/scatterlist.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "scatterlist_32.h" +#else +# include "scatterlist_64.h" +#endif diff --git a/include/asm-i386/scatterlist.h b/include/asm-x86/scatterlist_32.h index d7e45a8f1aae..d7e45a8f1aae 100644 --- a/include/asm-i386/scatterlist.h +++ b/include/asm-x86/scatterlist_32.h diff --git a/include/asm-x86_64/scatterlist.h b/include/asm-x86/scatterlist_64.h index eaf7ada27e14..eaf7ada27e14 100644 --- a/include/asm-x86_64/scatterlist.h +++ b/include/asm-x86/scatterlist_64.h diff --git a/include/asm-x86/seccomp.h b/include/asm-x86/seccomp.h new file mode 100644 index 000000000000..c62e58a5a90d --- /dev/null +++ b/include/asm-x86/seccomp.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "seccomp_32.h" +#else +# include "seccomp_64.h" +#endif diff --git a/include/asm-i386/seccomp.h b/include/asm-x86/seccomp_32.h index 18da19e89bff..18da19e89bff 100644 --- a/include/asm-i386/seccomp.h +++ b/include/asm-x86/seccomp_32.h diff --git a/include/asm-x86_64/seccomp.h b/include/asm-x86/seccomp_64.h index 553af65a2287..553af65a2287 100644 --- a/include/asm-x86_64/seccomp.h +++ b/include/asm-x86/seccomp_64.h diff --git a/include/asm-x86/sections.h b/include/asm-x86/sections.h new file mode 100644 index 000000000000..ae6c69d9be3f --- /dev/null +++ b/include/asm-x86/sections.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "sections_32.h" +#else +# include "sections_64.h" +#endif diff --git a/include/asm-i386/sections.h b/include/asm-x86/sections_32.h index 2dcbb92918b2..2dcbb92918b2 100644 --- a/include/asm-i386/sections.h +++ b/include/asm-x86/sections_32.h diff --git a/include/asm-x86_64/sections.h b/include/asm-x86/sections_64.h index c746d9f1e70c..c746d9f1e70c 100644 --- a/include/asm-x86_64/sections.h +++ b/include/asm-x86/sections_64.h diff --git a/include/asm-x86/segment.h b/include/asm-x86/segment.h new file mode 100644 index 000000000000..605068280e28 --- /dev/null +++ b/include/asm-x86/segment.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "segment_32.h" +#else +# include "segment_64.h" +#endif diff --git a/include/asm-i386/segment.h b/include/asm-x86/segment_32.h index 597a47c2515f..597a47c2515f 100644 --- a/include/asm-i386/segment.h +++ b/include/asm-x86/segment_32.h diff --git a/include/asm-x86_64/segment.h b/include/asm-x86/segment_64.h index 04b8ab21328f..04b8ab21328f 100644 --- a/include/asm-x86_64/segment.h +++ b/include/asm-x86/segment_64.h diff --git a/include/asm-x86/semaphore.h b/include/asm-x86/semaphore.h new file mode 100644 index 000000000000..572c0b67a6b0 --- /dev/null +++ b/include/asm-x86/semaphore.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "semaphore_32.h" +#else +# include "semaphore_64.h" +#endif diff --git a/include/asm-i386/semaphore.h b/include/asm-x86/semaphore_32.h index 4e34a468c383..4e34a468c383 100644 --- a/include/asm-i386/semaphore.h +++ b/include/asm-x86/semaphore_32.h diff --git a/include/asm-x86_64/semaphore.h b/include/asm-x86/semaphore_64.h index 1194888536b9..1194888536b9 100644 --- a/include/asm-x86_64/semaphore.h +++ b/include/asm-x86/semaphore_64.h diff --git a/include/asm-x86/sembuf.h b/include/asm-x86/sembuf.h new file mode 100644 index 000000000000..e42c971e383f --- /dev/null +++ b/include/asm-x86/sembuf.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "sembuf_32.h" +# else +# include "sembuf_64.h" +# endif +#else +# ifdef __i386__ +# include "sembuf_32.h" +# else +# include "sembuf_64.h" +# endif +#endif diff --git a/include/asm-i386/sembuf.h b/include/asm-x86/sembuf_32.h index 323835166c14..323835166c14 100644 --- a/include/asm-i386/sembuf.h +++ b/include/asm-x86/sembuf_32.h diff --git a/include/asm-x86_64/sembuf.h b/include/asm-x86/sembuf_64.h index 63b52925ae2a..63b52925ae2a 100644 --- a/include/asm-x86_64/sembuf.h +++ b/include/asm-x86/sembuf_64.h diff --git a/include/asm-x86/serial.h b/include/asm-x86/serial.h new file mode 100644 index 000000000000..cf1b05227b29 --- /dev/null +++ b/include/asm-x86/serial.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "serial_32.h" +#else +# include "serial_64.h" +#endif diff --git a/include/asm-x86/serial_32.h b/include/asm-x86/serial_32.h new file mode 100644 index 000000000000..bd67480ca109 --- /dev/null +++ b/include/asm-x86/serial_32.h @@ -0,0 +1,29 @@ +/* + * include/asm-i386/serial.h + */ + + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#define SERIAL_PORT_DFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ + { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ + { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ diff --git a/include/asm-x86/serial_64.h b/include/asm-x86/serial_64.h new file mode 100644 index 000000000000..b0496e0d72a6 --- /dev/null +++ b/include/asm-x86/serial_64.h @@ -0,0 +1,29 @@ +/* + * include/asm-x86_64/serial.h + */ + + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#define SERIAL_PORT_DFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ + { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ + { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h new file mode 100644 index 000000000000..81c0d98bb1c8 --- /dev/null +++ b/include/asm-x86/setup.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "setup_32.h" +# else +# include "setup_64.h" +# endif +#else +# ifdef __i386__ +# include "setup_32.h" +# else +# include "setup_64.h" +# endif +#endif diff --git a/include/asm-i386/setup.h b/include/asm-x86/setup_32.h index 0d5bff9dc4a5..7862fe858a9e 100644 --- a/include/asm-i386/setup.h +++ b/include/asm-x86/setup_32.h @@ -81,6 +81,10 @@ void __init add_memory_region(unsigned long long start, extern unsigned long init_pg_tables_end; +#ifndef CONFIG_PARAVIRT +#define paravirt_post_allocator_init() do {} while (0) +#endif + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-x86_64/setup.h b/include/asm-x86/setup_64.h index eaeff73d6c10..eaeff73d6c10 100644 --- a/include/asm-x86_64/setup.h +++ b/include/asm-x86/setup_64.h diff --git a/include/asm-x86/shmbuf.h b/include/asm-x86/shmbuf.h new file mode 100644 index 000000000000..e85f1cb11217 --- /dev/null +++ b/include/asm-x86/shmbuf.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "shmbuf_32.h" +# else +# include "shmbuf_64.h" +# endif +#else +# ifdef __i386__ +# include "shmbuf_32.h" +# else +# include "shmbuf_64.h" +# endif +#endif diff --git a/include/asm-i386/shmbuf.h b/include/asm-x86/shmbuf_32.h index d1cdc3cb079b..d1cdc3cb079b 100644 --- a/include/asm-i386/shmbuf.h +++ b/include/asm-x86/shmbuf_32.h diff --git a/include/asm-x86_64/shmbuf.h b/include/asm-x86/shmbuf_64.h index 5a6d6dda7c48..5a6d6dda7c48 100644 --- a/include/asm-x86_64/shmbuf.h +++ b/include/asm-x86/shmbuf_64.h diff --git a/include/asm-x86/shmparam.h b/include/asm-x86/shmparam.h new file mode 100644 index 000000000000..165627cc5345 --- /dev/null +++ b/include/asm-x86/shmparam.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "shmparam_32.h" +# else +# include "shmparam_64.h" +# endif +#else +# ifdef __i386__ +# include "shmparam_32.h" +# else +# include "shmparam_64.h" +# endif +#endif diff --git a/include/asm-i386/shmparam.h b/include/asm-x86/shmparam_32.h index 786243a5b319..786243a5b319 100644 --- a/include/asm-i386/shmparam.h +++ b/include/asm-x86/shmparam_32.h diff --git a/include/asm-x86_64/shmparam.h b/include/asm-x86/shmparam_64.h index d7021620dcb7..d7021620dcb7 100644 --- a/include/asm-x86_64/shmparam.h +++ b/include/asm-x86/shmparam_64.h diff --git a/include/asm-x86/sigcontext.h b/include/asm-x86/sigcontext.h new file mode 100644 index 000000000000..0d16ceff1599 --- /dev/null +++ b/include/asm-x86/sigcontext.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "sigcontext_32.h" +# else +# include "sigcontext_64.h" +# endif +#else +# ifdef __i386__ +# include "sigcontext_32.h" +# else +# include "sigcontext_64.h" +# endif +#endif diff --git a/include/asm-x86_64/sigcontext32.h b/include/asm-x86/sigcontext32.h index 3d657038ab7c..3d657038ab7c 100644 --- a/include/asm-x86_64/sigcontext32.h +++ b/include/asm-x86/sigcontext32.h diff --git a/include/asm-i386/sigcontext.h b/include/asm-x86/sigcontext_32.h index aaef089a7787..aaef089a7787 100644 --- a/include/asm-i386/sigcontext.h +++ b/include/asm-x86/sigcontext_32.h diff --git a/include/asm-x86_64/sigcontext.h b/include/asm-x86/sigcontext_64.h index b4e40236666c..b4e40236666c 100644 --- a/include/asm-x86_64/sigcontext.h +++ b/include/asm-x86/sigcontext_64.h diff --git a/include/asm-x86/siginfo.h b/include/asm-x86/siginfo.h new file mode 100644 index 000000000000..0b8e4bb47d25 --- /dev/null +++ b/include/asm-x86/siginfo.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "siginfo_32.h" +# else +# include "siginfo_64.h" +# endif +#else +# ifdef __i386__ +# include "siginfo_32.h" +# else +# include "siginfo_64.h" +# endif +#endif diff --git a/include/asm-i386/siginfo.h b/include/asm-x86/siginfo_32.h index fe18f98fccfa..fe18f98fccfa 100644 --- a/include/asm-i386/siginfo.h +++ b/include/asm-x86/siginfo_32.h diff --git a/include/asm-x86_64/siginfo.h b/include/asm-x86/siginfo_64.h index d09a1e6e7246..d09a1e6e7246 100644 --- a/include/asm-x86_64/siginfo.h +++ b/include/asm-x86/siginfo_64.h diff --git a/include/asm-x86/signal.h b/include/asm-x86/signal.h new file mode 100644 index 000000000000..bf5a63f457da --- /dev/null +++ b/include/asm-x86/signal.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "signal_32.h" +# else +# include "signal_64.h" +# endif +#else +# ifdef __i386__ +# include "signal_32.h" +# else +# include "signal_64.h" +# endif +#endif diff --git a/include/asm-i386/signal.h b/include/asm-x86/signal_32.h index c3e8adec5918..c3e8adec5918 100644 --- a/include/asm-i386/signal.h +++ b/include/asm-x86/signal_32.h diff --git a/include/asm-x86_64/signal.h b/include/asm-x86/signal_64.h index 4581f978b299..4581f978b299 100644 --- a/include/asm-x86_64/signal.h +++ b/include/asm-x86/signal_64.h diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h new file mode 100644 index 000000000000..f2e8319a6b0b --- /dev/null +++ b/include/asm-x86/smp.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "smp_32.h" +#else +# include "smp_64.h" +#endif diff --git a/include/asm-i386/smp.h b/include/asm-x86/smp_32.h index 0c7132787062..1f73bde165b1 100644 --- a/include/asm-i386/smp.h +++ b/include/asm-x86/smp_32.h @@ -43,9 +43,12 @@ extern u8 x86_cpu_to_apicid[]; #define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] +extern void set_cpu_sibling_map(int cpu); + #ifdef CONFIG_HOTPLUG_CPU extern void cpu_exit_clear(void); extern void cpu_uninit(void); +extern void remove_siblinginfo(int cpu); #endif struct smp_ops @@ -129,6 +132,8 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); extern unsigned int num_processors; +void __cpuinit smp_store_cpu_info(int id); + #endif /* !__ASSEMBLY__ */ #else /* CONFIG_SMP */ diff --git a/include/asm-x86_64/smp.h b/include/asm-x86/smp_64.h index 3f303d2365ed..3f303d2365ed 100644 --- a/include/asm-x86_64/smp.h +++ b/include/asm-x86/smp_64.h diff --git a/include/asm-i386/socket.h b/include/asm-x86/socket.h index 99ca648b94c5..99ca648b94c5 100644 --- a/include/asm-i386/socket.h +++ b/include/asm-x86/socket.h diff --git a/include/asm-x86/sockios.h b/include/asm-x86/sockios.h new file mode 100644 index 000000000000..5a134fc70b9c --- /dev/null +++ b/include/asm-x86/sockios.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "sockios_32.h" +# else +# include "sockios_64.h" +# endif +#else +# ifdef __i386__ +# include "sockios_32.h" +# else +# include "sockios_64.h" +# endif +#endif diff --git a/include/asm-i386/sockios.h b/include/asm-x86/sockios_32.h index ff528c7d255c..ff528c7d255c 100644 --- a/include/asm-i386/sockios.h +++ b/include/asm-x86/sockios_32.h diff --git a/include/asm-x86_64/sockios.h b/include/asm-x86/sockios_64.h index d726ba2513e3..d726ba2513e3 100644 --- a/include/asm-x86_64/sockios.h +++ b/include/asm-x86/sockios_64.h diff --git a/include/asm-x86/sparsemem.h b/include/asm-x86/sparsemem.h new file mode 100644 index 000000000000..3f203b1d9ee8 --- /dev/null +++ b/include/asm-x86/sparsemem.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "sparsemem_32.h" +#else +# include "sparsemem_64.h" +#endif diff --git a/include/asm-i386/sparsemem.h b/include/asm-x86/sparsemem_32.h index cfeed990585f..cfeed990585f 100644 --- a/include/asm-i386/sparsemem.h +++ b/include/asm-x86/sparsemem_32.h diff --git a/include/asm-x86_64/sparsemem.h b/include/asm-x86/sparsemem_64.h index dabb16714a71..dabb16714a71 100644 --- a/include/asm-x86_64/sparsemem.h +++ b/include/asm-x86/sparsemem_64.h diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h new file mode 100644 index 000000000000..d74d85e71dcb --- /dev/null +++ b/include/asm-x86/spinlock.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "spinlock_32.h" +#else +# include "spinlock_64.h" +#endif diff --git a/include/asm-i386/spinlock.h b/include/asm-x86/spinlock_32.h index d3bcebed60ca..d3bcebed60ca 100644 --- a/include/asm-i386/spinlock.h +++ b/include/asm-x86/spinlock_32.h diff --git a/include/asm-x86_64/spinlock.h b/include/asm-x86/spinlock_64.h index 88bf981e73cf..88bf981e73cf 100644 --- a/include/asm-x86_64/spinlock.h +++ b/include/asm-x86/spinlock_64.h diff --git a/include/asm-i386/spinlock_types.h b/include/asm-x86/spinlock_types.h index 4da9345c1500..4da9345c1500 100644 --- a/include/asm-i386/spinlock_types.h +++ b/include/asm-x86/spinlock_types.h diff --git a/include/asm-i386/srat.h b/include/asm-x86/srat.h index 165ab4bdc02b..165ab4bdc02b 100644 --- a/include/asm-i386/srat.h +++ b/include/asm-x86/srat.h diff --git a/include/asm-x86_64/stacktrace.h b/include/asm-x86/stacktrace.h index 6f0b54594307..6f0b54594307 100644 --- a/include/asm-x86_64/stacktrace.h +++ b/include/asm-x86/stacktrace.h diff --git a/include/asm-x86/stat.h b/include/asm-x86/stat.h new file mode 100644 index 000000000000..3ff6b50ef833 --- /dev/null +++ b/include/asm-x86/stat.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "stat_32.h" +# else +# include "stat_64.h" +# endif +#else +# ifdef __i386__ +# include "stat_32.h" +# else +# include "stat_64.h" +# endif +#endif diff --git a/include/asm-i386/stat.h b/include/asm-x86/stat_32.h index 67eae78323ba..67eae78323ba 100644 --- a/include/asm-i386/stat.h +++ b/include/asm-x86/stat_32.h diff --git a/include/asm-x86_64/stat.h b/include/asm-x86/stat_64.h index fd9f00d560f8..fd9f00d560f8 100644 --- a/include/asm-x86_64/stat.h +++ b/include/asm-x86/stat_64.h diff --git a/include/asm-x86/statfs.h b/include/asm-x86/statfs.h new file mode 100644 index 000000000000..327fb5d7a148 --- /dev/null +++ b/include/asm-x86/statfs.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "statfs_32.h" +# else +# include "statfs_64.h" +# endif +#else +# ifdef __i386__ +# include "statfs_32.h" +# else +# include "statfs_64.h" +# endif +#endif diff --git a/include/asm-i386/statfs.h b/include/asm-x86/statfs_32.h index 24972c175132..24972c175132 100644 --- a/include/asm-i386/statfs.h +++ b/include/asm-x86/statfs_32.h diff --git a/include/asm-x86_64/statfs.h b/include/asm-x86/statfs_64.h index b3f4718af30b..b3f4718af30b 100644 --- a/include/asm-x86_64/statfs.h +++ b/include/asm-x86/statfs_64.h diff --git a/include/asm-x86/string.h b/include/asm-x86/string.h new file mode 100644 index 000000000000..6dfd6d9373a0 --- /dev/null +++ b/include/asm-x86/string.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "string_32.h" +#else +# include "string_64.h" +#endif diff --git a/include/asm-i386/string.h b/include/asm-x86/string_32.h index b9277361954b..a9b64453bdf5 100644 --- a/include/asm-i386/string.h +++ b/include/asm-x86/string_32.h @@ -2,203 +2,35 @@ #define _I386_STRING_H_ #ifdef __KERNEL__ -/* - * On a 486 or Pentium, we are better off not using the - * byte string operations. But on a 386 or a PPro the - * byte string ops are faster than doing it by hand - * (MUCH faster on a Pentium). - */ - -/* - * This string-include defines all string functions as inline - * functions. Use gcc. It also assumes ds=es=data space, this should be - * normal. Most of the string-functions are rather heavily hand-optimized, - * see especially strsep,strstr,str[c]spn. They should work, but are not - * very easy to understand. Everything is done entirely within the register - * set, making the functions fast and clean. String instructions have been - * used through-out, making for "slightly" unclear code :-) - * - * NO Copyright (C) 1991, 1992 Linus Torvalds, - * consider these trivial functions to be PD. - */ -/* AK: in fact I bet it would be better to move this stuff all out of line. - */ +/* Let gcc decide wether to inline or use the out of line functions */ #define __HAVE_ARCH_STRCPY -static inline char * strcpy(char * dest,const char *src) -{ -int d0, d1, d2; -__asm__ __volatile__( - "1:\tlodsb\n\t" - "stosb\n\t" - "testb %%al,%%al\n\t" - "jne 1b" - : "=&S" (d0), "=&D" (d1), "=&a" (d2) - :"0" (src),"1" (dest) : "memory"); -return dest; -} +extern char *strcpy(char *dest, const char *src); #define __HAVE_ARCH_STRNCPY -static inline char * strncpy(char * dest,const char *src,size_t count) -{ -int d0, d1, d2, d3; -__asm__ __volatile__( - "1:\tdecl %2\n\t" - "js 2f\n\t" - "lodsb\n\t" - "stosb\n\t" - "testb %%al,%%al\n\t" - "jne 1b\n\t" - "rep\n\t" - "stosb\n" - "2:" - : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3) - :"0" (src),"1" (dest),"2" (count) : "memory"); -return dest; -} +extern char *strncpy(char *dest, const char *src, size_t count); #define __HAVE_ARCH_STRCAT -static inline char * strcat(char * dest,const char * src) -{ -int d0, d1, d2, d3; -__asm__ __volatile__( - "repne\n\t" - "scasb\n\t" - "decl %1\n" - "1:\tlodsb\n\t" - "stosb\n\t" - "testb %%al,%%al\n\t" - "jne 1b" - : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) - : "0" (src), "1" (dest), "2" (0), "3" (0xffffffffu):"memory"); -return dest; -} +extern char *strcat(char *dest, const char *src); #define __HAVE_ARCH_STRNCAT -static inline char * strncat(char * dest,const char * src,size_t count) -{ -int d0, d1, d2, d3; -__asm__ __volatile__( - "repne\n\t" - "scasb\n\t" - "decl %1\n\t" - "movl %8,%3\n" - "1:\tdecl %3\n\t" - "js 2f\n\t" - "lodsb\n\t" - "stosb\n\t" - "testb %%al,%%al\n\t" - "jne 1b\n" - "2:\txorl %2,%2\n\t" - "stosb" - : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) - : "0" (src),"1" (dest),"2" (0),"3" (0xffffffffu), "g" (count) - : "memory"); -return dest; -} +extern char *strncat(char *dest, const char *src, size_t count); #define __HAVE_ARCH_STRCMP -static inline int strcmp(const char * cs,const char * ct) -{ -int d0, d1; -register int __res; -__asm__ __volatile__( - "1:\tlodsb\n\t" - "scasb\n\t" - "jne 2f\n\t" - "testb %%al,%%al\n\t" - "jne 1b\n\t" - "xorl %%eax,%%eax\n\t" - "jmp 3f\n" - "2:\tsbbl %%eax,%%eax\n\t" - "orb $1,%%al\n" - "3:" - :"=a" (__res), "=&S" (d0), "=&D" (d1) - :"1" (cs),"2" (ct) - :"memory"); -return __res; -} +extern int strcmp(const char *cs, const char *ct); #define __HAVE_ARCH_STRNCMP -static inline int strncmp(const char * cs,const char * ct,size_t count) -{ -register int __res; -int d0, d1, d2; -__asm__ __volatile__( - "1:\tdecl %3\n\t" - "js 2f\n\t" - "lodsb\n\t" - "scasb\n\t" - "jne 3f\n\t" - "testb %%al,%%al\n\t" - "jne 1b\n" - "2:\txorl %%eax,%%eax\n\t" - "jmp 4f\n" - "3:\tsbbl %%eax,%%eax\n\t" - "orb $1,%%al\n" - "4:" - :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2) - :"1" (cs),"2" (ct),"3" (count) - :"memory"); -return __res; -} +extern int strncmp(const char *cs, const char *ct, size_t count); #define __HAVE_ARCH_STRCHR -static inline char * strchr(const char * s, int c) -{ -int d0; -register char * __res; -__asm__ __volatile__( - "movb %%al,%%ah\n" - "1:\tlodsb\n\t" - "cmpb %%ah,%%al\n\t" - "je 2f\n\t" - "testb %%al,%%al\n\t" - "jne 1b\n\t" - "movl $1,%1\n" - "2:\tmovl %1,%0\n\t" - "decl %0" - :"=a" (__res), "=&S" (d0) - :"1" (s),"0" (c) - :"memory"); -return __res; -} +extern char *strchr(const char *s, int c); #define __HAVE_ARCH_STRRCHR -static inline char * strrchr(const char * s, int c) -{ -int d0, d1; -register char * __res; -__asm__ __volatile__( - "movb %%al,%%ah\n" - "1:\tlodsb\n\t" - "cmpb %%ah,%%al\n\t" - "jne 2f\n\t" - "leal -1(%%esi),%0\n" - "2:\ttestb %%al,%%al\n\t" - "jne 1b" - :"=g" (__res), "=&S" (d0), "=&a" (d1) - :"0" (0),"1" (s),"2" (c) - :"memory"); -return __res; -} +extern char *strrchr(const char *s, int c); #define __HAVE_ARCH_STRLEN -static inline size_t strlen(const char * s) -{ -int d0; -register int __res; -__asm__ __volatile__( - "repne\n\t" - "scasb\n\t" - "notl %0\n\t" - "decl %0" - :"=c" (__res), "=&D" (d0) - :"1" (s),"a" (0), "0" (0xffffffffu) - :"memory"); -return __res; -} +extern size_t strlen(const char *s); static __always_inline void * __memcpy(void * to, const void * from, size_t n) { @@ -207,9 +39,7 @@ __asm__ __volatile__( "rep ; movsl\n\t" "movl %4,%%ecx\n\t" "andl $3,%%ecx\n\t" -#if 1 /* want to pay 2 byte penalty for a chance to skip microcoded rep? */ "jz 1f\n\t" -#endif "rep ; movsb\n\t" "1:" : "=&c" (d0), "=&D" (d1), "=&S" (d2) @@ -328,23 +158,7 @@ void *memmove(void * dest,const void * src, size_t n); #define memcmp __builtin_memcmp #define __HAVE_ARCH_MEMCHR -static inline void * memchr(const void * cs,int c,size_t count) -{ -int d0; -register void * __res; -if (!count) - return NULL; -__asm__ __volatile__( - "repne\n\t" - "scasb\n\t" - "je 1f\n\t" - "movl $1,%0\n" - "1:\tdecl %0" - :"=D" (__res), "=&c" (d0) - :"a" (c),"0" (cs),"1" (count) - :"memory"); -return __res; -} +extern void *memchr(const void * cs,int c,size_t count); static inline void * __memset_generic(void * s, char c,size_t count) { @@ -386,29 +200,10 @@ return (s); /* Added by Gertjan van Wingerde to make minix and sysv module work */ #define __HAVE_ARCH_STRNLEN -static inline size_t strnlen(const char * s, size_t count) -{ -int d0; -register int __res; -__asm__ __volatile__( - "movl %2,%0\n\t" - "jmp 2f\n" - "1:\tcmpb $0,(%0)\n\t" - "je 3f\n\t" - "incl %0\n" - "2:\tdecl %1\n\t" - "cmpl $-1,%1\n\t" - "jne 1b\n" - "3:\tsubl %2,%0" - :"=a" (__res), "=&d" (d0) - :"c" (s),"1" (count) - :"memory"); -return __res; -} +extern size_t strnlen(const char * s, size_t count); /* end of additional stuff */ #define __HAVE_ARCH_STRSTR - extern char *strstr(const char *cs, const char *ct); /* @@ -474,19 +269,7 @@ __asm__ __volatile__( \ * find the first occurrence of byte 'c', or 1 past the area if none */ #define __HAVE_ARCH_MEMSCAN -static inline void * memscan(void * addr, int c, size_t size) -{ - if (!size) - return addr; - __asm__("repnz; scasb\n\t" - "jnz 1f\n\t" - "dec %%edi\n" - "1:" - : "=D" (addr), "=c" (size) - : "0" (addr), "1" (size), "a" (c) - : "memory"); - return addr; -} +extern void *memscan(void * addr, int c, size_t size); #endif /* __KERNEL__ */ diff --git a/include/asm-x86_64/string.h b/include/asm-x86/string_64.h index 9505d9f4bead..e583da7918fb 100644 --- a/include/asm-x86_64/string.h +++ b/include/asm-x86/string_64.h @@ -29,6 +29,9 @@ return (to); function. */ #define __HAVE_ARCH_MEMCPY 1 +#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4 +extern void *memcpy(void *to, const void *from, size_t len); +#else extern void *__memcpy(void *to, const void *from, size_t len); #define memcpy(dst,src,len) \ ({ size_t __len = (len); \ @@ -38,7 +41,7 @@ extern void *__memcpy(void *to, const void *from, size_t len); else \ __ret = __builtin_memcpy((dst),(src),__len); \ __ret; }) - +#endif #define __HAVE_ARCH_MEMSET void *memset(void *s, int c, size_t n); diff --git a/include/asm-x86/suspend.h b/include/asm-x86/suspend.h new file mode 100644 index 000000000000..9bd521fe4570 --- /dev/null +++ b/include/asm-x86/suspend.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "suspend_32.h" +#else +# include "suspend_64.h" +#endif diff --git a/include/asm-i386/suspend.h b/include/asm-x86/suspend_32.h index 8dbaafe611ff..a2520732ffd6 100644 --- a/include/asm-i386/suspend.h +++ b/include/asm-x86/suspend_32.h @@ -21,7 +21,7 @@ struct saved_context { unsigned long return_address; } __attribute__((packed)); -#ifdef CONFIG_ACPI_SLEEP +#ifdef CONFIG_ACPI extern unsigned long saved_eip; extern unsigned long saved_esp; extern unsigned long saved_ebp; diff --git a/include/asm-x86_64/suspend.h b/include/asm-x86/suspend_64.h index 9c3f8de90d2d..b897e8cb55fb 100644 --- a/include/asm-x86_64/suspend.h +++ b/include/asm-x86/suspend_64.h @@ -44,7 +44,6 @@ extern unsigned long saved_context_eflags; extern void fix_processor_context(void); -#ifdef CONFIG_ACPI_SLEEP extern unsigned long saved_rip; extern unsigned long saved_rsp; extern unsigned long saved_rbp; @@ -54,4 +53,3 @@ extern unsigned long saved_rdi; /* routines for saving/restoring kernel state */ extern int acpi_save_state_mem(void); -#endif diff --git a/include/asm-x86_64/swiotlb.h b/include/asm-x86/swiotlb.h index f9c589539a82..f9c589539a82 100644 --- a/include/asm-x86_64/swiotlb.h +++ b/include/asm-x86/swiotlb.h diff --git a/include/asm-i386/sync_bitops.h b/include/asm-x86/sync_bitops.h index cbce08a2d135..cbce08a2d135 100644 --- a/include/asm-i386/sync_bitops.h +++ b/include/asm-x86/sync_bitops.h diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h new file mode 100644 index 000000000000..692562b48f2a --- /dev/null +++ b/include/asm-x86/system.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "system_32.h" +#else +# include "system_64.h" +#endif diff --git a/include/asm-i386/system.h b/include/asm-x86/system_32.h index 94ed3686a5f3..d69ba937e092 100644 --- a/include/asm-i386/system.h +++ b/include/asm-x86/system_32.h @@ -214,11 +214,6 @@ static inline unsigned long get_limit(unsigned long segment) */ -/* - * Actually only lfence would be needed for mb() because all stores done - * by the kernel should be already ordered. But keep a full barrier for now. - */ - #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) @@ -310,15 +305,6 @@ void enable_hlt(void); extern int es7000_plat; void cpu_idle_wait(void); -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible: - */ -static inline void sched_cacheflush(void) -{ - wbinvd(); -} - extern unsigned long arch_align_stack(unsigned long sp); extern void free_init_pages(char *what, unsigned long begin, unsigned long end); diff --git a/include/asm-x86_64/system.h b/include/asm-x86/system_64.h index ead9f9a56234..02175aa1d16a 100644 --- a/include/asm-x86_64/system.h +++ b/include/asm-x86/system_64.h @@ -75,19 +75,31 @@ static inline unsigned long read_cr0(void) unsigned long cr0; asm volatile("movq %%cr0,%0" : "=r" (cr0)); return cr0; -} +} static inline void write_cr0(unsigned long val) { asm volatile("movq %0,%%cr0" :: "r" (val)); -} +} + +static inline unsigned long read_cr2(void) +{ + unsigned long cr2; + asm("movq %%cr2,%0" : "=r" (cr2)); + return cr2; +} + +static inline void write_cr2(unsigned long val) +{ + asm volatile("movq %0,%%cr2" :: "r" (val)); +} static inline unsigned long read_cr3(void) { unsigned long cr3; asm("movq %%cr3,%0" : "=r" (cr3)); return cr3; -} +} static inline void write_cr3(unsigned long val) { @@ -99,27 +111,30 @@ static inline unsigned long read_cr4(void) unsigned long cr4; asm("movq %%cr4,%0" : "=r" (cr4)); return cr4; -} +} static inline void write_cr4(unsigned long val) { asm volatile("movq %0,%%cr4" :: "r" (val) : "memory"); -} - -#define stts() write_cr0(8 | read_cr0()) +} -#define wbinvd() \ - __asm__ __volatile__ ("wbinvd": : :"memory"); +static inline unsigned long read_cr8(void) +{ + unsigned long cr8; + asm("movq %%cr8,%0" : "=r" (cr8)); + return cr8; +} -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - */ -static inline void sched_cacheflush(void) +static inline void write_cr8(unsigned long val) { - wbinvd(); + asm volatile("movq %0,%%cr8" :: "r" (val) : "memory"); } +#define stts() write_cr0(8 | read_cr0()) + +#define wbinvd() \ + __asm__ __volatile__ ("wbinvd": : :"memory") + #endif /* __KERNEL__ */ #define nop() __asm__ __volatile__ ("nop") diff --git a/include/asm-x86_64/tce.h b/include/asm-x86/tce.h index dbb047febc5e..cd955d3d112f 100644 --- a/include/asm-x86_64/tce.h +++ b/include/asm-x86/tce.h @@ -41,8 +41,8 @@ struct iommu_table; extern void tce_build(struct iommu_table *tbl, unsigned long index, unsigned int npages, unsigned long uaddr, int direction); extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages); -extern void* alloc_tce_table(void); -extern void free_tce_table(void *tbl); -extern int build_tce_table(struct pci_dev *dev, void __iomem *bbar); +extern void * __init alloc_tce_table(void); +extern void __init free_tce_table(void *tbl); +extern int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar); #endif /* _ASM_X86_64_TCE_H */ diff --git a/include/asm-x86/termbits.h b/include/asm-x86/termbits.h new file mode 100644 index 000000000000..69f3080e2a1d --- /dev/null +++ b/include/asm-x86/termbits.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "termbits_32.h" +# else +# include "termbits_64.h" +# endif +#else +# ifdef __i386__ +# include "termbits_32.h" +# else +# include "termbits_64.h" +# endif +#endif diff --git a/include/asm-i386/termbits.h b/include/asm-x86/termbits_32.h index a21700352e7b..a21700352e7b 100644 --- a/include/asm-i386/termbits.h +++ b/include/asm-x86/termbits_32.h diff --git a/include/asm-x86_64/termbits.h b/include/asm-x86/termbits_64.h index 7405756dd41b..7405756dd41b 100644 --- a/include/asm-x86_64/termbits.h +++ b/include/asm-x86/termbits_64.h diff --git a/include/asm-x86/termios.h b/include/asm-x86/termios.h new file mode 100644 index 000000000000..a4f4ae20a591 --- /dev/null +++ b/include/asm-x86/termios.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "termios_32.h" +# else +# include "termios_64.h" +# endif +#else +# ifdef __i386__ +# include "termios_32.h" +# else +# include "termios_64.h" +# endif +#endif diff --git a/include/asm-i386/termios.h b/include/asm-x86/termios_32.h index f520b7c16fa2..6fdb2c841b73 100644 --- a/include/asm-i386/termios.h +++ b/include/asm-x86/termios_32.h @@ -40,7 +40,6 @@ struct termio { /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ #ifdef __KERNEL__ -#include <linux/module.h> /* intr=^C quit=^\ erase=del kill=^U eof=^D vtime=\0 vmin=\1 sxtc=\0 diff --git a/include/asm-x86_64/termios.h b/include/asm-x86/termios_64.h index 35ee59b78329..35ee59b78329 100644 --- a/include/asm-x86_64/termios.h +++ b/include/asm-x86/termios_64.h diff --git a/include/asm-i386/therm_throt.h b/include/asm-x86/therm_throt.h index 399bf6026b16..399bf6026b16 100644 --- a/include/asm-i386/therm_throt.h +++ b/include/asm-x86/therm_throt.h diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h new file mode 100644 index 000000000000..d5fd12f2abdb --- /dev/null +++ b/include/asm-x86/thread_info.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "thread_info_32.h" +#else +# include "thread_info_64.h" +#endif diff --git a/include/asm-i386/thread_info.h b/include/asm-x86/thread_info_32.h index 54424e045e01..22a8cbcd35e2 100644 --- a/include/asm-i386/thread_info.h +++ b/include/asm-x86/thread_info_32.h @@ -124,15 +124,14 @@ static inline struct thread_info *current_thread_info(void) * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ -#define TIF_IRET 5 /* return with iret */ -#define TIF_SYSCALL_EMU 6 /* syscall emulation active */ -#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ -#define TIF_SECCOMP 8 /* secure computing */ -#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */ +#define TIF_IRET 4 /* return with iret */ +#define TIF_SYSCALL_EMU 5 /* syscall emulation active */ +#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */ +#define TIF_SECCOMP 7 /* secure computing */ +#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal() */ #define TIF_MEMDIE 16 #define TIF_DEBUG 17 /* uses debug registers */ #define TIF_IO_BITMAP 18 /* uses I/O bitmap */ @@ -140,7 +139,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_NOTSC 20 /* TSC is not accessible in userland */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) diff --git a/include/asm-x86_64/thread_info.h b/include/asm-x86/thread_info_64.h index 10bb5a8ed688..beae2bfb62ca 100644 --- a/include/asm-x86_64/thread_info.h +++ b/include/asm-x86/thread_info_64.h @@ -107,7 +107,6 @@ static inline struct thread_info *stack_thread_info(void) * Warning: layout of LSW is hardcoded in entry.S */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/ @@ -115,6 +114,7 @@ static inline struct thread_info *stack_thread_info(void) #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal */ +#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */ /* 16 free */ #define TIF_IA32 17 /* 32bit process */ #define TIF_FORK 18 /* ret_from_fork */ @@ -125,7 +125,6 @@ static inline struct thread_info *stack_thread_info(void) #define TIF_FREEZE 23 /* is freezing for suspend */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) @@ -133,6 +132,7 @@ static inline struct thread_info *stack_thread_info(void) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) +#define _TIF_MCE_NOTIFY (1<<TIF_MCE_NOTIFY) #define _TIF_IA32 (1<<TIF_IA32) #define _TIF_FORK (1<<TIF_FORK) #define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) diff --git a/include/asm-i386/time.h b/include/asm-x86/time.h index eac011366dc2..eac011366dc2 100644 --- a/include/asm-i386/time.h +++ b/include/asm-x86/time.h diff --git a/include/asm-x86/timer.h b/include/asm-x86/timer.h new file mode 100644 index 000000000000..0db7e994fb8b --- /dev/null +++ b/include/asm-x86/timer.h @@ -0,0 +1,50 @@ +#ifndef _ASMi386_TIMER_H +#define _ASMi386_TIMER_H +#include <linux/init.h> +#include <linux/pm.h> + +#define TICK_SIZE (tick_nsec / 1000) + +unsigned long long native_sched_clock(void); +unsigned long native_calculate_cpu_khz(void); + +extern int timer_ack; +extern int no_timer_check; +extern int recalibrate_cpu_khz(void); + +#ifndef CONFIG_PARAVIRT +#define calculate_cpu_khz() native_calculate_cpu_khz() +#endif + +/* Accellerators for sched_clock() + * convert from cycles(64bits) => nanoseconds (64bits) + * basic equation: + * ns = cycles / (freq / ns_per_sec) + * ns = cycles * (ns_per_sec / freq) + * ns = cycles * (10^9 / (cpu_khz * 10^3)) + * ns = cycles * (10^6 / cpu_khz) + * + * Then we use scaling math (suggested by george@mvista.com) to get: + * ns = cycles * (10^6 * SC / cpu_khz) / SC + * ns = cycles * cyc2ns_scale / SC + * + * And since SC is a constant power of two, we can convert the div + * into a shift. + * + * We can use khz divisor instead of mhz to keep a better percision, since + * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. + * (mathieu.desnoyers@polymtl.ca) + * + * -johnstul@us.ibm.com "math is hard, lets go shopping!" + */ +extern unsigned long cyc2ns_scale __read_mostly; + +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ + +static inline unsigned long long cycles_2_ns(unsigned long long cyc) +{ + return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; +} + + +#endif diff --git a/include/asm-x86/timex.h b/include/asm-x86/timex.h new file mode 100644 index 000000000000..39a21ab030f0 --- /dev/null +++ b/include/asm-x86/timex.h @@ -0,0 +1,18 @@ +/* x86 architecture timex specifications */ +#ifndef _ASM_X86_TIMEX_H +#define _ASM_X86_TIMEX_H + +#include <asm/processor.h> +#include <asm/tsc.h> + +#ifdef CONFIG_X86_ELAN +# define PIT_TICK_RATE 1189200 /* AMD Elan has different frequency! */ +#else +# define PIT_TICK_RATE 1193182 /* Underlying HZ */ +#endif +#define CLOCK_TICK_RATE PIT_TICK_RATE + +extern int read_current_timer(unsigned long *timer_value); +#define ARCH_HAS_READ_CURRENT_TIMER 1 + +#endif diff --git a/include/asm-x86/tlb.h b/include/asm-x86/tlb.h new file mode 100644 index 000000000000..7d55c3762b43 --- /dev/null +++ b/include/asm-x86/tlb.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "tlb_32.h" +#else +# include "tlb_64.h" +#endif diff --git a/include/asm-i386/tlb.h b/include/asm-x86/tlb_32.h index c006c5c92bea..c006c5c92bea 100644 --- a/include/asm-i386/tlb.h +++ b/include/asm-x86/tlb_32.h diff --git a/include/asm-x86_64/tlb.h b/include/asm-x86/tlb_64.h index cd4c3c590a0e..cd4c3c590a0e 100644 --- a/include/asm-x86_64/tlb.h +++ b/include/asm-x86/tlb_64.h diff --git a/include/asm-x86/tlbflush.h b/include/asm-x86/tlbflush.h new file mode 100644 index 000000000000..9af4cc83a1af --- /dev/null +++ b/include/asm-x86/tlbflush.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "tlbflush_32.h" +#else +# include "tlbflush_64.h" +#endif diff --git a/include/asm-i386/tlbflush.h b/include/asm-x86/tlbflush_32.h index fc525c5cd5a9..a50fa6741486 100644 --- a/include/asm-i386/tlbflush.h +++ b/include/asm-x86/tlbflush_32.h @@ -160,7 +160,11 @@ DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate); native_flush_tlb_others(&mask, mm, va) #endif -#define flush_tlb_kernel_range(start, end) flush_tlb_all() +static inline void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + flush_tlb_all(); +} static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86/tlbflush_64.h index 8516225a8389..888eb4abdd07 100644 --- a/include/asm-x86_64/tlbflush.h +++ b/include/asm-x86/tlbflush_64.h @@ -92,7 +92,11 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st #endif -#define flush_tlb_kernel_range(start, end) flush_tlb_all() +static inline void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + flush_tlb_all(); +} static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h new file mode 100644 index 000000000000..b10fde9798ea --- /dev/null +++ b/include/asm-x86/topology.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "topology_32.h" +#else +# include "topology_64.h" +#endif diff --git a/include/asm-i386/topology.h b/include/asm-x86/topology_32.h index 7fc512d90ea8..19b2dafd0c81 100644 --- a/include/asm-i386/topology.h +++ b/include/asm-x86/topology_32.h @@ -67,7 +67,7 @@ static inline int node_to_first_cpu(int node) return first_cpu(mask); } -#define pcibus_to_node(bus) ((long) (bus)->sysdata) +#define pcibus_to_node(bus) ((struct pci_sysdata *)((bus)->sysdata))->node #define pcibus_to_cpumask(bus) node_to_cpumask(pcibus_to_node(bus)) /* sched_domains SD_NODE_INIT for NUMAQ machines */ diff --git a/include/asm-x86_64/topology.h b/include/asm-x86/topology_64.h index 4fd6fb23953e..36e52fba7960 100644 --- a/include/asm-x86_64/topology.h +++ b/include/asm-x86/topology_64.h @@ -22,7 +22,7 @@ extern int __node_distance(int, int); #define parent_node(node) (node) #define node_to_first_cpu(node) (first_cpu(node_to_cpumask[node])) #define node_to_cpumask(node) (node_to_cpumask[node]) -#define pcibus_to_node(bus) ((long)(bus->sysdata)) +#define pcibus_to_node(bus) ((struct pci_sysdata *)((bus)->sysdata))->node #define pcibus_to_cpumask(bus) node_to_cpumask(pcibus_to_node(bus)); #define numa_node_id() read_pda(nodenumber) diff --git a/include/asm-i386/tsc.h b/include/asm-x86/tsc.h index 62c091ffcccc..6baab30dc2c8 100644 --- a/include/asm-i386/tsc.h +++ b/include/asm-x86/tsc.h @@ -1,13 +1,14 @@ /* - * linux/include/asm-i386/tsc.h - * - * i386 TSC related functions + * x86 TSC related functions */ -#ifndef _ASM_i386_TSC_H -#define _ASM_i386_TSC_H +#ifndef _ASM_X86_TSC_H +#define _ASM_X86_TSC_H #include <asm/processor.h> +#define NS_SCALE 10 /* 2^10, carefully chosen */ +#define US_SCALE 32 /* 2^32, arbitralrily chosen */ + /* * Standard way to access the cycle counter. */ @@ -63,6 +64,7 @@ extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); extern int unsynchronized_tsc(void); extern void init_tsc_clocksource(void); +int check_tsc_unstable(void); /* * Boot-time check whether the TSCs are synchronized across @@ -71,4 +73,8 @@ extern void init_tsc_clocksource(void); extern void check_tsc_sync_source(int cpu); extern void check_tsc_sync_target(void); +#ifdef CONFIG_X86_64 +extern void tsc_calibrate(void); +#endif + #endif diff --git a/include/asm-x86/types.h b/include/asm-x86/types.h new file mode 100644 index 000000000000..a777a9b83974 --- /dev/null +++ b/include/asm-x86/types.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "types_32.h" +# else +# include "types_64.h" +# endif +#else +# ifdef __i386__ +# include "types_32.h" +# else +# include "types_64.h" +# endif +#endif diff --git a/include/asm-i386/types.h b/include/asm-x86/types_32.h index ad0a55bd782f..ad0a55bd782f 100644 --- a/include/asm-i386/types.h +++ b/include/asm-x86/types_32.h diff --git a/include/asm-x86_64/types.h b/include/asm-x86/types_64.h index 2d4491aae281..2d4491aae281 100644 --- a/include/asm-x86_64/types.h +++ b/include/asm-x86/types_64.h diff --git a/include/asm-x86/uaccess.h b/include/asm-x86/uaccess.h new file mode 100644 index 000000000000..9fefd2947e78 --- /dev/null +++ b/include/asm-x86/uaccess.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "uaccess_32.h" +#else +# include "uaccess_64.h" +#endif diff --git a/include/asm-i386/uaccess.h b/include/asm-x86/uaccess_32.h index e2aa5e0d0cc7..d2a4f7be9c2c 100644 --- a/include/asm-i386/uaccess.h +++ b/include/asm-x86/uaccess_32.h @@ -581,7 +581,7 @@ long __must_check __strncpy_from_user(char *dst, * If there is a limit on the length of a valid string, you may wish to * consider using strnlen_user() instead. */ -#define strlen_user(str) strnlen_user(str, ~0UL >> 1) +#define strlen_user(str) strnlen_user(str, LONG_MAX) long strnlen_user(const char __user *str, long n); unsigned long __must_check clear_user(void __user *mem, unsigned long len); diff --git a/include/asm-x86_64/uaccess.h b/include/asm-x86/uaccess_64.h index 9df30b939c4e..f4ce8768ad44 100644 --- a/include/asm-x86_64/uaccess.h +++ b/include/asm-x86/uaccess_64.h @@ -100,7 +100,7 @@ struct exception_table_entry case 8: __get_user_x(8,__ret_gu,__val_gu,ptr); break; \ default: __get_user_bad(); break; \ } \ - (x) = (typeof(*(ptr)))__val_gu; \ + (x) = (__force typeof(*(ptr)))__val_gu; \ __ret_gu; \ }) @@ -192,7 +192,7 @@ struct __large_struct { unsigned long buf[100]; }; int __gu_err; \ unsigned long __gu_val; \ __get_user_size(__gu_val,(ptr),(size),__gu_err); \ - (x) = (typeof(*(ptr)))__gu_val; \ + (x) = (__force typeof(*(ptr)))__gu_val; \ __gu_err; \ }) diff --git a/include/asm-x86/ucontext.h b/include/asm-x86/ucontext.h new file mode 100644 index 000000000000..175c8cb59731 --- /dev/null +++ b/include/asm-x86/ucontext.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "ucontext_32.h" +# else +# include "ucontext_64.h" +# endif +#else +# ifdef __i386__ +# include "ucontext_32.h" +# else +# include "ucontext_64.h" +# endif +#endif diff --git a/include/asm-i386/ucontext.h b/include/asm-x86/ucontext_32.h index b0db36925f55..b0db36925f55 100644 --- a/include/asm-i386/ucontext.h +++ b/include/asm-x86/ucontext_32.h diff --git a/include/asm-x86_64/ucontext.h b/include/asm-x86/ucontext_64.h index 159a3da9e112..159a3da9e112 100644 --- a/include/asm-x86_64/ucontext.h +++ b/include/asm-x86/ucontext_64.h diff --git a/include/asm-x86/unaligned.h b/include/asm-x86/unaligned.h new file mode 100644 index 000000000000..68067150fbcb --- /dev/null +++ b/include/asm-x86/unaligned.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "unaligned_32.h" +#else +# include "unaligned_64.h" +#endif diff --git a/include/asm-i386/unaligned.h b/include/asm-x86/unaligned_32.h index 7acd7957621e..7acd7957621e 100644 --- a/include/asm-i386/unaligned.h +++ b/include/asm-x86/unaligned_32.h diff --git a/include/asm-x86_64/unaligned.h b/include/asm-x86/unaligned_64.h index d4bf78dc6f39..d4bf78dc6f39 100644 --- a/include/asm-x86_64/unaligned.h +++ b/include/asm-x86/unaligned_64.h diff --git a/include/asm-x86/unistd.h b/include/asm-x86/unistd.h new file mode 100644 index 000000000000..2a58ed3e51d8 --- /dev/null +++ b/include/asm-x86/unistd.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "unistd_32.h" +# else +# include "unistd_64.h" +# endif +#else +# ifdef __i386__ +# include "unistd_32.h" +# else +# include "unistd_64.h" +# endif +#endif diff --git a/include/asm-i386/unistd.h b/include/asm-x86/unistd_32.h index e84ace1ec8bf..9b15545eb9b5 100644 --- a/include/asm-i386/unistd.h +++ b/include/asm-x86/unistd_32.h @@ -329,10 +329,11 @@ #define __NR_signalfd 321 #define __NR_timerfd 322 #define __NR_eventfd 323 +#define __NR_fallocate 324 #ifdef __KERNEL__ -#define NR_syscalls 324 +#define NR_syscalls 325 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86/unistd_64.h index 8696f8ad401e..fc4e73f5f1fa 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86/unistd_64.h @@ -630,6 +630,8 @@ __SYSCALL(__NR_signalfd, sys_signalfd) __SYSCALL(__NR_timerfd, sys_timerfd) #define __NR_eventfd 284 __SYSCALL(__NR_eventfd, sys_eventfd) +#define __NR_fallocate 285 +__SYSCALL(__NR_fallocate, sys_fallocate) #ifndef __NO_STUBS #define __ARCH_WANT_OLD_READDIR diff --git a/include/asm-x86/unwind.h b/include/asm-x86/unwind.h new file mode 100644 index 000000000000..7e4d7ad55208 --- /dev/null +++ b/include/asm-x86/unwind.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "unwind_32.h" +#else +# include "unwind_64.h" +#endif diff --git a/include/asm-i386/unwind.h b/include/asm-x86/unwind_32.h index 43c70c3de2f9..43c70c3de2f9 100644 --- a/include/asm-i386/unwind.h +++ b/include/asm-x86/unwind_32.h diff --git a/include/asm-x86_64/unwind.h b/include/asm-x86/unwind_64.h index 02710f6a4560..02710f6a4560 100644 --- a/include/asm-x86_64/unwind.h +++ b/include/asm-x86/unwind_64.h diff --git a/include/asm-x86/user.h b/include/asm-x86/user.h new file mode 100644 index 000000000000..484715abe74a --- /dev/null +++ b/include/asm-x86/user.h @@ -0,0 +1,13 @@ +#ifdef __KERNEL__ +# ifdef CONFIG_X86_32 +# include "user_32.h" +# else +# include "user_64.h" +# endif +#else +# ifdef __i386__ +# include "user_32.h" +# else +# include "user_64.h" +# endif +#endif diff --git a/include/asm-x86_64/user32.h b/include/asm-x86/user32.h index f769872debea..f769872debea 100644 --- a/include/asm-x86_64/user32.h +++ b/include/asm-x86/user32.h diff --git a/include/asm-i386/user.h b/include/asm-x86/user_32.h index 0e85d2a5e33a..0e85d2a5e33a 100644 --- a/include/asm-i386/user.h +++ b/include/asm-x86/user_32.h diff --git a/include/asm-x86_64/user.h b/include/asm-x86/user_64.h index 12785c649ac5..12785c649ac5 100644 --- a/include/asm-x86_64/user.h +++ b/include/asm-x86/user_64.h diff --git a/include/asm-i386/vga.h b/include/asm-x86/vga.h index 0ecf68ac03aa..0ecf68ac03aa 100644 --- a/include/asm-i386/vga.h +++ b/include/asm-x86/vga.h diff --git a/include/asm-x86/vgtod.h b/include/asm-x86/vgtod.h new file mode 100644 index 000000000000..3301f0929342 --- /dev/null +++ b/include/asm-x86/vgtod.h @@ -0,0 +1,29 @@ +#ifndef _ASM_VGTOD_H +#define _ASM_VGTOD_H 1 + +#include <asm/vsyscall.h> +#include <linux/clocksource.h> + +struct vsyscall_gtod_data { + seqlock_t lock; + + /* open coded 'struct timespec' */ + time_t wall_time_sec; + u32 wall_time_nsec; + + int sysctl_enabled; + struct timezone sys_tz; + struct { /* extract of a clocksource struct */ + cycle_t (*vread)(void); + cycle_t cycle_last; + cycle_t mask; + u32 mult; + u32 shift; + } clock; + struct timespec wall_to_monotonic; +}; +extern struct vsyscall_gtod_data __vsyscall_gtod_data +__section_vsyscall_gtod_data; +extern struct vsyscall_gtod_data vsyscall_gtod_data; + +#endif diff --git a/include/asm-i386/vic.h b/include/asm-x86/vic.h index 53100f353612..53100f353612 100644 --- a/include/asm-i386/vic.h +++ b/include/asm-x86/vic.h diff --git a/include/asm-i386/vm86.h b/include/asm-x86/vm86.h index a5edf517b992..a5edf517b992 100644 --- a/include/asm-i386/vm86.h +++ b/include/asm-x86/vm86.h diff --git a/include/asm-i386/vmi.h b/include/asm-x86/vmi.h index eb8bd892c01e..eb8bd892c01e 100644 --- a/include/asm-i386/vmi.h +++ b/include/asm-x86/vmi.h diff --git a/include/asm-i386/vmi_time.h b/include/asm-x86/vmi_time.h index 213930b995cb..478188130328 100644 --- a/include/asm-i386/vmi_time.h +++ b/include/asm-x86/vmi_time.h @@ -49,7 +49,7 @@ extern struct vmi_timer_ops { extern void __init vmi_time_init(void); extern unsigned long vmi_get_wallclock(void); extern int vmi_set_wallclock(unsigned long now); -extern unsigned long long vmi_get_sched_cycles(void); +extern unsigned long long vmi_sched_clock(void); extern unsigned long vmi_cpu_khz(void); #ifdef CONFIG_X86_LOCAL_APIC diff --git a/include/asm-i386/voyager.h b/include/asm-x86/voyager.h index 91a9932937ab..91a9932937ab 100644 --- a/include/asm-i386/voyager.h +++ b/include/asm-x86/voyager.h diff --git a/include/asm-x86_64/vsyscall.h b/include/asm-x86/vsyscall.h index 82b4afe65c91..f01c49f5d108 100644 --- a/include/asm-x86_64/vsyscall.h +++ b/include/asm-x86/vsyscall.h @@ -22,21 +22,19 @@ enum vsyscall_num { /* Definitions for CONFIG_GENERIC_TIME definitions */ #define __section_vsyscall_gtod_data __attribute__ \ ((unused, __section__ (".vsyscall_gtod_data"),aligned(16))) +#define __section_vsyscall_clock __attribute__ \ + ((unused, __section__ (".vsyscall_clock"),aligned(16))) #define __vsyscall_fn __attribute__ ((unused,__section__(".vsyscall_fn"))) #define VGETCPU_RDTSCP 1 #define VGETCPU_LSL 2 -#define hpet_readl(a) readl((const void __iomem *)fix_to_virt(FIX_HPET_BASE) + a) -#define hpet_writel(d,a) writel(d, (void __iomem *)fix_to_virt(FIX_HPET_BASE) + a) - extern int __vgetcpu_mode; extern volatile unsigned long __jiffies; /* kernel space (writeable) */ extern int vgetcpu_mode; extern struct timezone sys_tz; -extern struct vsyscall_gtod_data_t vsyscall_gtod_data; #endif /* __KERNEL__ */ diff --git a/include/asm-x86_64/vsyscall32.h b/include/asm-x86/vsyscall32.h index c631c082f8f7..c631c082f8f7 100644 --- a/include/asm-x86_64/vsyscall32.h +++ b/include/asm-x86/vsyscall32.h diff --git a/include/asm-x86/xen/hypercall.h b/include/asm-x86/xen/hypercall.h new file mode 100644 index 000000000000..bc0ee7d961ca --- /dev/null +++ b/include/asm-x86/xen/hypercall.h @@ -0,0 +1,413 @@ +/****************************************************************************** + * hypercall.h + * + * Linux-specific hypervisor handling. + * + * Copyright (c) 2002-2004, K A Fraser + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef __HYPERCALL_H__ +#define __HYPERCALL_H__ + +#include <linux/errno.h> +#include <linux/string.h> + +#include <xen/interface/xen.h> +#include <xen/interface/sched.h> +#include <xen/interface/physdev.h> + +extern struct { char _entry[32]; } hypercall_page[]; + +#define _hypercall0(type, name) \ +({ \ + long __res; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res) \ + : [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +#define _hypercall1(type, name, a1) \ +({ \ + long __res, __ign1; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res), "=b" (__ign1) \ + : "1" ((long)(a1)), \ + [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +#define _hypercall2(type, name, a1, a2) \ +({ \ + long __res, __ign1, __ign2; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res), "=b" (__ign1), "=c" (__ign2) \ + : "1" ((long)(a1)), "2" ((long)(a2)), \ + [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +#define _hypercall3(type, name, a1, a2, a3) \ +({ \ + long __res, __ign1, __ign2, __ign3; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \ + "=d" (__ign3) \ + : "1" ((long)(a1)), "2" ((long)(a2)), \ + "3" ((long)(a3)), \ + [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +#define _hypercall4(type, name, a1, a2, a3, a4) \ +({ \ + long __res, __ign1, __ign2, __ign3, __ign4; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \ + "=d" (__ign3), "=S" (__ign4) \ + : "1" ((long)(a1)), "2" ((long)(a2)), \ + "3" ((long)(a3)), "4" ((long)(a4)), \ + [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +#define _hypercall5(type, name, a1, a2, a3, a4, a5) \ +({ \ + long __res, __ign1, __ign2, __ign3, __ign4, __ign5; \ + asm volatile ( \ + "call %[call]" \ + : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \ + "=d" (__ign3), "=S" (__ign4), "=D" (__ign5) \ + : "1" ((long)(a1)), "2" ((long)(a2)), \ + "3" ((long)(a3)), "4" ((long)(a4)), \ + "5" ((long)(a5)), \ + [call] "m" (hypercall_page[__HYPERVISOR_##name]) \ + : "memory" ); \ + (type)__res; \ +}) + +static inline int +HYPERVISOR_set_trap_table(struct trap_info *table) +{ + return _hypercall1(int, set_trap_table, table); +} + +static inline int +HYPERVISOR_mmu_update(struct mmu_update *req, int count, + int *success_count, domid_t domid) +{ + return _hypercall4(int, mmu_update, req, count, success_count, domid); +} + +static inline int +HYPERVISOR_mmuext_op(struct mmuext_op *op, int count, + int *success_count, domid_t domid) +{ + return _hypercall4(int, mmuext_op, op, count, success_count, domid); +} + +static inline int +HYPERVISOR_set_gdt(unsigned long *frame_list, int entries) +{ + return _hypercall2(int, set_gdt, frame_list, entries); +} + +static inline int +HYPERVISOR_stack_switch(unsigned long ss, unsigned long esp) +{ + return _hypercall2(int, stack_switch, ss, esp); +} + +static inline int +HYPERVISOR_set_callbacks(unsigned long event_selector, + unsigned long event_address, + unsigned long failsafe_selector, + unsigned long failsafe_address) +{ + return _hypercall4(int, set_callbacks, + event_selector, event_address, + failsafe_selector, failsafe_address); +} + +static inline int +HYPERVISOR_fpu_taskswitch(int set) +{ + return _hypercall1(int, fpu_taskswitch, set); +} + +static inline int +HYPERVISOR_sched_op(int cmd, unsigned long arg) +{ + return _hypercall2(int, sched_op, cmd, arg); +} + +static inline long +HYPERVISOR_set_timer_op(u64 timeout) +{ + unsigned long timeout_hi = (unsigned long)(timeout>>32); + unsigned long timeout_lo = (unsigned long)timeout; + return _hypercall2(long, set_timer_op, timeout_lo, timeout_hi); +} + +static inline int +HYPERVISOR_set_debugreg(int reg, unsigned long value) +{ + return _hypercall2(int, set_debugreg, reg, value); +} + +static inline unsigned long +HYPERVISOR_get_debugreg(int reg) +{ + return _hypercall1(unsigned long, get_debugreg, reg); +} + +static inline int +HYPERVISOR_update_descriptor(u64 ma, u64 desc) +{ + return _hypercall4(int, update_descriptor, ma, ma>>32, desc, desc>>32); +} + +static inline int +HYPERVISOR_memory_op(unsigned int cmd, void *arg) +{ + return _hypercall2(int, memory_op, cmd, arg); +} + +static inline int +HYPERVISOR_multicall(void *call_list, int nr_calls) +{ + return _hypercall2(int, multicall, call_list, nr_calls); +} + +static inline int +HYPERVISOR_update_va_mapping(unsigned long va, pte_t new_val, + unsigned long flags) +{ + unsigned long pte_hi = 0; +#ifdef CONFIG_X86_PAE + pte_hi = new_val.pte_high; +#endif + return _hypercall4(int, update_va_mapping, va, + new_val.pte_low, pte_hi, flags); +} + +static inline int +HYPERVISOR_event_channel_op(int cmd, void *arg) +{ + int rc = _hypercall2(int, event_channel_op, cmd, arg); + if (unlikely(rc == -ENOSYS)) { + struct evtchn_op op; + op.cmd = cmd; + memcpy(&op.u, arg, sizeof(op.u)); + rc = _hypercall1(int, event_channel_op_compat, &op); + memcpy(arg, &op.u, sizeof(op.u)); + } + return rc; +} + +static inline int +HYPERVISOR_xen_version(int cmd, void *arg) +{ + return _hypercall2(int, xen_version, cmd, arg); +} + +static inline int +HYPERVISOR_console_io(int cmd, int count, char *str) +{ + return _hypercall3(int, console_io, cmd, count, str); +} + +static inline int +HYPERVISOR_physdev_op(int cmd, void *arg) +{ + int rc = _hypercall2(int, physdev_op, cmd, arg); + if (unlikely(rc == -ENOSYS)) { + struct physdev_op op; + op.cmd = cmd; + memcpy(&op.u, arg, sizeof(op.u)); + rc = _hypercall1(int, physdev_op_compat, &op); + memcpy(arg, &op.u, sizeof(op.u)); + } + return rc; +} + +static inline int +HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count) +{ + return _hypercall3(int, grant_table_op, cmd, uop, count); +} + +static inline int +HYPERVISOR_update_va_mapping_otherdomain(unsigned long va, pte_t new_val, + unsigned long flags, domid_t domid) +{ + unsigned long pte_hi = 0; +#ifdef CONFIG_X86_PAE + pte_hi = new_val.pte_high; +#endif + return _hypercall5(int, update_va_mapping_otherdomain, va, + new_val.pte_low, pte_hi, flags, domid); +} + +static inline int +HYPERVISOR_vm_assist(unsigned int cmd, unsigned int type) +{ + return _hypercall2(int, vm_assist, cmd, type); +} + +static inline int +HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args) +{ + return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args); +} + +static inline int +HYPERVISOR_suspend(unsigned long srec) +{ + return _hypercall3(int, sched_op, SCHEDOP_shutdown, + SHUTDOWN_suspend, srec); +} + +static inline int +HYPERVISOR_nmi_op(unsigned long op, unsigned long arg) +{ + return _hypercall2(int, nmi_op, op, arg); +} + +static inline void +MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, + pte_t new_val, unsigned long flags) +{ + mcl->op = __HYPERVISOR_update_va_mapping; + mcl->args[0] = va; +#ifdef CONFIG_X86_PAE + mcl->args[1] = new_val.pte_low; + mcl->args[2] = new_val.pte_high; +#else + mcl->args[1] = new_val.pte_low; + mcl->args[2] = 0; +#endif + mcl->args[3] = flags; +} + +static inline void +MULTI_grant_table_op(struct multicall_entry *mcl, unsigned int cmd, + void *uop, unsigned int count) +{ + mcl->op = __HYPERVISOR_grant_table_op; + mcl->args[0] = cmd; + mcl->args[1] = (unsigned long)uop; + mcl->args[2] = count; +} + +static inline void +MULTI_update_va_mapping_otherdomain(struct multicall_entry *mcl, unsigned long va, + pte_t new_val, unsigned long flags, + domid_t domid) +{ + mcl->op = __HYPERVISOR_update_va_mapping_otherdomain; + mcl->args[0] = va; +#ifdef CONFIG_X86_PAE + mcl->args[1] = new_val.pte_low; + mcl->args[2] = new_val.pte_high; +#else + mcl->args[1] = new_val.pte_low; + mcl->args[2] = 0; +#endif + mcl->args[3] = flags; + mcl->args[4] = domid; +} + +static inline void +MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr, + struct desc_struct desc) +{ + mcl->op = __HYPERVISOR_update_descriptor; + mcl->args[0] = maddr; + mcl->args[1] = maddr >> 32; + mcl->args[2] = desc.a; + mcl->args[3] = desc.b; +} + +static inline void +MULTI_memory_op(struct multicall_entry *mcl, unsigned int cmd, void *arg) +{ + mcl->op = __HYPERVISOR_memory_op; + mcl->args[0] = cmd; + mcl->args[1] = (unsigned long)arg; +} + +static inline void +MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req, + int count, int *success_count, domid_t domid) +{ + mcl->op = __HYPERVISOR_mmu_update; + mcl->args[0] = (unsigned long)req; + mcl->args[1] = count; + mcl->args[2] = (unsigned long)success_count; + mcl->args[3] = domid; +} + +static inline void +MULTI_mmuext_op(struct multicall_entry *mcl, struct mmuext_op *op, int count, + int *success_count, domid_t domid) +{ + mcl->op = __HYPERVISOR_mmuext_op; + mcl->args[0] = (unsigned long)op; + mcl->args[1] = count; + mcl->args[2] = (unsigned long)success_count; + mcl->args[3] = domid; +} + +static inline void +MULTI_set_gdt(struct multicall_entry *mcl, unsigned long *frames, int entries) +{ + mcl->op = __HYPERVISOR_set_gdt; + mcl->args[0] = (unsigned long)frames; + mcl->args[1] = entries; +} + +static inline void +MULTI_stack_switch(struct multicall_entry *mcl, + unsigned long ss, unsigned long esp) +{ + mcl->op = __HYPERVISOR_stack_switch; + mcl->args[0] = ss; + mcl->args[1] = esp; +} + +#endif /* __HYPERCALL_H__ */ diff --git a/include/asm-x86/xen/hypervisor.h b/include/asm-x86/xen/hypervisor.h new file mode 100644 index 000000000000..8e15dd28c91f --- /dev/null +++ b/include/asm-x86/xen/hypervisor.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * hypervisor.h + * + * Linux-specific hypervisor handling. + * + * Copyright (c) 2002-2004, K A Fraser + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef __HYPERVISOR_H__ +#define __HYPERVISOR_H__ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/version.h> + +#include <xen/interface/xen.h> +#include <xen/interface/version.h> + +#include <asm/ptrace.h> +#include <asm/page.h> +#include <asm/desc.h> +#if defined(__i386__) +# ifdef CONFIG_X86_PAE +# include <asm-generic/pgtable-nopud.h> +# else +# include <asm-generic/pgtable-nopmd.h> +# endif +#endif +#include <asm/xen/hypercall.h> + +/* arch/i386/kernel/setup.c */ +extern struct shared_info *HYPERVISOR_shared_info; +extern struct start_info *xen_start_info; +#define is_initial_xendomain() (xen_start_info->flags & SIF_INITDOMAIN) + +/* arch/i386/mach-xen/evtchn.c */ +/* Force a proper event-channel callback from Xen. */ +extern void force_evtchn_callback(void); + +/* Turn jiffies into Xen system time. */ +u64 jiffies_to_st(unsigned long jiffies); + + +#define MULTI_UVMFLAGS_INDEX 3 +#define MULTI_UVMDOMID_INDEX 4 + +#define is_running_on_xen() (xen_start_info ? 1 : 0) + +#endif /* __HYPERVISOR_H__ */ diff --git a/include/asm-x86/xen/interface.h b/include/asm-x86/xen/interface.h new file mode 100644 index 000000000000..165c3968e138 --- /dev/null +++ b/include/asm-x86/xen/interface.h @@ -0,0 +1,188 @@ +/****************************************************************************** + * arch-x86_32.h + * + * Guest OS interface to x86 32-bit Xen. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_ARCH_X86_32_H__ +#define __XEN_PUBLIC_ARCH_X86_32_H__ + +#ifdef __XEN__ +#define __DEFINE_GUEST_HANDLE(name, type) \ + typedef struct { type *p; } __guest_handle_ ## name +#else +#define __DEFINE_GUEST_HANDLE(name, type) \ + typedef type * __guest_handle_ ## name +#endif + +#define DEFINE_GUEST_HANDLE_STRUCT(name) \ + __DEFINE_GUEST_HANDLE(name, struct name) +#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name) +#define GUEST_HANDLE(name) __guest_handle_ ## name + +#ifndef __ASSEMBLY__ +/* Guest handles for primitive C types. */ +__DEFINE_GUEST_HANDLE(uchar, unsigned char); +__DEFINE_GUEST_HANDLE(uint, unsigned int); +__DEFINE_GUEST_HANDLE(ulong, unsigned long); +DEFINE_GUEST_HANDLE(char); +DEFINE_GUEST_HANDLE(int); +DEFINE_GUEST_HANDLE(long); +DEFINE_GUEST_HANDLE(void); +#endif + +/* + * SEGMENT DESCRIPTOR TABLES + */ +/* + * A number of GDT entries are reserved by Xen. These are not situated at the + * start of the GDT because some stupid OSes export hard-coded selector values + * in their ABI. These hard-coded values are always near the start of the GDT, + * so Xen places itself out of the way, at the far end of the GDT. + */ +#define FIRST_RESERVED_GDT_PAGE 14 +#define FIRST_RESERVED_GDT_BYTE (FIRST_RESERVED_GDT_PAGE * 4096) +#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8) + +/* + * These flat segments are in the Xen-private section of every GDT. Since these + * are also present in the initial GDT, many OSes will be able to avoid + * installing their own GDT. + */ +#define FLAT_RING1_CS 0xe019 /* GDT index 259 */ +#define FLAT_RING1_DS 0xe021 /* GDT index 260 */ +#define FLAT_RING1_SS 0xe021 /* GDT index 260 */ +#define FLAT_RING3_CS 0xe02b /* GDT index 261 */ +#define FLAT_RING3_DS 0xe033 /* GDT index 262 */ +#define FLAT_RING3_SS 0xe033 /* GDT index 262 */ + +#define FLAT_KERNEL_CS FLAT_RING1_CS +#define FLAT_KERNEL_DS FLAT_RING1_DS +#define FLAT_KERNEL_SS FLAT_RING1_SS +#define FLAT_USER_CS FLAT_RING3_CS +#define FLAT_USER_DS FLAT_RING3_DS +#define FLAT_USER_SS FLAT_RING3_SS + +/* And the trap vector is... */ +#define TRAP_INSTR "int $0x82" + +/* + * Virtual addresses beyond this are not modifiable by guest OSes. The + * machine->physical mapping table starts at this address, read-only. + */ +#ifdef CONFIG_X86_PAE +#define __HYPERVISOR_VIRT_START 0xF5800000 +#else +#define __HYPERVISOR_VIRT_START 0xFC000000 +#endif + +#ifndef HYPERVISOR_VIRT_START +#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START) +#endif + +#ifndef machine_to_phys_mapping +#define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START) +#endif + +/* Maximum number of virtual CPUs in multi-processor guests. */ +#define MAX_VIRT_CPUS 32 + +#ifndef __ASSEMBLY__ + +/* + * Send an array of these to HYPERVISOR_set_trap_table() + */ +#define TI_GET_DPL(_ti) ((_ti)->flags & 3) +#define TI_GET_IF(_ti) ((_ti)->flags & 4) +#define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl)) +#define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2)) + +struct trap_info { + uint8_t vector; /* exception vector */ + uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */ + uint16_t cs; /* code selector */ + unsigned long address; /* code offset */ +}; +DEFINE_GUEST_HANDLE_STRUCT(trap_info); + +struct cpu_user_regs { + uint32_t ebx; + uint32_t ecx; + uint32_t edx; + uint32_t esi; + uint32_t edi; + uint32_t ebp; + uint32_t eax; + uint16_t error_code; /* private */ + uint16_t entry_vector; /* private */ + uint32_t eip; + uint16_t cs; + uint8_t saved_upcall_mask; + uint8_t _pad0; + uint32_t eflags; /* eflags.IF == !saved_upcall_mask */ + uint32_t esp; + uint16_t ss, _pad1; + uint16_t es, _pad2; + uint16_t ds, _pad3; + uint16_t fs, _pad4; + uint16_t gs, _pad5; +}; +DEFINE_GUEST_HANDLE_STRUCT(cpu_user_regs); + +typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */ + +/* + * The following is all CPU context. Note that the fpu_ctxt block is filled + * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used. + */ +struct vcpu_guest_context { + /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */ + struct { char x[512]; } fpu_ctxt; /* User-level FPU registers */ +#define VGCF_I387_VALID (1<<0) +#define VGCF_HVM_GUEST (1<<1) +#define VGCF_IN_KERNEL (1<<2) + unsigned long flags; /* VGCF_* flags */ + struct cpu_user_regs user_regs; /* User-level CPU registers */ + struct trap_info trap_ctxt[256]; /* Virtual IDT */ + unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */ + unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */ + unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */ + unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */ + unsigned long debugreg[8]; /* DB0-DB7 (debug registers) */ + unsigned long event_callback_cs; /* CS:EIP of event callback */ + unsigned long event_callback_eip; + unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */ + unsigned long failsafe_callback_eip; + unsigned long vm_assist; /* VMASST_TYPE_* bitmap */ +}; +DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context); + +struct arch_shared_info { + unsigned long max_pfn; /* max pfn that appears in table */ + /* Frame containing list of mfns containing list of mfns containing p2m. */ + unsigned long pfn_to_mfn_frame_list_list; + unsigned long nmi_reason; +}; + +struct arch_vcpu_info { + unsigned long cr2; + unsigned long pad[5]; /* sizeof(struct vcpu_info) == 64 */ +}; + +#endif /* !__ASSEMBLY__ */ + +/* + * Prefix forces emulation of some non-trapping instructions. + * Currently only CPUID. + */ +#ifdef __ASSEMBLY__ +#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ; +#define XEN_CPUID XEN_EMULATE_PREFIX cpuid +#else +#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; " +#define XEN_CPUID XEN_EMULATE_PREFIX "cpuid" +#endif + +#endif diff --git a/include/asm-x86/xor.h b/include/asm-x86/xor.h new file mode 100644 index 000000000000..11b3bb86e17b --- /dev/null +++ b/include/asm-x86/xor.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "xor_32.h" +#else +# include "xor_64.h" +#endif diff --git a/include/asm-i386/xor.h b/include/asm-x86/xor_32.h index 23c86cef3b25..23c86cef3b25 100644 --- a/include/asm-i386/xor.h +++ b/include/asm-x86/xor_32.h diff --git a/include/asm-x86_64/xor.h b/include/asm-x86/xor_64.h index f942fcc21831..f942fcc21831 100644 --- a/include/asm-x86_64/xor.h +++ b/include/asm-x86/xor_64.h diff --git a/include/asm-x86_64/8253pit.h b/include/asm-x86_64/8253pit.h deleted file mode 100644 index 285f78488ccb..000000000000 --- a/include/asm-x86_64/8253pit.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * 8253/8254 Programmable Interval Timer - */ - -#ifndef _8253PIT_H -#define _8253PIT_H - -#define PIT_TICK_RATE 1193182UL - -#endif diff --git a/include/asm-x86_64/Kbuild b/include/asm-x86_64/Kbuild deleted file mode 100644 index 75a2deffca68..000000000000 --- a/include/asm-x86_64/Kbuild +++ /dev/null @@ -1,21 +0,0 @@ -include include/asm-generic/Kbuild.asm - -ALTARCH := i386 -ARCHDEF := defined __x86_64__ -ALTARCHDEF := defined __i386__ - -header-y += boot.h -header-y += bootsetup.h -header-y += debugreg.h -header-y += ldt.h -header-y += msr-index.h -header-y += prctl.h -header-y += ptrace-abi.h -header-y += sigcontext32.h -header-y += ucontext.h -header-y += vsyscall32.h - -unifdef-y += mce.h -unifdef-y += msr.h -unifdef-y += mtrr.h -unifdef-y += vsyscall.h diff --git a/include/asm-x86_64/boot.h b/include/asm-x86_64/boot.h deleted file mode 100644 index 3c46cea8db7f..000000000000 --- a/include/asm-x86_64/boot.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/boot.h> diff --git a/include/asm-x86_64/bootparam.h b/include/asm-x86_64/bootparam.h deleted file mode 100644 index aa82e5238d82..000000000000 --- a/include/asm-x86_64/bootparam.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/bootparam.h> diff --git a/include/asm-x86_64/cpu.h b/include/asm-x86_64/cpu.h deleted file mode 100644 index 8eea076525a4..000000000000 --- a/include/asm-x86_64/cpu.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/cpu.h> diff --git a/include/asm-x86_64/div64.h b/include/asm-x86_64/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-x86_64/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/div64.h> diff --git a/include/asm-x86_64/emergency-restart.h b/include/asm-x86_64/emergency-restart.h deleted file mode 100644 index 680c39563345..000000000000 --- a/include/asm-x86_64/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -extern void machine_emergency_restart(void); - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-x86_64/fcntl.h b/include/asm-x86_64/fcntl.h deleted file mode 100644 index 46ab12db5739..000000000000 --- a/include/asm-x86_64/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/fcntl.h> diff --git a/include/asm-x86_64/hpet.h b/include/asm-x86_64/hpet.h deleted file mode 100644 index 59a66f084611..000000000000 --- a/include/asm-x86_64/hpet.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef _ASM_X8664_HPET_H -#define _ASM_X8664_HPET_H 1 - -/* - * Documentation on HPET can be found at: - * http://www.intel.com/ial/home/sp/pcmmspec.htm - * ftp://download.intel.com/ial/home/sp/mmts098.pdf - */ - -#define HPET_MMAP_SIZE 1024 - -#define HPET_ID 0x000 -#define HPET_PERIOD 0x004 -#define HPET_CFG 0x010 -#define HPET_STATUS 0x020 -#define HPET_COUNTER 0x0f0 -#define HPET_Tn_OFFSET 0x20 -#define HPET_Tn_CFG(n) (0x100 + (n) * HPET_Tn_OFFSET) -#define HPET_Tn_ROUTE(n) (0x104 + (n) * HPET_Tn_OFFSET) -#define HPET_Tn_CMP(n) (0x108 + (n) * HPET_Tn_OFFSET) -#define HPET_T0_CFG HPET_Tn_CFG(0) -#define HPET_T0_CMP HPET_Tn_CMP(0) -#define HPET_T1_CFG HPET_Tn_CFG(1) -#define HPET_T1_CMP HPET_Tn_CMP(1) - -#define HPET_ID_VENDOR 0xffff0000 -#define HPET_ID_LEGSUP 0x00008000 -#define HPET_ID_64BIT 0x00002000 -#define HPET_ID_NUMBER 0x00001f00 -#define HPET_ID_REV 0x000000ff -#define HPET_ID_NUMBER_SHIFT 8 - -#define HPET_ID_VENDOR_SHIFT 16 -#define HPET_ID_VENDOR_8086 0x8086 - -#define HPET_CFG_ENABLE 0x001 -#define HPET_CFG_LEGACY 0x002 -#define HPET_LEGACY_8254 2 -#define HPET_LEGACY_RTC 8 - -#define HPET_TN_LEVEL 0x0002 -#define HPET_TN_ENABLE 0x0004 -#define HPET_TN_PERIODIC 0x0008 -#define HPET_TN_PERIODIC_CAP 0x0010 -#define HPET_TN_64BIT_CAP 0x0020 -#define HPET_TN_SETVAL 0x0040 -#define HPET_TN_32BIT 0x0100 -#define HPET_TN_ROUTE 0x3e00 -#define HPET_TN_FSB 0x4000 -#define HPET_TN_FSB_CAP 0x8000 - -#define HPET_TN_ROUTE_SHIFT 9 - -#define HPET_TICK_RATE (HZ * 100000UL) - -extern int is_hpet_enabled(void); -extern int hpet_rtc_timer_init(void); -extern int apic_is_clustered_box(void); -extern int hpet_arch_init(void); -extern int hpet_timer_stop_set_go(unsigned long tick); -extern int hpet_reenable(void); -extern unsigned int hpet_calibrate_tsc(void); - -extern int hpet_use_timer; -extern unsigned long hpet_address; -extern unsigned long hpet_period; -extern unsigned long hpet_tick; - -#ifdef CONFIG_HPET_EMULATE_RTC -extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask); -extern int hpet_set_rtc_irq_bit(unsigned long bit_mask); -extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec); -extern int hpet_set_periodic_freq(unsigned long freq); -extern int hpet_rtc_dropped_irq(void); -extern int hpet_rtc_timer_init(void); -#endif /* CONFIG_HPET_EMULATE_RTC */ - -#endif diff --git a/include/asm-x86_64/hypertransport.h b/include/asm-x86_64/hypertransport.h deleted file mode 100644 index c16c6ff4bdd7..000000000000 --- a/include/asm-x86_64/hypertransport.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef ASM_HYPERTRANSPORT_H -#define ASM_HYPERTRANSPORT_H - -/* - * Constants for x86 Hypertransport Interrupts. - */ - -#define HT_IRQ_LOW_BASE 0xf8000000 - -#define HT_IRQ_LOW_VECTOR_SHIFT 16 -#define HT_IRQ_LOW_VECTOR_MASK 0x00ff0000 -#define HT_IRQ_LOW_VECTOR(v) (((v) << HT_IRQ_LOW_VECTOR_SHIFT) & HT_IRQ_LOW_VECTOR_MASK) - -#define HT_IRQ_LOW_DEST_ID_SHIFT 8 -#define HT_IRQ_LOW_DEST_ID_MASK 0x0000ff00 -#define HT_IRQ_LOW_DEST_ID(v) (((v) << HT_IRQ_LOW_DEST_ID_SHIFT) & HT_IRQ_LOW_DEST_ID_MASK) - -#define HT_IRQ_LOW_DM_PHYSICAL 0x0000000 -#define HT_IRQ_LOW_DM_LOGICAL 0x0000040 - -#define HT_IRQ_LOW_RQEOI_EDGE 0x0000000 -#define HT_IRQ_LOW_RQEOI_LEVEL 0x0000020 - - -#define HT_IRQ_LOW_MT_FIXED 0x0000000 -#define HT_IRQ_LOW_MT_ARBITRATED 0x0000004 -#define HT_IRQ_LOW_MT_SMI 0x0000008 -#define HT_IRQ_LOW_MT_NMI 0x000000c -#define HT_IRQ_LOW_MT_INIT 0x0000010 -#define HT_IRQ_LOW_MT_STARTUP 0x0000014 -#define HT_IRQ_LOW_MT_EXTINT 0x0000018 -#define HT_IRQ_LOW_MT_LINT1 0x000008c -#define HT_IRQ_LOW_MT_LINT0 0x0000098 - -#define HT_IRQ_LOW_IRQ_MASKED 0x0000001 - - -#define HT_IRQ_HIGH_DEST_ID_SHIFT 0 -#define HT_IRQ_HIGH_DEST_ID_MASK 0x00ffffff -#define HT_IRQ_HIGH_DEST_ID(v) ((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK) - -#endif /* ASM_HYPERTRANSPORT_H */ diff --git a/include/asm-x86_64/ide.h b/include/asm-x86_64/ide.h deleted file mode 100644 index 4cef0ef61878..000000000000 --- a/include/asm-x86_64/ide.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/ide.h> diff --git a/include/asm-x86_64/ioctl.h b/include/asm-x86_64/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-x86_64/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ioctl.h> diff --git a/include/asm-x86_64/msidef.h b/include/asm-x86_64/msidef.h deleted file mode 100644 index 5b8acddb70fb..000000000000 --- a/include/asm-x86_64/msidef.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef ASM_MSIDEF_H -#define ASM_MSIDEF_H - -/* - * Constants for Intel APIC based MSI messages. - */ - -/* - * Shifts for MSI data - */ - -#define MSI_DATA_VECTOR_SHIFT 0 -#define MSI_DATA_VECTOR_MASK 0x000000ff -#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK) - -#define MSI_DATA_DELIVERY_MODE_SHIFT 8 -#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) -#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) - -#define MSI_DATA_LEVEL_SHIFT 14 -#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) -#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) - -#define MSI_DATA_TRIGGER_SHIFT 15 -#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) -#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) - -/* - * Shift/mask fields for msi address - */ - -#define MSI_ADDR_BASE_HI 0 -#define MSI_ADDR_BASE_LO 0xfee00000 - -#define MSI_ADDR_DEST_MODE_SHIFT 2 -#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) -#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) - -#define MSI_ADDR_REDIRECTION_SHIFT 3 -#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) /* dedicated cpu */ -#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) /* lowest priority */ - -#define MSI_ADDR_DEST_ID_SHIFT 12 -#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 -#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK) - -#endif /* ASM_MSIDEF_H */ diff --git a/include/asm-x86_64/msr-index.h b/include/asm-x86_64/msr-index.h deleted file mode 100644 index d77a63f1ddf2..000000000000 --- a/include/asm-x86_64/msr-index.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/msr-index.h> diff --git a/include/asm-x86_64/node.h b/include/asm-x86_64/node.h deleted file mode 100644 index 0ee6f88db048..000000000000 --- a/include/asm-x86_64/node.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/node.h> diff --git a/include/asm-x86_64/poll.h b/include/asm-x86_64/poll.h deleted file mode 100644 index c98509d3149e..000000000000 --- a/include/asm-x86_64/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/poll.h> diff --git a/include/asm-x86_64/processor-flags.h b/include/asm-x86_64/processor-flags.h deleted file mode 100644 index ec99a57b2c6a..000000000000 --- a/include/asm-x86_64/processor-flags.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/processor-flags.h> diff --git a/include/asm-x86_64/serial.h b/include/asm-x86_64/serial.h deleted file mode 100644 index 8ebd765c674a..000000000000 --- a/include/asm-x86_64/serial.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * include/asm-x86_64/serial.h - */ - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD ( 1843200 / 16 ) diff --git a/include/asm-x86_64/socket.h b/include/asm-x86_64/socket.h deleted file mode 100644 index 90af60cf3c0e..000000000000 --- a/include/asm-x86_64/socket.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -#include <asm/sockios.h> - -/* For setsockopt(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#endif /* _ASM_SOCKET_H */ diff --git a/include/asm-x86_64/spinlock_types.h b/include/asm-x86_64/spinlock_types.h deleted file mode 100644 index 4da9345c1500..000000000000 --- a/include/asm-x86_64/spinlock_types.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __ASM_SPINLOCK_TYPES_H -#define __ASM_SPINLOCK_TYPES_H - -#ifndef __LINUX_SPINLOCK_TYPES_H -# error "please don't include this file directly" -#endif - -typedef struct { - unsigned int slock; -} raw_spinlock_t; - -#define __RAW_SPIN_LOCK_UNLOCKED { 1 } - -typedef struct { - unsigned int lock; -} raw_rwlock_t; - -#define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } - -#endif diff --git a/include/asm-x86_64/therm_throt.h b/include/asm-x86_64/therm_throt.h deleted file mode 100644 index 5aac059007ba..000000000000 --- a/include/asm-x86_64/therm_throt.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/therm_throt.h> diff --git a/include/asm-x86_64/timex.h b/include/asm-x86_64/timex.h deleted file mode 100644 index f6527e1b6c1c..000000000000 --- a/include/asm-x86_64/timex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-x86_64/timex.h - * - * x86-64 architecture timex specifications - */ -#ifndef _ASMx8664_TIMEX_H -#define _ASMx8664_TIMEX_H - -#include <asm/8253pit.h> -#include <asm/msr.h> -#include <asm/vsyscall.h> -#include <asm/hpet.h> -#include <asm/system.h> -#include <asm/processor.h> -#include <asm/tsc.h> -#include <linux/compiler.h> - -#define CLOCK_TICK_RATE PIT_TICK_RATE /* Underlying HZ */ - -extern int read_current_timer(unsigned long *timer_value); -#define ARCH_HAS_READ_CURRENT_TIMER 1 - -#define USEC_PER_TICK (USEC_PER_SEC / HZ) -#define NSEC_PER_TICK (NSEC_PER_SEC / HZ) -#define FSEC_PER_TICK (FSEC_PER_SEC / HZ) - -#define NS_SCALE 10 /* 2^10, carefully chosen */ -#define US_SCALE 32 /* 2^32, arbitralrily chosen */ - -extern void mark_tsc_unstable(char *msg); -extern void set_cyc2ns_scale(unsigned long khz); -#endif diff --git a/include/asm-x86_64/tsc.h b/include/asm-x86_64/tsc.h deleted file mode 100644 index d66ba6ef25f6..000000000000 --- a/include/asm-x86_64/tsc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-i386/tsc.h> diff --git a/include/asm-x86_64/vga.h b/include/asm-x86_64/vga.h deleted file mode 100644 index 0ecf68ac03aa..000000000000 --- a/include/asm-x86_64/vga.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Access to VGA videoram - * - * (c) 1998 Martin Mares <mj@ucw.cz> - */ - -#ifndef _LINUX_ASM_VGA_H_ -#define _LINUX_ASM_VGA_H_ - -/* - * On the PC, we can just recalculate addresses and then - * access the videoram directly without any black magic. - */ - -#define VGA_MAP_MEM(x,s) (unsigned long)phys_to_virt(x) - -#define vga_readb(x) (*(x)) -#define vga_writeb(x,y) (*(y) = (x)) - -#endif diff --git a/include/asm-xtensa/a.out.h b/include/asm-xtensa/a.out.h index ffc4dcfd6ac1..05a2f67c6768 100644 --- a/include/asm-xtensa/a.out.h +++ b/include/asm-xtensa/a.out.h @@ -17,6 +17,7 @@ /* Note: the kernel needs the a.out definitions, even if only ELF is used. */ #define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP struct exec { diff --git a/include/asm-xtensa/bugs.h b/include/asm-xtensa/bugs.h index c42285320133..69b29d198249 100644 --- a/include/asm-xtensa/bugs.h +++ b/include/asm-xtensa/bugs.h @@ -13,10 +13,6 @@ #ifndef _XTENSA_BUGS_H #define _XTENSA_BUGS_H -#include <asm/processor.h> - -static void __init check_bugs(void) -{ -} +static void check_bugs(void) { } #endif /* _XTENSA_BUGS_H */ diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h index 1c4a78f29ae2..3bba2a540cf0 100644 --- a/include/asm-xtensa/cache.h +++ b/include/asm-xtensa/cache.h @@ -19,6 +19,15 @@ #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) +#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) +#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) + +/* Maximum cache size per way. */ +#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE +# define CACHE_WAY_SIZE DCACHE_WAY_SIZE +#else +# define CACHE_WAY_SIZE ICACHE_WAY_SIZE +#endif #endif /* _XTENSA_CACHE_H */ diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h index 22ef901b7845..b773c57e75a5 100644 --- a/include/asm-xtensa/cacheflush.h +++ b/include/asm-xtensa/cacheflush.h @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * (C) 2001 - 2006 Tensilica Inc. + * (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_CACHEFLUSH_H @@ -18,10 +18,7 @@ #include <asm/page.h> /* - * flush and invalidate data cache, invalidate instruction cache: - * - * __flush_invalidate_cache_all() - * __flush_invalidate_cache_range(from,sze) + * Lo-level routines for cache flushing. * * invalidate data or instruction cache: * @@ -40,26 +37,39 @@ * __flush_invalidate_dcache_all() * __flush_invalidate_dcache_page(adr) * __flush_invalidate_dcache_range(from,size) + * + * specials for cache aliasing: + * + * __flush_invalidate_dcache_page_alias(vaddr,paddr) + * __invalidate_icache_page_alias(vaddr,paddr) */ -extern void __flush_invalidate_cache_all(void); -extern void __flush_invalidate_cache_range(unsigned long, unsigned long); -extern void __flush_invalidate_dcache_all(void); +extern void __invalidate_dcache_all(void); extern void __invalidate_icache_all(void); - extern void __invalidate_dcache_page(unsigned long); extern void __invalidate_icache_page(unsigned long); extern void __invalidate_icache_range(unsigned long, unsigned long); extern void __invalidate_dcache_range(unsigned long, unsigned long); + #if XCHAL_DCACHE_IS_WRITEBACK +extern void __flush_invalidate_dcache_all(void); extern void __flush_dcache_page(unsigned long); +extern void __flush_dcache_range(unsigned long, unsigned long); extern void __flush_invalidate_dcache_page(unsigned long); extern void __flush_invalidate_dcache_range(unsigned long, unsigned long); #else -# define __flush_dcache_page(p) do { } while(0) -# define __flush_invalidate_dcache_page(p) do { } while(0) -# define __flush_invalidate_dcache_range(p,s) do { } while(0) +# define __flush_dcache_range(p,s) do { } while(0) +# define __flush_dcache_page(p) do { } while(0) +# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p) +# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s) +#endif + +#if (DCACHE_WAY_SIZE > PAGE_SIZE) +extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long); +#endif +#if (ICACHE_WAY_SIZE > PAGE_SIZE) +extern void __invalidate_icache_page_alias(unsigned long, unsigned long); #endif /* @@ -71,17 +81,21 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long); * (see also Documentation/cachetlb.txt) */ -#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK +#if (DCACHE_WAY_SIZE > PAGE_SIZE) -#define flush_cache_all() __flush_invalidate_cache_all(); -#define flush_cache_mm(mm) __flush_invalidate_cache_all(); -#define flush_cache_dup_mm(mm) __flush_invalidate_cache_all(); +#define flush_cache_all() \ + do { \ + __flush_invalidate_dcache_all(); \ + __invalidate_icache_all(); \ + } while (0) -#define flush_cache_vmap(start,end) __flush_invalidate_cache_all(); -#define flush_cache_vunmap(start,end) __flush_invalidate_cache_all(); +#define flush_cache_mm(mm) flush_cache_all() +#define flush_cache_dup_mm(mm) flush_cache_mm(mm) -extern void flush_dcache_page(struct page*); +#define flush_cache_vmap(start,end) flush_cache_all() +#define flush_cache_vunmap(start,end) flush_cache_all() +extern void flush_dcache_page(struct page*); extern void flush_cache_range(struct vm_area_struct*, ulong, ulong); extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long); @@ -101,24 +115,39 @@ extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned lon #endif +/* Ensure consistency between data and instruction cache. */ #define flush_icache_range(start,end) \ - __invalidate_icache_range(start,(end)-(start)) + do { \ + __flush_dcache_range(start, (end) - (start)); \ + __invalidate_icache_range(start,(end) - (start)); \ + } while (0) /* This is not required, see Documentation/cachetlb.txt */ - -#define flush_icache_page(vma,page) do { } while(0) +#define flush_icache_page(vma,page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) +#if (DCACHE_WAY_SIZE > PAGE_SIZE) -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) +extern void copy_to_user_page(struct vm_area_struct*, struct page*, + unsigned long, void*, const void*, unsigned long); +extern void copy_from_user_page(struct vm_area_struct*, struct page*, + unsigned long, void*, const void*, unsigned long); + +#else + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + memcpy(dst, src, len); \ + __flush_dcache_range((unsigned long) dst, len); \ + __invalidate_icache_range((unsigned long) dst, len); \ + } while (0) #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) -#endif /* __KERNEL__ */ +#endif +#endif /* __KERNEL__ */ #endif /* _XTENSA_CACHEFLUSH_H */ - diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h index 1569b53cec91..7083d46766a8 100644 --- a/include/asm-xtensa/elf.h +++ b/include/asm-xtensa/elf.h @@ -20,6 +20,56 @@ #define EM_XTENSA 94 #define EM_XTENSA_OLD 0xABC7 +/* Xtensa relocations defined by the ABIs */ + +#define R_XTENSA_NONE 0 +#define R_XTENSA_32 1 +#define R_XTENSA_RTLD 2 +#define R_XTENSA_GLOB_DAT 3 +#define R_XTENSA_JMP_SLOT 4 +#define R_XTENSA_RELATIVE 5 +#define R_XTENSA_PLT 6 +#define R_XTENSA_OP0 8 +#define R_XTENSA_OP1 9 +#define R_XTENSA_OP2 10 +#define R_XTENSA_ASM_EXPAND 11 +#define R_XTENSA_ASM_SIMPLIFY 12 +#define R_XTENSA_GNU_VTINHERIT 15 +#define R_XTENSA_GNU_VTENTRY 16 +#define R_XTENSA_DIFF8 17 +#define R_XTENSA_DIFF16 18 +#define R_XTENSA_DIFF32 19 +#define R_XTENSA_SLOT0_OP 20 +#define R_XTENSA_SLOT1_OP 21 +#define R_XTENSA_SLOT2_OP 22 +#define R_XTENSA_SLOT3_OP 23 +#define R_XTENSA_SLOT4_OP 24 +#define R_XTENSA_SLOT5_OP 25 +#define R_XTENSA_SLOT6_OP 26 +#define R_XTENSA_SLOT7_OP 27 +#define R_XTENSA_SLOT8_OP 28 +#define R_XTENSA_SLOT9_OP 29 +#define R_XTENSA_SLOT10_OP 30 +#define R_XTENSA_SLOT11_OP 31 +#define R_XTENSA_SLOT12_OP 32 +#define R_XTENSA_SLOT13_OP 33 +#define R_XTENSA_SLOT14_OP 34 +#define R_XTENSA_SLOT0_ALT 35 +#define R_XTENSA_SLOT1_ALT 36 +#define R_XTENSA_SLOT2_ALT 37 +#define R_XTENSA_SLOT3_ALT 38 +#define R_XTENSA_SLOT4_ALT 39 +#define R_XTENSA_SLOT5_ALT 40 +#define R_XTENSA_SLOT6_ALT 41 +#define R_XTENSA_SLOT7_ALT 42 +#define R_XTENSA_SLOT8_ALT 43 +#define R_XTENSA_SLOT9_ALT 44 +#define R_XTENSA_SLOT10_ALT 45 +#define R_XTENSA_SLOT11_ALT 46 +#define R_XTENSA_SLOT12_ALT 47 +#define R_XTENSA_SLOT13_ALT 48 +#define R_XTENSA_SLOT14_ALT 49 + /* ELF register definitions. This is needed for core dump support. */ /* diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h index 31ffc3f119c1..47c3616ea9ac 100644 --- a/include/asm-xtensa/io.h +++ b/include/asm-xtensa/io.h @@ -13,6 +13,8 @@ #ifdef __KERNEL__ #include <asm/byteorder.h> +#include <asm/page.h> +#include <linux/kernel.h> #include <linux/types.h> diff --git a/include/asm-xtensa/ioctls.h b/include/asm-xtensa/ioctls.h index 39e6f23921bb..0ffa942954b9 100644 --- a/include/asm-xtensa/ioctls.h +++ b/include/asm-xtensa/ioctls.h @@ -91,6 +91,10 @@ #define TIOCSBRK _IO('T', 39) /* BSD compatibility */ #define TIOCCBRK _IO('T', 40) /* BSD compatibility */ #define TIOCGSID _IOR('T', 41, pid_t) /* Return the session ID of FD*/ +#define TCGETS2 _IOR('T', 42, struct termios2) +#define TCSETS2 _IOW('T', 43, struct termios2) +#define TCSETSW2 _IOW('T', 44, struct termios2) +#define TCSETSF2 _IOW('T', 45, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h index 1213cde75438..55ce2c9749a3 100644 --- a/include/asm-xtensa/page.h +++ b/include/asm-xtensa/page.h @@ -1,11 +1,11 @@ /* - * linux/include/asm-xtensa/page.h + * include/asm-xtensa/page.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version2 as * published by the Free Software Foundation. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_PAGE_H @@ -14,6 +14,12 @@ #ifdef __KERNEL__ #include <asm/processor.h> +#include <asm/types.h> +#include <asm/cache.h> + +/* + * Fixed TLB translations in the processor. + */ #define XCHAL_KSEG_CACHED_VADDR 0xd0000000 #define XCHAL_KSEG_BYPASS_VADDR 0xd8000000 @@ -26,13 +32,60 @@ */ #define PAGE_SHIFT 12 -#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE - 1) & PAGE_MASK) #define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR -#define MAX_MEM_PFN XCHAL_KSEG_SIZE -#define PGTABLE_START 0x80000000 +#define MAX_MEM_PFN XCHAL_KSEG_SIZE +#define PGTABLE_START 0x80000000 + +/* + * Cache aliasing: + * + * If the cache size for one way is greater than the page size, we have to + * deal with cache aliasing. The cache index is wider than the page size: + * + * | |cache| cache index + * | pfn |off| virtual address + * |xxxx:X|zzz| + * | : | | + * | \ / | | + * |trans.| | + * | / \ | | + * |yyyy:Y|zzz| physical address + * + * When the page number is translated to the physical page address, the lowest + * bit(s) (X) that are part of the cache index are also translated (Y). + * If this translation changes bit(s) (X), the cache index is also afected, + * thus resulting in a different cache line than before. + * The kernel does not provide a mechanism to ensure that the page color + * (represented by this bit) remains the same when allocated or when pages + * are remapped. When user pages are mapped into kernel space, the color of + * the page might also change. + * + * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2 + * to temporarily map a patch so we can match the color. + */ + +#if DCACHE_WAY_SIZE > PAGE_SIZE +# define DCACHE_ALIAS_ORDER (DCACHE_WAY_SHIFT - PAGE_SHIFT) +# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1)) +# define DCACHE_ALIAS(a) (((a) & DCACHE_ALIAS_MASK) >> PAGE_SHIFT) +# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0) +#else +# define DCACHE_ALIAS_ORDER 0 +#endif + +#if ICACHE_WAY_SIZE > PAGE_SIZE +# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT) +# define ICACHE_ALIAS_MASK (PAGE_MASK & (ICACHE_WAY_SIZE - 1)) +# define ICACHE_ALIAS(a) (((a) & ICACHE_ALIAS_MASK) >> PAGE_SHIFT) +# define ICACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & ICACHE_ALIAS_MASK) == 0) +#else +# define ICACHE_ALIAS_ORDER 0 +#endif + #ifdef __ASSEMBLY__ @@ -58,34 +111,23 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * Pure 2^n version of get_order + * Use 'nsau' instructions if supported by the processor or the generic version. */ -static inline int get_order(unsigned long size) +#if XCHAL_HAVE_NSA + +static inline __attribute_const__ int get_order(unsigned long size) { - int order; -#ifndef XCHAL_HAVE_NSU - unsigned long x1, x2, x4, x8, x16; - - size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; - x1 = size & 0xAAAAAAAA; - x2 = size & 0xCCCCCCCC; - x4 = size & 0xF0F0F0F0; - x8 = size & 0xFF00FF00; - x16 = size & 0xFFFF0000; - order = x2 ? 2 : 0; - order += (x16 != 0) * 16; - order += (x8 != 0) * 8; - order += (x4 != 0) * 4; - order += (x1 != 0); - - return order; -#else - size = (size - 1) >> PAGE_SHIFT; - asm ("nsau %0, %1" : "=r" (order) : "r" (size)); - return 32 - order; -#endif + int lz; + asm ("nsau %0, %1" : "=r" (lz) : "r" ((size - 1) >> PAGE_SHIFT)); + return 32 - lz; } +#else + +# include <asm-generic/page.h> + +#endif struct page; extern void clear_page(void *page); @@ -96,11 +138,11 @@ extern void copy_page(void *to, void *from); * some extra work */ -#if (DCACHE_WAY_SIZE > PAGE_SIZE) -void clear_user_page(void *addr, unsigned long vaddr, struct page* page); -void copy_user_page(void *to,void* from,unsigned long vaddr,struct page* page); +#if DCACHE_WAY_SIZE > PAGE_SIZE +extern void clear_user_page(void*, unsigned long, struct page*); +extern void copy_user_page(void*, void*, unsigned long, struct page*); #else -# define clear_user_page(page,vaddr,pg) clear_page(page) +# define clear_user_page(page, vaddr, pg) clear_page(page) # define copy_user_page(to, from, vaddr, pg) copy_page(to, from) #endif diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h index d56ddf2055e1..3e5b56525102 100644 --- a/include/asm-xtensa/pgalloc.h +++ b/include/asm-xtensa/pgalloc.h @@ -1,11 +1,11 @@ /* - * linux/include/asm-xtensa/pgalloc.h + * include/asm-xtensa/pgalloc.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (C) 2001-2005 Tensilica Inc. + * Copyright (C) 2001-2007 Tensilica Inc. */ #ifndef _XTENSA_PGALLOC_H @@ -13,103 +13,54 @@ #ifdef __KERNEL__ -#include <linux/threads.h> #include <linux/highmem.h> -#include <asm/processor.h> -#include <asm/cacheflush.h> - - -/* Cache aliasing: - * - * If the cache size for one way is greater than the page size, we have to - * deal with cache aliasing. The cache index is wider than the page size: - * - * |cache | - * |pgnum |page| virtual address - * |xxxxxX|zzzz| - * | | | - * \ / | | - * trans.| | - * / \ | | - * |yyyyyY|zzzz| physical address - * - * When the page number is translated to the physical page address, the lowest - * bit(s) (X) that are also part of the cache index are also translated (Y). - * If this translation changes this bit (X), the cache index is also afected, - * thus resulting in a different cache line than before. - * The kernel does not provide a mechanism to ensure that the page color - * (represented by this bit) remains the same when allocated or when pages - * are remapped. When user pages are mapped into kernel space, the color of - * the page might also change. - * - * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2 - * to temporarily map a patch so we can match the color. - */ - -#if (DCACHE_WAY_SIZE > PAGE_SIZE) -# define PAGE_COLOR_MASK (PAGE_MASK & (DCACHE_WAY_SIZE-1)) -# define PAGE_COLOR(a) \ - (((unsigned long)(a)&PAGE_COLOR_MASK) >> PAGE_SHIFT) -# define PAGE_COLOR_EQ(a,b) \ - ((((unsigned long)(a) ^ (unsigned long)(b)) & PAGE_COLOR_MASK) == 0) -# define PAGE_COLOR_MAP0(v) \ - (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK)) -# define PAGE_COLOR_MAP1(v) \ - (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK) + DCACHE_WAY_SIZE) -#endif /* * Allocating and freeing a pmd is trivial: the 1-entry pmd is * inside the pgd, so has no extra memory associated with it. */ -#define pgd_free(pgd) free_page((unsigned long)(pgd)) - -#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK +#define pmd_populate_kernel(mm, pmdp, ptep) \ + (pmd_val(*(pmdp)) = ((unsigned long)ptep)) +#define pmd_populate(mm, pmdp, page) \ + (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page))) -static inline void -pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *pte) +static inline pgd_t* +pgd_alloc(struct mm_struct *mm) { - pmd_val(*(pmdp)) = (unsigned long)(pte); - __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp)); + return (pgd_t*) __get_free_pages(GFP_KERNEL | __GFP_ZERO, PGD_ORDER); } -static inline void -pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *page) +static inline void pgd_free(pgd_t *pgd) { - pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page); - __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp)); + free_page((unsigned long)pgd); } +/* Use a slab cache for the pte pages (see also sparc64 implementation) */ +extern struct kmem_cache *pgtable_cache; -#else - -# define pmd_populate_kernel(mm, pmdp, pte) \ - (pmd_val(*(pmdp)) = (unsigned long)(pte)) -# define pmd_populate(mm, pmdp, page) \ - (pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page)) - -#endif - -static inline pgd_t* -pgd_alloc(struct mm_struct *mm) +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) { - pgd_t *pgd; - - pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGD_ORDER); - - if (likely(pgd != NULL)) - __flush_dcache_page((unsigned long)pgd); + return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT); +} - return pgd; +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long addr) +{ + return virt_to_page(pte_alloc_one_kernel(mm, addr)); } -extern pte_t* pte_alloc_one_kernel(struct mm_struct* mm, unsigned long addr); -extern struct page* pte_alloc_one(struct mm_struct* mm, unsigned long addr); +static inline void pte_free_kernel(pte_t *pte) +{ + kmem_cache_free(pgtable_cache, pte); +} -#define pte_free_kernel(pte) free_page((unsigned long)pte) -#define pte_free(pte) __free_page(pte) +static inline void pte_free(struct page *page) +{ + kmem_cache_free(pgtable_cache, page_address(page)); +} #endif /* __KERNEL__ */ #endif /* _XTENSA_PGALLOC_H */ diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h index 06850f3b26a7..c0fcc1c9660c 100644 --- a/include/asm-xtensa/pgtable.h +++ b/include/asm-xtensa/pgtable.h @@ -1,11 +1,11 @@ /* - * linux/include/asm-xtensa/pgtable.h + * include/asm-xtensa/pgtable.h * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version2 as + * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_PGTABLE_H @@ -23,7 +23,7 @@ /* * The Xtensa architecture port of Linux has a two-level page table system, - * i.e. the logical three-level Linux page table layout are folded. + * i.e. the logical three-level Linux page table layout is folded. * Each task has the following memory page tables: * * PGD table (page directory), ie. 3rd-level page table: @@ -43,6 +43,7 @@ * * The individual pages are 4 kB big with special pages for the empty_zero_page. */ + #define PGDIR_SHIFT 22 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -53,24 +54,26 @@ */ #define PTRS_PER_PTE 1024 #define PTRS_PER_PTE_SHIFT 10 -#define PTRS_PER_PMD 1 #define PTRS_PER_PGD 1024 #define PGD_ORDER 0 -#define PMD_ORDER 0 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 +#define FIRST_USER_ADDRESS 0 #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) -/* virtual memory area. We keep a distance to other memory regions to be +/* + * Virtual memory area. We keep a distance to other memory regions to be * on the safe side. We also use this area for cache aliasing. */ -// FIXME: virtual memory area must be configuration-dependent - #define VMALLOC_START 0xC0000000 -#define VMALLOC_END 0xC7FF0000 +#define VMALLOC_END 0xC6FEFFFF +#define TLBTEMP_BASE_1 0xC6FF0000 +#define TLBTEMP_BASE_2 0xC6FF8000 +#define MODULE_START 0xC7000000 +#define MODULE_END 0xC7FFFFFF -/* Xtensa Linux config PTE layout (when present): +/* + * Xtensa Linux config PTE layout (when present): * 31-12: PPN * 11-6: Software * 5-4: RING @@ -86,47 +89,55 @@ * See further below for PTE layout for swapped-out pages. */ -#define _PAGE_VALID (1<<0) /* hardware: page is accessible */ -#define _PAGE_WRENABLE (1<<1) /* hardware: page is writable */ +#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */ +#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */ + +#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */ +#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */ /* None of these cache modes include MP coherency: */ -#define _PAGE_NO_CACHE (0<<2) /* bypass, non-speculative */ -#if XCHAL_DCACHE_IS_WRITEBACK -# define _PAGE_WRITEBACK (1<<2) /* write back */ -# define _PAGE_WRITETHRU (2<<2) /* write through */ -#else -# define _PAGE_WRITEBACK (1<<2) /* assume write through */ -# define _PAGE_WRITETHRU (1<<2) -#endif -#define _PAGE_NOALLOC (3<<2) /* don't allocate cache,if not cached */ -#define _CACHE_MASK (3<<2) +#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */ +#define _PAGE_CA_WB (1<<2) /* write-back */ +#define _PAGE_CA_WT (2<<2) /* write-through */ +#define _PAGE_CA_MASK (3<<2) +#define _PAGE_INVALID (3<<2) #define _PAGE_USER (1<<4) /* user access (ring=1) */ -#define _PAGE_KERNEL (0<<4) /* kernel access (ring=0) */ /* Software */ -#define _PAGE_RW (1<<6) /* software: page writable */ +#define _PAGE_WRITABLE_BIT 6 +#define _PAGE_WRITABLE (1<<6) /* software: page writable */ #define _PAGE_DIRTY (1<<7) /* software: page dirty */ #define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */ -#define _PAGE_FILE (1<<9) /* nonlinear file mapping*/ -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _CACHE_MASK | _PAGE_DIRTY) -#define _PAGE_PRESENT ( _PAGE_VALID | _PAGE_WRITEBACK | _PAGE_ACCESSED) +/* On older HW revisions, we always have to set bit 0 */ +#if XCHAL_HW_VERSION_MAJOR < 2000 +# define _PAGE_VALID (1<<0) +#else +# define _PAGE_VALID 0 +#endif -#ifdef CONFIG_MMU +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) +#define _PAGE_PRESENT (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED) -# define PAGE_NONE __pgprot(_PAGE_PRESENT) -# define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_RW) -# define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER) -# define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER) -# define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_KERNEL | _PAGE_WRENABLE) -# define PAGE_INVALID __pgprot(_PAGE_USER) +#ifdef CONFIG_MMU -# if (DCACHE_WAY_SIZE > PAGE_SIZE) -# define PAGE_DIRECTORY __pgprot(_PAGE_VALID | _PAGE_ACCESSED | _PAGE_KERNEL) -# else -# define PAGE_DIRECTORY __pgprot(_PAGE_PRESENT | _PAGE_KERNEL) -# endif +#define PAGE_NONE __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER) +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER) +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE) +#define PAGE_SHARED_EXEC \ + __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC) +#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE) +#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC) + +#if (DCACHE_WAY_SIZE > PAGE_SIZE) +# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED) +#else +# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB) +#endif #else /* no mmu */ @@ -145,23 +156,23 @@ * What follows is the closest we can get by reasonable means.. * See linux/mm/mmap.c for protection_map[] array that uses these definitions. */ -#define __P000 PAGE_NONE /* private --- */ -#define __P001 PAGE_READONLY /* private --r */ -#define __P010 PAGE_COPY /* private -w- */ -#define __P011 PAGE_COPY /* private -wr */ -#define __P100 PAGE_READONLY /* private x-- */ -#define __P101 PAGE_READONLY /* private x-r */ -#define __P110 PAGE_COPY /* private xw- */ -#define __P111 PAGE_COPY /* private xwr */ - -#define __S000 PAGE_NONE /* shared --- */ -#define __S001 PAGE_READONLY /* shared --r */ -#define __S010 PAGE_SHARED /* shared -w- */ -#define __S011 PAGE_SHARED /* shared -wr */ -#define __S100 PAGE_READONLY /* shared x-- */ -#define __S101 PAGE_READONLY /* shared x-r */ -#define __S110 PAGE_SHARED /* shared xw- */ -#define __S111 PAGE_SHARED /* shared xwr */ +#define __P000 PAGE_NONE /* private --- */ +#define __P001 PAGE_READONLY /* private --r */ +#define __P010 PAGE_COPY /* private -w- */ +#define __P011 PAGE_COPY /* private -wr */ +#define __P100 PAGE_READONLY_EXEC /* private x-- */ +#define __P101 PAGE_READONLY_EXEC /* private x-r */ +#define __P110 PAGE_COPY_EXEC /* private xw- */ +#define __P111 PAGE_COPY_EXEC /* private xwr */ + +#define __S000 PAGE_NONE /* shared --- */ +#define __S001 PAGE_READONLY /* shared --r */ +#define __S010 PAGE_SHARED /* shared -w- */ +#define __S011 PAGE_SHARED /* shared -wr */ +#define __S100 PAGE_READONLY_EXEC /* shared x-- */ +#define __S101 PAGE_READONLY_EXEC /* shared x-r */ +#define __S110 PAGE_SHARED_EXEC /* shared xw- */ +#define __S111 PAGE_SHARED_EXEC /* shared xwr */ #ifndef __ASSEMBLY__ @@ -183,35 +194,42 @@ extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; #define pmd_page(pmd) virt_to_page(pmd_val(pmd)) /* - * The following only work if pte_present() is true. + * pte status. */ -#define pte_none(pte) (!(pte_val(pte) ^ _PAGE_USER)) -#define pte_present(pte) (pte_val(pte) & _PAGE_VALID) +#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID) +#define pte_present(pte) \ + (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \ + || ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE)) #define pte_clear(mm,addr,ptep) \ - do { update_pte(ptep, __pte(_PAGE_USER)); } while(0) + do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0) #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK) -#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0) #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) +#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0) -/* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */ - -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } +static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~(_PAGE_RW | _PAGE_WRENABLE); return pte; } -static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } -static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } -static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pte; } +static inline pte_t pte_wrprotect(pte_t pte) + { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; } +static inline pte_t pte_mkclean(pte_t pte) + { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; } +static inline pte_t pte_mkold(pte_t pte) + { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } +static inline pte_t pte_mkdirty(pte_t pte) + { pte_val(pte) |= _PAGE_DIRTY; return pte; } +static inline pte_t pte_mkyoung(pte_t pte) + { pte_val(pte) |= _PAGE_ACCESSED; return pte; } +static inline pte_t pte_mkwrite(pte_t pte) + { pte_val(pte) |= _PAGE_WRITABLE; return pte; } /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ + #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) #define pte_same(a,b) (pte_val(a) == pte_val(b)) #define pte_page(x) pfn_to_page(pte_pfn(x)) @@ -232,8 +250,9 @@ static inline void update_pte(pte_t *ptep, pte_t pteval) { *ptep = pteval; #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK - __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (ptep)); + __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep)); #endif + } struct mm_struct; @@ -249,9 +268,6 @@ static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval) { *pmdp = pmdval; -#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK - __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp)); -#endif } struct vm_area_struct; @@ -306,52 +322,34 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) /* * Encode and decode a swap entry. - * Each PTE in a process VM's page table is either: - * "present" -- valid and not swapped out, protection bits are meaningful; - * "not present" -- which further subdivides in these two cases: - * "none" -- no mapping at all; identified by pte_none(), set by pte_clear( - * "swapped out" -- the page is swapped out, and the SWP macros below - * are used to store swap file info in the PTE itself. * - * In the Xtensa processor MMU, any PTE entries in user space (or anywhere - * in virtual memory that can map differently across address spaces) - * must have a correct ring value that represents the RASID field that - * is changed when switching address spaces. Eg. such PTE entries cannot - * be set to ring zero, because that can cause a (global) kernel ASID - * entry to be created in the TLBs (even with invalid cache attribute), - * potentially causing a multihit exception when going back to another - * address space that mapped the same virtual address at another ring. - * - * SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs. - * We also avoid using the _PAGE_VALID bit which must be zero for non-present - * pages. - * - * We end up with the following available bits: 1..3 and 7..31. - * We don't bother with 1..3 for now (we can use them later if needed), - * and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits - * for SWP_OFFSET. At least 5 bits are needed for SWP_TYPE, because it - * is currently implemented as an index into swap_info[MAX_SWAPFILES] - * and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>. - * However, for some reason all other architectures in the 2.4 kernel - * reserve either 6, 7, or 8 bits so I'll not detract from that for now. :) - * SWP_OFFSET is an offset into the swap file in page-size units, so - * with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB. - * - * FIXME: 2 GB isn't very big. Other bits can be used to allow - * larger swap sizes. In the meantime, it appears relatively easy to get - * around the 2 GB limitation by simply using multiple swap files. + * Format of swap pte: + * bit 0 MBZ + * bit 1 page-file (must be zero) + * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID) + * bits 4 - 5 ring protection (must be 01: _PAGE_USER) + * bits 6 - 10 swap type (5 bits -> 32 types) + * bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB) + + * Format of file pte: + * bit 0 MBZ + * bit 1 page-file (must be one: _PAGE_FILE) + * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID) + * bits 4 - 5 ring protection (must be 01: _PAGE_USER) + * bits 6 - 31 file offset / PAGE_SIZE */ -#define __swp_type(entry) (((entry).val >> 7) & 0x3f) -#define __swp_offset(entry) ((entry).val >> 13) -#define __swp_entry(type,offs) ((swp_entry_t) {((type) << 7) | ((offs) << 13)}) +#define __swp_type(entry) (((entry).val >> 6) & 0x1f) +#define __swp_offset(entry) ((entry).val >> 11) +#define __swp_entry(type,offs) \ + ((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID}) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) -#define PTE_FILE_MAX_BITS 29 -#define pte_to_pgoff(pte) (pte_val(pte) >> 3) -#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) - +#define PTE_FILE_MAX_BITS 28 +#define pte_to_pgoff(pte) (pte_val(pte) >> 4) +#define pgoff_to_pte(off) \ + ((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE }) #endif /* !defined (__ASSEMBLY__) */ @@ -394,13 +392,12 @@ extern void update_mmu_cache(struct vm_area_struct * vma, * remap a physical page `pfn' of size `size' with page protection `prot' * into virtual address `from' */ + #define io_remap_pfn_range(vma,from,pfn,size,prot) \ remap_pfn_range(vma, from, pfn, size, prot) -/* No page table caches to init */ - -#define pgtable_cache_init() do { } while (0) +extern void pgtable_cache_init(void); typedef pte_t *pte_addr_t; diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h index 4feb9f7f35a6..35145bcd96eb 100644 --- a/include/asm-xtensa/processor.h +++ b/include/asm-xtensa/processor.h @@ -33,7 +33,7 @@ * the 1 GB requirement applies to the stack as well. */ -#define TASK_SIZE 0x40000000 +#define TASK_SIZE __XTENSA_UL_CONST(0x40000000) /* * General exception cause assigned to debug exceptions. Debug exceptions go diff --git a/include/asm-xtensa/syscall.h b/include/asm-xtensa/syscall.h index 6cb0d42f11c8..05cebf8f62b1 100644 --- a/include/asm-xtensa/syscall.h +++ b/include/asm-xtensa/syscall.h @@ -1,3 +1,13 @@ +/* + * include/asm-xtensa/syscall.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 - 2007 Tensilica Inc. + */ + struct pt_regs; struct sigaction; asmlinkage long xtensa_execve(char*, char**, char**, struct pt_regs*); @@ -17,4 +27,16 @@ asmlinkage long sys_rt_sigaction(int, const struct sigaction __user *, struct sigaction __user *, size_t); -asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg); +asmlinkage long xtensa_shmat(int, char __user *, int); +asmlinkage long xtensa_fadvise64_64(int, int, + unsigned long long, unsigned long long); + +/* Should probably move to linux/syscalls.h */ +struct pollfd; +asmlinkage long sys_pselect6(int n, fd_set __user *inp, fd_set __user *outp, + fd_set __user *exp, struct timespec __user *tsp, void __user *sig); +asmlinkage long sys_ppoll(struct pollfd __user *ufds, unsigned int nfds, + struct timespec __user *tsp, const sigset_t __user *sigmask, + size_t sigsetsize); + + diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h index 9972c25ec86f..85aa6a3c0b6e 100644 --- a/include/asm-xtensa/termbits.h +++ b/include/asm-xtensa/termbits.h @@ -157,6 +157,7 @@ struct ktermios { #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -172,10 +173,12 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + /* c_lflag bits */ #define ISIG 0000001 diff --git a/include/asm-xtensa/termios.h b/include/asm-xtensa/termios.h index f14b42c8dac0..4673f42f88a7 100644 --- a/include/asm-xtensa/termios.h +++ b/include/asm-xtensa/termios.h @@ -95,8 +95,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* __KERNEL__ */ diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h index 3fa29799b435..52c958285bcb 100644 --- a/include/asm-xtensa/thread_info.h +++ b/include/asm-xtensa/thread_info.h @@ -110,17 +110,15 @@ static inline struct thread_info *current_thread_info(void) * - other flags in MSW */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ -#define TIF_IRET 5 /* return with iret */ -#define TIF_MEMDIE 6 -#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal() */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */ +#define TIF_IRET 4 /* return with iret */ +#define TIF_MEMDIE 5 +#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h index 28c7985a4000..a5fca59fba9e 100644 --- a/include/asm-xtensa/timex.h +++ b/include/asm-xtensa/timex.h @@ -41,10 +41,10 @@ extern unsigned long ccount_per_jiffy; extern unsigned long ccount_nsec; #define CCOUNT_PER_JIFFY ccount_per_jiffy -#define CCOUNT_NSEC ccount_nsec +#define NSEC_PER_CCOUNT ccount_nsec #else #define CCOUNT_PER_JIFFY (CONFIG_XTENSA_CPU_CLOCK*(1000000UL/HZ)) -#define CCOUNT_NSEC (1000000000UL / CONFIG_XTENSA_CPU_CLOCK) +#define NSEC_PER_CCOUNT (1000UL / CONFIG_XTENSA_CPU_CLOCK) #endif diff --git a/include/asm-xtensa/tlb.h b/include/asm-xtensa/tlb.h index 4562b2dcfbc0..4830232017af 100644 --- a/include/asm-xtensa/tlb.h +++ b/include/asm-xtensa/tlb.h @@ -11,14 +11,36 @@ #ifndef _XTENSA_TLB_H #define _XTENSA_TLB_H -#define tlb_start_vma(tlb,vma) do { } while (0) -#define tlb_end_vma(tlb,vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0) +#include <asm/cache.h> +#include <asm/page.h> + +#if (DCACHE_WAY_SIZE <= PAGE_SIZE) + +/* Note, read http://lkml.org/lkml/2004/1/15/6 */ + +# define tlb_start_vma(tlb,vma) do { } while (0) +# define tlb_end_vma(tlb,vma) do { } while (0) + +#else +# define tlb_start_vma(tlb, vma) \ + do { \ + if (!tlb->fullmm) \ + flush_cache_range(vma, vma->vm_start, vma->vm_end); \ + } while(0) + +# define tlb_end_vma(tlb, vma) \ + do { \ + if (!tlb->fullmm) \ + flush_tlb_range(vma, vma->vm_start, vma->vm_end); \ + } while(0) + +#endif + +#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0) #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) #include <asm-generic/tlb.h> -#include <asm/page.h> #define __pte_free_tlb(tlb,pte) pte_free(pte) diff --git a/include/asm-xtensa/types.h b/include/asm-xtensa/types.h index 9d99a8e9e337..f1e84526f999 100644 --- a/include/asm-xtensa/types.h +++ b/include/asm-xtensa/types.h @@ -11,6 +11,15 @@ #ifndef _XTENSA_TYPES_H #define _XTENSA_TYPES_H + +#ifdef __ASSEMBLY__ +# define __XTENSA_UL(x) (x) +# define __XTENSA_UL_CONST(x) x +#else +# define __XTENSA_UL(x) ((unsigned long)(x)) +# define __XTENSA_UL_CONST(x) x##UL +#endif + #ifndef __ASSEMBLY__ typedef unsigned short umode_t; diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h index 9bd34024431c..92968aabe34e 100644 --- a/include/asm-xtensa/unistd.h +++ b/include/asm-xtensa/unistd.h @@ -151,7 +151,7 @@ __SYSCALL( 61, sys_fcntl64, 3) #define __NR_available62 62 __SYSCALL( 62, sys_ni_syscall, 0) #define __NR_fadvise64_64 63 -__SYSCALL( 63, sys_fadvise64_64, 6) +__SYSCALL( 63, xtensa_fadvise64_64, 6) #define __NR_utime 64 /* glibc 2.3.3 ?? */ __SYSCALL( 64, sys_utime, 2) #define __NR_utimes 65 @@ -339,8 +339,8 @@ __SYSCALL(148, sys_setpgid, 2) __SYSCALL(149, sys_getpgid, 1) #define __NR_getppid 150 __SYSCALL(150, sys_getppid, 0) -#define __NR_available151 151 -__SYSCALL(151, sys_ni_syscall, 0) +#define __NR_getpgrp 151 +__SYSCALL(151, sys_getpgrp, 0) #define __NR_reserved152 152 /* set_thread_area */ __SYSCALL(152, sys_ni_syscall, 0) @@ -577,7 +577,112 @@ __SYSCALL(258, sys_keyctl, 5) #define __NR_available259 259 __SYSCALL(259, sys_ni_syscall, 0) -#define __NR_syscall_count 261 + +#define __NR_readahead 260 +__SYSCALL(260, sys_readahead, 5) +#define __NR_remap_file_pages 261 +__SYSCALL(261, sys_remap_file_pages, 5) +#define __NR_migrate_pages 262 +__SYSCALL(262, sys_migrate_pages, 0) +#define __NR_mbind 263 +__SYSCALL(263, sys_mbind, 6) +#define __NR_get_mempolicy 264 +__SYSCALL(264, sys_get_mempolicy, 5) +#define __NR_set_mempolicy 265 +__SYSCALL(265, sys_set_mempolicy, 3) +#define __NR_unshare 266 +__SYSCALL(266, sys_unshare, 1) +#define __NR_move_pages 267 +__SYSCALL(267, sys_move_pages, 0) +#define __NR_splice 268 +__SYSCALL(268, sys_splice, 0) +#define __NR_tee 269 +__SYSCALL(269, sys_tee, 0) +#define __NR_vmsplice 270 +__SYSCALL(270, sys_vmsplice, 0) +#define __NR_available271 271 +__SYSCALL(271, sys_ni_syscall, 0) + +#define __NR_pselect6 272 +__SYSCALL(272, sys_pselect6, 0) +#define __NR_ppoll 273 +__SYSCALL(273, sys_ppoll, 0) +#define __NR_epoll_pwait 274 +__SYSCALL(274, sys_epoll_pwait, 0) +#define __NR_available275 275 +__SYSCALL(275, sys_ni_syscall, 0) + +#define __NR_inotify_init 276 +__SYSCALL(276, sys_inotify_init, 0) +#define __NR_inotify_add_watch 277 +__SYSCALL(277, sys_inotify_add_watch, 3) +#define __NR_inotify_rm_watch 278 +__SYSCALL(278, sys_inotify_rm_watch, 2) +#define __NR_available279 279 +__SYSCALL(279, sys_ni_syscall, 0) + +#define __NR_getcpu 280 +__SYSCALL(280, sys_getcpu, 0) +#define __NR_kexec_load 281 +__SYSCALL(281, sys_ni_syscall, 0) + +#define __NR_ioprio_set 282 +__SYSCALL(282, sys_ioprio_set, 2) +#define __NR_ioprio_get 283 +__SYSCALL(283, sys_ioprio_get, 3) + +#define __NR_set_robust_list 284 +__SYSCALL(284, sys_set_robust_list, 3) +#define __NR_get_robust_list 285 +__SYSCALL(285, sys_get_robust_list, 3) +#define __NR_reserved286 286 /* sync_file_rangeX */ +__SYSCALL(286, sys_ni_syscall, 3) +#define __NR_available287 287 +__SYSCALL(287, sys_faccessat, 0) + +/* Relative File Operations */ + +#define __NR_openat 288 +__SYSCALL(288, sys_openat, 4) +#define __NR_mkdirat 289 +__SYSCALL(289, sys_mkdirat, 3) +#define __NR_mknodat 290 +__SYSCALL(290, sys_mknodat, 4) +#define __NR_unlinkat 291 +__SYSCALL(291, sys_unlinkat, 3) +#define __NR_renameat 292 +__SYSCALL(292, sys_renameat, 4) +#define __NR_linkat 293 +__SYSCALL(293, sys_linkat, 5) +#define __NR_symlinkat 294 +__SYSCALL(294, sys_symlinkat, 3) +#define __NR_readlinkat 295 +__SYSCALL(295, sys_readlinkat, 4) +#define __NR_utimensat 296 +__SYSCALL(296, sys_utimensat, 0) +#define __NR_fchownat 297 +__SYSCALL(297, sys_fchownat, 5) +#define __NR_futimesat 298 +__SYSCALL(298, sys_futimesat, 4) +#define __NR_fstatat64 299 +__SYSCALL(299, sys_fstatat64, 0) +#define __NR_fchmodat 300 +__SYSCALL(300, sys_fchmodat, 4) +#define __NR_faccessat 301 +__SYSCALL(301, sys_faccessat, 4) +#define __NR_available302 302 +__SYSCALL(302, sys_ni_syscall, 0) +#define __NR_available303 303 +__SYSCALL(303, sys_ni_syscall, 0) + +#define __NR_signalfd 304 +__SYSCALL(304, sys_signalfd, 3) +#define __NR_timerfd 305 +__SYSCALL(305, sys_timerfd, 4) +#define __NR_eventfd 306 +__SYSCALL(306, sys_eventfd, 1) + +#define __NR_syscall_count 307 /* * sysxtensa syscall handler @@ -612,8 +717,19 @@ __SYSCALL(259, sys_ni_syscall, 0) #define __ARCH_WANT_SYS_LLSEEK #define __ARCH_WANT_SYS_RT_SIGACTION #define __ARCH_WANT_SYS_RT_SIGSUSPEND +#define __ARCH_WANT_SYS_GETPGRP -#endif /* __KERNEL__ */ +/* + * Ignore legacy system calls in the checksyscalls.sh script + */ -#endif /* _XTENSA_UNISTD_H */ +#define __IGNORE_fork /* use clone */ +#define __IGNORE_time +#define __IGNORE_alarm /* use setitimer */ +#define __IGNORE_pause +#define __IGNORE_mmap /* use mmap2 */ +#define __IGNORE_vfork /* use clone */ +#define __IGNORE_fadvise64 /* use fadvise64_64 */ +#endif /* __KERNEL__ */ +#endif /* _XTENSA_UNISTD_H */ diff --git a/include/crypto/algapi.h b/include/crypto/algapi.h index b2b1e6efd812..b9b05d399d2b 100644 --- a/include/crypto/algapi.h +++ b/include/crypto/algapi.h @@ -91,9 +91,11 @@ struct blkcipher_walk { u8 *iv; int flags; + unsigned int blocksize; }; extern const struct crypto_type crypto_ablkcipher_type; +extern const struct crypto_type crypto_aead_type; extern const struct crypto_type crypto_blkcipher_type; extern const struct crypto_type crypto_hash_type; @@ -111,7 +113,8 @@ struct crypto_tfm *crypto_spawn_tfm(struct crypto_spawn *spawn, u32 type, struct crypto_attr_type *crypto_get_attr_type(struct rtattr **tb); int crypto_check_attr_type(struct rtattr **tb, u32 type); -struct crypto_alg *crypto_get_attr_alg(struct rtattr **tb, u32 type, u32 mask); +struct crypto_alg *crypto_attr_alg(struct rtattr *rta, u32 type, u32 mask); +int crypto_attr_u32(struct rtattr *rta, u32 *num); struct crypto_instance *crypto_alloc_instance(const char *name, struct crypto_alg *alg); @@ -127,6 +130,9 @@ int blkcipher_walk_virt(struct blkcipher_desc *desc, struct blkcipher_walk *walk); int blkcipher_walk_phys(struct blkcipher_desc *desc, struct blkcipher_walk *walk); +int blkcipher_walk_virt_block(struct blkcipher_desc *desc, + struct blkcipher_walk *walk, + unsigned int blocksize); static inline void *crypto_tfm_ctx_aligned(struct crypto_tfm *tfm) { @@ -160,6 +166,36 @@ static inline void *crypto_ablkcipher_ctx(struct crypto_ablkcipher *tfm) return crypto_tfm_ctx(&tfm->base); } +static inline void *crypto_ablkcipher_ctx_aligned(struct crypto_ablkcipher *tfm) +{ + return crypto_tfm_ctx_aligned(&tfm->base); +} + +static inline struct aead_alg *crypto_aead_alg(struct crypto_aead *tfm) +{ + return &crypto_aead_tfm(tfm)->__crt_alg->cra_aead; +} + +static inline void *crypto_aead_ctx(struct crypto_aead *tfm) +{ + return crypto_tfm_ctx(&tfm->base); +} + +static inline struct crypto_instance *crypto_aead_alg_instance( + struct crypto_aead *aead) +{ + return crypto_tfm_alg_instance(&aead->base); +} + +static inline struct crypto_ablkcipher *crypto_spawn_ablkcipher( + struct crypto_spawn *spawn) +{ + u32 type = CRYPTO_ALG_TYPE_BLKCIPHER; + u32 mask = CRYPTO_ALG_TYPE_MASK; + + return __crypto_ablkcipher_cast(crypto_spawn_tfm(spawn, type, mask)); +} + static inline struct crypto_blkcipher *crypto_spawn_blkcipher( struct crypto_spawn *spawn) { @@ -223,16 +259,16 @@ static inline struct crypto_async_request *crypto_get_backlog( container_of(queue->backlog, struct crypto_async_request, list); } -static inline int ablkcipher_enqueue_request(struct ablkcipher_alg *alg, +static inline int ablkcipher_enqueue_request(struct crypto_queue *queue, struct ablkcipher_request *request) { - return crypto_enqueue_request(alg->queue, &request->base); + return crypto_enqueue_request(queue, &request->base); } static inline struct ablkcipher_request *ablkcipher_dequeue_request( - struct ablkcipher_alg *alg) + struct crypto_queue *queue) { - return ablkcipher_request_cast(crypto_dequeue_request(alg->queue)); + return ablkcipher_request_cast(crypto_dequeue_request(queue)); } static inline void *ablkcipher_request_ctx(struct ablkcipher_request *req) @@ -240,10 +276,31 @@ static inline void *ablkcipher_request_ctx(struct ablkcipher_request *req) return req->__ctx; } -static inline int ablkcipher_tfm_in_queue(struct crypto_ablkcipher *tfm) +static inline int ablkcipher_tfm_in_queue(struct crypto_queue *queue, + struct crypto_ablkcipher *tfm) +{ + return crypto_tfm_in_queue(queue, crypto_ablkcipher_tfm(tfm)); +} + +static inline void *aead_request_ctx(struct aead_request *req) +{ + return req->__ctx; +} + +static inline void aead_request_complete(struct aead_request *req, int err) +{ + req->base.complete(&req->base, err); +} + +static inline u32 aead_request_flags(struct aead_request *req) +{ + return req->base.flags; +} + +static inline struct crypto_alg *crypto_get_attr_alg(struct rtattr **tb, + u32 type, u32 mask) { - return crypto_tfm_in_queue(crypto_ablkcipher_alg(tfm)->queue, - crypto_ablkcipher_tfm(tfm)); + return crypto_attr_alg(tb[1], type, mask); } #endif /* _CRYPTO_ALGAPI_H */ diff --git a/include/crypto/gf128mul.h b/include/crypto/gf128mul.h index 4fd315202442..4086b8ebfafe 100644 --- a/include/crypto/gf128mul.h +++ b/include/crypto/gf128mul.h @@ -161,6 +161,8 @@ void gf128mul_lle(be128 *a, const be128 *b); void gf128mul_bbe(be128 *a, const be128 *b); +/* multiply by x in ble format, needed by XTS */ +void gf128mul_x_ble(be128 *a, const be128 *b); /* 4k table optimization */ diff --git a/include/crypto/sha.h b/include/crypto/sha.h new file mode 100644 index 000000000000..0686e1f7a24b --- /dev/null +++ b/include/crypto/sha.h @@ -0,0 +1,53 @@ +/* + * Common values for SHA algorithms + */ + +#ifndef _CRYPTO_SHA_H +#define _CRYPTO_SHA_H + +#define SHA1_DIGEST_SIZE 20 +#define SHA1_BLOCK_SIZE 64 + +#define SHA256_DIGEST_SIZE 32 +#define SHA256_BLOCK_SIZE 64 + +#define SHA384_DIGEST_SIZE 48 +#define SHA384_BLOCK_SIZE 128 + +#define SHA512_DIGEST_SIZE 64 +#define SHA512_BLOCK_SIZE 128 + +#define SHA1_H0 0x67452301UL +#define SHA1_H1 0xefcdab89UL +#define SHA1_H2 0x98badcfeUL +#define SHA1_H3 0x10325476UL +#define SHA1_H4 0xc3d2e1f0UL + +#define SHA256_H0 0x6a09e667UL +#define SHA256_H1 0xbb67ae85UL +#define SHA256_H2 0x3c6ef372UL +#define SHA256_H3 0xa54ff53aUL +#define SHA256_H4 0x510e527fUL +#define SHA256_H5 0x9b05688cUL +#define SHA256_H6 0x1f83d9abUL +#define SHA256_H7 0x5be0cd19UL + +#define SHA384_H0 0xcbbb9d5dc1059ed8ULL +#define SHA384_H1 0x629a292a367cd507ULL +#define SHA384_H2 0x9159015a3070dd17ULL +#define SHA384_H3 0x152fecd8f70e5939ULL +#define SHA384_H4 0x67332667ffc00b31ULL +#define SHA384_H5 0x8eb44a8768581511ULL +#define SHA384_H6 0xdb0c2e0d64f98fa7ULL +#define SHA384_H7 0x47b5481dbefa4fa4ULL + +#define SHA512_H0 0x6a09e667f3bcc908ULL +#define SHA512_H1 0xbb67ae8584caa73bULL +#define SHA512_H2 0x3c6ef372fe94f82bULL +#define SHA512_H3 0xa54ff53a5f1d36f1ULL +#define SHA512_H4 0x510e527fade682d1ULL +#define SHA512_H5 0x9b05688c2b3e6c1fULL +#define SHA512_H6 0x1f83d9abfb41bd6bULL +#define SHA512_H7 0x5be0cd19137e2179ULL + +#endif diff --git a/include/linux/Kbuild b/include/linux/Kbuild index bcf875e844fe..818cc3a50e6b 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -7,6 +7,7 @@ header-y += raid/ header-y += spi/ header-y += sunrpc/ header-y += tc_act/ +header-y += tc_ematch/ header-y += netfilter/ header-y += netfilter_arp/ header-y += netfilter_bridge/ @@ -137,6 +138,7 @@ header-y += radeonfb.h header-y += raw.h header-y += resource.h header-y += rose.h +header-y += serial_reg.h header-y += smbno.h header-y += snmp.h header-y += sockios.h diff --git a/include/linux/acpi.h b/include/linux/acpi.h index fccd8b548d93..bf5e0009de75 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -33,6 +33,7 @@ #endif #include <linux/list.h> +#include <linux/mod_devicetable.h> #include <acpi/acpi.h> #include <acpi/acpi_bus.h> @@ -88,10 +89,8 @@ int acpi_table_parse (char *id, acpi_table_handler handler); int __init acpi_table_parse_entries(char *id, unsigned long table_size, int entry_id, acpi_table_entry_handler handler, unsigned int max_entries); int acpi_table_parse_madt (enum acpi_madt_type id, acpi_table_entry_handler handler, unsigned int max_entries); -int acpi_table_parse_srat (enum acpi_srat_type id, acpi_table_entry_handler handler, unsigned int max_entries); int acpi_parse_mcfg (struct acpi_table_header *header); void acpi_table_print_madt_entry (struct acpi_subtable_header *madt); -void acpi_table_print_srat_entry (struct acpi_subtable_header *srat); /* the following four functions are architecture-dependent */ #ifdef CONFIG_HAVE_ARCH_PARSE_SRAT @@ -122,7 +121,7 @@ extern struct acpi_mcfg_allocation *pci_mmcfg_config; extern int pci_mmcfg_config_num; extern int sbf_port; -extern unsigned long acpi_video_flags; +extern unsigned long acpi_realmode_flags; #else /* !CONFIG_ACPI */ @@ -233,6 +232,9 @@ extern int acpi_paddr_to_node(u64 start_addr, u64 size); extern int pnpacpi_disabled; +#define PXM_INVAL (-1) +#define NID_INVAL (-1) + #else /* CONFIG_ACPI */ static inline int acpi_boot_init(void) diff --git a/include/linux/aer.h b/include/linux/aer.h index 509656286e53..bcf236d825e8 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -15,11 +15,26 @@ extern int pci_disable_pcie_error_reporting(struct pci_dev *dev); extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev); #else -#define pci_enable_pcie_error_reporting(dev) (-EINVAL) -#define pci_find_aer_capability(dev) (0) -#define pci_disable_pcie_error_reporting(dev) (-EINVAL) -#define pci_cleanup_aer_uncorrect_error_status(dev) (-EINVAL) -#define pci_cleanup_aer_correct_error_status(dev) (-EINVAL) +static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) +{ + return -EINVAL; +} +static inline int pci_find_aer_capability(struct pci_dev *dev) +{ + return 0; +} +static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) +{ + return -EINVAL; +} +static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) +{ + return -EINVAL; +} +static inline int pci_cleanup_aer_correct_error_status(struct pci_dev *dev) +{ + return -EINVAL; +} #endif #endif //_AER_H_ diff --git a/include/linux/aio.h b/include/linux/aio.h index b903fc02bdb7..d10e608f232d 100644 --- a/include/linux/aio.h +++ b/include/linux/aio.h @@ -86,7 +86,7 @@ struct kioctx; */ struct kiocb { struct list_head ki_run_list; - long ki_flags; + unsigned long ki_flags; int ki_users; unsigned ki_key; /* id of this request */ diff --git a/include/linux/apm_bios.h b/include/linux/apm_bios.h index 290aef326812..5f921c84827a 100644 --- a/include/linux/apm_bios.h +++ b/include/linux/apm_bios.h @@ -21,20 +21,22 @@ typedef unsigned short apm_eventinfo_t; #ifdef __KERNEL__ +#include <linux/types.h> + #define APM_CS (GDT_ENTRY_APMBIOS_BASE * 8) #define APM_CS_16 (APM_CS + 8) #define APM_DS (APM_CS_16 + 8) struct apm_bios_info { - unsigned short version; - unsigned short cseg; - unsigned long offset; - unsigned short cseg_16; - unsigned short dseg; - unsigned short flags; - unsigned short cseg_len; - unsigned short cseg_16_len; - unsigned short dseg_len; + u16 version; + u16 cseg; + u32 offset; + u16 cseg_16; + u16 dseg; + u16 flags; + u16 cseg_len; + u16 cseg_16_len; + u16 dseg_len; }; /* Results of APM Installation Check */ diff --git a/include/linux/arcdevice.h b/include/linux/arcdevice.h index 2f85049cfb3d..fde675872c56 100644 --- a/include/linux/arcdevice.h +++ b/include/linux/arcdevice.h @@ -214,7 +214,7 @@ extern struct ArcProto *arc_proto_map[256], *arc_proto_default, */ struct Incoming { struct sk_buff *skb; /* packet data buffer */ - uint16_t sequence; /* sequence number of assembly */ + __be16 sequence; /* sequence number of assembly */ uint8_t lastpacket, /* number of last packet (from 1) */ numpackets; /* number of packets in split */ }; @@ -292,7 +292,7 @@ struct arcnet_local { struct { uint16_t sequence; /* sequence number (incs with each packet) */ - uint16_t aborted_seq; + __be16 aborted_seq; struct Incoming incoming[256]; /* one from each address */ } rfc1201; diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index ff1255079fa1..bdca3f1b3213 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -51,10 +51,6 @@ struct dma_chan_ref { * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a * dependency chain * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. - * @ASYNC_TX_KMAP_SRC: if the transaction is to be performed synchronously - * take an atomic mapping (KM_USER0) on the source page(s) - * @ASYNC_TX_KMAP_DST: if the transaction is to be performed synchronously - * take an atomic mapping (KM_USER0) on the dest page(s) */ enum async_tx_flags { ASYNC_TX_XOR_ZERO_DST = (1 << 0), @@ -62,8 +58,6 @@ enum async_tx_flags { ASYNC_TX_ASSUME_COHERENT = (1 << 2), ASYNC_TX_ACK = (1 << 3), ASYNC_TX_DEP_ACK = (1 << 4), - ASYNC_TX_KMAP_SRC = (1 << 5), - ASYNC_TX_KMAP_DST = (1 << 6), }; #ifdef CONFIG_DMA_ENGINE diff --git a/include/linux/ata.h b/include/linux/ata.h index b5a20162af32..a4f373f8b798 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -64,6 +64,28 @@ enum { ATA_ID_PROD_LEN = 40, ATA_PCI_CTL_OFS = 2, + + ATA_PIO0 = (1 << 0), + ATA_PIO1 = ATA_PIO0 | (1 << 1), + ATA_PIO2 = ATA_PIO1 | (1 << 2), + ATA_PIO3 = ATA_PIO2 | (1 << 3), + ATA_PIO4 = ATA_PIO3 | (1 << 4), + ATA_PIO5 = ATA_PIO4 | (1 << 5), + ATA_PIO6 = ATA_PIO5 | (1 << 6), + + ATA_SWDMA0 = (1 << 0), + ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1), + ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2), + + ATA_SWDMA2_ONLY = (1 << 2), + + ATA_MWDMA0 = (1 << 0), + ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1), + ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2), + + ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2), + ATA_MWDMA2_ONLY = (1 << 2), + ATA_UDMA0 = (1 << 0), ATA_UDMA1 = ATA_UDMA0 | (1 << 1), ATA_UDMA2 = ATA_UDMA1 | (1 << 2), @@ -208,6 +230,12 @@ enum { SETFEATURES_SPINUP = 0x07, /* Spin-up drive */ + SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */ + SETFEATURES_SATA_DISABLE = 0x90, /* Disable use of SATA feature */ + + /* SETFEATURE Sector counts for SATA features */ + SATA_AN = 0x05, /* Asynchronous Notification */ + /* ATAPI stuff */ ATAPI_PKT_DMA = (1 << 0), ATAPI_DMADIR = (1 << 2), /* ATAPI data dir: @@ -259,6 +287,15 @@ enum { SERR_PROTOCOL = (1 << 10), /* protocol violation */ SERR_INTERNAL = (1 << 11), /* host internal error */ SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */ + SERR_PHY_INT_ERR = (1 << 17), /* PHY internal error */ + SERR_COMM_WAKE = (1 << 18), /* Comm wake */ + SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */ + SERR_DISPARITY = (1 << 20), /* Disparity */ + SERR_CRC = (1 << 21), /* CRC error */ + SERR_HANDSHAKE = (1 << 22), /* Handshake error */ + SERR_LINK_SEQ_ERR = (1 << 23), /* Link sequence error */ + SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */ + SERR_UNRECOG_FIS = (1 << 25), /* Unrecognized FIS */ SERR_DEV_XCHG = (1 << 26), /* device exchanged */ /* struct ata_taskfile flags */ @@ -319,24 +356,17 @@ struct ata_taskfile { }; #define ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0) -#define ata_id_rahead_enabled(id) ((id)[85] & (1 << 6)) -#define ata_id_wcache_enabled(id) ((id)[85] & (1 << 5)) -#define ata_id_hpa_enabled(id) ((id)[85] & (1 << 10)) -#define ata_id_has_fua(id) ((id)[84] & (1 << 6)) -#define ata_id_has_flush(id) ((id)[83] & (1 << 12)) -#define ata_id_has_flush_ext(id) ((id)[83] & (1 << 13)) -#define ata_id_has_lba48(id) ((id)[83] & (1 << 10)) -#define ata_id_has_hpa(id) ((id)[82] & (1 << 10)) -#define ata_id_has_wcache(id) ((id)[82] & (1 << 5)) -#define ata_id_has_pm(id) ((id)[82] & (1 << 3)) #define ata_id_has_lba(id) ((id)[49] & (1 << 9)) #define ata_id_has_dma(id) ((id)[49] & (1 << 8)) #define ata_id_has_ncq(id) ((id)[76] & (1 << 8)) #define ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1) #define ata_id_removeable(id) ((id)[0] & (1 << 7)) -#define ata_id_has_dword_io(id) ((id)[50] & (1 << 0)) +#define ata_id_has_dword_io(id) ((id)[48] & (1 << 0)) +#define ata_id_has_atapi_AN(id) \ + ( (((id)[76] != 0x0000) && ((id)[76] != 0xffff)) && \ + ((id)[78] & (1 << 5)) ) #define ata_id_iordy_disable(id) ((id)[49] & (1 << 10)) -#define ata_id_has_iordy(id) ((id)[49] & (1 << 9)) +#define ata_id_has_iordy(id) ((id)[49] & (1 << 11)) #define ata_id_u32(id,n) \ (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) #define ata_id_u64(id,n) \ @@ -347,6 +377,90 @@ struct ata_taskfile { #define ata_id_cdb_intr(id) (((id)[0] & 0x60) == 0x20) +static inline int ata_id_has_fua(const u16 *id) +{ + if ((id[84] & 0xC000) != 0x4000) + return 0; + return id[84] & (1 << 6); +} + +static inline int ata_id_has_flush(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[83] & (1 << 12); +} + +static inline int ata_id_has_flush_ext(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[83] & (1 << 13); +} + +static inline int ata_id_has_lba48(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[83] & (1 << 10); +} + +static inline int ata_id_hpa_enabled(const u16 *id) +{ + /* Yes children, word 83 valid bits cover word 82 data */ + if ((id[83] & 0xC000) != 0x4000) + return 0; + /* And 87 covers 85-87 */ + if ((id[87] & 0xC000) != 0x4000) + return 0; + /* Check command sets enabled as well as supported */ + if ((id[85] & ( 1 << 10)) == 0) + return 0; + return id[82] & (1 << 10); +} + +static inline int ata_id_has_wcache(const u16 *id) +{ + /* Yes children, word 83 valid bits cover word 82 data */ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[82] & (1 << 5); +} + +static inline int ata_id_has_pm(const u16 *id) +{ + if ((id[83] & 0xC000) != 0x4000) + return 0; + return id[82] & (1 << 3); +} + +static inline int ata_id_rahead_enabled(const u16 *id) +{ + if ((id[87] & 0xC000) != 0x4000) + return 0; + return id[85] & (1 << 6); +} + +static inline int ata_id_wcache_enabled(const u16 *id) +{ + if ((id[87] & 0xC000) != 0x4000) + return 0; + return id[85] & (1 << 5); +} + +/** + * ata_id_major_version - get ATA level of drive + * @id: Identify data + * + * Caveats: + * ATA-1 considers identify optional + * ATA-2 introduces mandatory identify + * ATA-3 introduces word 80 and accurate reporting + * + * The practical impact of this is that ata_id_major_version cannot + * reliably report on drives below ATA3. + */ + static inline unsigned int ata_id_major_version(const u16 *id) { unsigned int mver; diff --git a/include/linux/audit.h b/include/linux/audit.h index 8ca7ca0b47f0..9ae740936a65 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -63,8 +63,8 @@ #define AUDIT_ADD_RULE 1011 /* Add syscall filtering rule */ #define AUDIT_DEL_RULE 1012 /* Delete syscall filtering rule */ #define AUDIT_LIST_RULES 1013 /* List syscall filtering rules */ -#define AUDIT_TTY_GET 1014 /* Get TTY auditing status */ -#define AUDIT_TTY_SET 1015 /* Set TTY auditing status */ +#define AUDIT_TTY_GET 1016 /* Get TTY auditing status */ +#define AUDIT_TTY_SET 1017 /* Set TTY auditing status */ #define AUDIT_FIRST_USER_MSG 1100 /* Userspace messages mostly uninteresting to kernel */ #define AUDIT_USER_AVC 1107 /* We filter this differently */ @@ -108,10 +108,11 @@ #define AUDIT_MAC_CIPSOV4_DEL 1408 /* NetLabel: del CIPSOv4 DOI entry */ #define AUDIT_MAC_MAP_ADD 1409 /* NetLabel: add LSM domain mapping */ #define AUDIT_MAC_MAP_DEL 1410 /* NetLabel: del LSM domain mapping */ -#define AUDIT_MAC_IPSEC_ADDSA 1411 /* Add a XFRM state */ -#define AUDIT_MAC_IPSEC_DELSA 1412 /* Delete a XFRM state */ -#define AUDIT_MAC_IPSEC_ADDSPD 1413 /* Add a XFRM policy */ -#define AUDIT_MAC_IPSEC_DELSPD 1414 /* Delete a XFRM policy */ +#define AUDIT_MAC_IPSEC_ADDSA 1411 /* Not used */ +#define AUDIT_MAC_IPSEC_DELSA 1412 /* Not used */ +#define AUDIT_MAC_IPSEC_ADDSPD 1413 /* Not used */ +#define AUDIT_MAC_IPSEC_DELSPD 1414 /* Not used */ +#define AUDIT_MAC_IPSEC_EVENT 1415 /* Audit an IPSec event */ #define AUDIT_FIRST_KERN_ANOM_MSG 1700 #define AUDIT_LAST_KERN_ANOM_MSG 1799 @@ -161,7 +162,7 @@ * are currently used in an audit field constant understood by the kernel. * If you are adding a new #define AUDIT_<whatever>, please ensure that * AUDIT_UNUSED_BITS is updated if need be. */ -#define AUDIT_UNUSED_BITS 0x0FFFFC00 +#define AUDIT_UNUSED_BITS 0x07FFFC00 /* Rule fields */ @@ -213,25 +214,29 @@ #define AUDIT_NEGATE 0x80000000 /* These are the supported operators. - * 4 2 1 - * = > < - * ------- - * 0 0 0 0 nonsense - * 0 0 1 1 < - * 0 1 0 2 > - * 0 1 1 3 != - * 1 0 0 4 = - * 1 0 1 5 <= - * 1 1 0 6 >= - * 1 1 1 7 all operators + * 4 2 1 8 + * = > < ? + * ---------- + * 0 0 0 0 00 nonsense + * 0 0 0 1 08 & bit mask + * 0 0 1 0 10 < + * 0 1 0 0 20 > + * 0 1 1 0 30 != + * 1 0 0 0 40 = + * 1 0 0 1 48 &= bit test + * 1 0 1 0 50 <= + * 1 1 0 0 60 >= + * 1 1 1 1 78 all operators */ +#define AUDIT_BIT_MASK 0x08000000 #define AUDIT_LESS_THAN 0x10000000 #define AUDIT_GREATER_THAN 0x20000000 #define AUDIT_NOT_EQUAL 0x30000000 #define AUDIT_EQUAL 0x40000000 +#define AUDIT_BIT_TEST (AUDIT_BIT_MASK|AUDIT_EQUAL) #define AUDIT_LESS_THAN_OR_EQUAL (AUDIT_LESS_THAN|AUDIT_EQUAL) #define AUDIT_GREATER_THAN_OR_EQUAL (AUDIT_GREATER_THAN|AUDIT_EQUAL) -#define AUDIT_OPERATORS (AUDIT_EQUAL|AUDIT_NOT_EQUAL) +#define AUDIT_OPERATORS (AUDIT_EQUAL|AUDIT_NOT_EQUAL|AUDIT_BIT_MASK) /* Status symbols */ /* Mask values */ @@ -407,7 +412,6 @@ extern int audit_bprm(struct linux_binprm *bprm); extern int audit_socketcall(int nargs, unsigned long *args); extern int audit_sockaddr(int len, void *addr); extern int __audit_fd_pair(int fd1, int fd2); -extern int audit_avc_path(struct dentry *dentry, struct vfsmount *mnt); extern int audit_set_macxattr(const char *name); extern int __audit_mq_open(int oflag, mode_t mode, struct mq_attr __user *u_attr); extern int __audit_mq_timedsend(mqd_t mqdes, size_t msg_len, unsigned int msg_prio, const struct timespec __user *u_abs_timeout); @@ -487,7 +491,6 @@ extern int audit_signals; #define audit_socketcall(n,a) ({ 0; }) #define audit_fd_pair(n,a) ({ 0; }) #define audit_sockaddr(len, addr) ({ 0; }) -#define audit_avc_path(dentry, mnt) ({ 0; }) #define audit_set_macxattr(n) do { ; } while (0) #define audit_mq_open(o,m,a) ({ 0; }) #define audit_mq_timedsend(d,l,p,t) ({ 0; }) diff --git a/include/linux/backlight.h b/include/linux/backlight.h index 1023ba0d6e55..1ee9488ca2e4 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -69,8 +69,8 @@ struct backlight_device { /* The framebuffer notifier block */ struct notifier_block fb_notif; - /* The class device structure */ - struct class_device class_dev; + + struct device dev; }; static inline void backlight_update_status(struct backlight_device *bd) @@ -85,6 +85,20 @@ extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, struct backlight_ops *ops); extern void backlight_device_unregister(struct backlight_device *bd); -#define to_backlight_device(obj) container_of(obj, struct backlight_device, class_dev) +#define to_backlight_device(obj) container_of(obj, struct backlight_device, dev) + +static inline void * bl_get_data(struct backlight_device *bl_dev) +{ + return dev_get_drvdata(&bl_dev->dev); +} + +struct generic_bl_info { + const char *name; + int max_intensity; + int default_intensity; + int limit_mask; + void (*set_bl_intensity)(int intensity); + void (*kick_battery)(void); +}; #endif diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h index e1a708337be3..91c8c07fe8b7 100644 --- a/include/linux/binfmts.h +++ b/include/linux/binfmts.h @@ -6,11 +6,13 @@ struct pt_regs; /* - * MAX_ARG_PAGES defines the number of pages allocated for arguments - * and envelope for the new program. 32 should suffice, this gives - * a maximum env+arg of 128kB w/4KB pages! + * These are the maximum length and maximum number of strings passed to the + * execve() system call. MAX_ARG_STRLEN is essentially random but serves to + * prevent the kernel from being unduly impacted by misaddressed pointers. + * MAX_ARG_STRINGS is chosen to fit in a signed 32-bit integer. */ -#define MAX_ARG_PAGES 32 +#define MAX_ARG_STRLEN (PAGE_SIZE * 32) +#define MAX_ARG_STRINGS 0x7FFFFFFF /* sizeof(linux_binprm->buf) */ #define BINPRM_BUF_SIZE 128 @@ -24,7 +26,12 @@ struct pt_regs; */ struct linux_binprm{ char buf[BINPRM_BUF_SIZE]; +#ifdef CONFIG_MMU + struct vm_area_struct *vma; +#else +# define MAX_ARG_PAGES 32 struct page *page[MAX_ARG_PAGES]; +#endif struct mm_struct *mm; unsigned long p; /* current top of mem */ int sh_bang; @@ -40,6 +47,7 @@ struct linux_binprm{ unsigned interp_flags; unsigned interp_data; unsigned long loader, exec; + unsigned long argv_len; }; #define BINPRM_FLAGS_ENFORCE_NONDUMP_BIT 0 @@ -68,7 +76,7 @@ extern int register_binfmt(struct linux_binfmt *); extern int unregister_binfmt(struct linux_binfmt *); extern int prepare_binprm(struct linux_binprm *); -extern void remove_arg_zero(struct linux_binprm *); +extern int __must_check remove_arg_zero(struct linux_binprm *); extern int search_binary_handler(struct linux_binprm *,struct pt_regs *); extern int flush_old_exec(struct linux_binprm * bprm); @@ -85,6 +93,7 @@ extern int suid_dumpable; extern int setup_arg_pages(struct linux_binprm * bprm, unsigned long stack_top, int executable_stack); +extern int bprm_mm_init(struct linux_binprm *bprm); extern int copy_strings_kernel(int argc,char ** argv,struct linux_binprm *bprm); extern void compute_creds(struct linux_binprm *binprm); extern int do_coredump(long signr, int exit_code, struct pt_regs * regs); diff --git a/include/linux/bio.h b/include/linux/bio.h index 4d85262b4fa4..089a8bc55dd4 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -24,6 +24,8 @@ #include <linux/mempool.h> #include <linux/ioprio.h> +#ifdef CONFIG_BLOCK + /* Platforms may set this to teach the BIO layer about IOMMU hardware. */ #include <asm/io.h> @@ -62,7 +64,7 @@ struct bio_vec { struct bio_set; struct bio; -typedef int (bio_end_io_t) (struct bio *, unsigned int, int); +typedef void (bio_end_io_t) (struct bio *, int); typedef void (bio_destructor_t) (struct bio *); /* @@ -224,7 +226,7 @@ struct bio { #define BIO_SEG_BOUNDARY(q, b1, b2) \ BIOVEC_SEG_BOUNDARY((q), __BVEC_END((b1)), __BVEC_START((b2))) -#define bio_io_error(bio, bytes) bio_endio((bio), (bytes), -EIO) +#define bio_io_error(bio) bio_endio((bio), -EIO) /* * drivers should not use the __ version unless they _really_ want to @@ -284,7 +286,7 @@ extern struct bio *bio_alloc_bioset(gfp_t, int, struct bio_set *); extern void bio_put(struct bio *); extern void bio_free(struct bio *, struct bio_set *); -extern void bio_endio(struct bio *, unsigned int, int); +extern void bio_endio(struct bio *, int); struct request_queue; extern int bio_phys_segments(struct request_queue *, struct bio *); extern int bio_hw_segments(struct request_queue *, struct bio *); @@ -361,4 +363,5 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx, __bio_kmap_irq((bio), (bio)->bi_idx, (flags)) #define bio_kunmap_irq(buf,flags) __bio_kunmap_irq(buf, flags) +#endif /* CONFIG_BLOCK */ #endif /* __LINUX_BIO_H */ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index f78965fc6426..5ed888b04b29 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -1,6 +1,8 @@ #ifndef _LINUX_BLKDEV_H #define _LINUX_BLKDEV_H +#ifdef CONFIG_BLOCK + #include <linux/sched.h> #include <linux/major.h> #include <linux/genhd.h> @@ -18,26 +20,10 @@ #include <asm/scatterlist.h> -#ifdef CONFIG_LBD -# include <asm/div64.h> -# define sector_div(a, b) do_div(a, b) -#else -# define sector_div(n, b)( \ -{ \ - int _res; \ - _res = (n) % (b); \ - (n) /= (b); \ - _res; \ -} \ -) -#endif - -#ifdef CONFIG_BLOCK - struct scsi_ioctl_command; struct request_queue; -typedef struct request_queue request_queue_t; +typedef struct request_queue request_queue_t __deprecated; struct elevator_queue; typedef struct elevator_queue elevator_t; struct request_pm_state; @@ -233,7 +219,7 @@ struct request { struct list_head queuelist; struct list_head donelist; - request_queue_t *q; + struct request_queue *q; unsigned int cmd_flags; enum rq_cmd_type_bits cmd_type; @@ -337,15 +323,15 @@ struct request_pm_state #include <linux/elevator.h> -typedef void (request_fn_proc) (request_queue_t *q); -typedef int (make_request_fn) (request_queue_t *q, struct bio *bio); -typedef int (prep_rq_fn) (request_queue_t *, struct request *); -typedef void (unplug_fn) (request_queue_t *); +typedef void (request_fn_proc) (struct request_queue *q); +typedef int (make_request_fn) (struct request_queue *q, struct bio *bio); +typedef int (prep_rq_fn) (struct request_queue *, struct request *); +typedef void (unplug_fn) (struct request_queue *); struct bio_vec; -typedef int (merge_bvec_fn) (request_queue_t *, struct bio *, struct bio_vec *); -typedef int (issue_flush_fn) (request_queue_t *, struct gendisk *, sector_t *); -typedef void (prepare_flush_fn) (request_queue_t *, struct request *); +typedef int (merge_bvec_fn) (struct request_queue *, struct bio *, struct bio_vec *); +typedef int (issue_flush_fn) (struct request_queue *, struct gendisk *, sector_t *); +typedef void (prepare_flush_fn) (struct request_queue *, struct request *); typedef void (softirq_done_fn)(struct request *); enum blk_queue_state { @@ -471,7 +457,6 @@ struct request_queue int orderr, ordcolor; struct request pre_flush_rq, bar_rq, post_flush_rq; struct request *orig_bar_rq; - unsigned int bi_size; struct mutex sysfs_lock; @@ -483,8 +468,8 @@ struct request_queue #define QUEUE_FLAG_CLUSTER 0 /* cluster several segments into 1 */ #define QUEUE_FLAG_QUEUED 1 /* uses generic tag queueing */ #define QUEUE_FLAG_STOPPED 2 /* queue is stopped */ -#define QUEUE_FLAG_READFULL 3 /* write queue has been filled */ -#define QUEUE_FLAG_WRITEFULL 4 /* read queue has been filled */ +#define QUEUE_FLAG_READFULL 3 /* read queue has been filled */ +#define QUEUE_FLAG_WRITEFULL 4 /* write queue has been filled */ #define QUEUE_FLAG_DEAD 5 /* queue being torn down */ #define QUEUE_FLAG_REENTER 6 /* Re-entrancy avoidance */ #define QUEUE_FLAG_PLUGGED 7 /* queue is plugged */ @@ -626,34 +611,47 @@ extern unsigned long blk_max_low_pfn, blk_max_pfn; #ifdef CONFIG_BOUNCE extern int init_emergency_isa_pool(void); -extern void blk_queue_bounce(request_queue_t *q, struct bio **bio); +extern void blk_queue_bounce(struct request_queue *q, struct bio **bio); #else static inline int init_emergency_isa_pool(void) { return 0; } -static inline void blk_queue_bounce(request_queue_t *q, struct bio **bio) +static inline void blk_queue_bounce(struct request_queue *q, struct bio **bio) { } #endif /* CONFIG_MMU */ -#define rq_for_each_bio(_bio, rq) \ +struct req_iterator { + int i; + struct bio *bio; +}; + +/* This should not be used directly - use rq_for_each_segment */ +#define __rq_for_each_bio(_bio, rq) \ if ((rq->bio)) \ for (_bio = (rq)->bio; _bio; _bio = _bio->bi_next) +#define rq_for_each_segment(bvl, _rq, _iter) \ + __rq_for_each_bio(_iter.bio, _rq) \ + bio_for_each_segment(bvl, _iter.bio, _iter.i) + +#define rq_iter_last(rq, _iter) \ + (_iter.bio->bi_next == NULL && _iter.i == _iter.bio->bi_vcnt-1) + extern int blk_register_queue(struct gendisk *disk); extern void blk_unregister_queue(struct gendisk *disk); extern void register_disk(struct gendisk *dev); extern void generic_make_request(struct bio *bio); extern void blk_put_request(struct request *); -extern void __blk_put_request(request_queue_t *, struct request *); +extern void __blk_put_request(struct request_queue *, struct request *); extern void blk_end_sync_rq(struct request *rq, int error); -extern struct request *blk_get_request(request_queue_t *, int, gfp_t); -extern void blk_insert_request(request_queue_t *, struct request *, int, void *); -extern void blk_requeue_request(request_queue_t *, struct request *); -extern void blk_plug_device(request_queue_t *); -extern int blk_remove_plug(request_queue_t *); -extern void blk_recount_segments(request_queue_t *, struct bio *); +extern struct request *blk_get_request(struct request_queue *, int, gfp_t); +extern void blk_insert_request(struct request_queue *, struct request *, int, void *); +extern void blk_requeue_request(struct request_queue *, struct request *); +extern void blk_plug_device(struct request_queue *); +extern int blk_remove_plug(struct request_queue *); +extern void blk_recount_segments(struct request_queue *, struct bio *); extern int scsi_cmd_ioctl(struct file *, struct request_queue *, struct gendisk *, unsigned int, void __user *); extern int sg_scsi_ioctl(struct file *, struct request_queue *, @@ -662,14 +660,15 @@ extern int sg_scsi_ioctl(struct file *, struct request_queue *, /* * Temporary export, until SCSI gets fixed up. */ -extern int ll_back_merge_fn(request_queue_t *, struct request *, struct bio *); +extern int blk_rq_append_bio(struct request_queue *q, struct request *rq, + struct bio *bio); /* * A queue has just exitted congestion. Note this in the global counter of * congested queues, and wake up anyone who was waiting for requests to be * put back. */ -static inline void blk_clear_queue_congested(request_queue_t *q, int rw) +static inline void blk_clear_queue_congested(struct request_queue *q, int rw) { clear_bdi_congested(&q->backing_dev_info, rw); } @@ -678,34 +677,29 @@ static inline void blk_clear_queue_congested(request_queue_t *q, int rw) * A queue has just entered congestion. Flag that in the queue's VM-visible * state flags and increment the global gounter of congested queues. */ -static inline void blk_set_queue_congested(request_queue_t *q, int rw) +static inline void blk_set_queue_congested(struct request_queue *q, int rw) { set_bdi_congested(&q->backing_dev_info, rw); } -extern void blk_start_queue(request_queue_t *q); -extern void blk_stop_queue(request_queue_t *q); +extern void blk_start_queue(struct request_queue *q); +extern void blk_stop_queue(struct request_queue *q); extern void blk_sync_queue(struct request_queue *q); -extern void __blk_stop_queue(request_queue_t *q); -extern void blk_run_queue(request_queue_t *); -extern void blk_start_queueing(request_queue_t *); -extern int blk_rq_map_user(request_queue_t *, struct request *, void __user *, unsigned long); +extern void __blk_stop_queue(struct request_queue *q); +extern void blk_run_queue(struct request_queue *); +extern void blk_start_queueing(struct request_queue *); +extern int blk_rq_map_user(struct request_queue *, struct request *, void __user *, unsigned long); extern int blk_rq_unmap_user(struct bio *); -extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, gfp_t); -extern int blk_rq_map_user_iov(request_queue_t *, struct request *, +extern int blk_rq_map_kern(struct request_queue *, struct request *, void *, unsigned int, gfp_t); +extern int blk_rq_map_user_iov(struct request_queue *, struct request *, struct sg_iovec *, int, unsigned int); -extern int blk_execute_rq(request_queue_t *, struct gendisk *, +extern int blk_execute_rq(struct request_queue *, struct gendisk *, struct request *, int); -extern void blk_execute_rq_nowait(request_queue_t *, struct gendisk *, +extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *, struct request *, int, rq_end_io_fn *); -extern int blk_fill_sghdr_rq(request_queue_t *, struct request *, - struct sg_io_hdr *, int); -extern int blk_unmap_sghdr_rq(struct request *, struct sg_io_hdr *); -extern int blk_complete_sghdr_rq(struct request *, struct sg_io_hdr *, - struct bio *); extern int blk_verify_command(unsigned char *, int); -static inline request_queue_t *bdev_get_queue(struct block_device *bdev) +static inline struct request_queue *bdev_get_queue(struct block_device *bdev) { return bdev->bd_disk->queue; } @@ -754,41 +748,41 @@ static inline void blkdev_dequeue_request(struct request *req) /* * Access functions for manipulating queue properties */ -extern request_queue_t *blk_init_queue_node(request_fn_proc *rfn, +extern struct request_queue *blk_init_queue_node(request_fn_proc *rfn, spinlock_t *lock, int node_id); -extern request_queue_t *blk_init_queue(request_fn_proc *, spinlock_t *); -extern void blk_cleanup_queue(request_queue_t *); -extern void blk_queue_make_request(request_queue_t *, make_request_fn *); -extern void blk_queue_bounce_limit(request_queue_t *, u64); -extern void blk_queue_max_sectors(request_queue_t *, unsigned int); -extern void blk_queue_max_phys_segments(request_queue_t *, unsigned short); -extern void blk_queue_max_hw_segments(request_queue_t *, unsigned short); -extern void blk_queue_max_segment_size(request_queue_t *, unsigned int); -extern void blk_queue_hardsect_size(request_queue_t *, unsigned short); -extern void blk_queue_stack_limits(request_queue_t *t, request_queue_t *b); -extern void blk_queue_segment_boundary(request_queue_t *, unsigned long); -extern void blk_queue_prep_rq(request_queue_t *, prep_rq_fn *pfn); -extern void blk_queue_merge_bvec(request_queue_t *, merge_bvec_fn *); -extern void blk_queue_dma_alignment(request_queue_t *, int); -extern void blk_queue_softirq_done(request_queue_t *, softirq_done_fn *); +extern struct request_queue *blk_init_queue(request_fn_proc *, spinlock_t *); +extern void blk_cleanup_queue(struct request_queue *); +extern void blk_queue_make_request(struct request_queue *, make_request_fn *); +extern void blk_queue_bounce_limit(struct request_queue *, u64); +extern void blk_queue_max_sectors(struct request_queue *, unsigned int); +extern void blk_queue_max_phys_segments(struct request_queue *, unsigned short); +extern void blk_queue_max_hw_segments(struct request_queue *, unsigned short); +extern void blk_queue_max_segment_size(struct request_queue *, unsigned int); +extern void blk_queue_hardsect_size(struct request_queue *, unsigned short); +extern void blk_queue_stack_limits(struct request_queue *t, struct request_queue *b); +extern void blk_queue_segment_boundary(struct request_queue *, unsigned long); +extern void blk_queue_prep_rq(struct request_queue *, prep_rq_fn *pfn); +extern void blk_queue_merge_bvec(struct request_queue *, merge_bvec_fn *); +extern void blk_queue_dma_alignment(struct request_queue *, int); +extern void blk_queue_softirq_done(struct request_queue *, softirq_done_fn *); extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev); -extern int blk_queue_ordered(request_queue_t *, unsigned, prepare_flush_fn *); -extern void blk_queue_issue_flush_fn(request_queue_t *, issue_flush_fn *); -extern int blk_do_ordered(request_queue_t *, struct request **); -extern unsigned blk_ordered_cur_seq(request_queue_t *); +extern int blk_queue_ordered(struct request_queue *, unsigned, prepare_flush_fn *); +extern void blk_queue_issue_flush_fn(struct request_queue *, issue_flush_fn *); +extern int blk_do_ordered(struct request_queue *, struct request **); +extern unsigned blk_ordered_cur_seq(struct request_queue *); extern unsigned blk_ordered_req_seq(struct request *); -extern void blk_ordered_complete_seq(request_queue_t *, unsigned, int); +extern void blk_ordered_complete_seq(struct request_queue *, unsigned, int); -extern int blk_rq_map_sg(request_queue_t *, struct request *, struct scatterlist *); +extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *); extern void blk_dump_rq_flags(struct request *, char *); -extern void generic_unplug_device(request_queue_t *); -extern void __generic_unplug_device(request_queue_t *); +extern void generic_unplug_device(struct request_queue *); +extern void __generic_unplug_device(struct request_queue *); extern long nr_blockdev_pages(void); -int blk_get_queue(request_queue_t *); -request_queue_t *blk_alloc_queue(gfp_t); -request_queue_t *blk_alloc_queue_node(gfp_t, int); -extern void blk_put_queue(request_queue_t *); +int blk_get_queue(struct request_queue *); +struct request_queue *blk_alloc_queue(gfp_t); +struct request_queue *blk_alloc_queue_node(gfp_t, int); +extern void blk_put_queue(struct request_queue *); /* * tag stuff @@ -796,13 +790,13 @@ extern void blk_put_queue(request_queue_t *); #define blk_queue_tag_depth(q) ((q)->queue_tags->busy) #define blk_queue_tag_queue(q) ((q)->queue_tags->busy < (q)->queue_tags->max_depth) #define blk_rq_tagged(rq) ((rq)->cmd_flags & REQ_QUEUED) -extern int blk_queue_start_tag(request_queue_t *, struct request *); -extern struct request *blk_queue_find_tag(request_queue_t *, int); -extern void blk_queue_end_tag(request_queue_t *, struct request *); -extern int blk_queue_init_tags(request_queue_t *, int, struct blk_queue_tag *); -extern void blk_queue_free_tags(request_queue_t *); -extern int blk_queue_resize_tags(request_queue_t *, int); -extern void blk_queue_invalidate_tags(request_queue_t *); +extern int blk_queue_start_tag(struct request_queue *, struct request *); +extern struct request *blk_queue_find_tag(struct request_queue *, int); +extern void blk_queue_end_tag(struct request_queue *, struct request *); +extern int blk_queue_init_tags(struct request_queue *, int, struct blk_queue_tag *); +extern void blk_queue_free_tags(struct request_queue *); +extern int blk_queue_resize_tags(struct request_queue *, int); +extern void blk_queue_invalidate_tags(struct request_queue *); extern struct blk_queue_tag *blk_init_tags(int); extern void blk_free_tags(struct blk_queue_tag *); @@ -814,7 +808,6 @@ static inline struct request *blk_map_queue_find_tag(struct blk_queue_tag *bqt, return bqt->tag_index[tag]; } -extern void blk_rq_bio_prep(request_queue_t *, struct request *, struct bio *); extern int blkdev_issue_flush(struct block_device *, sector_t *); #define MAX_PHYS_SEGMENTS 128 @@ -826,7 +819,7 @@ extern int blkdev_issue_flush(struct block_device *, sector_t *); #define blkdev_entry_to_request(entry) list_entry((entry), struct request, queuelist) -static inline int queue_hardsect_size(request_queue_t *q) +static inline int queue_hardsect_size(struct request_queue *q) { int retval = 512; @@ -841,7 +834,7 @@ static inline int bdev_hardsect_size(struct block_device *bdev) return queue_hardsect_size(bdev_get_queue(bdev)); } -static inline int queue_dma_alignment(request_queue_t *q) +static inline int queue_dma_alignment(struct request_queue *q) { int retval = 511; diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h index 3680ff9a30ed..7e11d23ac36a 100644 --- a/include/linux/blktrace_api.h +++ b/include/linux/blktrace_api.h @@ -105,7 +105,7 @@ struct blk_io_trace { */ struct blk_io_trace_remap { __be32 device; - u32 __pad; + __be32 device_from; __be64 sector; }; @@ -142,10 +142,14 @@ struct blk_user_trace_setup { u32 pid; }; +#ifdef __KERNEL__ #if defined(CONFIG_BLK_DEV_IO_TRACE) extern int blk_trace_ioctl(struct block_device *, unsigned, char __user *); -extern void blk_trace_shutdown(request_queue_t *); +extern void blk_trace_shutdown(struct request_queue *); extern void __blk_add_trace(struct blk_trace *, sector_t, int, int, u32, int, int, void *); +extern int do_blk_trace_setup(struct request_queue *q, + struct block_device *bdev, struct blk_user_trace_setup *buts); + /** * blk_add_trace_rq - Add a trace for a request oriented action @@ -272,6 +276,7 @@ static inline void blk_add_trace_remap(struct request_queue *q, struct bio *bio, return; r.device = cpu_to_be32(dev); + r.device_from = cpu_to_be32(bio->bi_bdev->bd_dev); r.sector = cpu_to_be64(to); __blk_add_trace(bt, from, bio->bi_size, bio->bi_rw, BLK_TA_REMAP, !bio_flagged(bio, BIO_UPTODATE), sizeof(r), &r); @@ -285,6 +290,7 @@ static inline void blk_add_trace_remap(struct request_queue *q, struct bio *bio, #define blk_add_trace_generic(q, rq, rw, what) do { } while (0) #define blk_add_trace_pdu_int(q, what, bio, pdu) do { } while (0) #define blk_add_trace_remap(q, bio, dev, f, t) do {} while (0) +#define do_blk_trace_setup(q, bdev, buts) (-ENOTTY) #endif /* CONFIG_BLK_DEV_IO_TRACE */ - +#endif /* __KERNEL__ */ #endif diff --git a/include/linux/bsg.h b/include/linux/bsg.h index 8547b10c388b..60e377b520f8 100644 --- a/include/linux/bsg.h +++ b/include/linux/bsg.h @@ -15,14 +15,18 @@ struct sg_io_v4 { __u32 request_len; /* [i] in bytes */ __u64 request; /* [i], [*i] {SCSI: cdb} */ + __u64 request_tag; /* [i] {SCSI: task tag (only if flagged)} */ __u32 request_attr; /* [i] {SCSI: task attribute} */ - __u32 request_tag; /* [i] {SCSI: task tag (only if flagged)} */ __u32 request_priority; /* [i] {SCSI: task priority} */ + __u32 request_extra; /* [i] {spare, for padding} */ __u32 max_response_len; /* [i] in bytes */ __u64 response; /* [i], [*o] {SCSI: (auto)sense data} */ - /* "din_" for data in (from device); "dout_" for data out (to device) */ + /* "dout_": data out (to device); "din_": data in (from device) */ + __u32 dout_iovec_count; /* [i] 0 -> "flat" dout transfer else + dout_xfer points to array of iovec */ __u32 dout_xfer_len; /* [i] bytes to be transferred to device */ + __u32 din_iovec_count; /* [i] 0 -> "flat" din transfer */ __u32 din_xfer_len; /* [i] bytes to be transferred from device */ __u64 dout_xferp; /* [i], [*i] */ __u64 din_xferp; /* [i], [*o] */ @@ -39,8 +43,9 @@ struct sg_io_v4 { __u32 info; /* [o] additional information */ __u32 duration; /* [o] time to complete, in milliseconds */ __u32 response_len; /* [o] bytes of response actually written */ - __s32 din_resid; /* [o] actual_din_xfer_len - din_xfer_len */ - __u32 generated_tag; /* [o] {SCSI: task tag that transport chose} */ + __s32 din_resid; /* [o] din_xfer_len - actual_din_xfer_len */ + __s32 dout_resid; /* [o] dout_xfer_len - actual_dout_xfer_len */ + __u64 generated_tag; /* [o] {SCSI: transport generated task tag} */ __u32 spare_out; /* [o] */ __u32 padding; @@ -53,15 +58,19 @@ struct bsg_class_device { struct class_device *class_dev; struct device *dev; int minor; - struct list_head list; struct request_queue *queue; }; -extern int bsg_register_queue(struct request_queue *, const char *); +extern int bsg_register_queue(struct request_queue *, struct device *, const char *); extern void bsg_unregister_queue(struct request_queue *); #else -#define bsg_register_queue(disk, name) (0) -#define bsg_unregister_queue(disk) do { } while (0) +static inline int bsg_register_queue(struct request_queue * rq, struct device *dev, const char *name) +{ + return 0; +} +static inline void bsg_unregister_queue(struct request_queue *rq) +{ +} #endif #endif /* __KERNEL__ */ diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h index 5c6e12853a9b..35cadad84b14 100644 --- a/include/linux/buffer_head.h +++ b/include/linux/buffer_head.h @@ -209,6 +209,8 @@ int cont_prepare_write(struct page*, unsigned, unsigned, get_block_t*, int generic_cont_expand(struct inode *inode, loff_t size); int generic_cont_expand_simple(struct inode *inode, loff_t size); int block_commit_write(struct page *page, unsigned from, unsigned to); +int block_page_mkwrite(struct vm_area_struct *vma, struct page *page, + get_block_t get_block); void block_sync_page(struct page *); sector_t generic_block_bmap(struct address_space *, sector_t, get_block_t *); int generic_commit_write(struct file *, struct page *, unsigned, unsigned); diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h index 8486e78f7335..d2ddea926895 100644 --- a/include/linux/clockchips.h +++ b/include/linux/clockchips.h @@ -8,7 +8,7 @@ #ifndef _LINUX_CLOCKCHIPS_H #define _LINUX_CLOCKCHIPS_H -#ifdef CONFIG_GENERIC_CLOCKEVENTS +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BUILD #include <linux/clocksource.h> #include <linux/cpumask.h> @@ -23,6 +23,7 @@ enum clock_event_mode { CLOCK_EVT_MODE_SHUTDOWN, CLOCK_EVT_MODE_PERIODIC, CLOCK_EVT_MODE_ONESHOT, + CLOCK_EVT_MODE_RESUME, }; /* Clock event notification values */ @@ -119,22 +120,20 @@ extern void clockevents_register_device(struct clock_event_device *dev); extern void clockevents_exchange_device(struct clock_event_device *old, struct clock_event_device *new); -extern -struct clock_event_device *clockevents_request_device(unsigned int features, - cpumask_t cpumask); -extern void clockevents_release_device(struct clock_event_device *dev); extern void clockevents_set_mode(struct clock_event_device *dev, enum clock_event_mode mode); extern int clockevents_register_notifier(struct notifier_block *nb); -extern void clockevents_unregister_notifier(struct notifier_block *nb); extern int clockevents_program_event(struct clock_event_device *dev, ktime_t expires, ktime_t now); +#ifdef CONFIG_GENERIC_CLOCKEVENTS extern void clockevents_notify(unsigned long reason, void *arg); - #else +# define clockevents_notify(reason, arg) do { } while (0) +#endif + +#else /* CONFIG_GENERIC_CLOCKEVENTS_BUILD */ -static inline void clockevents_resume_events(void) { } #define clockevents_notify(reason, arg) do { } while (0) #endif diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index bf297b03a4e4..16ea3374dddf 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -67,6 +67,12 @@ struct clocksource { unsigned long flags; cycle_t (*vread)(void); void (*resume)(void); +#ifdef CONFIG_IA64 + void *fsys_mmio; /* used by fsyscall asm code */ +#define CLKSRC_FSYS_MMIO_SET(mmio, addr) ((mmio) = (addr)) +#else +#define CLKSRC_FSYS_MMIO_SET(mmio, addr) do { } while (0) +#endif /* timekeeping specific data, ignore */ cycle_t cycle_interval; diff --git a/include/linux/coda_linux.h b/include/linux/coda_linux.h index e4ac016ad272..1c47a34aa794 100644 --- a/include/linux/coda_linux.h +++ b/include/linux/coda_linux.h @@ -36,16 +36,12 @@ extern const struct file_operations coda_ioctl_operations; /* operations shared over more than one file */ int coda_open(struct inode *i, struct file *f); -int coda_flush(struct file *f, fl_owner_t id); int coda_release(struct inode *i, struct file *f); int coda_permission(struct inode *inode, int mask, struct nameidata *nd); int coda_revalidate_inode(struct dentry *); int coda_getattr(struct vfsmount *, struct dentry *, struct kstat *); int coda_setattr(struct dentry *, struct iattr *); -/* global variables */ -extern int coda_fake_statfs; - /* this file: heloers */ static __inline__ struct CodaFid *coda_i2f(struct inode *); static __inline__ char *coda_i2s(struct inode *); diff --git a/include/linux/coda_proc.h b/include/linux/coda_proc.h deleted file mode 100644 index 0dc1b0458e75..000000000000 --- a/include/linux/coda_proc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * coda_statis.h - * - * CODA operation statistics - * - * (c) March, 1998 - * by Michihiro Kuramochi, Zhenyu Xia and Zhanyong Wan - * zhanyong.wan@yale.edu - * - */ - -#ifndef _CODA_PROC_H -#define _CODA_PROC_H - -void coda_sysctl_init(void); -void coda_sysctl_clean(void); - -#include <linux/sysctl.h> -#include <linux/coda_fs_i.h> -#include <linux/coda.h> - -/* these four files are presented to show the result of the statistics: - * - * /proc/fs/coda/vfs_stats - * cache_inv_stats - * - * these four files are presented to reset the statistics to 0: - * - * /proc/sys/coda/vfs_stats - * cache_inv_stats - */ - -/* VFS operation statistics */ -struct coda_vfs_stats -{ - /* file operations */ - int open; - int flush; - int release; - int fsync; - - /* dir operations */ - int readdir; - - /* inode operations */ - int create; - int lookup; - int link; - int unlink; - int symlink; - int mkdir; - int rmdir; - int rename; - int permission; - - /* symlink operatoins*/ - int follow_link; - int readlink; -}; - -/* cache invalidation statistics */ -struct coda_cache_inv_stats -{ - int flush; - int purge_user; - int zap_dir; - int zap_file; - int zap_vnode; - int purge_fid; - int replace; -}; - -/* these global variables hold the actual statistics data */ -extern struct coda_vfs_stats coda_vfs_stat; - -#endif /* _CODA_PROC_H */ diff --git a/include/linux/coda_psdev.h b/include/linux/coda_psdev.h index b541bb3d1f4b..07ae8f846055 100644 --- a/include/linux/coda_psdev.h +++ b/include/linux/coda_psdev.h @@ -8,11 +8,6 @@ struct kstatfs; -struct coda_sb_info -{ - struct venus_comm *sbi_vcomm; -}; - /* communication pending/processing queues */ struct venus_comm { u_long vc_seq; @@ -24,9 +19,9 @@ struct venus_comm { }; -static inline struct coda_sb_info *coda_sbp(struct super_block *sb) +static inline struct venus_comm *coda_vcp(struct super_block *sb) { - return ((struct coda_sb_info *)((sb)->s_fs_info)); + return (struct venus_comm *)((sb)->s_fs_info); } @@ -38,9 +33,6 @@ int venus_setattr(struct super_block *, struct CodaFid *, struct coda_vattr *); int venus_lookup(struct super_block *sb, struct CodaFid *fid, const char *name, int length, int *type, struct CodaFid *resfid); -int venus_store(struct super_block *sb, struct CodaFid *fid, int flags, - vuid_t uid); -int venus_release(struct super_block *sb, struct CodaFid *fid, int flags); int venus_close(struct super_block *sb, struct CodaFid *fid, int flags, vuid_t uid); int venus_open(struct super_block *sb, struct CodaFid *fid, int flags, @@ -74,8 +66,6 @@ int venus_statfs(struct dentry *dentry, struct kstatfs *sfs); /* messages between coda filesystem in kernel and Venus */ -extern int coda_hard; -extern unsigned long coda_timeout; struct upc_req { struct list_head uc_chain; caddr_t uc_data; @@ -85,7 +75,6 @@ struct upc_req { u_short uc_opcode; /* copied from data to save lookup */ int uc_unique; wait_queue_head_t uc_sleep; /* process' wait queue */ - unsigned long uc_posttime; }; #define REQ_ASYNC 0x1 diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h index a03e9398a6c2..14f7494280f0 100644 --- a/include/linux/compiler-gcc4.h +++ b/include/linux/compiler-gcc4.h @@ -23,3 +23,21 @@ * code */ #define uninitialized_var(x) x = x + +#if !(__GNUC__ == 4 && __GNUC_MINOR__ < 3) +/* Mark functions as cold. gcc will assume any path leading to a call + to them will be unlikely. This means a lot of manual unlikely()s + are unnecessary now for any paths leading to the usual suspects + like BUG(), printk(), panic() etc. [but let's keep them for now for + older compilers] + + Early snapshots of gcc 4.3 don't support this and we can't detect this + in the preprocessor, but we can live with this because they're unreleased. + Maketime probing would be overkill here. + + gcc also has a __attribute__((__hot__)) to move hot functions into + a special section, but I don't see any sense in this right now in + the kernel context */ +#define __cold __attribute__((__cold__)) + +#endif diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 8287a72bb6a9..86f9a3a6137d 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -15,8 +15,8 @@ # define __acquire(x) __context__(x,1) # define __release(x) __context__(x,-1) # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) -extern void __chk_user_ptr(const void __user *); -extern void __chk_io_ptr(const void __iomem *); +extern void __chk_user_ptr(const volatile void __user *); +extern void __chk_io_ptr(const volatile void __iomem *); #else # define __user # define __kernel @@ -174,4 +174,13 @@ extern void __chk_io_ptr(const void __iomem *); # define __attribute_const__ /* unimplemented */ #endif +/* + * Tell gcc if a function is cold. The compiler will assume any path + * directly leading to the call is unlikely. + */ + +#ifndef __cold +#define __cold +#endif + #endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/connector.h b/include/linux/connector.h index 10eb56b2940a..b62f823e90cf 100644 --- a/include/linux/connector.h +++ b/include/linux/connector.h @@ -153,7 +153,7 @@ struct cn_dev { u32 seq, groups; struct sock *nls; - void (*input) (struct sock * sk, int len); + void (*input) (struct sk_buff *skb); struct cn_queue_dev *cbdev; }; diff --git a/include/linux/cpu.h b/include/linux/cpu.h index c2236bbff412..0ad72c4cf312 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -41,8 +41,6 @@ extern void cpu_remove_sysdev_attr(struct sysdev_attribute *attr); extern int cpu_add_sysdev_attr_group(struct attribute_group *attrs); extern void cpu_remove_sysdev_attr_group(struct attribute_group *attrs); -extern struct sysdev_attribute attr_sched_mc_power_savings; -extern struct sysdev_attribute attr_sched_smt_power_savings; extern int sched_create_sysfs_power_savings_entries(struct sysdev_class *cls); #ifdef CONFIG_HOTPLUG_CPU @@ -128,16 +126,16 @@ static inline void cpuhotplug_mutex_unlock(struct mutex *cpu_hp_mutex) static inline int cpu_is_offline(int cpu) { return 0; } #endif /* CONFIG_HOTPLUG_CPU */ -#ifdef CONFIG_SUSPEND_SMP +#ifdef CONFIG_PM_SLEEP_SMP extern int suspend_cpu_hotplug; extern int disable_nonboot_cpus(void); extern void enable_nonboot_cpus(void); -#else +#else /* !CONFIG_PM_SLEEP_SMP */ #define suspend_cpu_hotplug 0 static inline int disable_nonboot_cpus(void) { return 0; } static inline void enable_nonboot_cpus(void) {} -#endif +#endif /* !CONFIG_PM_SLEEP_SMP */ #endif /* _LINUX_CPU_H_ */ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 963051a967d6..23932d7741a9 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -32,20 +32,24 @@ * CPUFREQ NOTIFIER INTERFACE * *********************************************************************/ +#define CPUFREQ_TRANSITION_NOTIFIER (0) +#define CPUFREQ_POLICY_NOTIFIER (1) + #ifdef CONFIG_CPU_FREQ int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list); -#else +int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list); +#else /* CONFIG_CPU_FREQ */ static inline int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list) { return 0; } -#endif -int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list); - -#define CPUFREQ_TRANSITION_NOTIFIER (0) -#define CPUFREQ_POLICY_NOTIFIER (1) - +static inline int cpufreq_unregister_notifier(struct notifier_block *nb, + unsigned int list) +{ + return 0; +} +#endif /* CONFIG_CPU_FREQ */ /* if (cpufreq_driver->target) exists, the ->governor decides what frequency * within the limits is used. If (cpufreq_driver->setpolicy> exists, these @@ -163,6 +167,9 @@ struct cpufreq_governor { char name[CPUFREQ_NAME_LEN]; int (*governor) (struct cpufreq_policy *policy, unsigned int event); + unsigned int max_transition_latency; /* HW must be able to switch to + next freq faster than this value in nano secs or we + will fallback to performance governor */ struct list_head governor_list; struct module *owner; }; @@ -268,22 +275,17 @@ struct freq_attr { int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); int cpufreq_update_policy(unsigned int cpu); +/* query the current CPU frequency (in kHz). If zero, cpufreq couldn't detect it */ +unsigned int cpufreq_get(unsigned int cpu); -/* - * query the last known CPU freq (in kHz). If zero, cpufreq couldn't detect it - */ +/* query the last known CPU freq (in kHz). If zero, cpufreq couldn't detect it */ #ifdef CONFIG_CPU_FREQ unsigned int cpufreq_quick_get(unsigned int cpu); -unsigned int cpufreq_get(unsigned int cpu); #else static inline unsigned int cpufreq_quick_get(unsigned int cpu) { return 0; } -static inline unsigned int cpufreq_get(unsigned int cpu) -{ - return 0; -} #endif @@ -292,12 +294,24 @@ static inline unsigned int cpufreq_get(unsigned int cpu) *********************************************************************/ -#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE +/* + Performance governor is fallback governor if any other gov failed to + auto load due latency restrictions +*/ +#ifdef CONFIG_CPU_FREQ_GOV_PERFORMANCE extern struct cpufreq_governor cpufreq_gov_performance; -#define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_performance +#endif +#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_performance) #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE) extern struct cpufreq_governor cpufreq_gov_userspace; -#define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_userspace +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_userspace) +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND) +extern struct cpufreq_governor cpufreq_gov_ondemand; +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_ondemand) +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE) +extern struct cpufreq_governor cpufreq_gov_conservative; +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_conservative) #endif diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 357e8cfedc37..fc32694287e2 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -34,6 +34,7 @@ #define CRYPTO_ALG_TYPE_HASH 0x00000003 #define CRYPTO_ALG_TYPE_BLKCIPHER 0x00000004 #define CRYPTO_ALG_TYPE_COMPRESS 0x00000005 +#define CRYPTO_ALG_TYPE_AEAD 0x00000006 #define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e @@ -91,9 +92,9 @@ struct scatterlist; struct crypto_ablkcipher; struct crypto_async_request; +struct crypto_aead; struct crypto_blkcipher; struct crypto_hash; -struct crypto_queue; struct crypto_tfm; struct crypto_type; @@ -121,6 +122,32 @@ struct ablkcipher_request { void *__ctx[] CRYPTO_MINALIGN_ATTR; }; +/** + * struct aead_request - AEAD request + * @base: Common attributes for async crypto requests + * @assoclen: Length in bytes of associated data for authentication + * @cryptlen: Length of data to be encrypted or decrypted + * @iv: Initialisation vector + * @assoc: Associated data + * @src: Source data + * @dst: Destination data + * @__ctx: Start of private context data + */ +struct aead_request { + struct crypto_async_request base; + + unsigned int assoclen; + unsigned int cryptlen; + + u8 *iv; + + struct scatterlist *assoc; + struct scatterlist *src; + struct scatterlist *dst; + + void *__ctx[] CRYPTO_MINALIGN_ATTR; +}; + struct blkcipher_desc { struct crypto_blkcipher *tfm; void *info; @@ -150,13 +177,21 @@ struct ablkcipher_alg { int (*encrypt)(struct ablkcipher_request *req); int (*decrypt)(struct ablkcipher_request *req); - struct crypto_queue *queue; - unsigned int min_keysize; unsigned int max_keysize; unsigned int ivsize; }; +struct aead_alg { + int (*setkey)(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen); + int (*encrypt)(struct aead_request *req); + int (*decrypt)(struct aead_request *req); + + unsigned int ivsize; + unsigned int authsize; +}; + struct blkcipher_alg { int (*setkey)(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen); @@ -212,6 +247,7 @@ struct compress_alg { }; #define cra_ablkcipher cra_u.ablkcipher +#define cra_aead cra_u.aead #define cra_blkcipher cra_u.blkcipher #define cra_cipher cra_u.cipher #define cra_digest cra_u.digest @@ -237,6 +273,7 @@ struct crypto_alg { union { struct ablkcipher_alg ablkcipher; + struct aead_alg aead; struct blkcipher_alg blkcipher; struct cipher_alg cipher; struct digest_alg digest; @@ -284,6 +321,16 @@ struct ablkcipher_tfm { unsigned int reqsize; }; +struct aead_tfm { + int (*setkey)(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen); + int (*encrypt)(struct aead_request *req); + int (*decrypt)(struct aead_request *req); + unsigned int ivsize; + unsigned int authsize; + unsigned int reqsize; +}; + struct blkcipher_tfm { void *iv; int (*setkey)(struct crypto_tfm *tfm, const u8 *key, @@ -323,6 +370,7 @@ struct compress_tfm { }; #define crt_ablkcipher crt_u.ablkcipher +#define crt_aead crt_u.aead #define crt_blkcipher crt_u.blkcipher #define crt_cipher crt_u.cipher #define crt_hash crt_u.hash @@ -334,6 +382,7 @@ struct crypto_tfm { union { struct ablkcipher_tfm ablkcipher; + struct aead_tfm aead; struct blkcipher_tfm blkcipher; struct cipher_tfm cipher; struct hash_tfm hash; @@ -349,6 +398,10 @@ struct crypto_ablkcipher { struct crypto_tfm base; }; +struct crypto_aead { + struct crypto_tfm base; +}; + struct crypto_blkcipher { struct crypto_tfm base; }; @@ -369,11 +422,15 @@ enum { CRYPTOA_UNSPEC, CRYPTOA_ALG, CRYPTOA_TYPE, + CRYPTOA_U32, __CRYPTOA_MAX, }; #define CRYPTOA_MAX (__CRYPTOA_MAX - 1) +/* Maximum number of (rtattr) parameters for each template. */ +#define CRYPTO_MAX_ATTRS 32 + struct crypto_attr_alg { char name[CRYPTO_MAX_ALG_NAME]; }; @@ -383,6 +440,10 @@ struct crypto_attr_type { u32 mask; }; +struct crypto_attr_u32 { + u32 num; +}; + /* * Transform user interface. */ @@ -563,7 +624,8 @@ static inline int crypto_ablkcipher_decrypt(struct ablkcipher_request *req) return crt->decrypt(req); } -static inline int crypto_ablkcipher_reqsize(struct crypto_ablkcipher *tfm) +static inline unsigned int crypto_ablkcipher_reqsize( + struct crypto_ablkcipher *tfm) { return crypto_ablkcipher_crt(tfm)->reqsize; } @@ -619,6 +681,150 @@ static inline void ablkcipher_request_set_crypt( req->info = iv; } +static inline struct crypto_aead *__crypto_aead_cast(struct crypto_tfm *tfm) +{ + return (struct crypto_aead *)tfm; +} + +static inline struct crypto_aead *crypto_alloc_aead(const char *alg_name, + u32 type, u32 mask) +{ + type &= ~CRYPTO_ALG_TYPE_MASK; + type |= CRYPTO_ALG_TYPE_AEAD; + mask |= CRYPTO_ALG_TYPE_MASK; + + return __crypto_aead_cast(crypto_alloc_base(alg_name, type, mask)); +} + +static inline struct crypto_tfm *crypto_aead_tfm(struct crypto_aead *tfm) +{ + return &tfm->base; +} + +static inline void crypto_free_aead(struct crypto_aead *tfm) +{ + crypto_free_tfm(crypto_aead_tfm(tfm)); +} + +static inline struct aead_tfm *crypto_aead_crt(struct crypto_aead *tfm) +{ + return &crypto_aead_tfm(tfm)->crt_aead; +} + +static inline unsigned int crypto_aead_ivsize(struct crypto_aead *tfm) +{ + return crypto_aead_crt(tfm)->ivsize; +} + +static inline unsigned int crypto_aead_authsize(struct crypto_aead *tfm) +{ + return crypto_aead_crt(tfm)->authsize; +} + +static inline unsigned int crypto_aead_blocksize(struct crypto_aead *tfm) +{ + return crypto_tfm_alg_blocksize(crypto_aead_tfm(tfm)); +} + +static inline unsigned int crypto_aead_alignmask(struct crypto_aead *tfm) +{ + return crypto_tfm_alg_alignmask(crypto_aead_tfm(tfm)); +} + +static inline u32 crypto_aead_get_flags(struct crypto_aead *tfm) +{ + return crypto_tfm_get_flags(crypto_aead_tfm(tfm)); +} + +static inline void crypto_aead_set_flags(struct crypto_aead *tfm, u32 flags) +{ + crypto_tfm_set_flags(crypto_aead_tfm(tfm), flags); +} + +static inline void crypto_aead_clear_flags(struct crypto_aead *tfm, u32 flags) +{ + crypto_tfm_clear_flags(crypto_aead_tfm(tfm), flags); +} + +static inline int crypto_aead_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen) +{ + return crypto_aead_crt(tfm)->setkey(tfm, key, keylen); +} + +static inline struct crypto_aead *crypto_aead_reqtfm(struct aead_request *req) +{ + return __crypto_aead_cast(req->base.tfm); +} + +static inline int crypto_aead_encrypt(struct aead_request *req) +{ + return crypto_aead_crt(crypto_aead_reqtfm(req))->encrypt(req); +} + +static inline int crypto_aead_decrypt(struct aead_request *req) +{ + return crypto_aead_crt(crypto_aead_reqtfm(req))->decrypt(req); +} + +static inline unsigned int crypto_aead_reqsize(struct crypto_aead *tfm) +{ + return crypto_aead_crt(tfm)->reqsize; +} + +static inline void aead_request_set_tfm(struct aead_request *req, + struct crypto_aead *tfm) +{ + req->base.tfm = crypto_aead_tfm(tfm); +} + +static inline struct aead_request *aead_request_alloc(struct crypto_aead *tfm, + gfp_t gfp) +{ + struct aead_request *req; + + req = kmalloc(sizeof(*req) + crypto_aead_reqsize(tfm), gfp); + + if (likely(req)) + aead_request_set_tfm(req, tfm); + + return req; +} + +static inline void aead_request_free(struct aead_request *req) +{ + kfree(req); +} + +static inline void aead_request_set_callback(struct aead_request *req, + u32 flags, + crypto_completion_t complete, + void *data) +{ + req->base.complete = complete; + req->base.data = data; + req->base.flags = flags; +} + +static inline void aead_request_set_crypt(struct aead_request *req, + struct scatterlist *src, + struct scatterlist *dst, + unsigned int cryptlen, u8 *iv) +{ + req->src = src; + req->dst = dst; + req->cryptlen = cryptlen; + req->iv = iv; +} + +static inline void aead_request_set_assoc(struct aead_request *req, + struct scatterlist *assoc, + unsigned int assoclen) +{ + req->assoc = assoc; + req->assoclen = assoclen; +} + static inline struct crypto_blkcipher *__crypto_blkcipher_cast( struct crypto_tfm *tfm) { diff --git a/include/linux/dccp.h b/include/linux/dccp.h index fda2148d8c85..f3fc4392e93d 100644 --- a/include/linux/dccp.h +++ b/include/linux/dccp.h @@ -56,10 +56,9 @@ struct dccp_hdr_ext { }; /** - * struct dccp_hdr_request - Conection initiation request header + * struct dccp_hdr_request - Connection initiation request header * * @dccph_req_service - Service to which the client app wants to connect - * @dccph_req_options - list of options (must be a multiple of 32 bits */ struct dccp_hdr_request { __be32 dccph_req_service; @@ -76,12 +75,10 @@ struct dccp_hdr_ack_bits { __be32 dccph_ack_nr_low; }; /** - * struct dccp_hdr_response - Conection initiation response header + * struct dccp_hdr_response - Connection initiation response header * - * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR - * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR + * @dccph_resp_ack - 48 bit Acknowledgment Number Subheader (5.3) * @dccph_resp_service - Echoes the Service Code on a received DCCP-Request - * @dccph_resp_options - list of options (must be a multiple of 32 bits */ struct dccp_hdr_response { struct dccp_hdr_ack_bits dccph_resp_ack; @@ -91,8 +88,9 @@ struct dccp_hdr_response { /** * struct dccp_hdr_reset - Unconditionally shut down a connection * - * @dccph_reset_service - Echoes the Service Code on a received DCCP-Request - * @dccph_reset_options - list of options (must be a multiple of 32 bits + * @dccph_reset_ack - 48 bit Acknowledgment Number Subheader (5.6) + * @dccph_reset_code - one of %dccp_reset_codes + * @dccph_reset_data - the Data 1 ... Data 3 fields from 5.6 */ struct dccp_hdr_reset { struct dccp_hdr_ack_bits dccph_reset_ack; @@ -204,6 +202,7 @@ struct dccp_so_feat { #define DCCP_SOCKOPT_SERVICE 2 #define DCCP_SOCKOPT_CHANGE_L 3 #define DCCP_SOCKOPT_CHANGE_R 4 +#define DCCP_SOCKOPT_GET_CUR_MPS 5 #define DCCP_SOCKOPT_SEND_CSCOV 10 #define DCCP_SOCKOPT_RECV_CSCOV 11 #define DCCP_SOCKOPT_CCID_RX_INFO 128 @@ -215,6 +214,7 @@ struct dccp_so_feat { #ifdef __KERNEL__ #include <linux/in.h> +#include <linux/ktime.h> #include <linux/list.h> #include <linux/uio.h> #include <linux/workqueue.h> @@ -391,7 +391,6 @@ struct dccp_opt_pend { struct dccp_opt_conf *dccpop_sc; }; -extern void __dccp_minisock_init(struct dccp_minisock *dmsk); extern void dccp_minisock_init(struct dccp_minisock *dmsk); extern int dccp_parse_options(struct sock *sk, struct sk_buff *skb); @@ -471,6 +470,7 @@ struct dccp_ackvec; * @dccps_pcrlen - receiver partial checksum coverage (via sockopt) * @dccps_ndp_count - number of Non Data Packets since last data packet * @dccps_mss_cache - current value of MSS (path MTU minus header sizes) + * @dccps_rate_last - timestamp for rate-limiting DCCP-Sync (RFC 4340, 7.5.4) * @dccps_minisock - associated minisock (accessed via dccp_msk) * @dccps_hc_rx_ackvec - rx half connection ack vector * @dccps_hc_rx_ccid - CCID used for the receiver (or receiving half-connection) @@ -498,7 +498,7 @@ struct dccp_sock { __u64 dccps_gar; __be32 dccps_service; struct dccp_service_list *dccps_service_list; - struct timeval dccps_timestamp_time; + ktime_t dccps_timestamp_time; __u32 dccps_timestamp_echo; __u16 dccps_l_ack_ratio; __u16 dccps_r_ack_ratio; @@ -506,12 +506,12 @@ struct dccp_sock { __u16 dccps_pcrlen; unsigned long dccps_ndp_count; __u32 dccps_mss_cache; + unsigned long dccps_rate_last; struct dccp_minisock dccps_minisock; struct dccp_ackvec *dccps_hc_rx_ackvec; struct ccid *dccps_hc_rx_ccid; struct ccid *dccps_hc_tx_ccid; struct dccp_options_received dccps_options_received; - struct timeval dccps_epoch; enum dccp_role dccps_role:2; __u8 dccps_hc_rx_insert_options:1; __u8 dccps_hc_tx_insert_options:1; diff --git a/include/linux/dcookies.h b/include/linux/dcookies.h index 0fe7cdf326f7..98c69ab80c84 100644 --- a/include/linux/dcookies.h +++ b/include/linux/dcookies.h @@ -12,6 +12,7 @@ #ifdef CONFIG_PROFILING +#include <linux/dcache.h> #include <linux/types.h> struct dcookie_user; diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 104e51e20e14..f592d6de3b97 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -49,6 +49,12 @@ struct dentry *debugfs_create_u32(const char *name, mode_t mode, struct dentry *parent, u32 *value); struct dentry *debugfs_create_u64(const char *name, mode_t mode, struct dentry *parent, u64 *value); +struct dentry *debugfs_create_x8(const char *name, mode_t mode, + struct dentry *parent, u8 *value); +struct dentry *debugfs_create_x16(const char *name, mode_t mode, + struct dentry *parent, u16 *value); +struct dentry *debugfs_create_x32(const char *name, mode_t mode, + struct dentry *parent, u32 *value); struct dentry *debugfs_create_bool(const char *name, mode_t mode, struct dentry *parent, u32 *value); @@ -122,6 +128,27 @@ static inline struct dentry *debugfs_create_u64(const char *name, mode_t mode, return ERR_PTR(-ENODEV); } +static inline struct dentry *debugfs_create_x8(const char *name, mode_t mode, + struct dentry *parent, + u8 *value) +{ + return ERR_PTR(-ENODEV); +} + +static inline struct dentry *debugfs_create_x16(const char *name, mode_t mode, + struct dentry *parent, + u16 *value) +{ + return ERR_PTR(-ENODEV); +} + +static inline struct dentry *debugfs_create_x32(const char *name, mode_t mode, + struct dentry *parent, + u32 *value) +{ + return ERR_PTR(-ENODEV); +} + static inline struct dentry *debugfs_create_bool(const char *name, mode_t mode, struct dentry *parent, u32 *value) diff --git a/include/linux/device.h b/include/linux/device.h index be2debed70d2..2e15822fe409 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -64,12 +64,9 @@ struct bus_type { struct bus_attribute * bus_attrs; struct device_attribute * dev_attrs; struct driver_attribute * drv_attrs; - struct bus_attribute drivers_autoprobe_attr; - struct bus_attribute drivers_probe_attr; int (*match)(struct device * dev, struct device_driver * drv); - int (*uevent)(struct device *dev, char **envp, - int num_envp, char *buffer, int buffer_size); + int (*uevent)(struct device *dev, struct kobj_uevent_env *env); int (*probe)(struct device * dev); int (*remove)(struct device * dev); void (*shutdown)(struct device * dev); @@ -189,10 +186,8 @@ struct class { struct class_device_attribute * class_dev_attrs; struct device_attribute * dev_attrs; - int (*uevent)(struct class_device *dev, char **envp, - int num_envp, char *buffer, int buffer_size); - int (*dev_uevent)(struct device *dev, char **envp, int num_envp, - char *buffer, int buffer_size); + int (*uevent)(struct class_device *dev, struct kobj_uevent_env *env); + int (*dev_uevent)(struct device *dev, struct kobj_uevent_env *env); void (*release)(struct class_device *dev); void (*class_release)(struct class *class); @@ -268,8 +263,7 @@ struct class_device { struct attribute_group ** groups; /* optional groups */ void (*release)(struct class_device *dev); - int (*uevent)(struct class_device *dev, char **envp, - int num_envp, char *buffer, int buffer_size); + int (*uevent)(struct class_device *dev, struct kobj_uevent_env *env); char class_id[BUS_ID_SIZE]; /* unique to this class */ }; @@ -337,8 +331,7 @@ extern void class_device_destroy(struct class *cls, dev_t devt); struct device_type { const char *name; struct attribute_group **groups; - int (*uevent)(struct device *dev, char **envp, int num_envp, - char *buffer, int buffer_size); + int (*uevent)(struct device *dev, struct kobj_uevent_env *env); void (*release)(struct device *dev); int (*suspend)(struct device * dev, pm_message_t state); int (*resume)(struct device * dev); @@ -551,6 +544,9 @@ extern void put_device(struct device * dev); /* drivers/base/power/shutdown.c */ extern void device_shutdown(void); +/* drivers/base/sys.c */ +extern void sysdev_shutdown(void); + /* drivers/base/firmware.c */ extern int __must_check firmware_register(struct kset *); @@ -572,6 +568,16 @@ dev_dbg(struct device * dev, const char * fmt, ...) } #endif +#ifdef VERBOSE_DEBUG +#define dev_vdbg dev_dbg +#else +static inline int __attribute__ ((format (printf, 2, 3))) +dev_vdbg(struct device * dev, const char * fmt, ...) +{ + return 0; +} +#endif + #define dev_err(dev, format, arg...) \ dev_printk(KERN_ERR , dev , format , ## arg) #define dev_info(dev, format, arg...) \ diff --git a/include/linux/dmi.h b/include/linux/dmi.h index b8ac7b01c45e..00fc7a9c35ec 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -54,7 +54,7 @@ struct dmi_strmatch { }; struct dmi_system_id { - int (*callback)(struct dmi_system_id *); + int (*callback)(const struct dmi_system_id *); const char *ident; struct dmi_strmatch matches[4]; void *driver_data; @@ -71,22 +71,22 @@ struct dmi_device { #ifdef CONFIG_DMI -extern int dmi_check_system(struct dmi_system_id *list); -extern char * dmi_get_system_info(int field); -extern struct dmi_device * dmi_find_device(int type, const char *name, - struct dmi_device *from); +extern int dmi_check_system(const struct dmi_system_id *list); +extern const char * dmi_get_system_info(int field); +extern const struct dmi_device * dmi_find_device(int type, const char *name, + const struct dmi_device *from); extern void dmi_scan_machine(void); extern int dmi_get_year(int field); -extern int dmi_name_in_vendors(char *str); +extern int dmi_name_in_vendors(const char *str); #else -static inline int dmi_check_system(struct dmi_system_id *list) { return 0; } -static inline char * dmi_get_system_info(int field) { return NULL; } -static inline struct dmi_device * dmi_find_device(int type, const char *name, - struct dmi_device *from) { return NULL; } +static inline int dmi_check_system(const struct dmi_system_id *list) { return 0; } +static inline const char * dmi_get_system_info(int field) { return NULL; } +static inline const struct dmi_device * dmi_find_device(int type, const char *name, + const struct dmi_device *from) { return NULL; } static inline int dmi_get_year(int year) { return 0; } -static inline int dmi_name_in_vendors(char *s) { return 0; } +static inline int dmi_name_in_vendors(const char *s) { return 0; } #endif diff --git a/include/linux/dvb/video.h b/include/linux/dvb/video.h index 93e4c3a6d190..50839fe9e39e 100644 --- a/include/linux/dvb/video.h +++ b/include/linux/dvb/video.h @@ -29,6 +29,7 @@ #ifdef __KERNEL__ #include <linux/types.h> #else +#include <asm/types.h> #include <stdint.h> #include <time.h> #endif diff --git a/include/linux/edac.h b/include/linux/edac.h new file mode 100644 index 000000000000..eab451e69a91 --- /dev/null +++ b/include/linux/edac.h @@ -0,0 +1,29 @@ +/* + * Generic EDAC defs + * + * Author: Dave Jiang <djiang@mvista.com> + * + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + */ +#ifndef _LINUX_EDAC_H_ +#define _LINUX_EDAC_H_ + +#include <asm/atomic.h> + +#define EDAC_OPSTATE_INVAL -1 +#define EDAC_OPSTATE_POLL 0 +#define EDAC_OPSTATE_NMI 1 +#define EDAC_OPSTATE_INT 2 + +extern int edac_op_state; +extern int edac_err_assert; +extern atomic_t edac_handlers; + +extern int edac_handler_set(void); +extern void edac_atomic_assert_error(void); + +#endif diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h index d774b7778c91..a55c873e8b66 100644 --- a/include/linux/eeprom_93cx6.h +++ b/include/linux/eeprom_93cx6.h @@ -21,13 +21,14 @@ /* Module: eeprom_93cx6 Abstract: EEPROM reader datastructures for 93cx6 chipsets. - Supported chipsets: 93c46 & 93c66. + Supported chipsets: 93c46, 93c56 and 93c66. */ /* * EEPROM operation defines. */ #define PCI_EEPROM_WIDTH_93C46 6 +#define PCI_EEPROM_WIDTH_93C56 8 #define PCI_EEPROM_WIDTH_93C66 8 #define PCI_EEPROM_WIDTH_OPCODE 3 #define PCI_EEPROM_WRITE_OPCODE 0x05 diff --git a/include/linux/elevator.h b/include/linux/elevator.h index e88fcbc77f8f..e8f42133a616 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -5,29 +5,29 @@ #ifdef CONFIG_BLOCK -typedef int (elevator_merge_fn) (request_queue_t *, struct request **, +typedef int (elevator_merge_fn) (struct request_queue *, struct request **, struct bio *); -typedef void (elevator_merge_req_fn) (request_queue_t *, struct request *, struct request *); +typedef void (elevator_merge_req_fn) (struct request_queue *, struct request *, struct request *); -typedef void (elevator_merged_fn) (request_queue_t *, struct request *, int); +typedef void (elevator_merged_fn) (struct request_queue *, struct request *, int); -typedef int (elevator_allow_merge_fn) (request_queue_t *, struct request *, struct bio *); +typedef int (elevator_allow_merge_fn) (struct request_queue *, struct request *, struct bio *); -typedef int (elevator_dispatch_fn) (request_queue_t *, int); +typedef int (elevator_dispatch_fn) (struct request_queue *, int); -typedef void (elevator_add_req_fn) (request_queue_t *, struct request *); -typedef int (elevator_queue_empty_fn) (request_queue_t *); -typedef struct request *(elevator_request_list_fn) (request_queue_t *, struct request *); -typedef void (elevator_completed_req_fn) (request_queue_t *, struct request *); -typedef int (elevator_may_queue_fn) (request_queue_t *, int); +typedef void (elevator_add_req_fn) (struct request_queue *, struct request *); +typedef int (elevator_queue_empty_fn) (struct request_queue *); +typedef struct request *(elevator_request_list_fn) (struct request_queue *, struct request *); +typedef void (elevator_completed_req_fn) (struct request_queue *, struct request *); +typedef int (elevator_may_queue_fn) (struct request_queue *, int); -typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, gfp_t); +typedef int (elevator_set_req_fn) (struct request_queue *, struct request *, gfp_t); typedef void (elevator_put_req_fn) (struct request *); -typedef void (elevator_activate_req_fn) (request_queue_t *, struct request *); -typedef void (elevator_deactivate_req_fn) (request_queue_t *, struct request *); +typedef void (elevator_activate_req_fn) (struct request_queue *, struct request *); +typedef void (elevator_deactivate_req_fn) (struct request_queue *, struct request *); -typedef void *(elevator_init_fn) (request_queue_t *); +typedef void *(elevator_init_fn) (struct request_queue *); typedef void (elevator_exit_fn) (elevator_t *); struct elevator_ops @@ -94,27 +94,27 @@ struct elevator_queue /* * block elevator interface */ -extern void elv_dispatch_sort(request_queue_t *, struct request *); -extern void elv_dispatch_add_tail(request_queue_t *, struct request *); -extern void elv_add_request(request_queue_t *, struct request *, int, int); -extern void __elv_add_request(request_queue_t *, struct request *, int, int); -extern void elv_insert(request_queue_t *, struct request *, int); -extern int elv_merge(request_queue_t *, struct request **, struct bio *); -extern void elv_merge_requests(request_queue_t *, struct request *, +extern void elv_dispatch_sort(struct request_queue *, struct request *); +extern void elv_dispatch_add_tail(struct request_queue *, struct request *); +extern void elv_add_request(struct request_queue *, struct request *, int, int); +extern void __elv_add_request(struct request_queue *, struct request *, int, int); +extern void elv_insert(struct request_queue *, struct request *, int); +extern int elv_merge(struct request_queue *, struct request **, struct bio *); +extern void elv_merge_requests(struct request_queue *, struct request *, struct request *); -extern void elv_merged_request(request_queue_t *, struct request *, int); -extern void elv_dequeue_request(request_queue_t *, struct request *); -extern void elv_requeue_request(request_queue_t *, struct request *); -extern int elv_queue_empty(request_queue_t *); +extern void elv_merged_request(struct request_queue *, struct request *, int); +extern void elv_dequeue_request(struct request_queue *, struct request *); +extern void elv_requeue_request(struct request_queue *, struct request *); +extern int elv_queue_empty(struct request_queue *); extern struct request *elv_next_request(struct request_queue *q); -extern struct request *elv_former_request(request_queue_t *, struct request *); -extern struct request *elv_latter_request(request_queue_t *, struct request *); -extern int elv_register_queue(request_queue_t *q); -extern void elv_unregister_queue(request_queue_t *q); -extern int elv_may_queue(request_queue_t *, int); -extern void elv_completed_request(request_queue_t *, struct request *); -extern int elv_set_request(request_queue_t *, struct request *, gfp_t); -extern void elv_put_request(request_queue_t *, struct request *); +extern struct request *elv_former_request(struct request_queue *, struct request *); +extern struct request *elv_latter_request(struct request_queue *, struct request *); +extern int elv_register_queue(struct request_queue *q); +extern void elv_unregister_queue(struct request_queue *q); +extern int elv_may_queue(struct request_queue *, int); +extern void elv_completed_request(struct request_queue *, struct request *); +extern int elv_set_request(struct request_queue *, struct request *, gfp_t); +extern void elv_put_request(struct request_queue *, struct request *); /* * io scheduler registration @@ -125,18 +125,18 @@ extern void elv_unregister(struct elevator_type *); /* * io scheduler sysfs switching */ -extern ssize_t elv_iosched_show(request_queue_t *, char *); -extern ssize_t elv_iosched_store(request_queue_t *, const char *, size_t); +extern ssize_t elv_iosched_show(struct request_queue *, char *); +extern ssize_t elv_iosched_store(struct request_queue *, const char *, size_t); -extern int elevator_init(request_queue_t *, char *); +extern int elevator_init(struct request_queue *, char *); extern void elevator_exit(elevator_t *); extern int elv_rq_merge_ok(struct request *, struct bio *); /* * Helper functions. */ -extern struct request *elv_rb_former_request(request_queue_t *, struct request *); -extern struct request *elv_rb_latter_request(request_queue_t *, struct request *); +extern struct request *elv_rb_former_request(struct request_queue *, struct request *); +extern struct request *elv_rb_latter_request(struct request_queue *, struct request *); /* * rb support functions. diff --git a/include/linux/elf-em.h b/include/linux/elf-em.h index 0311bad838b1..5834e843a946 100644 --- a/include/linux/elf-em.h +++ b/include/linux/elf-em.h @@ -20,7 +20,8 @@ #define EM_PARISC 15 /* HPPA */ #define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ #define EM_PPC 20 /* PowerPC */ -#define EM_PPC64 21 /* PowerPC64 */ +#define EM_PPC64 21 /* PowerPC64 */ +#define EM_SPU 23 /* Cell BE SPU */ #define EM_SH 42 /* SuperH */ #define EM_SPARCV9 43 /* SPARC v9 64-bit */ #define EM_IA_64 50 /* HP/Intel IA-64 */ diff --git a/include/linux/elf.h b/include/linux/elf.h index 8b17ffe222c4..d2da84acf45d 100644 --- a/include/linux/elf.h +++ b/include/linux/elf.h @@ -389,12 +389,14 @@ extern Elf64_Dyn _DYNAMIC []; #endif +/* Optional callbacks to write extra ELF notes. */ #ifndef ARCH_HAVE_EXTRA_ELF_NOTES -static inline int arch_notes_size(void) { return 0; } -static inline void arch_write_notes(struct file *file) { } - -#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size() -#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file) -#endif /* ARCH_HAVE_EXTRA_ELF_NOTES */ +static inline int elf_coredump_extra_notes_size(void) { return 0; } +static inline int elf_coredump_extra_notes_write(struct file *file, + loff_t *foffset) { return 0; } +#else +extern int elf_coredump_extra_notes_size(void); +extern int elf_coredump_extra_notes_write(struct file *file, loff_t *foffset); +#endif #endif /* _LINUX_ELF_H */ diff --git a/include/linux/elfnote.h b/include/linux/elfnote.h index 9a1e0674e56c..e831759b2fb5 100644 --- a/include/linux/elfnote.h +++ b/include/linux/elfnote.h @@ -38,17 +38,25 @@ * e.g. ELFNOTE(XYZCo, 42, .asciz, "forty-two") * ELFNOTE(XYZCo, 12, .long, 0xdeadbeef) */ -#define ELFNOTE(name, type, desctype, descdata) \ -.pushsection .note.name, "",@note ; \ - .align 4 ; \ +#define ELFNOTE_START(name, type, flags) \ +.pushsection .note.name, flags,@note ; \ + .balign 4 ; \ .long 2f - 1f /* namesz */ ; \ - .long 4f - 3f /* descsz */ ; \ + .long 4484f - 3f /* descsz */ ; \ .long type ; \ 1:.asciz #name ; \ -2:.align 4 ; \ -3:desctype descdata ; \ -4:.align 4 ; \ +2:.balign 4 ; \ +3: + +#define ELFNOTE_END \ +4484:.balign 4 ; \ .popsection ; + +#define ELFNOTE(name, type, desc) \ + ELFNOTE_START(name, type, "") \ + desc ; \ + ELFNOTE_END + #else /* !__ASSEMBLER__ */ #include <linux/elf.h> /* diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index 6cdb97365e47..b7558ec81ed5 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -29,15 +29,19 @@ #include <linux/random.h> #ifdef __KERNEL__ -extern int eth_header(struct sk_buff *skb, struct net_device *dev, - unsigned short type, void *daddr, - void *saddr, unsigned len); -extern int eth_rebuild_header(struct sk_buff *skb); extern __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); -extern void eth_header_cache_update(struct hh_cache *hh, struct net_device *dev, - unsigned char * haddr); -extern int eth_header_cache(struct neighbour *neigh, - struct hh_cache *hh); +extern const struct header_ops eth_header_ops; + +extern int eth_header(struct sk_buff *skb, struct net_device *dev, + unsigned short type, + const void *daddr, const void *saddr, unsigned len); +extern int eth_rebuild_header(struct sk_buff *skb); +extern int eth_header_parse(const struct sk_buff *skb, unsigned char *haddr); +extern int eth_header_cache(const struct neighbour *neigh, struct hh_cache *hh); +extern void eth_header_cache_update(struct hh_cache *hh, + const struct net_device *dev, + const unsigned char *haddr); + extern struct net_device *alloc_etherdev_mq(int sizeof_priv, unsigned int queue_count); #define alloc_etherdev(sizeof_priv) alloc_etherdev_mq(sizeof_priv, 1) diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 3a632244f31b..71d4ada6f315 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -39,7 +39,8 @@ struct ethtool_drvinfo { char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */ /* For PCI devices, use pci_name(pci_dev). */ char reserved1[32]; - char reserved2[16]; + char reserved2[12]; + __u32 n_priv_flags; /* number of flags valid in ETHTOOL_GPFLAGS */ __u32 n_stats; /* number of u64's from ETHTOOL_GSTATS */ __u32 testinfo_len; __u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */ @@ -219,6 +220,7 @@ struct ethtool_pauseparam { enum ethtool_stringset { ETH_SS_TEST = 0, ETH_SS_STATS, + ETH_SS_PRIV_FLAGS, }; /* for passing string sets for data tagging */ @@ -256,6 +258,19 @@ struct ethtool_perm_addr { __u8 data[0]; }; +/* boolean flags controlling per-interface behavior characteristics. + * When reading, the flag indicates whether or not a certain behavior + * is enabled/present. When writing, the flag indicates whether + * or not the driver should turn on (set) or off (clear) a behavior. + * + * Some behaviors may read-only (unconditionally absent or present). + * If such is the case, return EINVAL in the set-flags operation if the + * flag differs from the read-only value. + */ +enum ethtool_flags { + ETH_FLAG_LRO = (1 << 15), /* LRO is enabled */ +}; + #ifdef __KERNEL__ struct net_device; @@ -270,10 +285,10 @@ u32 ethtool_op_get_sg(struct net_device *dev); int ethtool_op_set_sg(struct net_device *dev, u32 data); u32 ethtool_op_get_tso(struct net_device *dev); int ethtool_op_set_tso(struct net_device *dev, u32 data); -int ethtool_op_get_perm_addr(struct net_device *dev, - struct ethtool_perm_addr *addr, u8 *data); u32 ethtool_op_get_ufo(struct net_device *dev); int ethtool_op_set_ufo(struct net_device *dev, u32 data); +u32 ethtool_op_get_flags(struct net_device *dev); +int ethtool_op_set_flags(struct net_device *dev, u32 data); /** * ðtool_ops - Alter and report network device settings @@ -309,7 +324,8 @@ int ethtool_op_set_ufo(struct net_device *dev, u32 data); * get_strings: Return a set of strings that describe the requested objects * phys_id: Identify the device * get_stats: Return statistics about the device - * get_perm_addr: Gets the permanent hardware address + * get_flags: get 32-bit flags bitmap + * set_flags: set 32-bit flags bitmap * * Description: * @@ -362,17 +378,23 @@ struct ethtool_ops { int (*set_sg)(struct net_device *, u32); u32 (*get_tso)(struct net_device *); int (*set_tso)(struct net_device *, u32); - int (*self_test_count)(struct net_device *); void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); void (*get_strings)(struct net_device *, u32 stringset, u8 *); int (*phys_id)(struct net_device *, u32); - int (*get_stats_count)(struct net_device *); void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *); - int (*get_perm_addr)(struct net_device *, struct ethtool_perm_addr *, u8 *); int (*begin)(struct net_device *); void (*complete)(struct net_device *); u32 (*get_ufo)(struct net_device *); int (*set_ufo)(struct net_device *, u32); + u32 (*get_flags)(struct net_device *); + int (*set_flags)(struct net_device *, u32); + u32 (*get_priv_flags)(struct net_device *); + int (*set_priv_flags)(struct net_device *, u32); + int (*get_sset_count)(struct net_device *, int); + + /* the following hooks are obsolete */ + int (*self_test_count)(struct net_device *);/* use get_sset_count */ + int (*get_stats_count)(struct net_device *);/* use get_sset_count */ }; #endif /* __KERNEL__ */ @@ -414,6 +436,10 @@ struct ethtool_ops { #define ETHTOOL_SUFO 0x00000022 /* Set UFO enable (ethtool_value) */ #define ETHTOOL_GGSO 0x00000023 /* Get GSO enable (ethtool_value) */ #define ETHTOOL_SGSO 0x00000024 /* Set GSO enable (ethtool_value) */ +#define ETHTOOL_GFLAGS 0x00000025 /* Get flags bitmap(ethtool_value) */ +#define ETHTOOL_SFLAGS 0x00000026 /* Set flags bitmap(ethtool_value) */ +#define ETHTOOL_GPFLAGS 0x00000027 /* Get driver-private flags bitmap */ +#define ETHTOOL_SPFLAGS 0x00000028 /* Set driver-private flags bitmap */ /* compatibility with older code */ #define SPARC_ETH_GSET ETHTOOL_GSET diff --git a/include/linux/ext4_fs.h b/include/linux/ext4_fs.h index de1f9f78625a..cdee7aaa57aa 100644 --- a/include/linux/ext4_fs.h +++ b/include/linux/ext4_fs.h @@ -71,7 +71,7 @@ /* * Maximal count of links to a file */ -#define EXT4_LINK_MAX 32000 +#define EXT4_LINK_MAX 65000 /* * Macro-instructions used to manage several block sizes @@ -102,6 +102,7 @@ EXT4_GOOD_OLD_FIRST_INO : \ (s)->s_first_ino) #endif +#define EXT4_BLOCK_ALIGN(size, blkbits) ALIGN((size), (1 << (blkbits))) /* * Macro-instructions used to manage fragments @@ -201,6 +202,7 @@ struct ext4_group_desc #define EXT4_STATE_JDATA 0x00000001 /* journaled data exists */ #define EXT4_STATE_NEW 0x00000002 /* inode is newly created */ #define EXT4_STATE_XATTR 0x00000004 /* has in-inode xattrs */ +#define EXT4_STATE_NO_EXPAND 0x00000008 /* No space for expansion */ /* Used to pass group descriptor data when online resize is done */ struct ext4_new_group_input { @@ -225,6 +227,11 @@ struct ext4_new_group_data { __u32 free_blocks_count; }; +/* + * Following is used by preallocation code to tell get_blocks() that we + * want uninitialzed extents. + */ +#define EXT4_CREATE_UNINITIALIZED_EXT 2 /* * ioctl commands @@ -237,7 +244,7 @@ struct ext4_new_group_data { #define EXT4_IOC_GROUP_ADD _IOW('f', 8,struct ext4_new_group_input) #define EXT4_IOC_GETVERSION_OLD FS_IOC_GETVERSION #define EXT4_IOC_SETVERSION_OLD FS_IOC_SETVERSION -#ifdef CONFIG_JBD_DEBUG +#ifdef CONFIG_JBD2_DEBUG #define EXT4_IOC_WAIT_FOR_READONLY _IOR('f', 99, long) #endif #define EXT4_IOC_GETRSVSZ _IOR('f', 5, long) @@ -253,7 +260,7 @@ struct ext4_new_group_data { #define EXT4_IOC32_GETRSVSZ _IOR('f', 5, int) #define EXT4_IOC32_SETRSVSZ _IOW('f', 6, int) #define EXT4_IOC32_GROUP_EXTEND _IOW('f', 7, unsigned int) -#ifdef CONFIG_JBD_DEBUG +#ifdef CONFIG_JBD2_DEBUG #define EXT4_IOC32_WAIT_FOR_READONLY _IOR('f', 99, int) #endif #define EXT4_IOC32_GETVERSION_OLD FS_IOC32_GETVERSION @@ -282,7 +289,7 @@ struct ext4_inode { __le16 i_uid; /* Low 16 bits of Owner Uid */ __le32 i_size; /* Size in bytes */ __le32 i_atime; /* Access time */ - __le32 i_ctime; /* Creation time */ + __le32 i_ctime; /* Inode Change time */ __le32 i_mtime; /* Modification time */ __le32 i_dtime; /* Deletion Time */ __le16 i_gid; /* Low 16 bits of Group Id */ @@ -331,10 +338,85 @@ struct ext4_inode { } osd2; /* OS dependent 2 */ __le16 i_extra_isize; __le16 i_pad1; + __le32 i_ctime_extra; /* extra Change time (nsec << 2 | epoch) */ + __le32 i_mtime_extra; /* extra Modification time(nsec << 2 | epoch) */ + __le32 i_atime_extra; /* extra Access time (nsec << 2 | epoch) */ + __le32 i_crtime; /* File Creation time */ + __le32 i_crtime_extra; /* extra FileCreationtime (nsec << 2 | epoch) */ }; #define i_size_high i_dir_acl +#define EXT4_EPOCH_BITS 2 +#define EXT4_EPOCH_MASK ((1 << EXT4_EPOCH_BITS) - 1) +#define EXT4_NSEC_MASK (~0UL << EXT4_EPOCH_BITS) + +/* + * Extended fields will fit into an inode if the filesystem was formatted + * with large inodes (-I 256 or larger) and there are not currently any EAs + * consuming all of the available space. For new inodes we always reserve + * enough space for the kernel's known extended fields, but for inodes + * created with an old kernel this might not have been the case. None of + * the extended inode fields is critical for correct filesystem operation. + * This macro checks if a certain field fits in the inode. Note that + * inode-size = GOOD_OLD_INODE_SIZE + i_extra_isize + */ +#define EXT4_FITS_IN_INODE(ext4_inode, einode, field) \ + ((offsetof(typeof(*ext4_inode), field) + \ + sizeof((ext4_inode)->field)) \ + <= (EXT4_GOOD_OLD_INODE_SIZE + \ + (einode)->i_extra_isize)) \ + +static inline __le32 ext4_encode_extra_time(struct timespec *time) +{ + return cpu_to_le32((sizeof(time->tv_sec) > 4 ? + time->tv_sec >> 32 : 0) | + ((time->tv_nsec << 2) & EXT4_NSEC_MASK)); +} + +static inline void ext4_decode_extra_time(struct timespec *time, __le32 extra) +{ + if (sizeof(time->tv_sec) > 4) + time->tv_sec |= (__u64)(le32_to_cpu(extra) & EXT4_EPOCH_MASK) + << 32; + time->tv_nsec = (le32_to_cpu(extra) & EXT4_NSEC_MASK) >> 2; +} + +#define EXT4_INODE_SET_XTIME(xtime, inode, raw_inode) \ +do { \ + (raw_inode)->xtime = cpu_to_le32((inode)->xtime.tv_sec); \ + if (EXT4_FITS_IN_INODE(raw_inode, EXT4_I(inode), xtime ## _extra)) \ + (raw_inode)->xtime ## _extra = \ + ext4_encode_extra_time(&(inode)->xtime); \ +} while (0) + +#define EXT4_EINODE_SET_XTIME(xtime, einode, raw_inode) \ +do { \ + if (EXT4_FITS_IN_INODE(raw_inode, einode, xtime)) \ + (raw_inode)->xtime = cpu_to_le32((einode)->xtime.tv_sec); \ + if (EXT4_FITS_IN_INODE(raw_inode, einode, xtime ## _extra)) \ + (raw_inode)->xtime ## _extra = \ + ext4_encode_extra_time(&(einode)->xtime); \ +} while (0) + +#define EXT4_INODE_GET_XTIME(xtime, inode, raw_inode) \ +do { \ + (inode)->xtime.tv_sec = (signed)le32_to_cpu((raw_inode)->xtime); \ + if (EXT4_FITS_IN_INODE(raw_inode, EXT4_I(inode), xtime ## _extra)) \ + ext4_decode_extra_time(&(inode)->xtime, \ + raw_inode->xtime ## _extra); \ +} while (0) + +#define EXT4_EINODE_GET_XTIME(xtime, einode, raw_inode) \ +do { \ + if (EXT4_FITS_IN_INODE(raw_inode, einode, xtime)) \ + (einode)->xtime.tv_sec = \ + (signed)le32_to_cpu((raw_inode)->xtime); \ + if (EXT4_FITS_IN_INODE(raw_inode, einode, xtime ## _extra)) \ + ext4_decode_extra_time(&(einode)->xtime, \ + raw_inode->xtime ## _extra); \ +} while (0) + #if defined(__KERNEL__) || defined(__linux__) #define i_reserved1 osd1.linux1.l_i_reserved1 #define i_frag osd2.linux2.l_i_frag @@ -533,6 +615,13 @@ static inline struct ext4_inode_info *EXT4_I(struct inode *inode) return container_of(inode, struct ext4_inode_info, vfs_inode); } +static inline struct timespec ext4_current_time(struct inode *inode) +{ + return (inode->i_sb->s_time_gran < NSEC_PER_SEC) ? + current_fs_time(inode->i_sb) : CURRENT_TIME_SEC; +} + + static inline int ext4_valid_inum(struct super_block *sb, unsigned long ino) { return ino == EXT4_ROOT_INO || @@ -603,6 +692,8 @@ static inline int ext4_valid_inum(struct super_block *sb, unsigned long ino) #define EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 #define EXT4_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 #define EXT4_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 +#define EXT4_FEATURE_RO_COMPAT_DIR_NLINK 0x0020 +#define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE 0x0040 #define EXT4_FEATURE_INCOMPAT_COMPRESSION 0x0001 #define EXT4_FEATURE_INCOMPAT_FILETYPE 0x0002 @@ -620,6 +711,8 @@ static inline int ext4_valid_inum(struct super_block *sb, unsigned long ino) EXT4_FEATURE_INCOMPAT_64BIT) #define EXT4_FEATURE_RO_COMPAT_SUPP (EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER| \ EXT4_FEATURE_RO_COMPAT_LARGE_FILE| \ + EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \ + EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE | \ EXT4_FEATURE_RO_COMPAT_BTREE_DIR) /* @@ -862,6 +955,7 @@ extern int ext4_change_inode_journal_flag(struct inode *, int); extern int ext4_get_inode_loc(struct inode *, struct ext4_iloc *); extern void ext4_truncate (struct inode *); extern void ext4_set_inode_flags(struct inode *); +extern void ext4_get_inode_flags(struct ext4_inode_info *); extern void ext4_set_aops(struct inode *inode); extern int ext4_writepage_trans_blocks(struct inode *); extern int ext4_block_truncate_page(handle_t *handle, struct page *page, @@ -983,6 +1077,8 @@ extern int ext4_ext_get_blocks(handle_t *handle, struct inode *inode, extern void ext4_ext_truncate(struct inode *, struct page *); extern void ext4_ext_init(struct super_block *); extern void ext4_ext_release(struct super_block *); +extern long ext4_fallocate(struct inode *inode, int mode, loff_t offset, + loff_t len); static inline int ext4_get_blocks_wrap(handle_t *handle, struct inode *inode, sector_t block, unsigned long max_blocks, struct buffer_head *bh, diff --git a/include/linux/ext4_fs_extents.h b/include/linux/ext4_fs_extents.h index acfe59740b03..81406f3655d4 100644 --- a/include/linux/ext4_fs_extents.h +++ b/include/linux/ext4_fs_extents.h @@ -141,7 +141,25 @@ typedef int (*ext_prepare_callback)(struct inode *, struct ext4_ext_path *, #define EXT_MAX_BLOCK 0xffffffff -#define EXT_MAX_LEN ((1UL << 15) - 1) +/* + * EXT_INIT_MAX_LEN is the maximum number of blocks we can have in an + * initialized extent. This is 2^15 and not (2^16 - 1), since we use the + * MSB of ee_len field in the extent datastructure to signify if this + * particular extent is an initialized extent or an uninitialized (i.e. + * preallocated). + * EXT_UNINIT_MAX_LEN is the maximum number of blocks we can have in an + * uninitialized extent. + * If ee_len is <= 0x8000, it is an initialized extent. Otherwise, it is an + * uninitialized one. In other words, if MSB of ee_len is set, it is an + * uninitialized extent with only one special scenario when ee_len = 0x8000. + * In this case we can not have an uninitialized extent of zero length and + * thus we make it as a special case of initialized extent with 0x8000 length. + * This way we get better extent-to-group alignment for initialized extents. + * Hence, the maximum number of blocks we can have in an *initialized* + * extent is 2^15 (32768) and in an *uninitialized* extent is 2^15-1 (32767). + */ +#define EXT_INIT_MAX_LEN (1UL << 15) +#define EXT_UNINIT_MAX_LEN (EXT_INIT_MAX_LEN - 1) #define EXT_FIRST_EXTENT(__hdr__) \ @@ -188,8 +206,31 @@ ext4_ext_invalidate_cache(struct inode *inode) EXT4_I(inode)->i_cached_extent.ec_type = EXT4_EXT_CACHE_NO; } +static inline void ext4_ext_mark_uninitialized(struct ext4_extent *ext) +{ + /* We can not have an uninitialized extent of zero length! */ + BUG_ON((le16_to_cpu(ext->ee_len) & ~EXT_INIT_MAX_LEN) == 0); + ext->ee_len |= cpu_to_le16(EXT_INIT_MAX_LEN); +} + +static inline int ext4_ext_is_uninitialized(struct ext4_extent *ext) +{ + /* Extent with ee_len of 0x8000 is treated as an initialized extent */ + return (le16_to_cpu(ext->ee_len) > EXT_INIT_MAX_LEN); +} + +static inline int ext4_ext_get_actual_len(struct ext4_extent *ext) +{ + return (le16_to_cpu(ext->ee_len) <= EXT_INIT_MAX_LEN ? + le16_to_cpu(ext->ee_len) : + (le16_to_cpu(ext->ee_len) - EXT_INIT_MAX_LEN)); +} + extern int ext4_extent_tree_init(handle_t *, struct inode *); extern int ext4_ext_calc_credits_for_insert(struct inode *, struct ext4_ext_path *); +extern int ext4_ext_try_to_merge(struct inode *inode, + struct ext4_ext_path *path, + struct ext4_extent *); extern unsigned int ext4_ext_check_overlap(struct inode *, struct ext4_extent *, struct ext4_ext_path *); extern int ext4_ext_insert_extent(handle_t *, struct inode *, struct ext4_ext_path *, struct ext4_extent *); extern int ext4_ext_walk_space(struct inode *, unsigned long, unsigned long, ext_prepare_callback, void *); diff --git a/include/linux/ext4_fs_i.h b/include/linux/ext4_fs_i.h index 9de494406995..1a511e9905aa 100644 --- a/include/linux/ext4_fs_i.h +++ b/include/linux/ext4_fs_i.h @@ -153,6 +153,11 @@ struct ext4_inode_info { unsigned long i_ext_generation; struct ext4_ext_cache i_cached_extent; + /* + * File creation time. Its function is same as that of + * struct timespec i_{a,c,m}time in the generic inode. + */ + struct timespec i_crtime; }; #endif /* _LINUX_EXT4_FS_I */ diff --git a/include/linux/ext4_fs_sb.h b/include/linux/ext4_fs_sb.h index 2347557a327a..1b2ffee12be9 100644 --- a/include/linux/ext4_fs_sb.h +++ b/include/linux/ext4_fs_sb.h @@ -73,7 +73,7 @@ struct ext4_sb_info { struct list_head s_orphan; unsigned long s_commit_interval; struct block_device *journal_bdev; -#ifdef CONFIG_JBD_DEBUG +#ifdef CONFIG_JBD2_DEBUG struct timer_list turn_ro_timer; /* For turning read-only (crash simulation) */ wait_queue_head_t ro_wait_queue; /* For people waiting for the fs to go read-only */ #endif @@ -81,6 +81,7 @@ struct ext4_sb_info { char *s_qf_names[MAXQUOTAS]; /* Names of quota files with journalled quota */ int s_jquota_fmt; /* Format of quota to use */ #endif + unsigned int s_want_extra_isize; /* New inodes should reserve # bytes */ #ifdef EXTENTS_STATS /* ext4 extents stats */ diff --git a/include/linux/falloc.h b/include/linux/falloc.h new file mode 100644 index 000000000000..8e912ab6a072 --- /dev/null +++ b/include/linux/falloc.h @@ -0,0 +1,6 @@ +#ifndef _FALLOC_H_ +#define _FALLOC_H_ + +#define FALLOC_FL_KEEP_SIZE 0x01 /* default is extend size */ + +#endif /* _FALLOC_H_ */ diff --git a/include/linux/freezer.h b/include/linux/freezer.h index 2d38b1a74662..efded00ad08c 100644 --- a/include/linux/freezer.h +++ b/include/linux/freezer.h @@ -5,7 +5,7 @@ #include <linux/sched.h> -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP /* * Check if a process has been frozen */ @@ -25,7 +25,7 @@ static inline int freezing(struct task_struct *p) /* * Request that a process be frozen */ -static inline void freeze(struct task_struct *p) +static inline void set_freeze_flag(struct task_struct *p) { set_tsk_thread_flag(p, TIF_FREEZE); } @@ -33,7 +33,7 @@ static inline void freeze(struct task_struct *p) /* * Sometimes we may need to cancel the previous 'freeze' request */ -static inline void do_not_freeze(struct task_struct *p) +static inline void clear_freeze_flag(struct task_struct *p) { clear_tsk_thread_flag(p, TIF_FREEZE); } @@ -56,7 +56,7 @@ static inline int thaw_process(struct task_struct *p) wake_up_process(p); return 1; } - clear_tsk_thread_flag(p, TIF_FREEZE); + clear_freeze_flag(p); task_unlock(p); return 0; } @@ -126,10 +126,11 @@ static inline void set_freezable(void) current->flags &= ~PF_NOFREEZE; } -#else +#else /* !CONFIG_PM_SLEEP */ static inline int frozen(struct task_struct *p) { return 0; } static inline int freezing(struct task_struct *p) { return 0; } -static inline void freeze(struct task_struct *p) { BUG(); } +static inline void set_freeze_flag(struct task_struct *p) {} +static inline void clear_freeze_flag(struct task_struct *p) {} static inline int thaw_process(struct task_struct *p) { return 1; } static inline void refrigerator(void) {} @@ -142,6 +143,6 @@ static inline void freezer_do_not_count(void) {} static inline void freezer_count(void) {} static inline int freezer_should_skip(struct task_struct *p) { return 0; } static inline void set_freezable(void) {} -#endif +#endif /* !CONFIG_PM_SLEEP */ #endif /* FREEZER_H_INCLUDED */ diff --git a/include/linux/fs.h b/include/linux/fs.h index 98205f680476..16421f662a7a 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -697,20 +697,26 @@ struct fown_struct { * Track a single file's readahead state */ struct file_ra_state { - unsigned long start; /* Current window */ - unsigned long size; - unsigned long flags; /* ra flags RA_FLAG_xxx*/ - unsigned long cache_hit; /* cache hit count*/ - unsigned long prev_index; /* Cache last read() position */ - unsigned long ahead_start; /* Ahead window */ - unsigned long ahead_size; + pgoff_t start; /* where readahead started */ + unsigned long size; /* # of readahead pages */ + unsigned long async_size; /* do asynchronous readahead when + there are only # of pages ahead */ + unsigned long ra_pages; /* Maximum readahead window */ unsigned long mmap_hit; /* Cache hit stat for mmap accesses */ unsigned long mmap_miss; /* Cache miss stat for mmap accesses */ + unsigned long prev_index; /* Cache last read() position */ unsigned int prev_offset; /* Offset where last read() ended in a page */ }; -#define RA_FLAG_MISS 0x01 /* a cache miss occured against this file */ -#define RA_FLAG_INCACHE 0x02 /* file is already in cache */ + +/* + * Check if @index falls in the readahead windows. + */ +static inline int ra_has_index(struct file_ra_state *ra, pgoff_t index) +{ + return (index >= ra->start && + index < ra->start + ra->size); +} struct file { /* @@ -862,7 +868,7 @@ extern void locks_init_lock(struct file_lock *); extern void locks_copy_lock(struct file_lock *, struct file_lock *); extern void locks_remove_posix(struct file *, fl_owner_t); extern void locks_remove_flock(struct file *); -extern int posix_test_lock(struct file *, struct file_lock *); +extern void posix_test_lock(struct file *, struct file_lock *); extern int posix_lock_file(struct file *, struct file_lock *, struct file_lock *); extern int posix_lock_file_wait(struct file *, struct file_lock *); extern int posix_unblock_lock(struct file *, struct file_lock *); @@ -872,7 +878,8 @@ extern int vfs_cancel_lock(struct file *filp, struct file_lock *fl); extern int flock_lock_file_wait(struct file *filp, struct file_lock *fl); extern int __break_lease(struct inode *inode, unsigned int flags); extern void lease_get_mtime(struct inode *, struct timespec *time); -extern int setlease(struct file *, long, struct file_lock **); +extern int generic_setlease(struct file *, long, struct file_lock **); +extern int vfs_setlease(struct file *, long, struct file_lock **); extern int lease_modify(struct file_lock **, int); extern int lock_may_read(struct inode *, loff_t start, unsigned long count); extern int lock_may_write(struct inode *, loff_t start, unsigned long count); @@ -1122,6 +1129,7 @@ struct file_operations { int (*flock) (struct file *, int, struct file_lock *); ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int); ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int); + int (*setlease)(struct file *, long, struct file_lock **); }; struct inode_operations { @@ -1147,6 +1155,8 @@ struct inode_operations { ssize_t (*listxattr) (struct dentry *, char *, size_t); int (*removexattr) (struct dentry *, const char *); void (*truncate_range)(struct inode *, loff_t, loff_t); + long (*fallocate)(struct inode *inode, int mode, loff_t offset, + loff_t len); }; struct seq_file; @@ -1459,7 +1469,7 @@ extern int alloc_chrdev_region(dev_t *, unsigned, unsigned, const char *); extern int register_chrdev_region(dev_t, unsigned, const char *); extern int register_chrdev(unsigned int, const char *, const struct file_operations *); -extern int unregister_chrdev(unsigned int, const char *); +extern void unregister_chrdev(unsigned int, const char *); extern void unregister_chrdev_region(dev_t, unsigned); extern int chrdev_open(struct inode *, struct file *); extern void chrdev_show(struct seq_file *,off_t); @@ -1649,7 +1659,6 @@ extern int sb_min_blocksize(struct super_block *, int); extern int generic_file_mmap(struct file *, struct vm_area_struct *); extern int generic_file_readonly_mmap(struct file *, struct vm_area_struct *); extern int file_read_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size); -extern int file_send_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size); int generic_write_checks(struct file *file, loff_t *pos, size_t *count, int isblk); extern ssize_t generic_file_aio_read(struct kiocb *, const struct iovec *, unsigned long, loff_t); extern ssize_t generic_file_aio_write(struct kiocb *, const struct iovec *, unsigned long, loff_t); diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h index 543cd3cd9e77..9bc045b8c478 100644 --- a/include/linux/fs_enet_pd.h +++ b/include/linux/fs_enet_pd.h @@ -16,6 +16,7 @@ #ifndef FS_ENET_PD_H #define FS_ENET_PD_H +#include <linux/string.h> #include <asm/types.h> #define FS_ENET_NAME "fs_enet" @@ -119,6 +120,7 @@ struct fs_platform_info { u32 cp_page; /* CPM page */ u32 cp_block; /* CPM sblock */ + u32 cp_command; /* CPM page/sblock/mcn */ u32 clk_trx; /* some stuff for pins & mux configuration*/ u32 clk_rx; @@ -133,7 +135,11 @@ struct fs_platform_info { u32 device_flags; int phy_addr; /* the phy address (-1 no phy) */ +#ifdef CONFIG_PPC_CPM_NEW_BINDING + char bus_id[16]; +#else const char* bus_id; +#endif int phy_irq; /* the phy irq (if it exists) */ const struct fs_mii_bus_info *bus_info; diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 695741b0e420..1831b196c70a 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -53,6 +53,7 @@ struct gianfar_platform_data { u32 bus_id; u32 phy_id; u8 mac_addr[6]; + phy_interface_t interface; }; struct gianfar_mdio_data { diff --git a/include/linux/genetlink.h b/include/linux/genetlink.h index f7a93770e1be..7da02c93002b 100644 --- a/include/linux/genetlink.h +++ b/include/linux/genetlink.h @@ -39,6 +39,9 @@ enum { CTRL_CMD_NEWOPS, CTRL_CMD_DELOPS, CTRL_CMD_GETOPS, + CTRL_CMD_NEWMCAST_GRP, + CTRL_CMD_DELMCAST_GRP, + CTRL_CMD_GETMCAST_GRP, /* unused */ __CTRL_CMD_MAX, }; @@ -52,6 +55,7 @@ enum { CTRL_ATTR_HDRSIZE, CTRL_ATTR_MAXATTR, CTRL_ATTR_OPS, + CTRL_ATTR_MCAST_GROUPS, __CTRL_ATTR_MAX, }; @@ -66,4 +70,13 @@ enum { #define CTRL_ATTR_OP_MAX (__CTRL_ATTR_OP_MAX - 1) +enum { + CTRL_ATTR_MCAST_GRP_UNSPEC, + CTRL_ATTR_MCAST_GRP_NAME, + CTRL_ATTR_MCAST_GRP_ID, + __CTRL_ATTR_MCAST_GRP_MAX, +}; + +#define CTRL_ATTR_MCAST_GRP_MAX (__CTRL_ATTR_MCAST_GRP_MAX - 1) + #endif /* __LINUX_GENERIC_NETLINK_H */ diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 9756fc102a83..a47b8025d399 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -264,7 +264,7 @@ static inline void set_capacity(struct gendisk *disk, sector_t size) #ifdef CONFIG_SOLARIS_X86_PARTITION -#define SOLARIS_X86_NUMSLICE 8 +#define SOLARIS_X86_NUMSLICE 16 #define SOLARIS_X86_VTOC_SANE (0x600DDEEEUL) struct solaris_x86_slice { diff --git a/include/linux/gfs2_ondisk.h b/include/linux/gfs2_ondisk.h index a44a6a078f0a..c3c19f926e6f 100644 --- a/include/linux/gfs2_ondisk.h +++ b/include/linux/gfs2_ondisk.h @@ -170,6 +170,33 @@ struct gfs2_rgrp { }; /* + * quota linked list: user quotas and group quotas form two separate + * singly linked lists. ll_next stores uids or gids of next quotas in the + * linked list. + +Given the uid/gid, how to calculate the quota file offsets for the corresponding +gfs2_quota structures on disk: + +for user quotas, given uid, +offset = uid * sizeof(struct gfs2_quota); + +for group quotas, given gid, +offset = (gid * sizeof(struct gfs2_quota)) + sizeof(struct gfs2_quota); + + + uid:0 gid:0 uid:12 gid:12 uid:17 gid:17 uid:5142 gid:5142 ++-------+-------+ +-------+-------+ +-------+- - - -+ +- - - -+-------+ +| valid | valid | :: | valid | valid | :: | valid | inval | :: | inval | valid | ++-------+-------+ +-------+-------+ +-------+- - - -+ +- - - -+-------+ +next:12 next:12 next:17 next:5142 next:NULL next:NULL + | | | | |<-- user quota list | + \______|___________/ \______|___________/ group quota list -->| + | | | + \__________________/ \_______________________________________/ + +*/ + +/* * quota structure */ @@ -177,7 +204,8 @@ struct gfs2_quota { __be64 qu_limit; __be64 qu_warn; __be64 qu_value; - __u8 qu_reserved[64]; + __be32 qu_ll_next; /* location of next quota in list */ + __u8 qu_reserved[60]; }; /* diff --git a/include/linux/highmem.h b/include/linux/highmem.h index 12c5e4e3135a..1fcb0033179e 100644 --- a/include/linux/highmem.h +++ b/include/linux/highmem.h @@ -103,21 +103,6 @@ __alloc_zeroed_user_highpage(gfp_t movableflags, #endif /** - * alloc_zeroed_user_highpage - Allocate a zeroed HIGHMEM page for a VMA - * @vma: The VMA the page is to be allocated for - * @vaddr: The virtual address the page will be inserted into - * - * This function will allocate a page for a VMA that the caller knows will - * not be able to move in the future using move_pages() or reclaim. If it - * is known that the page can move, use alloc_zeroed_user_highpage_movable - */ -static inline struct page * -alloc_zeroed_user_highpage(struct vm_area_struct *vma, unsigned long vaddr) -{ - return __alloc_zeroed_user_highpage(0, vma, vaddr); -} - -/** * alloc_zeroed_user_highpage_movable - Allocate a zeroed HIGHMEM page for a VMA that the caller knows can move * @vma: The VMA the page is to be allocated for * @vaddr: The virtual address the page will be inserted into diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 49b7053043ad..3a19b032c0eb 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -1,6 +1,8 @@ #ifndef _LINUX_HUGETLB_H #define _LINUX_HUGETLB_H +#include <linux/fs.h> + #ifdef CONFIG_HUGETLB_PAGE #include <linux/mempolicy.h> @@ -64,11 +66,8 @@ void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr, * If the arch doesn't supply something else, assume that hugepage * size aligned regions are ok without further preparation. */ -static inline int prepare_hugepage_range(unsigned long addr, unsigned long len, - pgoff_t pgoff) +static inline int prepare_hugepage_range(unsigned long addr, unsigned long len) { - if (pgoff & (~HPAGE_MASK >> PAGE_SHIFT)) - return -EINVAL; if (len & ~HPAGE_MASK) return -EINVAL; if (addr & ~HPAGE_MASK) @@ -76,8 +75,7 @@ static inline int prepare_hugepage_range(unsigned long addr, unsigned long len, return 0; } #else -int prepare_hugepage_range(unsigned long addr, unsigned long len, - pgoff_t pgoff); +int prepare_hugepage_range(unsigned long addr, unsigned long len); #endif #ifndef ARCH_HAS_SETCLEAR_HUGE_PTE @@ -115,7 +113,7 @@ static inline unsigned long hugetlb_total_pages(void) #define hugetlb_report_meminfo(buf) 0 #define hugetlb_report_node_meminfo(n, buf) 0 #define follow_huge_pmd(mm, addr, pmd, write) NULL -#define prepare_hugepage_range(addr,len,pgoff) (-EINVAL) +#define prepare_hugepage_range(addr,len) (-EINVAL) #define pmd_huge(x) 0 #define is_hugepage_only_range(mm, addr, len) 0 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) ({BUG(); 0; }) diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index aa83d4163096..a271b67a8e2d 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -115,9 +115,11 @@ #define I2C_DRIVERID_KS0127 86 /* Samsung ks0127 video decoder */ #define I2C_DRIVERID_TLV320AIC23B 87 /* TI TLV320AIC23B audio codec */ #define I2C_DRIVERID_ISL1208 88 /* Intersil ISL1208 RTC */ -#define I2C_DRIVERID_WM8731 89 /* Wolfson WM8731 audio codec */ -#define I2C_DRIVERID_WM8750 90 /* Wolfson WM8750 audio codec */ -#define I2C_DRIVERID_WM8753 91 /* Wolfson WM8753 audio codec */ +#define I2C_DRIVERID_WM8731 89 /* Wolfson WM8731 audio codec */ +#define I2C_DRIVERID_WM8750 90 /* Wolfson WM8750 audio codec */ +#define I2C_DRIVERID_WM8753 91 /* Wolfson WM8753 audio codec */ +#define I2C_DRIVERID_LM4857 92 /* LM4857 Audio Amplifier */ +#define I2C_DRIVERID_VP27SMPX 93 /* Panasonic VP27s tuner internal MPX */ #define I2C_DRIVERID_I2CDEV 900 #define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */ @@ -195,6 +197,7 @@ #define I2C_HW_B_EM28XX 0x01001f /* em28xx video capture cards */ #define I2C_HW_B_CX2341X 0x010020 /* Conexant CX2341X MPEG encoder cards */ #define I2C_HW_B_INTELFB 0x010021 /* intel framebuffer driver */ +#define I2C_HW_B_CX23885 0x010022 /* conexant 23885 based tv cards (bus1) */ /* --- PCF 8584 based algorithms */ #define I2C_HW_P_LP 0x020000 /* Parallel port interface */ diff --git a/include/linux/i2c-isa.h b/include/linux/i2c-isa.h deleted file mode 100644 index 67e3598c4cec..000000000000 --- a/include/linux/i2c-isa.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * i2c-isa.h - definitions for the i2c-isa pseudo-i2c-adapter interface - * - * Copyright (C) 2005 Jean Delvare <khali@linux-fr.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _LINUX_I2C_ISA_H -#define _LINUX_I2C_ISA_H - -#include <linux/i2c.h> - -extern int i2c_isa_add_driver(struct i2c_driver *driver); -extern int i2c_isa_del_driver(struct i2c_driver *driver); - -/* Detect whether we are on the isa bus. This is only useful to hybrid - (i2c+isa) drivers. */ -#define i2c_is_isa_adapter(adapptr) \ - ((adapptr)->id == I2C_HW_ISA) -#define i2c_is_isa_client(clientptr) \ - i2c_is_isa_adapter((clientptr)->adapter) - -#endif /* _LINUX_I2C_ISA_H */ diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 2eaba21b9b1a..2a32f2fd940d 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -156,10 +156,14 @@ struct i2c_driver { * @name: Indicates the type of the device, usually a chip name that's * generic enough to hide second-sourcing and compatible revisions. * @adapter: manages the bus segment hosting this I2C device + * @driver: device's driver, hence pointer to access routines + * @usage_count: counts current number of users of this client * @dev: Driver model device node for the slave. * @irq: indicates the IRQ generated by this device (if any) * @driver_name: Identifies new-style driver used with this device; also * used as the module name for hotplug/coldplug modprobe support. + * @list: list of active/busy clients + * @released: used to synchronize client releases & detaches and references * * An i2c_client identifies a single device (i.e. chip) connected to an * i2c bus. The behaviour exposed to Linux is defined by the driver @@ -368,7 +372,6 @@ struct i2c_client_address_data { /* The numbers to use to set I2C bus address */ #define ANY_I2C_BUS 0xffff -#define ANY_I2C_ISA_BUS 9191 /* ----- functions exported by i2c.o */ diff --git a/include/linux/i2o.h b/include/linux/i2o.h index 333a370a3bdc..9752307d16ba 100644 --- a/include/linux/i2o.h +++ b/include/linux/i2o.h @@ -946,8 +946,7 @@ static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name, strcpy(pool->name, name); pool->slab = - kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL, - NULL); + kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL); if (!pool->slab) goto free_name; diff --git a/include/linux/ide.h b/include/linux/ide.h index 19ab25804056..85d448b4abec 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -555,7 +555,7 @@ typedef struct ide_drive_s { char name[4]; /* drive name, such as "hda" */ char driver_req[10]; /* requests specific driver */ - request_queue_t *queue; /* request queue */ + struct request_queue *queue; /* request queue */ struct request *rq; /* current request */ struct ide_drive_s *next; /* circular list of hwgroup drives */ @@ -634,7 +634,7 @@ typedef struct ide_drive_s { unsigned int bios_cyl; /* BIOS/fdisk/LILO number of cyls */ unsigned int cyl; /* "real" number of cyls */ - unsigned int drive_data; /* use by tuneproc/selectproc */ + unsigned int drive_data; /* used by set_pio_mode/selectproc */ unsigned int failures; /* current failure count */ unsigned int max_failures; /* maximum allowed failure count */ u64 probed_capacity;/* initial reported media capacity (ide-cd only currently) */ @@ -681,6 +681,10 @@ typedef struct hwif_s { u8 straight8; /* Alan's straight 8 check */ u8 bus_state; /* power state of the IDE bus */ + u8 host_flags; + + u8 pio_mask; + u8 atapi_dma; /* host supports atapi_dma */ u8 ultra_mask; u8 mwdma_mask; @@ -698,10 +702,10 @@ typedef struct hwif_s { #if 0 ide_hwif_ops_t *hwifops; #else - /* routine to tune PIO mode for drives */ - void (*tuneproc)(ide_drive_t *, u8); + /* routine to set PIO mode for drives */ + void (*set_pio_mode)(ide_drive_t *, const u8); /* routine to retune DMA modes for drives */ - int (*speedproc)(ide_drive_t *, u8); + int (*speedproc)(ide_drive_t *, const u8); /* tweaks hardware to select drive */ void (*selectproc)(ide_drive_t *); /* chipset polling based on hba specifics */ @@ -719,6 +723,7 @@ typedef struct hwif_s { /* driver soft-power interface */ int (*busproc)(ide_drive_t *, int); #endif + u8 (*mdma_filter)(ide_drive_t *); u8 (*udma_filter)(ide_drive_t *); void (*ata_input_data)(ide_drive_t *, void *, u32); @@ -1202,7 +1207,7 @@ extern void ide_stall_queue(ide_drive_t *drive, unsigned long timeout); extern int ide_spin_wait_hwgroup(ide_drive_t *); extern void ide_timer_expiry(unsigned long); extern irqreturn_t ide_intr(int irq, void *dev_id); -extern void do_ide_request(request_queue_t *); +extern void do_ide_request(struct request_queue *); void ide_init_disk(struct gendisk *, ide_drive_t *); @@ -1244,7 +1249,19 @@ typedef struct ide_pci_enablebit_s { enum { /* Uses ISA control ports not PCI ones. */ - IDEPCI_FLAG_ISA_PORTS = (1 << 0), + IDE_HFLAG_ISA_PORTS = (1 << 0), + /* single port device */ + IDE_HFLAG_SINGLE = (1 << 1), + /* don't use legacy PIO blacklist */ + IDE_HFLAG_PIO_NO_BLACKLIST = (1 << 2), + /* don't use conservative PIO "downgrade" */ + IDE_HFLAG_PIO_NO_DOWNGRADE = (1 << 3), + /* use PIO8/9 for prefetch off/on */ + IDE_HFLAG_ABUSE_PREFETCH = (1 << 4), + /* use PIO6/7 for fast-devsel off/on */ + IDE_HFLAG_ABUSE_FAST_DEVSEL = (1 << 5), + /* use 100-102 and 200-202 PIO values to set DMA modes */ + IDE_HFLAG_ABUSE_DMA_MODES = (1 << 6), }; typedef struct ide_pci_device_s { @@ -1256,13 +1273,13 @@ typedef struct ide_pci_device_s { void (*init_hwif)(ide_hwif_t *); void (*init_dma)(ide_hwif_t *, unsigned long); void (*fixup)(ide_hwif_t *); - u8 channels; u8 autodma; ide_pci_enablebit_t enablebits[2]; u8 bootable; unsigned int extra; struct ide_pci_device_s *next; - u8 flags; + u8 host_flags; + u8 pio_mask; u8 udma_mask; } ide_pci_device_t; @@ -1275,16 +1292,24 @@ void ide_init_sg_cmd(ide_drive_t *, struct request *); #define BAD_DMA_DRIVE 0 #define GOOD_DMA_DRIVE 1 -#ifdef CONFIG_BLK_DEV_IDEDMA struct drive_list_entry { const char *id_model; const char *id_firmware; }; int ide_in_drive_list(struct hd_driveid *, const struct drive_list_entry *); + +#ifdef CONFIG_BLK_DEV_IDEDMA int __ide_dma_bad_drive(ide_drive_t *); int __ide_dma_good_drive(ide_drive_t *); -u8 ide_max_dma_mode(ide_drive_t *); + +u8 ide_find_dma_mode(ide_drive_t *, u8); + +static inline u8 ide_max_dma_mode(ide_drive_t *drive) +{ + return ide_find_dma_mode(drive, XFER_UDMA_6); +} + int ide_tune_dma(ide_drive_t *); void ide_dma_off(ide_drive_t *); void ide_dma_verbose(ide_drive_t *); @@ -1302,7 +1327,6 @@ void ide_dma_host_off(ide_drive_t *); void ide_dma_off_quietly(ide_drive_t *); void ide_dma_host_on(ide_drive_t *); extern int __ide_dma_on(ide_drive_t *); -extern int __ide_dma_check(ide_drive_t *); extern int ide_dma_setup(ide_drive_t *); extern void ide_dma_start(ide_drive_t *); extern int __ide_dma_end(ide_drive_t *); @@ -1311,6 +1335,7 @@ extern void ide_dma_timeout(ide_drive_t *); #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ #else +static inline u8 ide_find_dma_mode(ide_drive_t *drive, u8 speed) { return 0; } static inline u8 ide_max_dma_mode(ide_drive_t *drive) { return 0; } static inline int ide_tune_dma(ide_drive_t *drive) { return 0; } static inline void ide_dma_off(ide_drive_t *drive) { ; } @@ -1327,11 +1352,13 @@ extern int ide_acpi_exec_tfs(ide_drive_t *drive); extern void ide_acpi_get_timing(ide_hwif_t *hwif); extern void ide_acpi_push_timing(ide_hwif_t *hwif); extern void ide_acpi_init(ide_hwif_t *hwif); +extern void ide_acpi_set_state(ide_hwif_t *hwif, int on); #else static inline int ide_acpi_exec_tfs(ide_drive_t *drive) { return 0; } static inline void ide_acpi_get_timing(ide_hwif_t *hwif) { ; } static inline void ide_acpi_push_timing(ide_hwif_t *hwif) { ; } static inline void ide_acpi_init(ide_hwif_t *hwif) { ; } +static inline void ide_acpi_set_state(ide_hwif_t *hwif, int on) {} #endif extern int ide_hwif_request_regions(ide_hwif_t *hwif); @@ -1357,12 +1384,29 @@ static inline void ide_set_hwifdata (ide_hwif_t * hwif, void *data) } /* ide-lib.c */ -u8 ide_rate_filter(ide_drive_t *, u8); extern char *ide_xfer_verbose(u8 xfer_rate); extern void ide_toggle_bounce(ide_drive_t *drive, int on); extern int ide_set_xfer_rate(ide_drive_t *drive, u8 rate); int ide_use_fast_pio(ide_drive_t *); +static inline int ide_dev_has_iordy(struct hd_driveid *id) +{ + return ((id->field_valid & 2) && (id->capability & 8)) ? 1 : 0; +} + +static inline int ide_dev_is_sata(struct hd_driveid *id) +{ + /* + * See if word 93 is 0 AND drive is at least ATA-5 compatible + * verifying that word 80 by casting it to a signed type -- + * this trick allows us to filter out the reserved values of + * 0x0000 and 0xffff along with the earlier ATA revisions... + */ + if (id->hw_config == 0 && (short)id->major_rev_num >= 0x0020) + return 1; + return 0; +} + u8 ide_dump_status(ide_drive_t *, const char *, u8); typedef struct ide_pio_timings_s { @@ -1372,16 +1416,16 @@ typedef struct ide_pio_timings_s { /* active + recovery (+ setup for some chips) */ } ide_pio_timings_t; -typedef struct ide_pio_data_s { - u8 pio_mode; - u8 use_iordy; - u8 overridden; - unsigned int cycle_time; -} ide_pio_data_t; - -extern u8 ide_get_best_pio_mode (ide_drive_t *drive, u8 mode_wanted, u8 max_mode, ide_pio_data_t *d); +unsigned int ide_pio_cycle_time(ide_drive_t *, u8); +u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); extern const ide_pio_timings_t ide_pio_timings[6]; +void ide_set_pio(ide_drive_t *, u8); + +static inline void ide_set_max_pio(ide_drive_t *drive) +{ + ide_set_pio(drive, 255); +} extern spinlock_t ide_lock; extern struct mutex ide_cfg_mtx; diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index 272f8c8c90da..30621c27159f 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -16,6 +16,7 @@ #define IEEE80211_H #include <linux/types.h> +#include <asm/byteorder.h> #define FCS_LEN 4 @@ -350,4 +351,64 @@ enum ieee80211_eid { #define WLAN_MAX_KEY_LEN 32 +/** + * ieee80211_get_SA - get pointer to SA + * + * Given an 802.11 frame, this function returns the offset + * to the source address (SA). It does not verify that the + * header is long enough to contain the address, and the + * header must be long enough to contain the frame control + * field. + * + * @hdr: the frame + */ +static inline u8 *ieee80211_get_SA(struct ieee80211_hdr *hdr) +{ + u8 *raw = (u8 *) hdr; + u8 tofrom = (*(raw+1)) & 3; /* get the TODS and FROMDS bits */ + + switch (tofrom) { + case 2: + return hdr->addr3; + case 3: + return hdr->addr4; + } + return hdr->addr2; +} + +/** + * ieee80211_get_DA - get pointer to DA + * + * Given an 802.11 frame, this function returns the offset + * to the destination address (DA). It does not verify that + * the header is long enough to contain the address, and the + * header must be long enough to contain the frame control + * field. + * + * @hdr: the frame + */ +static inline u8 *ieee80211_get_DA(struct ieee80211_hdr *hdr) +{ + u8 *raw = (u8 *) hdr; + u8 to_ds = (*(raw+1)) & 1; /* get the TODS bit */ + + if (to_ds) + return hdr->addr3; + return hdr->addr1; +} + +/** + * ieee80211_get_morefrag - determine whether the MOREFRAGS bit is set + * + * This function determines whether the "more fragments" bit is set + * in the frame. + * + * @hdr: the frame + */ +static inline int ieee80211_get_morefrag(struct ieee80211_hdr *hdr) +{ + return (le16_to_cpu(hdr->frame_control) & + IEEE80211_FCTL_MOREFRAGS) != 0; +} + #endif /* IEEE80211_H */ diff --git a/include/linux/if_arcnet.h b/include/linux/if_arcnet.h index af380cb876a0..27ea2ac445ad 100644 --- a/include/linux/if_arcnet.h +++ b/include/linux/if_arcnet.h @@ -59,7 +59,7 @@ struct arc_rfc1201 { uint8_t proto; /* protocol ID field - varies */ uint8_t split_flag; /* for use with split packets */ - uint16_t sequence; /* sequence number */ + __be16 sequence; /* sequence number */ uint8_t payload[0]; /* space remaining in packet (504 bytes)*/ }; #define RFC1201_HDR_SIZE 4 diff --git a/include/linux/if_bridge.h b/include/linux/if_bridge.h index 4ff211d98769..99e3a1a00099 100644 --- a/include/linux/if_bridge.h +++ b/include/linux/if_bridge.h @@ -104,7 +104,7 @@ struct __fdb_entry #include <linux/netdevice.h> -extern void brioctl_set(int (*ioctl_hook)(unsigned int, void __user *)); +extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); extern struct sk_buff *(*br_handle_frame_hook)(struct net_bridge_port *p, struct sk_buff *skb); extern int (*br_should_route_hook)(struct sk_buff **pskb); diff --git a/include/linux/if_eql.h b/include/linux/if_eql.h index b68752fdc5c4..79c4f268410d 100644 --- a/include/linux/if_eql.h +++ b/include/linux/if_eql.h @@ -58,7 +58,6 @@ typedef struct equalizer { slave_queue_t queue; int min_slaves; int max_slaves; - struct net_device_stats stats; struct timer_list timer; } equalizer_t; diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h index 3213f6f4aa58..5f9297793661 100644 --- a/include/linux/if_ether.h +++ b/include/linux/if_ether.h @@ -117,9 +117,19 @@ static inline struct ethhdr *eth_hdr(const struct sk_buff *skb) return (struct ethhdr *)skb_mac_header(skb); } +int eth_header_parse(const struct sk_buff *skb, unsigned char *haddr); + #ifdef CONFIG_SYSCTL extern struct ctl_table ether_table[]; #endif + +/* + * Display a 6 byte device address (MAC) in a readable format. + */ +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +extern char *print_mac(char *buf, const u8 *addr); +#define DECLARE_MAC_BUF(var) char var[18] __maybe_unused + #endif #endif /* _LINUX_IF_ETHER_H */ diff --git a/include/linux/if_link.h b/include/linux/if_link.h index 422084d18ce1..84c3492ae5cb 100644 --- a/include/linux/if_link.h +++ b/include/linux/if_link.h @@ -78,6 +78,7 @@ enum IFLA_LINKMODE, IFLA_LINKINFO, #define IFLA_LINKINFO IFLA_LINKINFO + IFLA_NET_NS_PID, __IFLA_MAX }; diff --git a/include/linux/if_pppol2tp.h b/include/linux/if_pppol2tp.h index 516203b6fdeb..a7d6a2234b31 100644 --- a/include/linux/if_pppol2tp.h +++ b/include/linux/if_pppol2tp.h @@ -32,8 +32,8 @@ struct pppol2tp_addr struct sockaddr_in addr; /* IP address and port to send to */ - __be16 s_tunnel, s_session; /* For matching incoming packets */ - __be16 d_tunnel, d_session; /* For sending outgoing packets */ + __u16 s_tunnel, s_session; /* For matching incoming packets */ + __u16 d_tunnel, d_session; /* For sending outgoing packets */ }; /* Socket options: diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h index 25652545ba6e..40743e032845 100644 --- a/include/linux/if_pppox.h +++ b/include/linux/if_pppox.h @@ -40,7 +40,7 @@ /************************************************************************ * PPPoE addressing definition */ -typedef __u16 sid_t; +typedef __be16 sid_t; struct pppoe_addr{ sid_t sid; /* Session identifier */ unsigned char remote[ETH_ALEN]; /* Remote address */ @@ -90,8 +90,8 @@ struct sockaddr_pppol2tp { #define PADS_CODE 0x65 #define PADT_CODE 0xa7 struct pppoe_tag { - __u16 tag_type; - __u16 tag_len; + __be16 tag_type; + __be16 tag_len; char tag_data[0]; } __attribute ((packed)); @@ -118,8 +118,8 @@ struct pppoe_hdr { #error "Please fix <asm/byteorder.h>" #endif __u8 code; - __u16 sid; - __u16 length; + __be16 sid; + __be16 length; struct pppoe_tag tag[0]; } __attribute__ ((packed)); @@ -152,7 +152,7 @@ struct pppox_sock { union { struct pppoe_opt pppoe; } proto; - unsigned short num; + __be16 num; }; #define pppoe_dev proto.pppoe.dev #define pppoe_ifindex proto.pppoe.ifindex @@ -172,7 +172,7 @@ static inline struct sock *sk_pppox(struct pppox_sock *po) struct module; struct pppox_proto { - int (*create)(struct socket *sock); + int (*create)(struct net *net, struct socket *sock); int (*ioctl)(struct socket *sock, unsigned int cmd, unsigned long arg); struct module *owner; diff --git a/include/linux/if_shaper.h b/include/linux/if_shaper.h index 68c896a36a34..3b1b7ba19825 100644 --- a/include/linux/if_shaper.h +++ b/include/linux/if_shaper.h @@ -24,19 +24,7 @@ struct shaper unsigned long recovery; /* Time we can next clock a packet out on an empty queue */ spinlock_t lock; - struct net_device_stats stats; struct net_device *dev; - int (*hard_start_xmit) (struct sk_buff *skb, - struct net_device *dev); - int (*hard_header) (struct sk_buff *skb, - struct net_device *dev, - unsigned short type, - void *daddr, - void *saddr, - unsigned len); - int (*rebuild_header)(struct sk_buff *skb); - int (*hard_header_cache)(struct neighbour *neigh, struct hh_cache *hh); - void (*header_cache_update)(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr); struct net_device_stats* (*get_stats)(struct net_device *dev); struct timer_list timer; }; diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index 42eb6945b93e..33e489d5bb33 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -42,7 +42,6 @@ struct tun_struct { struct sk_buff_head readq; struct net_device *dev; - struct net_device_stats stats; struct fasync_struct *fasync; diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index f8443fdb124a..976d4b1067d1 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -62,7 +62,7 @@ struct vlan_hdr { #define VLAN_VID_MASK 0xfff /* found in socket.c */ -extern void vlan_ioctl_set(int (*hook)(void __user *)); +extern void vlan_ioctl_set(int (*hook)(struct net *, void __user *)); #define VLAN_NAME "vlan" diff --git a/include/linux/inet_lro.h b/include/linux/inet_lro.h new file mode 100644 index 000000000000..e1fc1d16d3cd --- /dev/null +++ b/include/linux/inet_lro.h @@ -0,0 +1,177 @@ +/* + * linux/include/linux/inet_lro.h + * + * Large Receive Offload (ipv4 / tcp) + * + * (C) Copyright IBM Corp. 2007 + * + * Authors: + * Jan-Bernd Themann <themann@de.ibm.com> + * Christoph Raisch <raisch@de.ibm.com> + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __INET_LRO_H_ +#define __INET_LRO_H_ + +#include <net/ip.h> +#include <net/tcp.h> + +/* + * LRO statistics + */ + +struct net_lro_stats { + unsigned long aggregated; + unsigned long flushed; + unsigned long no_desc; +}; + +/* + * LRO descriptor for a tcp session + */ +struct net_lro_desc { + struct sk_buff *parent; + struct sk_buff *last_skb; + struct skb_frag_struct *next_frag; + struct iphdr *iph; + struct tcphdr *tcph; + struct vlan_group *vgrp; + __wsum data_csum; + u32 tcp_rcv_tsecr; + u32 tcp_rcv_tsval; + u32 tcp_ack; + u32 tcp_next_seq; + u32 skb_tot_frags_len; + u16 ip_tot_len; + u16 tcp_saw_tstamp; /* timestamps enabled */ + u16 tcp_window; + u16 vlan_tag; + int pkt_aggr_cnt; /* counts aggregated packets */ + int vlan_packet; + int mss; + int active; +}; + +/* + * Large Receive Offload (LRO) Manager + * + * Fields must be set by driver + */ + +struct net_lro_mgr { + struct net_device *dev; + struct net_lro_stats stats; + + /* LRO features */ + unsigned long features; +#define LRO_F_NAPI 1 /* Pass packets to stack via NAPI */ +#define LRO_F_EXTRACT_VLAN_ID 2 /* Set flag if VLAN IDs are extracted + from received packets and eth protocol + is still ETH_P_8021Q */ + + u32 ip_summed; /* Set in non generated SKBs in page mode */ + u32 ip_summed_aggr; /* Set in aggregated SKBs: CHECKSUM_UNNECESSARY + * or CHECKSUM_NONE */ + + int max_desc; /* Max number of LRO descriptors */ + int max_aggr; /* Max number of LRO packets to be aggregated */ + + struct net_lro_desc *lro_arr; /* Array of LRO descriptors */ + + /* + * Optimized driver functions + * + * get_skb_header: returns tcp and ip header for packet in SKB + */ + int (*get_skb_header)(struct sk_buff *skb, void **ip_hdr, + void **tcpudp_hdr, u64 *hdr_flags, void *priv); + + /* hdr_flags: */ +#define LRO_IPV4 1 /* ip_hdr is IPv4 header */ +#define LRO_TCP 2 /* tcpudp_hdr is TCP header */ + + /* + * get_frag_header: returns mac, tcp and ip header for packet in SKB + * + * @hdr_flags: Indicate what kind of LRO has to be done + * (IPv4/IPv6/TCP/UDP) + */ + int (*get_frag_header)(struct skb_frag_struct *frag, void **mac_hdr, + void **ip_hdr, void **tcpudp_hdr, u64 *hdr_flags, + void *priv); +}; + +/* + * Processes a SKB + * + * @lro_mgr: LRO manager to use + * @skb: SKB to aggregate + * @priv: Private data that may be used by driver functions + * (for example get_tcp_ip_hdr) + */ + +void lro_receive_skb(struct net_lro_mgr *lro_mgr, + struct sk_buff *skb, + void *priv); + +/* + * Processes a SKB with VLAN HW acceleration support + */ + +void lro_vlan_hwaccel_receive_skb(struct net_lro_mgr *lro_mgr, + struct sk_buff *skb, + struct vlan_group *vgrp, + u16 vlan_tag, + void *priv); + +/* + * Processes a fragment list + * + * This functions aggregate fragments and generate SKBs do pass + * the packets to the stack. + * + * @lro_mgr: LRO manager to use + * @frags: Fragment to be processed. Must contain entire header in first + * element. + * @len: Length of received data + * @true_size: Actual size of memory the fragment is consuming + * @priv: Private data that may be used by driver functions + * (for example get_tcp_ip_hdr) + */ + +void lro_receive_frags(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, void *priv, __wsum sum); + +void lro_vlan_hwaccel_receive_frags(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, + struct vlan_group *vgrp, + u16 vlan_tag, + void *priv, __wsum sum); + +/* + * Forward all aggregated SKBs held by lro_mgr to network stack + */ + +void lro_flush_all(struct net_lro_mgr *lro_mgr); + +void lro_flush_pkt(struct net_lro_mgr *lro_mgr, + struct iphdr *iph, struct tcphdr *tcph); + +#endif diff --git a/include/linux/init.h b/include/linux/init.h index 5b5285316339..f8d9d0b5cffc 100644 --- a/include/linux/init.h +++ b/include/linux/init.h @@ -40,7 +40,7 @@ /* These are for everybody (although not all archs will actually discard it in modules) */ -#define __init __attribute__ ((__section__ (".init.text"))) +#define __init __attribute__ ((__section__ (".init.text"))) __cold #define __initdata __attribute__ ((__section__ (".init.data"))) #define __exitdata __attribute__ ((__section__(".exit.data"))) #define __exit_call __attribute_used__ __attribute__ ((__section__ (".exitcall.exit"))) @@ -57,11 +57,12 @@ * The markers follow same syntax rules as __init / __initdata. */ #define __init_refok noinline __attribute__ ((__section__ (".text.init.refok"))) #define __initdata_refok __attribute__ ((__section__ (".data.init.refok"))) +#define __exit_refok noinline __attribute__ ((__section__ (".exit.text.refok"))) #ifdef MODULE -#define __exit __attribute__ ((__section__(".exit.text"))) +#define __exit __attribute__ ((__section__(".exit.text"))) __cold #else -#define __exit __attribute_used__ __attribute__ ((__section__(".exit.text"))) +#define __exit __attribute_used__ __attribute__ ((__section__(".exit.text"))) __cold #endif /* For assembly routines */ @@ -114,7 +115,7 @@ void prepare_namespace(void); * * This only exists for built-in code, not for modules. */ -#define pure_initcall(fn) __define_initcall("0",fn,1) +#define pure_initcall(fn) __define_initcall("0",fn,0) #define core_initcall(fn) __define_initcall("1",fn,1) #define core_initcall_sync(fn) __define_initcall("1s",fn,1s) diff --git a/include/linux/init_task.h b/include/linux/init_task.h index cab741c2d603..513bc3e489f0 100644 --- a/include/linux/init_task.h +++ b/include/linux/init_task.h @@ -9,6 +9,7 @@ #include <linux/ipc.h> #include <linux/pid_namespace.h> #include <linux/user_namespace.h> +#include <net/net_namespace.h> #define INIT_FDTABLE \ { \ @@ -78,6 +79,7 @@ extern struct nsproxy init_nsproxy; .nslock = __SPIN_LOCK_UNLOCKED(nsproxy.nslock), \ .uts_ns = &init_uts_ns, \ .mnt_ns = NULL, \ + INIT_NET_NS(net_ns) \ INIT_IPC_NS(ipc_ns) \ .user_ns = &init_user_ns, \ } @@ -86,7 +88,7 @@ extern struct nsproxy init_nsproxy; .count = ATOMIC_INIT(1), \ .action = { { { .sa_handler = NULL, } }, }, \ .siglock = __SPIN_LOCK_UNLOCKED(sighand.siglock), \ - .signalfd_list = LIST_HEAD_INIT(sighand.signalfd_list), \ + .signalfd_wqh = __WAIT_QUEUE_HEAD_INITIALIZER(sighand.signalfd_wqh), \ } extern struct group_info init_groups; diff --git a/include/linux/input.h b/include/linux/input.h index d09e5e8be325..125e925320fd 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -360,9 +360,16 @@ struct input_absinfo { #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 +#define KEY_UWB 239 #define KEY_UNKNOWN 240 +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */ +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 @@ -552,6 +559,8 @@ struct input_absinfo { #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 5323f6275854..5523f19d88d2 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -11,8 +11,6 @@ #include <linux/hardirq.h> #include <linux/sched.h> #include <linux/irqflags.h> -#include <linux/bottom_half.h> -#include <linux/device.h> #include <asm/atomic.h> #include <asm/ptrace.h> #include <asm/system.h> @@ -97,6 +95,8 @@ extern int __must_check request_irq(unsigned int, irq_handler_t handler, unsigned long, const char *, void *); extern void free_irq(unsigned int, void *); +struct device; + extern int __must_check devm_request_irq(struct device *dev, unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *devname, void *dev_id); @@ -120,11 +120,11 @@ extern void devm_free_irq(struct device *dev, unsigned int irq, void *dev_id); # define local_irq_enable_in_hardirq() local_irq_enable() #endif -#ifdef CONFIG_GENERIC_HARDIRQS extern void disable_irq_nosync(unsigned int irq); extern void disable_irq(unsigned int irq); extern void enable_irq(unsigned int irq); +#ifdef CONFIG_GENERIC_HARDIRQS /* * Special lockdep variants of irq disabling/enabling. * These should be used for locking constructs that diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h index 2eaa142cd061..baf29387cab4 100644 --- a/include/linux/ioprio.h +++ b/include/linux/ioprio.h @@ -53,6 +53,14 @@ static inline int task_ioprio(struct task_struct *task) return IOPRIO_NORM; } +static inline int task_ioprio_class(struct task_struct *task) +{ + if (ioprio_valid(task->ioprio)) + return IOPRIO_PRIO_CLASS(task->ioprio); + + return IOPRIO_CLASS_BE; +} + static inline int task_nice_ioprio(struct task_struct *task) { return (task_nice(task) + 20) / 5; diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 97983dc9df13..5d35a4cc3bff 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -96,27 +96,6 @@ struct ipv6_destopt_hao { struct in6_addr addr; } __attribute__ ((__packed__)); -struct ipv6_auth_hdr { - __u8 nexthdr; - __u8 hdrlen; /* This one is measured in 32 bit units! */ - __be16 reserved; - __be32 spi; - __be32 seq_no; /* Sequence number */ - __u8 auth_data[0]; /* Length variable but >=4. Mind the 64 bit alignment! */ -}; - -struct ipv6_esp_hdr { - __be32 spi; - __be32 seq_no; /* Sequence number */ - __u8 enc_data[0]; /* Length variable but >=8. Mind the 64 bit alignment! */ -}; - -struct ipv6_comp_hdr { - __u8 nexthdr; - __u8 flags; - __be16 cpi; -}; - /* * IPv6 fixed header * @@ -219,7 +198,6 @@ enum { #include <linux/tcp.h> #include <linux/udp.h> -#include <net/if_inet6.h> /* struct ipv6_mc_socklist */ #include <net/inet_sock.h> static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb) @@ -273,6 +251,10 @@ struct tcp6_request_sock { struct inet6_request_sock tcp6rsk_inet6; }; +struct ipv6_mc_socklist; +struct ipv6_ac_socklist; +struct ipv6_fl_socklist; + /** * struct ipv6_pinfo - ipv6 private area * diff --git a/include/linux/irda.h b/include/linux/irda.h index 8e3735714c1c..28f88ecba344 100644 --- a/include/linux/irda.h +++ b/include/linux/irda.h @@ -77,6 +77,7 @@ typedef enum { IRDA_ACT200L_DONGLE = 10, IRDA_MA600_DONGLE = 11, IRDA_TOIM3232_DONGLE = 12, + IRDA_EP7211_DONGLE = 13, } IRDA_DONGLE; /* Protocol types to be used for SOCK_DGRAM */ diff --git a/include/linux/irq.h b/include/linux/irq.h index 44657197fcb0..efc88538b2ba 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -140,6 +140,7 @@ struct irq_chip { * @wake_depth: enable depth, for multiple set_irq_wake() callers * @irq_count: stats field to detect stalled irqs * @irqs_unhandled: stats field for spurious unhandled interrupts + * @last_unhandled: aging timer for unhandled count * @lock: locking for SMP * @affinity: IRQ affinity on SMP * @cpu: cpu index useful for balancing diff --git a/include/linux/isa.h b/include/linux/isa.h index 1b855335cb11..b0270e3814c8 100644 --- a/include/linux/isa.h +++ b/include/linux/isa.h @@ -22,7 +22,18 @@ struct isa_driver { #define to_isa_driver(x) container_of((x), struct isa_driver, driver) +#ifdef CONFIG_ISA int isa_register_driver(struct isa_driver *, unsigned int); void isa_unregister_driver(struct isa_driver *); +#else +static inline int isa_register_driver(struct isa_driver *d, unsigned int i) +{ + return 0; +} + +static inline void isa_unregister_driver(struct isa_driver *d) +{ +} +#endif #endif /* __LINUX_ISA_H */ diff --git a/include/linux/isdn.h b/include/linux/isdn.h index 3c7875b7ab5b..ad09506554a3 100644 --- a/include/linux/isdn.h +++ b/include/linux/isdn.h @@ -353,13 +353,6 @@ typedef struct isdn_net_local_s { /* a particular channel (including */ /* the frame_cnt */ - int (*org_hhc)( - struct neighbour *neigh, - struct hh_cache *hh); - /* Ptr to orig. header_cache_update */ - void (*org_hcu)(struct hh_cache *, - struct net_device *, - unsigned char *); int pppbind; /* ippp device for bindings */ int dialtimeout; /* How long shall we try on dialing? (jiffies) */ int dialwait; /* How long shall we wait after failed attempt? (jiffies) */ @@ -389,7 +382,7 @@ typedef struct isdn_net_dev_s { online */ spinlock_t queue_lock; /* lock to protect queue */ void *next; /* Pointer to next isdn-interface */ - struct net_device dev; /* interface to upper levels */ + struct net_device *dev; /* interface to upper levels */ #ifdef CONFIG_ISDN_PPP ippp_bundle * pb; /* pointer to the common bundle structure * with the per-bundle data */ diff --git a/include/media/ivtv.h b/include/linux/ivtv.h index 412b48ea8eda..794b8daa9378 100644 --- a/include/media/ivtv.h +++ b/include/linux/ivtv.h @@ -18,8 +18,15 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _LINUX_IVTV_H -#define _LINUX_IVTV_H +#ifndef __LINUX_IVTV_H__ +#define __LINUX_IVTV_H__ + +#ifdef __KERNEL__ +#include <linux/compiler.h> /* need __user */ +#else +#define __user +#endif +#include <linux/types.h> /* ivtv knows several distinct output modes: MPEG streaming, YUV streaming, YUV updates through user DMA and the passthrough diff --git a/include/linux/ivtvfb.h b/include/linux/ivtvfb.h new file mode 100644 index 000000000000..e980ba62ddcc --- /dev/null +++ b/include/linux/ivtvfb.h @@ -0,0 +1,42 @@ +/* + On Screen Display cx23415 Framebuffer driver + + Copyright (C) 2006, 2007 Ian Armstrong <ian@iarmst.demon.co.uk> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_IVTVFB_H__ +#define __LINUX_IVTVFB_H__ + +#ifdef __KERNEL__ +#include <linux/compiler.h> /* need __user */ +#else +#define __user +#endif +#include <linux/types.h> + +/* Framebuffer external API */ + +struct ivtvfb_dma_frame { + void __user *source; + unsigned long dest_offset; + int count; +}; + +#define IVTVFB_IOC_DMA_FRAME _IOW('V', BASE_VIDIOC_PRIVATE+0, struct ivtvfb_dma_frame) +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) + +#endif diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h index 0e0fedd2039a..260d6d76c5f3 100644 --- a/include/linux/jbd2.h +++ b/include/linux/jbd2.h @@ -50,14 +50,14 @@ */ #define JBD_DEFAULT_MAX_COMMIT_AGE 5 -#ifdef CONFIG_JBD_DEBUG +#ifdef CONFIG_JBD2_DEBUG /* * Define JBD_EXPENSIVE_CHECKING to enable more expensive internal * consistency checks. By default we don't do this unless - * CONFIG_JBD_DEBUG is on. + * CONFIG_JBD2_DEBUG is on. */ #define JBD_EXPENSIVE_CHECKING -extern int jbd2_journal_enable_debug; +extern u8 jbd2_journal_enable_debug; #define jbd_debug(n, f, a...) \ do { \ diff --git a/include/linux/jiffies.h b/include/linux/jiffies.h index c080f61fb024..d7a5e034c3a2 100644 --- a/include/linux/jiffies.h +++ b/include/linux/jiffies.h @@ -36,8 +36,6 @@ /* LATCH is used in the interval timer and ftape setup. */ #define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */ -#define LATCH_HPET ((HPET_TICK_RATE + HZ/2) / HZ) - /* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, the we can * improve accuracy by shifting LSH bits, hence calculating: * (NOM << LSH) / DEN @@ -53,13 +51,9 @@ /* HZ is the requested value. ACTHZ is actual HZ ("<< 8" is for accuracy) */ #define ACTHZ (SH_DIV (CLOCK_TICK_RATE, LATCH, 8)) -#define ACTHZ_HPET (SH_DIV (HPET_TICK_RATE, LATCH_HPET, 8)) - /* TICK_NSEC is the time between ticks in nsec assuming real ACTHZ */ #define TICK_NSEC (SH_DIV (1000000UL * 1000, ACTHZ, 8)) -#define TICK_NSEC_HPET (SH_DIV(1000000UL * 1000, ACTHZ_HPET, 8)) - /* TICK_USEC is the time between ticks in usec assuming fake USER_HZ */ #define TICK_USEC ((1000000UL + USER_HZ/2) / USER_HZ) diff --git a/include/linux/kbd_kern.h b/include/linux/kbd_kern.h index 506ad20c18f8..8bdb16bfe5fb 100644 --- a/include/linux/kbd_kern.h +++ b/include/linux/kbd_kern.h @@ -161,4 +161,7 @@ static inline void con_schedule_flip(struct tty_struct *t) schedule_delayed_work(&t->buf.work, 0); } +/* mac_hid.c */ +extern int mac_hid_mouse_emulate_buttons(int, unsigned int, int); + #endif diff --git a/include/linux/kdebug.h b/include/linux/kdebug.h index 5db38d6d8b92..ed815090b3bc 100644 --- a/include/linux/kdebug.h +++ b/include/linux/kdebug.h @@ -3,6 +3,8 @@ #include <asm/kdebug.h> +struct notifier_block; + struct die_args { struct pt_regs *regs; const char *str; diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 1eb9cde550c4..d9725a28a265 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -34,6 +34,7 @@ extern const char linux_proc_banner[]; #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) @@ -41,6 +42,20 @@ extern const char linux_proc_banner[]; #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#ifdef CONFIG_LBD +# include <asm/div64.h> +# define sector_div(a, b) do_div(a, b) +#else +# define sector_div(n, b)( \ +{ \ + int _res; \ + _res = (n) % (b); \ + (n) /= (b); \ + _res; \ +} \ +) +#endif + /** * upper_32_bits - return bits 32-63 of a number * @n: the number we're accessing @@ -106,7 +121,7 @@ extern int cond_resched(void); extern struct atomic_notifier_head panic_notifier_list; extern long (*panic_blink)(long time); NORET_TYPE void panic(const char * fmt, ...) - __attribute__ ((NORET_AND format (printf, 1, 2))); + __attribute__ ((NORET_AND format (printf, 1, 2))) __cold; extern void oops_enter(void); extern void oops_exit(void); extern int oops_may_print(void); @@ -155,14 +170,14 @@ extern void dump_thread(struct pt_regs *regs, struct user *dump); asmlinkage int vprintk(const char *fmt, va_list args) __attribute__ ((format (printf, 1, 0))); asmlinkage int printk(const char * fmt, ...) - __attribute__ ((format (printf, 1, 2))); + __attribute__ ((format (printf, 1, 2))) __cold; #else static inline int vprintk(const char *s, va_list args) __attribute__ ((format (printf, 1, 0))); static inline int vprintk(const char *s, va_list args) { return 0; } static inline int printk(const char *s, ...) __attribute__ ((format (printf, 1, 2))); -static inline int printk(const char *s, ...) { return 0; } +static inline int __cold printk(const char *s, ...) { return 0; } #endif unsigned long int_sqrt(unsigned long); @@ -212,7 +227,7 @@ extern enum system_states { #define TAINT_USER (1<<6) #define TAINT_DIE (1<<7) -extern void dump_stack(void); +extern void dump_stack(void) __cold; enum { DUMP_PREFIX_NONE, @@ -224,9 +239,9 @@ extern void hex_dump_to_buffer(const void *buf, size_t len, char *linebuf, size_t linebuflen, bool ascii); extern void print_hex_dump(const char *level, const char *prefix_str, int prefix_type, int rowsize, int groupsize, - void *buf, size_t len, bool ascii); + const void *buf, size_t len, bool ascii); extern void print_hex_dump_bytes(const char *prefix_str, int prefix_type, - void *buf, size_t len); + const void *buf, size_t len); #define hex_asc(x) "0123456789abcdef"[x] #ifdef DEBUG diff --git a/include/linux/keyboard.h b/include/linux/keyboard.h index f892b272f3ff..33b5c2e325b9 100644 --- a/include/linux/keyboard.h +++ b/include/linux/keyboard.h @@ -439,8 +439,10 @@ extern unsigned short plain_map[NR_KEYS]; #define K_BRL_DOT6 K(KT_BRL, 6) #define K_BRL_DOT7 K(KT_BRL, 7) #define K_BRL_DOT8 K(KT_BRL, 8) +#define K_BRL_DOT9 K(KT_BRL, 9) +#define K_BRL_DOT10 K(KT_BRL, 10) -#define NR_BRL 9 +#define NR_BRL 11 #define MAX_DIACR 256 #endif diff --git a/include/linux/kmod.h b/include/linux/kmod.h index 10f505c8431d..5dc13848891b 100644 --- a/include/linux/kmod.h +++ b/include/linux/kmod.h @@ -36,13 +36,57 @@ static inline int request_module(const char * name, ...) { return -ENOSYS; } #define try_then_request_module(x, mod...) ((x) ?: (request_module(mod), (x))) struct key; -extern int call_usermodehelper_keys(char *path, char *argv[], char *envp[], - struct key *session_keyring, int wait); +struct file; +struct subprocess_info; + +/* Allocate a subprocess_info structure */ +struct subprocess_info *call_usermodehelper_setup(char *path, + char **argv, char **envp); + +/* Set various pieces of state into the subprocess_info structure */ +void call_usermodehelper_setkeys(struct subprocess_info *info, + struct key *session_keyring); +int call_usermodehelper_stdinpipe(struct subprocess_info *sub_info, + struct file **filp); +void call_usermodehelper_setcleanup(struct subprocess_info *info, + void (*cleanup)(char **argv, char **envp)); + +enum umh_wait { + UMH_NO_WAIT = -1, /* don't wait at all */ + UMH_WAIT_EXEC = 0, /* wait for the exec, but not the process */ + UMH_WAIT_PROC = 1, /* wait for the process to complete */ +}; + +/* Actually execute the sub-process */ +int call_usermodehelper_exec(struct subprocess_info *info, enum umh_wait wait); + +/* Free the subprocess_info. This is only needed if you're not going + to call call_usermodehelper_exec */ +void call_usermodehelper_freeinfo(struct subprocess_info *info); static inline int -call_usermodehelper(char *path, char **argv, char **envp, int wait) +call_usermodehelper(char *path, char **argv, char **envp, enum umh_wait wait) { - return call_usermodehelper_keys(path, argv, envp, NULL, wait); + struct subprocess_info *info; + + info = call_usermodehelper_setup(path, argv, envp); + if (info == NULL) + return -ENOMEM; + return call_usermodehelper_exec(info, wait); +} + +static inline int +call_usermodehelper_keys(char *path, char **argv, char **envp, + struct key *session_keyring, enum umh_wait wait) +{ + struct subprocess_info *info; + + info = call_usermodehelper_setup(path, argv, envp); + if (info == NULL) + return -ENOMEM; + + call_usermodehelper_setkeys(info, session_keyring); + return call_usermodehelper_exec(info, wait); } extern void usermodehelper_init(void); diff --git a/include/linux/kobject.h b/include/linux/kobject.h index 06cbf41d32d2..4a0d27f475d7 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -1,8 +1,10 @@ /* * kobject.h - generic kernel object infrastructure. * - * Copyright (c) 2002-2003 Patrick Mochel - * Copyright (c) 2002-2003 Open Source Development Labs + * Copyright (c) 2002-2003 Patrick Mochel + * Copyright (c) 2002-2003 Open Source Development Labs + * Copyright (c) 2006-2007 Greg Kroah-Hartman <greg@kroah.com> + * Copyright (c) 2006-2007 Novell Inc. * * This file is released under the GPLv2. * @@ -29,6 +31,8 @@ #define KOBJ_NAME_LEN 20 #define UEVENT_HELPER_PATH_LEN 256 +#define UEVENT_NUM_ENVP 32 /* number of env pointers */ +#define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ /* path to the userspace helper executed on an event */ extern char uevent_helper[]; @@ -36,27 +40,34 @@ extern char uevent_helper[]; /* counter to tag the uevent, read only except for the kobject core */ extern u64 uevent_seqnum; -/* the actions here must match the proper string in lib/kobject_uevent.c */ -typedef int __bitwise kobject_action_t; +/* + * The actions here must match the index to the string array + * in lib/kobject_uevent.c + * + * Do not add new actions here without checking with the driver-core + * maintainers. Action strings are not meant to express subsystem + * or device specific properties. In most cases you want to send a + * kobject_uevent_env(kobj, KOBJ_CHANGE, env) with additional event + * specific variables added to the event environment. + */ enum kobject_action { - KOBJ_ADD = (__force kobject_action_t) 0x01, /* exclusive to core */ - KOBJ_REMOVE = (__force kobject_action_t) 0x02, /* exclusive to core */ - KOBJ_CHANGE = (__force kobject_action_t) 0x03, /* device state change */ - KOBJ_OFFLINE = (__force kobject_action_t) 0x04, /* device offline */ - KOBJ_ONLINE = (__force kobject_action_t) 0x05, /* device online */ - KOBJ_MOVE = (__force kobject_action_t) 0x06, /* device move */ + KOBJ_ADD, + KOBJ_REMOVE, + KOBJ_CHANGE, + KOBJ_MOVE, + KOBJ_ONLINE, + KOBJ_OFFLINE, + KOBJ_MAX }; struct kobject { const char * k_name; - char name[KOBJ_NAME_LEN]; struct kref kref; struct list_head entry; struct kobject * parent; struct kset * kset; struct kobj_type * ktype; struct sysfs_dirent * sd; - wait_queue_head_t poll; }; extern int kobject_set_name(struct kobject *, const char *, ...) @@ -71,14 +82,9 @@ extern void kobject_init(struct kobject *); extern void kobject_cleanup(struct kobject *); extern int __must_check kobject_add(struct kobject *); -extern int __must_check kobject_shadow_add(struct kobject *kobj, - struct sysfs_dirent *shadow_parent); extern void kobject_del(struct kobject *); extern int __must_check kobject_rename(struct kobject *, const char *new_name); -extern int __must_check kobject_shadow_rename(struct kobject *kobj, - struct sysfs_dirent *new_parent, - const char *new_name); extern int __must_check kobject_move(struct kobject *, struct kobject *); extern int __must_check kobject_register(struct kobject *); @@ -99,37 +105,44 @@ struct kobj_type { struct attribute ** default_attrs; }; +struct kobj_uevent_env { + char *envp[UEVENT_NUM_ENVP]; + int envp_idx; + char buf[UEVENT_BUFFER_SIZE]; + int buflen; +}; -/** - * kset - a set of kobjects of a specific type, belonging - * to a specific subsystem. - * - * All kobjects of a kset should be embedded in an identical - * type. This type may have a descriptor, which the kset points - * to. This allows there to exist sets of objects of the same - * type in different subsystems. - * - * A subsystem does not have to be a list of only one type - * of object; multiple ksets can belong to one subsystem. All - * ksets of a subsystem share the subsystem's lock. - * - * Each kset can support specific event variables; it can - * supress the event generation or add subsystem specific - * variables carried with the event. - */ struct kset_uevent_ops { int (*filter)(struct kset *kset, struct kobject *kobj); const char *(*name)(struct kset *kset, struct kobject *kobj); - int (*uevent)(struct kset *kset, struct kobject *kobj, char **envp, - int num_envp, char *buffer, int buffer_size); + int (*uevent)(struct kset *kset, struct kobject *kobj, + struct kobj_uevent_env *env); }; +/** + * struct kset - a set of kobjects of a specific type, belonging to a specific subsystem. + * + * A kset defines a group of kobjects. They can be individually + * different "types" but overall these kobjects all want to be grouped + * together and operated on in the same manner. ksets are used to + * define the attribute callbacks and other common events that happen to + * a kobject. + * + * @ktype: the struct kobj_type for this specific kset + * @list: the list of all kobjects for this kset + * @list_lock: a lock for iterating over the kobjects + * @kobj: the embedded kobject for this kset (recursion, isn't it fun...) + * @uevent_ops: the set of uevent operations for this kset. These are + * called whenever a kobject has something happen to it so that the kset + * can add new environment variables, or filter out the uevents if so + * desired. + */ struct kset { - struct kobj_type * ktype; + struct kobj_type *ktype; struct list_head list; spinlock_t list_lock; struct kobject kobj; - struct kset_uevent_ops * uevent_ops; + struct kset_uevent_ops *uevent_ops; }; @@ -164,22 +177,22 @@ static inline struct kobj_type * get_ktype(struct kobject * k) extern struct kobject * kset_find_obj(struct kset *, const char *); -/** +/* * Use this when initializing an embedded kset with no other * fields to initialize. */ -#define set_kset_name(str) .kset = { .kobj = { .name = str } } +#define set_kset_name(str) .kset = { .kobj = { .k_name = str } } #define decl_subsys(_name,_type,_uevent_ops) \ struct kset _name##_subsys = { \ - .kobj = { .name = __stringify(_name) }, \ + .kobj = { .k_name = __stringify(_name) }, \ .ktype = _type, \ .uevent_ops =_uevent_ops, \ } #define decl_subsys_name(_varname,_name,_type,_uevent_ops) \ struct kset _varname##_subsys = { \ - .kobj = { .name = __stringify(_name) }, \ + .kobj = { .k_name = __stringify(_name) }, \ .ktype = _type, \ .uevent_ops =_uevent_ops, \ } @@ -189,7 +202,7 @@ extern struct kset kernel_subsys; /* The global /sys/hypervisor/ subsystem */ extern struct kset hypervisor_subsys; -/** +/* * Helpers for setting the kset of registered objects. * Often, a registered object belongs to a kset embedded in a * subsystem. These do no magic, just make the resulting code @@ -207,49 +220,9 @@ extern struct kset hypervisor_subsys; #define kobj_set_kset_s(obj,subsys) \ (obj)->kobj.kset = &(subsys) -/** - * kset_set_kset_s(obj,subsys) - set kset for embedded kset. - * @obj: ptr to some object type. - * @subsys: a subsystem object (not a ptr). - * - * Can be used for any object type with an embedded ->kset. - * Sets the kset of @obj's embedded kobject (via its embedded - * kset) to @subsys.kset. This makes @obj a member of that - * kset. - */ - -#define kset_set_kset_s(obj,subsys) \ - (obj)->kset.kobj.kset = &(subsys) - -/** - * subsys_set_kset(obj,subsys) - set kset for subsystem - * @obj: ptr to some object type. - * @subsys: a subsystem object (not a ptr). - * - * Can be used for any object type with an embedded ->subsys. - * Sets the kset of @obj's kobject to @subsys.kset. This makes - * the object a member of that kset. - */ - -#define subsys_set_kset(obj,_subsys) \ - (obj)->subsys.kobj.kset = &(_subsys) - -extern void subsystem_init(struct kset *); extern int __must_check subsystem_register(struct kset *); extern void subsystem_unregister(struct kset *); -static inline struct kset *subsys_get(struct kset *s) -{ - if (s) - return kset_get(s); - return NULL; -} - -static inline void subsys_put(struct kset *s) -{ - kset_put(s); -} - struct subsys_attribute { struct attribute attr; ssize_t (*show)(struct kset *, char *); @@ -264,10 +237,11 @@ int kobject_uevent(struct kobject *kobj, enum kobject_action action); int kobject_uevent_env(struct kobject *kobj, enum kobject_action action, char *envp[]); -int add_uevent_var(char **envp, int num_envp, int *cur_index, - char *buffer, int buffer_size, int *cur_len, - const char *format, ...) - __attribute__((format (printf, 7, 8))); +int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...) + __attribute__((format (printf, 2, 3))); + +int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type); #else static inline int kobject_uevent(struct kobject *kobj, enum kobject_action action) { return 0; } @@ -276,10 +250,12 @@ static inline int kobject_uevent_env(struct kobject *kobj, char *envp[]) { return 0; } -static inline int add_uevent_var(char **envp, int num_envp, int *cur_index, - char *buffer, int buffer_size, int *cur_len, - const char *format, ...) +static inline int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...) { return 0; } + +static inline int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type) +{ return -EINVAL; } #endif #endif /* __KERNEL__ */ diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index 23adf6075ae4..51464d12a4e5 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -116,9 +116,12 @@ struct kprobe { */ struct jprobe { struct kprobe kp; - kprobe_opcode_t *entry; /* probe handling code to jump to */ + void *entry; /* probe handling code to jump to */ }; +/* For backward compatibility with old code using JPROBE_ENTRY() */ +#define JPROBE_ENTRY(handler) (handler) + DECLARE_PER_CPU(struct kprobe *, current_kprobe); DECLARE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); @@ -211,6 +214,7 @@ int longjmp_break_handler(struct kprobe *, struct pt_regs *); int register_jprobe(struct jprobe *p); void unregister_jprobe(struct jprobe *p); void jprobe_return(void); +unsigned long arch_deref_entry_point(void *); int register_kretprobe(struct kretprobe *rp); void unregister_kretprobe(struct kretprobe *rp); diff --git a/include/linux/ktime.h b/include/linux/ktime.h index dae7143644fe..a6ddec141f96 100644 --- a/include/linux/ktime.h +++ b/include/linux/ktime.h @@ -102,6 +102,13 @@ static inline ktime_t ktime_set(const long secs, const unsigned long nsecs) #define ktime_add_ns(kt, nsval) \ ({ (ktime_t){ .tv64 = (kt).tv64 + (nsval) }; }) +/* + * Subtract a scalar nanosecod from a ktime_t variable + * res = kt - nsval: + */ +#define ktime_sub_ns(kt, nsval) \ + ({ (ktime_t){ .tv64 = (kt).tv64 - (nsval) }; }) + /* convert a timespec to ktime_t format: */ static inline ktime_t timespec_to_ktime(struct timespec ts) { @@ -200,6 +207,15 @@ static inline ktime_t ktime_add(const ktime_t add1, const ktime_t add2) extern ktime_t ktime_add_ns(const ktime_t kt, u64 nsec); /** + * ktime_sub_ns - Subtract a scalar nanoseconds value from a ktime_t variable + * @kt: minuend + * @nsec: the scalar nsec value to subtract + * + * Returns the subtraction of @nsec from @kt in ktime_t format + */ +extern ktime_t ktime_sub_ns(const ktime_t kt, u64 nsec); + +/** * timespec_to_ktime - convert a timespec to ktime_t format * @ts: the timespec variable to convert * @@ -289,6 +305,11 @@ static inline ktime_t ktime_add_us(const ktime_t kt, const u64 usec) return ktime_add_ns(kt, usec * 1000); } +static inline ktime_t ktime_sub_us(const ktime_t kt, const u64 usec) +{ + return ktime_sub_ns(kt, usec * 1000); +} + /* * The resolution of the clocks. The resolution value is returned in * the clock_getres() system call to give application programmers an diff --git a/include/linux/lcd.h b/include/linux/lcd.h index 598793c0745b..1d379787f2e7 100644 --- a/include/linux/lcd.h +++ b/include/linux/lcd.h @@ -62,8 +62,8 @@ struct lcd_device { struct mutex update_lock; /* The framebuffer notifier block */ struct notifier_block fb_notif; - /* The class device structure */ - struct class_device class_dev; + + struct device dev; }; static inline void lcd_set_power(struct lcd_device *ld, int power) @@ -75,9 +75,15 @@ static inline void lcd_set_power(struct lcd_device *ld, int power) } extern struct lcd_device *lcd_device_register(const char *name, - void *devdata, struct lcd_ops *ops); + struct device *parent, void *devdata, struct lcd_ops *ops); extern void lcd_device_unregister(struct lcd_device *ld); -#define to_lcd_device(obj) container_of(obj, struct lcd_device, class_dev) +#define to_lcd_device(obj) container_of(obj, struct lcd_device, dev) + +static inline void * lcd_get_data(struct lcd_device *ld_dev) +{ + return dev_get_drvdata(&ld_dev->dev); +} + #endif diff --git a/include/linux/leds.h b/include/linux/leds.h index 494bed7c2fc1..dc1178f6184b 100644 --- a/include/linux/leds.h +++ b/include/linux/leds.h @@ -13,9 +13,9 @@ #define __LINUX_LEDS_H_INCLUDED #include <linux/list.h> +#include <linux/spinlock.h> struct device; -struct class_device; /* * LED Core */ @@ -37,7 +37,7 @@ struct led_classdev { void (*brightness_set)(struct led_classdev *led_cdev, enum led_brightness brightness); - struct class_device *class_dev; + struct device *dev; struct list_head node; /* LED Device list */ char *default_trigger; /* Trigger to use */ @@ -109,4 +109,18 @@ extern void ledtrig_ide_activity(void); #define ledtrig_ide_activity() do {} while(0) #endif +/* For the leds-gpio driver */ +struct gpio_led { + const char *name; + char *default_trigger; + unsigned gpio; + u8 active_low; +}; + +struct gpio_led_platform_data { + int num_leds; + struct gpio_led *leds; +}; + + #endif /* __LINUX_LEDS_H_INCLUDED */ diff --git a/include/linux/lguest.h b/include/linux/lguest.h new file mode 100644 index 000000000000..157ad64aa7ce --- /dev/null +++ b/include/linux/lguest.h @@ -0,0 +1,116 @@ +/* Things the lguest guest needs to know. Note: like all lguest interfaces, + * this is subject to wild and random change between versions. */ +#ifndef _ASM_LGUEST_H +#define _ASM_LGUEST_H + +#ifndef __ASSEMBLY__ +#include <asm/irq.h> + +#define LHCALL_FLUSH_ASYNC 0 +#define LHCALL_LGUEST_INIT 1 +#define LHCALL_CRASH 2 +#define LHCALL_LOAD_GDT 3 +#define LHCALL_NEW_PGTABLE 4 +#define LHCALL_FLUSH_TLB 5 +#define LHCALL_LOAD_IDT_ENTRY 6 +#define LHCALL_SET_STACK 7 +#define LHCALL_TS 8 +#define LHCALL_SET_CLOCKEVENT 9 +#define LHCALL_HALT 10 +#define LHCALL_BIND_DMA 12 +#define LHCALL_SEND_DMA 13 +#define LHCALL_SET_PTE 14 +#define LHCALL_SET_PMD 15 +#define LHCALL_LOAD_TLS 16 + +#define LG_CLOCK_MIN_DELTA 100UL +#define LG_CLOCK_MAX_DELTA ULONG_MAX + +/*G:031 First, how does our Guest contact the Host to ask for privileged + * operations? There are two ways: the direct way is to make a "hypercall", + * to make requests of the Host Itself. + * + * Our hypercall mechanism uses the highest unused trap code (traps 32 and + * above are used by real hardware interrupts). Seventeen hypercalls are + * available: the hypercall number is put in the %eax register, and the + * arguments (when required) are placed in %edx, %ebx and %ecx. If a return + * value makes sense, it's returned in %eax. + * + * Grossly invalid calls result in Sudden Death at the hands of the vengeful + * Host, rather than returning failure. This reflects Winston Churchill's + * definition of a gentleman: "someone who is only rude intentionally". */ +#define LGUEST_TRAP_ENTRY 0x1F + +static inline unsigned long +hcall(unsigned long call, + unsigned long arg1, unsigned long arg2, unsigned long arg3) +{ + /* "int" is the Intel instruction to trigger a trap. */ + asm volatile("int $" __stringify(LGUEST_TRAP_ENTRY) + /* The call is in %eax (aka "a"), and can be replaced */ + : "=a"(call) + /* The other arguments are in %eax, %edx, %ebx & %ecx */ + : "a"(call), "d"(arg1), "b"(arg2), "c"(arg3) + /* "memory" means this might write somewhere in memory. + * This isn't true for all calls, but it's safe to tell + * gcc that it might happen so it doesn't get clever. */ + : "memory"); + return call; +} +/*:*/ + +void async_hcall(unsigned long call, + unsigned long arg1, unsigned long arg2, unsigned long arg3); + +/* Can't use our min() macro here: needs to be a constant */ +#define LGUEST_IRQS (NR_IRQS < 32 ? NR_IRQS: 32) + +#define LHCALL_RING_SIZE 64 +struct hcall_ring +{ + u32 eax, edx, ebx, ecx; +}; + +/*G:032 The second method of communicating with the Host is to via "struct + * lguest_data". The Guest's very first hypercall is to tell the Host where + * this is, and then the Guest and Host both publish information in it. :*/ +struct lguest_data +{ + /* 512 == enabled (same as eflags in normal hardware). The Guest + * changes interrupts so often that a hypercall is too slow. */ + unsigned int irq_enabled; + /* Fine-grained interrupt disabling by the Guest */ + DECLARE_BITMAP(blocked_interrupts, LGUEST_IRQS); + + /* The Host writes the virtual address of the last page fault here, + * which saves the Guest a hypercall. CR2 is the native register where + * this address would normally be found. */ + unsigned long cr2; + + /* Wallclock time set by the Host. */ + struct timespec time; + + /* Async hypercall ring. Instead of directly making hypercalls, we can + * place them in here for processing the next time the Host wants. + * This batching can be quite efficient. */ + + /* 0xFF == done (set by Host), 0 == pending (set by Guest). */ + u8 hcall_status[LHCALL_RING_SIZE]; + /* The actual registers for the hypercalls. */ + struct hcall_ring hcalls[LHCALL_RING_SIZE]; + +/* Fields initialized by the Host at boot: */ + /* Memory not to try to access */ + unsigned long reserve_mem; + /* ID of this Guest (used by network driver to set ethernet address) */ + u16 guestid; + /* KHz for the TSC clock. */ + u32 tsc_khz; + +/* Fields initialized by the Guest at boot: */ + /* Instruction range to suppress interrupts even if enabled */ + unsigned long noirq_start, noirq_end; +}; +extern struct lguest_data lguest_data; +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_LGUEST_H */ diff --git a/include/linux/lguest_bus.h b/include/linux/lguest_bus.h new file mode 100644 index 000000000000..d27853ddc644 --- /dev/null +++ b/include/linux/lguest_bus.h @@ -0,0 +1,51 @@ +#ifndef _ASM_LGUEST_DEVICE_H +#define _ASM_LGUEST_DEVICE_H +/* Everything you need to know about lguest devices. */ +#include <linux/device.h> +#include <linux/lguest.h> +#include <linux/lguest_launcher.h> + +struct lguest_device { + /* Unique busid, and index into lguest_page->devices[] */ + unsigned int index; + + struct device dev; + + /* Driver can hang data off here. */ + void *private; +}; + +/*D:380 Since interrupt numbers are arbitrary, we use a convention: each device + * can use the interrupt number corresponding to its index. The +1 is because + * interrupt 0 is not usable (it's actually the timer interrupt). */ +static inline int lgdev_irq(const struct lguest_device *dev) +{ + return dev->index + 1; +} +/*:*/ + +/* dma args must not be vmalloced! */ +void lguest_send_dma(unsigned long key, struct lguest_dma *dma); +int lguest_bind_dma(unsigned long key, struct lguest_dma *dmas, + unsigned int num, u8 irq); +void lguest_unbind_dma(unsigned long key, struct lguest_dma *dmas); + +/* Map the virtual device space */ +void *lguest_map(unsigned long phys_addr, unsigned long pages); +void lguest_unmap(void *); + +struct lguest_driver { + const char *name; + struct module *owner; + u16 device_type; + int (*probe)(struct lguest_device *dev); + void (*remove)(struct lguest_device *dev); + + struct device_driver drv; +}; + +extern int register_lguest_driver(struct lguest_driver *drv); +extern void unregister_lguest_driver(struct lguest_driver *drv); + +extern struct lguest_device_desc *lguest_devices; /* Just past max_pfn */ +#endif /* _ASM_LGUEST_DEVICE_H */ diff --git a/include/linux/lguest_launcher.h b/include/linux/lguest_launcher.h new file mode 100644 index 000000000000..641670579446 --- /dev/null +++ b/include/linux/lguest_launcher.h @@ -0,0 +1,127 @@ +#ifndef _ASM_LGUEST_USER +#define _ASM_LGUEST_USER +/* Everything the "lguest" userspace program needs to know. */ +/* They can register up to 32 arrays of lguest_dma. */ +#define LGUEST_MAX_DMA 32 +/* At most we can dma 16 lguest_dma in one op. */ +#define LGUEST_MAX_DMA_SECTIONS 16 + +/* How many devices? Assume each one wants up to two dma arrays per device. */ +#define LGUEST_MAX_DEVICES (LGUEST_MAX_DMA/2) + +/*D:200 + * Lguest I/O + * + * The lguest I/O mechanism is the only way Guests can talk to devices. There + * are two hypercalls involved: SEND_DMA for output and BIND_DMA for input. In + * each case, "struct lguest_dma" describes the buffer: this contains 16 + * addr/len pairs, and if there are fewer buffer elements the len array is + * terminated with a 0. + * + * I/O is organized by keys: BIND_DMA attaches buffers to a particular key, and + * SEND_DMA transfers to buffers bound to particular key. By convention, keys + * correspond to a physical address within the device's page. This means that + * devices will never accidentally end up with the same keys, and allows the + * Host use The Futex Trick (as we'll see later in our journey). + * + * SEND_DMA simply indicates a key to send to, and the physical address of the + * "struct lguest_dma" to send. The Host will write the number of bytes + * transferred into the "struct lguest_dma"'s used_len member. + * + * BIND_DMA indicates a key to bind to, a pointer to an array of "struct + * lguest_dma"s ready for receiving, the size of that array, and an interrupt + * to trigger when data is received. The Host will only allow transfers into + * buffers with a used_len of zero: it then sets used_len to the number of + * bytes transferred and triggers the interrupt for the Guest to process the + * new input. */ +struct lguest_dma +{ + /* 0 if free to be used, filled by the Host. */ + u32 used_len; + unsigned long addr[LGUEST_MAX_DMA_SECTIONS]; + u16 len[LGUEST_MAX_DMA_SECTIONS]; +}; +/*:*/ + +/*D:460 This is the layout of a block device memory page. The Launcher sets up + * the num_sectors initially to tell the Guest the size of the disk. The Guest + * puts the type, sector and length of the request in the first three fields, + * then DMAs to the Host. The Host processes the request, sets up the result, + * then DMAs back to the Guest. */ +struct lguest_block_page +{ + /* 0 is a read, 1 is a write. */ + int type; + u32 sector; /* Offset in device = sector * 512. */ + u32 bytes; /* Length expected to be read/written in bytes */ + /* 0 = pending, 1 = done, 2 = done, error */ + int result; + u32 num_sectors; /* Disk length = num_sectors * 512 */ +}; + +/*D:520 The network device is basically a memory page where all the Guests on + * the network publish their MAC (ethernet) addresses: it's an array of "struct + * lguest_net": */ +struct lguest_net +{ + /* Simply the mac address (with multicast bit meaning promisc). */ + unsigned char mac[6]; +}; +/*:*/ + +/* Where the Host expects the Guest to SEND_DMA console output to. */ +#define LGUEST_CONSOLE_DMA_KEY 0 + +/*D:010 + * Drivers + * + * The Guest needs devices to do anything useful. Since we don't let it touch + * real devices (think of the damage it could do!) we provide virtual devices. + * We could emulate a PCI bus with various devices on it, but that is a fairly + * complex burden for the Host and suboptimal for the Guest, so we have our own + * "lguest" bus and simple drivers. + * + * Devices are described by an array of LGUEST_MAX_DEVICES of these structs, + * placed by the Launcher just above the top of physical memory: + */ +struct lguest_device_desc { + /* The device type: console, network, disk etc. */ + u16 type; +#define LGUEST_DEVICE_T_CONSOLE 1 +#define LGUEST_DEVICE_T_NET 2 +#define LGUEST_DEVICE_T_BLOCK 3 + + /* The specific features of this device: these depends on device type + * except for LGUEST_DEVICE_F_RANDOMNESS. */ + u16 features; +#define LGUEST_NET_F_NOCSUM 0x4000 /* Don't bother checksumming */ +#define LGUEST_DEVICE_F_RANDOMNESS 0x8000 /* IRQ is fairly random */ + + /* This is how the Guest reports status of the device: the Host can set + * LGUEST_DEVICE_S_REMOVED to indicate removal, but the rest are only + * ever manipulated by the Guest, and only ever set. */ + u16 status; +/* 256 and above are device specific. */ +#define LGUEST_DEVICE_S_ACKNOWLEDGE 1 /* We have seen device. */ +#define LGUEST_DEVICE_S_DRIVER 2 /* We have found a driver */ +#define LGUEST_DEVICE_S_DRIVER_OK 4 /* Driver says OK! */ +#define LGUEST_DEVICE_S_REMOVED 8 /* Device has gone away. */ +#define LGUEST_DEVICE_S_REMOVED_ACK 16 /* Driver has been told. */ +#define LGUEST_DEVICE_S_FAILED 128 /* Something actually failed */ + + /* Each device exists somewhere in Guest physical memory, over some + * number of pages. */ + u16 num_pages; + u32 pfn; +}; +/*:*/ + +/* Write command first word is a request. */ +enum lguest_req +{ + LHREQ_INITIALIZE, /* + pfnlimit, pgdir, start, pageoffset */ + LHREQ_GETDMA, /* + addr (returns &lguest_dma, irq in ->used_len) */ + LHREQ_IRQ, /* + irq */ + LHREQ_BREAK, /* + on/off flag (on blocks until someone does off) */ +}; +#endif /* _ASM_LGUEST_USER */ diff --git a/include/linux/libata.h b/include/linux/libata.h index 47cd2a1c5544..229a9ff9f924 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -28,7 +28,6 @@ #include <linux/delay.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/dma-mapping.h> #include <asm/scatterlist.h> #include <linux/io.h> @@ -107,12 +106,6 @@ static inline u32 ata_msg_init(int dval, int default_msg_enable_bits) /* defines only for the constants which don't work well as enums */ #define ATA_TAG_POISON 0xfafbfcfdU -/* move to PCI layer? */ -static inline struct device *pci_dev_to_dev(struct pci_dev *pdev) -{ - return &pdev->dev; -} - enum { /* various global constants */ LIBATA_MAX_PRD = ATA_MAX_PRD / 2, @@ -139,11 +132,12 @@ enum { ATA_DFLAG_FLUSH_EXT = (1 << 4), /* do FLUSH_EXT instead of FLUSH */ ATA_DFLAG_ACPI_PENDING = (1 << 5), /* ACPI resume action pending */ ATA_DFLAG_ACPI_FAILED = (1 << 6), /* ACPI on devcfg has failed */ - ATA_DFLAG_CFG_MASK = (1 << 8) - 1, + ATA_DFLAG_AN = (1 << 7), /* AN configured */ + ATA_DFLAG_CFG_MASK = (1 << 12) - 1, - ATA_DFLAG_PIO = (1 << 8), /* device limited to PIO mode */ - ATA_DFLAG_NCQ_OFF = (1 << 9), /* device limited to non-NCQ mode */ - ATA_DFLAG_SPUNDOWN = (1 << 10), /* XXX: for spindown_compat */ + ATA_DFLAG_PIO = (1 << 12), /* device limited to PIO mode */ + ATA_DFLAG_NCQ_OFF = (1 << 13), /* device limited to non-NCQ mode */ + ATA_DFLAG_SPUNDOWN = (1 << 14), /* XXX: for spindown_compat */ ATA_DFLAG_INIT_MASK = (1 << 16) - 1, ATA_DFLAG_DETACH = (1 << 16), @@ -154,7 +148,22 @@ enum { ATA_DEV_ATA_UNSUP = 2, /* ATA device (unsupported) */ ATA_DEV_ATAPI = 3, /* ATAPI device */ ATA_DEV_ATAPI_UNSUP = 4, /* ATAPI device (unsupported) */ - ATA_DEV_NONE = 5, /* no device */ + ATA_DEV_PMP = 5, /* SATA port multiplier */ + ATA_DEV_PMP_UNSUP = 6, /* SATA port multiplier (unsupported) */ + ATA_DEV_SEMB = 7, /* SEMB */ + ATA_DEV_SEMB_UNSUP = 8, /* SEMB (unsupported) */ + ATA_DEV_NONE = 9, /* no device */ + + /* struct ata_link flags */ + ATA_LFLAG_HRST_TO_RESUME = (1 << 0), /* hardreset to resume link */ + ATA_LFLAG_SKIP_D2H_BSY = (1 << 1), /* can't wait for the first D2H + * Register FIS clearing BSY */ + ATA_LFLAG_NO_SRST = (1 << 2), /* avoid softreset */ + ATA_LFLAG_ASSUME_ATA = (1 << 3), /* assume ATA class */ + ATA_LFLAG_ASSUME_SEMB = (1 << 4), /* assume SEMB class */ + ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB, + ATA_LFLAG_NO_RETRY = (1 << 5), /* don't retry this link */ + ATA_LFLAG_DISABLED = (1 << 6), /* link is disabled */ /* struct ata_port flags */ ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ @@ -170,13 +179,12 @@ enum { ATA_FLAG_PIO_POLLING = (1 << 9), /* use polling PIO if LLD * doesn't handle PIO interrupts */ ATA_FLAG_NCQ = (1 << 10), /* host supports NCQ */ - ATA_FLAG_HRST_TO_RESUME = (1 << 11), /* hardreset to resume phy */ - ATA_FLAG_SKIP_D2H_BSY = (1 << 12), /* can't wait for the first D2H - * Register FIS clearing BSY */ ATA_FLAG_DEBUGMSG = (1 << 13), ATA_FLAG_IGN_SIMPLEX = (1 << 15), /* ignore SIMPLEX */ ATA_FLAG_NO_IORDY = (1 << 16), /* controller lacks iordy */ ATA_FLAG_ACPI_SATA = (1 << 17), /* need native SATA ACPI layout */ + ATA_FLAG_AN = (1 << 18), /* controller supports AN */ + ATA_FLAG_PMP = (1 << 19), /* controller supports PMP */ /* The following flag belongs to ap->pflags but is kept in * ap->flags because it's referenced in many LLDs and will be @@ -195,6 +203,7 @@ enum { ATA_PFLAG_UNLOADING = (1 << 5), /* module is unloading */ ATA_PFLAG_SCSI_HOTPLUG = (1 << 6), /* SCSI hotplug scheduled */ ATA_PFLAG_INITIALIZING = (1 << 7), /* being initialized, don't touch */ + ATA_PFLAG_RESETTING = (1 << 8), /* reset in progress */ ATA_PFLAG_SUSPENDED = (1 << 17), /* port is suspended (power) */ ATA_PFLAG_PM_PENDING = (1 << 18), /* PM operation pending */ @@ -207,6 +216,7 @@ enum { ATA_QCFLAG_DMAMAP = ATA_QCFLAG_SG | ATA_QCFLAG_SINGLE, ATA_QCFLAG_IO = (1 << 3), /* standard IO command */ ATA_QCFLAG_RESULT_TF = (1 << 4), /* result TF requested */ + ATA_QCFLAG_CLEAR_EXCL = (1 << 5), /* clear excl_link on completion */ ATA_QCFLAG_FAILED = (1 << 16), /* cmd failed and is owned by EH */ ATA_QCFLAG_SENSE_VALID = (1 << 17), /* sense data valid */ @@ -216,6 +226,8 @@ enum { ATA_HOST_SIMPLEX = (1 << 0), /* Host is simplex, one DMA channel per host only */ ATA_HOST_STARTED = (1 << 1), /* Host started */ + /* bits 24:31 of host->flags are reserved for LLD specific flags */ + /* various lengths of time */ ATA_TMOUT_BOOT = 30 * HZ, /* heuristic */ ATA_TMOUT_BOOT_QUICK = 7 * HZ, /* heuristic */ @@ -261,6 +273,10 @@ enum { /* ering size */ ATA_ERING_SIZE = 32, + /* return values for ->qc_defer */ + ATA_DEFER_LINK = 1, + ATA_DEFER_PORT = 2, + /* desc_len for ata_eh_info and context */ ATA_EH_DESC_LEN = 80, @@ -268,6 +284,7 @@ enum { ATA_EH_REVALIDATE = (1 << 0), ATA_EH_SOFTRESET = (1 << 1), ATA_EH_HARDRESET = (1 << 2), + ATA_EH_ENABLE_LINK = (1 << 3), ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET, ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE, @@ -287,12 +304,16 @@ enum { ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET, ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK, - /* max repeat if error condition is still set after ->error_handler */ - ATA_EH_MAX_REPEAT = 5, + /* max tries if error condition is still set after ->error_handler */ + ATA_EH_MAX_TRIES = 5, /* how hard are we gonna try to probe/recover devices */ ATA_PROBE_MAX_TRIES = 3, ATA_EH_DEV_TRIES = 3, + ATA_EH_PMP_TRIES = 5, + ATA_EH_PMP_LINK_TRIES = 3, + + SATA_PMP_SCR_TIMEOUT = 250, /* Horkage types. May be set by libata or controller on drives (some horkage may be drive/controller pair dependant */ @@ -301,6 +322,15 @@ enum { ATA_HORKAGE_NODMA = (1 << 1), /* DMA problems */ ATA_HORKAGE_NONCQ = (1 << 2), /* Don't use NCQ */ ATA_HORKAGE_MAX_SEC_128 = (1 << 3), /* Limit max sects to 128 */ + ATA_HORKAGE_BROKEN_HPA = (1 << 4), /* Broken HPA */ + ATA_HORKAGE_SKIP_PM = (1 << 5), /* Skip PM operations */ + ATA_HORKAGE_HPA_SIZE = (1 << 6), /* native size off by one */ + + /* DMA mask for user DMA control: User visible values; DO NOT + renumber */ + ATA_DMA_MASK_ATA = (1 << 0), /* DMA on ATA Disk */ + ATA_DMA_MASK_ATAPI = (1 << 1), /* DMA on ATAPI */ + ATA_DMA_MASK_CFA = (1 << 2), /* DMA on CF Card */ }; enum hsm_task_states { @@ -323,20 +353,22 @@ enum ata_completion_errors { AC_ERR_INVALID = (1 << 7), /* invalid argument */ AC_ERR_OTHER = (1 << 8), /* unknown */ AC_ERR_NODEV_HINT = (1 << 9), /* polling device detection hint */ + AC_ERR_NCQ = (1 << 10), /* marker for offending NCQ qc */ }; /* forward declarations */ struct scsi_device; struct ata_port_operations; struct ata_port; +struct ata_link; struct ata_queued_cmd; /* typedefs */ typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc); -typedef int (*ata_prereset_fn_t)(struct ata_port *ap, unsigned long deadline); -typedef int (*ata_reset_fn_t)(struct ata_port *ap, unsigned int *classes, +typedef int (*ata_prereset_fn_t)(struct ata_link *link, unsigned long deadline); +typedef int (*ata_reset_fn_t)(struct ata_link *link, unsigned int *classes, unsigned long deadline); -typedef void (*ata_postreset_fn_t)(struct ata_port *ap, unsigned int *classes); +typedef void (*ata_postreset_fn_t)(struct ata_link *link, unsigned int *classes); struct ata_ioports { void __iomem *cmd_addr; @@ -359,8 +391,6 @@ struct ata_ioports { struct ata_host { spinlock_t lock; struct device *dev; - unsigned long irq; - unsigned long irq2; void __iomem * const *iomap; unsigned int n_ports; void *private_data; @@ -411,6 +441,7 @@ struct ata_queued_cmd { ata_qc_cb_t complete_fn; void *private_data; + void *lldd_task; }; struct ata_port_stats { @@ -431,7 +462,7 @@ struct ata_ering { }; struct ata_device { - struct ata_port *ap; + struct ata_link *link; unsigned int devno; /* 0 or 1 */ unsigned long flags; /* ATA_DFLAG_xxx */ unsigned int horkage; /* List of broken features */ @@ -442,7 +473,12 @@ struct ata_device { /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */ u64 n_sectors; /* size of device, if ATA */ unsigned int class; /* ATA_DEV_xxx */ - u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */ + + union { + u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */ + u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */ + }; + u8 pio_mode; u8 dma_mode; u8 xfer_mode; @@ -505,6 +541,27 @@ struct ata_acpi_gtm { u32 flags; } __packed; +struct ata_link { + struct ata_port *ap; + int pmp; /* port multiplier port # */ + + unsigned int active_tag; /* active tag on this link */ + u32 sactive; /* active NCQ commands */ + + unsigned int flags; /* ATA_LFLAG_xxx */ + + unsigned int hw_sata_spd_limit; + unsigned int sata_spd_limit; + unsigned int sata_spd; /* current SATA PHY speed */ + + /* record runtime error info, protected by host_set lock */ + struct ata_eh_info eh_info; + /* EH context */ + struct ata_eh_context eh_context; + + struct ata_device device[ATA_MAX_DEVICES]; +}; + struct ata_port { struct Scsi_Host *scsi_host; /* our co-allocated scsi host */ const struct ata_port_operations *ops; @@ -528,22 +585,17 @@ struct ata_port { unsigned int mwdma_mask; unsigned int udma_mask; unsigned int cbl; /* cable type; ATA_CBL_xxx */ - unsigned int hw_sata_spd_limit; - unsigned int sata_spd_limit; /* SATA PHY speed limit */ - - /* record runtime error info, protected by host lock */ - struct ata_eh_info eh_info; - /* EH context owned by EH */ - struct ata_eh_context eh_context; - - struct ata_device device[ATA_MAX_DEVICES]; struct ata_queued_cmd qcmd[ATA_MAX_QUEUE]; unsigned long qc_allocated; unsigned int qc_active; + int nr_active_links; /* #links with active qcs */ + + struct ata_link link; /* host default link */ - unsigned int active_tag; - u32 sactive; + int nr_pmp_links; /* nr of available PMP links */ + struct ata_link *pmp_link; /* array of PMP links */ + struct ata_link *excl_link; /* for PMP qc exclusion */ struct ata_port_stats stats; struct ata_host *host; @@ -559,10 +611,14 @@ struct ata_port { u32 msg_enable; struct list_head eh_done_q; wait_queue_head_t eh_wait_q; + int eh_tries; pm_message_t pm_mesg; int *pm_result; + struct timer_list fastdrain_timer; + unsigned long fastdrain_cnt; + void *private_data; #ifdef CONFIG_ATA_ACPI @@ -573,8 +629,6 @@ struct ata_port { }; struct ata_port_operations { - void (*port_disable) (struct ata_port *); - void (*dev_config) (struct ata_device *); void (*set_piomode) (struct ata_port *, struct ata_device *); @@ -590,7 +644,7 @@ struct ata_port_operations { void (*dev_select)(struct ata_port *ap, unsigned int device); void (*phy_reset) (struct ata_port *ap); /* obsolete */ - int (*set_mode) (struct ata_port *ap, struct ata_device **r_failed_dev); + int (*set_mode) (struct ata_link *link, struct ata_device **r_failed_dev); int (*cable_detect) (struct ata_port *ap); @@ -601,9 +655,14 @@ struct ata_port_operations { void (*data_xfer) (struct ata_device *, unsigned char *, unsigned int, int); + int (*qc_defer) (struct ata_queued_cmd *qc); void (*qc_prep) (struct ata_queued_cmd *qc); unsigned int (*qc_issue) (struct ata_queued_cmd *qc); + /* port multiplier */ + void (*pmp_attach) (struct ata_port *ap); + void (*pmp_detach) (struct ata_port *ap); + /* Error handlers. ->error_handler overrides ->eng_timeout and * indicates that new-style EH is in place. */ @@ -617,11 +676,9 @@ struct ata_port_operations { irq_handler_t irq_handler; void (*irq_clear) (struct ata_port *); u8 (*irq_on) (struct ata_port *); - u8 (*irq_ack) (struct ata_port *ap, unsigned int chk_drq); - u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg); - void (*scr_write) (struct ata_port *ap, unsigned int sc_reg, - u32 val); + int (*scr_read) (struct ata_port *ap, unsigned int sc_reg, u32 *val); + int (*scr_write) (struct ata_port *ap, unsigned int sc_reg, u32 val); int (*port_suspend) (struct ata_port *ap, pm_message_t mesg); int (*port_resume) (struct ata_port *ap); @@ -638,6 +695,7 @@ struct ata_port_operations { struct ata_port_info { struct scsi_host_template *sht; unsigned long flags; + unsigned long link_flags; unsigned long pio_mask; unsigned long mwdma_mask; unsigned long udma_mask; @@ -681,38 +739,27 @@ static inline int ata_port_is_dummy(struct ata_port *ap) return ap->ops == &ata_dummy_port_ops; } -extern void sata_print_link_status(struct ata_port *ap); +extern void sata_print_link_status(struct ata_link *link); extern void ata_port_probe(struct ata_port *); extern void __sata_phy_reset(struct ata_port *ap); extern void sata_phy_reset(struct ata_port *ap); extern void ata_bus_reset(struct ata_port *ap); -extern int sata_set_spd(struct ata_port *ap); -extern int sata_phy_debounce(struct ata_port *ap, const unsigned long *param, - unsigned long deadline); -extern int sata_phy_resume(struct ata_port *ap, const unsigned long *param, - unsigned long deadline); -extern int ata_std_prereset(struct ata_port *ap, unsigned long deadline); -extern int ata_std_softreset(struct ata_port *ap, unsigned int *classes, +extern int sata_set_spd(struct ata_link *link); +extern int sata_link_debounce(struct ata_link *link, + const unsigned long *params, unsigned long deadline); +extern int sata_link_resume(struct ata_link *link, const unsigned long *params, + unsigned long deadline); +extern int ata_std_prereset(struct ata_link *link, unsigned long deadline); +extern int ata_std_softreset(struct ata_link *link, unsigned int *classes, unsigned long deadline); -extern int sata_port_hardreset(struct ata_port *ap, const unsigned long *timing, - unsigned long deadline); -extern int sata_std_hardreset(struct ata_port *ap, unsigned int *class, +extern int sata_link_hardreset(struct ata_link *link, + const unsigned long *timing, unsigned long deadline); +extern int sata_std_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline); -extern void ata_std_postreset(struct ata_port *ap, unsigned int *classes); +extern void ata_std_postreset(struct ata_link *link, unsigned int *classes); extern void ata_port_disable(struct ata_port *); extern void ata_std_ports(struct ata_ioports *ioaddr); -#ifdef CONFIG_PCI -extern int ata_pci_init_one (struct pci_dev *pdev, - const struct ata_port_info * const * ppi); -extern void ata_pci_remove_one (struct pci_dev *pdev); -#ifdef CONFIG_PM -extern void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg); -extern int __must_check ata_pci_device_do_resume(struct pci_dev *pdev); -extern int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); -extern int ata_pci_device_resume(struct pci_dev *pdev); -#endif -extern int ata_pci_clear_simplex(struct pci_dev *pdev); -#endif /* CONFIG_PCI */ + extern struct ata_host *ata_host_alloc(struct device *dev, int max_ports); extern struct ata_host *ata_host_alloc_pinfo(struct device *dev, const struct ata_port_info * const * ppi, int n_ports); @@ -738,12 +785,12 @@ extern int ata_sas_slave_configure(struct scsi_device *, struct ata_port *); extern int ata_sas_queuecmd(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *), struct ata_port *ap); extern unsigned int ata_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc); -extern int sata_scr_valid(struct ata_port *ap); -extern int sata_scr_read(struct ata_port *ap, int reg, u32 *val); -extern int sata_scr_write(struct ata_port *ap, int reg, u32 val); -extern int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val); -extern int ata_port_online(struct ata_port *ap); -extern int ata_port_offline(struct ata_port *ap); +extern int sata_scr_valid(struct ata_link *link); +extern int sata_scr_read(struct ata_link *link, int reg, u32 *val); +extern int sata_scr_write(struct ata_link *link, int reg, u32 val); +extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val); +extern int ata_link_online(struct ata_link *link); +extern int ata_link_offline(struct ata_link *link); #ifdef CONFIG_PM extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg); extern void ata_host_resume(struct ata_host *host); @@ -757,14 +804,16 @@ extern void ata_port_queue_task(struct ata_port *ap, work_func_t fn, extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, unsigned long interval_msec, unsigned long timeout_msec); -extern unsigned int ata_dev_try_classify(struct ata_port *, unsigned int, u8 *); +extern unsigned int ata_dev_try_classify(struct ata_device *dev, int present, + u8 *r_err); /* * Default driver ops implementations */ extern void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); extern void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf); -extern void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp); +extern void ata_tf_to_fis(const struct ata_taskfile *tf, + u8 pmp, int is_cmd, u8 *fis); extern void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf); extern void ata_noop_dev_select (struct ata_port *ap, unsigned int device); extern void ata_std_dev_select (struct ata_port *ap, unsigned int device); @@ -778,6 +827,7 @@ extern void ata_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data); extern void ata_data_xfer_noirq(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data); +extern int ata_std_qc_defer(struct ata_queued_cmd *qc); extern void ata_dumb_qc_prep(struct ata_queued_cmd *qc); extern void ata_qc_prep(struct ata_queued_cmd *qc); extern void ata_noop_qc_prep(struct ata_queued_cmd *qc); @@ -821,11 +871,8 @@ extern void ata_scsi_slave_destroy(struct scsi_device *sdev); extern int ata_scsi_change_queue_depth(struct scsi_device *sdev, int queue_depth); extern struct ata_device *ata_dev_pair(struct ata_device *adev); -extern int ata_do_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev); +extern int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev); extern u8 ata_irq_on(struct ata_port *ap); -extern u8 ata_dummy_irq_on(struct ata_port *ap); -extern u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq); -extern u8 ata_dummy_irq_ack(struct ata_port *ap, unsigned int chk_drq); extern int ata_cable_40wire(struct ata_port *ap); extern int ata_cable_80wire(struct ata_port *ap); @@ -860,8 +907,29 @@ enum { ATA_TIMING_CYCLE | ATA_TIMING_UDMA, }; +/* libata-acpi.c */ +#ifdef CONFIG_ATA_ACPI +extern int ata_acpi_cbl_80wire(struct ata_port *ap); +int ata_acpi_stm(const struct ata_port *ap, struct ata_acpi_gtm *stm); +int ata_acpi_gtm(const struct ata_port *ap, struct ata_acpi_gtm *stm); +#else +static inline int ata_acpi_cbl_80wire(struct ata_port *ap) { return 0; } +#endif #ifdef CONFIG_PCI +struct pci_dev; + +extern int ata_pci_init_one (struct pci_dev *pdev, + const struct ata_port_info * const * ppi); +extern void ata_pci_remove_one (struct pci_dev *pdev); +#ifdef CONFIG_PM +extern void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg); +extern int __must_check ata_pci_device_do_resume(struct pci_dev *pdev); +extern int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); +extern int ata_pci_device_resume(struct pci_dev *pdev); +#endif +extern int ata_pci_clear_simplex(struct pci_dev *pdev); + struct pci_bits { unsigned int reg; /* PCI config register to read */ unsigned int width; /* 1 (8 bit), 2 (16 bit), 4 (32 bit) */ @@ -879,13 +947,29 @@ extern unsigned long ata_pci_default_filter(struct ata_device *, unsigned long); #endif /* CONFIG_PCI */ /* + * PMP + */ +extern int sata_pmp_qc_defer_cmd_switch(struct ata_queued_cmd *qc); +extern int sata_pmp_std_prereset(struct ata_link *link, unsigned long deadline); +extern int sata_pmp_std_hardreset(struct ata_link *link, unsigned int *class, + unsigned long deadline); +extern void sata_pmp_std_postreset(struct ata_link *link, unsigned int *class); +extern void sata_pmp_do_eh(struct ata_port *ap, + ata_prereset_fn_t prereset, ata_reset_fn_t softreset, + ata_reset_fn_t hardreset, ata_postreset_fn_t postreset, + ata_prereset_fn_t pmp_prereset, ata_reset_fn_t pmp_softreset, + ata_reset_fn_t pmp_hardreset, ata_postreset_fn_t pmp_postreset); + +/* * EH */ extern void ata_eng_timeout(struct ata_port *ap); extern void ata_port_schedule_eh(struct ata_port *ap); +extern int ata_link_abort(struct ata_link *link); extern int ata_port_abort(struct ata_port *ap); extern int ata_port_freeze(struct ata_port *ap); +extern int sata_async_notification(struct ata_port *ap); extern void ata_eh_freeze_port(struct ata_port *ap); extern void ata_eh_thaw_port(struct ata_port *ap); @@ -903,37 +987,53 @@ extern void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset, #define ata_port_printk(ap, lv, fmt, args...) \ printk(lv"ata%u: "fmt, (ap)->print_id , ##args) +#define ata_link_printk(link, lv, fmt, args...) do { \ + if ((link)->ap->nr_pmp_links) \ + printk(lv"ata%u.%02u: "fmt, (link)->ap->print_id, \ + (link)->pmp , ##args); \ + else \ + printk(lv"ata%u: "fmt, (link)->ap->print_id , ##args); \ + } while(0) + #define ata_dev_printk(dev, lv, fmt, args...) \ - printk(lv"ata%u.%02u: "fmt, (dev)->ap->print_id, (dev)->devno , ##args) + printk(lv"ata%u.%02u: "fmt, (dev)->link->ap->print_id, \ + (dev)->link->pmp + (dev)->devno , ##args) /* * ata_eh_info helpers */ -#define ata_ehi_push_desc(ehi, fmt, args...) do { \ - (ehi)->desc_len += scnprintf((ehi)->desc + (ehi)->desc_len, \ - ATA_EH_DESC_LEN - (ehi)->desc_len, \ - fmt , ##args); \ -} while (0) - -#define ata_ehi_clear_desc(ehi) do { \ - (ehi)->desc[0] = '\0'; \ - (ehi)->desc_len = 0; \ -} while (0) - -static inline void __ata_ehi_hotplugged(struct ata_eh_info *ehi) +extern void __ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...) + __attribute__ ((format (printf, 2, 3))); +extern void ata_ehi_push_desc(struct ata_eh_info *ehi, const char *fmt, ...) + __attribute__ ((format (printf, 2, 3))); +extern void ata_ehi_clear_desc(struct ata_eh_info *ehi); + +static inline void ata_ehi_schedule_probe(struct ata_eh_info *ehi) { - ehi->flags |= ATA_EHI_HOTPLUGGED | ATA_EHI_RESUME_LINK; + ehi->flags |= ATA_EHI_RESUME_LINK; ehi->action |= ATA_EH_SOFTRESET; ehi->probe_mask |= (1 << ATA_MAX_DEVICES) - 1; } static inline void ata_ehi_hotplugged(struct ata_eh_info *ehi) { - __ata_ehi_hotplugged(ehi); + ata_ehi_schedule_probe(ehi); + ehi->flags |= ATA_EHI_HOTPLUGGED; + ehi->action |= ATA_EH_ENABLE_LINK; ehi->err_mask |= AC_ERR_ATA_BUS; } /* + * port description helpers + */ +extern void ata_port_desc(struct ata_port *ap, const char *fmt, ...) + __attribute__ ((format (printf, 2, 3))); +#ifdef CONFIG_PCI +extern void ata_port_pbar_desc(struct ata_port *ap, int bar, ssize_t offset, + const char *name); +#endif + +/* * qc helpers */ static inline int @@ -988,12 +1088,14 @@ static inline unsigned int ata_tag_internal(unsigned int tag) */ static inline unsigned int ata_class_enabled(unsigned int class) { - return class == ATA_DEV_ATA || class == ATA_DEV_ATAPI; + return class == ATA_DEV_ATA || class == ATA_DEV_ATAPI || + class == ATA_DEV_PMP || class == ATA_DEV_SEMB; } static inline unsigned int ata_class_disabled(unsigned int class) { - return class == ATA_DEV_ATA_UNSUP || class == ATA_DEV_ATAPI_UNSUP; + return class == ATA_DEV_ATA_UNSUP || class == ATA_DEV_ATAPI_UNSUP || + class == ATA_DEV_PMP_UNSUP || class == ATA_DEV_SEMB_UNSUP; } static inline unsigned int ata_class_absent(unsigned int class) @@ -1017,15 +1119,62 @@ static inline unsigned int ata_dev_absent(const struct ata_device *dev) } /* - * port helpers + * link helpers */ -static inline int ata_port_max_devices(const struct ata_port *ap) +static inline int ata_is_host_link(const struct ata_link *link) +{ + return link == &link->ap->link; +} + +static inline int ata_link_max_devices(const struct ata_link *link) { - if (ap->flags & ATA_FLAG_SLAVE_POSS) + if (ata_is_host_link(link) && link->ap->flags & ATA_FLAG_SLAVE_POSS) return 2; return 1; } +static inline int ata_link_active(struct ata_link *link) +{ + return ata_tag_valid(link->active_tag) || link->sactive; +} + +static inline struct ata_link *ata_port_first_link(struct ata_port *ap) +{ + if (ap->nr_pmp_links) + return ap->pmp_link; + return &ap->link; +} + +static inline struct ata_link *ata_port_next_link(struct ata_link *link) +{ + struct ata_port *ap = link->ap; + + if (link == &ap->link) { + if (!ap->nr_pmp_links) + return NULL; + return ap->pmp_link; + } + + if (++link - ap->pmp_link < ap->nr_pmp_links) + return link; + return NULL; +} + +#define __ata_port_for_each_link(lk, ap) \ + for ((lk) = &(ap)->link; (lk); (lk) = ata_port_next_link(lk)) + +#define ata_port_for_each_link(link, ap) \ + for ((link) = ata_port_first_link(ap); (link); \ + (link) = ata_port_next_link(link)) + +#define ata_link_for_each_dev(dev, link) \ + for ((dev) = (link)->device; \ + (dev) < (link)->device + ata_link_max_devices(link) || ((dev) = NULL); \ + (dev)++) + +#define ata_link_for_each_dev_reverse(dev, link) \ + for ((dev) = (link)->device + ata_link_max_devices(link) - 1; \ + (dev) >= (link)->device || ((dev) = NULL); (dev)--) static inline u8 ata_chk_status(struct ata_port *ap) { @@ -1107,9 +1256,11 @@ static inline u8 ata_wait_idle(struct ata_port *ap) { u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); +#ifdef ATA_DEBUG if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ))) - DPRINTK("ATA: abnormal status 0x%X on port 0x%p\n", - status, ap->ioaddr.status_addr); + ata_port_printk(ap, KERN_DEBUG, "abnormal Status 0x%X\n", + status); +#endif return status; } @@ -1146,7 +1297,7 @@ static inline void ata_tf_init(struct ata_device *dev, struct ata_taskfile *tf) { memset(tf, 0, sizeof(*tf)); - tf->ctl = dev->ap->ctl; + tf->ctl = dev->link->ap->ctl; if (dev->devno == 0) tf->device = ATA_DEVICE_OBS; else diff --git a/include/linux/list.h b/include/linux/list.h index f29fc9c1a964..ad9dcb9e3375 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -525,6 +525,20 @@ static inline void list_splice_init_rcu(struct list_head *list, pos = list_entry(pos->member.next, typeof(*pos), member)) /** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** * list_for_each_entry_from - iterate over list of given type from the current point * @pos: the type * to use as a loop cursor. * @head: the head for your list. diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h index 14c937d345cb..0e843bf65877 100644 --- a/include/linux/lockdep.h +++ b/include/linux/lockdep.h @@ -1,7 +1,8 @@ /* * Runtime locking correctness validator * - * Copyright (C) 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com> + * Copyright (C) 2006,2007 Red Hat, Inc., Ingo Molnar <mingo@redhat.com> + * Copyright (C) 2007 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> * * see Documentation/lockdep-design.txt for more details. */ @@ -9,6 +10,7 @@ #define __LINUX_LOCKDEP_H struct task_struct; +struct lockdep_map; #ifdef CONFIG_LOCKDEP @@ -114,8 +116,44 @@ struct lock_class { const char *name; int name_version; + +#ifdef CONFIG_LOCK_STAT + unsigned long contention_point[4]; +#endif +}; + +#ifdef CONFIG_LOCK_STAT +struct lock_time { + s64 min; + s64 max; + s64 total; + unsigned long nr; +}; + +enum bounce_type { + bounce_acquired_write, + bounce_acquired_read, + bounce_contended_write, + bounce_contended_read, + nr_bounce_types, + + bounce_acquired = bounce_acquired_write, + bounce_contended = bounce_contended_write, }; +struct lock_class_stats { + unsigned long contention_point[4]; + struct lock_time read_waittime; + struct lock_time write_waittime; + struct lock_time read_holdtime; + struct lock_time write_holdtime; + unsigned long bounces[nr_bounce_types]; +}; + +struct lock_class_stats lock_stats(struct lock_class *class); +void clear_lock_stats(struct lock_class *class); +#endif + /* * Map the lock object (the lock instance) to the lock-class object. * This is embedded into specific lock instances: @@ -124,6 +162,9 @@ struct lockdep_map { struct lock_class_key *key; struct lock_class *class_cache; const char *name; +#ifdef CONFIG_LOCK_STAT + int cpu; +#endif }; /* @@ -165,6 +206,10 @@ struct held_lock { unsigned long acquire_ip; struct lockdep_map *instance; +#ifdef CONFIG_LOCK_STAT + u64 waittime_stamp; + u64 holdtime_stamp; +#endif /* * The lock-stack is unified in that the lock chains of interrupt * contexts nest ontop of process context chains, but we 'separate' @@ -281,6 +326,30 @@ struct lock_class_key { }; #endif /* !LOCKDEP */ +#ifdef CONFIG_LOCK_STAT + +extern void lock_contended(struct lockdep_map *lock, unsigned long ip); +extern void lock_acquired(struct lockdep_map *lock); + +#define LOCK_CONTENDED(_lock, try, lock) \ +do { \ + if (!try(_lock)) { \ + lock_contended(&(_lock)->dep_map, _RET_IP_); \ + lock(_lock); \ + } \ + lock_acquired(&(_lock)->dep_map); \ +} while (0) + +#else /* CONFIG_LOCK_STAT */ + +#define lock_contended(lockdep_map, ip) do {} while (0) +#define lock_acquired(lockdep_map) do {} while (0) + +#define LOCK_CONTENDED(_lock, try, lock) \ + lock(_lock) + +#endif /* CONFIG_LOCK_STAT */ + #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_GENERIC_HARDIRQS) extern void early_init_irq_lock_class(void); #else diff --git a/include/linux/loop.h b/include/linux/loop.h index 0b99b31f017b..26a0a103898f 100644 --- a/include/linux/loop.h +++ b/include/linux/loop.h @@ -63,7 +63,7 @@ struct loop_device { struct task_struct *lo_thread; wait_queue_head_t lo_event; - request_queue_t *lo_queue; + struct request_queue *lo_queue; struct gendisk *lo_disk; struct list_head lo_list; }; diff --git a/include/linux/major.h b/include/linux/major.h index 7e7c9093919a..0cb98053537a 100644 --- a/include/linux/major.h +++ b/include/linux/major.h @@ -158,6 +158,8 @@ #define VXSPEC_MAJOR 200 /* VERITAS volume config driver */ #define VXDMP_MAJOR 201 /* VERITAS volume multipath driver */ +#define XENVBD_MAJOR 202 /* Xen virtual block device */ + #define MSR_MAJOR 202 #define CPUID_MAJOR 203 diff --git a/include/linux/mdio-bitbang.h b/include/linux/mdio-bitbang.h new file mode 100644 index 000000000000..8ea9a42a4c02 --- /dev/null +++ b/include/linux/mdio-bitbang.h @@ -0,0 +1,42 @@ +#ifndef __LINUX_MDIO_BITBANG_H +#define __LINUX_MDIO_BITBANG_H + +#include <linux/phy.h> +#include <linux/module.h> + +struct mdiobb_ctrl; + +struct mdiobb_ops { + struct module *owner; + + /* Set the Management Data Clock high if level is one, + * low if level is zero. + */ + void (*set_mdc)(struct mdiobb_ctrl *ctrl, int level); + + /* Configure the Management Data I/O pin as an input if + * "output" is zero, or an output if "output" is one. + */ + void (*set_mdio_dir)(struct mdiobb_ctrl *ctrl, int output); + + /* Set the Management Data I/O pin high if value is one, + * low if "value" is zero. This may only be called + * when the MDIO pin is configured as an output. + */ + void (*set_mdio_data)(struct mdiobb_ctrl *ctrl, int value); + + /* Retrieve the state Management Data I/O pin. */ + int (*get_mdio_data)(struct mdiobb_ctrl *ctrl); +}; + +struct mdiobb_ctrl { + const struct mdiobb_ops *ops; +}; + +/* The returned bus is not yet registered with the phy layer. */ +struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl); + +/* The bus must already have been unregistered. */ +void free_mdio_bitbang(struct mii_bus *bus); + +#endif diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h index e147cf50529f..a020eb2d4e2a 100644 --- a/include/linux/mempolicy.h +++ b/include/linux/mempolicy.h @@ -159,14 +159,14 @@ extern void mpol_fix_fork_child_flag(struct task_struct *p); extern struct mempolicy default_policy; extern struct zonelist *huge_zonelist(struct vm_area_struct *vma, - unsigned long addr, gfp_t gfp_flags); + unsigned long addr, gfp_t gfp_flags, struct mempolicy **mpol); extern unsigned slab_node(struct mempolicy *policy); extern enum zone_type policy_zone; static inline void check_highest_zone(enum zone_type k) { - if (k > policy_zone) + if (k > policy_zone && k != ZONE_MOVABLE) policy_zone = k; } @@ -256,7 +256,7 @@ static inline void mpol_fix_fork_child_flag(struct task_struct *p) #define set_cpuset_being_rebound(x) do {} while (0) static inline struct zonelist *huge_zonelist(struct vm_area_struct *vma, - unsigned long addr, gfp_t gfp_flags) + unsigned long addr, gfp_t gfp_flags, struct mempolicy **mpol) { return NODE_DATA(0)->node_zonelists + gfp_zone(gfp_flags); } diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index cfb78fb2c046..222815d91c40 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -49,6 +49,10 @@ enum { }; enum { + MLX4_BOARD_ID_LEN = 64 +}; + +enum { MLX4_DEV_CAP_FLAG_RC = 1 << 0, MLX4_DEV_CAP_FLAG_UC = 1 << 1, MLX4_DEV_CAP_FLAG_UD = 1 << 2, @@ -210,6 +214,17 @@ struct mlx4_mr { int enabled; }; +struct mlx4_fmr { + struct mlx4_mr mr; + struct mlx4_mpt_entry *mpt; + __be64 *mtts; + dma_addr_t dma_handle; + int max_pages; + int max_maps; + int maps; + u8 page_shift; +}; + struct mlx4_uar { unsigned long pfn; int index; @@ -272,6 +287,8 @@ struct mlx4_dev { unsigned long flags; struct mlx4_caps caps; struct radix_tree_root qp_table_tree; + u32 rev_id; + char board_id[MLX4_BOARD_ID_LEN]; }; struct mlx4_init_port_param { @@ -331,4 +348,14 @@ int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); +int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, + int npages, u64 iova, u32 *lkey, u32 *rkey); +int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, + int max_maps, u8 page_shift, struct mlx4_fmr *fmr); +int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); +void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, + u32 *lkey, u32 *rkey); +int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); +int mlx4_SYNC_TPT(struct mlx4_dev *dev); + #endif /* MLX4_DEVICE_H */ diff --git a/include/linux/mm.h b/include/linux/mm.h index a5c451816fdc..1692dd6cb915 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -10,7 +10,6 @@ #include <linux/mmzone.h> #include <linux/rbtree.h> #include <linux/prio_tree.h> -#include <linux/fs.h> #include <linux/mutex.h> #include <linux/debug_locks.h> #include <linux/backing-dev.h> @@ -18,7 +17,9 @@ struct mempolicy; struct anon_vma; +struct file_ra_state; struct user_struct; +struct writeback_control; #ifndef CONFIG_DISCONTIGMEM /* Don't use mapnrs, do it properly */ extern unsigned long max_mapnr; @@ -168,6 +169,8 @@ extern unsigned int kobjsize(const void *objp); #define VM_INSERTPAGE 0x02000000 /* The vma has had "vm_insert_page()" done on it */ #define VM_ALWAYSDUMP 0x04000000 /* Always include in core dumps */ +#define VM_CAN_NONLINEAR 0x08000000 /* Has ->fault & does nonlinear pages */ + #ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */ #define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS #endif @@ -190,6 +193,30 @@ extern unsigned int kobjsize(const void *objp); */ extern pgprot_t protection_map[16]; +#define FAULT_FLAG_WRITE 0x01 /* Fault was a write access */ +#define FAULT_FLAG_NONLINEAR 0x02 /* Fault was via a nonlinear mapping */ + + +/* + * vm_fault is filled by the the pagefault handler and passed to the vma's + * ->fault function. The vma's ->fault is responsible for returning a bitmask + * of VM_FAULT_xxx flags that give details about how the fault was handled. + * + * pgoff should be used in favour of virtual_address, if possible. If pgoff + * is used, one may set VM_CAN_NONLINEAR in the vma->vm_flags to get nonlinear + * mapping support. + */ +struct vm_fault { + unsigned int flags; /* FAULT_FLAG_xxx flags */ + pgoff_t pgoff; /* Logical page offset based on vma */ + void __user *virtual_address; /* Faulting virtual address */ + + struct page *page; /* ->fault handlers should return a + * page here, unless VM_FAULT_NOPAGE + * is set (which is also implied by + * VM_FAULT_ERROR). + */ +}; /* * These are the virtual MM functions - opening of an area, closing and @@ -199,9 +226,11 @@ extern pgprot_t protection_map[16]; struct vm_operations_struct { void (*open)(struct vm_area_struct * area); void (*close)(struct vm_area_struct * area); - struct page * (*nopage)(struct vm_area_struct * area, unsigned long address, int *type); - unsigned long (*nopfn)(struct vm_area_struct * area, unsigned long address); - int (*populate)(struct vm_area_struct * area, unsigned long address, unsigned long len, pgprot_t prot, unsigned long pgoff, int nonblock); + int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf); + struct page *(*nopage)(struct vm_area_struct *area, + unsigned long address, int *type); + unsigned long (*nopfn)(struct vm_area_struct *area, + unsigned long address); /* notification that a previously read-only page is about to become * writable, if an error is returned it will cause a SIGBUS */ @@ -655,7 +684,6 @@ static inline int page_mapped(struct page *page) */ #define NOPAGE_SIGBUS (NULL) #define NOPAGE_OOM ((struct page *) (-1)) -#define NOPAGE_REFAULT ((struct page *) (-2)) /* Return to userspace, rerun */ /* * Error return values for the *_nopfn functions @@ -669,16 +697,18 @@ static inline int page_mapped(struct page *page) * Used to decide whether a process gets delivered SIGBUS or * just gets major/minor fault counters bumped up. */ -#define VM_FAULT_OOM 0x00 -#define VM_FAULT_SIGBUS 0x01 -#define VM_FAULT_MINOR 0x02 -#define VM_FAULT_MAJOR 0x03 - -/* - * Special case for get_user_pages. - * Must be in a distinct bit from the above VM_FAULT_ flags. - */ -#define VM_FAULT_WRITE 0x10 + +#define VM_FAULT_MINOR 0 /* For backwards compat. Remove me quickly. */ + +#define VM_FAULT_OOM 0x0001 +#define VM_FAULT_SIGBUS 0x0002 +#define VM_FAULT_MAJOR 0x0004 +#define VM_FAULT_WRITE 0x0008 /* Special case for get_user_pages */ + +#define VM_FAULT_NOPAGE 0x0100 /* ->fault installed the pte, not return page */ +#define VM_FAULT_LOCKED 0x0200 /* ->fault locked the returned page */ + +#define VM_FAULT_ERROR (VM_FAULT_OOM | VM_FAULT_SIGBUS) #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) @@ -762,20 +792,10 @@ static inline void unmap_shared_mapping_range(struct address_space *mapping, extern int vmtruncate(struct inode * inode, loff_t offset); extern int vmtruncate_range(struct inode * inode, loff_t offset, loff_t end); -extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot); -extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot); #ifdef CONFIG_MMU -extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, +extern int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, int write_access); - -static inline int handle_mm_fault(struct mm_struct *mm, - struct vm_area_struct *vma, unsigned long address, - int write_access) -{ - return __handle_mm_fault(mm, vma, address, write_access) & - (~VM_FAULT_WRITE); -} #else static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, @@ -789,7 +809,6 @@ static inline int handle_mm_fault(struct mm_struct *mm, extern int make_pages_present(unsigned long addr, unsigned long end); extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write); -void install_arg_page(struct vm_area_struct *, struct page *, unsigned long); int get_user_pages(struct task_struct *tsk, struct mm_struct *mm, unsigned long start, int len, int write, int force, struct page **pages, struct vm_area_struct **vmas); @@ -806,9 +825,15 @@ int FASTCALL(set_page_dirty(struct page *page)); int set_page_dirty_lock(struct page *page); int clear_page_dirty_for_io(struct page *page); +extern unsigned long move_page_tables(struct vm_area_struct *vma, + unsigned long old_addr, struct vm_area_struct *new_vma, + unsigned long new_addr, unsigned long len); extern unsigned long do_mremap(unsigned long addr, unsigned long old_len, unsigned long new_len, unsigned long flags, unsigned long new_addr); +extern int mprotect_fixup(struct vm_area_struct *vma, + struct vm_area_struct **pprev, unsigned long start, + unsigned long end, unsigned long newflags); /* * A callback you can register to apply pressure to ageable caches. @@ -837,38 +862,7 @@ struct shrinker { extern void register_shrinker(struct shrinker *); extern void unregister_shrinker(struct shrinker *); -/* - * Some shared mappigns will want the pages marked read-only - * to track write events. If so, we'll downgrade vm_page_prot - * to the private version (using protection_map[] without the - * VM_SHARED bit). - */ -static inline int vma_wants_writenotify(struct vm_area_struct *vma) -{ - unsigned int vm_flags = vma->vm_flags; - - /* If it was private or non-writable, the write bit is already clear */ - if ((vm_flags & (VM_WRITE|VM_SHARED)) != ((VM_WRITE|VM_SHARED))) - return 0; - - /* The backer wishes to know when pages are first written to? */ - if (vma->vm_ops && vma->vm_ops->page_mkwrite) - return 1; - - /* The open routine did something to the protections already? */ - if (pgprot_val(vma->vm_page_prot) != - pgprot_val(protection_map[vm_flags & - (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)])) - return 0; - - /* Specialty mapping? */ - if (vm_flags & (VM_PFNMAP|VM_INSERTPAGE)) - return 0; - - /* Can the mapping track the dirty pages? */ - return vma->vm_file && vma->vm_file->f_mapping && - mapping_cap_account_dirty(vma->vm_file->f_mapping); -} +int vma_wants_writenotify(struct vm_area_struct *vma); extern pte_t *FASTCALL(get_locked_pte(struct mm_struct *mm, unsigned long addr, spinlock_t **ptl)); @@ -1048,7 +1042,7 @@ static inline void vma_nonlinear_insert(struct vm_area_struct *vma, } /* mmap.c */ -extern int __vm_enough_memory(long pages, int cap_sys_admin); +extern int __vm_enough_memory(struct mm_struct *mm, long pages, int cap_sys_admin); extern void vma_adjust(struct vm_area_struct *vma, unsigned long start, unsigned long end, pgoff_t pgoff, struct vm_area_struct *insert); extern struct vm_area_struct *vma_merge(struct mm_struct *, @@ -1104,9 +1098,7 @@ extern void truncate_inode_pages_range(struct address_space *, loff_t lstart, loff_t lend); /* generic vm_area_ops exported for stackable file systems */ -extern struct page *filemap_nopage(struct vm_area_struct *, unsigned long, int *); -extern int filemap_populate(struct vm_area_struct *, unsigned long, - unsigned long, pgprot_t, unsigned long, int); +extern int filemap_fault(struct vm_area_struct *, struct vm_fault *); /* mm/page-writeback.c */ int write_one_page(struct page *page, int wait); @@ -1121,13 +1113,20 @@ int do_page_cache_readahead(struct address_space *mapping, struct file *filp, pgoff_t offset, unsigned long nr_to_read); int force_page_cache_readahead(struct address_space *mapping, struct file *filp, pgoff_t offset, unsigned long nr_to_read); -unsigned long page_cache_readahead(struct address_space *mapping, - struct file_ra_state *ra, - struct file *filp, - pgoff_t offset, - unsigned long size); -void handle_ra_miss(struct address_space *mapping, - struct file_ra_state *ra, pgoff_t offset); + +void page_cache_sync_readahead(struct address_space *mapping, + struct file_ra_state *ra, + struct file *filp, + pgoff_t offset, + unsigned long size); + +void page_cache_async_readahead(struct address_space *mapping, + struct file_ra_state *ra, + struct file *filp, + struct page *pg, + pgoff_t offset, + unsigned long size); + unsigned long max_sane_readahead(unsigned long nr); /* Do stack extension */ @@ -1135,6 +1134,8 @@ extern int expand_stack(struct vm_area_struct *vma, unsigned long address); #ifdef CONFIG_IA64 extern int expand_upwards(struct vm_area_struct *vma, unsigned long address); #endif +extern int expand_stack_downwards(struct vm_area_struct *vma, + unsigned long address); /* Look up the first VMA which satisfies addr < vm_end, NULL if none. */ extern struct vm_area_struct * find_vma(struct mm_struct * mm, unsigned long addr); @@ -1215,7 +1216,7 @@ void drop_slab(void); extern int randomize_va_space; #endif -__attribute__((weak)) const char *arch_vma_name(struct vm_area_struct *vma); +const char * arch_vma_name(struct vm_area_struct *vma); #endif /* __KERNEL__ */ #endif /* _LINUX_MM_H */ diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index badf702fcff4..0d508ac17d64 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -55,7 +55,28 @@ struct sd_switch_caps { unsigned int hs_max_dtr; }; +struct sdio_cccr { + unsigned int sdio_vsn; + unsigned int sd_vsn; + unsigned int multi_block:1, + low_speed:1, + wide_bus:1, + high_power:1, + high_speed:1; +}; + +struct sdio_cis { + unsigned short vendor; + unsigned short device; + unsigned short blksize; + unsigned int max_dtr; +}; + struct mmc_host; +struct sdio_func; +struct sdio_func_tuple; + +#define SDIO_MAX_FUNCS 7 /* * MMC device @@ -67,11 +88,13 @@ struct mmc_card { unsigned int type; /* card type */ #define MMC_TYPE_MMC 0 /* MMC card */ #define MMC_TYPE_SD 1 /* SD card */ +#define MMC_TYPE_SDIO 2 /* SDIO card */ unsigned int state; /* (our) card state */ #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ #define MMC_STATE_READONLY (1<<1) /* card is read-only */ #define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */ #define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ + u32 raw_cid[4]; /* raw card CID */ u32 raw_csd[4]; /* raw card CSD */ u32 raw_scr[2]; /* raw card SCR */ @@ -80,10 +103,19 @@ struct mmc_card { struct mmc_ext_csd ext_csd; /* mmc v4 extended card specific */ struct sd_scr scr; /* extra SD information */ struct sd_switch_caps sw_caps; /* switch (CMD6) caps */ + + unsigned int sdio_funcs; /* number of SDIO functions */ + struct sdio_cccr cccr; /* common card info */ + struct sdio_cis cis; /* common tuple info */ + struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */ + unsigned num_info; /* number of info strings */ + const char **info; /* info strings */ + struct sdio_func_tuple *tuples; /* unknown common tuples */ }; #define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC) #define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD) +#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) #define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 04bbe12fae8d..d0c3abed74c2 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -25,14 +25,20 @@ struct mmc_command { #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ -#define MMC_CMD_MASK (3 << 5) /* command type */ + +#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ #define MMC_CMD_AC (0 << 5) #define MMC_CMD_ADTC (1 << 5) #define MMC_CMD_BC (2 << 5) #define MMC_CMD_BCR (3 << 5) +#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ +#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ +#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ +#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ + /* - * These are the response types, and correspond to valid bit + * These are the native response types, and correspond to valid bit * patterns of the above flags. One additional valid pattern * is all zeros, which means we don't expect a response. */ @@ -41,12 +47,30 @@ struct mmc_command { #define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) #define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) /* + * These are the SPI response types for MMC, SD, and SDIO cards. + * Commands return R1, with maybe more info. Zero is an error type; + * callers must always provide the appropriate MMC_RSP_SPI_Rx flags. + */ +#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1) +#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY) +#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) +#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) +#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) +#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) +#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) + +#define mmc_spi_resp_type(cmd) ((cmd)->flags & \ + (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY|MMC_RSP_SPI_S2|MMC_RSP_SPI_B4)) + +/* * These are the command types. */ #define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) @@ -54,12 +78,19 @@ struct mmc_command { unsigned int retries; /* max number of retries */ unsigned int error; /* command error */ -#define MMC_ERR_NONE 0 -#define MMC_ERR_TIMEOUT 1 -#define MMC_ERR_BADCRC 2 -#define MMC_ERR_FIFO 3 -#define MMC_ERR_FAILED 4 -#define MMC_ERR_INVALID 5 +/* + * Standard errno values are used for errors, but some have specific + * meaning in the MMC layer: + * + * ETIMEDOUT Card took too long to respond + * EILSEQ Basic format problem with the received or sent data + * (e.g. CRC check failed, incorrect opcode in response + * or bad end bit) + * EINVAL Request cannot be performed because of restrictions + * in hardware and/or the driver + * ENOMEDIUM Host can determine that the slot is empty and is + * actively failing requests + */ struct mmc_data *data; /* data segment associated with cmd */ struct mmc_request *mrq; /* associated request */ @@ -76,7 +107,6 @@ struct mmc_data { #define MMC_DATA_WRITE (1 << 8) #define MMC_DATA_READ (1 << 9) #define MMC_DATA_STREAM (1 << 10) -#define MMC_DATA_MULTI (1 << 11) unsigned int bytes_xfered; @@ -99,14 +129,25 @@ struct mmc_request { struct mmc_host; struct mmc_card; -extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *); +extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *); extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, struct mmc_command *, int); -extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *, int); +extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *); -extern void mmc_claim_host(struct mmc_host *host); +extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort); extern void mmc_release_host(struct mmc_host *host); +/** + * mmc_claim_host - exclusively claim a host + * @host: mmc host to claim + * + * Claim a host for a set of operations. + */ +static inline void mmc_claim_host(struct mmc_host *host) +{ + __mmc_claim_host(host, NULL); +} + #endif diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index b1350dfd3e91..125eee1407ff 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -10,6 +10,8 @@ #ifndef LINUX_MMC_HOST_H #define LINUX_MMC_HOST_H +#include <linux/leds.h> + #include <linux/mmc/core.h> struct mmc_ios { @@ -51,6 +53,7 @@ struct mmc_host_ops { void (*request)(struct mmc_host *host, struct mmc_request *req); void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); int (*get_ro)(struct mmc_host *host); + void (*enable_sdio_irq)(struct mmc_host *host, int enable); }; struct mmc_card; @@ -87,9 +90,10 @@ struct mmc_host { #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ #define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */ -#define MMC_CAP_BYTEBLOCK (1 << 2) /* Can do non-log2 block sizes */ -#define MMC_CAP_MMC_HIGHSPEED (1 << 3) /* Can do MMC high-speed timing */ -#define MMC_CAP_SD_HIGHSPEED (1 << 4) /* Can do SD high-speed timing */ +#define MMC_CAP_MMC_HIGHSPEED (1 << 2) /* Can do MMC high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED (1 << 3) /* Can do SD high-speed timing */ +#define MMC_CAP_SDIO_IRQ (1 << 4) /* Can signal pending SDIO IRQs */ +#define MMC_CAP_SPI (1 << 5) /* Talks only SPI protocols */ /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ @@ -106,6 +110,14 @@ struct mmc_host { struct mmc_ios ios; /* current io bus settings */ u32 ocr; /* the current OCR setting */ + /* group bitfields together to minimize padding */ + unsigned int use_spi_crc:1; + unsigned int claimed:1; /* host exclusively claimed */ + unsigned int bus_dead:1; /* bus has been released */ +#ifdef CONFIG_MMC_DEBUG + unsigned int removed:1; /* host is being removed */ +#endif + unsigned int mode; /* current card mode of host */ #define MMC_MODE_MMC 0 #define MMC_MODE_SD 1 @@ -113,16 +125,19 @@ struct mmc_host { struct mmc_card *card; /* device attached to this host */ wait_queue_head_t wq; - unsigned int claimed:1; /* host exclusively claimed */ struct delayed_work detect; -#ifdef CONFIG_MMC_DEBUG - unsigned int removed:1; /* host is being removed */ -#endif const struct mmc_bus_ops *bus_ops; /* current bus driver */ unsigned int bus_refs; /* reference counter */ - unsigned int bus_dead:1; /* bus has been released */ + + unsigned int sdio_irqs; + struct task_struct *sdio_irq_thread; + atomic_t sdio_irq_thread_abort; + +#ifdef CONFIG_LEDS_TRIGGERS + struct led_trigger *led; /* activity led */ +#endif unsigned long private[0] ____cacheline_aligned; }; @@ -137,6 +152,8 @@ static inline void *mmc_priv(struct mmc_host *host) return (void *)host->private; } +#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) + #define mmc_dev(x) ((x)->parent) #define mmc_classdev(x) (&(x)->class_dev) #define mmc_hostname(x) ((x)->class_dev.bus_id) @@ -147,5 +164,11 @@ extern int mmc_resume_host(struct mmc_host *); extern void mmc_detect_change(struct mmc_host *, unsigned long delay); extern void mmc_request_done(struct mmc_host *, struct mmc_request *); +static inline void mmc_signal_sdio_irq(struct mmc_host *host) +{ + host->ops->enable_sdio_irq(host, 0); + wake_up_process(host->sdio_irq_thread); +} + #endif diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index e3ed9b95040e..4236fbf0b6fb 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -27,7 +27,7 @@ /* Standard MMC commands (4.1) type argument response */ /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ +#define MMC_GO_IDLE_STATE 0 /* bc */ #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ #define MMC_ALL_SEND_CID 2 /* bcr R2 */ #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ @@ -39,8 +39,10 @@ #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ +#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ +#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ +#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ /* class 2 */ #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ @@ -90,15 +92,15 @@ */ /* - MMC status in R1 + MMC status in R1, for native mode (SPI bits are different) Type - e : error bit + e : error bit s : status bit r : detected and set for the actual command response x : detected and set during command execution. the host must poll the card by sending status command in order to read these bits. Clear condition - a : according to the card state + a : according to the card state b : always related to the previous command. Reception of a valid command will clear it (with a delay of one command) c : clear by read @@ -124,10 +126,33 @@ #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ #define R1_ERASE_RESET (1 << 13) /* sr, c */ #define R1_STATUS(x) (x & 0xFFFFE000) -#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ #define R1_APP_CMD (1 << 5) /* sr, c */ +/* + * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS + * R1 is the low order byte; R2 is the next highest byte, when present. + */ +#define R1_SPI_IDLE (1 << 0) +#define R1_SPI_ERASE_RESET (1 << 1) +#define R1_SPI_ILLEGAL_COMMAND (1 << 2) +#define R1_SPI_COM_CRC (1 << 3) +#define R1_SPI_ERASE_SEQ (1 << 4) +#define R1_SPI_ADDRESS (1 << 5) +#define R1_SPI_PARAMETER (1 << 6) +/* R1 bit 7 is always zero */ +#define R2_SPI_CARD_LOCKED (1 << 8) +#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1 << 10) +#define R2_SPI_CC_ERROR (1 << 11) +#define R2_SPI_CARD_ECC_ERROR (1 << 12) +#define R2_SPI_WP_VIOLATION (1 << 13) +#define R2_SPI_ERASE_PARAM (1 << 14) +#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE + /* These are unpacked versions of the actual responses */ struct _mmc_csd { @@ -182,6 +207,7 @@ struct _mmc_csd { */ #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ + /* (and for SPI, CMD58,59) */ #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ /* (CMD11) */ #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ @@ -227,6 +253,7 @@ struct _mmc_csd { #define EXT_CSD_BUS_WIDTH 183 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ /* diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h new file mode 100644 index 000000000000..47ba464f5170 --- /dev/null +++ b/include/linux/mmc/sdio.h @@ -0,0 +1,159 @@ +/* + * include/linux/mmc/sdio.h + * + * Copyright 2006-2007 Pierre Ossman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#ifndef MMC_SDIO_H +#define MMC_SDIO_H + +/* SDIO commands type argument response */ +#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ +#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ +#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */ + +/* + * SD_IO_RW_DIRECT argument format: + * + * [31] R/W flag + * [30:28] Function number + * [27] RAW flag + * [25:9] Register address + * [7:0] Data + */ + +/* + * SD_IO_RW_EXTENDED argument format: + * + * [31] R/W flag + * [30:28] Function number + * [27] Block mode + * [26] Increment address + * [25:9] Register address + * [8:0] Byte/block count + */ + +/* + SDIO status in R5 + Type + e : error bit + s : status bit + r : detected and set for the actual command response + x : detected and set during command execution. the host must poll + the card by sending status command in order to read these bits. + Clear condition + a : according to the card state + b : always related to the previous command. Reception of + a valid command will clear it (with a delay of one command) + c : clear by read + */ + +#define R5_COM_CRC_ERROR (1 << 15) /* er, b */ +#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */ +#define R5_ERROR (1 << 11) /* erx, c */ +#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */ +#define R5_OUT_OF_RANGE (1 << 8) /* er, c */ +#define R5_STATUS(x) (x & 0xCB00) +#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */ + +/* + * Card Common Control Registers (CCCR) + */ + +#define SDIO_CCCR_CCCR 0x00 + +#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */ +#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */ +#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */ + +#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */ +#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */ +#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */ +#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */ + +#define SDIO_CCCR_SD 0x01 + +#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */ +#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */ +#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */ + +#define SDIO_CCCR_IOEx 0x02 +#define SDIO_CCCR_IORx 0x03 + +#define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */ +#define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */ + +#define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */ + +#define SDIO_CCCR_IF 0x07 /* bus interface controls */ + +#define SDIO_BUS_WIDTH_1BIT 0x00 +#define SDIO_BUS_WIDTH_4BIT 0x02 + +#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */ + +#define SDIO_CCCR_CAPS 0x08 + +#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */ +#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */ +#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */ +#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */ +#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */ +#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */ +#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */ +#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */ + +#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */ + +/* Following 4 regs are valid only if SBS is set */ +#define SDIO_CCCR_SUSPEND 0x0c +#define SDIO_CCCR_SELx 0x0d +#define SDIO_CCCR_EXECx 0x0e +#define SDIO_CCCR_READYx 0x0f + +#define SDIO_CCCR_BLKSIZE 0x10 + +#define SDIO_CCCR_POWER 0x12 + +#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */ +#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */ + +#define SDIO_CCCR_SPEED 0x13 + +#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */ +#define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */ + +/* + * Function Basic Registers (FBR) + */ + +#define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */ + +#define SDIO_FBR_STD_IF 0x00 + +#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */ +#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */ + +#define SDIO_FBR_STD_IF_EXT 0x01 + +#define SDIO_FBR_POWER 0x02 + +#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */ +#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */ + +#define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */ + + +#define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */ + +#define SDIO_FBR_CSA_DATA 0x0F + +#define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ + +#endif + diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h new file mode 100644 index 000000000000..b050f4d7b41f --- /dev/null +++ b/include/linux/mmc/sdio_func.h @@ -0,0 +1,153 @@ +/* + * include/linux/mmc/sdio_func.h + * + * Copyright 2007 Pierre Ossman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#ifndef MMC_SDIO_FUNC_H +#define MMC_SDIO_FUNC_H + +#include <linux/device.h> +#include <linux/mod_devicetable.h> + +struct mmc_card; +struct sdio_func; + +typedef void (sdio_irq_handler_t)(struct sdio_func *); + +/* + * SDIO function CIS tuple (unknown to the core) + */ +struct sdio_func_tuple { + struct sdio_func_tuple *next; + unsigned char code; + unsigned char size; + unsigned char data[0]; +}; + +/* + * SDIO function devices + */ +struct sdio_func { + struct mmc_card *card; /* the card this device belongs to */ + struct device dev; /* the device */ + sdio_irq_handler_t *irq_handler; /* IRQ callback */ + unsigned int num; /* function number */ + + unsigned char class; /* standard interface class */ + unsigned short vendor; /* vendor id */ + unsigned short device; /* device id */ + + unsigned max_blksize; /* maximum block size */ + unsigned cur_blksize; /* current block size */ + + unsigned int state; /* function state */ +#define SDIO_STATE_PRESENT (1<<0) /* present in sysfs */ + + u8 tmpbuf[4]; /* DMA:able scratch buffer */ + + unsigned num_info; /* number of info strings */ + const char **info; /* info strings */ + + struct sdio_func_tuple *tuples; +}; + +#define sdio_func_present(f) ((f)->state & SDIO_STATE_PRESENT) + +#define sdio_func_set_present(f) ((f)->state |= SDIO_STATE_PRESENT) + +#define sdio_func_id(f) ((f)->dev.bus_id) + +#define sdio_get_drvdata(f) dev_get_drvdata(&(f)->dev) +#define sdio_set_drvdata(f,d) dev_set_drvdata(&(f)->dev, d) + +/* + * SDIO function device driver + */ +struct sdio_driver { + char *name; + const struct sdio_device_id *id_table; + + int (*probe)(struct sdio_func *, const struct sdio_device_id *); + void (*remove)(struct sdio_func *); + + struct device_driver drv; +}; + +/** + * SDIO_DEVICE - macro used to describe a specific SDIO device + * @vend: the 16 bit manufacturer code + * @dev: the 16 bit function id + * + * This macro is used to create a struct sdio_device_id that matches a + * specific device. The class field will be set to SDIO_ANY_ID. + */ +#define SDIO_DEVICE(vend,dev) \ + .class = SDIO_ANY_ID, \ + .vendor = (vend), .device = (dev) + +/** + * SDIO_DEVICE_CLASS - macro used to describe a specific SDIO device class + * @dev_class: the 8 bit standard interface code + * + * This macro is used to create a struct sdio_device_id that matches a + * specific standard SDIO function type. The vendor and device fields will + * be set to SDIO_ANY_ID. + */ +#define SDIO_DEVICE_CLASS(dev_class) \ + .class = (dev_class), \ + .vendor = SDIO_ANY_ID, .device = SDIO_ANY_ID + +extern int sdio_register_driver(struct sdio_driver *); +extern void sdio_unregister_driver(struct sdio_driver *); + +/* + * SDIO I/O operations + */ +extern void sdio_claim_host(struct sdio_func *func); +extern void sdio_release_host(struct sdio_func *func); + +extern int sdio_enable_func(struct sdio_func *func); +extern int sdio_disable_func(struct sdio_func *func); + +extern int sdio_set_block_size(struct sdio_func *func, unsigned blksz); + +extern int sdio_claim_irq(struct sdio_func *func, sdio_irq_handler_t *handler); +extern int sdio_release_irq(struct sdio_func *func); + +extern unsigned char sdio_readb(struct sdio_func *func, + unsigned int addr, int *err_ret); +extern unsigned short sdio_readw(struct sdio_func *func, + unsigned int addr, int *err_ret); +extern unsigned long sdio_readl(struct sdio_func *func, + unsigned int addr, int *err_ret); + +extern int sdio_memcpy_fromio(struct sdio_func *func, void *dst, + unsigned int addr, int count); +extern int sdio_readsb(struct sdio_func *func, void *dst, + unsigned int addr, int count); + +extern void sdio_writeb(struct sdio_func *func, unsigned char b, + unsigned int addr, int *err_ret); +extern void sdio_writew(struct sdio_func *func, unsigned short b, + unsigned int addr, int *err_ret); +extern void sdio_writel(struct sdio_func *func, unsigned long b, + unsigned int addr, int *err_ret); + +extern int sdio_memcpy_toio(struct sdio_func *func, unsigned int addr, + void *src, int count); +extern int sdio_writesb(struct sdio_func *func, unsigned int addr, + void *src, int count); + +extern unsigned char sdio_f0_readb(struct sdio_func *func, + unsigned int addr, int *err_ret); +extern void sdio_f0_writeb(struct sdio_func *func, unsigned char b, + unsigned int addr, int *err_ret); + +#endif + diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h new file mode 100644 index 000000000000..09306d47ff5e --- /dev/null +++ b/include/linux/mmc/sdio_ids.h @@ -0,0 +1,23 @@ +/* + * SDIO Classes, Interface Types, Manufacturer IDs, etc. + */ + +#ifndef MMC_SDIO_IDS_H +#define MMC_SDIO_IDS_H + +/* + * Standard SDIO Function Interfaces + */ + +#define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */ +#define SDIO_CLASS_UART 0x01 /* standard UART interface */ +#define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */ +#define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */ +#define SDIO_CLASS_GPS 0x04 /* GPS standard interface */ +#define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */ +#define SDIO_CLASS_PHS 0x06 /* PHS standard interface */ +#define SDIO_CLASS_WLAN 0x07 /* WLAN interface */ +#define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */ + + +#endif diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index da8eb8ad9e9b..4e5627379b09 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -120,7 +120,6 @@ enum zone_type { * --------------------------- * parisc, ia64, sparc <4G * s390 <2G - * arm26 <48M * arm Various * alpha Unlimited or 0-16MB. * @@ -411,6 +410,24 @@ struct zonelist { #endif }; +#ifdef CONFIG_NUMA +/* + * Only custom zonelists like MPOL_BIND need to be filtered as part of + * policies. As described in the comment for struct zonelist_cache, these + * zonelists will not have a zlcache so zlcache_ptr will not be set. Use + * that to determine if the zonelists needs to be filtered or not. + */ +static inline int alloc_should_filter_zonelist(struct zonelist *zonelist) +{ + return !zonelist->zlcache_ptr; +} +#else +static inline int alloc_should_filter_zonelist(struct zonelist *zonelist) +{ + return 0; +} +#endif /* CONFIG_NUMA */ + #ifdef CONFIG_ARCH_POPULATES_NODE_MAP struct node_active_region { unsigned long start_pfn; diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index af04a555b52c..74523d999f7a 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -159,6 +159,13 @@ struct ap_device_id { #define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01 +#define ACPI_ID_LEN 16 /* only 9 bytes needed here, 16 bytes are used */ + /* to workaround crosscompile issues */ + +struct acpi_device_id { + __u8 id[ACPI_ID_LEN]; + kernel_ulong_t driver_data; +}; #define PNP_ID_LEN 8 #define PNP_MAX_DEVICES 8 @@ -333,4 +340,30 @@ struct parisc_device_id { #define PA_HVERSION_ANY_ID 0xffff #define PA_SVERSION_ANY_ID 0xffffffff +/* SDIO */ + +#define SDIO_ANY_ID (~0) + +struct sdio_device_id { + __u8 class; /* Standard interface or SDIO_ANY_ID */ + __u16 vendor; /* Vendor or SDIO_ANY_ID */ + __u16 device; /* Device ID or SDIO_ANY_ID */ + kernel_ulong_t driver_data; /* Data private to the driver */ +}; + +/* SSB core, see drivers/ssb/ */ +struct ssb_device_id { + __u16 vendor; + __u16 coreid; + __u8 revision; +}; +#define SSB_DEVICE(_vendor, _coreid, _revision) \ + { .vendor = _vendor, .coreid = _coreid, .revision = _revision, } +#define SSB_DEVTABLE_END \ + { 0, }, + +#define SSB_ANY_VENDOR 0xFFFF +#define SSB_ANY_ID 0xFFFF +#define SSB_ANY_REV 0xFF + #endif /* LINUX_MOD_DEVICETABLE_H */ diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h index b021b3a2b65a..9c8049005052 100644 --- a/include/linux/mv643xx.h +++ b/include/linux/mv643xx.h @@ -1302,4 +1302,12 @@ struct mv643xx_eth_platform_data { u8 mac_addr[6]; /* mac address if non-zero*/ }; +/* Watchdog Platform Device, Driver Data */ +#define MV64x60_WDT_NAME "mv64x60_wdt" + +struct mv64x60_wdt_pdata { + int timeout; /* watchdog expiry in seconds, default 10 */ + int bus_clk; /* bus clock in MHz, default 133 */ +}; + #endif /* __ASM_MV643XX_H */ diff --git a/include/linux/namei.h b/include/linux/namei.h index b7dd24917f0d..6c38efbd810f 100644 --- a/include/linux/namei.h +++ b/include/linux/namei.h @@ -69,8 +69,8 @@ extern int FASTCALL(__user_walk_fd(int dfd, const char __user *, unsigned, struc #define user_path_walk_link(name,nd) \ __user_walk_fd(AT_FDCWD, name, 0, nd) extern int FASTCALL(path_lookup(const char *, unsigned, struct nameidata *)); -extern int FASTCALL(path_walk(const char *, struct nameidata *)); -extern int FASTCALL(link_path_walk(const char *, struct nameidata *)); +extern int vfs_path_lookup(struct dentry *, struct vfsmount *, + const char *, unsigned int, struct nameidata *); extern void path_release(struct nameidata *); extern void path_release_on_umount(struct nameidata *); diff --git a/include/linux/net.h b/include/linux/net.h index efc45177b503..c136abce7ef6 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -23,6 +23,7 @@ struct poll_table_struct; struct inode; +struct net; #define NPROTO 34 /* should be enough for now.. */ @@ -169,7 +170,7 @@ struct proto_ops { struct net_proto_family { int family; - int (*create)(struct socket *sock, int protocol); + int (*create)(struct net *net, struct socket *sock, int protocol); struct module *owner; }; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index da7a13c97eb8..5a11f889e56a 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -31,6 +31,7 @@ #ifdef __KERNEL__ #include <linux/timer.h> +#include <linux/delay.h> #include <asm/atomic.h> #include <asm/cache.h> #include <asm/byteorder.h> @@ -38,6 +39,9 @@ #include <linux/device.h> #include <linux/percpu.h> #include <linux/dmaengine.h> +#include <linux/workqueue.h> + +#include <net/net_namespace.h> struct vlan_group; struct ethtool_ops; @@ -246,6 +250,19 @@ struct hh_cache #define LL_RESERVED_SPACE_EXTRA(dev,extra) \ ((((dev)->hard_header_len+extra)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) +struct header_ops { + int (*create) (struct sk_buff *skb, struct net_device *dev, + unsigned short type, const void *daddr, + const void *saddr, unsigned len); + int (*parse)(const struct sk_buff *skb, unsigned char *haddr); + int (*rebuild)(struct sk_buff *skb); +#define HAVE_HEADER_CACHE + int (*cache)(const struct neighbour *neigh, struct hh_cache *hh); + void (*cache_update)(struct hh_cache *hh, + const struct net_device *dev, + const unsigned char *haddr); +}; + /* These flag bits are private to the generic network queueing * layer, they may not be explicitly referenced by any other * code. @@ -258,7 +275,6 @@ enum netdev_state_t __LINK_STATE_PRESENT, __LINK_STATE_SCHED, __LINK_STATE_NOCARRIER, - __LINK_STATE_RX_SCHED, __LINK_STATE_LINKWATCH_PENDING, __LINK_STATE_DORMANT, __LINK_STATE_QDISC_RUNNING, @@ -278,6 +294,120 @@ struct netdev_boot_setup { extern int __init netdev_boot_setup(char *str); /* + * Structure for NAPI scheduling similar to tasklet but with weighting + */ +struct napi_struct { + /* The poll_list must only be managed by the entity which + * changes the state of the NAPI_STATE_SCHED bit. This means + * whoever atomically sets that bit can add this napi_struct + * to the per-cpu poll_list, and whoever clears that bit + * can remove from the list right before clearing the bit. + */ + struct list_head poll_list; + + unsigned long state; + int weight; + int (*poll)(struct napi_struct *, int); +#ifdef CONFIG_NETPOLL + spinlock_t poll_lock; + int poll_owner; + struct net_device *dev; + struct list_head dev_list; +#endif +}; + +enum +{ + NAPI_STATE_SCHED, /* Poll is scheduled */ +}; + +extern void FASTCALL(__napi_schedule(struct napi_struct *n)); + +/** + * napi_schedule_prep - check if napi can be scheduled + * @n: napi context + * + * Test if NAPI routine is already running, and if not mark + * it as running. This is used as a condition variable + * insure only one NAPI poll instance runs + */ +static inline int napi_schedule_prep(struct napi_struct *n) +{ + return !test_and_set_bit(NAPI_STATE_SCHED, &n->state); +} + +/** + * napi_schedule - schedule NAPI poll + * @n: napi context + * + * Schedule NAPI poll routine to be called if it is not already + * running. + */ +static inline void napi_schedule(struct napi_struct *n) +{ + if (napi_schedule_prep(n)) + __napi_schedule(n); +} + +/* Try to reschedule poll. Called by dev->poll() after napi_complete(). */ +static inline int napi_reschedule(struct napi_struct *napi) +{ + if (napi_schedule_prep(napi)) { + __napi_schedule(napi); + return 1; + } + return 0; +} + +/** + * napi_complete - NAPI processing complete + * @n: napi context + * + * Mark NAPI processing as complete. + */ +static inline void __napi_complete(struct napi_struct *n) +{ + BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); + list_del(&n->poll_list); + smp_mb__before_clear_bit(); + clear_bit(NAPI_STATE_SCHED, &n->state); +} + +static inline void napi_complete(struct napi_struct *n) +{ + local_irq_disable(); + __napi_complete(n); + local_irq_enable(); +} + +/** + * napi_disable - prevent NAPI from scheduling + * @n: napi context + * + * Stop NAPI from being scheduled on this context. + * Waits till any outstanding processing completes. + */ +static inline void napi_disable(struct napi_struct *n) +{ + while (test_and_set_bit(NAPI_STATE_SCHED, &n->state)) + msleep_interruptible(1); +} + +/** + * napi_enable - enable NAPI scheduling + * @n: napi context + * + * Resume NAPI from being scheduled on this context. + * Must be paired with napi_disable. + */ +static inline void napi_enable(struct napi_struct *n) +{ + BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); + smp_mb__before_clear_bit(); + clear_bit(NAPI_STATE_SCHED, &n->state); +} + +/* * The DEVICE structure. * Actually, this whole structure is a big mistake. It mixes I/O * data with strictly "high-level" data, and it has to know about @@ -319,6 +449,9 @@ struct net_device unsigned long state; struct list_head dev_list; +#ifdef CONFIG_NETPOLL + struct list_head napi_list; +#endif /* The device initialization function. Called only once. */ int (*init)(struct net_device *dev); @@ -339,8 +472,11 @@ struct net_device #define NETIF_F_HW_VLAN_FILTER 512 /* Receive filtering on VLAN */ #define NETIF_F_VLAN_CHALLENGED 1024 /* Device cannot handle VLAN packets */ #define NETIF_F_GSO 2048 /* Enable software GSO. */ -#define NETIF_F_LLTX 4096 /* LockLess TX */ +#define NETIF_F_LLTX 4096 /* LockLess TX - deprecated. Please */ + /* do not use LLTX in new drivers */ +#define NETIF_F_NETNS_LOCAL 8192 /* Does not change network namespaces */ #define NETIF_F_MULTI_QUEUE 16384 /* Has multiple TX/RX queues */ +#define NETIF_F_LRO 32768 /* large receive offload */ /* Segmentation offload features */ #define NETIF_F_GSO_SHIFT 16 @@ -379,6 +515,9 @@ struct net_device #endif const struct ethtool_ops *ethtool_ops; + /* Hardware header description */ + const struct header_ops *header_ops; + /* * This marks the end of the "visible" part of the structure. All * fields hereafter are internal to the system, and may change at @@ -430,12 +569,6 @@ struct net_device /* * Cache line mostly used on receive path (including eth_type_trans()) */ - struct list_head poll_list ____cacheline_aligned_in_smp; - /* Link to poll list */ - - int (*poll) (struct net_device *dev, int *quota); - int quota; - int weight; unsigned long last_rx; /* Time of last Rx */ /* Interface address info used in eth_type_trans() */ unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address, (before bcast @@ -508,13 +641,6 @@ struct net_device int (*open)(struct net_device *dev); int (*stop)(struct net_device *dev); #define HAVE_NETDEV_POLL - int (*hard_header) (struct sk_buff *skb, - struct net_device *dev, - unsigned short type, - void *daddr, - void *saddr, - unsigned len); - int (*rebuild_header)(struct sk_buff *skb); #define HAVE_CHANGE_RX_FLAGS void (*change_rx_flags)(struct net_device *dev, int flags); @@ -531,12 +657,6 @@ struct net_device #define HAVE_SET_CONFIG int (*set_config)(struct net_device *dev, struct ifmap *map); -#define HAVE_HEADER_CACHE - int (*hard_header_cache)(struct neighbour *neigh, - struct hh_cache *hh); - void (*header_cache_update)(struct hh_cache *hh, - struct net_device *dev, - unsigned char * haddr); #define HAVE_CHANGE_MTU int (*change_mtu)(struct net_device *dev, int new_mtu); @@ -550,8 +670,6 @@ struct net_device void (*vlan_rx_kill_vid)(struct net_device *dev, unsigned short vid); - int (*hard_header_parse)(struct sk_buff *skb, - unsigned char *haddr); int (*neigh_setup)(struct net_device *dev, struct neigh_parms *); #ifdef CONFIG_NETPOLL struct netpoll_info *npinfo; @@ -560,6 +678,9 @@ struct net_device void (*poll_controller)(struct net_device *dev); #endif + /* Network namespace this network device is inside */ + struct net *nd_net; + /* bridge stuff */ struct net_bridge_port *br_port; /* macvlan */ @@ -575,24 +696,46 @@ struct net_device /* The TX queue control structures */ unsigned int egress_subqueue_count; - struct net_device_subqueue egress_subqueue[0]; + struct net_device_subqueue egress_subqueue[1]; }; #define to_net_dev(d) container_of(d, struct net_device, dev) #define NETDEV_ALIGN 32 #define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) +/** + * netdev_priv - access network device private data + * @dev: network device + * + * Get network device private data + */ static inline void *netdev_priv(const struct net_device *dev) { return dev->priv; } -#define SET_MODULE_OWNER(dev) do { } while (0) /* Set the sysfs physical device reference for the network logical device * if set prior to registration will cause a symlink during initialization. */ #define SET_NETDEV_DEV(net, pdev) ((net)->dev.parent = (pdev)) +static inline void netif_napi_add(struct net_device *dev, + struct napi_struct *napi, + int (*poll)(struct napi_struct *, int), + int weight) +{ + INIT_LIST_HEAD(&napi->poll_list); + napi->poll = poll; + napi->weight = weight; +#ifdef CONFIG_NETPOLL + napi->dev = dev; + list_add(&napi->dev_list, &dev->napi_list); + spin_lock_init(&napi->poll_lock); + napi->poll_owner = -1; +#endif + set_bit(NAPI_STATE_SCHED, &napi->state); +} + struct packet_type { __be16 type; /* This is really htons(ether_type). */ struct net_device *dev; /* NULL is wildcarded here */ @@ -610,45 +753,46 @@ struct packet_type { #include <linux/interrupt.h> #include <linux/notifier.h> -extern struct net_device loopback_dev; /* The loopback */ -extern struct list_head dev_base_head; /* All devices */ extern rwlock_t dev_base_lock; /* Device list lock */ -#define for_each_netdev(d) \ - list_for_each_entry(d, &dev_base_head, dev_list) -#define for_each_netdev_safe(d, n) \ - list_for_each_entry_safe(d, n, &dev_base_head, dev_list) -#define for_each_netdev_continue(d) \ - list_for_each_entry_continue(d, &dev_base_head, dev_list) + +#define for_each_netdev(net, d) \ + list_for_each_entry(d, &(net)->dev_base_head, dev_list) +#define for_each_netdev_safe(net, d, n) \ + list_for_each_entry_safe(d, n, &(net)->dev_base_head, dev_list) +#define for_each_netdev_continue(net, d) \ + list_for_each_entry_continue(d, &(net)->dev_base_head, dev_list) #define net_device_entry(lh) list_entry(lh, struct net_device, dev_list) static inline struct net_device *next_net_device(struct net_device *dev) { struct list_head *lh; + struct net *net; + net = dev->nd_net; lh = dev->dev_list.next; - return lh == &dev_base_head ? NULL : net_device_entry(lh); + return lh == &net->dev_base_head ? NULL : net_device_entry(lh); } -static inline struct net_device *first_net_device(void) +static inline struct net_device *first_net_device(struct net *net) { - return list_empty(&dev_base_head) ? NULL : - net_device_entry(dev_base_head.next); + return list_empty(&net->dev_base_head) ? NULL : + net_device_entry(net->dev_base_head.next); } extern int netdev_boot_setup_check(struct net_device *dev); extern unsigned long netdev_boot_base(const char *prefix, int unit); -extern struct net_device *dev_getbyhwaddr(unsigned short type, char *hwaddr); -extern struct net_device *dev_getfirstbyhwtype(unsigned short type); -extern struct net_device *__dev_getfirstbyhwtype(unsigned short type); +extern struct net_device *dev_getbyhwaddr(struct net *net, unsigned short type, char *hwaddr); +extern struct net_device *dev_getfirstbyhwtype(struct net *net, unsigned short type); +extern struct net_device *__dev_getfirstbyhwtype(struct net *net, unsigned short type); extern void dev_add_pack(struct packet_type *pt); extern void dev_remove_pack(struct packet_type *pt); extern void __dev_remove_pack(struct packet_type *pt); -extern struct net_device *dev_get_by_flags(unsigned short flags, +extern struct net_device *dev_get_by_flags(struct net *net, unsigned short flags, unsigned short mask); -extern struct net_device *dev_get_by_name(const char *name); -extern struct net_device *__dev_get_by_name(const char *name); +extern struct net_device *dev_get_by_name(struct net *net, const char *name); +extern struct net_device *__dev_get_by_name(struct net *net, const char *name); extern int dev_alloc_name(struct net_device *dev, const char *name); extern int dev_open(struct net_device *dev); extern int dev_close(struct net_device *dev); @@ -659,14 +803,35 @@ extern void free_netdev(struct net_device *dev); extern void synchronize_net(void); extern int register_netdevice_notifier(struct notifier_block *nb); extern int unregister_netdevice_notifier(struct notifier_block *nb); -extern int call_netdevice_notifiers(unsigned long val, void *v); -extern struct net_device *dev_get_by_index(int ifindex); -extern struct net_device *__dev_get_by_index(int ifindex); +extern int call_netdevice_notifiers(unsigned long val, struct net_device *dev); +extern struct net_device *dev_get_by_index(struct net *net, int ifindex); +extern struct net_device *__dev_get_by_index(struct net *net, int ifindex); extern int dev_restart(struct net_device *dev); #ifdef CONFIG_NETPOLL_TRAP extern int netpoll_trap(void); #endif +static inline int dev_hard_header(struct sk_buff *skb, struct net_device *dev, + unsigned short type, + const void *daddr, const void *saddr, + unsigned len) +{ + if (!dev->header_ops) + return 0; + + return dev->header_ops->create(skb, dev, type, daddr, saddr, len); +} + +static inline int dev_parse_header(const struct sk_buff *skb, + unsigned char *haddr) +{ + const struct net_device *dev = skb->dev; + + if (!dev->header_ops->parse) + return 0; + return dev->header_ops->parse(skb, haddr); +} + typedef int gifconf_func_t(struct net_device * dev, char __user * bufptr, int len); extern int register_gifconf(unsigned int family, gifconf_func_t * gifconf); static inline int unregister_gifconf(unsigned int family) @@ -678,7 +843,6 @@ static inline int unregister_gifconf(unsigned int family) * Incoming packets are placed on per-cpu queues so that * no locking is needed. */ - struct softnet_data { struct net_device *output_queue; @@ -686,7 +850,7 @@ struct softnet_data struct list_head poll_list; struct sk_buff *completion_queue; - struct net_device backlog_dev; /* Sorry. 8) */ + struct napi_struct backlog; #ifdef CONFIG_NET_DMA struct dma_chan *net_dma; #endif @@ -704,11 +868,24 @@ static inline void netif_schedule(struct net_device *dev) __netif_schedule(dev); } +/** + * netif_start_queue - allow transmit + * @dev: network device + * + * Allow upper layers to call the device hard_start_xmit routine. + */ static inline void netif_start_queue(struct net_device *dev) { clear_bit(__LINK_STATE_XOFF, &dev->state); } +/** + * netif_wake_queue - restart transmit + * @dev: network device + * + * Allow upper layers to call the device hard_start_xmit routine. + * Used for flow control when transmit resources are available. + */ static inline void netif_wake_queue(struct net_device *dev) { #ifdef CONFIG_NETPOLL_TRAP @@ -721,16 +898,35 @@ static inline void netif_wake_queue(struct net_device *dev) __netif_schedule(dev); } +/** + * netif_stop_queue - stop transmitted packets + * @dev: network device + * + * Stop upper layers calling the device hard_start_xmit routine. + * Used for flow control when transmit resources are unavailable. + */ static inline void netif_stop_queue(struct net_device *dev) { set_bit(__LINK_STATE_XOFF, &dev->state); } +/** + * netif_queue_stopped - test if transmit queue is flowblocked + * @dev: network device + * + * Test if transmit queue on device is currently unable to send. + */ static inline int netif_queue_stopped(const struct net_device *dev) { return test_bit(__LINK_STATE_XOFF, &dev->state); } +/** + * netif_running - test if up + * @dev: network device + * + * Test if the device has been brought up. + */ static inline int netif_running(const struct net_device *dev) { return test_bit(__LINK_STATE_START, &dev->state); @@ -742,6 +938,14 @@ static inline int netif_running(const struct net_device *dev) * done at the overall netdevice level. * Also test the device if we're multiqueue. */ + +/** + * netif_start_subqueue - allow sending packets on subqueue + * @dev: network device + * @queue_index: sub queue index + * + * Start individual transmit queue of a device with multiple transmit queues. + */ static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) { #ifdef CONFIG_NETDEVICES_MULTIQUEUE @@ -749,6 +953,13 @@ static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) #endif } +/** + * netif_stop_subqueue - stop sending packets on subqueue + * @dev: network device + * @queue_index: sub queue index + * + * Stop individual transmit queue of a device with multiple transmit queues. + */ static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) { #ifdef CONFIG_NETDEVICES_MULTIQUEUE @@ -760,6 +971,13 @@ static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) #endif } +/** + * netif_subqueue_stopped - test status of subqueue + * @dev: network device + * @queue_index: sub queue index + * + * Check individual transmit queue of a device with multiple transmit queues. + */ static inline int netif_subqueue_stopped(const struct net_device *dev, u16 queue_index) { @@ -771,6 +989,14 @@ static inline int netif_subqueue_stopped(const struct net_device *dev, #endif } + +/** + * netif_wake_subqueue - allow sending packets on subqueue + * @dev: network device + * @queue_index: sub queue index + * + * Resume individual transmit queue of a device with multiple transmit queues. + */ static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) { #ifdef CONFIG_NETDEVICES_MULTIQUEUE @@ -784,6 +1010,13 @@ static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) #endif } +/** + * netif_is_multiqueue - test if device has multiple transmit queues + * @dev: network device + * + * Check if device has multiple transmit queues + * Always falls if NETDEVICE_MULTIQUEUE is not configured + */ static inline int netif_is_multiqueue(const struct net_device *dev) { #ifdef CONFIG_NETDEVICES_MULTIQUEUE @@ -796,20 +1029,7 @@ static inline int netif_is_multiqueue(const struct net_device *dev) /* Use this variant when it is known for sure that it * is executing from interrupt context. */ -static inline void dev_kfree_skb_irq(struct sk_buff *skb) -{ - if (atomic_dec_and_test(&skb->users)) { - struct softnet_data *sd; - unsigned long flags; - - local_irq_save(flags); - sd = &__get_cpu_var(softnet_data); - skb->next = sd->completion_queue; - sd->completion_queue = skb; - raise_softirq_irqoff(NET_TX_SOFTIRQ); - local_irq_restore(flags); - } -} +extern void dev_kfree_skb_irq(struct sk_buff *skb); /* Use this variant in places where it could be invoked * either from interrupt or non-interrupt context. @@ -822,29 +1042,41 @@ extern int netif_rx_ni(struct sk_buff *skb); #define HAVE_NETIF_RECEIVE_SKB 1 extern int netif_receive_skb(struct sk_buff *skb); extern int dev_valid_name(const char *name); -extern int dev_ioctl(unsigned int cmd, void __user *); -extern int dev_ethtool(struct ifreq *); +extern int dev_ioctl(struct net *net, unsigned int cmd, void __user *); +extern int dev_ethtool(struct net *net, struct ifreq *); extern unsigned dev_get_flags(const struct net_device *); extern int dev_change_flags(struct net_device *, unsigned); extern int dev_change_name(struct net_device *, char *); +extern int dev_change_net_namespace(struct net_device *, + struct net *, const char *); extern int dev_set_mtu(struct net_device *, int); extern int dev_set_mac_address(struct net_device *, struct sockaddr *); extern int dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev); -extern void dev_init(void); - extern int netdev_budget; /* Called by rtnetlink.c:rtnl_unlock() */ extern void netdev_run_todo(void); +/** + * dev_put - release reference to device + * @dev: network device + * + * Release reference to device to allow it to be freed. + */ static inline void dev_put(struct net_device *dev) { atomic_dec(&dev->refcnt); } +/** + * dev_hold - get reference to device + * @dev: network device + * + * Hold reference to device to keep it from being freed. + */ static inline void dev_hold(struct net_device *dev) { atomic_inc(&dev->refcnt); @@ -861,6 +1093,12 @@ static inline void dev_hold(struct net_device *dev) extern void linkwatch_fire_event(struct net_device *dev); +/** + * netif_carrier_ok - test if carrier present + * @dev: network device + * + * Check if carrier is present on device + */ static inline int netif_carrier_ok(const struct net_device *dev) { return !test_bit(__LINK_STATE_NOCARRIER, &dev->state); @@ -872,30 +1110,66 @@ extern void netif_carrier_on(struct net_device *dev); extern void netif_carrier_off(struct net_device *dev); +/** + * netif_dormant_on - mark device as dormant. + * @dev: network device + * + * Mark device as dormant (as per RFC2863). + * + * The dormant state indicates that the relevant interface is not + * actually in a condition to pass packets (i.e., it is not 'up') but is + * in a "pending" state, waiting for some external event. For "on- + * demand" interfaces, this new state identifies the situation where the + * interface is waiting for events to place it in the up state. + * + */ static inline void netif_dormant_on(struct net_device *dev) { if (!test_and_set_bit(__LINK_STATE_DORMANT, &dev->state)) linkwatch_fire_event(dev); } +/** + * netif_dormant_off - set device as not dormant. + * @dev: network device + * + * Device is not in dormant state. + */ static inline void netif_dormant_off(struct net_device *dev) { if (test_and_clear_bit(__LINK_STATE_DORMANT, &dev->state)) linkwatch_fire_event(dev); } +/** + * netif_dormant - test if carrier present + * @dev: network device + * + * Check if carrier is present on device + */ static inline int netif_dormant(const struct net_device *dev) { return test_bit(__LINK_STATE_DORMANT, &dev->state); } +/** + * netif_oper_up - test if device is operational + * @dev: network device + * + * Check if carrier is operational + */ static inline int netif_oper_up(const struct net_device *dev) { return (dev->operstate == IF_OPER_UP || dev->operstate == IF_OPER_UNKNOWN /* backward compat */); } -/* Hot-plugging. */ +/** + * netif_device_present - is device available or removed + * @dev: network device + * + * Check if device has not been removed from system. + */ static inline int netif_device_present(struct net_device *dev) { return test_bit(__LINK_STATE_PRESENT, &dev->state); @@ -955,46 +1229,38 @@ static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits) return (1 << debug_value) - 1; } -/* Test if receive needs to be scheduled */ -static inline int __netif_rx_schedule_prep(struct net_device *dev) -{ - return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state); -} - /* Test if receive needs to be scheduled but only if up */ -static inline int netif_rx_schedule_prep(struct net_device *dev) +static inline int netif_rx_schedule_prep(struct net_device *dev, + struct napi_struct *napi) { - return netif_running(dev) && __netif_rx_schedule_prep(dev); + return netif_running(dev) && napi_schedule_prep(napi); } /* Add interface to tail of rx poll list. This assumes that _prep has * already been called and returned 1. */ - -extern void __netif_rx_schedule(struct net_device *dev); +static inline void __netif_rx_schedule(struct net_device *dev, + struct napi_struct *napi) +{ + dev_hold(dev); + __napi_schedule(napi); +} /* Try to reschedule poll. Called by irq handler. */ -static inline void netif_rx_schedule(struct net_device *dev) +static inline void netif_rx_schedule(struct net_device *dev, + struct napi_struct *napi) { - if (netif_rx_schedule_prep(dev)) - __netif_rx_schedule(dev); + if (netif_rx_schedule_prep(dev, napi)) + __netif_rx_schedule(dev, napi); } -/* Try to reschedule poll. Called by dev->poll() after netif_rx_complete(). - * Do not inline this? - */ -static inline int netif_rx_reschedule(struct net_device *dev, int undo) +/* Try to reschedule poll. Called by dev->poll() after netif_rx_complete(). */ +static inline int netif_rx_reschedule(struct net_device *dev, + struct napi_struct *napi) { - if (netif_rx_schedule_prep(dev)) { - unsigned long flags; - - dev->quota += undo; - - local_irq_save(flags); - list_add_tail(&dev->poll_list, &__get_cpu_var(softnet_data).poll_list); - __raise_softirq_irqoff(NET_RX_SOFTIRQ); - local_irq_restore(flags); + if (napi_schedule_prep(napi)) { + __netif_rx_schedule(dev, napi); return 1; } return 0; @@ -1003,12 +1269,11 @@ static inline int netif_rx_reschedule(struct net_device *dev, int undo) /* same as netif_rx_complete, except that local_irq_save(flags) * has already been issued */ -static inline void __netif_rx_complete(struct net_device *dev) +static inline void __netif_rx_complete(struct net_device *dev, + struct napi_struct *napi) { - BUG_ON(!test_bit(__LINK_STATE_RX_SCHED, &dev->state)); - list_del(&dev->poll_list); - smp_mb__before_clear_bit(); - clear_bit(__LINK_STATE_RX_SCHED, &dev->state); + __napi_complete(napi); + dev_put(dev); } /* Remove interface from poll list: it must be in the poll list @@ -1016,32 +1281,31 @@ static inline void __netif_rx_complete(struct net_device *dev) * it completes the work. The device cannot be out of poll list at this * moment, it is BUG(). */ -static inline void netif_rx_complete(struct net_device *dev) +static inline void netif_rx_complete(struct net_device *dev, + struct napi_struct *napi) { unsigned long flags; local_irq_save(flags); - __netif_rx_complete(dev); + __netif_rx_complete(dev, napi); local_irq_restore(flags); } -static inline void netif_poll_disable(struct net_device *dev) -{ - while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) - /* No hurry. */ - schedule_timeout_interruptible(1); -} - -static inline void netif_poll_enable(struct net_device *dev) +/** + * netif_tx_lock - grab network device transmit lock + * @dev: network device + * + * Get network device transmit lock + */ +static inline void __netif_tx_lock(struct net_device *dev, int cpu) { - smp_mb__before_clear_bit(); - clear_bit(__LINK_STATE_RX_SCHED, &dev->state); + spin_lock(&dev->_xmit_lock); + dev->xmit_lock_owner = cpu; } static inline void netif_tx_lock(struct net_device *dev) { - spin_lock(&dev->_xmit_lock); - dev->xmit_lock_owner = smp_processor_id(); + __netif_tx_lock(dev, smp_processor_id()); } static inline void netif_tx_lock_bh(struct net_device *dev) @@ -1070,6 +1334,18 @@ static inline void netif_tx_unlock_bh(struct net_device *dev) spin_unlock_bh(&dev->_xmit_lock); } +#define HARD_TX_LOCK(dev, cpu) { \ + if ((dev->features & NETIF_F_LLTX) == 0) { \ + __netif_tx_lock(dev, cpu); \ + } \ +} + +#define HARD_TX_UNLOCK(dev) { \ + if ((dev->features & NETIF_F_LLTX) == 0) { \ + netif_tx_unlock(dev); \ + } \ +} + static inline void netif_tx_disable(struct net_device *dev) { netif_tx_lock_bh(dev); @@ -1098,16 +1374,14 @@ extern int dev_mc_delete(struct net_device *dev, void *addr, int alen, int all extern int dev_mc_add(struct net_device *dev, void *addr, int alen, int newonly); extern int dev_mc_sync(struct net_device *to, struct net_device *from); extern void dev_mc_unsync(struct net_device *to, struct net_device *from); -extern void dev_mc_discard(struct net_device *dev); extern int __dev_addr_delete(struct dev_addr_list **list, int *count, void *addr, int alen, int all); extern int __dev_addr_add(struct dev_addr_list **list, int *count, void *addr, int alen, int newonly); -extern void __dev_addr_discard(struct dev_addr_list **list); extern void dev_set_promiscuity(struct net_device *dev, int inc); extern void dev_set_allmulti(struct net_device *dev, int inc); extern void netdev_state_change(struct net_device *dev); extern void netdev_features_change(struct net_device *dev); /* Load a device via the kmod */ -extern void dev_load(const char *name); +extern void dev_load(struct net *net, const char *name); extern void dev_mcast_init(void); extern int netdev_max_backlog; extern int weight_p; @@ -1133,6 +1407,8 @@ extern void dev_seq_stop(struct seq_file *seq, void *v); extern void linkwatch_run_queue(void); +extern int netdev_compute_features(unsigned long all, unsigned long one); + static inline int net_gso_ok(int features, int gso_type) { int feature = gso_type << NETIF_F_GSO_SHIFT; diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 0eed0b7ab2df..1dd075eda595 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -88,9 +88,8 @@ struct nf_sockopt_ops int (*compat_get)(struct sock *sk, int optval, void __user *user, int *len); - /* Number of users inside set() or get(). */ - unsigned int use; - struct task_struct *cleanup_task; + /* Use the module struct to lock set/get code in place */ + struct module *owner; }; /* Each queued (to userspace) skbuff has one of these. */ diff --git a/include/linux/netfilter/Kbuild b/include/linux/netfilter/Kbuild index 43397a414cd6..f2eaea2234ec 100644 --- a/include/linux/netfilter/Kbuild +++ b/include/linux/netfilter/Kbuild @@ -28,6 +28,7 @@ header-y += xt_policy.h header-y += xt_realm.h header-y += xt_sctp.h header-y += xt_state.h +header-y += xt_statistic.h header-y += xt_string.h header-y += xt_tcpmss.h header-y += xt_tcpudp.h @@ -39,5 +40,6 @@ unifdef-y += nf_conntrack_common.h unifdef-y += nf_conntrack_ftp.h unifdef-y += nf_conntrack_tcp.h unifdef-y += nfnetlink.h +unifdef-y += nfnetlink_compat.h unifdef-y += x_tables.h unifdef-y += xt_physdev.h diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h index 0f9311df1559..0d8424f76899 100644 --- a/include/linux/netfilter/nfnetlink.h +++ b/include/linux/netfilter/nfnetlink.h @@ -1,16 +1,7 @@ #ifndef _NFNETLINK_H #define _NFNETLINK_H #include <linux/types.h> - -#ifndef __KERNEL__ -/* nfnetlink groups: Up to 32 maximum - backwards compatibility for userspace */ -#define NF_NETLINK_CONNTRACK_NEW 0x00000001 -#define NF_NETLINK_CONNTRACK_UPDATE 0x00000002 -#define NF_NETLINK_CONNTRACK_DESTROY 0x00000004 -#define NF_NETLINK_CONNTRACK_EXP_NEW 0x00000008 -#define NF_NETLINK_CONNTRACK_EXP_UPDATE 0x00000010 -#define NF_NETLINK_CONNTRACK_EXP_DESTROY 0x00000020 -#endif +#include <linux/netfilter/nfnetlink_compat.h> enum nfnetlink_groups { NFNLGRP_NONE, @@ -31,48 +22,6 @@ enum nfnetlink_groups { }; #define NFNLGRP_MAX (__NFNLGRP_MAX - 1) -/* Generic structure for encapsulation optional netfilter information. - * It is reminiscent of sockaddr, but with sa_family replaced - * with attribute type. - * ! This should someday be put somewhere generic as now rtnetlink and - * ! nfnetlink use the same attributes methods. - J. Schulist. - */ - -struct nfattr -{ - u_int16_t nfa_len; - u_int16_t nfa_type; /* we use 15 bits for the type, and the highest - * bit to indicate whether the payload is nested */ -}; - -/* FIXME: Apart from NFNL_NFA_NESTED shamelessly copy and pasted from - * rtnetlink.h, it's time to put this in a generic file */ - -#define NFNL_NFA_NEST 0x8000 -#define NFA_TYPE(attr) ((attr)->nfa_type & 0x7fff) - -#define NFA_ALIGNTO 4 -#define NFA_ALIGN(len) (((len) + NFA_ALIGNTO - 1) & ~(NFA_ALIGNTO - 1)) -#define NFA_OK(nfa,len) ((len) > 0 && (nfa)->nfa_len >= sizeof(struct nfattr) \ - && (nfa)->nfa_len <= (len)) -#define NFA_NEXT(nfa,attrlen) ((attrlen) -= NFA_ALIGN((nfa)->nfa_len), \ - (struct nfattr *)(((char *)(nfa)) + NFA_ALIGN((nfa)->nfa_len))) -#define NFA_LENGTH(len) (NFA_ALIGN(sizeof(struct nfattr)) + (len)) -#define NFA_SPACE(len) NFA_ALIGN(NFA_LENGTH(len)) -#define NFA_DATA(nfa) ((void *)(((char *)(nfa)) + NFA_LENGTH(0))) -#define NFA_PAYLOAD(nfa) ((int)((nfa)->nfa_len) - NFA_LENGTH(0)) -#define NFA_NEST(skb, type) \ -({ struct nfattr *__start = (struct nfattr *)skb_tail_pointer(skb); \ - NFA_PUT(skb, (NFNL_NFA_NEST | type), 0, NULL); \ - __start; }) -#define NFA_NEST_END(skb, start) \ -({ (start)->nfa_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ - (skb)->len; }) -#define NFA_NEST_CANCEL(skb, start) \ -({ if (start) \ - skb_trim(skb, (unsigned char *) (start) - (skb)->data); \ - -1; }) - /* General form of address family dependent message. */ struct nfgenmsg { @@ -83,10 +32,6 @@ struct nfgenmsg { #define NFNETLINK_V0 0 -#define NFM_NFA(n) ((struct nfattr *)(((char *)(n)) \ - + NLMSG_ALIGN(sizeof(struct nfgenmsg)))) -#define NFM_PAYLOAD(n) NLMSG_PAYLOAD(n, sizeof(struct nfgenmsg)) - /* netfilter netlink message types are split in two pieces: * 8 bit subsystem, 8bit operation. */ @@ -107,49 +52,26 @@ struct nfgenmsg { #include <linux/netlink.h> #include <linux/capability.h> +#include <net/netlink.h> struct nfnl_callback { int (*call)(struct sock *nl, struct sk_buff *skb, - struct nlmsghdr *nlh, struct nfattr *cda[]); - u_int16_t attr_count; /* number of nfattr's */ + struct nlmsghdr *nlh, struct nlattr *cda[]); + const struct nla_policy *policy; /* netlink attribute policy */ + const u_int16_t attr_count; /* number of nlattr's */ }; struct nfnetlink_subsystem { const char *name; - __u8 subsys_id; /* nfnetlink subsystem ID */ - __u8 cb_count; /* number of callbacks */ - struct nfnl_callback *cb; /* callback for individual types */ + __u8 subsys_id; /* nfnetlink subsystem ID */ + __u8 cb_count; /* number of callbacks */ + const struct nfnl_callback *cb; /* callback for individual types */ }; -extern void __nfa_fill(struct sk_buff *skb, int attrtype, - int attrlen, const void *data); -#define NFA_PUT(skb, attrtype, attrlen, data) \ -({ if (skb_tailroom(skb) < (int)NFA_SPACE(attrlen)) goto nfattr_failure; \ - __nfa_fill(skb, attrtype, attrlen, data); }) - -extern int nfnetlink_subsys_register(struct nfnetlink_subsystem *n); -extern int nfnetlink_subsys_unregister(struct nfnetlink_subsystem *n); - -extern void nfattr_parse(struct nfattr *tb[], int maxattr, - struct nfattr *nfa, int len); - -#define nfattr_parse_nested(tb, max, nfa) \ - nfattr_parse((tb), (max), NFA_DATA((nfa)), NFA_PAYLOAD((nfa))) - -#define nfattr_bad_size(tb, max, cta_min) \ -({ int __i, __res = 0; \ - for (__i=0; __i<max; __i++) { \ - if (!cta_min[__i]) \ - continue; \ - if (tb[__i] && NFA_PAYLOAD(tb[__i]) < cta_min[__i]){ \ - __res = 1; \ - break; \ - } \ - } \ - __res; \ -}) +extern int nfnetlink_subsys_register(const struct nfnetlink_subsystem *n); +extern int nfnetlink_subsys_unregister(const struct nfnetlink_subsystem *n); extern int nfnetlink_has_listeners(unsigned int group); extern int nfnetlink_send(struct sk_buff *skb, u32 pid, unsigned group, diff --git a/include/linux/netfilter/nfnetlink_compat.h b/include/linux/netfilter/nfnetlink_compat.h new file mode 100644 index 000000000000..02a42d875cf7 --- /dev/null +++ b/include/linux/netfilter/nfnetlink_compat.h @@ -0,0 +1,61 @@ +#ifndef _NFNETLINK_COMPAT_H +#define _NFNETLINK_COMPAT_H +#ifndef __KERNEL +/* Old nfnetlink macros for userspace */ + +/* nfnetlink groups: Up to 32 maximum */ +#define NF_NETLINK_CONNTRACK_NEW 0x00000001 +#define NF_NETLINK_CONNTRACK_UPDATE 0x00000002 +#define NF_NETLINK_CONNTRACK_DESTROY 0x00000004 +#define NF_NETLINK_CONNTRACK_EXP_NEW 0x00000008 +#define NF_NETLINK_CONNTRACK_EXP_UPDATE 0x00000010 +#define NF_NETLINK_CONNTRACK_EXP_DESTROY 0x00000020 + +/* Generic structure for encapsulation optional netfilter information. + * It is reminiscent of sockaddr, but with sa_family replaced + * with attribute type. + * ! This should someday be put somewhere generic as now rtnetlink and + * ! nfnetlink use the same attributes methods. - J. Schulist. + */ + +struct nfattr +{ + u_int16_t nfa_len; + u_int16_t nfa_type; /* we use 15 bits for the type, and the highest + * bit to indicate whether the payload is nested */ +}; + +/* FIXME: Apart from NFNL_NFA_NESTED shamelessly copy and pasted from + * rtnetlink.h, it's time to put this in a generic file */ + +#define NFNL_NFA_NEST 0x8000 +#define NFA_TYPE(attr) ((attr)->nfa_type & 0x7fff) + +#define NFA_ALIGNTO 4 +#define NFA_ALIGN(len) (((len) + NFA_ALIGNTO - 1) & ~(NFA_ALIGNTO - 1)) +#define NFA_OK(nfa,len) ((len) > 0 && (nfa)->nfa_len >= sizeof(struct nfattr) \ + && (nfa)->nfa_len <= (len)) +#define NFA_NEXT(nfa,attrlen) ((attrlen) -= NFA_ALIGN((nfa)->nfa_len), \ + (struct nfattr *)(((char *)(nfa)) + NFA_ALIGN((nfa)->nfa_len))) +#define NFA_LENGTH(len) (NFA_ALIGN(sizeof(struct nfattr)) + (len)) +#define NFA_SPACE(len) NFA_ALIGN(NFA_LENGTH(len)) +#define NFA_DATA(nfa) ((void *)(((char *)(nfa)) + NFA_LENGTH(0))) +#define NFA_PAYLOAD(nfa) ((int)((nfa)->nfa_len) - NFA_LENGTH(0)) +#define NFA_NEST(skb, type) \ +({ struct nfattr *__start = (struct nfattr *)skb_tail_pointer(skb); \ + NFA_PUT(skb, (NFNL_NFA_NEST | type), 0, NULL); \ + __start; }) +#define NFA_NEST_END(skb, start) \ +({ (start)->nfa_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ + (skb)->len; }) +#define NFA_NEST_CANCEL(skb, start) \ +({ if (start) \ + skb_trim(skb, (unsigned char *) (start) - (skb)->data); \ + -1; }) + +#define NFM_NFA(n) ((struct nfattr *)(((char *)(n)) \ + + NLMSG_ALIGN(sizeof(struct nfgenmsg)))) +#define NFM_PAYLOAD(n) NLMSG_PAYLOAD(n, sizeof(struct nfgenmsg)) + +#endif /* ! __KERNEL__ */ +#endif /* _NFNETLINK_COMPAT_H */ diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h index d7c35039721e..4affa3fe78e0 100644 --- a/include/linux/netfilter/nfnetlink_conntrack.h +++ b/include/linux/netfilter/nfnetlink_conntrack.h @@ -36,6 +36,7 @@ enum ctattr_type { CTA_USE, CTA_ID, CTA_NAT_DST, + CTA_TUPLE_MASTER, __CTA_MAX }; #define CTA_MAX (__CTA_MAX - 1) diff --git a/include/linux/netfilter/xt_connlimit.h b/include/linux/netfilter/xt_connlimit.h index 90ae8b474cb8..37e933c9987d 100644 --- a/include/linux/netfilter/xt_connlimit.h +++ b/include/linux/netfilter/xt_connlimit.h @@ -5,8 +5,8 @@ struct xt_connlimit_data; struct xt_connlimit_info { union { - u_int32_t v4_mask; - u_int32_t v6_mask[4]; + __be32 v4_mask; + __be32 v6_mask[4]; }; unsigned int limit, inverse; diff --git a/include/linux/netfilter/xt_time.h b/include/linux/netfilter/xt_time.h new file mode 100644 index 000000000000..14b6df412c9f --- /dev/null +++ b/include/linux/netfilter/xt_time.h @@ -0,0 +1,25 @@ +#ifndef _XT_TIME_H +#define _XT_TIME_H 1 + +struct xt_time_info { + u_int32_t date_start; + u_int32_t date_stop; + u_int32_t daytime_start; + u_int32_t daytime_stop; + u_int32_t monthdays_match; + u_int8_t weekdays_match; + u_int8_t flags; +}; + +enum { + /* Match against local time (instead of UTC) */ + XT_TIME_LOCAL_TZ = 1 << 0, + + /* Shortcuts */ + XT_TIME_ALL_MONTHDAYS = 0xFFFFFFFE, + XT_TIME_ALL_WEEKDAYS = 0xFE, + XT_TIME_MIN_DAYTIME = 0, + XT_TIME_MAX_DAYTIME = 24 * 60 * 60 - 1, +}; + +#endif /* _XT_TIME_H */ diff --git a/include/linux/netfilter_ipv4/ipt_iprange.h b/include/linux/netfilter_ipv4/ipt_iprange.h index 34ab0fb736e2..a92fefc3c7ec 100644 --- a/include/linux/netfilter_ipv4/ipt_iprange.h +++ b/include/linux/netfilter_ipv4/ipt_iprange.h @@ -1,6 +1,8 @@ #ifndef _IPT_IPRANGE_H #define _IPT_IPRANGE_H +#include <linux/types.h> + #define IPRANGE_SRC 0x01 /* Match source IP address */ #define IPRANGE_DST 0x02 /* Match destination IP address */ #define IPRANGE_SRC_INV 0x10 /* Negate the condition */ diff --git a/include/linux/netlink.h b/include/linux/netlink.h index 2e23353c28a5..7c1f3b1d2ee5 100644 --- a/include/linux/netlink.h +++ b/include/linux/netlink.h @@ -27,6 +27,8 @@ #define MAX_LINKS 32 +struct net; + struct sockaddr_nl { sa_family_t nl_family; /* AF_NETLINK */ @@ -129,6 +131,20 @@ struct nlattr __u16 nla_type; }; +/* + * nla_type (16 bits) + * +---+---+-------------------------------+ + * | N | O | Attribute Type | + * +---+---+-------------------------------+ + * N := Carries nested attributes + * O := Payload stored in network byte order + * + * Note: The N and O flag are mutually exclusive. + */ +#define NLA_F_NESTED (1 << 15) +#define NLA_F_NET_BYTEORDER (1 << 14) +#define NLA_TYPE_MASK ~(NLA_F_NESTED | NLA_F_NET_BYTEORDER) + #define NLA_ALIGNTO 4 #define NLA_ALIGN(len) (((len) + NLA_ALIGNTO - 1) & ~(NLA_ALIGNTO - 1)) #define NLA_HDRLEN ((int) NLA_ALIGN(sizeof(struct nlattr))) @@ -157,10 +173,13 @@ struct netlink_skb_parms #define NETLINK_CREDS(skb) (&NETLINK_CB((skb)).creds) -extern struct sock *netlink_kernel_create(int unit, unsigned int groups, - void (*input)(struct sock *sk, int len), +extern struct sock *netlink_kernel_create(struct net *net, + int unit,unsigned int groups, + void (*input)(struct sk_buff *skb), struct mutex *cb_mutex, struct module *module); +extern int netlink_change_ngroups(struct sock *sk, unsigned int groups); +extern void netlink_clear_multicast_users(struct sock *sk, unsigned int group); extern void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err); extern int netlink_has_listeners(struct sock *sk, unsigned int group); extern int netlink_unicast(struct sock *ssk, struct sk_buff *skb, __u32 pid, int nonblock); @@ -175,7 +194,7 @@ struct sock *netlink_getsockbyfilp(struct file *filp); int netlink_attachskb(struct sock *sk, struct sk_buff *skb, int nonblock, long timeo, struct sock *ssk); void netlink_detachskb(struct sock *sk, struct sk_buff *skb); -int netlink_sendskb(struct sock *sk, struct sk_buff *skb, int protocol); +int netlink_sendskb(struct sock *sk, struct sk_buff *skb); /* * skb should fit one page. This choice is good for headerless malloc. @@ -204,6 +223,7 @@ struct netlink_callback struct netlink_notify { + struct net *net; int pid; int protocol; }; diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h index 29930b71a9aa..20250d963d72 100644 --- a/include/linux/netpoll.h +++ b/include/linux/netpoll.h @@ -25,8 +25,6 @@ struct netpoll { struct netpoll_info { atomic_t refcnt; - spinlock_t poll_lock; - int poll_owner; int rx_flags; spinlock_t rx_lock; struct netpoll *rx_np; /* netpoll that registered an rx_hook */ @@ -37,6 +35,7 @@ struct netpoll_info { void netpoll_poll(struct netpoll *np); void netpoll_send_udp(struct netpoll *np, const char *msg, int len); +void netpoll_print_options(struct netpoll *np); int netpoll_parse_options(struct netpoll *np, char *opt); int netpoll_setup(struct netpoll *np); int netpoll_trap(void); @@ -64,32 +63,61 @@ static inline int netpoll_rx(struct sk_buff *skb) return ret; } -static inline void *netpoll_poll_lock(struct net_device *dev) +static inline int netpoll_receive_skb(struct sk_buff *skb) { + if (!list_empty(&skb->dev->napi_list)) + return netpoll_rx(skb); + return 0; +} + +static inline void *netpoll_poll_lock(struct napi_struct *napi) +{ + struct net_device *dev = napi->dev; + rcu_read_lock(); /* deal with race on ->npinfo */ - if (dev->npinfo) { - spin_lock(&dev->npinfo->poll_lock); - dev->npinfo->poll_owner = smp_processor_id(); - return dev->npinfo; + if (dev && dev->npinfo) { + spin_lock(&napi->poll_lock); + napi->poll_owner = smp_processor_id(); + return napi; } return NULL; } static inline void netpoll_poll_unlock(void *have) { - struct netpoll_info *npi = have; + struct napi_struct *napi = have; - if (npi) { - npi->poll_owner = -1; - spin_unlock(&npi->poll_lock); + if (napi) { + napi->poll_owner = -1; + spin_unlock(&napi->poll_lock); } rcu_read_unlock(); } +static inline void netpoll_netdev_init(struct net_device *dev) +{ + INIT_LIST_HEAD(&dev->napi_list); +} + #else -#define netpoll_rx(a) 0 -#define netpoll_poll_lock(a) NULL -#define netpoll_poll_unlock(a) +static inline int netpoll_rx(struct sk_buff *skb) +{ + return 0; +} +static inline int netpoll_receive_skb(struct sk_buff *skb) +{ + return 0; +} +static inline void *netpoll_poll_lock(struct napi_struct *napi) +{ + return NULL; +} +static inline void netpoll_poll_unlock(void *have) +{ +} +static inline void netpoll_netdev_init(struct net_device *dev) +{ +} #endif #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index c098ae194f79..7250eeadd7b5 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -71,7 +71,7 @@ struct nfs_access_entry { struct nfs4_state; struct nfs_open_context { - struct kref kref; + atomic_t count; struct path path; struct rpc_cred *cred; struct nfs4_state *state; @@ -407,8 +407,8 @@ extern void nfs_release_automount_timer(void); /* * linux/fs/nfs/unlink.c */ -extern int nfs_async_unlink(struct dentry *); -extern void nfs_complete_unlink(struct dentry *); +extern int nfs_async_unlink(struct inode *dir, struct dentry *dentry); +extern void nfs_complete_unlink(struct dentry *dentry, struct inode *); /* * linux/fs/nfs/write.c @@ -431,6 +431,7 @@ extern int nfs_sync_mapping_range(struct address_space *, loff_t, loff_t, int); extern int nfs_wb_all(struct inode *inode); extern int nfs_wb_page(struct inode *inode, struct page* page); extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how); +extern int nfs_wb_page_cancel(struct inode *inode, struct page* page); #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) extern int nfs_commit_inode(struct inode *, int); extern struct nfs_write_data *nfs_commit_alloc(void); diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 38d77681cf27..cf74a4db84a5 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -278,6 +278,21 @@ struct nfs_writeres { }; /* + * Common arguments to the unlink call + */ +struct nfs_removeargs { + const struct nfs_fh *fh; + struct qstr name; + const u32 * bitmask; +}; + +struct nfs_removeres { + const struct nfs_server *server; + struct nfs4_change_info cinfo; + struct nfs_fattr dir_attr; +}; + +/* * Argument struct for decode_entry function */ struct nfs_entry { @@ -631,18 +646,6 @@ struct nfs4_readlink { struct page ** pages; /* zero-copy data */ }; -struct nfs4_remove_arg { - const struct nfs_fh * fh; - const struct qstr * name; - const u32 * bitmask; -}; - -struct nfs4_remove_res { - const struct nfs_server * server; - struct nfs4_change_info cinfo; - struct nfs_fattr * dir_attr; -}; - struct nfs4_rename_arg { const struct nfs_fh * old_dir; const struct nfs_fh * new_dir; @@ -788,9 +791,8 @@ struct nfs_rpc_ops { int (*create) (struct inode *, struct dentry *, struct iattr *, int, struct nameidata *); int (*remove) (struct inode *, struct qstr *); - int (*unlink_setup) (struct rpc_message *, - struct dentry *, struct qstr *); - int (*unlink_done) (struct dentry *, struct rpc_task *); + void (*unlink_setup) (struct rpc_message *, struct inode *dir); + int (*unlink_done) (struct rpc_task *, struct inode *); int (*rename) (struct inode *, struct qstr *, struct inode *, struct qstr *); int (*link) (struct inode *, struct inode *, struct qstr *); diff --git a/include/linux/nfsd/export.h b/include/linux/nfsd/export.h index 78feb7beff75..5cd192469096 100644 --- a/include/linux/nfsd/export.h +++ b/include/linux/nfsd/export.h @@ -116,18 +116,7 @@ struct svc_expkey { #define EX_NOHIDE(exp) ((exp)->ex_flags & NFSEXP_NOHIDE) #define EX_WGATHER(exp) ((exp)->ex_flags & NFSEXP_GATHERED_WRITES) -static inline int EX_RDONLY(struct svc_export *exp, struct svc_rqst *rqstp) -{ - struct exp_flavor_info *f; - struct exp_flavor_info *end = exp->ex_flavors + exp->ex_nflavors; - - for (f = exp->ex_flavors; f < end; f++) { - if (f->pseudoflavor == rqstp->rq_flavor) - return f->flags & NFSEXP_READONLY; - } - return exp->ex_flags & NFSEXP_READONLY; -} - +int nfsexp_flags(struct svc_rqst *rqstp, struct svc_export *exp); __be32 check_nfsd_access(struct svc_export *exp, struct svc_rqst *rqstp); /* diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h index 9a30ba2ca75e..538ee1dd3d0a 100644 --- a/include/linux/nl80211.h +++ b/include/linux/nl80211.h @@ -7,7 +7,97 @@ */ /** + * enum nl80211_commands - supported nl80211 commands + * + * @NL80211_CMD_UNSPEC: unspecified command to catch errors + * + * @NL80211_CMD_GET_WIPHY: request information about a wiphy or dump request + * to get a list of all present wiphys. + * @NL80211_CMD_SET_WIPHY: set wiphy name, needs %NL80211_ATTR_WIPHY and + * %NL80211_ATTR_WIPHY_NAME. + * @NL80211_CMD_NEW_WIPHY: Newly created wiphy, response to get request + * or rename notification. Has attributes %NL80211_ATTR_WIPHY and + * %NL80211_ATTR_WIPHY_NAME. + * @NL80211_CMD_DEL_WIPHY: Wiphy deleted. Has attributes + * %NL80211_ATTR_WIPHY and %NL80211_ATTR_WIPHY_NAME. + * + * @NL80211_CMD_GET_INTERFACE: Request an interface's configuration; + * either a dump request on a %NL80211_ATTR_WIPHY or a specific get + * on an %NL80211_ATTR_IFINDEX is supported. + * @NL80211_CMD_SET_INTERFACE: Set type of a virtual interface, requires + * %NL80211_ATTR_IFINDEX and %NL80211_ATTR_IFTYPE. + * @NL80211_CMD_NEW_INTERFACE: Newly created virtual interface or response + * to %NL80211_CMD_GET_INTERFACE. Has %NL80211_ATTR_IFINDEX, + * %NL80211_ATTR_WIPHY and %NL80211_ATTR_IFTYPE attributes. Can also + * be sent from userspace to request creation of a new virtual interface, + * then requires attributes %NL80211_ATTR_WIPHY, %NL80211_ATTR_IFTYPE and + * %NL80211_ATTR_IFNAME. + * @NL80211_CMD_DEL_INTERFACE: Virtual interface was deleted, has attributes + * %NL80211_ATTR_IFINDEX and %NL80211_ATTR_WIPHY. Can also be sent from + * userspace to request deletion of a virtual interface, then requires + * attribute %NL80211_ATTR_IFINDEX. + * + * @NL80211_CMD_MAX: highest used command number + * @__NL80211_CMD_AFTER_LAST: internal use + */ +enum nl80211_commands { +/* don't change the order or add anything inbetween, this is ABI! */ + NL80211_CMD_UNSPEC, + + NL80211_CMD_GET_WIPHY, /* can dump */ + NL80211_CMD_SET_WIPHY, + NL80211_CMD_NEW_WIPHY, + NL80211_CMD_DEL_WIPHY, + + NL80211_CMD_GET_INTERFACE, /* can dump */ + NL80211_CMD_SET_INTERFACE, + NL80211_CMD_NEW_INTERFACE, + NL80211_CMD_DEL_INTERFACE, + + /* add commands here */ + + /* used to define NL80211_CMD_MAX below */ + __NL80211_CMD_AFTER_LAST, + NL80211_CMD_MAX = __NL80211_CMD_AFTER_LAST - 1 +}; + + +/** + * enum nl80211_attrs - nl80211 netlink attributes + * + * @NL80211_ATTR_UNSPEC: unspecified attribute to catch errors + * + * @NL80211_ATTR_WIPHY: index of wiphy to operate on, cf. + * /sys/class/ieee80211/<phyname>/index + * @NL80211_ATTR_WIPHY_NAME: wiphy name (used for renaming) + * + * @NL80211_ATTR_IFINDEX: network interface index of the device to operate on + * @NL80211_ATTR_IFNAME: network interface name + * @NL80211_ATTR_IFTYPE: type of virtual interface, see &enum nl80211_iftype + * + * @NL80211_ATTR_MAX: highest attribute number currently defined + * @__NL80211_ATTR_AFTER_LAST: internal use + */ +enum nl80211_attrs { +/* don't change the order or add anything inbetween, this is ABI! */ + NL80211_ATTR_UNSPEC, + + NL80211_ATTR_WIPHY, + NL80211_ATTR_WIPHY_NAME, + + NL80211_ATTR_IFINDEX, + NL80211_ATTR_IFNAME, + NL80211_ATTR_IFTYPE, + + /* add attributes here, update the policy in nl80211.c */ + + __NL80211_ATTR_AFTER_LAST, + NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1 +}; + +/** * enum nl80211_iftype - (virtual) interface types + * * @NL80211_IFTYPE_UNSPECIFIED: unspecified type, driver decides * @NL80211_IFTYPE_ADHOC: independent BSS member * @NL80211_IFTYPE_STATION: managed BSS member @@ -15,9 +105,10 @@ * @NL80211_IFTYPE_AP_VLAN: VLAN interface for access points * @NL80211_IFTYPE_WDS: wireless distribution interface * @NL80211_IFTYPE_MONITOR: monitor interface receiving all frames + * @NL80211_IFTYPE_MAX: highest interface type number currently defined * @__NL80211_IFTYPE_AFTER_LAST: internal use * - * These values are used with the NL80211_ATTR_IFTYPE + * These values are used with the %NL80211_ATTR_IFTYPE * to set the type of an interface. * */ @@ -31,8 +122,8 @@ enum nl80211_iftype { NL80211_IFTYPE_MONITOR, /* keep last */ - __NL80211_IFTYPE_AFTER_LAST + __NL80211_IFTYPE_AFTER_LAST, + NL80211_IFTYPE_MAX = __NL80211_IFTYPE_AFTER_LAST - 1 }; -#define NL80211_IFTYPE_MAX (__NL80211_IFTYPE_AFTER_LAST - 1) #endif /* __LINUX_NL80211_H */ diff --git a/include/linux/notifier.h b/include/linux/notifier.h index 576f2bb34cc8..fad7ff17e468 100644 --- a/include/linux/notifier.h +++ b/include/linux/notifier.h @@ -157,6 +157,19 @@ extern int __srcu_notifier_call_chain(struct srcu_notifier_head *nh, */ #define NOTIFY_STOP (NOTIFY_OK|NOTIFY_STOP_MASK) +/* Encapsulate (negative) errno value (in particular, NOTIFY_BAD <=> EPERM). */ +static inline int notifier_from_errno(int err) +{ + return NOTIFY_STOP_MASK | (NOTIFY_OK - err); +} + +/* Restore (negative) errno value from notify return value. */ +static inline int notifier_to_errno(int ret) +{ + ret &= ~NOTIFY_STOP_MASK; + return ret > NOTIFY_OK ? NOTIFY_OK - ret : 0; +} + /* * Declared notifiers so far. I can imagine quite a few more chains * over time (eg laptop power reset chains, reboot chain (to clean @@ -212,5 +225,11 @@ extern int __srcu_notifier_call_chain(struct srcu_notifier_head *nh, #define CPU_DEAD_FROZEN (CPU_DEAD | CPU_TASKS_FROZEN) #define CPU_DYING_FROZEN (CPU_DYING | CPU_TASKS_FROZEN) +/* Hibernation and suspend events */ +#define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */ +#define PM_POST_HIBERNATION 0x0002 /* Hibernation finished */ +#define PM_SUSPEND_PREPARE 0x0003 /* Going to suspend the system */ +#define PM_POST_SUSPEND 0x0004 /* Suspend finished */ + #endif /* __KERNEL__ */ #endif /* _LINUX_NOTIFIER_H */ diff --git a/include/linux/nsproxy.h b/include/linux/nsproxy.h index ce06188b7a56..bec4485e3d76 100644 --- a/include/linux/nsproxy.h +++ b/include/linux/nsproxy.h @@ -29,6 +29,7 @@ struct nsproxy { struct mnt_namespace *mnt_ns; struct pid_namespace *pid_ns; struct user_namespace *user_ns; + struct net *net_ns; }; extern struct nsproxy init_nsproxy; diff --git a/include/linux/of.h b/include/linux/of.h new file mode 100644 index 000000000000..6df80e985914 --- /dev/null +++ b/include/linux/of.h @@ -0,0 +1,60 @@ +#ifndef _LINUX_OF_H +#define _LINUX_OF_H +/* + * Definitions for talking to the Open Firmware PROM on + * Power Macintosh and other computers. + * + * Copyright (C) 1996-2005 Paul Mackerras. + * + * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp. + * Updates for SPARC64 by David S. Miller + * Derived from PowerPC and Sparc prom.h files by Stephen Rothwell, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include <linux/types.h> + +#include <asm/bitops.h> +#include <asm/prom.h> + +/* flag descriptions */ +#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ +#define OF_DETACHED 2 /* node has been detached from the device tree */ + +#define OF_BAD_ADDR ((u64)-1) + +extern struct device_node *of_find_node_by_name(struct device_node *from, + const char *name); +#define for_each_node_by_name(dn, name) \ + for (dn = of_find_node_by_name(NULL, name); dn; \ + dn = of_find_node_by_name(dn, name)) +extern struct device_node *of_find_node_by_type(struct device_node *from, + const char *type); +#define for_each_node_by_type(dn, type) \ + for (dn = of_find_node_by_type(NULL, type); dn; \ + dn = of_find_node_by_type(dn, type)) +extern struct device_node *of_find_compatible_node(struct device_node *from, + const char *type, const char *compat); +#define for_each_compatible_node(dn, type, compatible) \ + for (dn = of_find_compatible_node(NULL, type, compatible); dn; \ + dn = of_find_compatible_node(dn, type, compatible)) +extern struct device_node *of_find_node_by_path(const char *path); +extern struct device_node *of_find_node_by_phandle(phandle handle); +extern struct device_node *of_get_parent(const struct device_node *node); +extern struct device_node *of_get_next_child(const struct device_node *node, + struct device_node *prev); +extern struct property *of_find_property(const struct device_node *np, + const char *name, + int *lenp); +extern int of_device_is_compatible(const struct device_node *device, + const char *); +extern const void *of_get_property(const struct device_node *node, + const char *name, + int *lenp); +extern int of_n_addr_cells(struct device_node *np); +extern int of_n_size_cells(struct device_node *np); + +#endif /* _LINUX_OF_H */ diff --git a/include/linux/of_device.h b/include/linux/of_device.h new file mode 100644 index 000000000000..91bf84b9d144 --- /dev/null +++ b/include/linux/of_device.h @@ -0,0 +1,26 @@ +#ifndef _LINUX_OF_DEVICE_H +#define _LINUX_OF_DEVICE_H +#ifdef __KERNEL__ + +#include <linux/device.h> +#include <linux/of.h> +#include <linux/mod_devicetable.h> + +#include <asm/of_device.h> + +#define to_of_device(d) container_of(d, struct of_device, dev) + +extern const struct of_device_id *of_match_node( + const struct of_device_id *matches, const struct device_node *node); +extern const struct of_device_id *of_match_device( + const struct of_device_id *matches, const struct of_device *dev); + +extern struct of_device *of_dev_get(struct of_device *dev); +extern void of_dev_put(struct of_device *dev); + +extern int of_device_register(struct of_device *ofdev); +extern void of_device_unregister(struct of_device *ofdev); +extern void of_release_dev(struct device *dev); + +#endif /* __KERNEL__ */ +#endif /* _LINUX_OF_DEVICE_H */ diff --git a/include/linux/of_platform.h b/include/linux/of_platform.h new file mode 100644 index 000000000000..448f70b30a0c --- /dev/null +++ b/include/linux/of_platform.h @@ -0,0 +1,57 @@ +#ifndef _LINUX_OF_PLATFORM_H +#define _LINUX_OF_PLATFORM_H +/* + * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp. + * <benh@kernel.crashing.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/mod_devicetable.h> +#include <linux/pm.h> +#include <linux/of_device.h> + +/* + * The of_platform_bus_type is a bus type used by drivers that do not + * attach to a macio or similar bus but still use OF probing + * mechanism + */ +extern struct bus_type of_platform_bus_type; + +/* + * An of_platform_driver driver is attached to a basic of_device on + * the "platform bus" (of_platform_bus_type) (or ISA, EBUS and SBUS + * busses on sparc). + */ +struct of_platform_driver +{ + const char *name; + const struct of_device_id *match_table; + struct module *owner; + + int (*probe)(struct of_device* dev, + const struct of_device_id *match); + int (*remove)(struct of_device* dev); + + int (*suspend)(struct of_device* dev, pm_message_t state); + int (*resume)(struct of_device* dev); + int (*shutdown)(struct of_device* dev); + + struct device_driver driver; +}; +#define to_of_platform_driver(drv) \ + container_of(drv,struct of_platform_driver, driver) + +#include <asm/of_platform.h> + +extern struct of_device *of_find_device_by_node(struct device_node *np); + +extern int of_bus_type_init(struct bus_type *bus, const char *name); + +#endif /* _LINUX_OF_PLATFORM_H */ diff --git a/include/linux/oprofile.h b/include/linux/oprofile.h index 0d514b252454..041bb31100f4 100644 --- a/include/linux/oprofile.h +++ b/include/linux/oprofile.h @@ -17,6 +17,26 @@ #include <linux/spinlock.h> #include <asm/atomic.h> +/* Each escaped entry is prefixed by ESCAPE_CODE + * then one of the following codes, then the + * relevant data. + * These #defines live in this file so that arch-specific + * buffer sync'ing code can access them. + */ +#define ESCAPE_CODE ~0UL +#define CTX_SWITCH_CODE 1 +#define CPU_SWITCH_CODE 2 +#define COOKIE_SWITCH_CODE 3 +#define KERNEL_ENTER_SWITCH_CODE 4 +#define KERNEL_EXIT_SWITCH_CODE 5 +#define MODULE_LOADED_CODE 6 +#define CTX_TGID_CODE 7 +#define TRACE_BEGIN_CODE 8 +#define TRACE_END_CODE 9 +#define XEN_ENTER_SWITCH_CODE 10 +#define SPU_PROFILING_CODE 11 +#define SPU_CTX_SWITCH_CODE 12 + struct super_block; struct dentry; struct file_operations; @@ -35,6 +55,14 @@ struct oprofile_operations { int (*start)(void); /* Stop delivering interrupts. */ void (*stop)(void); + /* Arch-specific buffer sync functions. + * Return value = 0: Success + * Return value = -1: Failure + * Return value = 1: Run generic sync function + */ + int (*sync_start)(void); + int (*sync_stop)(void); + /* Initiate a stack backtrace. Optional. */ void (*backtrace)(struct pt_regs * const regs, unsigned int depth); /* CPU identification string. */ @@ -56,6 +84,13 @@ int oprofile_arch_init(struct oprofile_operations * ops); void oprofile_arch_exit(void); /** + * Add data to the event buffer. + * The data passed is free-form, but typically consists of + * file offsets, dcookies, context information, and ESCAPE codes. + */ +void add_event_entry(unsigned long data); + +/** * Add a sample. This may be called from any context. Pass * smp_processor_id() as cpu. */ diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h index ae2d79f2107e..209d3a47f50f 100644 --- a/include/linux/page-flags.h +++ b/include/linux/page-flags.h @@ -90,8 +90,12 @@ #define PG_reclaim 17 /* To be reclaimed asap */ #define PG_buddy 19 /* Page is free, on buddy lists */ +/* PG_readahead is only used for file reads; PG_reclaim is only for writes */ +#define PG_readahead PG_reclaim /* Reminder to do async read-ahead */ + /* PG_owner_priv_1 users should have descriptive aliases */ #define PG_checked PG_owner_priv_1 /* Used by some filesystems */ +#define PG_pinned PG_owner_priv_1 /* Xen pinned pagetable */ #if (BITS_PER_LONG > 32) /* @@ -170,6 +174,10 @@ static inline void SetPageUptodate(struct page *page) #define SetPageChecked(page) set_bit(PG_checked, &(page)->flags) #define ClearPageChecked(page) clear_bit(PG_checked, &(page)->flags) +#define PagePinned(page) test_bit(PG_pinned, &(page)->flags) +#define SetPagePinned(page) set_bit(PG_pinned, &(page)->flags) +#define ClearPagePinned(page) clear_bit(PG_pinned, &(page)->flags) + #define PageReserved(page) test_bit(PG_reserved, &(page)->flags) #define SetPageReserved(page) set_bit(PG_reserved, &(page)->flags) #define ClearPageReserved(page) clear_bit(PG_reserved, &(page)->flags) @@ -181,37 +189,15 @@ static inline void SetPageUptodate(struct page *page) #define __SetPagePrivate(page) __set_bit(PG_private, &(page)->flags) #define __ClearPagePrivate(page) __clear_bit(PG_private, &(page)->flags) +/* + * Only test-and-set exist for PG_writeback. The unconditional operators are + * risky: they bypass page accounting. + */ #define PageWriteback(page) test_bit(PG_writeback, &(page)->flags) -#define SetPageWriteback(page) \ - do { \ - if (!test_and_set_bit(PG_writeback, \ - &(page)->flags)) \ - inc_zone_page_state(page, NR_WRITEBACK); \ - } while (0) -#define TestSetPageWriteback(page) \ - ({ \ - int ret; \ - ret = test_and_set_bit(PG_writeback, \ - &(page)->flags); \ - if (!ret) \ - inc_zone_page_state(page, NR_WRITEBACK); \ - ret; \ - }) -#define ClearPageWriteback(page) \ - do { \ - if (test_and_clear_bit(PG_writeback, \ - &(page)->flags)) \ - dec_zone_page_state(page, NR_WRITEBACK); \ - } while (0) -#define TestClearPageWriteback(page) \ - ({ \ - int ret; \ - ret = test_and_clear_bit(PG_writeback, \ - &(page)->flags); \ - if (ret) \ - dec_zone_page_state(page, NR_WRITEBACK); \ - ret; \ - }) +#define TestSetPageWriteback(page) test_and_set_bit(PG_writeback, \ + &(page)->flags) +#define TestClearPageWriteback(page) test_and_clear_bit(PG_writeback, \ + &(page)->flags) #define PageBuddy(page) test_bit(PG_buddy, &(page)->flags) #define __SetPageBuddy(page) __set_bit(PG_buddy, &(page)->flags) @@ -221,6 +207,10 @@ static inline void SetPageUptodate(struct page *page) #define SetPageMappedToDisk(page) set_bit(PG_mappedtodisk, &(page)->flags) #define ClearPageMappedToDisk(page) clear_bit(PG_mappedtodisk, &(page)->flags) +#define PageReadahead(page) test_bit(PG_readahead, &(page)->flags) +#define SetPageReadahead(page) set_bit(PG_readahead, &(page)->flags) +#define ClearPageReadahead(page) clear_bit(PG_readahead, &(page)->flags) + #define PageReclaim(page) test_bit(PG_reclaim, &(page)->flags) #define SetPageReclaim(page) set_bit(PG_reclaim, &(page)->flags) #define ClearPageReclaim(page) clear_bit(PG_reclaim, &(page)->flags) diff --git a/include/linux/pci.h b/include/linux/pci.h index 5e84f2e8d54c..768b93359f90 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -534,6 +534,7 @@ static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val int __must_check pci_enable_device(struct pci_dev *dev); int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask); +int __must_check pci_reenable_device(struct pci_dev *); int __must_check pcim_enable_device(struct pci_dev *pdev); void pcim_pin_device(struct pci_dev *pdev); @@ -556,6 +557,7 @@ int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); int pcix_get_max_mmrbc(struct pci_dev *dev); int pcix_get_mmrbc(struct pci_dev *dev); int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); +int pcie_get_readrq(struct pci_dev *dev); int pcie_set_readrq(struct pci_dev *dev, int rq); void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); @@ -577,6 +579,9 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state); pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); +/* Functions for PCI Hotplug drivers to use */ +int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); + /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ void pci_bus_assign_resources(struct pci_bus *bus); void pci_bus_size_bridges(struct pci_bus *bus); @@ -680,13 +685,16 @@ extern void pci_unblock_user_cfg_access(struct pci_dev *dev); * a PCI domain is defined to be a set of PCI busses which share * configuration space. */ -#ifndef CONFIG_PCI_DOMAINS +#ifdef CONFIG_PCI_DOMAINS +extern int pci_domains_supported; +#else +enum { pci_domains_supported = 0 }; static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } -#endif +#endif /* CONFIG_PCI_DOMAINS */ #else /* CONFIG_PCI is not enabled */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 2c7add169539..87439ad94685 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -360,6 +360,9 @@ #define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 #define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 #define PCI_DEVICE_ID_ATI_RS480 0x5950 +#define PCI_DEVICE_ID_ATI_RD580 0x5952 +#define PCI_DEVICE_ID_ATI_RX790 0x5957 +#define PCI_DEVICE_ID_ATI_RS690 0x7910 /* ATI IXP Chipset */ #define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 #define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353 @@ -371,10 +374,9 @@ #define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 #define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a #define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380 -#define PCI_DEVICE_ID_ATI_IXP600_SMBUS 0x4385 +#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385 #define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c #define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390 -#define PCI_DEVICE_ID_ATI_IXP700_SMBUS 0x4395 #define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c #define PCI_VENDOR_ID_VLSI 0x1004 @@ -495,6 +497,8 @@ #define PCI_VENDOR_ID_AMD 0x1022 #define PCI_DEVICE_ID_AMD_K8_NB 0x1100 +#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101 +#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102 #define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 @@ -609,7 +613,6 @@ #define PCI_DEVICE_ID_NEC_CBUS_3 0x003b #define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e #define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ -#define PCI_DEVICE_ID_NEC_NILE4 0x005a #define PCI_DEVICE_ID_NEC_VRC5476 0x009b #define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 #define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 @@ -826,6 +829,9 @@ #define PCI_DEVICE_ID_UMC_UM8886BF 0x673a #define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_VENDOR_ID_PICOPOWER 0x1066 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523 0x0002 +#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP 0x8002 #define PCI_VENDOR_ID_MYLEX 0x1069 #define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 @@ -1223,6 +1229,10 @@ #define PCI_DEVICE_ID_NVIDIA_NVENET_25 0x054D #define PCI_DEVICE_ID_NVIDIA_NVENET_26 0x054E #define PCI_DEVICE_ID_NVIDIA_NVENET_27 0x054F +#define PCI_DEVICE_ID_NVIDIA_NVENET_28 0x07DC +#define PCI_DEVICE_ID_NVIDIA_NVENET_29 0x07DD +#define PCI_DEVICE_ID_NVIDIA_NVENET_30 0x07DE +#define PCI_DEVICE_ID_NVIDIA_NVENET_31 0x07DF #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE 0x056C #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759 @@ -1282,6 +1292,7 @@ #define PCI_DEVICE_ID_VIA_VT3324 0x0324 #define PCI_DEVICE_ID_VIA_VT3336 0x0336 #define PCI_DEVICE_ID_VIA_VT3351 0x0351 +#define PCI_DEVICE_ID_VIA_VT3364 0x0364 #define PCI_DEVICE_ID_VIA_8371_0 0x0391 #define PCI_DEVICE_ID_VIA_8501_0 0x0501 #define PCI_DEVICE_ID_VIA_82C561 0x0561 @@ -1335,6 +1346,7 @@ #define PCI_DEVICE_ID_VIA_8231_4 0x8235 #define PCI_DEVICE_ID_VIA_8365_1 0x8305 #define PCI_DEVICE_ID_VIA_CX700 0x8324 +#define PCI_DEVICE_ID_VIA_VX800 0x8353 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 @@ -1462,6 +1474,8 @@ #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 #define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5C832 0x0832 +#define PCI_DEVICE_ID_RICOH_R5C843 0x0843 #define PCI_VENDOR_ID_DLINK 0x1186 #define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 @@ -1727,6 +1741,11 @@ #define PCI_VENDOR_ID_RADISYS 0x1331 +#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332 +#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415 +#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425 +#define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155 + #define PCI_VENDOR_ID_DOMEX 0x134a #define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 @@ -1832,6 +1851,8 @@ #define PCI_VENDOR_ID_ABOCOM 0x13D1 #define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 +#define PCI_VENDOR_ID_SUNDANCE 0x13f0 + #define PCI_VENDOR_ID_CMEDIA 0x13f6 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 @@ -1939,8 +1960,12 @@ #define PCI_DEVICE_ID_TIGON3_5751M 0x167d #define PCI_DEVICE_ID_TIGON3_5751F 0x167e #define PCI_DEVICE_ID_TIGON3_5787F 0x167f +#define PCI_DEVICE_ID_TIGON3_5761E 0x1680 +#define PCI_DEVICE_ID_TIGON3_5761 0x1681 +#define PCI_DEVICE_ID_TIGON3_5764 0x1684 #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5784 0x1698 #define PCI_DEVICE_ID_TIGON3_5786 0x169a #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c @@ -1970,6 +1995,8 @@ #define PCI_VENDOR_ID_ENE 0x1524 #define PCI_DEVICE_ID_ENE_CB712_SD 0x0550 #define PCI_DEVICE_ID_ENE_CB712_SD_2 0x0551 +#define PCI_DEVICE_ID_ENE_CB714_SD 0x0750 +#define PCI_DEVICE_ID_ENE_CB714_SD_2 0x0751 #define PCI_DEVICE_ID_ENE_1211 0x1211 #define PCI_DEVICE_ID_ENE_1225 0x1225 #define PCI_DEVICE_ID_ENE_1410 0x1410 @@ -2017,6 +2044,8 @@ #define PCI_VENDOR_ID_ARIMA 0x161f +#define PCI_VENDOR_ID_BROCADE 0x1657 + #define PCI_VENDOR_ID_SIBYTE 0x166d #define PCI_DEVICE_ID_BCM1250_PCI 0x0001 #define PCI_DEVICE_ID_BCM1250_HT 0x0002 @@ -2038,6 +2067,8 @@ #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea #define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb +#define PCI_VENDOR_ID_LENOVO 0x17aa + #define PCI_VENDOR_ID_ARECA 0x17d3 #define PCI_DEVICE_ID_ARECA_1110 0x1110 #define PCI_DEVICE_ID_ARECA_1120 0x1120 @@ -2069,6 +2100,28 @@ #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 +#define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_DEVICE_ID_MPC8548E 0x0012 +#define PCI_DEVICE_ID_MPC8548 0x0013 +#define PCI_DEVICE_ID_MPC8543E 0x0014 +#define PCI_DEVICE_ID_MPC8543 0x0015 +#define PCI_DEVICE_ID_MPC8547E 0x0018 +#define PCI_DEVICE_ID_MPC8545E 0x0019 +#define PCI_DEVICE_ID_MPC8545 0x001a +#define PCI_DEVICE_ID_MPC8568E 0x0020 +#define PCI_DEVICE_ID_MPC8568 0x0021 +#define PCI_DEVICE_ID_MPC8567E 0x0022 +#define PCI_DEVICE_ID_MPC8567 0x0023 +#define PCI_DEVICE_ID_MPC8533E 0x0030 +#define PCI_DEVICE_ID_MPC8533 0x0031 +#define PCI_DEVICE_ID_MPC8544E 0x0032 +#define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041 +#define PCI_DEVICE_ID_MPC8641 0x7010 +#define PCI_DEVICE_ID_MPC8641D 0x7011 +#define PCI_DEVICE_ID_MPC8610 0x7018 + #define PCI_VENDOR_ID_PASEMI 0x1959 #define PCI_VENDOR_ID_ATTANSIC 0x1969 @@ -2089,6 +2142,11 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_TEHUTI 0x1fc9 +#define PCI_DEVICE_ID_TEHUTI_3009 0x3009 +#define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +#define PCI_DEVICE_ID_TEHUTI_3014 0x3014 + #define PCI_VENDOR_ID_HINT 0x3388 #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 @@ -2187,6 +2245,7 @@ #define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 #define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 #define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc #define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd #define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 #define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 @@ -2209,6 +2268,7 @@ #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 #define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 +#define PCI_DEVICE_ID_INTEL_3000_HB 0x2778 #define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 #define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 @@ -2258,6 +2318,8 @@ #define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 #define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a #define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e +#define PCI_DEVICE_ID_INTEL_TOLAPAI_0 0x5031 +#define PCI_DEVICE_ID_INTEL_TOLAPAI_1 0x5032 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 495d368390e0..c1914a8b94a9 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -147,7 +147,7 @@ #define PCI_BRIDGE_CONTROL 0x3e #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ -#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ @@ -202,8 +202,12 @@ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ -#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ +#define PCI_CAP_ID_DBG 0x0A /* Debug port */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ +#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ @@ -316,7 +320,20 @@ #define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ +#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ + /* Max # of outstanding split transactions */ +#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ +#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ +#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ +#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ +#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ +#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ +#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ +#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ diff --git a/include/linux/phy.h b/include/linux/phy.h index 2a659789f9ca..f0742b6aaa64 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -25,6 +25,8 @@ #include <linux/timer.h> #include <linux/workqueue.h> +#include <asm/atomic.h> + #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ SUPPORTED_10baseT_Full | \ SUPPORTED_100baseT_Half | \ @@ -281,6 +283,7 @@ struct phy_device { /* Interrupt and Polling infrastructure */ struct work_struct phy_queue; struct timer_list phy_timer; + atomic_t irq_disable; spinlock_t lock; diff --git a/include/linux/phy_fixed.h b/include/linux/phy_fixed.h new file mode 100644 index 000000000000..04ba70d49fb8 --- /dev/null +++ b/include/linux/phy_fixed.h @@ -0,0 +1,38 @@ +#ifndef __PHY_FIXED_H +#define __PHY_FIXED_H + +#define MII_REGS_NUM 29 + +/* max number of virtual phy stuff */ +#define MAX_PHY_AMNT 10 +/* + The idea is to emulate normal phy behavior by responding with + pre-defined values to mii BMCR read, so that read_status hook could + take all the needed info. +*/ + +struct fixed_phy_status { + u8 link; + u16 speed; + u8 duplex; +}; + +/*----------------------------------------------------------------------------- + * Private information hoder for mii_bus + *-----------------------------------------------------------------------------*/ +struct fixed_info { + u16 *regs; + u8 regs_num; + struct fixed_phy_status phy_status; + struct phy_device *phydev; /* pointer to the container */ + /* link & speed cb */ + int (*link_update) (struct net_device *, struct fixed_phy_status *); + +}; + + +int fixed_mdio_set_link_update(struct phy_device *, + int (*link_update) (struct net_device *, struct fixed_phy_status *)); +struct fixed_info *fixed_mdio_get_phydev (int phydev_ind); + +#endif /* __PHY_FIXED_H */ diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h index 268c51599eb8..919af93b7059 100644 --- a/include/linux/pkt_sched.h +++ b/include/linux/pkt_sched.h @@ -77,8 +77,8 @@ struct tc_ratespec { unsigned char cell_log; unsigned char __reserved; - unsigned short feature; - short addend; + unsigned short overhead; + short cell_align; unsigned short mpu; __u32 rate; }; diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 8bbd459eafdc..e80804316cdb 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -15,7 +15,7 @@ struct platform_device { const char * name; - u32 id; + int id; struct device dev; u32 num_resources; struct resource * resource; @@ -35,9 +35,10 @@ extern struct resource *platform_get_resource_byname(struct platform_device *, u extern int platform_get_irq_byname(struct platform_device *, char *); extern int platform_add_devices(struct platform_device **, int); -extern struct platform_device *platform_device_register_simple(char *, unsigned int, struct resource *, unsigned int); +extern struct platform_device *platform_device_register_simple(char *, int id, + struct resource *, unsigned int); -extern struct platform_device *platform_device_alloc(const char *name, unsigned int id); +extern struct platform_device *platform_device_alloc(const char *name, int id); extern int platform_device_add_resources(struct platform_device *pdev, struct resource *res, unsigned int num); extern int platform_device_add_data(struct platform_device *pdev, const void *data, size_t size); extern int platform_device_add(struct platform_device *pdev); diff --git a/include/linux/pm.h b/include/linux/pm.h index 273781c82e4d..48b71badfb4c 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -25,6 +25,7 @@ #include <linux/list.h> #include <asm/atomic.h> +#include <asm/errno.h> /* * Power management requests... these are passed to pm_send_all() and friends. @@ -101,6 +102,7 @@ struct pm_dev */ extern void (*pm_idle)(void); extern void (*pm_power_off)(void); +extern void (*pm_power_off_prepare)(void); typedef int __bitwise suspend_state_t; @@ -164,6 +166,7 @@ struct pm_ops { int (*finish)(suspend_state_t state); }; +#ifdef CONFIG_SUSPEND extern struct pm_ops *pm_ops; /** @@ -192,6 +195,12 @@ extern void arch_suspend_disable_irqs(void); extern void arch_suspend_enable_irqs(void); extern int pm_suspend(suspend_state_t state); +#else /* !CONFIG_SUSPEND */ +#define suspend_valid_only_mem NULL + +static inline void pm_set_ops(struct pm_ops *pm_ops) {} +static inline int pm_suspend(suspend_state_t state) { return -ENOSYS; } +#endif /* !CONFIG_SUSPEND */ /* * Device power management @@ -265,7 +274,7 @@ typedef struct pm_message { struct dev_pm_info { pm_message_t power_state; unsigned can_wakeup:1; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP unsigned should_wakeup:1; struct list_head entry; #endif @@ -275,7 +284,7 @@ extern int device_power_down(pm_message_t state); extern void device_power_up(void); extern void device_resume(void); -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP extern int device_suspend(pm_message_t state); extern int device_prepare_suspend(pm_message_t state); @@ -284,8 +293,6 @@ extern int device_prepare_suspend(pm_message_t state); #define device_may_wakeup(dev) \ (device_can_wakeup(dev) && (dev)->power.should_wakeup) -extern int dpm_runtime_suspend(struct device *, pm_message_t); -extern void dpm_runtime_resume(struct device *); extern void __suspend_report_result(const char *function, void *fn, int ret); #define suspend_report_result(fn, ret) \ @@ -307,7 +314,7 @@ static inline int call_platform_enable_wakeup(struct device *dev, int is_on) return 0; } -#else /* !CONFIG_PM */ +#else /* !CONFIG_PM_SLEEP */ static inline int device_suspend(pm_message_t state) { @@ -317,15 +324,6 @@ static inline int device_suspend(pm_message_t state) #define device_set_wakeup_enable(dev,val) do{}while(0) #define device_may_wakeup(dev) (0) -static inline int dpm_runtime_suspend(struct device * dev, pm_message_t state) -{ - return 0; -} - -static inline void dpm_runtime_resume(struct device * dev) -{ -} - #define suspend_report_result(fn, ret) do { } while (0) static inline int call_platform_enable_wakeup(struct device *dev, int is_on) @@ -333,7 +331,7 @@ static inline int call_platform_enable_wakeup(struct device *dev, int is_on) return 0; } -#endif +#endif /* !CONFIG_PM_SLEEP */ /* changes to device_may_wakeup take effect on the next pm state change. * by default, devices should wakeup if they can. diff --git a/include/linux/pmu.h b/include/linux/pmu.h index 5ad913ff02b2..b7824c215354 100644 --- a/include/linux/pmu.h +++ b/include/linux/pmu.h @@ -226,7 +226,7 @@ extern unsigned int pmu_power_flags; extern void pmu_backlight_init(void); /* some code needs to know if the PMU was suspended for hibernation */ -#if defined(CONFIG_PM) && defined(CONFIG_PPC32) +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PPC32) extern int pmu_sys_suspended; #else /* if power management is not configured it can't be suspended */ diff --git a/include/linux/pnp.h b/include/linux/pnp.h index 2a1897e6f937..16b46aace349 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -1,7 +1,6 @@ /* * Linux Plug and Play Support * Copyright by Adam Belay <ambx1@neo.rr.com> - * */ #ifndef _LINUX_PNP_H @@ -23,7 +22,6 @@ struct pnp_protocol; struct pnp_dev; - /* * Resource Management */ @@ -73,37 +71,37 @@ struct pnp_dev; #define PNP_PORT_FLAG_FIXED (1<<1) struct pnp_port { - unsigned short min; /* min base number */ - unsigned short max; /* max base number */ - unsigned char align; /* align boundary */ - unsigned char size; /* size of range */ - unsigned char flags; /* port flags */ - unsigned char pad; /* pad */ - struct pnp_port *next; /* next port */ + unsigned short min; /* min base number */ + unsigned short max; /* max base number */ + unsigned char align; /* align boundary */ + unsigned char size; /* size of range */ + unsigned char flags; /* port flags */ + unsigned char pad; /* pad */ + struct pnp_port *next; /* next port */ }; #define PNP_IRQ_NR 256 struct pnp_irq { - DECLARE_BITMAP(map, PNP_IRQ_NR); /* bitmaks for IRQ lines */ - unsigned char flags; /* IRQ flags */ - unsigned char pad; /* pad */ - struct pnp_irq *next; /* next IRQ */ + DECLARE_BITMAP(map, PNP_IRQ_NR); /* bitmask for IRQ lines */ + unsigned char flags; /* IRQ flags */ + unsigned char pad; /* pad */ + struct pnp_irq *next; /* next IRQ */ }; struct pnp_dma { - unsigned char map; /* bitmask for DMA channels */ - unsigned char flags; /* DMA flags */ - struct pnp_dma *next; /* next port */ + unsigned char map; /* bitmask for DMA channels */ + unsigned char flags; /* DMA flags */ + struct pnp_dma *next; /* next port */ }; struct pnp_mem { - unsigned int min; /* min base number */ - unsigned int max; /* max base number */ - unsigned int align; /* align boundary */ - unsigned int size; /* size of range */ - unsigned char flags; /* memory flags */ - unsigned char pad; /* pad */ - struct pnp_mem *next; /* next memory resource */ + unsigned int min; /* min base number */ + unsigned int max; /* max base number */ + unsigned int align; /* align boundary */ + unsigned int size; /* size of range */ + unsigned char flags; /* memory flags */ + unsigned char pad; /* pad */ + struct pnp_mem *next; /* next memory resource */ }; #define PNP_RES_PRIORITY_PREFERRED 0 @@ -127,7 +125,6 @@ struct pnp_resource_table { struct resource irq_resource[PNP_MAX_IRQ]; }; - /* * Device Managemnt */ @@ -139,14 +136,14 @@ struct pnp_card { struct list_head protocol_list; /* node in protocol's list of cards */ struct list_head devices; /* devices attached to the card */ - struct pnp_protocol * protocol; - struct pnp_id * id; /* contains supported EISA IDs*/ + struct pnp_protocol *protocol; + struct pnp_id *id; /* contains supported EISA IDs */ char name[PNP_NAME_LEN]; /* contains a human-readable name */ - unsigned char pnpver; /* Plug & Play version */ - unsigned char productver; /* product version */ - unsigned int serial; /* serial number */ - unsigned char checksum; /* if zero - checksum passed */ + unsigned char pnpver; /* Plug & Play version */ + unsigned char productver; /* product version */ + unsigned int serial; /* serial number */ + unsigned char checksum; /* if zero - checksum passed */ struct proc_dir_entry *procdir; /* directory entry in /proc/bus/isapnp */ }; @@ -159,18 +156,18 @@ struct pnp_card { (card) = global_to_pnp_card((card)->global_list.next)) struct pnp_card_link { - struct pnp_card * card; - struct pnp_card_driver * driver; - void * driver_data; + struct pnp_card *card; + struct pnp_card_driver *driver; + void *driver_data; pm_message_t pm_state; }; -static inline void *pnp_get_card_drvdata (struct pnp_card_link *pcard) +static inline void *pnp_get_card_drvdata(struct pnp_card_link *pcard) { return pcard->driver_data; } -static inline void pnp_set_card_drvdata (struct pnp_card_link *pcard, void *data) +static inline void pnp_set_card_drvdata(struct pnp_card_link *pcard, void *data) { pcard->driver_data = data; } @@ -186,22 +183,22 @@ struct pnp_dev { struct list_head card_list; /* node in card's list of devices */ struct list_head rdev_list; /* node in cards list of requested devices */ - struct pnp_protocol * protocol; - struct pnp_card * card; /* card the device is attached to, none if NULL */ - struct pnp_driver * driver; - struct pnp_card_link * card_link; + struct pnp_protocol *protocol; + struct pnp_card *card; /* card the device is attached to, none if NULL */ + struct pnp_driver *driver; + struct pnp_card_link *card_link; - struct pnp_id * id; /* supported EISA IDs*/ + struct pnp_id *id; /* supported EISA IDs */ int active; int capabilities; - struct pnp_option * independent; - struct pnp_option * dependent; + struct pnp_option *independent; + struct pnp_option *dependent; struct pnp_resource_table res; char name[PNP_NAME_LEN]; /* contains a human-readable name */ - unsigned short regs; /* ISAPnP: supported registers */ - int flags; /* used by protocols */ + unsigned short regs; /* ISAPnP: supported registers */ + int flags; /* used by protocols */ struct proc_dir_entry *procent; /* device entry in /proc/bus/isapnp */ void *data; }; @@ -220,19 +217,19 @@ struct pnp_dev { (dev) = card_to_pnp_dev((dev)->card_list.next)) #define pnp_dev_name(dev) (dev)->name -static inline void *pnp_get_drvdata (struct pnp_dev *pdev) +static inline void *pnp_get_drvdata(struct pnp_dev *pdev) { return dev_get_drvdata(&pdev->dev); } -static inline void pnp_set_drvdata (struct pnp_dev *pdev, void *data) +static inline void pnp_set_drvdata(struct pnp_dev *pdev, void *data) { dev_set_drvdata(&pdev->dev, data); } struct pnp_fixup { char id[7]; - void (*quirk_function)(struct pnp_dev *dev); /* fixup function */ + void (*quirk_function) (struct pnp_dev * dev); /* fixup function */ }; /* config parameters */ @@ -269,7 +266,6 @@ extern struct pnp_protocol pnpbios_protocol; #define pnp_device_is_pnpbios(dev) 0 #endif - /* status */ #define PNP_READY 0x0000 #define PNP_ATTACHED 0x0001 @@ -287,17 +283,17 @@ extern struct pnp_protocol pnpbios_protocol; struct pnp_id { char id[PNP_ID_LEN]; - struct pnp_id * next; + struct pnp_id *next; }; struct pnp_driver { - char * name; + char *name; const struct pnp_device_id *id_table; unsigned int flags; - int (*probe) (struct pnp_dev *dev, const struct pnp_device_id *dev_id); + int (*probe) (struct pnp_dev *dev, const struct pnp_device_id *dev_id); void (*remove) (struct pnp_dev *dev); - int (*suspend) (struct pnp_dev *dev, pm_message_t state); - int (*resume) (struct pnp_dev *dev); + int (*suspend) (struct pnp_dev *dev, pm_message_t state); + int (*resume) (struct pnp_dev *dev); struct device_driver driver; }; @@ -305,13 +301,14 @@ struct pnp_driver { struct pnp_card_driver { struct list_head global_list; - char * name; + char *name; const struct pnp_card_device_id *id_table; unsigned int flags; - int (*probe) (struct pnp_card_link *card, const struct pnp_card_device_id *card_id); + int (*probe) (struct pnp_card_link *card, + const struct pnp_card_device_id *card_id); void (*remove) (struct pnp_card_link *card); - int (*suspend) (struct pnp_card_link *card, pm_message_t state); - int (*resume) (struct pnp_card_link *card); + int (*suspend) (struct pnp_card_link *card, pm_message_t state); + int (*resume) (struct pnp_card_link *card); struct pnp_driver link; }; @@ -321,25 +318,28 @@ struct pnp_card_driver { #define PNP_DRIVER_RES_DO_NOT_CHANGE 0x0001 /* do not change the state of the device */ #define PNP_DRIVER_RES_DISABLE 0x0003 /* ensure the device is disabled */ - /* * Protocol Management */ struct pnp_protocol { - struct list_head protocol_list; - char * name; + struct list_head protocol_list; + char *name; /* resource control functions */ - int (*get)(struct pnp_dev *dev, struct pnp_resource_table *res); - int (*set)(struct pnp_dev *dev, struct pnp_resource_table *res); - int (*disable)(struct pnp_dev *dev); + int (*get) (struct pnp_dev *dev, struct pnp_resource_table *res); + int (*set) (struct pnp_dev *dev, struct pnp_resource_table *res); + int (*disable) (struct pnp_dev *dev); + + /* protocol specific suspend/resume */ + int (*suspend) (struct pnp_dev * dev, pm_message_t state); + int (*resume) (struct pnp_dev * dev); /* used by pnp layer only (look but don't touch) */ - unsigned char number; /* protocol number*/ - struct device dev; /* link to driver model */ - struct list_head cards; - struct list_head devices; + unsigned char number; /* protocol number */ + struct device dev; /* link to driver model */ + struct list_head cards; + struct list_head devices; }; #define to_pnp_protocol(n) list_entry(n, struct pnp_protocol, protocol_list) @@ -352,7 +352,6 @@ struct pnp_protocol { (dev) != protocol_to_pnp_dev(&(protocol)->devices); \ (dev) = protocol_to_pnp_dev((dev)->protocol_list.next)) - extern struct bus_type pnp_bus_type; #if defined(CONFIG_PNP) @@ -372,21 +371,25 @@ void pnp_remove_card(struct pnp_card *card); int pnp_add_card_device(struct pnp_card *card, struct pnp_dev *dev); void pnp_remove_card_device(struct pnp_dev *dev); int pnp_add_card_id(struct pnp_id *id, struct pnp_card *card); -struct pnp_dev * pnp_request_card_device(struct pnp_card_link *clink, const char * id, struct pnp_dev * from); -void pnp_release_card_device(struct pnp_dev * dev); -int pnp_register_card_driver(struct pnp_card_driver * drv); -void pnp_unregister_card_driver(struct pnp_card_driver * drv); +struct pnp_dev *pnp_request_card_device(struct pnp_card_link *clink, + const char *id, struct pnp_dev *from); +void pnp_release_card_device(struct pnp_dev *dev); +int pnp_register_card_driver(struct pnp_card_driver *drv); +void pnp_unregister_card_driver(struct pnp_card_driver *drv); extern struct list_head pnp_cards; /* resource management */ -struct pnp_option * pnp_register_independent_option(struct pnp_dev *dev); -struct pnp_option * pnp_register_dependent_option(struct pnp_dev *dev, int priority); +struct pnp_option *pnp_register_independent_option(struct pnp_dev *dev); +struct pnp_option *pnp_register_dependent_option(struct pnp_dev *dev, + int priority); int pnp_register_irq_resource(struct pnp_option *option, struct pnp_irq *data); int pnp_register_dma_resource(struct pnp_option *option, struct pnp_dma *data); -int pnp_register_port_resource(struct pnp_option *option, struct pnp_port *data); +int pnp_register_port_resource(struct pnp_option *option, + struct pnp_port *data); int pnp_register_mem_resource(struct pnp_option *option, struct pnp_mem *data); void pnp_init_resource_table(struct pnp_resource_table *table); -int pnp_manual_config_dev(struct pnp_dev *dev, struct pnp_resource_table *res, int mode); +int pnp_manual_config_dev(struct pnp_dev *dev, struct pnp_resource_table *res, + int mode); int pnp_auto_config_dev(struct pnp_dev *dev); int pnp_validate_config(struct pnp_dev *dev); int pnp_start_dev(struct pnp_dev *dev); @@ -394,11 +397,11 @@ int pnp_stop_dev(struct pnp_dev *dev); int pnp_activate_dev(struct pnp_dev *dev); int pnp_disable_dev(struct pnp_dev *dev); void pnp_resource_change(struct resource *resource, resource_size_t start, - resource_size_t size); + resource_size_t size); /* protocol helpers */ -int pnp_is_active(struct pnp_dev * dev); -int compare_pnp_id(struct pnp_id * pos, const char * id); +int pnp_is_active(struct pnp_dev *dev); +int compare_pnp_id(struct pnp_id *pos, const char *id); int pnp_add_id(struct pnp_id *id, struct pnp_dev *dev); int pnp_register_driver(struct pnp_driver *drv); void pnp_unregister_driver(struct pnp_driver *drv); @@ -411,23 +414,24 @@ static inline void pnp_unregister_protocol(struct pnp_protocol *protocol) { } static inline int pnp_init_device(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_add_device(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_device_attach(struct pnp_dev *pnp_dev) { return -ENODEV; } -static inline void pnp_device_detach(struct pnp_dev *pnp_dev) { ; } +static inline void pnp_device_detach(struct pnp_dev *pnp_dev) { } + #define pnp_platform_devices 0 /* multidevice card support */ static inline int pnp_add_card(struct pnp_card *card) { return -ENODEV; } -static inline void pnp_remove_card(struct pnp_card *card) { ; } +static inline void pnp_remove_card(struct pnp_card *card) { } static inline int pnp_add_card_device(struct pnp_card *card, struct pnp_dev *dev) { return -ENODEV; } -static inline void pnp_remove_card_device(struct pnp_dev *dev) { ; } +static inline void pnp_remove_card_device(struct pnp_dev *dev) { } static inline int pnp_add_card_id(struct pnp_id *id, struct pnp_card *card) { return -ENODEV; } -static inline struct pnp_dev * pnp_request_card_device(struct pnp_card_link *clink, const char * id, struct pnp_dev * from) { return NULL; } -static inline void pnp_release_card_device(struct pnp_dev * dev) { ; } -static inline int pnp_register_card_driver(struct pnp_card_driver * drv) { return -ENODEV; } -static inline void pnp_unregister_card_driver(struct pnp_card_driver * drv) { ; } +static inline struct pnp_dev *pnp_request_card_device(struct pnp_card_link *clink, const char *id, struct pnp_dev *from) { return NULL; } +static inline void pnp_release_card_device(struct pnp_dev *dev) { } +static inline int pnp_register_card_driver(struct pnp_card_driver *drv) { return -ENODEV; } +static inline void pnp_unregister_card_driver(struct pnp_card_driver *drv) { } /* resource management */ -static inline struct pnp_option * pnp_register_independent_option(struct pnp_dev *dev) { return NULL; } -static inline struct pnp_option * pnp_register_dependent_option(struct pnp_dev *dev, int priority) { return NULL; } +static inline struct pnp_option *pnp_register_independent_option(struct pnp_dev *dev) { return NULL; } +static inline struct pnp_option *pnp_register_dependent_option(struct pnp_dev *dev, int priority) { return NULL; } static inline int pnp_register_irq_resource(struct pnp_option *option, struct pnp_irq *data) { return -ENODEV; } static inline int pnp_register_dma_resource(struct pnp_option *option, struct pnp_dma *data) { return -ENODEV; } static inline int pnp_register_port_resource(struct pnp_option *option, struct pnp_port *data) { return -ENODEV; } @@ -440,20 +444,17 @@ static inline int pnp_start_dev(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_stop_dev(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_activate_dev(struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_disable_dev(struct pnp_dev *dev) { return -ENODEV; } -static inline void pnp_resource_change(struct resource *resource, - resource_size_t start, - resource_size_t size) { } +static inline void pnp_resource_change(struct resource *resource, resource_size_t start, resource_size_t size) { } /* protocol helpers */ -static inline int pnp_is_active(struct pnp_dev * dev) { return 0; } -static inline int compare_pnp_id(struct pnp_id * pos, const char * id) { return -ENODEV; } +static inline int pnp_is_active(struct pnp_dev *dev) { return 0; } +static inline int compare_pnp_id(struct pnp_id *pos, const char *id) { return -ENODEV; } static inline int pnp_add_id(struct pnp_id *id, struct pnp_dev *dev) { return -ENODEV; } static inline int pnp_register_driver(struct pnp_driver *drv) { return -ENODEV; } -static inline void pnp_unregister_driver(struct pnp_driver *drv) { ; } +static inline void pnp_unregister_driver(struct pnp_driver *drv) { } #endif /* CONFIG_PNP */ - #define pnp_err(format, arg...) printk(KERN_ERR "pnp: " format "\n" , ## arg) #define pnp_info(format, arg...) printk(KERN_INFO "pnp: " format "\n" , ## arg) #define pnp_warn(format, arg...) printk(KERN_WARNING "pnp: " format "\n" , ## arg) diff --git a/include/linux/pnpbios.h b/include/linux/pnpbios.h index 0a282ac1f6b2..329192adc9dd 100644 --- a/include/linux/pnpbios.h +++ b/include/linux/pnpbios.h @@ -99,32 +99,32 @@ #pragma pack(1) struct pnp_dev_node_info { - __u16 no_nodes; - __u16 max_node_size; + __u16 no_nodes; + __u16 max_node_size; }; struct pnp_docking_station_info { - __u32 location_id; - __u32 serial; - __u16 capabilities; + __u32 location_id; + __u32 serial; + __u16 capabilities; }; struct pnp_isa_config_struc { - __u8 revision; - __u8 no_csns; - __u16 isa_rd_data_port; - __u16 reserved; + __u8 revision; + __u8 no_csns; + __u16 isa_rd_data_port; + __u16 reserved; }; struct escd_info_struc { - __u16 min_escd_write_size; - __u16 escd_size; - __u32 nv_storage_base; + __u16 min_escd_write_size; + __u16 escd_size; + __u32 nv_storage_base; }; struct pnp_bios_node { - __u16 size; - __u8 handle; - __u32 eisa_id; - __u8 type_code[3]; - __u16 flags; - __u8 data[0]; + __u16 size; + __u8 handle; + __u32 eisa_id; + __u8 type_code[3]; + __u16 flags; + __u8 data[0]; }; #pragma pack() @@ -133,22 +133,16 @@ struct pnp_bios_node { /* non-exported */ extern struct pnp_dev_node_info node_info; -extern int pnp_bios_dev_node_info (struct pnp_dev_node_info *data); -extern int pnp_bios_get_dev_node (u8 *nodenum, char config, struct pnp_bios_node *data); -extern int pnp_bios_set_dev_node (u8 nodenum, char config, struct pnp_bios_node *data); -extern int pnp_bios_get_stat_res (char *info); -extern int pnp_bios_isapnp_config (struct pnp_isa_config_struc *data); -extern int pnp_bios_escd_info (struct escd_info_struc *data); -extern int pnp_bios_read_escd (char *data, u32 nvram_base); +extern int pnp_bios_dev_node_info(struct pnp_dev_node_info *data); +extern int pnp_bios_get_dev_node(u8 *nodenum, char config, + struct pnp_bios_node *data); +extern int pnp_bios_set_dev_node(u8 nodenum, char config, + struct pnp_bios_node *data); +extern int pnp_bios_get_stat_res(char *info); +extern int pnp_bios_isapnp_config(struct pnp_isa_config_struc *data); +extern int pnp_bios_escd_info(struct escd_info_struc *data); +extern int pnp_bios_read_escd(char *data, u32 nvram_base); extern int pnp_bios_dock_station_info(struct pnp_docking_station_info *data); -#define needed 0 -#if needed -extern int pnp_bios_get_event (u16 *message); -extern int pnp_bios_send_message (u16 message); -extern int pnp_bios_set_stat_res (char *info); -extern int pnp_bios_apm_id_table (char *table, u16 *size); -extern int pnp_bios_write_escd (char *data, u32 nvram_base); -#endif #endif /* CONFIG_PNPBIOS */ diff --git a/include/linux/poll.h b/include/linux/poll.h index 27690798623f..16d813b364ef 100644 --- a/include/linux/poll.h +++ b/include/linux/poll.h @@ -21,6 +21,8 @@ #define WQUEUES_STACK_ALLOC (MAX_STACK_ALLOC - FRONTEND_STACK_ALLOC) #define N_INLINE_POLL_ENTRIES (WQUEUES_STACK_ALLOC / sizeof(struct poll_table_entry)) +#define DEFAULT_POLLMASK (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM) + struct poll_table_struct; /* diff --git a/include/linux/preempt.h b/include/linux/preempt.h index d0926d63406c..484988ed301e 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h @@ -8,6 +8,7 @@ #include <linux/thread_info.h> #include <linux/linkage.h> +#include <linux/list.h> #ifdef CONFIG_DEBUG_PREEMPT extern void fastcall add_preempt_count(int val); @@ -60,4 +61,47 @@ do { \ #endif +#ifdef CONFIG_PREEMPT_NOTIFIERS + +struct preempt_notifier; + +/** + * preempt_ops - notifiers called when a task is preempted and rescheduled + * @sched_in: we're about to be rescheduled: + * notifier: struct preempt_notifier for the task being scheduled + * cpu: cpu we're scheduled on + * @sched_out: we've just been preempted + * notifier: struct preempt_notifier for the task being preempted + * next: the task that's kicking us out + */ +struct preempt_ops { + void (*sched_in)(struct preempt_notifier *notifier, int cpu); + void (*sched_out)(struct preempt_notifier *notifier, + struct task_struct *next); +}; + +/** + * preempt_notifier - key for installing preemption notifiers + * @link: internal use + * @ops: defines the notifier functions to be called + * + * Usually used in conjunction with container_of(). + */ +struct preempt_notifier { + struct hlist_node link; + struct preempt_ops *ops; +}; + +void preempt_notifier_register(struct preempt_notifier *notifier); +void preempt_notifier_unregister(struct preempt_notifier *notifier); + +static inline void preempt_notifier_init(struct preempt_notifier *notifier, + struct preempt_ops *ops) +{ + INIT_HLIST_NODE(¬ifier->link); + notifier->ops = ops; +} + +#endif + #endif /* __LINUX_PREEMPT_H */ diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index 28e3664fdf1b..20741f668f7b 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -7,6 +7,7 @@ #include <linux/magic.h> #include <asm/atomic.h> +struct net; struct completion; /* @@ -75,7 +76,6 @@ struct proc_dir_entry { write_proc_t *write_proc; atomic_t count; /* use count */ int deleted; /* delete flag */ - void *set; int pde_users; /* number of callers into module in progress */ spinlock_t pde_unload_lock; /* proc_fops checks and pde_users bumps */ struct completion *pde_unload_completion; @@ -98,8 +98,6 @@ struct vmcore { extern struct proc_dir_entry proc_root; extern struct proc_dir_entry *proc_root_fs; -extern struct proc_dir_entry *proc_net; -extern struct proc_dir_entry *proc_net_stat; extern struct proc_dir_entry *proc_bus; extern struct proc_dir_entry *proc_root_driver; extern struct proc_dir_entry *proc_root_kcore; @@ -193,36 +191,21 @@ static inline struct proc_dir_entry *create_proc_info_entry(const char *name, if (res) res->get_info=get_info; return res; } - -static inline struct proc_dir_entry *proc_net_create(const char *name, - mode_t mode, get_info_t *get_info) -{ - return create_proc_info_entry(name,mode,proc_net,get_info); -} -static inline struct proc_dir_entry *proc_net_fops_create(const char *name, - mode_t mode, const struct file_operations *fops) -{ - struct proc_dir_entry *res = create_proc_entry(name, mode, proc_net); - if (res) - res->proc_fops = fops; - return res; -} - -static inline void proc_net_remove(const char *name) -{ - remove_proc_entry(name,proc_net); -} +extern struct proc_dir_entry *proc_net_create(struct net *net, + const char *name, mode_t mode, get_info_t *get_info); +extern struct proc_dir_entry *proc_net_fops_create(struct net *net, + const char *name, mode_t mode, const struct file_operations *fops); +extern void proc_net_remove(struct net *net, const char *name); #else #define proc_root_driver NULL -#define proc_net NULL #define proc_bus NULL -#define proc_net_fops_create(name, mode, fops) ({ (void)(mode), NULL; }) -#define proc_net_create(name, mode, info) ({ (void)(mode), NULL; }) -static inline void proc_net_remove(const char *name) {} +#define proc_net_fops_create(net, name, mode, fops) ({ (void)(mode), NULL; }) +#define proc_net_create(net, name, mode, info) ({ (void)(mode), NULL; }) +static inline void proc_net_remove(struct net *net, const char *name) {} static inline void proc_flush_task(struct task_struct *task) { } @@ -282,6 +265,13 @@ static inline struct proc_dir_entry *PDE(const struct inode *inode) return PROC_I(inode)->pde; } +static inline struct net *PDE_NET(struct proc_dir_entry *pde) +{ + return pde->parent->data; +} + +struct net *get_proc_net(const struct inode *inode); + struct proc_maps_private { struct pid *pid; struct task_struct *task; diff --git a/include/linux/raid/md_k.h b/include/linux/raid/md_k.h index 28ac632b42dd..dcb729244f47 100644 --- a/include/linux/raid/md_k.h +++ b/include/linux/raid/md_k.h @@ -227,7 +227,7 @@ struct mddev_s unsigned int safemode_delay; struct timer_list safemode_timer; atomic_t writes_pending; - request_queue_t *queue; /* for plugging ... */ + struct request_queue *queue; /* for plugging ... */ atomic_t write_behind; /* outstanding async IO */ unsigned int max_write_behind; /* 0 = sync */ @@ -265,7 +265,7 @@ struct mdk_personality int level; struct list_head list; struct module *owner; - int (*make_request)(request_queue_t *q, struct bio *bio); + int (*make_request)(struct request_queue *q, struct bio *bio); int (*run)(mddev_t *mddev); int (*stop)(mddev_t *mddev); void (*status)(struct seq_file *seq, mddev_t *mddev); diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index c6b7485eac7c..fe17d7d750c2 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -281,7 +281,6 @@ extern void FASTCALL(call_rcu(struct rcu_head *head, extern void FASTCALL(call_rcu_bh(struct rcu_head *head, void (*func)(struct rcu_head *head))); extern void synchronize_rcu(void); -void synchronize_idle(void); extern void rcu_barrier(void); #endif /* __KERNEL__ */ diff --git a/include/linux/reboot.h b/include/linux/reboot.h index 1dd1c707311f..85ea63f462af 100644 --- a/include/linux/reboot.h +++ b/include/linux/reboot.h @@ -67,6 +67,11 @@ extern void kernel_power_off(void); void ctrl_alt_del(void); +#define POWEROFF_CMD_PATH_LEN 256 +extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN]; + +extern int orderly_poweroff(bool force); + /* * Emergency restart, callable from an interrupt handler. */ diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index 965d5b3ea9eb..180a9d832dde 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -81,14 +81,16 @@ void reiserfs_warning(struct super_block *s, const char *fmt, ...); /* assertions handling */ /** always check a condition and panic if it's false. */ -#define RASSERT( cond, format, args... ) \ +#define __RASSERT( cond, scond, format, args... ) \ if( !( cond ) ) \ - reiserfs_panic( NULL, "reiserfs[%i]: assertion " #cond " failed at " \ + reiserfs_panic( NULL, "reiserfs[%i]: assertion " scond " failed at " \ __FILE__ ":%i:%s: " format "\n", \ in_interrupt() ? -1 : current -> pid, __LINE__ , __FUNCTION__ , ##args ) +#define RASSERT(cond, format, args...) __RASSERT(cond, #cond, format, ##args) + #if defined( CONFIG_REISERFS_CHECK ) -#define RFALSE( cond, format, args... ) RASSERT( !( cond ), format, ##args ) +#define RFALSE(cond, format, args...) __RASSERT(!(cond), "!(" #cond ")", format, ##args) #else #define RFALSE( cond, format, args... ) do {;} while( 0 ) #endif diff --git a/include/linux/resume-trace.h b/include/linux/resume-trace.h index 81e9299ca148..f3f4f28c6960 100644 --- a/include/linux/resume-trace.h +++ b/include/linux/resume-trace.h @@ -2,6 +2,7 @@ #define RESUME_TRACE_H #ifdef CONFIG_PM_TRACE +#include <asm/resume-trace.h> extern int pm_trace_enabled; @@ -9,20 +10,10 @@ struct device; extern void set_trace_device(struct device *); extern void generate_resume_trace(void *tracedata, unsigned int user); -#define TRACE_DEVICE(dev) set_trace_device(dev) -#define TRACE_RESUME(user) do { \ - if (pm_trace_enabled) { \ - void *tracedata; \ - asm volatile("movl $1f,%0\n" \ - ".section .tracedata,\"a\"\n" \ - "1:\t.word %c1\n" \ - "\t.long %c2\n" \ - ".previous" \ - :"=r" (tracedata) \ - : "i" (__LINE__), "i" (__FILE__)); \ - generate_resume_trace(tracedata, user); \ - } \ -} while (0) +#define TRACE_DEVICE(dev) do { \ + if (pm_trace_enabled) \ + set_trace_device(dev); \ + } while(0) #else diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h index a8a6ea809da0..0ce5e0b52dbd 100644 --- a/include/linux/rfkill.h +++ b/include/linux/rfkill.h @@ -2,7 +2,7 @@ #define __RFKILL_H /* - * Copyright (C) 2006 Ivo van Doorn + * Copyright (C) 2006 - 2007 Ivo van Doorn * Copyright (C) 2007 Dmitry Torokhov * * This program is free software; you can redistribute it and/or modify @@ -26,18 +26,19 @@ #include <linux/list.h> #include <linux/mutex.h> #include <linux/device.h> +#include <linux/leds.h> /** * enum rfkill_type - type of rfkill switch. - * RFKILL_TYPE_WLAN: switch is no a Wireless network devices. - * RFKILL_TYPE_BlUETOOTH: switch is on a bluetooth device. - * RFKILL_TYPE_IRDA: switch is on an infrared devices. + * RFKILL_TYPE_WLAN: switch is on a 802.11 wireless network device. + * RFKILL_TYPE_BLUETOOTH: switch is on a bluetooth device. + * RFKILL_TYPE_UWB: switch is on a ultra wideband device. */ enum rfkill_type { - RFKILL_TYPE_WLAN = 0, - RFKILL_TYPE_BLUETOOTH = 1, - RFKILL_TYPE_IRDA = 2, - RFKILL_TYPE_MAX = 3, + RFKILL_TYPE_WLAN , + RFKILL_TYPE_BLUETOOTH, + RFKILL_TYPE_UWB, + RFKILL_TYPE_MAX, }; enum rfkill_state { @@ -51,11 +52,14 @@ enum rfkill_state { * @type: Radio type which the button controls, the value stored * here should be a value from enum rfkill_type. * @state: State of the switch (on/off). + * @user_claim_unsupported: Whether the hardware supports exclusive + * RF-kill control by userspace. Set this before registering. * @user_claim: Set when the switch is controlled exlusively by userspace. * @mutex: Guards switch state transitions * @data: Pointer to the RF button drivers private data which will be * passed along when toggling radio state. * @toggle_radio(): Mandatory handler to control state of the radio. + * @led_trigger: A LED trigger for this button's LED. * @dev: Device structure integrating the switch into device tree. * @node: Used to place switch into list of all switches known to the * the system. @@ -67,6 +71,7 @@ struct rfkill { enum rfkill_type type; enum rfkill_state state; + bool user_claim_unsupported; bool user_claim; struct mutex mutex; @@ -74,6 +79,10 @@ struct rfkill { void *data; int (*toggle_radio)(void *data, enum rfkill_state state); +#ifdef CONFIG_RFKILL_LEDS + struct led_trigger led_trigger; +#endif + struct device dev; struct list_head node; }; @@ -84,6 +93,19 @@ void rfkill_free(struct rfkill *rfkill); int rfkill_register(struct rfkill *rfkill); void rfkill_unregister(struct rfkill *rfkill); -void rfkill_switch_all(enum rfkill_type type, enum rfkill_state state); +/** + * rfkill_get_led_name - Get the LED trigger name for the button's LED. + * This function might return a NULL pointer if registering of the + * LED trigger failed. + * Use this as "default_trigger" for the LED. + */ +static inline char *rfkill_get_led_name(struct rfkill *rfkill) +{ +#ifdef CONFIG_RFKILL_LEDS + return (char *)(rfkill->led_trigger.name); +#else + return NULL; +#endif +} #endif /* RFKILL_H */ diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index c91476ce314a..5bf618241ab9 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -97,6 +97,9 @@ enum { RTM_SETNEIGHTBL, #define RTM_SETNEIGHTBL RTM_SETNEIGHTBL + RTM_NEWNDUSEROPT = 68, +#define RTM_NEWNDUSEROPT RTM_NEWNDUSEROPT + __RTM_MAX, #define RTM_MAX (((__RTM_MAX + 3) & ~3) - 1) }; @@ -351,6 +354,8 @@ enum #define RTAX_INITCWND RTAX_INITCWND RTAX_FEATURES, #define RTAX_FEATURES RTAX_FEATURES + RTAX_RTO_MIN, +#define RTAX_RTO_MIN RTAX_RTO_MIN __RTAX_MAX }; @@ -477,6 +482,30 @@ enum #define TCA_RTA(r) ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct tcmsg)))) #define TCA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct tcmsg)) +/******************************************************************** + * Neighbor Discovery userland options + ****/ + +struct nduseroptmsg +{ + unsigned char nduseropt_family; + unsigned char nduseropt_pad1; + unsigned short nduseropt_opts_len; /* Total length of options */ + __u8 nduseropt_icmp_type; + __u8 nduseropt_icmp_code; + unsigned short nduseropt_pad2; + /* Followed by one or more ND options */ +}; + +enum +{ + NDUSEROPT_UNSPEC, + NDUSEROPT_SRCADDR, + __NDUSEROPT_MAX +}; + +#define NDUSEROPT_MAX (__NDUSEROPT_MAX - 1) + #ifndef __KERNEL__ /* RTnetlink multicast groups - backwards compatibility for userspace */ #define RTMGRP_LINK 1 @@ -540,6 +569,8 @@ enum rtnetlink_groups { #define RTNLGRP_IPV6_PREFIX RTNLGRP_IPV6_PREFIX RTNLGRP_IPV6_RULE, #define RTNLGRP_IPV6_RULE RTNLGRP_IPV6_RULE + RTNLGRP_ND_USEROPT, +#define RTNLGRP_ND_USEROPT RTNLGRP_ND_USEROPT __RTNLGRP_MAX }; #define RTNLGRP_MAX (__RTNLGRP_MAX - 1) diff --git a/include/linux/sched.h b/include/linux/sched.h index 731edaca8ffd..833f7dc2b8de 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -27,6 +27,7 @@ #define CLONE_NEWUTS 0x04000000 /* New utsname group? */ #define CLONE_NEWIPC 0x08000000 /* New ipcs */ #define CLONE_NEWUSER 0x10000000 /* New user namespace */ +#define CLONE_NEWNET 0x40000000 /* New network namespace */ /* * Scheduling policies @@ -113,7 +114,7 @@ extern unsigned long avenrun[]; /* Load averages */ #define FSHIFT 11 /* nr of bits of precision */ #define FIXED_1 (1<<FSHIFT) /* 1.0 as fixed-point */ -#define LOAD_FREQ (5*HZ) /* 5 sec intervals */ +#define LOAD_FREQ (5*HZ+1) /* 5 sec intervals */ #define EXP_1 1884 /* 1/exp(5sec/1min) as fixed-point */ #define EXP_5 2014 /* 1/exp(5sec/5min) */ #define EXP_15 2037 /* 1/exp(5sec/15min) */ @@ -139,7 +140,7 @@ struct cfs_rq; extern void proc_sched_show_task(struct task_struct *p, struct seq_file *m); extern void proc_sched_set_task(struct task_struct *p); extern void -print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now); +print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq); #else static inline void proc_sched_show_task(struct task_struct *p, struct seq_file *m) @@ -149,7 +150,7 @@ static inline void proc_sched_set_task(struct task_struct *p) { } static inline void -print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now) +print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) { } #endif @@ -345,6 +346,27 @@ typedef unsigned long mm_counter_t; (mm)->hiwater_vm = (mm)->total_vm; \ } while (0) +extern void set_dumpable(struct mm_struct *mm, int value); +extern int get_dumpable(struct mm_struct *mm); + +/* mm flags */ +/* dumpable bits */ +#define MMF_DUMPABLE 0 /* core dump is permitted */ +#define MMF_DUMP_SECURELY 1 /* core file is readable only by root */ +#define MMF_DUMPABLE_BITS 2 + +/* coredump filter bits */ +#define MMF_DUMP_ANON_PRIVATE 2 +#define MMF_DUMP_ANON_SHARED 3 +#define MMF_DUMP_MAPPED_PRIVATE 4 +#define MMF_DUMP_MAPPED_SHARED 5 +#define MMF_DUMP_FILTER_SHIFT MMF_DUMPABLE_BITS +#define MMF_DUMP_FILTER_BITS 4 +#define MMF_DUMP_FILTER_MASK \ + (((1 << MMF_DUMP_FILTER_BITS) - 1) << MMF_DUMP_FILTER_SHIFT) +#define MMF_DUMP_FILTER_DEFAULT \ + ((1 << MMF_DUMP_ANON_PRIVATE) | (1 << MMF_DUMP_ANON_SHARED)) + struct mm_struct { struct vm_area_struct * mmap; /* list of VMAs */ struct rb_root mm_rb; @@ -402,7 +424,7 @@ struct mm_struct { unsigned int token_priority; unsigned int last_interval; - unsigned char dumpable:2; + unsigned long flags; /* Must use atomic bitops to access the bits */ /* coredumping support */ int core_waiters; @@ -417,7 +439,7 @@ struct sighand_struct { atomic_t count; struct k_sigaction action[_NSIG]; spinlock_t siglock; - struct list_head signalfd_list; + wait_queue_head_t signalfd_wqh; }; struct pacct_struct { @@ -572,7 +594,7 @@ struct user_struct { #endif /* Hash table maintenance information */ - struct list_head uidhash_list; + struct hlist_node uidhash_node; uid_t uid; }; @@ -660,7 +682,7 @@ enum cpu_idle_type { #define SCHED_LOAD_SHIFT 10 #define SCHED_LOAD_SCALE (1L << SCHED_LOAD_SHIFT) -#define SCHED_LOAD_SCALE_FUZZ (SCHED_LOAD_SCALE >> 5) +#define SCHED_LOAD_SCALE_FUZZ SCHED_LOAD_SCALE #ifdef CONFIG_SMP #define SD_LOAD_BALANCE 1 /* Do load balancing on this domain. */ @@ -713,7 +735,6 @@ struct sched_domain { unsigned long max_interval; /* Maximum balance interval ms */ unsigned int busy_factor; /* less balancing by factor if busy */ unsigned int imbalance_pct; /* No balance until over watermark */ - unsigned long long cache_hot_time; /* Task considered cache hot (ns) */ unsigned int cache_nice_tries; /* Leave cache hot tasks for # tries */ unsigned int busy_idx; unsigned int idle_idx; @@ -765,6 +786,22 @@ extern int partition_sched_domains(cpumask_t *partition1, #endif /* CONFIG_SMP */ +/* + * A runqueue laden with a single nice 0 task scores a weighted_cpuload of + * SCHED_LOAD_SCALE. This function returns 1 if any cpu is laden with a + * task of nice 0 or enough lower priority tasks to bring up the + * weighted_cpuload + */ +static inline int above_background_load(void) +{ + unsigned long cpu; + + for_each_online_cpu(cpu) { + if (weighted_cpuload(cpu) >= SCHED_LOAD_SCALE) + return 1; + } + return 0; +} struct io_context; /* See blkdev.h */ struct cpuset; @@ -819,22 +856,20 @@ struct sched_domain; struct sched_class { struct sched_class *next; - void (*enqueue_task) (struct rq *rq, struct task_struct *p, - int wakeup, u64 now); - void (*dequeue_task) (struct rq *rq, struct task_struct *p, - int sleep, u64 now); + void (*enqueue_task) (struct rq *rq, struct task_struct *p, int wakeup); + void (*dequeue_task) (struct rq *rq, struct task_struct *p, int sleep); void (*yield_task) (struct rq *rq, struct task_struct *p); void (*check_preempt_curr) (struct rq *rq, struct task_struct *p); - struct task_struct * (*pick_next_task) (struct rq *rq, u64 now); - void (*put_prev_task) (struct rq *rq, struct task_struct *p, u64 now); + struct task_struct * (*pick_next_task) (struct rq *rq); + void (*put_prev_task) (struct rq *rq, struct task_struct *p); - int (*load_balance) (struct rq *this_rq, int this_cpu, + unsigned long (*load_balance) (struct rq *this_rq, int this_cpu, struct rq *busiest, unsigned long max_nr_move, unsigned long max_load_move, struct sched_domain *sd, enum cpu_idle_type idle, - int *all_pinned, unsigned long *total_load_moved); + int *all_pinned, int *this_best_prio); void (*set_curr_task) (struct rq *rq); void (*task_tick) (struct rq *rq, struct task_struct *p); @@ -868,23 +903,29 @@ struct sched_entity { struct rb_node run_node; unsigned int on_rq; + u64 exec_start; + u64 sum_exec_runtime; + u64 prev_sum_exec_runtime; u64 wait_start_fair; + u64 sleep_start_fair; + +#ifdef CONFIG_SCHEDSTATS u64 wait_start; - u64 exec_start; + u64 wait_max; + s64 sum_wait_runtime; + u64 sleep_start; - u64 sleep_start_fair; - u64 block_start; u64 sleep_max; + s64 sum_sleep_runtime; + + u64 block_start; u64 block_max; u64 exec_max; - u64 wait_max; - u64 last_ran; - u64 sum_exec_runtime; - s64 sum_wait_runtime; - s64 sum_sleep_runtime; unsigned long wait_runtime_overruns; unsigned long wait_runtime_underruns; +#endif + #ifdef CONFIG_FAIR_GROUP_SCHED struct sched_entity *parent; /* rq on which this entity is (to be) queued: */ @@ -914,6 +955,11 @@ struct task_struct { struct sched_class *sched_class; struct sched_entity se; +#ifdef CONFIG_PREEMPT_NOTIFIERS + /* list of struct preempt_notifier: */ + struct hlist_head preempt_notifiers; +#endif + unsigned short ioprio; #ifdef CONFIG_BLK_DEV_IO_TRACE unsigned int btrace_seq; @@ -1327,6 +1373,13 @@ static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask) #endif extern unsigned long long sched_clock(void); + +/* + * For kernel-internal use: high-speed (but slightly incorrect) per-cpu + * clock constructed from sched_clock(): + */ +extern unsigned long long cpu_clock(int cpu); + extern unsigned long long task_sched_runtime(struct task_struct *task); @@ -1337,7 +1390,8 @@ extern void sched_exec(void); #define sched_exec() {} #endif -extern void sched_clock_unstable_event(void); +extern void sched_clock_idle_sleep_event(void); +extern void sched_clock_idle_wakeup_event(u64 delta_ns); #ifdef CONFIG_HOTPLUG_CPU extern void idle_task_exit(void); @@ -1347,11 +1401,13 @@ static inline void idle_task_exit(void) {} extern void sched_idle_next(void); -extern unsigned int sysctl_sched_granularity; +extern unsigned int sysctl_sched_latency; +extern unsigned int sysctl_sched_min_granularity; extern unsigned int sysctl_sched_wakeup_granularity; extern unsigned int sysctl_sched_batch_wakeup_granularity; extern unsigned int sysctl_sched_stat_granularity; extern unsigned int sysctl_sched_runtime_limit; +extern unsigned int sysctl_sched_compat_yield; extern unsigned int sysctl_sched_child_runs_first; extern unsigned int sysctl_sched_features; @@ -1418,6 +1474,7 @@ static inline struct user_struct *get_uid(struct user_struct *u) } extern void free_uid(struct user_struct *); extern void switch_uid(struct user_struct *); +extern void release_uids(struct user_namespace *ns); #include <asm/current.h> diff --git a/include/linux/sctp.h b/include/linux/sctp.h index d70df61a029f..5eb38cc0e5a4 100644 --- a/include/linux/sctp.h +++ b/include/linux/sctp.h @@ -102,6 +102,9 @@ typedef enum { SCTP_CID_ECN_CWR = 13, SCTP_CID_SHUTDOWN_COMPLETE = 14, + /* AUTH Extension Section 4.1 */ + SCTP_CID_AUTH = 0x0F, + /* PR-SCTP Sec 3.2 */ SCTP_CID_FWD_TSN = 0xC0, @@ -180,6 +183,14 @@ typedef enum { SCTP_PARAM_SUPPORTED_ADDRESS_TYPES = __constant_htons(12), SCTP_PARAM_ECN_CAPABLE = __constant_htons(0x8000), + /* AUTH Extension Section 3 */ + SCTP_PARAM_RANDOM = __constant_htons(0x8002), + SCTP_PARAM_CHUNKS = __constant_htons(0x8003), + SCTP_PARAM_HMAC_ALGO = __constant_htons(0x8004), + + /* Add-IP: Supported Extensions, Section 4.2 */ + SCTP_PARAM_SUPPORTED_EXT = __constant_htons(0x8008), + /* PR-SCTP Sec 3.1 */ SCTP_PARAM_FWD_TSN_SUPPORT = __constant_htons(0xc000), @@ -296,6 +307,30 @@ typedef struct sctp_adaptation_ind_param { __be32 adaptation_ind; } __attribute__((packed)) sctp_adaptation_ind_param_t; +/* ADDIP Section 4.2.7 Supported Extensions Parameter */ +typedef struct sctp_supported_ext_param { + struct sctp_paramhdr param_hdr; + __u8 chunks[0]; +} __attribute__((packed)) sctp_supported_ext_param_t; + +/* AUTH Section 3.1 Random */ +typedef struct sctp_random_param { + sctp_paramhdr_t param_hdr; + __u8 random_val[0]; +} __attribute__((packed)) sctp_random_param_t; + +/* AUTH Section 3.2 Chunk List */ +typedef struct sctp_chunks_param { + sctp_paramhdr_t param_hdr; + __u8 chunks[0]; +} __attribute__((packed)) sctp_chunks_param_t; + +/* AUTH Section 3.3 HMAC Algorithm */ +typedef struct sctp_hmac_algo_param { + sctp_paramhdr_t param_hdr; + __be16 hmac_ids[0]; +} __attribute__((packed)) sctp_hmac_algo_param_t; + /* RFC 2960. Section 3.3.3 Initiation Acknowledgement (INIT ACK) (2): * The INIT ACK chunk is used to acknowledge the initiation of an SCTP * association. @@ -462,7 +497,19 @@ typedef enum { SCTP_ERROR_RSRC_LOW = __constant_htons(0x0101), SCTP_ERROR_DEL_SRC_IP = __constant_htons(0x0102), SCTP_ERROR_ASCONF_ACK = __constant_htons(0x0103), - SCTP_ERROR_REQ_REFUSED = __constant_htons(0x0104) + SCTP_ERROR_REQ_REFUSED = __constant_htons(0x0104), + + /* AUTH Section 4. New Error Cause + * + * This section defines a new error cause that will be sent if an AUTH + * chunk is received with an unsupported HMAC identifier. + * illustrates the new error cause. + * + * Cause Code Error Cause Name + * -------------------------------------------------------------- + * 0x0105 Unsupported HMAC Identifier + */ + SCTP_ERROR_UNSUP_HMAC = __constant_htons(0x0105) } sctp_error_t; @@ -600,4 +647,64 @@ typedef struct sctp_addip_chunk { sctp_addiphdr_t addip_hdr; } __attribute__((packed)) sctp_addip_chunk_t; +/* AUTH + * Section 4.1 Authentication Chunk (AUTH) + * + * This chunk is used to hold the result of the HMAC calculation. + * + * 0 1 2 3 + * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Type = 0x0F | Flags=0 | Length | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Shared Key Identifier | HMAC Identifier | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | + * \ HMAC / + * / \ + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * Type: 1 byte (unsigned integer) + * This value MUST be set to 0x0F for all AUTH-chunks. + * + * Flags: 1 byte (unsigned integer) + * Set to zero on transmit and ignored on receipt. + * + * Length: 2 bytes (unsigned integer) + * This value holds the length of the HMAC in bytes plus 8. + * + * Shared Key Identifier: 2 bytes (unsigned integer) + * This value describes which endpoint pair shared key is used. + * + * HMAC Identifier: 2 bytes (unsigned integer) + * This value describes which message digest is being used. Table 2 + * shows the currently defined values. + * + * The following Table 2 shows the currently defined values for HMAC + * identifiers. + * + * +-----------------+--------------------------+ + * | HMAC Identifier | Message Digest Algorithm | + * +-----------------+--------------------------+ + * | 0 | Reserved | + * | 1 | SHA-1 defined in [8] | + * | 2 | Reserved | + * | 3 | SHA-256 defined in [8] | + * +-----------------+--------------------------+ + * + * + * HMAC: n bytes (unsigned integer) This hold the result of the HMAC + * calculation. + */ +typedef struct sctp_authhdr { + __be16 shkey_id; + __be16 hmac_id; + __u8 hmac[0]; +} __attribute__((packed)) sctp_authhdr_t; + +typedef struct sctp_auth_chunk { + sctp_chunkhdr_t chunk_hdr; + sctp_authhdr_t auth_hdr; +} __attribute__((packed)) sctp_auth_chunk_t; + #endif /* __LINUX_SCTP_H__ */ diff --git a/include/linux/security.h b/include/linux/security.h index c11dc8aa0351..1a15526e9f67 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -54,7 +54,7 @@ extern int cap_inode_removexattr(struct dentry *dentry, char *name); extern int cap_task_post_setuid (uid_t old_ruid, uid_t old_euid, uid_t old_suid, int flags); extern void cap_task_reparent_to_init (struct task_struct *p); extern int cap_syslog (int type); -extern int cap_vm_enough_memory (long pages); +extern int cap_vm_enough_memory (struct mm_struct *mm, long pages); struct msghdr; struct sk_buff; @@ -1125,6 +1125,7 @@ struct request_sock; * Return 0 if permission is granted. * @vm_enough_memory: * Check permissions for allocating a new virtual mapping. + * @mm contains the mm struct it is being added to. * @pages contains the number of pages. * Return 0 if permission is granted. * @@ -1169,7 +1170,7 @@ struct security_operations { int (*quota_on) (struct dentry * dentry); int (*syslog) (int type); int (*settime) (struct timespec *ts, struct timezone *tz); - int (*vm_enough_memory) (long pages); + int (*vm_enough_memory) (struct mm_struct *mm, long pages); int (*bprm_alloc_security) (struct linux_binprm * bprm); void (*bprm_free_security) (struct linux_binprm * bprm); @@ -1469,10 +1470,14 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz) return security_ops->settime(ts, tz); } - static inline int security_vm_enough_memory(long pages) { - return security_ops->vm_enough_memory(pages); + return security_ops->vm_enough_memory(current->mm, pages); +} + +static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages) +{ + return security_ops->vm_enough_memory(mm, pages); } static inline int security_bprm_alloc (struct linux_binprm *bprm) @@ -2219,7 +2224,12 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz) static inline int security_vm_enough_memory(long pages) { - return cap_vm_enough_memory(pages); + return cap_vm_enough_memory(current->mm, pages); +} + +static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages) +{ + return cap_vm_enough_memory(mm, pages); } static inline int security_bprm_alloc (struct linux_binprm *bprm) diff --git a/include/linux/selection.h b/include/linux/selection.h index ed3408b400f1..f9457861937c 100644 --- a/include/linux/selection.h +++ b/include/linux/selection.h @@ -10,6 +10,8 @@ #include <linux/tiocl.h> #include <linux/vt_buffer.h> +struct tty_struct; + extern struct vc_data *sel_cons; extern void clear_selection(void); diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h index 83783ab0f552..8bf1e05115b4 100644 --- a/include/linux/seq_file.h +++ b/include/linux/seq_file.h @@ -46,6 +46,8 @@ int seq_path(struct seq_file *, struct vfsmount *, struct dentry *, char *); int single_open(struct file *, int (*)(struct seq_file *, void *), void *); int single_release(struct inode *, struct file *); +void *__seq_open_private(struct file *, const struct seq_operations *, int); +int seq_open_private(struct file *, const struct seq_operations *, int); int seq_release_private(struct inode *, struct file *); #define SEQ_START_TOKEN ((void *)1) diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index 706ee9a4c80c..afe0f6d9b9bc 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -20,7 +20,7 @@ struct plat_serial8250_port { unsigned long iobase; /* io base address */ void __iomem *membase; /* ioremap cookie or NULL */ - unsigned long mapbase; /* resource base */ + resource_size_t mapbase; /* resource base */ unsigned int irq; /* interrupt number */ unsigned int uartclk; /* UART clock rate */ unsigned char regshift; /* register shift */ @@ -60,6 +60,8 @@ void serial8250_unregister_port(int line); void serial8250_suspend_port(int line); void serial8250_resume_port(int line); +extern int early_serial_setup(struct uart_port *port); + extern int serial8250_find_port(struct uart_port *p); extern int serial8250_find_port_for_earlycon(void); extern int setup_early_serial8250_console(char *cmdline); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 9c721cd2c9d6..09d17b06bf02 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -62,8 +62,9 @@ /* NEC v850. */ #define PORT_V850E_UART 40 -/* DZ */ -#define PORT_DZ 47 +/* DEC */ +#define PORT_DZ 46 +#define PORT_ZS 47 /* Parisc type numbers. */ #define PORT_MUX 48 @@ -287,7 +288,7 @@ struct uart_port { const struct uart_ops *ops; unsigned int custom_divisor; unsigned int line; /* port index */ - unsigned long mapbase; /* for ioremap */ + resource_size_t mapbase; /* for ioremap */ struct device *dev; /* parent device */ unsigned char hub6; /* this should be in the 8250 driver */ unsigned char unused[3]; diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 1c5ed7d92b0f..96c0d93fc2ca 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -118,6 +118,7 @@ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ #define UART_MSR 6 /* In: Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ diff --git a/include/linux/signal.h b/include/linux/signal.h index ea91abe740da..0ae338866240 100644 --- a/include/linux/signal.h +++ b/include/linux/signal.h @@ -237,12 +237,15 @@ extern int group_send_sig_info(int sig, struct siginfo *info, struct task_struct extern int __group_send_sig_info(int, struct siginfo *, struct task_struct *); extern long do_sigpending(void __user *, unsigned long); extern int sigprocmask(int, sigset_t *, sigset_t *); +extern int show_unhandled_signals; struct pt_regs; extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie); extern struct kmem_cache *sighand_cachep; +int unhandled_signal(struct task_struct *tsk, int sig); + /* * In POSIX a signal is sent either to a specific thread (Linux task) * or to the process as a whole (Linux thread group). How the signal diff --git a/include/linux/signalfd.h b/include/linux/signalfd.h index 510429495690..4c9ff0910ae0 100644 --- a/include/linux/signalfd.h +++ b/include/linux/signalfd.h @@ -45,49 +45,17 @@ struct signalfd_siginfo { #ifdef CONFIG_SIGNALFD /* - * Deliver the signal to listening signalfd. This must be called - * with the sighand lock held. Same are the following that end up - * calling signalfd_deliver(). - */ -void signalfd_deliver(struct task_struct *tsk, int sig); - -/* - * No need to fall inside signalfd_deliver() if no signal listeners - * are available. + * Deliver the signal to listening signalfd. */ static inline void signalfd_notify(struct task_struct *tsk, int sig) { - if (unlikely(!list_empty(&tsk->sighand->signalfd_list))) - signalfd_deliver(tsk, sig); -} - -/* - * The signal -1 is used to notify the signalfd that the sighand - * is on its way to be detached. - */ -static inline void signalfd_detach_locked(struct task_struct *tsk) -{ - if (unlikely(!list_empty(&tsk->sighand->signalfd_list))) - signalfd_deliver(tsk, -1); -} - -static inline void signalfd_detach(struct task_struct *tsk) -{ - struct sighand_struct *sighand = tsk->sighand; - - if (unlikely(!list_empty(&sighand->signalfd_list))) { - spin_lock_irq(&sighand->siglock); - signalfd_deliver(tsk, -1); - spin_unlock_irq(&sighand->siglock); - } + if (unlikely(waitqueue_active(&tsk->sighand->signalfd_wqh))) + wake_up(&tsk->sighand->signalfd_wqh); } #else /* CONFIG_SIGNALFD */ -#define signalfd_deliver(t, s) do { } while (0) -#define signalfd_notify(t, s) do { } while (0) -#define signalfd_detach_locked(t) do { } while (0) -#define signalfd_detach(t) do { } while (0) +static inline void signalfd_notify(struct task_struct *tsk, int sig) { } #endif /* CONFIG_SIGNALFD */ diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index ce256438e619..a656cecd373c 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -134,8 +134,8 @@ typedef struct skb_frag_struct skb_frag_t; struct skb_frag_struct { struct page *page; - __u16 page_offset; - __u16 size; + __u32 page_offset; + __u32 size; }; /* This data is invariant across clones and lives at @@ -1352,6 +1352,22 @@ static inline int skb_clone_writable(struct sk_buff *skb, int len) skb_headroom(skb) + len <= skb->hdr_len; } +static inline int __skb_cow(struct sk_buff *skb, unsigned int headroom, + int cloned) +{ + int delta = 0; + + if (headroom < NET_SKB_PAD) + headroom = NET_SKB_PAD; + if (headroom > skb_headroom(skb)) + delta = headroom - skb_headroom(skb); + + if (delta || cloned) + return pskb_expand_head(skb, ALIGN(delta, NET_SKB_PAD), 0, + GFP_ATOMIC); + return 0; +} + /** * skb_cow - copy header of skb when it is required * @skb: buffer to cow @@ -1366,16 +1382,22 @@ static inline int skb_clone_writable(struct sk_buff *skb, int len) */ static inline int skb_cow(struct sk_buff *skb, unsigned int headroom) { - int delta = (headroom > NET_SKB_PAD ? headroom : NET_SKB_PAD) - - skb_headroom(skb); - - if (delta < 0) - delta = 0; + return __skb_cow(skb, headroom, skb_cloned(skb)); +} - if (delta || skb_cloned(skb)) - return pskb_expand_head(skb, (delta + (NET_SKB_PAD-1)) & - ~(NET_SKB_PAD-1), 0, GFP_ATOMIC); - return 0; +/** + * skb_cow_head - skb_cow but only making the head writable + * @skb: buffer to cow + * @headroom: needed headroom + * + * This function is identical to skb_cow except that we replace the + * skb_cloned check by skb_header_cloned. It should be used when + * you only need to push on some header and do not need to modify + * the data. + */ +static inline int skb_cow_head(struct sk_buff *skb, unsigned int headroom) +{ + return __skb_cow(skb, headroom, skb_header_cloned(skb)); } /** diff --git a/include/linux/slab.h b/include/linux/slab.h index 0e1d0daef6a2..d859354b9e51 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -40,7 +40,7 @@ */ #define ZERO_SIZE_PTR ((void *)16) -#define ZERO_OR_NULL_PTR(x) ((unsigned long)(x) < \ +#define ZERO_OR_NULL_PTR(x) ((unsigned long)(x) <= \ (unsigned long)ZERO_SIZE_PTR) /* @@ -51,7 +51,6 @@ int slab_is_available(void); struct kmem_cache *kmem_cache_create(const char *, size_t, size_t, unsigned long, - void (*)(void *, struct kmem_cache *, unsigned long), void (*)(void *, struct kmem_cache *, unsigned long)); void kmem_cache_destroy(struct kmem_cache *); int kmem_cache_shrink(struct kmem_cache *); @@ -70,7 +69,7 @@ int kmem_ptr_validate(struct kmem_cache *cachep, const void *ptr); */ #define KMEM_CACHE(__struct, __flags) kmem_cache_create(#__struct,\ sizeof(struct __struct), __alignof__(struct __struct),\ - (__flags), NULL, NULL) + (__flags), NULL) /* * The largest kmalloc size supported by the slab allocators is diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h index 07f7e4cbcee3..74962077f632 100644 --- a/include/linux/slub_def.h +++ b/include/linux/slub_def.h @@ -78,7 +78,7 @@ extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_HIGH + 1]; * Sorry that the following has to be that ugly but some versions of GCC * have trouble with constant propagation and loops. */ -static inline int kmalloc_index(size_t size) +static __always_inline int kmalloc_index(size_t size) { if (!size) return 0; @@ -133,7 +133,7 @@ static inline int kmalloc_index(size_t size) * This ought to end up with a global pointer to the right cache * in kmalloc_caches. */ -static inline struct kmem_cache *kmalloc_slab(size_t size) +static __always_inline struct kmem_cache *kmalloc_slab(size_t size) { int index = kmalloc_index(size); @@ -160,13 +160,13 @@ static inline struct kmem_cache *kmalloc_slab(size_t size) #define SLUB_DMA __GFP_DMA #else /* Disable DMA functionality */ -#define SLUB_DMA 0 +#define SLUB_DMA (__force gfp_t)0 #endif void *kmem_cache_alloc(struct kmem_cache *, gfp_t); void *__kmalloc(size_t size, gfp_t flags); -static inline void *kmalloc(size_t size, gfp_t flags) +static __always_inline void *kmalloc(size_t size, gfp_t flags) { if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { struct kmem_cache *s = kmalloc_slab(size); @@ -183,7 +183,7 @@ static inline void *kmalloc(size_t size, gfp_t flags) void *__kmalloc_node(size_t size, gfp_t flags, int node); void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); -static inline void *kmalloc_node(size_t size, gfp_t flags, int node) +static __always_inline void *kmalloc_node(size_t size, gfp_t flags, int node) { if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { struct kmem_cache *s = kmalloc_slab(size); diff --git a/include/linux/snmp.h b/include/linux/snmp.h index 802b3a38b041..89f0c2b5f405 100644 --- a/include/linux/snmp.h +++ b/include/linux/snmp.h @@ -82,6 +82,8 @@ enum __ICMP_MIB_MAX }; +#define __ICMPMSG_MIB_MAX 512 /* Out+In for all 8-bit ICMP types */ + /* icmp6 mib definitions */ /* * RFC 2466: ICMPv6-MIB @@ -91,35 +93,12 @@ enum ICMP6_MIB_NUM = 0, ICMP6_MIB_INMSGS, /* InMsgs */ ICMP6_MIB_INERRORS, /* InErrors */ - ICMP6_MIB_INDESTUNREACHS, /* InDestUnreachs */ - ICMP6_MIB_INPKTTOOBIGS, /* InPktTooBigs */ - ICMP6_MIB_INTIMEEXCDS, /* InTimeExcds */ - ICMP6_MIB_INPARMPROBLEMS, /* InParmProblems */ - ICMP6_MIB_INECHOS, /* InEchos */ - ICMP6_MIB_INECHOREPLIES, /* InEchoReplies */ - ICMP6_MIB_INGROUPMEMBQUERIES, /* InGroupMembQueries */ - ICMP6_MIB_INGROUPMEMBRESPONSES, /* InGroupMembResponses */ - ICMP6_MIB_INGROUPMEMBREDUCTIONS, /* InGroupMembReductions */ - ICMP6_MIB_INROUTERSOLICITS, /* InRouterSolicits */ - ICMP6_MIB_INROUTERADVERTISEMENTS, /* InRouterAdvertisements */ - ICMP6_MIB_INNEIGHBORSOLICITS, /* InNeighborSolicits */ - ICMP6_MIB_INNEIGHBORADVERTISEMENTS, /* InNeighborAdvertisements */ - ICMP6_MIB_INREDIRECTS, /* InRedirects */ ICMP6_MIB_OUTMSGS, /* OutMsgs */ - ICMP6_MIB_OUTDESTUNREACHS, /* OutDestUnreachs */ - ICMP6_MIB_OUTPKTTOOBIGS, /* OutPktTooBigs */ - ICMP6_MIB_OUTTIMEEXCDS, /* OutTimeExcds */ - ICMP6_MIB_OUTPARMPROBLEMS, /* OutParmProblems */ - ICMP6_MIB_OUTECHOREPLIES, /* OutEchoReplies */ - ICMP6_MIB_OUTROUTERSOLICITS, /* OutRouterSolicits */ - ICMP6_MIB_OUTNEIGHBORSOLICITS, /* OutNeighborSolicits */ - ICMP6_MIB_OUTNEIGHBORADVERTISEMENTS, /* OutNeighborAdvertisements */ - ICMP6_MIB_OUTREDIRECTS, /* OutRedirects */ - ICMP6_MIB_OUTGROUPMEMBRESPONSES, /* OutGroupMembResponses */ - ICMP6_MIB_OUTGROUPMEMBREDUCTIONS, /* OutGroupMembReductions */ __ICMP6_MIB_MAX }; +#define __ICMP6MSG_MIB_MAX 512 /* Out+In for all 8-bit ICMPv6 types */ + /* tcp mib definitions */ /* * RFC 1213: MIB-II TCP group @@ -231,6 +210,10 @@ enum LINUX_MIB_TCPABORTONLINGER, /* TCPAbortOnLinger */ LINUX_MIB_TCPABORTFAILED, /* TCPAbortFailed */ LINUX_MIB_TCPMEMORYPRESSURES, /* TCPMemoryPressures */ + LINUX_MIB_TCPSACKDISCARD, /* TCPSACKDiscard */ + LINUX_MIB_TCPDSACKIGNOREDOLD, /* TCPSACKIgnoredOld */ + LINUX_MIB_TCPDSACKIGNOREDNOUNDO, /* TCPSACKIgnoredNoUndo */ + LINUX_MIB_TCPSPURIOUSRTOS, /* TCPSpuriousRTOs */ __LINUX_MIB_MAX }; diff --git a/include/linux/spi/mmc_spi.h b/include/linux/spi/mmc_spi.h new file mode 100644 index 000000000000..e9bbe3ebd721 --- /dev/null +++ b/include/linux/spi/mmc_spi.h @@ -0,0 +1,33 @@ +#ifndef __LINUX_SPI_MMC_SPI_H +#define __LINUX_SPI_MMC_SPI_H + +struct device; +struct mmc_host; + +/* Put this in platform_data of a device being used to manage an MMC/SD + * card slot. (Modeled after PXA mmc glue; see that for usage examples.) + * + * REVISIT This is not a spi-specific notion. Any card slot should be + * able to handle it. If the MMC core doesn't adopt this kind of notion, + * switch the "struct device *" parameters over to "struct spi_device *". + */ +struct mmc_spi_platform_data { + /* driver activation and (optional) card detect irq hookup */ + int (*init)(struct device *, + irqreturn_t (*)(int, void *), + void *); + void (*exit)(struct device *, void *); + + /* sense switch on sd cards */ + int (*get_ro)(struct device *); + + /* how long to debounce card detect, in msecs */ + u16 detect_delay; + + /* power management */ + u16 powerup_msecs; /* delay of up to 250 msec */ + u32 ocr_mask; /* available voltages */ + void (*setpower)(struct device *, unsigned int maskval); +}; + +#endif /* __LINUX_SPI_MMC_SPI_H */ diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 302b81d1d117..002a3cddbdd5 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -77,6 +77,7 @@ struct spi_device { #define SPI_CS_HIGH 0x04 /* chipselect active high? */ #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ #define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ u8 bits_per_word; int irq; void *controller_state; @@ -138,6 +139,32 @@ struct spi_message; +/** + * struct spi_driver - Host side "protocol" driver + * @probe: Binds this driver to the spi device. Drivers can verify + * that the device is actually present, and may need to configure + * characteristics (such as bits_per_word) which weren't needed for + * the initial configuration done during system setup. + * @remove: Unbinds this driver from the spi device + * @shutdown: Standard shutdown callback used during system state + * transitions such as powerdown/halt and kexec + * @suspend: Standard suspend callback used during system state transitions + * @resume: Standard resume callback used during system state transitions + * @driver: SPI device drivers should initialize the name and owner + * field of this structure. + * + * This represents the kind of device driver that uses SPI messages to + * interact with the hardware at the other end of a SPI link. It's called + * a "protocol" driver because it works through messages rather than talking + * directly to SPI hardware (which is what the underlying SPI controller + * driver does to pass those messages). These protocols are defined in the + * specification for the device(s) supported by the driver. + * + * As a rule, those device protocols represent the lowest level interface + * supported by a driver, and it will support upper level interfaces too. + * Examples of such upper levels include frameworks like MTD, networking, + * MMC, RTC, filesystem character device nodes, and hardware monitoring. + */ struct spi_driver { int (*probe)(struct spi_device *spi); int (*remove)(struct spi_device *spi); @@ -667,7 +694,37 @@ static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) * parport adapters, or microcontrollers acting as USB-to-SPI bridges. */ -/* board-specific information about each SPI device */ +/** + * struct spi_board_info - board-specific template for a SPI device + * @modalias: Initializes spi_device.modalias; identifies the driver. + * @platform_data: Initializes spi_device.platform_data; the particular + * data stored there is driver-specific. + * @controller_data: Initializes spi_device.controller_data; some + * controllers need hints about hardware setup, e.g. for DMA. + * @irq: Initializes spi_device.irq; depends on how the board is wired. + * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits + * from the chip datasheet and board-specific signal quality issues. + * @bus_num: Identifies which spi_master parents the spi_device; unused + * by spi_new_device(), and otherwise depends on board wiring. + * @chip_select: Initializes spi_device.chip_select; depends on how + * the board is wired. + * @mode: Initializes spi_device.mode; based on the chip datasheet, board + * wiring (some devices support both 3WIRE and standard modes), and + * possibly presence of an inverter in the chipselect path. + * + * When adding new SPI devices to the device tree, these structures serve + * as a partial device template. They hold information which can't always + * be determined by drivers. Information that probe() can establish (such + * as the default transfer wordsize) is not included here. + * + * These structures are used in two places. Their primary role is to + * be stored in tables of board-specific device descriptors, which are + * declared early in board initialization and then used (much later) to + * populate a controller's device tree after the that controller's driver + * initializes. A secondary (and atypical) role is as a parameter to + * spi_new_device() call, which happens after those controller drivers + * are active in some dynamic board configuration models. + */ struct spi_board_info { /* the device name and module name are coupled, like platform_bus; * "modalias" is normally the driver name. diff --git a/include/linux/spi/spidev.h b/include/linux/spi/spidev.h index 7d700be57490..c93ef9d42a01 100644 --- a/include/linux/spi/spidev.h +++ b/include/linux/spi/spidev.h @@ -35,6 +35,10 @@ #define SPI_MODE_2 (SPI_CPOL|0) #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 +#define SPI_LSB_FIRST 0x08 +#define SPI_3WIRE 0x10 +#define SPI_LOOP 0x20 /*---------------------------------------------------------------------------*/ diff --git a/include/linux/spinlock_types.h b/include/linux/spinlock_types.h index 210549ba4ef4..f6a3a951b79e 100644 --- a/include/linux/spinlock_types.h +++ b/include/linux/spinlock_types.h @@ -9,14 +9,14 @@ * Released under the General Public License (GPL). */ -#include <linux/lockdep.h> - #if defined(CONFIG_SMP) # include <asm/spinlock_types.h> #else # include <linux/spinlock_types_up.h> #endif +#include <linux/lockdep.h> + typedef struct { raw_spinlock_t raw_lock; #if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) diff --git a/include/linux/spinlock_types_up.h b/include/linux/spinlock_types_up.h index 27644af20b7c..04135b0e198e 100644 --- a/include/linux/spinlock_types_up.h +++ b/include/linux/spinlock_types_up.h @@ -12,14 +12,10 @@ * Released under the General Public License (GPL). */ -#if defined(CONFIG_DEBUG_SPINLOCK) || \ - defined(CONFIG_DEBUG_LOCK_ALLOC) +#ifdef CONFIG_DEBUG_SPINLOCK typedef struct { volatile unsigned int slock; -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif } raw_spinlock_t; #define __RAW_SPIN_LOCK_UNLOCKED { 1 } @@ -34,9 +30,6 @@ typedef struct { } raw_spinlock_t; typedef struct { /* no debug version on UP */ -#ifdef CONFIG_DEBUG_LOCK_ALLOC - struct lockdep_map dep_map; -#endif } raw_rwlock_t; #define __RAW_RW_LOCK_UNLOCKED { } diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h new file mode 100644 index 000000000000..2b5c312c4960 --- /dev/null +++ b/include/linux/ssb/ssb.h @@ -0,0 +1,424 @@ +#ifndef LINUX_SSB_H_ +#define LINUX_SSB_H_ + +#include <linux/device.h> +#include <linux/list.h> +#include <linux/types.h> +#include <linux/spinlock.h> +#include <linux/pci.h> +#include <linux/mod_devicetable.h> + +#include <linux/ssb/ssb_regs.h> + + +struct pcmcia_device; +struct ssb_bus; +struct ssb_driver; + + +struct ssb_sprom_r1 { + u16 pci_spid; /* Subsystem Product ID for PCI */ + u16 pci_svid; /* Subsystem Vendor ID for PCI */ + u16 pci_pid; /* Product ID for PCI */ + u8 il0mac[6]; /* MAC address for 802.11b/g */ + u8 et0mac[6]; /* MAC address for Ethernet */ + u8 et1mac[6]; /* MAC address for 802.11a */ + u8 et0phyaddr:5; /* MII address for enet0 */ + u8 et1phyaddr:5; /* MII address for enet1 */ + u8 et0mdcport:1; /* MDIO for enet0 */ + u8 et1mdcport:1; /* MDIO for enet1 */ + u8 board_rev; /* Board revision */ + u8 country_code:4; /* Country Code */ + u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */ + u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */ + u16 pa0b0; + u16 pa0b1; + u16 pa0b2; + u16 pa1b0; + u16 pa1b1; + u16 pa1b2; + u8 gpio0; /* GPIO pin 0 */ + u8 gpio1; /* GPIO pin 1 */ + u8 gpio2; /* GPIO pin 2 */ + u8 gpio3; /* GPIO pin 3 */ + u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */ + u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */ + u8 itssi_a; /* Idle TSSI Target for A-PHY */ + u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ + u16 boardflags_lo; /* Boardflags (low 16 bits) */ + u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */ + u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ + u8 oem[8]; /* OEM string (rev 1 only) */ +}; + +struct ssb_sprom_r2 { + u16 boardflags_hi; /* Boardflags (high 16 bits) */ + u8 maxpwr_a_lo; /* A-PHY Max Power Low */ + u8 maxpwr_a_hi; /* A-PHY Max Power High */ + u16 pa1lob0; /* A-PHY PA Low Settings */ + u16 pa1lob1; /* A-PHY PA Low Settings */ + u16 pa1lob2; /* A-PHY PA Low Settings */ + u16 pa1hib0; /* A-PHY PA High Settings */ + u16 pa1hib1; /* A-PHY PA High Settings */ + u16 pa1hib2; /* A-PHY PA High Settings */ + u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */ + u8 country_str[2]; /* Two char Country Code */ +}; + +struct ssb_sprom_r3 { + u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */ + u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */ + u32 ofdmahpo; /* A-PHY OFDM High Power Offset */ + u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */ + u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */ + u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */ + u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */ + u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */ + u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */ + u32 ofdmgpo; /* G-PHY OFDM Power Offset */ +}; + +struct ssb_sprom_r4 { + /* TODO */ +}; + +struct ssb_sprom { + u8 revision; + u8 crc; + /* The valid r# fields are selected by the "revision". + * Revision 3 and lower inherit from lower revisions. + */ + union { + struct { + struct ssb_sprom_r1 r1; + struct ssb_sprom_r2 r2; + struct ssb_sprom_r3 r3; + }; + struct ssb_sprom_r4 r4; + }; +}; + +/* Information about the PCB the circuitry is soldered on. */ +struct ssb_boardinfo { + u16 vendor; + u16 type; + u16 rev; +}; + + +struct ssb_device; +/* Lowlevel read/write operations on the device MMIO. + * Internal, don't use that outside of ssb. */ +struct ssb_bus_ops { + u16 (*read16)(struct ssb_device *dev, u16 offset); + u32 (*read32)(struct ssb_device *dev, u16 offset); + void (*write16)(struct ssb_device *dev, u16 offset, u16 value); + void (*write32)(struct ssb_device *dev, u16 offset, u32 value); +}; + + +/* Core-ID values. */ +#define SSB_DEV_CHIPCOMMON 0x800 +#define SSB_DEV_ILINE20 0x801 +#define SSB_DEV_SDRAM 0x803 +#define SSB_DEV_PCI 0x804 +#define SSB_DEV_MIPS 0x805 +#define SSB_DEV_ETHERNET 0x806 +#define SSB_DEV_V90 0x807 +#define SSB_DEV_USB11_HOSTDEV 0x808 +#define SSB_DEV_ADSL 0x809 +#define SSB_DEV_ILINE100 0x80A +#define SSB_DEV_IPSEC 0x80B +#define SSB_DEV_PCMCIA 0x80D +#define SSB_DEV_INTERNAL_MEM 0x80E +#define SSB_DEV_MEMC_SDRAM 0x80F +#define SSB_DEV_EXTIF 0x811 +#define SSB_DEV_80211 0x812 +#define SSB_DEV_MIPS_3302 0x816 +#define SSB_DEV_USB11_HOST 0x817 +#define SSB_DEV_USB11_DEV 0x818 +#define SSB_DEV_USB20_HOST 0x819 +#define SSB_DEV_USB20_DEV 0x81A +#define SSB_DEV_SDIO_HOST 0x81B +#define SSB_DEV_ROBOSWITCH 0x81C +#define SSB_DEV_PARA_ATA 0x81D +#define SSB_DEV_SATA_XORDMA 0x81E +#define SSB_DEV_ETHERNET_GBIT 0x81F +#define SSB_DEV_PCIE 0x820 +#define SSB_DEV_MIMO_PHY 0x821 +#define SSB_DEV_SRAM_CTRLR 0x822 +#define SSB_DEV_MINI_MACPHY 0x823 +#define SSB_DEV_ARM_1176 0x824 +#define SSB_DEV_ARM_7TDMI 0x825 + +/* Vendor-ID values */ +#define SSB_VENDOR_BROADCOM 0x4243 + +/* Some kernel subsystems poke with dev->drvdata, so we must use the + * following ugly workaround to get from struct device to struct ssb_device */ +struct __ssb_dev_wrapper { + struct device dev; + struct ssb_device *sdev; +}; + +struct ssb_device { + /* Having a copy of the ops pointer in each dev struct + * is an optimization. */ + const struct ssb_bus_ops *ops; + + struct device *dev; + struct ssb_bus *bus; + struct ssb_device_id id; + + u8 core_index; + unsigned int irq; + + /* Internal-only stuff follows. */ + void *drvdata; /* Per-device data */ + void *devtypedata; /* Per-devicetype (eg 802.11) data */ +}; + +/* Go from struct device to struct ssb_device. */ +static inline +struct ssb_device * dev_to_ssb_dev(struct device *dev) +{ + struct __ssb_dev_wrapper *wrap; + wrap = container_of(dev, struct __ssb_dev_wrapper, dev); + return wrap->sdev; +} + +/* Device specific user data */ +static inline +void ssb_set_drvdata(struct ssb_device *dev, void *data) +{ + dev->drvdata = data; +} +static inline +void * ssb_get_drvdata(struct ssb_device *dev) +{ + return dev->drvdata; +} + +/* Devicetype specific user data. This is per device-type (not per device) */ +void ssb_set_devtypedata(struct ssb_device *dev, void *data); +static inline +void * ssb_get_devtypedata(struct ssb_device *dev) +{ + return dev->devtypedata; +} + + +struct ssb_driver { + const char *name; + const struct ssb_device_id *id_table; + + int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id); + void (*remove)(struct ssb_device *dev); + int (*suspend)(struct ssb_device *dev, pm_message_t state); + int (*resume)(struct ssb_device *dev); + void (*shutdown)(struct ssb_device *dev); + + struct device_driver drv; +}; +#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) + +extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); +static inline int ssb_driver_register(struct ssb_driver *drv) +{ + return __ssb_driver_register(drv, THIS_MODULE); +} +extern void ssb_driver_unregister(struct ssb_driver *drv); + + + + +enum ssb_bustype { + SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ + SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ + SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */ +}; + +/* board_vendor */ +#define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */ +#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */ +#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */ +/* board_type */ +#define SSB_BOARD_BCM94306MP 0x0418 +#define SSB_BOARD_BCM4309G 0x0421 +#define SSB_BOARD_BCM4306CB 0x0417 +#define SSB_BOARD_BCM4309MP 0x040C +#define SSB_BOARD_MP4318 0x044A +#define SSB_BOARD_BU4306 0x0416 +#define SSB_BOARD_BU4309 0x040A +/* chip_package */ +#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ +#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */ +#define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */ + +#include <linux/ssb/ssb_driver_chipcommon.h> +#include <linux/ssb/ssb_driver_mips.h> +#include <linux/ssb/ssb_driver_extif.h> +#include <linux/ssb/ssb_driver_pci.h> + +struct ssb_bus { + /* The MMIO area. */ + void __iomem *mmio; + + const struct ssb_bus_ops *ops; + + /* The core in the basic address register window. (PCI bus only) */ + struct ssb_device *mapped_device; + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ + u8 mapped_pcmcia_seg; + /* Lock for core and segment switching. */ + spinlock_t bar_lock; + + /* The bus this backplane is running on. */ + enum ssb_bustype bustype; + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ + struct pci_dev *host_pci; + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ + struct pcmcia_device *host_pcmcia; + +#ifdef CONFIG_SSB_PCIHOST + /* Mutex to protect the SPROM writing. */ + struct mutex pci_sprom_mutex; +#endif + + /* ID information about the Chip. */ + u16 chip_id; + u16 chip_rev; + u8 chip_package; + + /* List of devices (cores) on the backplane. */ + struct ssb_device devices[SSB_MAX_NR_CORES]; + u8 nr_devices; + + /* Reference count. Number of suspended devices. */ + u8 suspend_cnt; + + /* Software ID number for this bus. */ + unsigned int busnumber; + + /* The ChipCommon device (if available). */ + struct ssb_chipcommon chipco; + /* The PCI-core device (if available). */ + struct ssb_pcicore pcicore; + /* The MIPS-core device (if available). */ + struct ssb_mipscore mipscore; + /* The EXTif-core device (if available). */ + struct ssb_extif extif; + + /* The following structure elements are not available in early + * SSB initialization. Though, they are available for regular + * registered drivers at any stage. So be careful when + * using them in the ssb core code. */ + + /* ID information about the PCB. */ + struct ssb_boardinfo boardinfo; + /* Contents of the SPROM. */ + struct ssb_sprom sprom; + + /* Internal-only stuff follows. Do not touch. */ + struct list_head list; +#ifdef CONFIG_SSB_DEBUG + /* Is the bus already powered up? */ + bool powered_up; + int power_warn_count; +#endif /* DEBUG */ +}; + +/* The initialization-invariants. */ +struct ssb_init_invariants { + struct ssb_boardinfo boardinfo; + struct ssb_sprom sprom; +}; +/* Type of function to fetch the invariants. */ +typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus, + struct ssb_init_invariants *iv); + +/* Register a SSB system bus. get_invariants() is called after the + * basic system devices are initialized. + * The invariants are usually fetched from some NVRAM. + * Put the invariants into the struct pointed to by iv. */ +extern int ssb_bus_ssbbus_register(struct ssb_bus *bus, + unsigned long baseaddr, + ssb_invariants_func_t get_invariants); +#ifdef CONFIG_SSB_PCIHOST +extern int ssb_bus_pcibus_register(struct ssb_bus *bus, + struct pci_dev *host_pci); +#endif /* CONFIG_SSB_PCIHOST */ +#ifdef CONFIG_SSB_PCMCIAHOST +extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus, + struct pcmcia_device *pcmcia_dev, + unsigned long baseaddr); +#endif /* CONFIG_SSB_PCMCIAHOST */ + +extern void ssb_bus_unregister(struct ssb_bus *bus); + +extern u32 ssb_clockspeed(struct ssb_bus *bus); + +/* Is the device enabled in hardware? */ +int ssb_device_is_enabled(struct ssb_device *dev); +/* Enable a device and pass device-specific SSB_TMSLOW flags. + * If no device-specific flags are available, use 0. */ +void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags); +/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */ +void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags); + + +/* Device MMIO register read/write functions. */ +static inline u16 ssb_read16(struct ssb_device *dev, u16 offset) +{ + return dev->ops->read16(dev, offset); +} +static inline u32 ssb_read32(struct ssb_device *dev, u16 offset) +{ + return dev->ops->read32(dev, offset); +} +static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value) +{ + dev->ops->write16(dev, offset, value); +} +static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value) +{ + dev->ops->write32(dev, offset, value); +} + + +/* Translation (routing) bits that need to be ORed to DMA + * addresses before they are given to a device. */ +extern u32 ssb_dma_translation(struct ssb_device *dev); +#define SSB_DMA_TRANSLATION_MASK 0xC0000000 +#define SSB_DMA_TRANSLATION_SHIFT 30 + +extern int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask); + + +#ifdef CONFIG_SSB_PCIHOST +/* PCI-host wrapper driver */ +extern int ssb_pcihost_register(struct pci_driver *driver); +static inline void ssb_pcihost_unregister(struct pci_driver *driver) +{ + pci_unregister_driver(driver); +} +#endif /* CONFIG_SSB_PCIHOST */ + + +/* If a driver is shutdown or suspended, call this to signal + * that the bus may be completely powered down. SSB will decide, + * if it's really time to power down the bus, based on if there + * are other devices that want to run. */ +extern int ssb_bus_may_powerdown(struct ssb_bus *bus); +/* Before initializing and enabling a device, call this to power-up the bus. + * If you want to allow use of dynamic-power-control, pass the flag. + * Otherwise static always-on powercontrol will be used. */ +extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); + + +/* Various helper functions */ +extern u32 ssb_admatch_base(u32 adm); +extern u32 ssb_admatch_size(u32 adm); + + +#endif /* LINUX_SSB_H_ */ diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h new file mode 100644 index 000000000000..4cb995494662 --- /dev/null +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -0,0 +1,396 @@ +#ifndef LINUX_SSB_CHIPCO_H_ +#define LINUX_SSB_CHIPCO_H_ + +/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions + * + * The chipcommon core provides chip identification, SB control, + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, + * gpio interface, extbus, and support for serial and parallel flashes. + * + * Copyright 2005, Broadcom Corporation + * Copyright 2006, Michael Buesch <mb@bu3sch.de> + * + * Licensed under the GPL version 2. See COPYING for details. + */ + +/** ChipCommon core registers. **/ + +#define SSB_CHIPCO_CHIPID 0x0000 +#define SSB_CHIPCO_IDMASK 0x0000FFFF +#define SSB_CHIPCO_REVMASK 0x000F0000 +#define SSB_CHIPCO_REVSHIFT 16 +#define SSB_CHIPCO_PACKMASK 0x00F00000 +#define SSB_CHIPCO_PACKSHIFT 20 +#define SSB_CHIPCO_NRCORESMASK 0x0F000000 +#define SSB_CHIPCO_NRCORESSHIFT 24 +#define SSB_CHIPCO_CAP 0x0004 /* Capabilities */ +#define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */ +#define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ +#define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */ +#define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ +#define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ +#define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */ +#define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */ +#define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */ +#define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */ +#define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ +#define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */ +#define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */ +#define SSB_PLLTYPE_NONE 0x00000000 +#define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ +#define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ +#define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ +#define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ +#define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ +#define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ +#define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ +#define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */ +#define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */ +#define SSB_CHIPCO_CAP_OTPS_SHIFT 19 +#define SSB_CHIPCO_CAP_OTPS_BASE 5 +#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ +#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ +#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ +#define SSB_CHIPCO_CORECTL 0x0008 +#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ +#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ +#define SSB_CHIPCO_BIST 0x000C +#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ +#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 +#define SSB_CHIPCO_OTPS_PROTECT 0x00000007 +#define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001 +#define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002 +#define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004 +#define SSB_CHIPCO_OTPC 0x0014 /* OTP control */ +#define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000 +#define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00 +#define SSB_CHIPCO_OTPC_PRW_SHIFT 8 +#define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038 +#define SSB_CHIPCO_OTPC_VSEL 0x00000006 +#define SSB_CHIPCO_OTPC_SELVL 0x00000001 +#define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */ +#define SSB_CHIPCO_OTPP_COL 0x000000FF +#define SSB_CHIPCO_OTPP_ROW 0x0000FF00 +#define SSB_CHIPCO_OTPP_ROW_SHIFT 8 +#define SSB_CHIPCO_OTPP_READERR 0x10000000 +#define SSB_CHIPCO_OTPP_VALUE 0x20000000 +#define SSB_CHIPCO_OTPP_READ 0x40000000 +#define SSB_CHIPCO_OTPP_START 0x80000000 +#define SSB_CHIPCO_OTPP_BUSY 0x80000000 +#define SSB_CHIPCO_IRQSTAT 0x0020 +#define SSB_CHIPCO_IRQMASK 0x0024 +#define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */ +#define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ +#define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ +#define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */ +#define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */ +#define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */ +#define SSB_CHIPCO_JCMD_START 0x80000000 +#define SSB_CHIPCO_JCMD_BUSY 0x80000000 +#define SSB_CHIPCO_JCMD_PAUSE 0x40000000 +#define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000 +#define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000 +#define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000 +#define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000 +#define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000 +#define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000 +#define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000 +#define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00 +#define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ +#define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000 +#define SSB_CHIPCO_JCMD_ACC_DR 0x00010000 +#define SSB_CHIPCO_JCMD_ACC_IR 0x00020000 +#define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000 +#define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000 +#define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000 +#define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00 +#define SSB_CHIPCO_JCMD_IRW_SHIFT 8 +#define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F +#define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */ +#define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */ +#define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */ +#define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */ +#define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */ +#define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */ +#define SSB_CHIPCO_FLASHCTL 0x0040 +#define SSB_CHIPCO_FLASHCTL_START 0x80000000 +#define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START +#define SSB_CHIPCO_FLASHADDR 0x0044 +#define SSB_CHIPCO_FLASHDATA 0x0048 +#define SSB_CHIPCO_BCAST_ADDR 0x0050 +#define SSB_CHIPCO_BCAST_DATA 0x0054 +#define SSB_CHIPCO_GPIOIN 0x0060 +#define SSB_CHIPCO_GPIOOUT 0x0064 +#define SSB_CHIPCO_GPIOOUTEN 0x0068 +#define SSB_CHIPCO_GPIOCTL 0x006C +#define SSB_CHIPCO_GPIOPOL 0x0070 +#define SSB_CHIPCO_GPIOIRQ 0x0074 +#define SSB_CHIPCO_WATCHDOG 0x0080 +#define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ +#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 +#define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ +#define SSB_CHIPCO_CLOCK_N 0x0090 +#define SSB_CHIPCO_CLOCK_SB 0x0094 +#define SSB_CHIPCO_CLOCK_PCI 0x0098 +#define SSB_CHIPCO_CLOCK_M2 0x009C +#define SSB_CHIPCO_CLOCK_MIPS 0x00A0 +#define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */ +#define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000 +#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24 +#define SSB_CHIPCO_CLKDIV_OTP 0x000F0000 +#define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16 +#define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00 +#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8 +#define SSB_CHIPCO_CLKDIV_UART 0x000000FF +#define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */ +#define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ +#define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ +#define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ +#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ +#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ +#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ +#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ +#define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ +#define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ +#define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ +#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ +#define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ +#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ +#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16 +#define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ +#define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ +#define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ +#define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ +#define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ +#define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ +#define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ +#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16 +#define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */ +#define SSB_CHIPCO_PCMCIA_CFG 0x0100 +#define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104 +#define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108 +#define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C +#define SSB_CHIPCO_IDE_CFG 0x0110 +#define SSB_CHIPCO_IDE_MEMWAIT 0x0114 +#define SSB_CHIPCO_IDE_ATTRWAIT 0x0118 +#define SSB_CHIPCO_IDE_IOWAIT 0x011C +#define SSB_CHIPCO_PROG_CFG 0x0120 +#define SSB_CHIPCO_PROG_WAITCNT 0x0124 +#define SSB_CHIPCO_FLASH_CFG 0x0128 +#define SSB_CHIPCO_FLASH_WAITCNT 0x012C +#define SSB_CHIPCO_UART0_DATA 0x0300 +#define SSB_CHIPCO_UART0_IMR 0x0304 +#define SSB_CHIPCO_UART0_FCR 0x0308 +#define SSB_CHIPCO_UART0_LCR 0x030C +#define SSB_CHIPCO_UART0_MCR 0x0310 +#define SSB_CHIPCO_UART0_LSR 0x0314 +#define SSB_CHIPCO_UART0_MSR 0x0318 +#define SSB_CHIPCO_UART0_SCRATCH 0x031C +#define SSB_CHIPCO_UART1_DATA 0x0400 +#define SSB_CHIPCO_UART1_IMR 0x0404 +#define SSB_CHIPCO_UART1_FCR 0x0408 +#define SSB_CHIPCO_UART1_LCR 0x040C +#define SSB_CHIPCO_UART1_MCR 0x0410 +#define SSB_CHIPCO_UART1_LSR 0x0414 +#define SSB_CHIPCO_UART1_MSR 0x0418 +#define SSB_CHIPCO_UART1_SCRATCH 0x041C + + + +/** Clockcontrol masks and values **/ + +/* SSB_CHIPCO_CLOCK_N */ +#define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */ +#define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */ +#define SSB_CHIPCO_CLK_N2_SHIFT 8 +#define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */ +#define SSB_CHIPCO_CLK_PLLC_SHIFT 16 + +/* SSB_CHIPCO_CLOCK_SB/PCI/UART */ +#define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */ +#define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */ +#define SSB_CHIPCO_CLK_M2_SHIFT 8 +#define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */ +#define SSB_CHIPCO_CLK_M3_SHIFT 16 +#define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */ +#define SSB_CHIPCO_CLK_MC_SHIFT 24 + +/* N3M Clock control magic field values */ +#define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */ +#define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */ +#define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */ +#define SSB_CHIPCO_CLK_F6_5 0x09 +#define SSB_CHIPCO_CLK_F6_6 0x11 +#define SSB_CHIPCO_CLK_F6_7 0x21 + +#define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */ + +#define SSB_CHIPCO_CLK_MC_BYPASS 0x08 +#define SSB_CHIPCO_CLK_MC_M1 0x04 +#define SSB_CHIPCO_CLK_MC_M1M2 0x02 +#define SSB_CHIPCO_CLK_MC_M1M2M3 0x01 +#define SSB_CHIPCO_CLK_MC_M1M3 0x11 + +/* Type 2 Clock control magic field values */ +#define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ +#define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */ + +#define SSB_CHIPCO_CLK_T2MC_M1BYP 1 +#define SSB_CHIPCO_CLK_T2MC_M2BYP 2 +#define SSB_CHIPCO_CLK_T2MC_M3BYP 4 + +/* Type 6 Clock control magic field values */ +#define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */ +#define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */ +#define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */ +#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb)) + +/* Common clock base */ +#define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */ +#define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */ + +/* Clock control values for 200Mhz in 5350 */ +#define SSB_CHIPCO_CLK_5350_N 0x0311 +#define SSB_CHIPCO_CLK_5350_M 0x04020009 + + +/** Bits in the config registers **/ + +#define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */ +#define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */ +#define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */ +#define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */ +#define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */ +#define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */ +#define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */ +#define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */ +#define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */ +#define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */ + + +/** Flash-specific control/status values */ + +/* flashcontrol opcodes for ST flashes */ +#define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ +#define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ +#define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ +#define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ +#define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ +#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */ +#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ +#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ +#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ +#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */ + +/* Status register bits for ST flashes */ +#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ +#define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */ +#define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */ +#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2 +#define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */ + +/* flashcontrol opcodes for Atmel flashes */ +#define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */ +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */ +#define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */ +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */ +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289 +#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281 +#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */ +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */ +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261 +#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 +#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 + +/* Status register bits for Atmel flashes */ +#define SSB_CHIPCO_FLASHSTA_AT_READY 0x80 +#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40 +#define SSB_CHIPCO_FLASHSTA_AT_ID 0x38 +#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3 + + +/** OTP **/ + +/* OTP regions */ +#define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT +#define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT +#define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT + +/* OTP regions (Byte offsets from otp size) */ +#define SSB_CHIPCO_OTP_SWLIM_OFF (-8) +#define SSB_CHIPCO_OTP_CIDBASE_OFF 0 +#define SSB_CHIPCO_OTP_CIDLIM_OFF 8 + +/* Predefined OTP words (Word offset from otp size) */ +#define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4) +#define SSB_CHIPCO_OTP_HWSIGN_OFF (-3) +#define SSB_CHIPCO_OTP_SWSIGN_OFF (-2) +#define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1) + +#define SSB_CHIPCO_OTP_CID_OFF 0 +#define SSB_CHIPCO_OTP_PKG_OFF 1 +#define SSB_CHIPCO_OTP_FID_OFF 2 +#define SSB_CHIPCO_OTP_RSV_OFF 3 +#define SSB_CHIPCO_OTP_LIM_OFF 4 + +#define SSB_CHIPCO_OTP_SIGNATURE 0x578A +#define SSB_CHIPCO_OTP_MAGIC 0x4E56 + + +struct ssb_device; +struct ssb_serial_port; + +struct ssb_chipcommon { + struct ssb_device *dev; + u32 capabilities; + /* Fast Powerup Delay constant */ + u16 fast_pwrup_delay; +}; + +extern void ssb_chipcommon_init(struct ssb_chipcommon *cc); + +#include <linux/pm.h> +extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state); +extern void ssb_chipco_resume(struct ssb_chipcommon *cc); + +extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m); +extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m); +extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc, + unsigned long ns_per_cycle); + +enum ssb_clkmode { + SSB_CLKMODE_SLOW, + SSB_CLKMODE_FAST, + SSB_CLKMODE_DYNAMIC, +}; + +extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, + enum ssb_clkmode mode); + +extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, + u32 ticks); + +u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask); + +void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value); + +void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value); + +#ifdef CONFIG_SSB_SERIAL +extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, + struct ssb_serial_port *ports); +#endif /* CONFIG_SSB_SERIAL */ + +#endif /* LINUX_SSB_CHIPCO_H_ */ diff --git a/include/linux/ssb/ssb_driver_extif.h b/include/linux/ssb/ssb_driver_extif.h new file mode 100644 index 000000000000..a9164357b5ae --- /dev/null +++ b/include/linux/ssb/ssb_driver_extif.h @@ -0,0 +1,204 @@ +/* + * Hardware-specific External Interface I/O core definitions + * for the BCM47xx family of SiliconBackplane-based chips. + * + * The External Interface core supports a total of three external chip selects + * supporting external interfaces. One of the external chip selects is + * used for Flash, one is used for PCMCIA, and the other may be + * programmed to support either a synchronous interface or an + * asynchronous interface. The asynchronous interface can be used to + * support external devices such as UARTs and the BCM2019 Bluetooth + * baseband processor. + * The external interface core also contains 2 on-chip 16550 UARTs, clock + * frequency control, a watchdog interrupt timer, and a GPIO interface. + * + * Copyright 2005, Broadcom Corporation + * Copyright 2006, Michael Buesch + * + * Licensed under the GPL version 2. See COPYING for details. + */ +#ifndef LINUX_SSB_EXTIFCORE_H_ +#define LINUX_SSB_EXTIFCORE_H_ + +/* external interface address space */ +#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x) +#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) +#define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) +#define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000) +#define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000) + +#define SSB_EXTIF_NR_GPIOOUT 5 +/* GPIO NOTE: + * The multiple instances of output and output enable registers + * are present to allow driver software for multiple cores to control + * gpio outputs without needing to share a single register pair. + * Use the following helper macro to get a register offset value. + */ +#define SSB_EXTIF_GPIO_OUT(index) ({ \ + BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ + SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \ + }) +#define SSB_EXTIF_GPIO_OUTEN(index) ({ \ + BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \ + SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \ + }) + +/** EXTIF core registers **/ + +#define SSB_EXTIF_CTL 0x0000 +#define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */ +#define SSB_EXTIF_EXTSTAT 0x0004 +#define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */ +#define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */ +#define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */ +#define SSB_EXTIF_PCMCIA_CFG 0x0010 +#define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014 +#define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018 +#define SSB_EXTIF_PCMCIA_IOWAIT 0x001C +#define SSB_EXTIF_PROG_CFG 0x0020 +#define SSB_EXTIF_PROG_WAITCNT 0x0024 +#define SSB_EXTIF_FLASH_CFG 0x0028 +#define SSB_EXTIF_FLASH_WAITCNT 0x002C +#define SSB_EXTIF_WATCHDOG 0x0040 +#define SSB_EXTIF_CLOCK_N 0x0044 +#define SSB_EXTIF_CLOCK_SB 0x0048 +#define SSB_EXTIF_CLOCK_PCI 0x004C +#define SSB_EXTIF_CLOCK_MII 0x0050 +#define SSB_EXTIF_GPIO_IN 0x0060 +#define SSB_EXTIF_GPIO_OUT_BASE 0x0064 +#define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068 +#define SSB_EXTIF_EJTAG_OUTEN 0x0090 +#define SSB_EXTIF_GPIO_INTPOL 0x0094 +#define SSB_EXTIF_GPIO_INTMASK 0x0098 +#define SSB_EXTIF_UART_DATA 0x0300 +#define SSB_EXTIF_UART_TIMER 0x0310 +#define SSB_EXTIF_UART_FCR 0x0320 +#define SSB_EXTIF_UART_LCR 0x0330 +#define SSB_EXTIF_UART_MCR 0x0340 +#define SSB_EXTIF_UART_LSR 0x0350 +#define SSB_EXTIF_UART_MSR 0x0360 +#define SSB_EXTIF_UART_SCRATCH 0x0370 + + + + +/* pcmcia/prog/flash_config */ +#define SSB_EXTCFG_EN (1 << 0) /* enable */ +#define SSB_EXTCFG_MODE 0xE /* mode */ +#define SSB_EXTCFG_MODE_SHIFT 1 +#define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */ +#define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */ +#define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */ +#define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */ +#define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */ +#define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */ +#define SSB_EXTCFG_CLKDIV_SHIFT 6 +#define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */ +#define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */ +#define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */ +#define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */ +#define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */ + +/* pcmcia_memwait */ +#define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */ +#define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */ +#define SSB_PCMCIA_MEMW_1_SHIFT 8 +#define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */ +#define SSB_PCMCIA_MEMW_2_SHIFT 16 +#define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */ +#define SSB_PCMCIA_MEMW_3_SHIFT 24 + +/* pcmcia_attrwait */ +#define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */ +#define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */ +#define SSB_PCMCIA_ATTW_1_SHIFT 8 +#define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */ +#define SSB_PCMCIA_ATTW_2_SHIFT 16 +#define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */ +#define SSB_PCMCIA_ATTW_3_SHIFT 24 + +/* pcmcia_iowait */ +#define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */ +#define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */ +#define SSB_PCMCIA_IOW_1_SHIFT 8 +#define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */ +#define SSB_PCMCIA_IOW_2_SHIFT 16 +#define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */ +#define SSB_PCMCIA_IOW_3_SHIFT 24 + +/* prog_waitcount */ +#define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */ +#define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */ +#define SSB_PROG_WCNT_1_SHIFT 8 +#define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */ +#define SSB_PROG_WCNT_2_SHIFT 16 +#define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */ +#define SSB_PROG_WCNT_3_SHIFT 24 + +#define SSB_PROG_W0 0x0000000C +#define SSB_PROG_W1 0x00000A00 +#define SSB_PROG_W2 0x00020000 +#define SSB_PROG_W3 0x01000000 + +/* flash_waitcount */ +#define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */ +#define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */ +#define SSB_FLASH_WCNT_1_SHIFT 8 +#define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */ +#define SSB_FLASH_WCNT_2_SHIFT 16 +#define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */ +#define SSB_FLASH_WCNT_3_SHIFT 24 + +/* watchdog */ +#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ + + + +#ifdef CONFIG_SSB_DRIVER_EXTIF + +struct ssb_extif { + struct ssb_device *dev; +}; + +static inline bool ssb_extif_available(struct ssb_extif *extif) +{ + return (extif->dev != NULL); +} + +extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif, + u32 *plltype, u32 *n, u32 *m); + +extern void ssb_extif_timing_init(struct ssb_extif *extif, + unsigned long ns); + +u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); + +void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value); + +void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value); + +#ifdef CONFIG_SSB_SERIAL +extern int ssb_extif_serial_init(struct ssb_extif *extif, + struct ssb_serial_port *ports); +#endif /* CONFIG_SSB_SERIAL */ + + +#else /* CONFIG_SSB_DRIVER_EXTIF */ +/* extif disabled */ + +struct ssb_extif { +}; + +static inline bool ssb_extif_available(struct ssb_extif *extif) +{ + return 0; +} + +static inline +void ssb_extif_get_clockcontrol(struct ssb_extif *extif, + u32 *plltype, u32 *n, u32 *m) +{ +} + +#endif /* CONFIG_SSB_DRIVER_EXTIF */ +#endif /* LINUX_SSB_EXTIFCORE_H_ */ diff --git a/include/linux/ssb/ssb_driver_mips.h b/include/linux/ssb/ssb_driver_mips.h new file mode 100644 index 000000000000..5f44e9740cd2 --- /dev/null +++ b/include/linux/ssb/ssb_driver_mips.h @@ -0,0 +1,46 @@ +#ifndef LINUX_SSB_MIPSCORE_H_ +#define LINUX_SSB_MIPSCORE_H_ + +#ifdef CONFIG_SSB_DRIVER_MIPS + +struct ssb_device; + +struct ssb_serial_port { + void *regs; + unsigned long clockspeed; + unsigned int irq; + unsigned int baud_base; + unsigned int reg_shift; +}; + + +struct ssb_mipscore { + struct ssb_device *dev; + + int nr_serial_ports; + struct ssb_serial_port serial_ports[4]; + + u8 flash_buswidth; + u32 flash_window; + u32 flash_window_size; +}; + +extern void ssb_mipscore_init(struct ssb_mipscore *mcore); +extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore); + +extern unsigned int ssb_mips_irq(struct ssb_device *dev); + + +#else /* CONFIG_SSB_DRIVER_MIPS */ + +struct ssb_mipscore { +}; + +static inline +void ssb_mipscore_init(struct ssb_mipscore *mcore) +{ +} + +#endif /* CONFIG_SSB_DRIVER_MIPS */ + +#endif /* LINUX_SSB_MIPSCORE_H_ */ diff --git a/include/linux/ssb/ssb_driver_pci.h b/include/linux/ssb/ssb_driver_pci.h new file mode 100644 index 000000000000..9cfffb7b1a27 --- /dev/null +++ b/include/linux/ssb/ssb_driver_pci.h @@ -0,0 +1,106 @@ +#ifndef LINUX_SSB_PCICORE_H_ +#define LINUX_SSB_PCICORE_H_ + +#ifdef CONFIG_SSB_DRIVER_PCICORE + +/* PCI core registers. */ +#define SSB_PCICORE_CTL 0x0000 /* PCI Control */ +#define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */ +#define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */ +#define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */ +#define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */ +#define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */ +#define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */ +#define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */ +#define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */ +#define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */ +#define SSB_PCICORE_ARBCTL_PARKID_4710 0x00000002 /* 4710 */ +#define SSB_PCICORE_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */ +#define SSB_PCICORE_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */ +#define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */ +#define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */ +#define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */ +#define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */ +#define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */ +#define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */ +#define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */ +#define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */ +#define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */ +#define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */ +#define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */ +#define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */ +#define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */ +#define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */ +#define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */ +#define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */ +#define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */ +#define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */ +#define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */ +#define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */ +#define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */ +#define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */ +#define SSB_PCICORE_BCAST_ADDR_MASK 0x000000FF +#define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */ +#define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */ +#define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */ +#define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */ +#define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */ +#define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */ +#define SSB_PCICORE_SBTOPCI0_MASK 0xFC000000 +#define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */ +#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000 +#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */ +#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000 + +/* SBtoPCIx */ +#define SSB_PCICORE_SBTOPCI_MEM 0x00000000 +#define SSB_PCICORE_SBTOPCI_IO 0x00000001 +#define SSB_PCICORE_SBTOPCI_CFG0 0x00000002 +#define SSB_PCICORE_SBTOPCI_CFG1 0x00000003 +#define SSB_PCICORE_SBTOPCI_PREF 0x00000004 /* Prefetch enable */ +#define SSB_PCICORE_SBTOPCI_BURST 0x00000008 /* Burst enable */ +#define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */ +#define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */ +#define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */ +#define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */ +#define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */ + + +/* PCIcore specific boardflags */ +#define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ + + +struct ssb_pcicore { + struct ssb_device *dev; + u8 setup_done:1; + u8 hostmode:1; + u8 cardbusmode:1; +}; + +extern void ssb_pcicore_init(struct ssb_pcicore *pc); + +/* Enable IRQ routing for a specific device */ +extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, + struct ssb_device *dev); + + +#else /* CONFIG_SSB_DRIVER_PCICORE */ + + +struct ssb_pcicore { +}; + +static inline +void ssb_pcicore_init(struct ssb_pcicore *pc) +{ +} + +static inline +int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, + struct ssb_device *dev) +{ + return 0; +} + +#endif /* CONFIG_SSB_DRIVER_PCICORE */ +#endif /* LINUX_SSB_PCICORE_H_ */ diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h new file mode 100644 index 000000000000..47c7c71a5acf --- /dev/null +++ b/include/linux/ssb/ssb_regs.h @@ -0,0 +1,292 @@ +#ifndef LINUX_SSB_REGS_H_ +#define LINUX_SSB_REGS_H_ + + +/* SiliconBackplane Address Map. + * All regions may not exist on all chips. + */ +#define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */ +#define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ +#define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ +#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ +#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */ +#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */ + +#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */ +#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */ + +#define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */ +#define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */ +#define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */ + +#define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ +#define SSB_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ +#define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */ +#define SSB_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ +#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000) +#define SSB_LED (SSB_EXTIF_BASE + 0x00900000) + + +/* Enumeration space constants */ +#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */ +#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE) + + +/* mips address */ +#define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ + + +/* SSB PCI config space registers. */ +#define SSB_PMCSR 0x44 +#define SSB_PE 0x100 +#define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */ +#define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */ +#define SSB_SPROMCTL 0x88 /* SPROM control */ +#define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */ +#define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */ +#define SSB_PCI_IRQS 0x90 /* PCI interrupts */ +#define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */ +#define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */ +#define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */ +#define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */ +#define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */ +#define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ +#define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ +#define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ +#define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ + + +#define SSB_BAR0_MAX_RETRIES 50 + +/* Silicon backplane configuration register definitions */ +#define SSB_IPSFLAG 0x0F08 +#define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */ +#define SSB_IPSFLAG_IRQ1_SHIFT 0 +#define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */ +#define SSB_IPSFLAG_IRQ2_SHIFT 8 +#define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */ +#define SSB_IPSFLAG_IRQ3_SHIFT 16 +#define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */ +#define SSB_IPSFLAG_IRQ4_SHIFT 24 +#define SSB_TPSFLAG 0x0F18 +#define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */ +#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */ +#define SSB_TMERRLOGA 0x0F48 +#define SSB_TMERRLOG 0x0F50 +#define SSB_ADMATCH3 0x0F60 +#define SSB_ADMATCH2 0x0F68 +#define SSB_ADMATCH1 0x0F70 +#define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */ +#define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */ +#define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ +#define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ +#define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */ +#define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */ +#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ +#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ +#define SSB_IMSTATE_TO 0x00040000 /* Timeout */ +#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ +#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ +#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ +#define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ +#define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ +#define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ +#define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ +#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ +#define SSB_TMSLOW 0x0F98 /* SB Target State Low */ +#define SSB_TMSLOW_RESET 0x00000001 /* Reset */ +#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */ +#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */ +#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ +#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ +#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */ +#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */ +#define SSB_TMSHIGH 0x0F9C /* SB Target State High */ +#define SSB_TMSHIGH_SERR 0x00000001 /* S-error */ +#define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */ +#define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */ +#define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */ +#define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */ +#define SSB_TMSHIGH_COREFL_SHIFT 16 +#define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */ +#define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */ +#define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */ +#define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */ +#define SSB_BWA0 0x0FA0 +#define SSB_IMCFGLO 0x0FA8 +#define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */ +#define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */ +#define SSB_IMCFGLO_REQTO_SHIFT 4 +#define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */ +#define SSB_IMCFGLO_CONNID_SHIFT 16 +#define SSB_IMCFGHI 0x0FAC +#define SSB_ADMATCH0 0x0FB0 +#define SSB_TMCFGLO 0x0FB8 +#define SSB_TMCFGHI 0x0FBC +#define SSB_BCONFIG 0x0FC0 +#define SSB_BSTATE 0x0FC8 +#define SSB_ACTCFG 0x0FD8 +#define SSB_FLAGST 0x0FE8 +#define SSB_IDLOW 0x0FF8 +#define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */ +#define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */ +#define SSB_IDLOW_ADDRNGE_SHIFT 3 +#define SSB_IDLOW_SYNC 0x00000040 +#define SSB_IDLOW_INITIATOR 0x00000080 +#define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */ +#define SSB_IDLOW_MIBL_SHIFT 8 +#define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */ +#define SSB_IDLOW_MABL_SHIFT 12 +#define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */ +#define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */ +#define SSB_IDLOW_CCW_SHIFT 18 +#define SSB_IDLOW_TPT 0x00F00000 /* Target ports */ +#define SSB_IDLOW_TPT_SHIFT 20 +#define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */ +#define SSB_IDLOW_INITP_SHIFT 24 +#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */ +#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */ +#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */ +#define SSB_IDHIGH 0x0FFC /* SB Identification High */ +#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ +#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */ +#define SSB_IDHIGH_CC_SHIFT 4 +#define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ +#define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */ +#define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ +#define SSB_IDHIGH_VC_SHIFT 16 + +/* SPROM shadow area. If not otherwise noted, fields are + * two bytes wide. Note that the SPROM can _only_ be read + * in two-byte quantinies. + */ +#define SSB_SPROMSIZE_WORDS 64 +#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16)) +#define SSB_SPROM_BASE 0x1000 +#define SSB_SPROM_REVISION 0x107E +#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ +#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ +#define SSB_SPROM_REVISION_CRC_SHIFT 8 +/* SPROM Revision 1 */ +#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ +#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ +#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ +#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ +#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ +#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ +#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ +#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ +#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ +#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 +#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ +#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +#define SSB_SPROM1_BINF 0x105C /* Board info */ +#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ +#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ +#define SSB_SPROM1_BINF_CCODE_SHIFT 8 +#define SSB_SPROM1_BINF_ANTA 0x3000 /* Available A-PHY antennas */ +#define SSB_SPROM1_BINF_ANTA_SHIFT 12 +#define SSB_SPROM1_BINF_ANTBG 0xC000 /* Available B-PHY antennas */ +#define SSB_SPROM1_BINF_ANTBG_SHIFT 14 +#define SSB_SPROM1_PA0B0 0x105E +#define SSB_SPROM1_PA0B1 0x1060 +#define SSB_SPROM1_PA0B2 0x1062 +#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ +#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ +#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ +#define SSB_SPROM1_GPIOA_P1_SHIFT 8 +#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ +#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ +#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ +#define SSB_SPROM1_GPIOB_P3_SHIFT 8 +#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ +#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ +#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ +#define SSB_SPROM1_MAXPWR_A_SHIFT 8 +#define SSB_SPROM1_PA1B0 0x106A +#define SSB_SPROM1_PA1B1 0x106C +#define SSB_SPROM1_PA1B2 0x106E +#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ +#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ +#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ +#define SSB_SPROM1_ITSSI_A_SHIFT 8 +#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ +#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ +#define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */ +#define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */ +#define SSB_SPROM1_AGAIN_BG_SHIFT 8 +#define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */ +/* SPROM Revision 2 (inherits from rev 1) */ +#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ +#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ +#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ +#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ +#define SSB_SPROM2_MAXP_A_LO_SHIFT 8 +#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ +#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ +#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ +#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ +#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ +#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ +#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ +#define SSB_SPROM2_OPO_VALUE 0x00FF +#define SSB_SPROM2_OPO_UNUSED 0xFF00 +#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ +/* SPROM Revision 3 (inherits from rev 2) */ +#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ +#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ +#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ +#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ +#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ +#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 +#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ +#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 +#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ +#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ +#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ +#define SSB_SPROM3_CCKPO_2M_SHIFT 4 +#define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */ +#define SSB_SPROM3_CCKPO_55M_SHIFT 8 +#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ +#define SSB_SPROM3_CCKPO_11M_SHIFT 12 +#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ + +/* Values for SSB_SPROM1_BINF_CCODE */ +enum { + SSB_SPROM1CCODE_WORLD = 0, + SSB_SPROM1CCODE_THAILAND, + SSB_SPROM1CCODE_ISRAEL, + SSB_SPROM1CCODE_JORDAN, + SSB_SPROM1CCODE_CHINA, + SSB_SPROM1CCODE_JAPAN, + SSB_SPROM1CCODE_USA_CANADA_ANZ, + SSB_SPROM1CCODE_EUROPE, + SSB_SPROM1CCODE_USA_LOW, + SSB_SPROM1CCODE_JAPAN_HIGH, + SSB_SPROM1CCODE_ALL, + SSB_SPROM1CCODE_NONE, +}; + +/* Address-Match values and masks (SSB_ADMATCHxxx) */ +#define SSB_ADM_TYPE 0x00000003 /* Address type */ +#define SSB_ADM_TYPE0 0 +#define SSB_ADM_TYPE1 1 +#define SSB_ADM_TYPE2 2 +#define SSB_ADM_AD64 0x00000004 +#define SSB_ADM_SZ0 0x000000F8 /* Type0 size */ +#define SSB_ADM_SZ0_SHIFT 3 +#define SSB_ADM_SZ1 0x000001F8 /* Type1 size */ +#define SSB_ADM_SZ1_SHIFT 3 +#define SSB_ADM_SZ2 0x000001F8 /* Type2 size */ +#define SSB_ADM_SZ2_SHIFT 3 +#define SSB_ADM_EN 0x00000400 /* Enable */ +#define SSB_ADM_NEG 0x00000800 /* Negative decode */ +#define SSB_ADM_BASE0 0xFFFFFF00 /* Type0 base address */ +#define SSB_ADM_BASE0_SHIFT 8 +#define SSB_ADM_BASE1 0xFFFFF000 /* Type1 base address for the core */ +#define SSB_ADM_BASE1_SHIFT 12 +#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */ +#define SSB_ADM_BASE2_SHIFT 16 + + +#endif /* LINUX_SSB_REGS_H_ */ diff --git a/include/linux/stacktrace.h b/include/linux/stacktrace.h index 1d2b084c0185..e7fa657d0c49 100644 --- a/include/linux/stacktrace.h +++ b/include/linux/stacktrace.h @@ -13,7 +13,7 @@ extern void save_stack_trace(struct stack_trace *trace); extern void print_stack_trace(struct stack_trace *trace, int spaces); #else # define save_stack_trace(trace) do { } while (0) -# define print_stack_trace(trace) do { } while (0) +# define print_stack_trace(trace, spaces) do { } while (0) #endif #endif diff --git a/include/linux/string.h b/include/linux/string.h index 7f2eb6a477f9..836062b7582a 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -105,8 +105,12 @@ extern void * memchr(const void *,int,__kernel_size_t); #endif extern char *kstrdup(const char *s, gfp_t gfp); +extern char *kstrndup(const char *s, size_t len, gfp_t gfp); extern void *kmemdup(const void *src, size_t len, gfp_t gfp); +extern char **argv_split(gfp_t gfp, const char *str, int *argcp); +extern void argv_free(char **argv); + #ifdef __cplusplus } #endif diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h index 9e340fa23c06..c6b53d181bfa 100644 --- a/include/linux/sunrpc/xdr.h +++ b/include/linux/sunrpc/xdr.h @@ -12,6 +12,7 @@ #include <linux/uio.h> #include <asm/byteorder.h> #include <linux/scatterlist.h> +#include <linux/smp_lock.h> /* * Buffer adjustment @@ -36,6 +37,21 @@ struct xdr_netobj { typedef int (*kxdrproc_t)(void *rqstp, __be32 *data, void *obj); /* + * We're still requiring the BKL in the xdr code until it's been + * more carefully audited, at which point this wrapper will become + * unnecessary. + */ +static inline int rpc_call_xdrproc(kxdrproc_t xdrproc, void *rqstp, __be32 *data, void *obj) +{ + int ret; + + lock_kernel(); + ret = xdrproc(rqstp, data, obj); + unlock_kernel(); + return ret; +} + +/* * Basic structure for transmission/reception of a client XDR message. * Features a header (for a linear buffer containing RPC headers * and the data payload for short messages), and then an array of diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 9c7cb6430666..388cace9751f 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -24,7 +24,7 @@ struct pbe { extern void drain_local_pages(void); extern void mark_free_pages(struct zone *zone); -#if defined(CONFIG_PM) && defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) extern int pm_prepare_console(void); extern void pm_restore_console(void); #else @@ -43,14 +43,18 @@ static inline void pm_restore_console(void) {} * @prepare: prepare system for hibernation * @enter: shut down system after state has been saved to disk * @finish: finish/clean up after state has been reloaded + * @pre_restore: prepare system for the restoration from a hibernation image + * @restore_cleanup: clean up after a failing image restoration */ struct hibernation_ops { int (*prepare)(void); int (*enter)(void); void (*finish)(void); + int (*pre_restore)(void); + void (*restore_cleanup)(void); }; -#if defined(CONFIG_PM) && defined(CONFIG_SOFTWARE_SUSPEND) +#ifdef CONFIG_HIBERNATION /* kernel/power/snapshot.c */ extern void __register_nosave_region(unsigned long b, unsigned long e, int km); static inline void register_nosave_region(unsigned long b, unsigned long e) @@ -68,21 +72,62 @@ extern unsigned long get_safe_page(gfp_t gfp_mask); extern void hibernation_set_ops(struct hibernation_ops *ops); extern int hibernate(void); -#else -static inline void register_nosave_region(unsigned long b, unsigned long e) {} -static inline void register_nosave_region_late(unsigned long b, unsigned long e) {} +#else /* CONFIG_HIBERNATION */ static inline int swsusp_page_is_forbidden(struct page *p) { return 0; } static inline void swsusp_set_page_free(struct page *p) {} static inline void swsusp_unset_page_free(struct page *p) {} static inline void hibernation_set_ops(struct hibernation_ops *ops) {} static inline int hibernate(void) { return -ENOSYS; } -#endif /* defined(CONFIG_PM) && defined(CONFIG_SOFTWARE_SUSPEND) */ +#endif /* CONFIG_HIBERNATION */ +#ifdef CONFIG_PM_SLEEP void save_processor_state(void); void restore_processor_state(void); struct saved_context; void __save_processor_state(struct saved_context *ctxt); void __restore_processor_state(struct saved_context *ctxt); +/* kernel/power/main.c */ +extern struct blocking_notifier_head pm_chain_head; + +static inline int register_pm_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&pm_chain_head, nb); +} + +static inline int unregister_pm_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&pm_chain_head, nb); +} + +#define pm_notifier(fn, pri) { \ + static struct notifier_block fn##_nb = \ + { .notifier_call = fn, .priority = pri }; \ + register_pm_notifier(&fn##_nb); \ +} +#else /* !CONFIG_PM_SLEEP */ + +static inline int register_pm_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline int unregister_pm_notifier(struct notifier_block *nb) +{ + return 0; +} + +#define pm_notifier(fn, pri) do { (void)(fn); } while (0) +#endif /* !CONFIG_PM_SLEEP */ + +#ifndef CONFIG_HIBERNATION +static inline void register_nosave_region(unsigned long b, unsigned long e) +{ +} +static inline void register_nosave_region_late(unsigned long b, unsigned long e) +{ +} +#endif + #endif /* _LINUX_SWSUSP_H */ diff --git a/include/linux/swap.h b/include/linux/swap.h index 665f85f2a3af..edf681a7fd8f 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -221,7 +221,7 @@ extern void swap_unplug_io_fn(struct backing_dev_info *, struct page *); /* linux/mm/page_io.c */ extern int swap_readpage(struct file *, struct page *); extern int swap_writepage(struct page *page, struct writeback_control *wbc); -extern int end_swap_bio_read(struct bio *bio, unsigned int bytes_done, int err); +extern void end_swap_bio_read(struct bio *bio, int err); /* linux/mm/swap_state.c */ extern struct address_space swapper_space; diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 83d0ec11235e..61def7c8fbb3 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -549,7 +549,7 @@ asmlinkage long sys_inotify_rm_watch(int fd, u32 wd); asmlinkage long sys_spu_run(int fd, __u32 __user *unpc, __u32 __user *ustatus); asmlinkage long sys_spu_create(const char __user *name, - unsigned int flags, mode_t mode); + unsigned int flags, mode_t mode, int fd); asmlinkage long sys_mknodat(int dfd, const char __user * filename, int mode, unsigned dev); @@ -610,6 +610,7 @@ asmlinkage long sys_signalfd(int ufd, sigset_t __user *user_mask, size_t sizemas asmlinkage long sys_timerfd(int ufd, int clockid, int flags, const struct itimerspec __user *utmr); asmlinkage long sys_eventfd(unsigned int count); +asmlinkage long sys_fallocate(int fd, int mode, loff_t offset, loff_t len); int kernel_execve(const char *filename, char *const argv[], char *const envp[]); diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 47f1c53332ce..483050c924c3 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -62,7 +62,7 @@ enum CTL_KERN=1, /* General kernel info and control */ CTL_VM=2, /* VM management */ CTL_NET=3, /* Networking */ - /* was CTL_PROC */ + CTL_PROC=4, /* removal breaks strace(1) compilation */ CTL_FS=5, /* Filesystems */ CTL_DEBUG=6, /* Debugging */ CTL_DEV=7, /* Devices */ diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index be8228e50a27..149ab62329e2 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -3,6 +3,8 @@ * * Copyright (c) 2001,2002 Patrick Mochel * Copyright (c) 2004 Silicon Graphics, Inc. + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo <teheo@suse.de> * * Please see Documentation/filesystems/sysfs.txt for more information. */ @@ -17,23 +19,20 @@ struct kobject; struct module; -struct nameidata; -struct dentry; -struct sysfs_dirent; /* FIXME * The *owner field is no longer used, but leave around * until the tree gets cleaned up fully. */ struct attribute { - const char * name; - struct module * owner; + const char *name; + struct module *owner; mode_t mode; }; struct attribute_group { - const char * name; - struct attribute ** attrs; + const char *name; + struct attribute **attrs; }; @@ -77,72 +76,41 @@ struct sysfs_ops { ssize_t (*store)(struct kobject *,struct attribute *,const char *, size_t); }; -#define SYSFS_TYPE_MASK 0x00ff -#define SYSFS_ROOT 0x0001 -#define SYSFS_DIR 0x0002 -#define SYSFS_KOBJ_ATTR 0x0004 -#define SYSFS_KOBJ_BIN_ATTR 0x0008 -#define SYSFS_KOBJ_LINK 0x0020 -#define SYSFS_COPY_NAME (SYSFS_DIR | SYSFS_KOBJ_LINK) - -#define SYSFS_FLAG_MASK ~SYSFS_TYPE_MASK -#define SYSFS_FLAG_REMOVED 0x0100 - #ifdef CONFIG_SYSFS -extern int sysfs_schedule_callback(struct kobject *kobj, - void (*func)(void *), void *data, struct module *owner); - -extern int __must_check -sysfs_create_dir(struct kobject *kobj, struct sysfs_dirent *shadow_parent_sd); - -extern void -sysfs_remove_dir(struct kobject *); - -extern int __must_check -sysfs_rename_dir(struct kobject *kobj, struct sysfs_dirent *new_parent_sd, - const char *new_name); - -extern int __must_check -sysfs_move_dir(struct kobject *, struct kobject *); - -extern int __must_check -sysfs_create_file(struct kobject *, const struct attribute *); +int sysfs_schedule_callback(struct kobject *kobj, void (*func)(void *), + void *data, struct module *owner); -extern int __must_check -sysfs_update_file(struct kobject *, const struct attribute *); +int __must_check sysfs_create_dir(struct kobject *kobj); +void sysfs_remove_dir(struct kobject *kobj); +int __must_check sysfs_rename_dir(struct kobject *kobj, const char *new_name); +int __must_check sysfs_move_dir(struct kobject *kobj, + struct kobject *new_parent_kobj); -extern int __must_check -sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, mode_t mode); - -extern void -sysfs_remove_file(struct kobject *, const struct attribute *); - -extern int __must_check -sysfs_create_link(struct kobject * kobj, struct kobject * target, const char * name); - -extern void -sysfs_remove_link(struct kobject *, const char * name); +int __must_check sysfs_create_file(struct kobject *kobj, + const struct attribute *attr); +int __must_check sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, + mode_t mode); +void sysfs_remove_file(struct kobject *kobj, const struct attribute *attr); int __must_check sysfs_create_bin_file(struct kobject *kobj, - struct bin_attribute *attr); + struct bin_attribute *attr); void sysfs_remove_bin_file(struct kobject *kobj, struct bin_attribute *attr); -int __must_check sysfs_create_group(struct kobject *, - const struct attribute_group *); -void sysfs_remove_group(struct kobject *, const struct attribute_group *); +int __must_check sysfs_create_link(struct kobject *kobj, struct kobject *target, + const char *name); +void sysfs_remove_link(struct kobject *kobj, const char *name); + +int __must_check sysfs_create_group(struct kobject *kobj, + const struct attribute_group *grp); +void sysfs_remove_group(struct kobject *kobj, + const struct attribute_group *grp); int sysfs_add_file_to_group(struct kobject *kobj, - const struct attribute *attr, const char *group); + const struct attribute *attr, const char *group); void sysfs_remove_file_from_group(struct kobject *kobj, - const struct attribute *attr, const char *group); - -void sysfs_notify(struct kobject * k, char *dir, char *attr); - + const struct attribute *attr, const char *group); -extern int sysfs_make_shadowed_dir(struct kobject *kobj, - void * (*follow_link)(struct dentry *, struct nameidata *)); -extern struct sysfs_dirent *sysfs_create_shadow_dir(struct kobject *kobj); -extern void sysfs_remove_shadow_dir(struct sysfs_dirent *shadow_sd); +void sysfs_notify(struct kobject *kobj, char *dir, char *attr); extern int __must_check sysfs_init(void); @@ -154,75 +122,76 @@ static inline int sysfs_schedule_callback(struct kobject *kobj, return -ENOSYS; } -static inline int sysfs_create_dir(struct kobject *kobj, - struct sysfs_dirent *shadow_parent_sd) +static inline int sysfs_create_dir(struct kobject *kobj) { return 0; } -static inline void sysfs_remove_dir(struct kobject * k) +static inline void sysfs_remove_dir(struct kobject *kobj) { ; } -static inline int sysfs_rename_dir(struct kobject *kobj, - struct sysfs_dirent *new_parent_sd, - const char *new_name) +static inline int sysfs_rename_dir(struct kobject *kobj, const char *new_name) { return 0; } -static inline int sysfs_move_dir(struct kobject * k, struct kobject * new_parent) +static inline int sysfs_move_dir(struct kobject *kobj, + struct kobject *new_parent_kobj) { return 0; } -static inline int sysfs_create_file(struct kobject * k, const struct attribute * a) +static inline int sysfs_create_file(struct kobject *kobj, + const struct attribute *attr) { return 0; } -static inline int sysfs_update_file(struct kobject * k, const struct attribute * a) -{ - return 0; -} -static inline int sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, mode_t mode) +static inline int sysfs_chmod_file(struct kobject *kobj, + struct attribute *attr, mode_t mode) { return 0; } -static inline void sysfs_remove_file(struct kobject * k, const struct attribute * a) +static inline void sysfs_remove_file(struct kobject *kobj, + const struct attribute *attr) { ; } -static inline int sysfs_create_link(struct kobject * k, struct kobject * t, const char * n) +static inline int sysfs_create_bin_file(struct kobject *kobj, + struct bin_attribute *attr) { return 0; } -static inline void sysfs_remove_link(struct kobject * k, const char * name) +static inline int sysfs_remove_bin_file(struct kobject *kobj, + struct bin_attribute *attr) { - ; + return 0; } - -static inline int sysfs_create_bin_file(struct kobject * k, struct bin_attribute * a) +static inline int sysfs_create_link(struct kobject *kobj, + struct kobject *target, const char *name) { return 0; } -static inline int sysfs_remove_bin_file(struct kobject * k, struct bin_attribute * a) +static inline void sysfs_remove_link(struct kobject *kobj, const char *name) { - return 0; + ; } -static inline int sysfs_create_group(struct kobject * k, const struct attribute_group *g) +static inline int sysfs_create_group(struct kobject *kobj, + const struct attribute_group *grp) { return 0; } -static inline void sysfs_remove_group(struct kobject * k, const struct attribute_group * g) +static inline void sysfs_remove_group(struct kobject *kobj, + const struct attribute_group *grp) { ; } @@ -238,14 +207,8 @@ static inline void sysfs_remove_file_from_group(struct kobject *kobj, { } -static inline void sysfs_notify(struct kobject * k, char *dir, char *attr) -{ -} - -static inline int sysfs_make_shadowed_dir(struct kobject *kobj, - void * (*follow_link)(struct dentry *, struct nameidata *)) +static inline void sysfs_notify(struct kobject *kobj, char *dir, char *attr) { - return 0; } static inline int __must_check sysfs_init(void) diff --git a/include/linux/tc_act/tc_nat.h b/include/linux/tc_act/tc_nat.h new file mode 100644 index 000000000000..e7cf31e8ba79 --- /dev/null +++ b/include/linux/tc_act/tc_nat.h @@ -0,0 +1,29 @@ +#ifndef __LINUX_TC_NAT_H +#define __LINUX_TC_NAT_H + +#include <linux/pkt_cls.h> +#include <linux/types.h> + +#define TCA_ACT_NAT 9 + +enum +{ + TCA_NAT_UNSPEC, + TCA_NAT_PARMS, + TCA_NAT_TM, + __TCA_NAT_MAX +}; +#define TCA_NAT_MAX (__TCA_NAT_MAX - 1) + +#define TCA_NAT_FLAG_EGRESS 1 + +struct tc_nat +{ + tc_gen; + __be32 old_addr; + __be32 new_addr; + __be32 mask; + __u32 flags; +}; + +#endif diff --git a/include/linux/tcp.h b/include/linux/tcp.h index c6b9f92e8289..c5b94c1a5ee2 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -304,7 +304,6 @@ struct tcp_sock { u32 rtt_seq; /* sequence number to update rttvar */ u32 packets_out; /* Packets which are "in flight" */ - u32 left_out; /* Packets which leaved network */ u32 retrans_out; /* Retransmitted packets out */ /* * Options received (usually on last packet, some only on SYN packets). @@ -333,6 +332,9 @@ struct tcp_sock { struct tcp_sack_block_wire recv_sack_cache[4]; + u32 highest_sack; /* Start seq of globally highest revd SACK + * (validity guaranteed only if sacked_out > 0) */ + /* from STCP, retrans queue hinting */ struct sk_buff* lost_skb_hint; @@ -341,10 +343,12 @@ struct tcp_sock { struct sk_buff *forward_skb_hint; struct sk_buff *fastpath_skb_hint; - int fastpath_cnt_hint; + int fastpath_cnt_hint; /* Lags behind by current skb's pcount + * compared to respective fackets_out */ int lost_cnt_hint; int retransmit_cnt_hint; - int forward_cnt_hint; + + u32 lost_retrans_low; /* Sent seq after any rxmit (lowest) */ u16 advmss; /* Advertised MSS */ u16 prior_ssthresh; /* ssthresh saved at recovery start */ diff --git a/include/linux/time.h b/include/linux/time.h index ec3b0ced0afe..6a5f503b4f1d 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -4,6 +4,7 @@ #include <linux/types.h> #ifdef __KERNEL__ +# include <linux/cache.h> # include <linux/seqlock.h> #endif @@ -94,17 +95,15 @@ extern struct timespec wall_to_monotonic; extern seqlock_t xtime_lock __attribute__((weak)); extern unsigned long read_persistent_clock(void); +extern int update_persistent_clock(struct timespec now); +extern int no_sync_cmos_clock __read_mostly; void timekeeping_init(void); -static inline unsigned long get_seconds(void) -{ - return xtime.tv_sec; -} - +unsigned long get_seconds(void); struct timespec current_kernel_time(void); #define CURRENT_TIME (current_kernel_time()) -#define CURRENT_TIME_SEC ((struct timespec) { xtime.tv_sec, 0 }) +#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 }) extern void do_gettimeofday(struct timeval *tv); extern int do_settimeofday(struct timespec *tv); diff --git a/include/linux/timex.h b/include/linux/timex.h index da929dbbea2a..37ac3ff90faf 100644 --- a/include/linux/timex.h +++ b/include/linux/timex.h @@ -224,66 +224,6 @@ static inline int ntp_synced(void) __x < 0 ? -(-__x >> __s) : __x >> __s; \ }) - -#ifdef CONFIG_TIME_INTERPOLATION - -#define TIME_SOURCE_CPU 0 -#define TIME_SOURCE_MMIO64 1 -#define TIME_SOURCE_MMIO32 2 -#define TIME_SOURCE_FUNCTION 3 - -/* For proper operations time_interpolator clocks must run slightly slower - * than the standard clock since the interpolator may only correct by having - * time jump forward during a tick. A slower clock is usually a side effect - * of the integer divide of the nanoseconds in a second by the frequency. - * The accuracy of the division can be increased by specifying a shift. - * However, this may cause the clock not to be slow enough. - * The interpolator will self-tune the clock by slowing down if no - * resets occur or speeding up if the time jumps per analysis cycle - * become too high. - * - * Setting jitter compensates for a fluctuating timesource by comparing - * to the last value read from the timesource to insure that an earlier value - * is not returned by a later call. The price to pay - * for the compensation is that the timer routines are not as scalable anymore. - */ - -struct time_interpolator { - u16 source; /* time source flags */ - u8 shift; /* increases accuracy of multiply by shifting. */ - /* Note that bits may be lost if shift is set too high */ - u8 jitter; /* if set compensate for fluctuations */ - u32 nsec_per_cyc; /* set by register_time_interpolator() */ - void *addr; /* address of counter or function */ - cycles_t mask; /* mask the valid bits of the counter */ - unsigned long offset; /* nsec offset at last update of interpolator */ - u64 last_counter; /* counter value in units of the counter at last update */ - cycles_t last_cycle; /* Last timer value if TIME_SOURCE_JITTER is set */ - u64 frequency; /* frequency in counts/second */ - long drift; /* drift in parts-per-million (or -1) */ - unsigned long skips; /* skips forward */ - unsigned long ns_skipped; /* nanoseconds skipped */ - struct time_interpolator *next; -}; - -extern void register_time_interpolator(struct time_interpolator *); -extern void unregister_time_interpolator(struct time_interpolator *); -extern void time_interpolator_reset(void); -extern unsigned long time_interpolator_get_offset(void); -extern void time_interpolator_update(long delta_nsec); - -#else /* !CONFIG_TIME_INTERPOLATION */ - -static inline void time_interpolator_reset(void) -{ -} - -static inline void time_interpolator_update(long delta_nsec) -{ -} - -#endif /* !CONFIG_TIME_INTERPOLATION */ - #define TICK_LENGTH_SHIFT 32 #ifdef CONFIG_NO_HZ diff --git a/include/linux/topology.h b/include/linux/topology.h index d0890a7e5bab..525d437b1253 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -185,7 +185,6 @@ .max_interval = 64*num_online_cpus(), \ .busy_factor = 128, \ .imbalance_pct = 133, \ - .cache_hot_time = (10*1000000), \ .cache_nice_tries = 1, \ .busy_idx = 3, \ .idle_idx = 3, \ diff --git a/include/linux/tty.h b/include/linux/tty.h index 691a1748d9d2..60478f6e5dc6 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -21,7 +21,6 @@ * (Note: the *_driver.minor_start values 1, 64, 128, 192 are * hardcoded at present.) */ -#define NR_PTYS CONFIG_LEGACY_PTY_COUNT /* Number of legacy ptys */ #define NR_UNIX98_PTY_DEFAULT 4096 /* Default maximum for Unix98 ptys */ #define NR_UNIX98_PTY_MAX (1 << MINORBITS) /* Absolute limit */ #define NR_LDISCS 17 @@ -274,6 +273,8 @@ struct tty_struct { #define TTY_PTY_LOCK 16 /* pty private */ #define TTY_NO_WRITE_SPLIT 17 /* Preserve write boundaries to driver */ #define TTY_HUPPED 18 /* Post driver->hangup() */ +#define TTY_FLUSHING 19 /* Flushing to ldisc in progress */ +#define TTY_FLUSHPENDING 20 /* Queued buffer flush pending */ #define TTY_WRITE_FLUSH(tty) tty_write_flush((tty)) diff --git a/include/linux/uio_driver.h b/include/linux/uio_driver.h new file mode 100644 index 000000000000..44c28e94df50 --- /dev/null +++ b/include/linux/uio_driver.h @@ -0,0 +1,91 @@ +/* + * include/linux/uio_driver.h + * + * Copyright(C) 2005, Benedikt Spranger <b.spranger@linutronix.de> + * Copyright(C) 2005, Thomas Gleixner <tglx@linutronix.de> + * Copyright(C) 2006, Hans J. Koch <hjk@linutronix.de> + * Copyright(C) 2006, Greg Kroah-Hartman <greg@kroah.com> + * + * Userspace IO driver. + * + * Licensed under the GPLv2 only. + */ + +#ifndef _UIO_DRIVER_H_ +#define _UIO_DRIVER_H_ + +#include <linux/module.h> +#include <linux/fs.h> +#include <linux/interrupt.h> + +/** + * struct uio_mem - description of a UIO memory region + * @kobj: kobject for this mapping + * @addr: address of the device's memory + * @size: size of IO + * @memtype: type of memory addr points to + * @internal_addr: ioremap-ped version of addr, for driver internal use + */ +struct uio_mem { + struct kobject kobj; + unsigned long addr; + unsigned long size; + int memtype; + void __iomem *internal_addr; +}; + +#define MAX_UIO_MAPS 5 + +struct uio_device; + +/** + * struct uio_info - UIO device capabilities + * @uio_dev: the UIO device this info belongs to + * @name: device name + * @version: device driver version + * @mem: list of mappable memory regions, size==0 for end of list + * @irq: interrupt number or UIO_IRQ_CUSTOM + * @irq_flags: flags for request_irq() + * @priv: optional private data + * @handler: the device's irq handler + * @mmap: mmap operation for this uio device + * @open: open operation for this uio device + * @release: release operation for this uio device + */ +struct uio_info { + struct uio_device *uio_dev; + char *name; + char *version; + struct uio_mem mem[MAX_UIO_MAPS]; + long irq; + unsigned long irq_flags; + void *priv; + irqreturn_t (*handler)(int irq, struct uio_info *dev_info); + int (*mmap)(struct uio_info *info, struct vm_area_struct *vma); + int (*open)(struct uio_info *info, struct inode *inode); + int (*release)(struct uio_info *info, struct inode *inode); +}; + +extern int __must_check + __uio_register_device(struct module *owner, + struct device *parent, + struct uio_info *info); +static inline int __must_check + uio_register_device(struct device *parent, struct uio_info *info) +{ + return __uio_register_device(THIS_MODULE, parent, info); +} +extern void uio_unregister_device(struct uio_info *info); +extern void uio_event_notify(struct uio_info *info); + +/* defines for uio_device->irq */ +#define UIO_IRQ_CUSTOM -1 +#define UIO_IRQ_NONE -2 + +/* defines for uio_device->memtype */ +#define UIO_MEM_NONE 0 +#define UIO_MEM_PHYS 1 +#define UIO_MEM_LOGICAL 2 +#define UIO_MEM_VIRTUAL 3 + +#endif /* _LINUX_UIO_DRIVER_H_ */ diff --git a/include/linux/umem.h b/include/linux/umem.h deleted file mode 100644 index f36ebfc32bf6..000000000000 --- a/include/linux/umem.h +++ /dev/null @@ -1,138 +0,0 @@ - -/* - * This file contains defines for the - * Micro Memory MM5415 - * family PCI Memory Module with Battery Backup. - * - * Copyright Micro Memory INC 2001. All rights reserved. - * Release under the terms of the GNU GENERAL PUBLIC LICENSE version 2. - * See the file COPYING. - */ - -#ifndef _DRIVERS_BLOCK_MM_H -#define _DRIVERS_BLOCK_MM_H - - -#define IRQ_TIMEOUT (1 * HZ) - -/* CSR register definition */ -#define MEMCTRLSTATUS_MAGIC 0x00 -#define MM_MAGIC_VALUE (unsigned char)0x59 - -#define MEMCTRLSTATUS_BATTERY 0x04 -#define BATTERY_1_DISABLED 0x01 -#define BATTERY_1_FAILURE 0x02 -#define BATTERY_2_DISABLED 0x04 -#define BATTERY_2_FAILURE 0x08 - -#define MEMCTRLSTATUS_MEMORY 0x07 -#define MEM_128_MB 0xfe -#define MEM_256_MB 0xfc -#define MEM_512_MB 0xf8 -#define MEM_1_GB 0xf0 -#define MEM_2_GB 0xe0 - -#define MEMCTRLCMD_LEDCTRL 0x08 -#define LED_REMOVE 2 -#define LED_FAULT 4 -#define LED_POWER 6 -#define LED_FLIP 255 -#define LED_OFF 0x00 -#define LED_ON 0x01 -#define LED_FLASH_3_5 0x02 -#define LED_FLASH_7_0 0x03 -#define LED_POWER_ON 0x00 -#define LED_POWER_OFF 0x01 -#define USER_BIT1 0x01 -#define USER_BIT2 0x02 - -#define MEMORY_INITIALIZED USER_BIT1 - -#define MEMCTRLCMD_ERRCTRL 0x0C -#define EDC_NONE_DEFAULT 0x00 -#define EDC_NONE 0x01 -#define EDC_STORE_READ 0x02 -#define EDC_STORE_CORRECT 0x03 - -#define MEMCTRLCMD_ERRCNT 0x0D -#define MEMCTRLCMD_ERRSTATUS 0x0E - -#define ERROR_DATA_LOG 0x20 -#define ERROR_ADDR_LOG 0x28 -#define ERROR_COUNT 0x3D -#define ERROR_SYNDROME 0x3E -#define ERROR_CHECK 0x3F - -#define DMA_PCI_ADDR 0x40 -#define DMA_LOCAL_ADDR 0x48 -#define DMA_TRANSFER_SIZE 0x50 -#define DMA_DESCRIPTOR_ADDR 0x58 -#define DMA_SEMAPHORE_ADDR 0x60 -#define DMA_STATUS_CTRL 0x68 -#define DMASCR_GO 0x00001 -#define DMASCR_TRANSFER_READ 0x00002 -#define DMASCR_CHAIN_EN 0x00004 -#define DMASCR_SEM_EN 0x00010 -#define DMASCR_DMA_COMP_EN 0x00020 -#define DMASCR_CHAIN_COMP_EN 0x00040 -#define DMASCR_ERR_INT_EN 0x00080 -#define DMASCR_PARITY_INT_EN 0x00100 -#define DMASCR_ANY_ERR 0x00800 -#define DMASCR_MBE_ERR 0x01000 -#define DMASCR_PARITY_ERR_REP 0x02000 -#define DMASCR_PARITY_ERR_DET 0x04000 -#define DMASCR_SYSTEM_ERR_SIG 0x08000 -#define DMASCR_TARGET_ABT 0x10000 -#define DMASCR_MASTER_ABT 0x20000 -#define DMASCR_DMA_COMPLETE 0x40000 -#define DMASCR_CHAIN_COMPLETE 0x80000 - -/* -3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE -READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA -TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE -TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS -(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, -AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING -DMA READ OPERATIONS. -*/ -#define DMASCR_READ 0x60000000 -#define DMASCR_READLINE 0xE0000000 -#define DMASCR_READMULTI 0xC0000000 - - -#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) -#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) - -#define WINDOWMAP_WINNUM 0x7B - -#define DMA_READ_FROM_HOST 0 -#define DMA_WRITE_TO_HOST 1 - -struct mm_dma_desc { - __le64 pci_addr; - __le64 local_addr; - __le32 transfer_size; - u32 zero1; - __le64 next_desc_addr; - __le64 sem_addr; - __le32 control_bits; - u32 zero2; - - dma_addr_t data_dma_handle; - - /* Copy of the bits */ - __le64 sem_control_bits; -} __attribute__((aligned(8))); - -#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332 -#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415 -#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425 -#define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155 - -/* bits for card->flags */ -#define UM_FLAG_DMA_IN_REGS 1 -#define UM_FLAG_NO_BYTE_STATUS 2 -#define UM_FLAG_NO_BATTREG 4 -#define UM_FLAG_NO_BATT 8 -#endif diff --git a/include/linux/usb.h b/include/linux/usb.h index 7a60946df3b6..c5c8f169d3cf 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -52,6 +52,7 @@ struct ep_device; * @ep_dev: ep_device for sysfs info * @extra: descriptors following this endpoint in the configuration * @extralen: how many bytes of "extra" are valid + * @enabled: URBs may be submitted to this endpoint * * USB requests are always queued to a given endpoint, identified by a * descriptor within an active interface in a given USB configuration. @@ -64,6 +65,7 @@ struct usb_host_endpoint { unsigned char *extra; /* Extra descriptors */ int extralen; + int enabled; }; /* host-side wrapper for one interface setting's parsed descriptors */ @@ -94,6 +96,7 @@ enum usb_interface_condition { * endpoint configurations. They will be in no particular order. * @num_altsetting: number of altsettings defined. * @cur_altsetting: the current altsetting. + * @intf_assoc: interface association descriptor * @driver: the USB driver that is bound to this interface. * @minor: the minor number assigned to this interface, if this * interface is bound to a driver that uses the USB major number. @@ -213,6 +216,7 @@ struct usb_interface_cache { * @desc: the device's configuration descriptor. * @string: pointer to the cached version of the iConfiguration string, if * present for this configuration. + * @intf_assoc: list of any interface association descriptors in this config * @interface: array of pointers to usb_interface structures, one for each * interface in the configuration. The number of interfaces is stored * in desc.bNumInterfaces. These pointers are valid only while the @@ -342,6 +346,11 @@ struct usb_tt; * * Usbcore drivers should not set usbdev->state directly. Instead use * usb_set_device_state(). + * + * @authorized: (user space) policy determines if we authorize this + * device to be used or not. By default, wired USB + * devices are authorized. WUSB devices are not, until we + * authorize them from user space. FIXME -- complete doc */ struct usb_device { int devnum; /* Address on USB bus */ @@ -374,8 +383,11 @@ struct usb_device { u8 portnum; /* Parent port number (origin 1) */ u8 level; /* Number of USB hub ancestors */ + unsigned can_submit:1; /* URBs may be submitted */ unsigned discon_suspended:1; /* Disconnected while suspended */ unsigned have_langid:1; /* whether string_langid is valid */ + unsigned authorized:1; /* Policy has determined we can use it */ + unsigned wusb:1; /* Device is Wireless USB */ int string_langid; /* language ID for strings */ /* static strings from the device */ @@ -403,6 +415,7 @@ struct usb_device { int pm_usage_cnt; /* usage counter for autosuspend */ u32 quirks; /* quirks of the whole device */ + atomic_t urbnum; /* number of URBs submitted for the whole device */ #ifdef CONFIG_PM struct delayed_work autosuspend; /* for delayed autosuspends */ @@ -417,6 +430,7 @@ struct usb_device { unsigned persist_enabled:1; /* USB_PERSIST enabled for this dev */ unsigned autosuspend_disabled:1; /* autosuspend and autoresume */ unsigned autoresume_disabled:1; /* disabled by the user */ + unsigned skip_sys_resume:1; /* skip the next system resume */ #endif }; #define to_usb_device(d) container_of(d, struct usb_device, dev) @@ -553,6 +567,29 @@ static inline int usb_make_path (struct usb_device *dev, char *buf, /*-------------------------------------------------------------------------*/ /** + * usb_endpoint_num - get the endpoint's number + * @epd: endpoint to be checked + * + * Returns @epd's number: 0 to 15. + */ +static inline int usb_endpoint_num(const struct usb_endpoint_descriptor *epd) +{ + return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; +} + +/** + * usb_endpoint_type - get the endpoint's transfer type + * @epd: endpoint to be checked + * + * Returns one of USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT} according + * to @epd's transfer type. + */ +static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd) +{ + return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; +} + +/** * usb_endpoint_dir_in - check if the endpoint has IN direction * @epd: endpoint to be checked * @@ -994,6 +1031,8 @@ extern int usb_disabled(void); /* * urb->transfer_flags: + * + * Note: URB_DIR_IN/OUT is automatically set in usb_submit_urb(). */ #define URB_SHORT_NOT_OK 0x0001 /* report short reads as errors */ #define URB_ISO_ASAP 0x0002 /* iso-only, urb->start_frame @@ -1006,6 +1045,10 @@ extern int usb_disabled(void); * needed */ #define URB_FREE_BUFFER 0x0100 /* Free transfer buffer with the URB */ +#define URB_DIR_IN 0x0200 /* Transfer from device to host */ +#define URB_DIR_OUT 0 +#define URB_DIR_MASK URB_DIR_IN + struct usb_iso_packet_descriptor { unsigned int offset; unsigned int length; /* expected length */ @@ -1035,6 +1078,8 @@ typedef void (*usb_complete_t)(struct urb *); * @urb_list: For use by current owner of the URB. * @anchor_list: membership in the list of an anchor * @anchor: to anchor URBs to a common mooring + * @ep: Points to the endpoint's data structure. Will eventually + * replace @pipe. * @pipe: Holds endpoint number, direction, type, and more. * Create these values with the eight macros available; * usb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is "ctrl" @@ -1199,10 +1244,10 @@ struct urb { /* private: usb core and host controller only fields in the urb */ struct kref kref; /* reference count of the URB */ - spinlock_t lock; /* lock for the URB */ void *hcpriv; /* private data for host controller */ atomic_t use_count; /* concurrent submissions counter */ u8 reject; /* submissions will fail */ + int unlinked; /* unlink error code */ /* public: documented fields in the urb that can be used by drivers */ struct list_head urb_list; /* list head for use by the urb's @@ -1210,6 +1255,7 @@ struct urb struct list_head anchor_list; /* the URB may be anchored by the driver */ struct usb_anchor *anchor; struct usb_device *dev; /* (in) pointer to associated device */ + struct usb_host_endpoint *ep; /* (internal) pointer to endpoint struct */ unsigned int pipe; /* (in) pipe information */ int status; /* (return) non-ISO status */ unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/ @@ -1255,7 +1301,6 @@ static inline void usb_fill_control_urb (struct urb *urb, usb_complete_t complete_fn, void *context) { - spin_lock_init(&urb->lock); urb->dev = dev; urb->pipe = pipe; urb->setup_packet = setup_packet; @@ -1286,7 +1331,6 @@ static inline void usb_fill_bulk_urb (struct urb *urb, usb_complete_t complete_fn, void *context) { - spin_lock_init(&urb->lock); urb->dev = dev; urb->pipe = pipe; urb->transfer_buffer = transfer_buffer; @@ -1322,7 +1366,6 @@ static inline void usb_fill_int_urb (struct urb *urb, void *context, int interval) { - spin_lock_init(&urb->lock); urb->dev = dev; urb->pipe = pipe; urb->transfer_buffer = transfer_buffer; @@ -1350,6 +1393,30 @@ extern void usb_unanchor_urb(struct urb *urb); extern int usb_wait_anchor_empty_timeout(struct usb_anchor *anchor, unsigned int timeout); +/** + * usb_urb_dir_in - check if an URB describes an IN transfer + * @urb: URB to be checked + * + * Returns 1 if @urb describes an IN transfer (device-to-host), + * otherwise 0. + */ +static inline int usb_urb_dir_in(struct urb *urb) +{ + return (urb->transfer_flags & URB_DIR_MASK) == URB_DIR_IN; +} + +/** + * usb_urb_dir_out - check if an URB describes an OUT transfer + * @urb: URB to be checked + * + * Returns 1 if @urb describes an OUT transfer (host-to-device), + * otherwise 0. + */ +static inline int usb_urb_dir_out(struct urb *urb) +{ + return (urb->transfer_flags & URB_DIR_MASK) == URB_DIR_OUT; +} + void *usb_buffer_alloc (struct usb_device *dev, size_t size, gfp_t mem_flags, dma_addr_t *dma); void usb_buffer_free (struct usb_device *dev, size_t size, @@ -1362,13 +1429,13 @@ void usb_buffer_unmap (struct urb *urb); #endif struct scatterlist; -int usb_buffer_map_sg(const struct usb_device *dev, unsigned pipe, +int usb_buffer_map_sg(const struct usb_device *dev, int is_in, struct scatterlist *sg, int nents); #if 0 -void usb_buffer_dmasync_sg(const struct usb_device *dev, unsigned pipe, +void usb_buffer_dmasync_sg(const struct usb_device *dev, int is_in, struct scatterlist *sg, int n_hw_ents); #endif -void usb_buffer_unmap_sg(const struct usb_device *dev, unsigned pipe, +void usb_buffer_unmap_sg(const struct usb_device *dev, int is_in, struct scatterlist *sg, int n_hw_ents); /*-------------------------------------------------------------------* diff --git a/include/linux/usb_gadget.h b/include/linux/usb/gadget.h index 4f59b2aa8a9e..46705e91573d 100644 --- a/include/linux/usb_gadget.h +++ b/include/linux/usb/gadget.h @@ -1,5 +1,5 @@ /* - * <linux/usb_gadget.h> + * <linux/usb/gadget.h> * * We call the USB code inside a Linux-based peripheral device a "gadget" * driver, except for the hardware-specific bus glue. One USB host can @@ -22,10 +22,10 @@ struct usb_ep; /** * struct usb_request - describes one i/o request * @buf: Buffer used for data. Always provide this; some controllers - * only use PIO, or don't use DMA for some endpoints. + * only use PIO, or don't use DMA for some endpoints. * @dma: DMA address corresponding to 'buf'. If you don't set this - * field, and the usb controller needs one, it is responsible - * for mapping and unmapping the buffer. + * field, and the usb controller needs one, it is responsible + * for mapping and unmapping the buffer. * @length: Length of that data * @no_interrupt: If true, hints that no completion irq is needed. * Helpful sometimes with deep request queues that are handled @@ -45,16 +45,16 @@ struct usb_ep; * @context: For use by the completion callback * @list: For use by the gadget driver. * @status: Reports completion code, zero or a negative errno. - * Normally, faults block the transfer queue from advancing until - * the completion callback returns. - * Code "-ESHUTDOWN" indicates completion caused by device disconnect, - * or when the driver disabled the endpoint. + * Normally, faults block the transfer queue from advancing until + * the completion callback returns. + * Code "-ESHUTDOWN" indicates completion caused by device disconnect, + * or when the driver disabled the endpoint. * @actual: Reports bytes transferred to/from the buffer. For reads (OUT - * transfers) this may be less than the requested length. If the - * short_not_ok flag is set, short reads are treated as errors - * even when status otherwise indicates successful completion. - * Note that for writes (IN transfers) some data bytes may still - * reside in a device-side FIFO when the request is reported as + * transfers) this may be less than the requested length. If the + * short_not_ok flag is set, short reads are treated as errors + * even when status otherwise indicates successful completion. + * Note that for writes (IN transfers) some data bytes may still + * reside in a device-side FIFO when the request is reported as * complete. * * These are allocated/freed through the endpoint they're used with. The @@ -128,7 +128,7 @@ struct usb_ep_ops { * value can sometimes be reduced (hardware allowing), according to * the endpoint descriptor used to configure the endpoint. * @driver_data:for use by the gadget driver. all other fields are - * read-only to gadget drivers. + * read-only to gadget drivers. * * the bus controller driver lists all the general purpose endpoints in * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, @@ -148,10 +148,10 @@ struct usb_ep { /** * usb_ep_enable - configure endpoint, making it usable * @ep:the endpoint being configured. may not be the endpoint named "ep0". - * drivers discover endpoints through the ep_list of a usb_gadget. + * drivers discover endpoints through the ep_list of a usb_gadget. * @desc:descriptor for desired behavior. caller guarantees this pointer - * remains valid until the endpoint is disabled; the data byte order - * is little-endian (usb-standard). + * remains valid until the endpoint is disabled; the data byte order + * is little-endian (usb-standard). * * when configurations are set, or when interface settings change, the driver * will enable or disable the relevant endpoints. while it is enabled, an @@ -232,7 +232,7 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req) * @ep:the endpoint associated with the request * @req:the request being submitted * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't - * pre-allocate all necessary memory with the request. + * pre-allocate all necessary memory with the request. * * This tells the device controller to perform the specified request through * that endpoint (reading or writing a buffer). When the request completes, @@ -415,7 +415,7 @@ struct usb_gadget_ops { * struct usb_gadget - represents a usb slave device * @ops: Function pointers used to access hardware-specific operations. * @ep0: Endpoint zero, used when reading or writing responses to - * driver setup() requests + * driver setup() requests * @ep_list: List of other endpoints supported by the device. * @speed: Speed of current connection to USB host. * @is_dualspeed: True if the controller supports both high and full speed @@ -432,7 +432,7 @@ struct usb_gadget_ops { * @b_hnp_enable: OTG device feature flag, indicating that the A-Host * enabled HNP support. * @name: Identifies the controller hardware type. Used in diagnostics - * and sometimes configuration. + * and sometimes configuration. * @dev: Driver model state for this abstract device. * * Gadgets have a mostly-portable "gadget driver" implementing device @@ -480,6 +480,39 @@ static inline void *get_gadget_data (struct usb_gadget *gadget) /** + * gadget_is_dualspeed - return true iff the hardware handles high speed + * @gadget: controller that might support both high and full speeds + */ +static inline int gadget_is_dualspeed(struct usb_gadget *g) +{ +#ifdef CONFIG_USB_GADGET_DUALSPEED + /* runtime test would check "g->is_dualspeed" ... that might be + * useful to work around hardware bugs, but is mostly pointless + */ + return 1; +#else + return 0; +#endif +} + +/** + * gadget_is_otg - return true iff the hardware is OTG-ready + * @gadget: controller that might have a Mini-AB connector + * + * This is a runtime test, since kernels with a USB-OTG stack sometimes + * run on boards which only have a Mini-B (or Mini-A) connector. + */ +static inline int gadget_is_otg(struct usb_gadget *g) +{ +#ifdef CONFIG_USB_OTG + return g->is_otg; +#else + return 0; +#endif +} + + +/** * usb_gadget_frame_number - returns the current frame number * @gadget: controller that reports the frame number * @@ -655,23 +688,23 @@ usb_gadget_disconnect (struct usb_gadget *gadget) * @function: String describing the gadget's function * @speed: Highest speed the driver handles. * @bind: Invoked when the driver is bound to a gadget, usually - * after registering the driver. - * At that point, ep0 is fully initialized, and ep_list holds - * the currently-available endpoints. - * Called in a context that permits sleeping. + * after registering the driver. + * At that point, ep0 is fully initialized, and ep_list holds + * the currently-available endpoints. + * Called in a context that permits sleeping. * @setup: Invoked for ep0 control requests that aren't handled by - * the hardware level driver. Most calls must be handled by - * the gadget driver, including descriptor and configuration - * management. The 16 bit members of the setup data are in - * USB byte order. Called in_interrupt; this may not sleep. Driver + * the hardware level driver. Most calls must be handled by + * the gadget driver, including descriptor and configuration + * management. The 16 bit members of the setup data are in + * USB byte order. Called in_interrupt; this may not sleep. Driver * queues a response to ep0, or returns negative to stall. * @disconnect: Invoked after all transfers have been stopped, - * when the host is disconnected. May be called in_interrupt; this - * may not sleep. Some devices can't detect disconnect, so this might + * when the host is disconnected. May be called in_interrupt; this + * may not sleep. Some devices can't detect disconnect, so this might * not be called except as part of controller shutdown. * @unbind: Invoked when the driver is unbound from a gadget, - * usually from rmmod (after a disconnect is reported). - * Called in a context that permits sleeping. + * usually from rmmod (after a disconnect is reported). + * Called in a context that permits sleeping. * @suspend: Invoked on USB suspend. May be called in_interrupt. * @resume: Invoked on USB resume. May be called in_interrupt. * @driver: Driver model state for this driver. diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h index 8da374caf582..2692ec9389ca 100644 --- a/include/linux/usb/quirks.h +++ b/include/linux/usb/quirks.h @@ -4,11 +4,8 @@ * belong here. */ -/* device must not be autosuspended */ -#define USB_QUIRK_NO_AUTOSUSPEND 0x00000001 - /* string descriptors must not be fetched using a 255-byte read */ -#define USB_QUIRK_STRING_FETCH_255 0x00000002 +#define USB_QUIRK_STRING_FETCH_255 0x00000001 /* device can't resume correctly so reset it instead */ -#define USB_QUIRK_RESET_RESUME 0x00000004 +#define USB_QUIRK_RESET_RESUME 0x00000002 diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h index e8b8928232c8..488ce128885c 100644 --- a/include/linux/usb/serial.h +++ b/include/linux/usb/serial.h @@ -141,7 +141,7 @@ struct usb_serial { }; #define to_usb_serial(d) container_of(d, struct usb_serial, kref) -#define NUM_DONT_CARE (-1) +#define NUM_DONT_CARE 99 /* get and set the serial private data pointer helper functions */ static inline void *usb_get_serial_data (struct usb_serial *serial) @@ -160,12 +160,18 @@ static inline void usb_set_serial_data (struct usb_serial *serial, void *data) * in the syslog messages when a device is inserted or removed. * @id_table: pointer to a list of usb_device_id structures that define all * of the devices this structure can support. - * @num_interrupt_in: the number of interrupt in endpoints this device will - * have. - * @num_interrupt_out: the number of interrupt out endpoints this device will - * have. - * @num_bulk_in: the number of bulk in endpoints this device will have. - * @num_bulk_out: the number of bulk out endpoints this device will have. + * @num_interrupt_in: If a device doesn't have this many interrupt-in + * endpoints, it won't be sent to the driver's attach() method. + * (But it might still be sent to the probe() method.) + * @num_interrupt_out: If a device doesn't have this many interrupt-out + * endpoints, it won't be sent to the driver's attach() method. + * (But it might still be sent to the probe() method.) + * @num_bulk_in: If a device doesn't have this many bulk-in + * endpoints, it won't be sent to the driver's attach() method. + * (But it might still be sent to the probe() method.) + * @num_bulk_out: If a device doesn't have this many bulk-out + * endpoints, it won't be sent to the driver's attach() method. + * (But it might still be sent to the probe() method.) * @num_ports: the number of different ports this device will have. * @calc_num_ports: pointer to a function to determine how many ports this * device has dynamically. It will be called after the probe() diff --git a/include/linux/usb_sl811.h b/include/linux/usb_sl811.h deleted file mode 100644 index 4f2d012d7309..000000000000 --- a/include/linux/usb_sl811.h +++ /dev/null @@ -1,26 +0,0 @@ - -/* - * board initialization should put one of these into dev->platform_data - * and place the sl811hs onto platform_bus named "sl811-hcd". - */ - -struct sl811_platform_data { - unsigned can_wakeup:1; - - /* given port_power, msec/2 after power on till power good */ - u8 potpg; - - /* mA/2 power supplied on this port (max = default = 250) */ - u8 power; - - /* sl811 relies on an external source of VBUS current */ - void (*port_power)(struct device *dev, int is_on); - - /* pulse sl811 nRST (probably with a GPIO) */ - void (*reset)(struct device *dev); - - // some boards need something like these: - // int (*check_overcurrent)(struct device *dev); - // void (*clock_enable)(struct device *dev, int is_on); -}; - diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h index bb320573bb9e..b5f41d4c2eec 100644 --- a/include/linux/user_namespace.h +++ b/include/linux/user_namespace.h @@ -11,7 +11,7 @@ struct user_namespace { struct kref kref; - struct list_head uidhash_table[UIDHASH_SZ]; + struct hlist_head uidhash_table[UIDHASH_SZ]; struct user_struct *root_user; }; @@ -49,7 +49,7 @@ static inline struct user_namespace *copy_user_ns(int flags, if (flags & CLONE_NEWUSER) return ERR_PTR(-EINVAL); - return NULL; + return old_ns; } static inline void put_user_ns(struct user_namespace *ns) diff --git a/include/linux/video_output.h b/include/linux/video_output.h index e63e0c03ee0d..2fb46bc9340d 100644 --- a/include/linux/video_output.h +++ b/include/linux/video_output.h @@ -31,9 +31,9 @@ struct output_properties { struct output_device { int request_state; struct output_properties *props; - struct class_device class_dev; + struct device dev; }; -#define to_output_device(obj) container_of(obj, struct output_device, class_dev) +#define to_output_device(obj) container_of(obj, struct output_device, dev) struct output_device *video_output_register(const char *name, struct device *dev, void *devdata, diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index d16a2b57dc81..1f503e94eff1 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -60,6 +60,7 @@ #include <linux/compiler.h> /* need __user */ #else #define __user +#include <sys/time.h> #endif #include <linux/types.h> @@ -270,6 +271,7 @@ struct v4l2_pix_format /* Pixel format FOURCC depth Description */ #define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */ +#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R','4','4','4') /* 16 xxxxrrrr ggggbbbb */ #define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */ #define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */ #define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */ @@ -279,6 +281,7 @@ struct v4l2_pix_format #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */ #define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P','A','L','8') /* 8 8-bit palette */ #define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */ #define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */ #define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y','U','Y','V') /* 16 YUV 4:2:2 */ @@ -286,6 +289,10 @@ struct v4l2_pix_format #define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16 YVU422 planar */ #define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16 YVU411 planar */ #define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */ +#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y','4','4','4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y','U','V','O') /* 16 YUV-5-5-5 */ +#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y','U','V','P') /* 16 YUV-5-6-5 */ +#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y','U','V','4') /* 32 YUV-8-8-8-8 */ /* two planes -- one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N','V','1','2') /* 12 Y/CbCr 4:2:0 */ @@ -297,7 +304,6 @@ struct v4l2_pix_format #define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y','Y','U','V') /* 16 YUV 4:2:2 */ #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H','I','2','4') /* 8 8-bit color */ #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H','M','1','2') /* 8 YUV 4:2:0 16x16 macroblocks */ -#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R','4','4','4') /* 16 xxxxrrrr ggggbbbb */ /* see http://www.siliconimaging.com/RGB%20Bayer.htm */ #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B','A','8','1') /* 8 BGBG.. GRGR.. */ @@ -616,7 +622,6 @@ struct v4l2_framebuffer #define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 #define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 #define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 -#define V4L2_FBUF_CAP_GLOBAL_INV_ALPHA 0x0080 /* Flags for the 'flags' field. */ #define V4L2_FBUF_FLAG_PRIMARY 0x0001 #define V4L2_FBUF_FLAG_OVERLAY 0x0002 @@ -624,7 +629,6 @@ struct v4l2_framebuffer #define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 #define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 #define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 -#define V4L2_FBUF_FLAG_GLOBAL_INV_ALPHA 0x0040 struct v4l2_clip { diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h index 132b260aef1e..89338b468d0d 100644 --- a/include/linux/vmalloc.h +++ b/include/linux/vmalloc.h @@ -58,6 +58,13 @@ void vmalloc_sync_all(void); /* * Lowlevel-APIs (not for driver use!) */ + +static inline size_t get_vm_area_size(const struct vm_struct *area) +{ + /* return actual size without guard page */ + return area->size - PAGE_SIZE; +} + extern struct vm_struct *get_vm_area(unsigned long size, unsigned long flags); extern struct vm_struct *__get_vm_area(unsigned long size, unsigned long flags, unsigned long start, unsigned long end); @@ -70,6 +77,10 @@ extern int map_vm_area(struct vm_struct *area, pgprot_t prot, struct page ***pages); extern void unmap_kernel_range(unsigned long addr, unsigned long size); +/* Allocate/destroy a 'vmalloc' VM area. */ +extern struct vm_struct *alloc_vm_area(size_t size); +extern void free_vm_area(struct vm_struct *area); + /* * Internals. Dont't use.. */ diff --git a/include/linux/writeback.h b/include/linux/writeback.h index 4ef4d22e5e43..c7c3337c3a88 100644 --- a/include/linux/writeback.h +++ b/include/linux/writeback.h @@ -5,6 +5,7 @@ #define WRITEBACK_H #include <linux/sched.h> +#include <linux/fs.h> struct backing_dev_info; @@ -127,7 +128,7 @@ int sync_page_range(struct inode *inode, struct address_space *mapping, loff_t pos, loff_t count); int sync_page_range_nolock(struct inode *inode, struct address_space *mapping, loff_t pos, loff_t count); -void set_page_dirty_balance(struct page *page); +void set_page_dirty_balance(struct page *page, int page_mkwrite); void writeback_set_ratelimit(void); /* pdflush.c */ diff --git a/include/linux/xilinxfb.h b/include/linux/xilinxfb.h new file mode 100644 index 000000000000..f2463f559fb9 --- /dev/null +++ b/include/linux/xilinxfb.h @@ -0,0 +1,30 @@ +/* + * Platform device data for Xilinx Framebuffer device + * + * Copyright 2007 Secret Lab Technologies Ltd. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __XILINXFB_H__ +#define __XILINXFB_H__ + +#include <linux/types.h> + +/* ML300/403 reference design framebuffer driver platform data struct */ +struct xilinxfb_platform_data { + u32 rotate_screen; /* Flag to rotate display 180 degrees */ + u32 screen_height_mm; /* Physical dimentions of screen in mm */ + u32 screen_width_mm; + u32 xres, yres; /* resolution of screen in pixels */ + u32 xvirt, yvirt; /* resolution of memory buffer */ + + /* Physical address of framebuffer memory; If non-zero, driver + * will use provided memory address instead of allocating one from + * the consistent pool. */ + u32 fb_phys; +}; + +#endif /* __XILINXFB_H__ */ diff --git a/include/linux/zlib.h b/include/linux/zlib.h index 9e3192a7dc6f..40c49cb3eb51 100644 --- a/include/linux/zlib.h +++ b/include/linux/zlib.h @@ -82,7 +82,7 @@ struct internal_state; typedef struct z_stream_s { - Byte *next_in; /* next input byte */ + const Byte *next_in; /* next input byte */ uInt avail_in; /* number of bytes available at next_in */ uLong total_in; /* total nb of input bytes read so far */ @@ -699,4 +699,8 @@ extern int zlib_inflateInit2(z_streamp strm, int windowBits); struct internal_state {int dummy;}; /* hack for buggy compilers */ #endif +/* Utility function: initialize zlib, unpack binary blob, clean up zlib, + * return len or negative error code. */ +extern int zlib_inflate_blob(void *dst, unsigned dst_sz, const void *src, unsigned src_sz); + #endif /* _ZLIB_H */ diff --git a/include/math-emu/op-common.h b/include/math-emu/op-common.h index 93780abd01bc..bb46e7645d53 100644 --- a/include/math-emu/op-common.h +++ b/include/math-emu/op-common.h @@ -145,13 +145,16 @@ do { \ { \ X##_e = 1; \ _FP_FRAC_SET_##wc(X, _FP_ZEROFRAC_##wc); \ + FP_SET_EXCEPTION(FP_EX_INEXACT); \ } \ else \ { \ X##_e = 0; \ _FP_FRAC_SRL_##wc(X, _FP_WORKBITS); \ - FP_SET_EXCEPTION(FP_EX_UNDERFLOW); \ } \ + if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT) || \ + (FP_TRAPPING_EXCEPTIONS & FP_EX_UNDERFLOW)) \ + FP_SET_EXCEPTION(FP_EX_UNDERFLOW); \ } \ else \ { \ diff --git a/include/math-emu/soft-fp.h b/include/math-emu/soft-fp.h index d02eb64a865b..a6f873b45f98 100644 --- a/include/math-emu/soft-fp.h +++ b/include/math-emu/soft-fp.h @@ -97,12 +97,19 @@ #define FP_INHIBIT_RESULTS 0 #endif +#ifndef FP_TRAPPING_EXCEPTIONS +#define FP_TRAPPING_EXCEPTIONS 0 +#endif + #define FP_SET_EXCEPTION(ex) \ _fex |= (ex) #define FP_UNSET_EXCEPTION(ex) \ _fex &= ~(ex) +#define FP_CUR_EXCEPTIONS \ + (_fex) + #define FP_CLEAR_EXCEPTIONS \ _fex = 0 diff --git a/include/media/cx2341x.h b/include/media/cx2341x.h index 38c12fed7535..af8071d7620d 100644 --- a/include/media/cx2341x.h +++ b/include/media/cx2341x.h @@ -91,7 +91,7 @@ int cx2341x_update(void *priv, cx2341x_mbox_func func, int cx2341x_ctrl_query(struct cx2341x_mpeg_params *params, struct v4l2_queryctrl *qctrl); const char **cx2341x_ctrl_get_menu(u32 id); -int cx2341x_ext_ctrls(struct cx2341x_mpeg_params *params, +int cx2341x_ext_ctrls(struct cx2341x_mpeg_params *params, int busy, struct v4l2_ext_controls *ctrls, unsigned int cmd); void cx2341x_fill_defaults(struct cx2341x_mpeg_params *p); void cx2341x_log_status(struct cx2341x_mpeg_params *p, const char *prefix); diff --git a/include/media/ir-common.h b/include/media/ir-common.h index 9807a7c15830..7a785fa77212 100644 --- a/include/media/ir-common.h +++ b/include/media/ir-common.h @@ -140,6 +140,7 @@ extern IR_KEYTAB_TYPE ir_codes_budget_ci_old[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_asus_pc39[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_encore_enltv[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_tt_1500[IR_KEYTAB_SIZE]; +extern IR_KEYTAB_TYPE ir_codes_fusionhdtv_mce[IR_KEYTAB_SIZE]; #endif diff --git a/include/media/saa7146.h b/include/media/saa7146.h index d3f4f5a38214..cd3ff2c29d5e 100644 --- a/include/media/saa7146.h +++ b/include/media/saa7146.h @@ -114,7 +114,7 @@ struct saa7146_dev struct mutex lock; unsigned char __iomem *mem; /* pointer to mapped IO memory */ - int revision; /* chip revision; needed for bug-workarounds*/ + u32 revision; /* chip revision; needed for bug-workarounds*/ /* pci-device & irq stuff*/ char name[32]; @@ -146,7 +146,6 @@ struct saa7146_dev /* from saa7146_i2c.c */ int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); -int saa7146_i2c_transfer(struct saa7146_dev *saa, const struct i2c_msg *msgs, int num, int retries); /* from saa7146_core.c */ extern struct list_head saa7146_devices; @@ -157,8 +156,8 @@ struct saa7146_format* format_by_fourcc(struct saa7146_dev *dev, int fourcc); int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); -char *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); -void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, char *mem, struct saa7146_pgtable *pt); +void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); +void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); diff --git a/include/media/saa7146_vv.h b/include/media/saa7146_vv.h index cce20ed5cf6c..e49f7e156061 100644 --- a/include/media/saa7146_vv.h +++ b/include/media/saa7146_vv.h @@ -4,7 +4,7 @@ #include <linux/videodev.h> #include <media/v4l2-common.h> #include <media/saa7146.h> -#include <media/video-buf.h> +#include <media/videobuf-dma-sg.h> #define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */ #define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */ diff --git a/include/media/tuner-types.h b/include/media/tuner-types.h index e5ad3fcfe984..b201371416a0 100644 --- a/include/media/tuner-types.h +++ b/include/media/tuner-types.h @@ -79,6 +79,10 @@ struct tuner_params { /* Select 18% (or according to datasheet 0%) L standard PLL gating, vs the driver default of 36%. */ unsigned int default_pll_gating_18:1; + /* IF to use in radio mode. Tuners with a separate radio IF filter + seem to use 10.7, while those without use 33.3 for PAL/SECAM tuners + and 41.3 for NTSC tuners. 0 = 10.7, 1 = 33.3, 2 = 41.3 */ + unsigned int radio_if:2; /* Default tda9887 TOP value in dB for the low band. Default is 0. Range: -16:+15 */ signed int default_top_low:5; diff --git a/include/media/tuner.h b/include/media/tuner.h index 6dcf3c45707d..c03dceb92605 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -23,8 +23,6 @@ #define _TUNER_H #include <linux/videodev2.h> -#include <linux/i2c.h> -#include <media/tuner-types.h> extern int tuner_debug; @@ -124,6 +122,7 @@ extern int tuner_debug; #define TUNER_THOMSON_FE6600 72 /* DViCO FusionHDTV DVB-T Hybrid */ #define TUNER_SAMSUNG_TCPG_6121P30A 73 /* Hauppauge PVR-500 PAL */ #define TUNER_TDA9887 74 /* This tuner should be used only internally */ +#define TUNER_TEA5761 75 /* Only FM Radio Tuner */ /* tv card specific */ #define TDA9887_PRESENT (1<<0) @@ -147,6 +146,7 @@ extern int tuner_debug; #define TDA9887_AUTOMUTE (1<<18) #define TDA9887_GATING_18 (1<<19) #define TDA9887_GAIN_NORMAL (1<<20) +#define TDA9887_RIF_41_3 (1<<21) /* radio IF1 41.3 vs 33.3 */ #ifdef __KERNEL__ @@ -182,74 +182,6 @@ struct tuner_setup { int (*tuner_callback) (void *dev, int command,int arg); }; -struct tuner { - /* device */ - struct i2c_client i2c; - - unsigned int type; /* chip type */ - - unsigned int mode; - unsigned int mode_mask; /* Combination of allowable modes */ - - unsigned int tv_freq; /* keep track of the current settings */ - unsigned int radio_freq; - u16 last_div; - unsigned int audmode; - v4l2_std_id std; - - int using_v4l2; - - /* used by tda9887 */ - unsigned int tda9887_config; - unsigned char tda9887_data[4]; - - /* used by MT2032 */ - unsigned int xogc; - unsigned int radio_if2; - - /* used by tda8290 */ - unsigned char tda8290_easy_mode; - unsigned char tda827x_lpsel; - unsigned char tda827x_addr; - unsigned char tda827x_ver; - unsigned int sgIF; - - unsigned int config; - int (*tuner_callback) (void *dev, int command,int arg); - - /* function ptrs */ - void (*set_tv_freq)(struct i2c_client *c, unsigned int freq); - void (*set_radio_freq)(struct i2c_client *c, unsigned int freq); - int (*has_signal)(struct i2c_client *c); - int (*is_stereo)(struct i2c_client *c); - int (*get_afc)(struct i2c_client *c); - void (*tuner_status)(struct i2c_client *c); - void (*standby)(struct i2c_client *c); -}; - -extern unsigned const int tuner_count; - -extern int microtune_init(struct i2c_client *c); -extern int xc3028_init(struct i2c_client *c); -extern int tda8290_init(struct i2c_client *c); -extern int tda8290_probe(struct i2c_client *c); -extern int tea5767_tuner_init(struct i2c_client *c); -extern int default_tuner_init(struct i2c_client *c); -extern int tea5767_autodetection(struct i2c_client *c); -extern int tda9887_tuner_init(struct i2c_client *c); - -#define tuner_warn(fmt, arg...) do {\ - printk(KERN_WARNING "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ - i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) -#define tuner_info(fmt, arg...) do {\ - printk(KERN_INFO "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ - i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) -#define tuner_dbg(fmt, arg...) do {\ - extern int tuner_debug; \ - if (tuner_debug) \ - printk(KERN_DEBUG "%s %d-%04x: " fmt, t->i2c.driver->driver.name, \ - i2c_adapter_id(t->i2c.adapter), t->i2c.addr , ##arg); } while (0) - #endif /* __KERNEL__ */ #endif /* _TUNER_H */ diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index 09d16c4f00f7..8ae42c41dd08 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -65,6 +65,9 @@ enum { V4L2_IDENT_CX23415 = 415, V4L2_IDENT_CX23416 = 416, + /* module vp27smpx: just ident 2700 */ + V4L2_IDENT_VP27SMPX = 2700, + /* module wm8739: just ident 8739 */ V4L2_IDENT_WM8739 = 8739, diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index d62847f846c2..e75d5e6c4cea 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -23,8 +23,6 @@ #include <linux/videodev2.h> #endif -#include <linux/fs.h> - #define VIDEO_MAJOR 81 /* Minor device allocation */ #define MINOR_VFL_TYPE_GRABBER_MIN 0 @@ -88,8 +86,11 @@ struct video_device /* device ops */ const struct file_operations *fops; + /* sysfs */ + struct device class_dev; /* v4l device */ + struct device *dev; /* device parent */ + /* device info */ - struct device *dev; char name[32]; int type; /* v4l1 */ int type2; /* v4l2 */ @@ -334,9 +335,11 @@ void *priv; /* for videodev.c intenal usage -- please don't touch */ int users; /* video_exclusive_{open|close} ... */ struct mutex lock; /* ... helper function uses these */ - struct class_device class_dev; /* sysfs */ }; +/* Class-dev to video-device */ +#define to_video_device(cd) container_of(cd, struct video_device, class_dev) + /* Version 2 functions */ extern int video_register_device(struct video_device *vfd, int type, int nr); void video_unregister_device(struct video_device *); @@ -354,25 +357,23 @@ extern int video_usercopy(struct inode *inode, struct file *file, int (*func)(struct inode *inode, struct file *file, unsigned int cmd, void *arg)); - #ifdef CONFIG_VIDEO_V4L1_COMPAT #include <linux/mm.h> -#define to_video_device(cd) container_of(cd, struct video_device, class_dev) static inline int __must_check video_device_create_file(struct video_device *vfd, - struct class_device_attribute *attr) + struct device_attribute *attr) { - int ret = class_device_create_file(&vfd->class_dev, attr); + int ret = device_create_file(&vfd->class_dev, attr); if (ret < 0) printk(KERN_WARNING "%s error: %d\n", __FUNCTION__, ret); return ret; } static inline void video_device_remove_file(struct video_device *vfd, - struct class_device_attribute *attr) + struct device_attribute *attr) { - class_device_remove_file(&vfd->class_dev, attr); + device_remove_file(&vfd->class_dev, attr); } #endif /* CONFIG_VIDEO_V4L1_COMPAT */ diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h new file mode 100644 index 000000000000..066ebfc4f983 --- /dev/null +++ b/include/media/v4l2-int-device.h @@ -0,0 +1,278 @@ +/* + * include/media/v4l2-int-device.h + * + * V4L2 internal ioctl interface. + * + * Copyright (C) 2007 Nokia Corporation. + * + * Contact: Sakari Ailus <sakari.ailus@nokia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#ifndef V4L2_INT_DEVICE_H +#define V4L2_INT_DEVICE_H + +#include <linux/module.h> +#include <media/v4l2-common.h> + +#define V4L2NAMESIZE 32 + +/* + * + * The internal V4L2 device interface core. + * + */ + +enum v4l2_int_type { + v4l2_int_type_master = 1, + v4l2_int_type_slave +}; + +struct v4l2_int_device; + +struct v4l2_int_master { + int (*attach)(struct v4l2_int_device *master, + struct v4l2_int_device *slave); + void (*detach)(struct v4l2_int_device *master); +}; + +typedef int (v4l2_int_ioctl_func)(struct v4l2_int_device *); +typedef int (v4l2_int_ioctl_func_0)(struct v4l2_int_device *); +typedef int (v4l2_int_ioctl_func_1)(struct v4l2_int_device *, void *); + +struct v4l2_int_ioctl_desc { + int num; + v4l2_int_ioctl_func *func; +}; + +struct v4l2_int_slave { + /* Don't touch master. */ + struct v4l2_int_device *master; + + char attach_to[V4L2NAMESIZE]; + + int num_ioctls; + struct v4l2_int_ioctl_desc *ioctls; +}; + +struct v4l2_int_device { + /* Don't touch head. */ + struct list_head head; + + struct module *module; + + char name[V4L2NAMESIZE]; + + enum v4l2_int_type type; + union { + struct v4l2_int_master *master; + struct v4l2_int_slave *slave; + } u; + + void *priv; +}; + +int v4l2_int_device_register(struct v4l2_int_device *d); +void v4l2_int_device_unregister(struct v4l2_int_device *d); + +int v4l2_int_ioctl_0(struct v4l2_int_device *d, int cmd); +int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg); + +/* + * + * Types and definitions for IOCTL commands. + * + */ + +/* Slave interface type. */ +enum v4l2_if_type { + /* + * Parallel 8-, 10- or 12-bit interface, used by for example + * on certain image sensors. + */ + V4L2_IF_TYPE_BT656, +}; + +enum v4l2_if_type_bt656_mode { + /* + * Modes without Bt synchronisation codes. Separate + * synchronisation signal lines are used. + */ + V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT, + V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT, + V4L2_IF_TYPE_BT656_MODE_NOBT_12BIT, + /* + * Use Bt synchronisation codes. The vertical and horizontal + * synchronisation is done based on synchronisation codes. + */ + V4L2_IF_TYPE_BT656_MODE_BT_8BIT, + V4L2_IF_TYPE_BT656_MODE_BT_10BIT, +}; + +struct v4l2_if_type_bt656 { + /* + * 0: Frame begins when vsync is high. + * 1: Frame begins when vsync changes from low to high. + */ + unsigned frame_start_on_rising_vs:1; + /* Use Bt synchronisation codes for sync correction. */ + unsigned bt_sync_correct:1; + /* Swap every two adjacent image data elements. */ + unsigned swap:1; + /* Inverted latch clock polarity from slave. */ + unsigned latch_clk_inv:1; + /* Hs polarity. 0 is active high, 1 active low. */ + unsigned nobt_hs_inv:1; + /* Vs polarity. 0 is active high, 1 active low. */ + unsigned nobt_vs_inv:1; + enum v4l2_if_type_bt656_mode mode; + /* Minimum accepted bus clock for slave (in Hz). */ + u32 clock_min; + /* Maximum accepted bus clock for slave. */ + u32 clock_max; + /* + * Current wish of the slave. May only change in response to + * ioctls that affect image capture. + */ + u32 clock_curr; +}; + +struct v4l2_ifparm { + enum v4l2_if_type if_type; + union { + struct v4l2_if_type_bt656 bt656; + } u; +}; + +/* IOCTL command numbers. */ +enum v4l2_int_ioctl_num { + /* + * + * "Proper" V4L ioctls, as in struct video_device. + * + */ + vidioc_int_enum_fmt_cap_num = 1, + vidioc_int_g_fmt_cap_num, + vidioc_int_s_fmt_cap_num, + vidioc_int_try_fmt_cap_num, + vidioc_int_queryctrl_num, + vidioc_int_g_ctrl_num, + vidioc_int_s_ctrl_num, + vidioc_int_g_parm_num, + vidioc_int_s_parm_num, + + /* + * + * Strictly internal ioctls. + * + */ + /* Initialise the device when slave attaches to the master. */ + vidioc_int_dev_init_num = 1000, + /* Delinitialise the device at slave detach. */ + vidioc_int_dev_exit_num, + /* Set device power state: 0 is off, non-zero is on. */ + vidioc_int_s_power_num, + /* Get slave interface parameters. */ + vidioc_int_g_ifparm_num, + /* Does the slave need to be reset after VIDIOC_DQBUF? */ + vidioc_int_g_needs_reset_num, + + /* + * + * VIDIOC_INT_* ioctls. + * + */ + /* VIDIOC_INT_RESET */ + vidioc_int_reset_num, + /* VIDIOC_INT_INIT */ + vidioc_int_init_num, + /* VIDIOC_INT_G_CHIP_IDENT */ + vidioc_int_g_chip_ident_num, + + /* + * + * Start of private ioctls. + * + */ + vidioc_int_priv_start_num = 2000, +}; + +/* + * + * IOCTL wrapper functions for better type checking. + * + */ + +#define V4L2_INT_WRAPPER_0(name) \ + static inline int vidioc_int_##name(struct v4l2_int_device *d) \ + { \ + return v4l2_int_ioctl_0(d, vidioc_int_##name##_num); \ + } \ + \ + static inline struct v4l2_int_ioctl_desc \ + vidioc_int_##name##_cb(int (*func) \ + (struct v4l2_int_device *)) \ + { \ + struct v4l2_int_ioctl_desc desc; \ + \ + desc.num = vidioc_int_##name##_num; \ + desc.func = (v4l2_int_ioctl_func *)func; \ + \ + return desc; \ + } + +#define V4L2_INT_WRAPPER_1(name, arg_type, asterisk) \ + static inline int vidioc_int_##name(struct v4l2_int_device *d, \ + arg_type asterisk arg) \ + { \ + return v4l2_int_ioctl_1(d, vidioc_int_##name##_num, \ + (void *)(unsigned long)arg); \ + } \ + \ + static inline struct v4l2_int_ioctl_desc \ + vidioc_int_##name##_cb(int (*func) \ + (struct v4l2_int_device *, \ + arg_type asterisk)) \ + { \ + struct v4l2_int_ioctl_desc desc; \ + \ + desc.num = vidioc_int_##name##_num; \ + desc.func = (v4l2_int_ioctl_func *)func; \ + \ + return desc; \ + } + +V4L2_INT_WRAPPER_1(enum_fmt_cap, struct v4l2_fmtdesc, *); +V4L2_INT_WRAPPER_1(g_fmt_cap, struct v4l2_format, *); +V4L2_INT_WRAPPER_1(s_fmt_cap, struct v4l2_format, *); +V4L2_INT_WRAPPER_1(try_fmt_cap, struct v4l2_format, *); +V4L2_INT_WRAPPER_1(queryctrl, struct v4l2_queryctrl, *); +V4L2_INT_WRAPPER_1(g_ctrl, struct v4l2_control, *); +V4L2_INT_WRAPPER_1(s_ctrl, struct v4l2_control, *); +V4L2_INT_WRAPPER_1(g_parm, struct v4l2_streamparm, *); +V4L2_INT_WRAPPER_1(s_parm, struct v4l2_streamparm, *); + +V4L2_INT_WRAPPER_0(dev_init); +V4L2_INT_WRAPPER_0(dev_exit); +V4L2_INT_WRAPPER_1(s_power, int, ); +V4L2_INT_WRAPPER_1(g_ifparm, struct v4l2_ifparm, *); +V4L2_INT_WRAPPER_1(g_needs_reset, void, *); + +V4L2_INT_WRAPPER_0(reset); +V4L2_INT_WRAPPER_0(init); +V4L2_INT_WRAPPER_1(g_chip_ident, int, *); + +#endif diff --git a/include/media/video-buf.h b/include/media/videobuf-core.h index d6f079476db3..9fa09fb800a1 100644 --- a/include/media/video-buf.h +++ b/include/media/videobuf-core.h @@ -1,48 +1,26 @@ /* + * generic helper functions for handling video4linux capture buffers * - * generic helper functions for video4linux capture buffers, to handle - * memory management and PCI DMA. - * Right now, bttv, saa7134, saa7146 and cx88 use it. - * - * The functions expect the hardware being able to scatter gatter - * (i.e. the buffers are not linear in physical memory, but fragmented - * into PAGE_SIZE chunks). They also assume the driver does not need - * to touch the video data. - * - * device specific map/unmap/sync stuff now are mapped as file operations - * to allow its usage by USB and virtual devices. + * (c) 2007 Mauro Carvalho Chehab, <mchehab@infradead.org> * + * Highly based on video-buf written originally by: * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> * (c) 2006 Mauro Carvalho Chehab, <mchehab@infradead.org> * (c) 2006 Ted Walther and John Sokol * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; either version 2 */ -#include <linux/videodev2.h> #include <linux/poll.h> +#ifdef CONFIG_VIDEO_V4L1_COMPAT +#include <linux/videodev.h> +#endif +#include <linux/videodev2.h> #define UNSET (-1U) -/* --------------------------------------------------------------------- */ - -/* - * Return a scatterlist for some page-aligned vmalloc()'ed memory - * block (NULL on errors). Memory for the scatterlist is allocated - * using kmalloc. The caller must free the memory. - */ -struct scatterlist* videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages); - -/* - * Return a scatterlist for a an array of userpages (NULL on errors). - * Memory for the scatterlist is allocated using kmalloc. The caller - * must free the memory. - */ -struct scatterlist* videobuf_pages_to_sg(struct page **pages, int nr_pages, - int offset); struct videobuf_buffer; struct videobuf_queue; @@ -50,69 +28,6 @@ struct videobuf_queue; /* --------------------------------------------------------------------- */ /* - * A small set of helper functions to manage buffers (both userland - * and kernel) for DMA. - * - * videobuf_dma_init_*() - * creates a buffer. The userland version takes a userspace - * pointer + length. The kernel version just wants the size and - * does memory allocation too using vmalloc_32(). - * - * videobuf_dma_*() - * see Documentation/DMA-mapping.txt, these functions to - * basically the same. The map function does also build a - * scatterlist for the buffer (and unmap frees it ...) - * - * videobuf_dma_free() - * no comment ... - * - */ - -struct videobuf_dmabuf { - u32 magic; - - /* for userland buffer */ - int offset; - struct page **pages; - - /* for kernel buffers */ - void *vmalloc; - - /* Stores the userspace pointer to vmalloc area */ - void *varea; - - /* for overlay buffers (pci-pci dma) */ - dma_addr_t bus_addr; - - /* common */ - struct scatterlist *sglist; - int sglen; - int nr_pages; - int direction; -}; - -void videobuf_dma_init(struct videobuf_dmabuf *dma); -int videobuf_dma_init_user(struct videobuf_dmabuf *dma, int direction, - unsigned long data, unsigned long size); -int videobuf_dma_init_kernel(struct videobuf_dmabuf *dma, int direction, - int nr_pages); -int videobuf_dma_init_overlay(struct videobuf_dmabuf *dma, int direction, - dma_addr_t addr, int nr_pages); -int videobuf_dma_free(struct videobuf_dmabuf *dma); - -int videobuf_dma_map(struct videobuf_queue* q,struct videobuf_dmabuf *dma); -int videobuf_dma_sync(struct videobuf_queue* q,struct videobuf_dmabuf *dma); -int videobuf_dma_unmap(struct videobuf_queue* q,struct videobuf_dmabuf *dma); - - /*FIXME: these variants are used only on *-alsa code, where videobuf is - * used without queue - */ -int videobuf_pci_dma_map(struct pci_dev *pci,struct videobuf_dmabuf *dma); -int videobuf_pci_dma_unmap(struct pci_dev *pci,struct videobuf_dmabuf *dma); - -/* --------------------------------------------------------------------- */ - -/* * A small set of helper functions to manage video4linux buffers. * * struct videobuf_buffer holds the data structures used by the helper @@ -162,26 +77,33 @@ struct videobuf_buffer { unsigned int input; enum v4l2_field field; enum videobuf_state state; - struct videobuf_dmabuf dma; struct list_head stream; /* QBUF/DQBUF list */ - /* for mmap'ed buffers */ - enum v4l2_memory memory; - size_t boff; /* buffer offset (mmap + overlay) */ - size_t bsize; /* buffer size */ - unsigned long baddr; /* buffer addr (userland ptr!) */ - struct videobuf_mapping *map; - /* touched by irq handler */ struct list_head queue; wait_queue_head_t done; unsigned int field_count; struct timeval ts; -}; -typedef int (vb_map_sg_t)(void *dev,struct scatterlist *sglist,int nr_pages, - int direction); + /* Memory type */ + enum v4l2_memory memory; + + /* buffer size */ + size_t bsize; + + /* buffer offset (mmap + overlay) */ + size_t boff; + /* buffer addr (userland ptr!) */ + unsigned long baddr; + + /* for mmap'ed buffers */ + struct videobuf_mapping *map; + + /* Private pointer to allow specific methods to store their data */ + int privsize; + void *priv; +}; struct videobuf_queue_ops { int (*buf_setup)(struct videobuf_queue *q, @@ -193,14 +115,37 @@ struct videobuf_queue_ops { struct videobuf_buffer *vb); void (*buf_release)(struct videobuf_queue *q, struct videobuf_buffer *vb); +}; - /* Helper operations - device dependent. - * If null, videobuf_init defaults all to PCI handling - */ +#define MAGIC_QTYPE_OPS 0x12261003 + +/* Helper operations - device type dependent */ +struct videobuf_qtype_ops { + u32 magic; - vb_map_sg_t *vb_map_sg; - vb_map_sg_t *vb_dma_sync_sg; - vb_map_sg_t *vb_unmap_sg; + void* (*alloc) (size_t size); + int (*iolock) (struct videobuf_queue* q, + struct videobuf_buffer *vb, + struct v4l2_framebuffer *fbuf); + int (*mmap) (struct videobuf_queue *q, + unsigned int *count, + unsigned int *size, + enum v4l2_memory memory); + int (*sync) (struct videobuf_queue* q, + struct videobuf_buffer *buf); + int (*copy_to_user) (struct videobuf_queue *q, + char __user *data, + size_t count, + int nonblocking); + int (*copy_stream) (struct videobuf_queue *q, + char __user *data, + size_t count, + size_t pos, + int vbihack, + int nonblocking); + int (*mmap_free) (struct videobuf_queue *q); + int (*mmap_mapper) (struct videobuf_queue *q, + struct vm_area_struct *vma); }; struct videobuf_queue { @@ -215,6 +160,7 @@ struct videobuf_queue { enum v4l2_field last; /* for field=V4L2_FIELD_ALTERNATE */ struct videobuf_buffer *bufs[VIDEO_MAX_FRAME]; struct videobuf_queue_ops *ops; + struct videobuf_qtype_ops *int_ops; /* capture via mmap() + ioctl(QBUF/DQBUF) */ unsigned int streaming; @@ -229,28 +175,25 @@ struct videobuf_queue { void *priv_data; }; -void* videobuf_alloc(unsigned int size); int videobuf_waiton(struct videobuf_buffer *vb, int non_blocking, int intr); int videobuf_iolock(struct videobuf_queue* q, struct videobuf_buffer *vb, struct v4l2_framebuffer *fbuf); -/* Maps fops to PCI stuff */ -void videobuf_queue_pci(struct videobuf_queue* q); +void *videobuf_alloc(struct videobuf_queue* q); -void videobuf_queue_init(struct videobuf_queue *q, +void videobuf_queue_core_init(struct videobuf_queue *q, struct videobuf_queue_ops *ops, void *dev, spinlock_t *irqlock, enum v4l2_buf_type type, enum v4l2_field field, unsigned int msize, - void *priv); + void *priv, + struct videobuf_qtype_ops *int_ops); int videobuf_queue_is_busy(struct videobuf_queue *q); void videobuf_queue_cancel(struct videobuf_queue *q); enum v4l2_field videobuf_next_field(struct videobuf_queue *q); -void videobuf_status(struct v4l2_buffer *b, struct videobuf_buffer *vb, - enum v4l2_buf_type type); int videobuf_reqbufs(struct videobuf_queue *q, struct v4l2_requestbuffers *req); int videobuf_querybuf(struct videobuf_queue *q, struct v4l2_buffer *b); @@ -258,6 +201,10 @@ int videobuf_qbuf(struct videobuf_queue *q, struct v4l2_buffer *b); int videobuf_dqbuf(struct videobuf_queue *q, struct v4l2_buffer *b, int nonblocking); +#ifdef CONFIG_VIDEO_V4L1_COMPAT +int videobuf_cgmbuf(struct videobuf_queue *q, + struct video_mbuf *mbuf, int count); +#endif int videobuf_streamon(struct videobuf_queue *q); int videobuf_streamoff(struct videobuf_queue *q); diff --git a/include/media/videobuf-dma-sg.h b/include/media/videobuf-dma-sg.h new file mode 100644 index 000000000000..38105031db23 --- /dev/null +++ b/include/media/videobuf-dma-sg.h @@ -0,0 +1,122 @@ +/* + * helper functions for PCI DMA video4linux capture buffers + * + * The functions expect the hardware being able to scatter gatter + * (i.e. the buffers are not linear in physical memory, but fragmented + * into PAGE_SIZE chunks). They also assume the driver does not need + * to touch the video data. + * + * (c) 2007 Mauro Carvalho Chehab, <mchehab@infradead.org> + * + * Highly based on video-buf written originally by: + * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org> + * (c) 2006 Mauro Carvalho Chehab, <mchehab@infradead.org> + * (c) 2006 Ted Walther and John Sokol + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 + */ + +#include <media/videobuf-core.h> + +/* --------------------------------------------------------------------- */ + +/* + * Return a scatterlist for some page-aligned vmalloc()'ed memory + * block (NULL on errors). Memory for the scatterlist is allocated + * using kmalloc. The caller must free the memory. + */ +struct scatterlist* videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages); + +/* + * Return a scatterlist for a an array of userpages (NULL on errors). + * Memory for the scatterlist is allocated using kmalloc. The caller + * must free the memory. + */ +struct scatterlist* videobuf_pages_to_sg(struct page **pages, int nr_pages, + int offset); + +/* --------------------------------------------------------------------- */ + +/* + * A small set of helper functions to manage buffers (both userland + * and kernel) for DMA. + * + * videobuf_dma_init_*() + * creates a buffer. The userland version takes a userspace + * pointer + length. The kernel version just wants the size and + * does memory allocation too using vmalloc_32(). + * + * videobuf_dma_*() + * see Documentation/DMA-mapping.txt, these functions to + * basically the same. The map function does also build a + * scatterlist for the buffer (and unmap frees it ...) + * + * videobuf_dma_free() + * no comment ... + * + */ + +struct videobuf_dmabuf { + u32 magic; + + /* for userland buffer */ + int offset; + struct page **pages; + + /* for kernel buffers */ + void *vmalloc; + + /* Stores the userspace pointer to vmalloc area */ + void *varea; + + /* for overlay buffers (pci-pci dma) */ + dma_addr_t bus_addr; + + /* common */ + struct scatterlist *sglist; + int sglen; + int nr_pages; + int direction; +}; + +struct videbuf_pci_sg_memory +{ + u32 magic; + + /* for mmap'ed buffers */ + struct videobuf_dmabuf dma; +}; + +void videobuf_dma_init(struct videobuf_dmabuf *dma); +int videobuf_dma_init_user(struct videobuf_dmabuf *dma, int direction, + unsigned long data, unsigned long size); +int videobuf_dma_init_kernel(struct videobuf_dmabuf *dma, int direction, + int nr_pages); +int videobuf_dma_init_overlay(struct videobuf_dmabuf *dma, int direction, + dma_addr_t addr, int nr_pages); +int videobuf_dma_free(struct videobuf_dmabuf *dma); + +int videobuf_dma_map(struct videobuf_queue* q,struct videobuf_dmabuf *dma); +int videobuf_dma_sync(struct videobuf_queue* q,struct videobuf_dmabuf *dma); +int videobuf_dma_unmap(struct videobuf_queue* q,struct videobuf_dmabuf *dma); +struct videobuf_dmabuf *videobuf_to_dma (struct videobuf_buffer *buf); + +void *videobuf_pci_alloc (size_t size); + +void videobuf_queue_pci_init(struct videobuf_queue* q, + struct videobuf_queue_ops *ops, + void *dev, + spinlock_t *irqlock, + enum v4l2_buf_type type, + enum v4l2_field field, + unsigned int msize, + void *priv); + + /*FIXME: these variants are used only on *-alsa code, where videobuf is + * used without queue + */ +int videobuf_pci_dma_map(struct pci_dev *pci,struct videobuf_dmabuf *dma); +int videobuf_pci_dma_unmap(struct pci_dev *pci,struct videobuf_dmabuf *dma); + diff --git a/include/media/video-buf-dvb.h b/include/media/videobuf-dvb.h index 8233cafdeef6..8233cafdeef6 100644 --- a/include/media/video-buf-dvb.h +++ b/include/media/videobuf-dvb.h diff --git a/include/media/videobuf-vmalloc.h b/include/media/videobuf-vmalloc.h new file mode 100644 index 000000000000..26a8958d23d1 --- /dev/null +++ b/include/media/videobuf-vmalloc.h @@ -0,0 +1,41 @@ +/* + * helper functions for vmalloc capture buffers + * + * The functions expect the hardware being able to scatter gatter + * (i.e. the buffers are not linear in physical memory, but fragmented + * into PAGE_SIZE chunks). They also assume the driver does not need + * to touch the video data. + * + * (c) 2007 Mauro Carvalho Chehab, <mchehab@infradead.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 + */ + +#include <media/videobuf-core.h> + +/* --------------------------------------------------------------------- */ + +struct videbuf_vmalloc_memory +{ + u32 magic; + + void *vmalloc; + + /* remap_vmalloc_range seems to need to run after mmap() on some cases */ + struct vm_area_struct *vma; +}; + +void videobuf_queue_vmalloc_init(struct videobuf_queue* q, + struct videobuf_queue_ops *ops, + void *dev, + spinlock_t *irqlock, + enum v4l2_buf_type type, + enum v4l2_field field, + unsigned int msize, + void *priv); + +void *videobuf_to_vmalloc (struct videobuf_buffer *buf); + +void videobuf_vmalloc_free (struct videobuf_buffer *buf); diff --git a/include/mtd/ubi-header.h b/include/mtd/ubi-header.h index fa479c71aa34..74efa7763479 100644 --- a/include/mtd/ubi-header.h +++ b/include/mtd/ubi-header.h @@ -74,42 +74,13 @@ enum { UBI_COMPAT_REJECT = 5 }; -/* - * ubi16_t/ubi32_t/ubi64_t - 16, 32, and 64-bit integers used in UBI on-flash - * data structures. - */ -typedef struct { - uint16_t int16; -} __attribute__ ((packed)) ubi16_t; - -typedef struct { - uint32_t int32; -} __attribute__ ((packed)) ubi32_t; - -typedef struct { - uint64_t int64; -} __attribute__ ((packed)) ubi64_t; - -/* - * In this implementation of UBI uses the big-endian format for on-flash - * integers. The below are the corresponding conversion macros. - */ -#define cpu_to_ubi16(x) ((ubi16_t){__cpu_to_be16(x)}) -#define ubi16_to_cpu(x) ((uint16_t)__be16_to_cpu((x).int16)) - -#define cpu_to_ubi32(x) ((ubi32_t){__cpu_to_be32(x)}) -#define ubi32_to_cpu(x) ((uint32_t)__be32_to_cpu((x).int32)) - -#define cpu_to_ubi64(x) ((ubi64_t){__cpu_to_be64(x)}) -#define ubi64_to_cpu(x) ((uint64_t)__be64_to_cpu((x).int64)) - /* Sizes of UBI headers */ #define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr) #define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr) /* Sizes of UBI headers without the ending CRC */ -#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(ubi32_t)) -#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(ubi32_t)) +#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(__be32)) +#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(__be32)) /** * struct ubi_ec_hdr - UBI erase counter header. @@ -137,14 +108,14 @@ typedef struct { * eraseblocks. */ struct ubi_ec_hdr { - ubi32_t magic; - uint8_t version; - uint8_t padding1[3]; - ubi64_t ec; /* Warning: the current limit is 31-bit anyway! */ - ubi32_t vid_hdr_offset; - ubi32_t data_offset; - uint8_t padding2[36]; - ubi32_t hdr_crc; + __be32 magic; + __u8 version; + __u8 padding1[3]; + __be64 ec; /* Warning: the current limit is 31-bit anyway! */ + __be32 vid_hdr_offset; + __be32 data_offset; + __u8 padding2[36]; + __be32 hdr_crc; } __attribute__ ((packed)); /** @@ -262,22 +233,22 @@ struct ubi_ec_hdr { * software (say, cramfs) on top of the UBI volume. */ struct ubi_vid_hdr { - ubi32_t magic; - uint8_t version; - uint8_t vol_type; - uint8_t copy_flag; - uint8_t compat; - ubi32_t vol_id; - ubi32_t lnum; - ubi32_t leb_ver; /* obsolete, to be removed, don't use */ - ubi32_t data_size; - ubi32_t used_ebs; - ubi32_t data_pad; - ubi32_t data_crc; - uint8_t padding1[4]; - ubi64_t sqnum; - uint8_t padding2[12]; - ubi32_t hdr_crc; + __be32 magic; + __u8 version; + __u8 vol_type; + __u8 copy_flag; + __u8 compat; + __be32 vol_id; + __be32 lnum; + __be32 leb_ver; /* obsolete, to be removed, don't use */ + __be32 data_size; + __be32 used_ebs; + __be32 data_pad; + __be32 data_crc; + __u8 padding1[4]; + __be64 sqnum; + __u8 padding2[12]; + __be32 hdr_crc; } __attribute__ ((packed)); /* Internal UBI volumes count */ @@ -306,7 +277,7 @@ struct ubi_vid_hdr { #define UBI_VTBL_RECORD_SIZE sizeof(struct ubi_vtbl_record) /* Size of the volume table record without the ending CRC */ -#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(ubi32_t)) +#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(__be32)) /** * struct ubi_vtbl_record - a record in the volume table. @@ -346,15 +317,15 @@ struct ubi_vid_hdr { * Empty records contain all zeroes and the CRC checksum of those zeroes. */ struct ubi_vtbl_record { - ubi32_t reserved_pebs; - ubi32_t alignment; - ubi32_t data_pad; - uint8_t vol_type; - uint8_t upd_marker; - ubi16_t name_len; - uint8_t name[UBI_VOL_NAME_MAX+1]; - uint8_t padding2[24]; - ubi32_t crc; + __be32 reserved_pebs; + __be32 alignment; + __be32 data_pad; + __u8 vol_type; + __u8 upd_marker; + __be16 name_len; + __u8 name[UBI_VOL_NAME_MAX+1]; + __u8 padding2[24]; + __be32 crc; } __attribute__ ((packed)); #endif /* !__UBI_HEADER_H__ */ diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h index 88884d39f28f..7726ff41c3e6 100644 --- a/include/net/9p/9p.h +++ b/include/net/9p/9p.h @@ -412,6 +412,18 @@ int p9_idpool_check(int id, struct p9_idpool *p); int p9_error_init(void); int p9_errstr2errno(char *, int); + +#ifdef CONFIG_SYSCTL int __init p9_sysctl_register(void); void __exit p9_sysctl_unregister(void); +#else +static inline int p9_sysctl_register(void) +{ + return 0; +} +static inline void p9_sysctl_unregister(void) +{ +} +#endif + #endif /* NET_9P_H */ diff --git a/include/net/af_unix.h b/include/net/af_unix.h index 6de1e9e35c73..0864a775de24 100644 --- a/include/net/af_unix.h +++ b/include/net/af_unix.h @@ -12,37 +12,8 @@ extern void unix_gc(void); #define UNIX_HASH_SIZE 256 -extern struct hlist_head unix_socket_table[UNIX_HASH_SIZE + 1]; -extern spinlock_t unix_table_lock; - extern atomic_t unix_tot_inflight; -static inline struct sock *first_unix_socket(int *i) -{ - for (*i = 0; *i <= UNIX_HASH_SIZE; (*i)++) { - if (!hlist_empty(&unix_socket_table[*i])) - return __sk_head(&unix_socket_table[*i]); - } - return NULL; -} - -static inline struct sock *next_unix_socket(int *i, struct sock *s) -{ - struct sock *next = sk_next(s); - /* More in this chain? */ - if (next) - return next; - /* Look for next non-empty chain. */ - for ((*i)++; *i <= UNIX_HASH_SIZE; (*i)++) { - if (!hlist_empty(&unix_socket_table[*i])) - return __sk_head(&unix_socket_table[*i]); - } - return NULL; -} - -#define forall_unix_sockets(i, s) \ - for (s = first_unix_socket(&(i)); s; s = next_unix_socket(&(i),(s))) - struct unix_address { atomic_t refcnt; int len; diff --git a/include/net/ah.h b/include/net/ah.h index 8f257c159902..ae1c322f4242 100644 --- a/include/net/ah.h +++ b/include/net/ah.h @@ -9,8 +9,6 @@ struct ah_data { - u8 *key; - int key_len; u8 *work_icv; int icv_full_len; int icv_trunc_len; @@ -40,4 +38,11 @@ out: return err; } +struct ip_auth_hdr; + +static inline struct ip_auth_hdr *ip_auth_hdr(const struct sk_buff *skb) +{ + return (struct ip_auth_hdr *)skb_transport_header(skb); +} + #endif diff --git a/include/net/ax25.h b/include/net/ax25.h index 99a4e364c74a..4e3cd93f81fc 100644 --- a/include/net/ax25.h +++ b/include/net/ax25.h @@ -363,8 +363,11 @@ extern int ax25_rx_iframe(ax25_cb *, struct sk_buff *); extern int ax25_kiss_rcv(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *); /* ax25_ip.c */ -extern int ax25_hard_header(struct sk_buff *, struct net_device *, unsigned short, void *, void *, unsigned int); +extern int ax25_hard_header(struct sk_buff *, struct net_device *, + unsigned short, const void *, + const void *, unsigned int); extern int ax25_rebuild_header(struct sk_buff *); +extern const struct header_ops ax25_header_ops; /* ax25_out.c */ extern ax25_cb *ax25_send_frame(struct sk_buff *, int, ax25_address *, ax25_address *, ax25_digi *, struct net_device *); diff --git a/include/net/ax88796.h b/include/net/ax88796.h index ee786a043b3d..51329dae44e6 100644 --- a/include/net/ax88796.h +++ b/include/net/ax88796.h @@ -14,6 +14,7 @@ #define AXFLG_HAS_EEPROM (1<<0) #define AXFLG_MAC_FROMDEV (1<<1) /* device already has MAC */ +#define AXFLG_HAS_93CX6 (1<<2) /* use eeprom_93cx6 driver */ struct ax_plat_data { unsigned int flags; diff --git a/include/net/bluetooth/l2cap.h b/include/net/bluetooth/l2cap.h index 87df4e87622d..70e70f5d3dd6 100644 --- a/include/net/bluetooth/l2cap.h +++ b/include/net/bluetooth/l2cap.h @@ -34,7 +34,7 @@ /* L2CAP socket address */ struct sockaddr_l2 { sa_family_t l2_family; - unsigned short l2_psm; + __le16 l2_psm; bdaddr_t l2_bdaddr; }; @@ -76,32 +76,32 @@ struct l2cap_conninfo { /* L2CAP structures */ struct l2cap_hdr { - __u16 len; - __u16 cid; + __le16 len; + __le16 cid; } __attribute__ ((packed)); #define L2CAP_HDR_SIZE 4 struct l2cap_cmd_hdr { __u8 code; __u8 ident; - __u16 len; + __le16 len; } __attribute__ ((packed)); #define L2CAP_CMD_HDR_SIZE 4 struct l2cap_cmd_rej { - __u16 reason; + __le16 reason; } __attribute__ ((packed)); struct l2cap_conn_req { - __u16 psm; - __u16 scid; + __le16 psm; + __le16 scid; } __attribute__ ((packed)); struct l2cap_conn_rsp { - __u16 dcid; - __u16 scid; - __u16 result; - __u16 status; + __le16 dcid; + __le16 scid; + __le16 result; + __le16 status; } __attribute__ ((packed)); /* connect result */ @@ -117,15 +117,15 @@ struct l2cap_conn_rsp { #define L2CAP_CS_AUTHOR_PEND 0x0002 struct l2cap_conf_req { - __u16 dcid; - __u16 flags; + __le16 dcid; + __le16 flags; __u8 data[0]; } __attribute__ ((packed)); struct l2cap_conf_rsp { - __u16 scid; - __u16 flags; - __u16 result; + __le16 scid; + __le16 flags; + __le16 result; __u8 data[0]; } __attribute__ ((packed)); @@ -149,23 +149,23 @@ struct l2cap_conf_opt { #define L2CAP_CONF_MAX_SIZE 22 struct l2cap_disconn_req { - __u16 dcid; - __u16 scid; + __le16 dcid; + __le16 scid; } __attribute__ ((packed)); struct l2cap_disconn_rsp { - __u16 dcid; - __u16 scid; + __le16 dcid; + __le16 scid; } __attribute__ ((packed)); struct l2cap_info_req { - __u16 type; + __le16 type; __u8 data[0]; } __attribute__ ((packed)); struct l2cap_info_rsp { - __u16 type; - __u16 result; + __le16 type; + __le16 result; __u8 data[0]; } __attribute__ ((packed)); @@ -207,7 +207,7 @@ struct l2cap_conn { struct l2cap_pinfo { struct bt_sock bt; - __u16 psm; + __le16 psm; __u16 dcid; __u16 scid; @@ -225,7 +225,7 @@ struct l2cap_pinfo { __u8 ident; - __u16 sport; + __le16 sport; struct l2cap_conn *conn; struct sock *next_c; diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 7edaef6b29d6..d30960e1755c 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -3,15 +3,15 @@ #include <linux/netlink.h> #include <linux/skbuff.h> +#include <linux/nl80211.h> #include <net/genetlink.h> /* * 802.11 configuration in-kernel interface * - * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> + * Copyright 2006, 2007 Johannes Berg <johannes@sipsolutions.net> */ - /* Radiotap header iteration * implemented in net/wireless/radiotap.c * docs in Documentation/networking/radiotap-headers.txt @@ -68,11 +68,16 @@ struct wiphy; * @add_virtual_intf: create a new virtual interface with the given name * * @del_virtual_intf: remove the virtual interface determined by ifindex. + * + * @change_virtual_intf: change type of virtual interface + * */ struct cfg80211_ops { int (*add_virtual_intf)(struct wiphy *wiphy, char *name, - unsigned int type); + enum nl80211_iftype type); int (*del_virtual_intf)(struct wiphy *wiphy, int ifindex); + int (*change_virtual_intf)(struct wiphy *wiphy, int ifindex, + enum nl80211_iftype type); }; #endif /* __NET_CFG80211_H */ diff --git a/include/net/dn_route.h b/include/net/dn_route.h index c10e8e7e59a7..60c9f22d8694 100644 --- a/include/net/dn_route.h +++ b/include/net/dn_route.h @@ -100,8 +100,7 @@ static inline void dn_rt_finish_output(struct sk_buff *skb, char *dst, char *src if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_LOOPBACK)) dst = NULL; - if (!dev->hard_header || (dev->hard_header(skb, dev, ETH_P_DNA_RT, - dst, src, skb->len) >= 0)) + if (dev_hard_header(skb, dev, ETH_P_DNA_RT, dst, src, skb->len) >= 0) dn_rt_send(skb); else kfree_skb(skb); diff --git a/include/net/esp.h b/include/net/esp.h index d05d8d2c78f4..c1bc529809da 100644 --- a/include/net/esp.h +++ b/include/net/esp.h @@ -13,8 +13,6 @@ struct esp_data /* Confidentiality */ struct { - u8 *key; /* Key */ - int key_len; /* Key length */ int padlen; /* 0..255 */ /* ivlen is offset from enc_data, where encrypted data start. * It is logically different of crypto_tfm_alg_ivsize(tfm). @@ -28,14 +26,9 @@ struct esp_data /* Integrity. It is active when icv_full_len != 0 */ struct { - u8 *key; /* Key */ - int key_len; /* Length of the key */ u8 *work_icv; int icv_full_len; int icv_trunc_len; - void (*icv)(struct esp_data*, - struct sk_buff *skb, - int offset, int len, u8 *icv); struct crypto_hash *tfm; } auth; }; @@ -60,4 +53,11 @@ static inline int esp_mac_digest(struct esp_data *esp, struct sk_buff *skb, return crypto_hash_final(&desc, esp->auth.work_icv); } +struct ip_esp_hdr; + +static inline struct ip_esp_hdr *ip_esp_hdr(const struct sk_buff *skb) +{ + return (struct ip_esp_hdr *)skb_transport_header(skb); +} + #endif diff --git a/include/net/fib_rules.h b/include/net/fib_rules.h index 83e41dd15ccd..017aebd90683 100644 --- a/include/net/fib_rules.h +++ b/include/net/fib_rules.h @@ -65,7 +65,7 @@ struct fib_rules_ops int nlgroup; const struct nla_policy *policy; - struct list_head *rules_list; + struct list_head rules_list; struct module *owner; }; diff --git a/include/net/genetlink.h b/include/net/genetlink.h index b6eaca122db8..decdda546829 100644 --- a/include/net/genetlink.h +++ b/include/net/genetlink.h @@ -5,6 +5,22 @@ #include <net/netlink.h> /** + * struct genl_multicast_group - generic netlink multicast group + * @name: name of the multicast group, names are per-family + * @id: multicast group ID, assigned by the core, to use with + * genlmsg_multicast(). + * @list: list entry for linking + * @family: pointer to family, need not be set before registering + */ +struct genl_multicast_group +{ + struct genl_family *family; /* private */ + struct list_head list; /* private */ + char name[GENL_NAMSIZ]; + u32 id; +}; + +/** * struct genl_family - generic netlink family * @id: protocol family idenfitier * @hdrsize: length of user specific header in bytes @@ -14,6 +30,7 @@ * @attrbuf: buffer to store parsed attributes * @ops_list: list of all assigned operations * @family_list: family list + * @mcast_groups: multicast groups list */ struct genl_family { @@ -25,6 +42,7 @@ struct genl_family struct nlattr ** attrbuf; /* private */ struct list_head ops_list; /* private */ struct list_head family_list; /* private */ + struct list_head mcast_groups; /* private */ }; /** @@ -73,6 +91,10 @@ extern int genl_register_family(struct genl_family *family); extern int genl_unregister_family(struct genl_family *family); extern int genl_register_ops(struct genl_family *, struct genl_ops *ops); extern int genl_unregister_ops(struct genl_family *, struct genl_ops *ops); +extern int genl_register_mc_group(struct genl_family *family, + struct genl_multicast_group *grp); +extern void genl_unregister_mc_group(struct genl_family *family, + struct genl_multicast_group *grp); extern struct sock *genl_sock; diff --git a/include/net/icmp.h b/include/net/icmp.h index dc09474efcf3..9f7ef3c8baef 100644 --- a/include/net/icmp.h +++ b/include/net/icmp.h @@ -30,9 +30,16 @@ struct icmp_err { extern struct icmp_err icmp_err_convert[]; DECLARE_SNMP_STAT(struct icmp_mib, icmp_statistics); +DECLARE_SNMP_STAT(struct icmpmsg_mib, icmpmsg_statistics); #define ICMP_INC_STATS(field) SNMP_INC_STATS(icmp_statistics, field) #define ICMP_INC_STATS_BH(field) SNMP_INC_STATS_BH(icmp_statistics, field) #define ICMP_INC_STATS_USER(field) SNMP_INC_STATS_USER(icmp_statistics, field) +#define ICMPMSGOUT_INC_STATS(field) SNMP_INC_STATS(icmpmsg_statistics, field+256) +#define ICMPMSGOUT_INC_STATS_BH(field) SNMP_INC_STATS_BH(icmpmsg_statistics, field+256) +#define ICMPMSGOUT_INC_STATS_USER(field) SNMP_INC_STATS_USER(icmpmsg_statistics, field+256) +#define ICMPMSGIN_INC_STATS(field) SNMP_INC_STATS(icmpmsg_statistics, field) +#define ICMPMSGIN_INC_STATS_BH(field) SNMP_INC_STATS_BH(icmpmsg_statistics, field) +#define ICMPMSGIN_INC_STATS_USER(field) SNMP_INC_STATS_USER(icmpmsg_statistics, field) struct dst_entry; struct net_proto_family; @@ -42,6 +49,7 @@ extern void icmp_send(struct sk_buff *skb_in, int type, int code, __be32 info); extern int icmp_rcv(struct sk_buff *skb); extern int icmp_ioctl(struct sock *sk, int cmd, unsigned long arg); extern void icmp_init(struct net_proto_family *ops); +extern void icmp_out_count(unsigned char type); /* Move into dst.h ? */ extern int xrlim_allow(struct dst_entry *dst, int timeout); diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h index bbd85cd61ed5..164d13211165 100644 --- a/include/net/ieee80211.h +++ b/include/net/ieee80211.h @@ -119,11 +119,6 @@ do { if (ieee80211_debug_level & (level)) \ #define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) #endif /* CONFIG_IEEE80211_DEBUG */ -/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ - -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] - /* escape_essid() is intended to be used in debug (and possibly error) * messages. It should never be used for passing essid to user space. */ const char *escape_essid(const char *essid, u8 essid_len); diff --git a/include/net/ieee80211_radiotap.h b/include/net/ieee80211_radiotap.h index a0c2b41a24d7..dfd8bf66ce27 100644 --- a/include/net/ieee80211_radiotap.h +++ b/include/net/ieee80211_radiotap.h @@ -40,6 +40,7 @@ #include <linux/if_ether.h> #include <linux/kernel.h> +#include <asm/unaligned.h> /* Radiotap header version (from official NetBSD feed) */ #define IEEE80211RADIOTAP_VERSION "1.5" @@ -255,4 +256,13 @@ enum ieee80211_radiotap_type { (((x) == 14) ? 2484 : ((x) * 5) + 2407) : \ ((x) + 1000) * 5) +/* helpers */ +static inline int ieee80211_get_radiotap_len(unsigned char *data) +{ + struct ieee80211_radiotap_header *hdr = + (struct ieee80211_radiotap_header *)data; + + return le16_to_cpu(get_unaligned(&hdr->it_len)); +} + #endif /* IEEE80211_RADIOTAP_H */ diff --git a/include/net/ieee80211softmac.h b/include/net/ieee80211softmac.h index 89119277553d..1ef6282fdded 100644 --- a/include/net/ieee80211softmac.h +++ b/include/net/ieee80211softmac.h @@ -229,6 +229,8 @@ struct ieee80211softmac_device { /* this lock protects this structure */ spinlock_t lock; + struct workqueue_struct *wq; + u8 running; /* SoftMAC started? */ u8 scanning; diff --git a/include/net/if_inet6.h b/include/net/if_inet6.h index 3ec7d07346d6..448eccb20638 100644 --- a/include/net/if_inet6.h +++ b/include/net/if_inet6.h @@ -154,6 +154,7 @@ struct ipv6_devstat { struct proc_dir_entry *proc_dir_entry; DEFINE_SNMP_STAT(struct ipstats_mib, ipv6); DEFINE_SNMP_STAT(struct icmpv6_mib, icmpv6); + DEFINE_SNMP_STAT(struct icmpv6msg_mib, icmpv6msg); }; struct inet6_dev diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h index d27ee8c0da3f..8228b57eb18f 100644 --- a/include/net/inet_hashtables.h +++ b/include/net/inet_hashtables.h @@ -107,7 +107,7 @@ struct inet_hashinfo { */ struct inet_bind_hashbucket *bhash; - int bhash_size; + unsigned int bhash_size; unsigned int ehash_size; /* All sockets in TCP_LISTEN state will be in here. This is the only diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h index 47d52b2414db..abaff0597270 100644 --- a/include/net/inet_timewait_sock.h +++ b/include/net/inet_timewait_sock.h @@ -115,6 +115,7 @@ struct inet_timewait_sock { #define tw_refcnt __tw_common.skc_refcnt #define tw_hash __tw_common.skc_hash #define tw_prot __tw_common.skc_prot +#define tw_net __tw_common.skc_net volatile unsigned char tw_substate; /* 3 bits hole, try to pack */ unsigned char tw_rcv_wscale; diff --git a/include/net/ip.h b/include/net/ip.h index abf2820a1125..3af3ed9d320b 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -171,7 +171,8 @@ extern unsigned long snmp_fold_field(void *mib[], int offt); extern int snmp_mib_init(void *ptr[2], size_t mibsize, size_t mibalign); extern void snmp_mib_free(void *ptr[2]); -extern int sysctl_local_port_range[2]; +extern void inet_get_local_port_range(int *low, int *high); + extern int sysctl_ip_default_ttl; extern int sysctl_ip_nonlocal_bind; diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h index c48ea873f1e0..857821360bb6 100644 --- a/include/net/ip6_fib.h +++ b/include/net/ip6_fib.h @@ -105,6 +105,10 @@ struct rt6_info struct rt6key rt6i_src; u8 rt6i_protocol; + +#ifdef CONFIG_XFRM + u32 rt6i_flow_cache_genid; +#endif }; static inline struct inet6_dev *ip6_dst_idev(struct dst_entry *dst) diff --git a/include/net/ipcomp.h b/include/net/ipcomp.h index 87c1af3e5e82..330b74e813a9 100644 --- a/include/net/ipcomp.h +++ b/include/net/ipcomp.h @@ -1,14 +1,23 @@ #ifndef _NET_IPCOMP_H #define _NET_IPCOMP_H -#include <linux/crypto.h> #include <linux/types.h> #define IPCOMP_SCRATCH_SIZE 65400 +struct crypto_comp; + struct ipcomp_data { u16 threshold; struct crypto_comp **tfms; }; +struct ip_comp_hdr; +struct sk_buff; + +static inline struct ip_comp_hdr *ip_comp_hdr(const struct sk_buff *skb) +{ + return (struct ip_comp_hdr *)skb_transport_header(skb); +} + #endif diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 46b9dce82f6e..31b3f1b45a2b 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -17,6 +17,7 @@ #include <linux/ipv6.h> #include <linux/hardirq.h> +#include <net/if_inet6.h> #include <net/ndisc.h> #include <net/flow.h> #include <net/snmp.h> @@ -111,45 +112,28 @@ struct frag_hdr { extern int sysctl_ipv6_bindv6only; extern int sysctl_mld_max_msf; -/* MIBs */ -DECLARE_SNMP_STAT(struct ipstats_mib, ipv6_statistics); -#define IP6_INC_STATS(idev,field) ({ \ - struct inet6_dev *_idev = (idev); \ - if (likely(_idev != NULL)) \ - SNMP_INC_STATS(_idev->stats.ipv6, field); \ - SNMP_INC_STATS(ipv6_statistics, field); \ -}) -#define IP6_INC_STATS_BH(idev,field) ({ \ - struct inet6_dev *_idev = (idev); \ - if (likely(_idev != NULL)) \ - SNMP_INC_STATS_BH(_idev->stats.ipv6, field); \ - SNMP_INC_STATS_BH(ipv6_statistics, field); \ -}) -#define IP6_INC_STATS_USER(idev,field) ({ \ +#define _DEVINC(statname, modifier, idev, field) \ +({ \ struct inet6_dev *_idev = (idev); \ if (likely(_idev != NULL)) \ - SNMP_INC_STATS_USER(_idev->stats.ipv6, field); \ - SNMP_INC_STATS_USER(ipv6_statistics, field); \ + SNMP_INC_STATS##modifier((_idev)->stats.statname, (field)); \ + SNMP_INC_STATS##modifier(statname##_statistics, (field)); \ }) + +/* MIBs */ +DECLARE_SNMP_STAT(struct ipstats_mib, ipv6_statistics); + +#define IP6_INC_STATS(idev,field) _DEVINC(ipv6, , idev, field) +#define IP6_INC_STATS_BH(idev,field) _DEVINC(ipv6, _BH, idev, field) +#define IP6_INC_STATS_USER(idev,field) _DEVINC(ipv6, _USER, idev, field) + DECLARE_SNMP_STAT(struct icmpv6_mib, icmpv6_statistics); -#define ICMP6_INC_STATS(idev, field) ({ \ - struct inet6_dev *_idev = (idev); \ - if (likely(_idev != NULL)) \ - SNMP_INC_STATS(idev->stats.icmpv6, field); \ - SNMP_INC_STATS(icmpv6_statistics, field); \ -}) -#define ICMP6_INC_STATS_BH(idev, field) ({ \ - struct inet6_dev *_idev = (idev); \ - if (likely(_idev != NULL)) \ - SNMP_INC_STATS_BH((_idev)->stats.icmpv6, field); \ - SNMP_INC_STATS_BH(icmpv6_statistics, field); \ -}) -#define ICMP6_INC_STATS_USER(idev, field) ({ \ - struct inet6_dev *_idev = (idev); \ - if (likely(_idev != NULL)) \ - SNMP_INC_STATS_USER(_idev->stats.icmpv6, field); \ - SNMP_INC_STATS_USER(icmpv6_statistics, field); \ -}) +DECLARE_SNMP_STAT(struct icmpv6msg_mib, icmpv6msg_statistics); + +#define ICMP6_INC_STATS(idev, field) _DEVINC(icmpv6, , idev, field) +#define ICMP6_INC_STATS_BH(idev, field) _DEVINC(icmpv6, _BH, idev, field) +#define ICMP6_INC_STATS_USER(idev, field) _DEVINC(icmpv6, _USER, idev, field) + #define ICMP6_INC_STATS_OFFSET_BH(idev, field, offset) ({ \ struct inet6_dev *_idev = idev; \ __typeof__(offset) _offset = (offset); \ @@ -157,6 +141,20 @@ DECLARE_SNMP_STAT(struct icmpv6_mib, icmpv6_statistics); SNMP_INC_STATS_OFFSET_BH(_idev->stats.icmpv6, field, _offset); \ SNMP_INC_STATS_OFFSET_BH(icmpv6_statistics, field, _offset); \ }) + +#define ICMP6MSGOUT_INC_STATS(idev, field) \ + _DEVINC(icmpv6msg, , idev, field +256) +#define ICMP6MSGOUT_INC_STATS_BH(idev, field) \ + _DEVINC(icmpv6msg, _BH, idev, field +256) +#define ICMP6MSGOUT_INC_STATS_USER(idev, field) \ + _DEVINC(icmpv6msg, _USER, idev, field +256) +#define ICMP6MSGIN_INC_STATS(idev, field) \ + _DEVINC(icmpv6msg, , idev, field) +#define ICMP6MSGIN_INC_STATS_BH(idev, field) \ + _DEVINC(icmpv6msg, _BH, idev, field) +#define ICMP6MSGIN_INC_STATS_USER(idev, field) \ + _DEVINC(icmpv6msg, _USER, idev, field) + DECLARE_SNMP_STAT(struct udp_mib, udp_stats_in6); DECLARE_SNMP_STAT(struct udp_mib, udplite_stats_in6); #define UDP6_INC_STATS_BH(field, is_udplite) do { \ @@ -376,6 +374,12 @@ static inline int ipv6_addr_any(const struct in6_addr *a) a->s6_addr32[2] | a->s6_addr32[3] ) == 0); } +static inline int ipv6_addr_v4mapped(const struct in6_addr *a) +{ + return ((a->s6_addr32[0] | a->s6_addr32[1]) == 0 && + a->s6_addr32[2] == htonl(0x0000ffff)); +} + /* * find the first different bit between two addresses * length of address must be a multiple of 32bits diff --git a/include/net/iucv/af_iucv.h b/include/net/iucv/af_iucv.h index b6c468cd7f5b..85f80eadfa35 100644 --- a/include/net/iucv/af_iucv.h +++ b/include/net/iucv/af_iucv.h @@ -50,6 +50,12 @@ struct sockaddr_iucv { /* Common socket structures and functions */ +struct sock_msg_q { + struct iucv_path *path; + struct iucv_message msg; + struct list_head list; + spinlock_t lock; +}; #define iucv_sk(__sk) ((struct iucv_sock *) __sk) @@ -65,6 +71,7 @@ struct iucv_sock { struct iucv_path *path; struct sk_buff_head send_skb_q; struct sk_buff_head backlog_skb_q; + struct sock_msg_q message_q; unsigned int send_tag; }; @@ -74,29 +81,8 @@ struct iucv_sock_list { atomic_t autobind_name; }; -static void iucv_sock_destruct(struct sock *sk); -static void iucv_sock_cleanup_listen(struct sock *parent); -static void iucv_sock_kill(struct sock *sk); -static void iucv_sock_close(struct sock *sk); -static int iucv_sock_create(struct socket *sock, int proto); -static int iucv_sock_bind(struct socket *sock, struct sockaddr *addr, - int addr_len); -static int iucv_sock_connect(struct socket *sock, struct sockaddr *addr, - int alen, int flags); -static int iucv_sock_listen(struct socket *sock, int backlog); -static int iucv_sock_accept(struct socket *sock, struct socket *newsock, - int flags); -static int iucv_sock_getname(struct socket *sock, struct sockaddr *addr, - int *len, int peer); -static int iucv_sock_sendmsg(struct kiocb *iocb, struct socket *sock, - struct msghdr *msg, size_t len); -static int iucv_sock_recvmsg(struct kiocb *iocb, struct socket *sock, - struct msghdr *msg, size_t len, int flags); unsigned int iucv_sock_poll(struct file *file, struct socket *sock, poll_table *wait); -static int iucv_sock_release(struct socket *sock); -static int iucv_sock_shutdown(struct socket *sock, int how); - void iucv_sock_link(struct iucv_sock_list *l, struct sock *s); void iucv_sock_unlink(struct iucv_sock_list *l, struct sock *s); int iucv_sock_wait_state(struct sock *sk, int state, int state2, diff --git a/include/net/iw_handler.h b/include/net/iw_handler.h index f23d07ca7c59..369d50e08b99 100644 --- a/include/net/iw_handler.h +++ b/include/net/iw_handler.h @@ -431,7 +431,13 @@ struct iw_public_data { * Those may be called only within the kernel. */ -/* functions that may be called by driver modules */ +/* First : function strictly used inside the kernel */ + +/* Handle /proc/net/wireless, called in net/code/dev.c */ +extern int dev_get_wireless_info(char * buffer, char **start, off_t offset, + int length); + +/* Second : functions that may be called by driver modules */ /* Send a single event to user space */ extern void wireless_send_event(struct net_device * dev, diff --git a/include/net/llc_conn.h b/include/net/llc_conn.h index 00730d21b522..e2374e34989f 100644 --- a/include/net/llc_conn.h +++ b/include/net/llc_conn.h @@ -93,7 +93,7 @@ static __inline__ char llc_backlog_type(struct sk_buff *skb) return skb->cb[sizeof(skb->cb) - 1]; } -extern struct sock *llc_sk_alloc(int family, gfp_t priority, +extern struct sock *llc_sk_alloc(struct net *net, int family, gfp_t priority, struct proto *prot); extern void llc_sk_free(struct sock *sk); diff --git a/include/net/mac80211.h b/include/net/mac80211.h index c34fd9a6160a..5fcc4c104340 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -1,7 +1,9 @@ /* - * Low-level hardware driver -- IEEE 802.11 driver (80211.o) interface + * mac80211 <-> driver interface + * * Copyright 2002-2005, Devicescape Software, Inc. * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz> + * Copyright 2007 Johannes Berg <johannes@sipsolutions.net> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -20,29 +22,51 @@ #include <net/wireless.h> #include <net/cfg80211.h> -/* Note! Only ieee80211_tx_status_irqsafe() and ieee80211_rx_irqsafe() can be +/** + * DOC: Introduction + * + * mac80211 is the Linux stack for 802.11 hardware that implements + * only partial functionality in hard- or firmware. This document + * defines the interface between mac80211 and low-level hardware + * drivers. + */ + +/** + * DOC: Calling mac80211 from interrupts + * + * Only ieee80211_tx_status_irqsafe() and ieee80211_rx_irqsafe() can be * called in hardware interrupt context. The low-level driver must not call any * other functions in hardware interrupt context. If there is a need for such * call, the low-level driver should first ACK the interrupt and perform the - * IEEE 802.11 code call after this, e.g., from a scheduled tasklet (in - * software interrupt context). + * IEEE 802.11 code call after this, e.g. from a scheduled workqueue function. */ -/* - * Frame format used when passing frame between low-level hardware drivers - * and IEEE 802.11 driver the same as used in the wireless media, i.e., - * buffers start with IEEE 802.11 header and include the same octets that - * are sent over air. - * - * If hardware uses IEEE 802.3 headers (and perform 802.3 <-> 802.11 - * conversion in firmware), upper layer 802.11 code needs to be changed to - * support this. - * - * If the receive frame format is not the same as the real frame sent - * on the wireless media (e.g., due to padding etc.), upper layer 802.11 code - * could be updated to provide support for such format assuming this would - * optimize the performance, e.g., by removing need to re-allocation and - * copying of the data. +/** + * DOC: Warning + * + * If you're reading this document and not the header file itself, it will + * be incomplete because not all documentation has been converted yet. + */ + +/** + * DOC: Frame format + * + * As a general rule, when frames are passed between mac80211 and the driver, + * they start with the IEEE 802.11 header and include the same octets that are + * sent over the air except for the FCS which should be calculated by the + * hardware. + * + * There are, however, various exceptions to this rule for advanced features: + * + * The first exception is for hardware encryption and decryption offload + * where the IV/ICV may or may not be generated in hardware. + * + * Secondly, when the hardware handles fragmentation, the frame handed to + * the driver from mac80211 is the MSDU, not the MPDU. + * + * Finally, for received frames, the driver is able to indicate that it has + * filled a radiotap header and put that in front of the frame; if it does + * not do so then mac80211 may add this under certain circumstances. */ #define IEEE80211_CHAN_W_SCAN 0x00000001 @@ -71,14 +95,13 @@ struct ieee80211_channel { #define IEEE80211_RATE_SUPPORTED 0x00000010 #define IEEE80211_RATE_OFDM 0x00000020 #define IEEE80211_RATE_CCK 0x00000040 -#define IEEE80211_RATE_TURBO 0x00000080 #define IEEE80211_RATE_MANDATORY 0x00000100 #define IEEE80211_RATE_CCK_2 (IEEE80211_RATE_CCK | IEEE80211_RATE_PREAMBLE2) #define IEEE80211_RATE_MODULATION(f) \ (f & (IEEE80211_RATE_CCK | IEEE80211_RATE_OFDM)) -/* Low-level driver should set PREAMBLE2, OFDM, CCK, and TURBO flags. +/* Low-level driver should set PREAMBLE2, OFDM and CCK flags. * BASIC, SUPPORTED, ERP, and MANDATORY flags are set in 80211.o based on the * configuration. */ struct ieee80211_rate { @@ -97,44 +120,96 @@ struct ieee80211_rate { * optimizing channel utilization estimates */ }; -/* 802.11g is backwards-compatible with 802.11b, so a wlan card can - * actually be both in 11b and 11g modes at the same time. */ -enum { - MODE_IEEE80211A, /* IEEE 802.11a */ - MODE_IEEE80211B, /* IEEE 802.11b only */ - MODE_ATHEROS_TURBO, /* Atheros Turbo mode (2x.11a at 5 GHz) */ - MODE_IEEE80211G, /* IEEE 802.11g (and 802.11b compatibility) */ - MODE_ATHEROS_TURBOG, /* Atheros Turbo mode (2x.11g at 2.4 GHz) */ +/** + * enum ieee80211_phymode - PHY modes + * + * @MODE_IEEE80211A: 5GHz as defined by 802.11a/802.11h + * @MODE_IEEE80211B: 2.4 GHz as defined by 802.11b + * @MODE_IEEE80211G: 2.4 GHz as defined by 802.11g (with OFDM), + * backwards compatible with 11b mode + * @NUM_IEEE80211_MODES: internal + */ +enum ieee80211_phymode { + MODE_IEEE80211A, + MODE_IEEE80211B, + MODE_IEEE80211G, /* keep last */ NUM_IEEE80211_MODES }; +/** + * struct ieee80211_hw_mode - PHY mode definition + * + * This structure describes the capabilities supported by the device + * in a single PHY mode. + * + * @mode: the PHY mode for this definition + * @num_channels: number of supported channels + * @channels: pointer to array of supported channels + * @num_rates: number of supported bitrates + * @rates: pointer to array of supported bitrates + * @list: internal + */ struct ieee80211_hw_mode { - int mode; /* MODE_IEEE80211... */ - int num_channels; /* Number of channels (below) */ - struct ieee80211_channel *channels; /* Array of supported channels */ - int num_rates; /* Number of rates (below) */ - struct ieee80211_rate *rates; /* Array of supported rates */ - - struct list_head list; /* Internal, don't touch */ + struct list_head list; + struct ieee80211_channel *channels; + struct ieee80211_rate *rates; + enum ieee80211_phymode mode; + int num_channels; + int num_rates; }; +/** + * struct ieee80211_tx_queue_params - transmit queue configuration + * + * The information provided in this structure is required for QoS + * transmit queue configuration. + * + * @aifs: arbitration interface space [0..255, -1: use default] + * @cw_min: minimum contention window [will be a value of the form + * 2^n-1 in the range 1..1023; 0: use default] + * @cw_max: maximum contention window [like @cw_min] + * @burst_time: maximum burst time in units of 0.1ms, 0 meaning disabled + */ struct ieee80211_tx_queue_params { - int aifs; /* 0 .. 255; -1 = use default */ - int cw_min; /* 2^n-1: 1, 3, 7, .. , 1023; 0 = use default */ - int cw_max; /* 2^n-1: 1, 3, 7, .. , 1023; 0 = use default */ - int burst_time; /* maximum burst time in 0.1 ms (i.e., 10 = 1 ms); - * 0 = disabled */ + int aifs; + int cw_min; + int cw_max; + int burst_time; }; +/** + * struct ieee80211_tx_queue_stats_data - transmit queue statistics + * + * @len: number of packets in queue + * @limit: queue length limit + * @count: number of frames sent + */ struct ieee80211_tx_queue_stats_data { - unsigned int len; /* num packets in queue */ - unsigned int limit; /* queue len (soft) limit */ - unsigned int count; /* total num frames sent */ + unsigned int len; + unsigned int limit; + unsigned int count; }; -enum { +/** + * enum ieee80211_tx_queue - transmit queue number + * + * These constants are used with some callbacks that take a + * queue number to set parameters for a queue. + * + * @IEEE80211_TX_QUEUE_DATA0: data queue 0 + * @IEEE80211_TX_QUEUE_DATA1: data queue 1 + * @IEEE80211_TX_QUEUE_DATA2: data queue 2 + * @IEEE80211_TX_QUEUE_DATA3: data queue 3 + * @IEEE80211_TX_QUEUE_DATA4: data queue 4 + * @IEEE80211_TX_QUEUE_SVP: ?? + * @NUM_TX_DATA_QUEUES: number of data queues + * @IEEE80211_TX_QUEUE_AFTER_BEACON: transmit queue for frames to be + * sent after a beacon + * @IEEE80211_TX_QUEUE_BEACON: transmit queue for beacon frames + */ +enum ieee80211_tx_queue { IEEE80211_TX_QUEUE_DATA0, IEEE80211_TX_QUEUE_DATA1, IEEE80211_TX_QUEUE_DATA2, @@ -165,7 +240,6 @@ struct ieee80211_low_level_stats { /* Transmit control fields. This data structure is passed to low-level driver * with each TX frame. The low-level driver is responsible for configuring * the hardware to use given values (depending on what is supported). */ -#define HW_KEY_IDX_INVALID -1 struct ieee80211_tx_control { int tx_rate; /* Transmit rate, given as the hw specific value for the @@ -191,22 +265,23 @@ struct ieee80211_tx_control { #define IEEE80211_TXCTL_REQUEUE (1<<7) #define IEEE80211_TXCTL_FIRST_FRAGMENT (1<<8) /* this is a first fragment of * the frame */ -#define IEEE80211_TXCTL_TKIP_NEW_PHASE1_KEY (1<<9) +#define IEEE80211_TXCTL_LONG_RETRY_LIMIT (1<<10) /* this frame should be send + * using the through + * set_retry_limit configured + * long retry value */ u32 flags; /* tx control flags defined * above */ - u8 retry_limit; /* 1 = only first attempt, 2 = one retry, .. */ + u8 key_idx; /* keyidx from hw->set_key(), undefined if + * IEEE80211_TXCTL_DO_NOT_ENCRYPT is set */ + u8 retry_limit; /* 1 = only first attempt, 2 = one retry, .. + * This could be used when set_retry_limit + * is not implemented by the driver */ u8 power_level; /* per-packet transmit power level, in dBm */ u8 antenna_sel_tx; /* 0 = default/diversity, 1 = Ant0, 2 = Ant1 */ - s8 key_idx; /* -1 = do not encrypt, >= 0 keyidx from - * hw->set_key() */ u8 icv_len; /* length of the ICV/MIC field in octets */ u8 iv_len; /* length of the IV field in octets */ - u8 tkip_key[16]; /* generated phase2/phase1 key for hw TKIP */ u8 queue; /* hardware queue to use for this frame; * 0 = highest, hw->queues-1 = lowest */ - u8 sw_retry_attempt; /* number of times hw has tried to - * transmit frame (not incl. hw retries) */ - struct ieee80211_rate *rate; /* internal 80211.o rate */ struct ieee80211_rate *rts_rate; /* internal 80211.o rate * for RTS/CTS */ @@ -219,44 +294,124 @@ struct ieee80211_tx_control { int ifindex; /* internal */ }; -/* Receive status. The low-level driver should provide this information - * (the subset supported by hardware) to the 802.11 code with each received - * frame. */ + +/** + * enum mac80211_rx_flags - receive flags + * + * These flags are used with the @flag member of &struct ieee80211_rx_status. + * @RX_FLAG_MMIC_ERROR: Michael MIC error was reported on this frame. + * Use together with %RX_FLAG_MMIC_STRIPPED. + * @RX_FLAG_DECRYPTED: This frame was decrypted in hardware. + * @RX_FLAG_RADIOTAP: This frame starts with a radiotap header. + * @RX_FLAG_MMIC_STRIPPED: the Michael MIC is stripped off this frame, + * verification has been done by the hardware. + * @RX_FLAG_IV_STRIPPED: The IV/ICV are stripped from this frame. + * If this flag is set, the stack cannot do any replay detection + * hence the driver or hardware will have to do that. + * @RX_FLAG_FAILED_FCS_CRC: Set this flag if the FCS check failed on + * the frame. + * @RX_FLAG_FAILED_PLCP_CRC: Set this flag if the PCLP check failed on + * the frame. + */ +enum mac80211_rx_flags { + RX_FLAG_MMIC_ERROR = 1<<0, + RX_FLAG_DECRYPTED = 1<<1, + RX_FLAG_RADIOTAP = 1<<2, + RX_FLAG_MMIC_STRIPPED = 1<<3, + RX_FLAG_IV_STRIPPED = 1<<4, + RX_FLAG_FAILED_FCS_CRC = 1<<5, + RX_FLAG_FAILED_PLCP_CRC = 1<<6, +}; + +/** + * struct ieee80211_rx_status - receive status + * + * The low-level driver should provide this information (the subset + * supported by hardware) to the 802.11 code with each received + * frame. + * @mactime: MAC timestamp as defined by 802.11 + * @freq: frequency the radio was tuned to when receiving this frame, in MHz + * @channel: channel the radio was tuned to + * @phymode: active PHY mode + * @ssi: signal strength when receiving this frame + * @signal: used as 'qual' in statistics reporting + * @noise: PHY noise when receiving this frame + * @antenna: antenna used + * @rate: data rate + * @flag: %RX_FLAG_* + */ struct ieee80211_rx_status { u64 mactime; - int freq; /* receive frequency in Mhz */ + int freq; int channel; - int phymode; + enum ieee80211_phymode phymode; int ssi; - int signal; /* used as qual in statistics reporting */ + int signal; int noise; int antenna; int rate; -#define RX_FLAG_MMIC_ERROR (1<<0) -#define RX_FLAG_DECRYPTED (1<<1) -#define RX_FLAG_RADIOTAP (1<<2) int flag; }; -/* Transmit status. The low-level driver should provide this information - * (the subset supported by hardware) to the 802.11 code for each transmit - * frame. */ +/** + * enum ieee80211_tx_status_flags - transmit status flags + * + * Status flags to indicate various transmit conditions. + * + * @IEEE80211_TX_STATUS_TX_FILTERED: The frame was not transmitted + * because the destination STA was in powersave mode. + * + * @IEEE80211_TX_STATUS_ACK: Frame was acknowledged + */ +enum ieee80211_tx_status_flags { + IEEE80211_TX_STATUS_TX_FILTERED = 1<<0, + IEEE80211_TX_STATUS_ACK = 1<<1, +}; + +/** + * struct ieee80211_tx_status - transmit status + * + * As much information as possible should be provided for each transmitted + * frame with ieee80211_tx_status(). + * + * @control: a copy of the &struct ieee80211_tx_control passed to the driver + * in the tx() callback. + * + * @flags: transmit status flags, defined above + * + * @ack_signal: signal strength of the ACK frame + * + * @excessive_retries: set to 1 if the frame was retried many times + * but not acknowledged + * + * @retry_count: number of retries + * + * @queue_length: ?? REMOVE + * @queue_number: ?? REMOVE + */ struct ieee80211_tx_status { - /* copied ieee80211_tx_control structure */ struct ieee80211_tx_control control; - -#define IEEE80211_TX_STATUS_TX_FILTERED (1<<0) -#define IEEE80211_TX_STATUS_ACK (1<<1) /* whether the TX frame was ACKed */ - u32 flags; /* tx staus flags defined above */ - - int ack_signal; /* measured signal strength of the ACK frame */ - int excessive_retries; - int retry_count; - - int queue_length; /* information about TX queue */ + u8 flags; + bool excessive_retries; + u8 retry_count; + int ack_signal; + int queue_length; int queue_number; }; +/** + * enum ieee80211_conf_flags - configuration flags + * + * Flags to define PHY configuration options + * + * @IEEE80211_CONF_SHORT_SLOT_TIME: use 802.11g short slot time + * @IEEE80211_CONF_RADIOTAP: add radiotap header at receive time (if supported) + * + */ +enum ieee80211_conf_flags { + IEEE80211_CONF_SHORT_SLOT_TIME = 1<<0, + IEEE80211_CONF_RADIOTAP = 1<<1, +}; /** * struct ieee80211_conf - configuration of the device @@ -264,57 +419,46 @@ struct ieee80211_tx_status { * This struct indicates how the driver shall configure the hardware. * * @radio_enabled: when zero, driver is required to switch off the radio. + * TODO make a flag + * @channel: IEEE 802.11 channel number + * @freq: frequency in MHz + * @channel_val: hardware specific channel value for the channel + * @phymode: PHY mode to activate (REMOVE) + * @chan: channel to switch to, pointer to the channel information + * @mode: pointer to mode definition + * @regulatory_domain: ?? + * @beacon_int: beacon interval (TODO make interface config) + * @flags: configuration flags defined above + * @power_level: transmit power limit for current regulatory domain in dBm + * @antenna_max: maximum antenna gain + * @antenna_sel_tx: transmit antenna selection, 0: default/diversity, + * 1/2: antenna 0/1 + * @antenna_sel_rx: receive antenna selection, like @antenna_sel_tx */ struct ieee80211_conf { int channel; /* IEEE 802.11 channel number */ int freq; /* MHz */ int channel_val; /* hw specific value for the channel */ - int phymode; /* MODE_IEEE80211A, .. */ + enum ieee80211_phymode phymode; struct ieee80211_channel *chan; struct ieee80211_hw_mode *mode; unsigned int regulatory_domain; int radio_enabled; int beacon_int; - -#define IEEE80211_CONF_SHORT_SLOT_TIME (1<<0) /* use IEEE 802.11g Short Slot - * Time */ -#define IEEE80211_CONF_SSID_HIDDEN (1<<1) /* do not broadcast the ssid */ -#define IEEE80211_CONF_RADIOTAP (1<<2) /* use radiotap if supported - check this bit at RX time */ - u32 flags; /* configuration flags defined above */ - - u8 power_level; /* transmit power limit for current - * regulatory domain; in dBm */ - u8 antenna_max; /* maximum antenna gain */ - short tx_power_reduction; /* in 0.1 dBm */ - - /* 0 = default/diversity, 1 = Ant0, 2 = Ant1 */ + u32 flags; + u8 power_level; + u8 antenna_max; u8 antenna_sel_tx; u8 antenna_sel_rx; - - int antenna_def; - int antenna_mode; - - /* Following five fields are used for IEEE 802.11H */ - unsigned int radar_detect; - unsigned int spect_mgmt; - /* All following fields are currently unused. */ - unsigned int quiet_duration; /* duration of quiet period */ - unsigned int quiet_offset; /* how far into the beacon is the quiet - * period */ - unsigned int quiet_period; - u8 radar_firpwr_threshold; - u8 radar_rssi_threshold; - u8 pulse_height_threshold; - u8 pulse_rssi_threshold; - u8 pulse_inband_threshold; }; /** * enum ieee80211_if_types - types of 802.11 network interfaces * + * @IEEE80211_IF_TYPE_INVALID: invalid interface type, not used + * by mac80211 itself * @IEEE80211_IF_TYPE_AP: interface in AP mode. * @IEEE80211_IF_TYPE_MGMT: special interface for communication with hostap * daemon. Drivers should never see this type. @@ -322,16 +466,17 @@ struct ieee80211_conf { * @IEEE80211_IF_TYPE_IBSS: interface in IBSS (ad-hoc) mode. * @IEEE80211_IF_TYPE_MNTR: interface in monitor (rfmon) mode. * @IEEE80211_IF_TYPE_WDS: interface in WDS mode. - * @IEEE80211_IF_TYPE_VLAN: not used. + * @IEEE80211_IF_TYPE_VLAN: VLAN interface bound to an AP, drivers + * will never see this type. */ enum ieee80211_if_types { - IEEE80211_IF_TYPE_AP = 0x00000000, - IEEE80211_IF_TYPE_MGMT = 0x00000001, - IEEE80211_IF_TYPE_STA = 0x00000002, - IEEE80211_IF_TYPE_IBSS = 0x00000003, - IEEE80211_IF_TYPE_MNTR = 0x00000004, - IEEE80211_IF_TYPE_WDS = 0x5A580211, - IEEE80211_IF_TYPE_VLAN = 0x00080211, + IEEE80211_IF_TYPE_INVALID, + IEEE80211_IF_TYPE_AP, + IEEE80211_IF_TYPE_STA, + IEEE80211_IF_TYPE_IBSS, + IEEE80211_IF_TYPE_MNTR, + IEEE80211_IF_TYPE_WDS, + IEEE80211_IF_TYPE_VLAN, }; /** @@ -347,7 +492,6 @@ enum ieee80211_if_types { * @mac_addr: pointer to MAC address of the interface. This pointer is valid * until the interface is removed (i.e. it cannot be used after * remove_interface() callback was called for this interface). - * This pointer will be %NULL for monitor interfaces, be careful. * * This structure is used in add_interface() and remove_interface() * callbacks of &struct ieee80211_hw. @@ -360,7 +504,7 @@ enum ieee80211_if_types { */ struct ieee80211_if_init_conf { int if_id; - int type; + enum ieee80211_if_types type; void *mac_addr; }; @@ -377,11 +521,6 @@ struct ieee80211_if_init_conf { * config_interface() call, so copy the value somewhere if you need * it. * @ssid_len: length of the @ssid field. - * @generic_elem: used (together with @generic_elem_len) by drivers for - * hardware that generate beacons independently. The pointer is valid - * only during the config_interface() call, so copy the value somewhere - * if you need it. - * @generic_elem_len: length of the generic element. * @beacon: beacon template. Valid only if @host_gen_beacon_template in * &struct ieee80211_hw is set. The driver is responsible of freeing * the sk_buff. @@ -396,368 +535,571 @@ struct ieee80211_if_conf { u8 *bssid; u8 *ssid; size_t ssid_len; - u8 *generic_elem; - size_t generic_elem_len; struct sk_buff *beacon; struct ieee80211_tx_control *beacon_control; }; -typedef enum { ALG_NONE, ALG_WEP, ALG_TKIP, ALG_CCMP, ALG_NULL } -ieee80211_key_alg; +/** + * enum ieee80211_key_alg - key algorithm + * @ALG_WEP: WEP40 or WEP104 + * @ALG_TKIP: TKIP + * @ALG_CCMP: CCMP (AES) + */ +enum ieee80211_key_alg { + ALG_WEP, + ALG_TKIP, + ALG_CCMP, +}; -struct ieee80211_key_conf { +/** + * enum ieee80211_key_flags - key flags + * + * These flags are used for communication about keys between the driver + * and mac80211, with the @flags parameter of &struct ieee80211_key_conf. + * + * @IEEE80211_KEY_FLAG_WMM_STA: Set by mac80211, this flag indicates + * that the STA this key will be used with could be using QoS. + * @IEEE80211_KEY_FLAG_GENERATE_IV: This flag should be set by the + * driver to indicate that it requires IV generation for this + * particular key. + * @IEEE80211_KEY_FLAG_GENERATE_MMIC: This flag should be set by + * the driver for a TKIP key if it requires Michael MIC + * generation in software. + */ +enum ieee80211_key_flags { + IEEE80211_KEY_FLAG_WMM_STA = 1<<0, + IEEE80211_KEY_FLAG_GENERATE_IV = 1<<1, + IEEE80211_KEY_FLAG_GENERATE_MMIC= 1<<2, +}; - int hw_key_idx; /* filled + used by low-level driver */ - ieee80211_key_alg alg; - int keylen; - -#define IEEE80211_KEY_FORCE_SW_ENCRYPT (1<<0) /* to be cleared by low-level - driver */ -#define IEEE80211_KEY_DEFAULT_TX_KEY (1<<1) /* This key is the new default TX - key (used only for broadcast - keys). */ -#define IEEE80211_KEY_DEFAULT_WEP_ONLY (1<<2) /* static WEP is the only - configured security policy; - this allows some low-level - drivers to determine when - hwaccel can be used */ - u32 flags; /* key configuration flags defined above */ - - s8 keyidx; /* WEP key index */ +/** + * struct ieee80211_key_conf - key information + * + * This key information is given by mac80211 to the driver by + * the set_key() callback in &struct ieee80211_ops. + * + * @hw_key_idx: To be set by the driver, this is the key index the driver + * wants to be given when a frame is transmitted and needs to be + * encrypted in hardware. + * @alg: The key algorithm. + * @flags: key flags, see &enum ieee80211_key_flags. + * @keyidx: the key index (0-3) + * @keylen: key material length + * @key: key material + */ +struct ieee80211_key_conf { + enum ieee80211_key_alg alg; + u8 hw_key_idx; + u8 flags; + s8 keyidx; + u8 keylen; u8 key[0]; }; #define IEEE80211_SEQ_COUNTER_RX 0 #define IEEE80211_SEQ_COUNTER_TX 1 -typedef enum { - SET_KEY, DISABLE_KEY, REMOVE_ALL_KEYS, -} set_key_cmd; +/** + * enum set_key_cmd - key command + * + * Used with the set_key() callback in &struct ieee80211_ops, this + * indicates whether a key is being removed or added. + * + * @SET_KEY: a key is set + * @DISABLE_KEY: a key must be disabled + */ +enum set_key_cmd { + SET_KEY, DISABLE_KEY, +}; -/* This is driver-visible part of the per-hw state the stack keeps. */ -struct ieee80211_hw { - /* points to the cfg80211 wiphy for this piece. Note - * that you must fill in the perm_addr and dev fields - * of this structure, use the macros provided below. */ - struct wiphy *wiphy; +/** + * enum sta_notify_cmd - sta notify command + * + * Used with the sta_notify() callback in &struct ieee80211_ops, this + * indicates addition and removal of a station to station table + * + * @STA_NOTIFY_ADD: a station was added to the station table + * @STA_NOTIFY_REMOVE: a station being removed from the station table + */ +enum sta_notify_cmd { + STA_NOTIFY_ADD, STA_NOTIFY_REMOVE +}; - /* assigned by mac80211, don't write */ - struct ieee80211_conf conf; +/** + * enum ieee80211_hw_flags - hardware flags + * + * These flags are used to indicate hardware capabilities to + * the stack. Generally, flags here should have their meaning + * done in a way that the simplest hardware doesn't need setting + * any particular flags. There are some exceptions to this rule, + * however, so you are advised to review these flags carefully. + * + * @IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE: + * The device only needs to be supplied with a beacon template. + * If you need the host to generate each beacon then don't use + * this flag and call ieee80211_beacon_get() when you need the + * next beacon frame. Note that if you set this flag, you must + * implement the set_tim() callback for powersave mode to work + * properly. + * This flag is only relevant for access-point mode. + * + * @IEEE80211_HW_RX_INCLUDES_FCS: + * Indicates that received frames passed to the stack include + * the FCS at the end. + * + * @IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING: + * Some wireless LAN chipsets buffer broadcast/multicast frames + * for power saving stations in the hardware/firmware and others + * rely on the host system for such buffering. This option is used + * to configure the IEEE 802.11 upper layer to buffer broadcast and + * multicast frames when there are power saving stations so that + * the driver can fetch them with ieee80211_get_buffered_bc(). Note + * that not setting this flag works properly only when the + * %IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE is also not set because + * otherwise the stack will not know when the DTIM beacon was sent. + * + * @IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED: + * Channels are already configured to the default regulatory domain + * specified in the device's EEPROM + */ +enum ieee80211_hw_flags { + IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE = 1<<0, + IEEE80211_HW_RX_INCLUDES_FCS = 1<<1, + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 1<<2, + IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED = 1<<3, +}; - /* Single thread workqueue available for driver use - * Allocated by mac80211 on registration */ +/** + * struct ieee80211_hw - hardware information and state + * + * This structure contains the configuration and hardware + * information for an 802.11 PHY. + * + * @wiphy: This points to the &struct wiphy allocated for this + * 802.11 PHY. You must fill in the @perm_addr and @dev + * members of this structure using SET_IEEE80211_DEV() + * and SET_IEEE80211_PERM_ADDR(). + * + * @conf: &struct ieee80211_conf, device configuration, don't use. + * + * @workqueue: single threaded workqueue available for driver use, + * allocated by mac80211 on registration and flushed on + * unregistration. + * + * @priv: pointer to private area that was allocated for driver use + * along with this structure. + * + * @flags: hardware flags, see &enum ieee80211_hw_flags. + * + * @extra_tx_headroom: headroom to reserve in each transmit skb + * for use by the driver (e.g. for transmit headers.) + * + * @channel_change_time: time (in microseconds) it takes to change channels. + * + * @max_rssi: Maximum value for ssi in RX information, use + * negative numbers for dBm and 0 to indicate no support. + * + * @max_signal: like @max_rssi, but for the signal value. + * + * @max_noise: like @max_rssi, but for the noise value. + * + * @queues: number of available hardware transmit queues for + * data packets. WMM/QoS requires at least four. + */ +struct ieee80211_hw { + struct ieee80211_conf conf; + struct wiphy *wiphy; struct workqueue_struct *workqueue; - - /* Pointer to the private area that was - * allocated with this struct for you. */ void *priv; - - /* The rest is information about your hardware */ - - /* TODO: frame_type 802.11/802.3, sw_encryption requirements */ - - /* Some wireless LAN chipsets generate beacons in the hardware/firmware - * and others rely on host generated beacons. This option is used to - * configure the upper layer IEEE 802.11 module to generate beacons. - * The low-level driver can use ieee80211_beacon_get() to fetch the - * next beacon frame. */ -#define IEEE80211_HW_HOST_GEN_BEACON (1<<0) - - /* The device needs to be supplied with a beacon template only. */ -#define IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE (1<<1) - - /* Some devices handle decryption internally and do not - * indicate whether the frame was encrypted (unencrypted frames - * will be dropped by the hardware, unless specifically allowed - * through) */ -#define IEEE80211_HW_DEVICE_HIDES_WEP (1<<2) - - /* Whether RX frames passed to ieee80211_rx() include FCS in the end */ -#define IEEE80211_HW_RX_INCLUDES_FCS (1<<3) - - /* Some wireless LAN chipsets buffer broadcast/multicast frames for - * power saving stations in the hardware/firmware and others rely on - * the host system for such buffering. This option is used to - * configure the IEEE 802.11 upper layer to buffer broadcast/multicast - * frames when there are power saving stations so that low-level driver - * can fetch them with ieee80211_get_buffered_bc(). */ -#define IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING (1<<4) - -#define IEEE80211_HW_WEP_INCLUDE_IV (1<<5) - - /* will data nullfunc frames get proper TX status callback */ -#define IEEE80211_HW_DATA_NULLFUNC_ACK (1<<6) - - /* Force software encryption for TKIP packets if WMM is enabled. */ -#define IEEE80211_HW_NO_TKIP_WMM_HWACCEL (1<<7) - - /* Some devices handle Michael MIC internally and do not include MIC in - * the received packets passed up. device_strips_mic must be set - * for such devices. The 'encryption' frame control bit is expected to - * be still set in the IEEE 802.11 header with this option unlike with - * the device_hides_wep configuration option. - */ -#define IEEE80211_HW_DEVICE_STRIPS_MIC (1<<8) - - /* Device is capable of performing full monitor mode even during - * normal operation. */ -#define IEEE80211_HW_MONITOR_DURING_OPER (1<<9) - - /* Device does not need BSSID filter set to broadcast in order to - * receive all probe responses while scanning */ -#define IEEE80211_HW_NO_PROBE_FILTERING (1<<10) - - /* Channels are already configured to the default regulatory domain - * specified in the device's EEPROM */ -#define IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED (1<<11) - - /* calculate Michael MIC for an MSDU when doing hwcrypto */ -#define IEEE80211_HW_TKIP_INCLUDE_MMIC (1<<12) - /* Do TKIP phase1 key mixing in stack to support cards only do - * phase2 key mixing when doing hwcrypto */ -#define IEEE80211_HW_TKIP_REQ_PHASE1_KEY (1<<13) - /* Do TKIP phase1 and phase2 key mixing in stack and send the generated - * per-packet RC4 key with each TX frame when doing hwcrypto */ -#define IEEE80211_HW_TKIP_REQ_PHASE2_KEY (1<<14) - - u32 flags; /* hardware flags defined above */ - - /* Set to the size of a needed device specific skb headroom for TX skbs. */ + u32 flags; unsigned int extra_tx_headroom; - - /* This is the time in us to change channels - */ int channel_change_time; - /* Maximum values for various statistics. - * Leave at 0 to indicate no support. Use negative numbers for dBm. */ + u8 queues; s8 max_rssi; s8 max_signal; s8 max_noise; - - /* Number of available hardware TX queues for data packets. - * WMM requires at least four queues. */ - int queues; }; +/** + * SET_IEEE80211_DEV - set device for 802.11 hardware + * + * @hw: the &struct ieee80211_hw to set the device for + * @dev: the &struct device of this 802.11 device + */ static inline void SET_IEEE80211_DEV(struct ieee80211_hw *hw, struct device *dev) { set_wiphy_dev(hw->wiphy, dev); } +/** + * SET_IEEE80211_PERM_ADDR - set the permanenet MAC address for 802.11 hardware + * + * @hw: the &struct ieee80211_hw to set the MAC address for + * @addr: the address to set + */ static inline void SET_IEEE80211_PERM_ADDR(struct ieee80211_hw *hw, u8 *addr) { memcpy(hw->wiphy->perm_addr, addr, ETH_ALEN); } -/* Configuration block used by the low-level driver to tell the 802.11 code - * about supported hardware features and to pass function pointers to callback - * functions. */ +/** + * DOC: Hardware crypto acceleration + * + * mac80211 is capable of taking advantage of many hardware + * acceleration designs for encryption and decryption operations. + * + * The set_key() callback in the &struct ieee80211_ops for a given + * device is called to enable hardware acceleration of encryption and + * decryption. The callback takes an @address parameter that will be + * the broadcast address for default keys, the other station's hardware + * address for individual keys or the zero address for keys that will + * be used only for transmission. + * Multiple transmission keys with the same key index may be used when + * VLANs are configured for an access point. + * + * The @local_address parameter will always be set to our own address, + * this is only relevant if you support multiple local addresses. + * + * When transmitting, the TX control data will use the @hw_key_idx + * selected by the driver by modifying the &struct ieee80211_key_conf + * pointed to by the @key parameter to the set_key() function. + * + * The set_key() call for the %SET_KEY command should return 0 if + * the key is now in use, -%EOPNOTSUPP or -%ENOSPC if it couldn't be + * added; if you return 0 then hw_key_idx must be assigned to the + * hardware key index, you are free to use the full u8 range. + * + * When the cmd is %DISABLE_KEY then it must succeed. + * + * Note that it is permissible to not decrypt a frame even if a key + * for it has been uploaded to hardware, the stack will not make any + * decision based on whether a key has been uploaded or not but rather + * based on the receive flags. + * + * The &struct ieee80211_key_conf structure pointed to by the @key + * parameter is guaranteed to be valid until another call to set_key() + * removes it, but it can only be used as a cookie to differentiate + * keys. + */ + +/** + * DOC: Frame filtering + * + * mac80211 requires to see many management frames for proper + * operation, and users may want to see many more frames when + * in monitor mode. However, for best CPU usage and power consumption, + * having as few frames as possible percolate through the stack is + * desirable. Hence, the hardware should filter as much as possible. + * + * To achieve this, mac80211 uses filter flags (see below) to tell + * the driver's configure_filter() function which frames should be + * passed to mac80211 and which should be filtered out. + * + * The configure_filter() callback is invoked with the parameters + * @mc_count and @mc_list for the combined multicast address list + * of all virtual interfaces, @changed_flags telling which flags + * were changed and @total_flags with the new flag states. + * + * If your device has no multicast address filters your driver will + * need to check both the %FIF_ALLMULTI flag and the @mc_count + * parameter to see whether multicast frames should be accepted + * or dropped. + * + * All unsupported flags in @total_flags must be cleared, i.e. you + * should clear all bits except those you honoured. + */ + +/** + * enum ieee80211_filter_flags - hardware filter flags + * + * These flags determine what the filter in hardware should be + * programmed to let through and what should not be passed to the + * stack. It is always safe to pass more frames than requested, + * but this has negative impact on power consumption. + * + * @FIF_PROMISC_IN_BSS: promiscuous mode within your BSS, + * think of the BSS as your network segment and then this corresponds + * to the regular ethernet device promiscuous mode. + * + * @FIF_ALLMULTI: pass all multicast frames, this is used if requested + * by the user or if the hardware is not capable of filtering by + * multicast address. + * + * @FIF_FCSFAIL: pass frames with failed FCS (but you need to set the + * %RX_FLAG_FAILED_FCS_CRC for them) + * + * @FIF_PLCPFAIL: pass frames with failed PLCP CRC (but you need to set + * the %RX_FLAG_FAILED_PLCP_CRC for them + * + * @FIF_BCN_PRBRESP_PROMISC: This flag is set during scanning to indicate + * to the hardware that it should not filter beacons or probe responses + * by BSSID. Filtering them can greatly reduce the amount of processing + * mac80211 needs to do and the amount of CPU wakeups, so you should + * honour this flag if possible. + * + * @FIF_CONTROL: pass control frames, if PROMISC_IN_BSS is not set then + * only those addressed to this station + * + * @FIF_OTHER_BSS: pass frames destined to other BSSes + */ +enum ieee80211_filter_flags { + FIF_PROMISC_IN_BSS = 1<<0, + FIF_ALLMULTI = 1<<1, + FIF_FCSFAIL = 1<<2, + FIF_PLCPFAIL = 1<<3, + FIF_BCN_PRBRESP_PROMISC = 1<<4, + FIF_CONTROL = 1<<5, + FIF_OTHER_BSS = 1<<6, +}; + +/** + * enum ieee80211_erp_change_flags - erp change flags + * + * These flags are used with the erp_ie_changed() callback in + * &struct ieee80211_ops to indicate which parameter(s) changed. + * @IEEE80211_ERP_CHANGE_PROTECTION: protection changed + * @IEEE80211_ERP_CHANGE_PREAMBLE: barker preamble mode changed + */ +enum ieee80211_erp_change_flags { + IEEE80211_ERP_CHANGE_PROTECTION = 1<<0, + IEEE80211_ERP_CHANGE_PREAMBLE = 1<<1, +}; + + +/** + * struct ieee80211_ops - callbacks from mac80211 to the driver + * + * This structure contains various callbacks that the driver may + * handle or, in some cases, must handle, for example to configure + * the hardware to a new channel or to transmit a frame. + * + * @tx: Handler that 802.11 module calls for each transmitted frame. + * skb contains the buffer starting from the IEEE 802.11 header. + * The low-level driver should send the frame out based on + * configuration in the TX control data. Must be implemented and + * atomic. + * + * @start: Called before the first netdevice attached to the hardware + * is enabled. This should turn on the hardware and must turn on + * frame reception (for possibly enabled monitor interfaces.) + * Returns negative error codes, these may be seen in userspace, + * or zero. + * When the device is started it should not have a MAC address + * to avoid acknowledging frames before a non-monitor device + * is added. + * Must be implemented. + * + * @stop: Called after last netdevice attached to the hardware + * is disabled. This should turn off the hardware (at least + * it must turn off frame reception.) + * May be called right after add_interface if that rejects + * an interface. + * Must be implemented. + * + * @add_interface: Called when a netdevice attached to the hardware is + * enabled. Because it is not called for monitor mode devices, @open + * and @stop must be implemented. + * The driver should perform any initialization it needs before + * the device can be enabled. The initial configuration for the + * interface is given in the conf parameter. + * The callback may refuse to add an interface by returning a + * negative error code (which will be seen in userspace.) + * Must be implemented. + * + * @remove_interface: Notifies a driver that an interface is going down. + * The @stop callback is called after this if it is the last interface + * and no monitor interfaces are present. + * When all interfaces are removed, the MAC address in the hardware + * must be cleared so the device no longer acknowledges packets, + * the mac_addr member of the conf structure is, however, set to the + * MAC address of the device going away. + * Hence, this callback must be implemented. + * + * @config: Handler for configuration requests. IEEE 802.11 code calls this + * function to change hardware configuration, e.g., channel. + * + * @config_interface: Handler for configuration requests related to interfaces + * (e.g. BSSID changes.) + * + * @configure_filter: Configure the device's RX filter. + * See the section "Frame filtering" for more information. + * This callback must be implemented and atomic. + * + * @set_tim: Set TIM bit. If the hardware/firmware takes care of beacon + * generation (that is, %IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE is set) + * mac80211 calls this function when a TIM bit must be set or cleared + * for a given AID. Must be atomic. + * + * @set_key: See the section "Hardware crypto acceleration" + * This callback can sleep, and is only called between add_interface + * and remove_interface calls, i.e. while the interface with the + * given local_address is enabled. + * + * @set_ieee8021x: Enable/disable IEEE 802.1X. This item requests wlan card + * to pass unencrypted EAPOL-Key frames even when encryption is + * configured. If the wlan card does not require such a configuration, + * this function pointer can be set to NULL. + * + * @set_port_auth: Set port authorization state (IEEE 802.1X PAE) to be + * authorized (@authorized=1) or unauthorized (=0). This function can be + * used if the wlan hardware or low-level driver implements PAE. + * mac80211 will filter frames based on authorization state in any case, + * so this function pointer can be NULL if low-level driver does not + * require event notification about port state changes. + * + * @hw_scan: Ask the hardware to service the scan request, no need to start + * the scan state machine in stack. + * + * @get_stats: return low-level statistics + * + * @set_privacy_invoked: For devices that generate their own beacons and probe + * response or association responses this updates the state of privacy_invoked + * returns 0 for success or an error number. + * + * @get_sequence_counter: For devices that have internal sequence counters this + * callback allows mac80211 to access the current value of a counter. + * This callback seems not well-defined, tell us if you need it. + * + * @set_rts_threshold: Configuration of RTS threshold (if device needs it) + * + * @set_frag_threshold: Configuration of fragmentation threshold. Assign this if + * the device does fragmentation by itself; if this method is assigned then + * the stack will not do fragmentation. + * + * @set_retry_limit: Configuration of retry limits (if device needs it) + * + * @sta_notify: Notifies low level driver about addition or removal + * of assocaited station or AP. + * + * @erp_ie_changed: Handle ERP IE change notifications. Must be atomic. + * + * @conf_tx: Configure TX queue parameters (EDCF (aifs, cw_min, cw_max), + * bursting) for a hardware TX queue. The @queue parameter uses the + * %IEEE80211_TX_QUEUE_* constants. Must be atomic. + * + * @get_tx_stats: Get statistics of the current TX queue status. This is used + * to get number of currently queued packets (queue length), maximum queue + * size (limit), and total number of packets sent using each TX queue + * (count). This information is used for WMM to find out which TX + * queues have room for more packets and by hostapd to provide + * statistics about the current queueing state to external programs. + * + * @get_tsf: Get the current TSF timer value from firmware/hardware. Currently, + * this is only used for IBSS mode debugging and, as such, is not a + * required function. Must be atomic. + * + * @reset_tsf: Reset the TSF timer and allow firmware/hardware to synchronize + * with other STAs in the IBSS. This is only used in IBSS mode. This + * function is optional if the firmware/hardware takes full care of + * TSF synchronization. + * + * @beacon_update: Setup beacon data for IBSS beacons. Unlike access point, + * IBSS uses a fixed beacon frame which is configured using this + * function. + * If the driver returns success (0) from this callback, it owns + * the skb. That means the driver is responsible to kfree_skb() it. + * The control structure is not dynamically allocated. That means the + * driver does not own the pointer and if it needs it somewhere + * outside of the context of this function, it must copy it + * somewhere else. + * This handler is required only for IBSS mode. + * + * @tx_last_beacon: Determine whether the last IBSS beacon was sent by us. + * This is needed only for IBSS mode and the result of this function is + * used to determine whether to reply to Probe Requests. + */ struct ieee80211_ops { - /* Handler that 802.11 module calls for each transmitted frame. - * skb contains the buffer starting from the IEEE 802.11 header. - * The low-level driver should send the frame out based on - * configuration in the TX control data. - * Must be atomic. */ int (*tx)(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_tx_control *control); - - /* Handler for performing hardware reset. */ - int (*reset)(struct ieee80211_hw *hw); - - /* Handler that is called when any netdevice attached to the hardware - * device is set UP for the first time. This can be used, e.g., to - * enable interrupts and beacon sending. */ - int (*open)(struct ieee80211_hw *hw); - - /* Handler that is called when the last netdevice attached to the - * hardware device is set DOWN. This can be used, e.g., to disable - * interrupts and beacon sending. */ - int (*stop)(struct ieee80211_hw *hw); - - /* Handler for asking a driver if a new interface can be added (or, - * more exactly, set UP). If the handler returns zero, the interface - * is added. Driver should perform any initialization it needs prior - * to returning zero. By returning non-zero addition of the interface - * is inhibited. Unless monitor_during_oper is set, it is guaranteed - * that monitor interfaces and normal interfaces are mutually - * exclusive. If assigned, the open() handler is called after - * add_interface() if this is the first device added. The - * add_interface() callback has to be assigned because it is the only - * way to obtain the requested MAC address for any interface. - */ + int (*start)(struct ieee80211_hw *hw); + void (*stop)(struct ieee80211_hw *hw); int (*add_interface)(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf); - - /* Notify a driver that an interface is going down. The stop() handler - * is called prior to this if this is a last interface. */ void (*remove_interface)(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf); - - /* Handler for configuration requests. IEEE 802.11 code calls this - * function to change hardware configuration, e.g., channel. */ int (*config)(struct ieee80211_hw *hw, struct ieee80211_conf *conf); - - /* Handler for configuration requests related to interfaces (e.g. - * BSSID). */ int (*config_interface)(struct ieee80211_hw *hw, int if_id, struct ieee80211_if_conf *conf); - - /* ieee80211 drivers do not have access to the &struct net_device - * that is (are) connected with their device. Hence (and because - * we need to combine the multicast lists and flags for multiple - * virtual interfaces), they cannot assign set_multicast_list. - * The parameters here replace dev->flags and dev->mc_count, - * dev->mc_list is replaced by calling ieee80211_get_mc_list_item. - * Must be atomic. */ - void (*set_multicast_list)(struct ieee80211_hw *hw, - unsigned short flags, int mc_count); - - /* Set TIM bit handler. If the hardware/firmware takes care of beacon - * generation, IEEE 802.11 code uses this function to tell the - * low-level to set (or clear if set==0) TIM bit for the given aid. If - * host system is used to generate beacons, this handler is not used - * and low-level driver should set it to NULL. - * Must be atomic. */ + void (*configure_filter)(struct ieee80211_hw *hw, + unsigned int changed_flags, + unsigned int *total_flags, + int mc_count, struct dev_addr_list *mc_list); int (*set_tim)(struct ieee80211_hw *hw, int aid, int set); - - /* Set encryption key. IEEE 802.11 module calls this function to set - * encryption keys. addr is ff:ff:ff:ff:ff:ff for default keys and - * station hwaddr for individual keys. aid of the station is given - * to help low-level driver in selecting which key->hw_key_idx to use - * for this key. TX control data will use the hw_key_idx selected by - * the low-level driver. - * Must be atomic. */ - int (*set_key)(struct ieee80211_hw *hw, set_key_cmd cmd, - u8 *addr, struct ieee80211_key_conf *key, int aid); - - /* Set TX key index for default/broadcast keys. This is needed in cases - * where wlan card is doing full WEP/TKIP encapsulation (wep_include_iv - * is not set), in other cases, this function pointer can be set to - * NULL since the IEEE 802. 11 module takes care of selecting the key - * index for each TX frame. */ - int (*set_key_idx)(struct ieee80211_hw *hw, int idx); - - /* Enable/disable IEEE 802.1X. This item requests wlan card to pass - * unencrypted EAPOL-Key frames even when encryption is configured. - * If the wlan card does not require such a configuration, this - * function pointer can be set to NULL. */ + int (*set_key)(struct ieee80211_hw *hw, enum set_key_cmd cmd, + const u8 *local_address, const u8 *address, + struct ieee80211_key_conf *key); int (*set_ieee8021x)(struct ieee80211_hw *hw, int use_ieee8021x); - - /* Set port authorization state (IEEE 802.1X PAE) to be authorized - * (authorized=1) or unauthorized (authorized=0). This function can be - * used if the wlan hardware or low-level driver implements PAE. - * 80211.o module will anyway filter frames based on authorization - * state, so this function pointer can be NULL if low-level driver does - * not require event notification about port state changes. - * Currently unused. */ int (*set_port_auth)(struct ieee80211_hw *hw, u8 *addr, int authorized); - - /* Ask the hardware to service the scan request, no need to start - * the scan state machine in stack. */ int (*hw_scan)(struct ieee80211_hw *hw, u8 *ssid, size_t len); - - /* return low-level statistics */ int (*get_stats)(struct ieee80211_hw *hw, struct ieee80211_low_level_stats *stats); - - /* For devices that generate their own beacons and probe response - * or association responses this updates the state of privacy_invoked - * returns 0 for success or an error number */ int (*set_privacy_invoked)(struct ieee80211_hw *hw, int privacy_invoked); - - /* For devices that have internal sequence counters, allow 802.11 - * code to access the current value of a counter */ int (*get_sequence_counter)(struct ieee80211_hw *hw, u8* addr, u8 keyidx, u8 txrx, u32* iv32, u16* iv16); - - /* Configuration of RTS threshold (if device needs it) */ int (*set_rts_threshold)(struct ieee80211_hw *hw, u32 value); - - /* Configuration of fragmentation threshold. - * Assign this if the device does fragmentation by itself, - * if this method is assigned then the stack will not do - * fragmentation. */ int (*set_frag_threshold)(struct ieee80211_hw *hw, u32 value); - - /* Configuration of retry limits (if device needs it) */ int (*set_retry_limit)(struct ieee80211_hw *hw, u32 short_retry, u32 long_retr); - - /* Number of STAs in STA table notification (NULL = disabled). - * Must be atomic. */ - void (*sta_table_notification)(struct ieee80211_hw *hw, - int num_sta); - - /* Configure TX queue parameters (EDCF (aifs, cw_min, cw_max), - * bursting) for a hardware TX queue. - * queue = IEEE80211_TX_QUEUE_*. - * Must be atomic. */ + void (*sta_notify)(struct ieee80211_hw *hw, int if_id, + enum sta_notify_cmd, const u8 *addr); + void (*erp_ie_changed)(struct ieee80211_hw *hw, u8 changes, + int cts_protection, int preamble); int (*conf_tx)(struct ieee80211_hw *hw, int queue, const struct ieee80211_tx_queue_params *params); - - /* Get statistics of the current TX queue status. This is used to get - * number of currently queued packets (queue length), maximum queue - * size (limit), and total number of packets sent using each TX queue - * (count). - * Currently unused. */ int (*get_tx_stats)(struct ieee80211_hw *hw, struct ieee80211_tx_queue_stats *stats); - - /* Get the current TSF timer value from firmware/hardware. Currently, - * this is only used for IBSS mode debugging and, as such, is not a - * required function. - * Must be atomic. */ u64 (*get_tsf)(struct ieee80211_hw *hw); - - /* Reset the TSF timer and allow firmware/hardware to synchronize with - * other STAs in the IBSS. This is only used in IBSS mode. This - * function is optional if the firmware/hardware takes full care of - * TSF synchronization. */ void (*reset_tsf)(struct ieee80211_hw *hw); - - /* Setup beacon data for IBSS beacons. Unlike access point (Master), - * IBSS uses a fixed beacon frame which is configured using this - * function. This handler is required only for IBSS mode. */ int (*beacon_update)(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_tx_control *control); - - /* Determine whether the last IBSS beacon was sent by us. This is - * needed only for IBSS mode and the result of this function is used to - * determine whether to reply to Probe Requests. */ int (*tx_last_beacon)(struct ieee80211_hw *hw); }; -/* Allocate a new hardware device. This must be called once for each - * hardware device. The returned pointer must be used to refer to this - * device when calling other functions. 802.11 code allocates a private data - * area for the low-level driver. The size of this area is given as - * priv_data_len. +/** + * ieee80211_alloc_hw - Allocate a new hardware device + * + * This must be called once for each hardware device. The returned pointer + * must be used to refer to this device when calling other functions. + * mac80211 allocates a private data area for the driver pointed to by + * @priv in &struct ieee80211_hw, the size of this area is given as + * @priv_data_len. + * + * @priv_data_len: length of private data + * @ops: callbacks for this device */ struct ieee80211_hw *ieee80211_alloc_hw(size_t priv_data_len, const struct ieee80211_ops *ops); -/* Register hardware device to the IEEE 802.11 code and kernel. Low-level - * drivers must call this function before using any other IEEE 802.11 - * function except ieee80211_register_hwmode. */ +/** + * ieee80211_register_hw - Register hardware device + * + * You must call this function before any other functions + * except ieee80211_register_hwmode. + * + * @hw: the device to register as returned by ieee80211_alloc_hw() + */ int ieee80211_register_hw(struct ieee80211_hw *hw); -/* driver can use this and ieee80211_get_rx_led_name to get the - * name of the registered LEDs after ieee80211_register_hw - * was called. - * This is useful to set the default trigger on the LED class - * device that your driver should export for each LED the device - * has, that way the default behaviour will be as expected but - * the user can still change it/turn off the LED etc. - */ #ifdef CONFIG_MAC80211_LEDS extern char *__ieee80211_get_tx_led_name(struct ieee80211_hw *hw); extern char *__ieee80211_get_rx_led_name(struct ieee80211_hw *hw); +extern char *__ieee80211_get_assoc_led_name(struct ieee80211_hw *hw); #endif +/** + * ieee80211_get_tx_led_name - get name of TX LED + * + * mac80211 creates a transmit LED trigger for each wireless hardware + * that can be used to drive LEDs if your driver registers a LED device. + * This function returns the name (or %NULL if not configured for LEDs) + * of the trigger so you can automatically link the LED device. + * + * @hw: the hardware to get the LED trigger name for + */ static inline char *ieee80211_get_tx_led_name(struct ieee80211_hw *hw) { #ifdef CONFIG_MAC80211_LEDS @@ -767,6 +1109,16 @@ static inline char *ieee80211_get_tx_led_name(struct ieee80211_hw *hw) #endif } +/** + * ieee80211_get_rx_led_name - get name of RX LED + * + * mac80211 creates a receive LED trigger for each wireless hardware + * that can be used to drive LEDs if your driver registers a LED device. + * This function returns the name (or %NULL if not configured for LEDs) + * of the trigger so you can automatically link the LED device. + * + * @hw: the hardware to get the LED trigger name for + */ static inline char *ieee80211_get_rx_led_name(struct ieee80211_hw *hw) { #ifdef CONFIG_MAC80211_LEDS @@ -776,33 +1128,94 @@ static inline char *ieee80211_get_rx_led_name(struct ieee80211_hw *hw) #endif } +static inline char *ieee80211_get_assoc_led_name(struct ieee80211_hw *hw) +{ +#ifdef CONFIG_MAC80211_LEDS + return __ieee80211_get_assoc_led_name(hw); +#else + return NULL; +#endif +} + + /* Register a new hardware PHYMODE capability to the stack. */ int ieee80211_register_hwmode(struct ieee80211_hw *hw, struct ieee80211_hw_mode *mode); -/* Unregister a hardware device. This function instructs 802.11 code to free - * allocated resources and unregister netdevices from the kernel. */ +/** + * ieee80211_unregister_hw - Unregister a hardware device + * + * This function instructs mac80211 to free allocated resources + * and unregister netdevices from the networking subsystem. + * + * @hw: the hardware to unregister + */ void ieee80211_unregister_hw(struct ieee80211_hw *hw); -/* Free everything that was allocated including private data of a driver. */ +/** + * ieee80211_free_hw - free hardware descriptor + * + * This function frees everything that was allocated, including the + * private data for the driver. You must call ieee80211_unregister_hw() + * before calling this function + * + * @hw: the hardware to free + */ void ieee80211_free_hw(struct ieee80211_hw *hw); -/* Receive frame callback function. The low-level driver uses this function to - * send received frames to the IEEE 802.11 code. Receive buffer (skb) must - * start with IEEE 802.11 header. */ +/* trick to avoid symbol clashes with the ieee80211 subsystem */ void __ieee80211_rx(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_rx_status *status); + +/** + * ieee80211_rx - receive frame + * + * Use this function to hand received frames to mac80211. The receive + * buffer in @skb must start with an IEEE 802.11 header or a radiotap + * header if %RX_FLAG_RADIOTAP is set in the @status flags. + * + * This function may not be called in IRQ context. + * + * @hw: the hardware this frame came in on + * @skb: the buffer to receive, owned by mac80211 after this call + * @status: status of this frame; the status pointer need not be valid + * after this function returns + */ +static inline void ieee80211_rx(struct ieee80211_hw *hw, struct sk_buff *skb, + struct ieee80211_rx_status *status) +{ + __ieee80211_rx(hw, skb, status); +} + +/** + * ieee80211_rx_irqsafe - receive frame + * + * Like ieee80211_rx() but can be called in IRQ context + * (internally defers to a workqueue.) + * + * @hw: the hardware this frame came in on + * @skb: the buffer to receive, owned by mac80211 after this call + * @status: status of this frame; the status pointer need not be valid + * after this function returns and is not freed by mac80211, + * it is recommended that it points to a stack area + */ void ieee80211_rx_irqsafe(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_rx_status *status); -/* Transmit status callback function. The low-level driver must call this - * function to report transmit status for all the TX frames that had - * req_tx_status set in the transmit control fields. In addition, this should - * be called at least for all unicast frames to provide information for TX rate - * control algorithm. In order to maintain all statistics, this function is - * recommended to be called after each frame, including multicast/broadcast, is - * sent. */ +/** + * ieee80211_tx_status - transmit status callback + * + * Call this function for all transmitted frames after they have been + * transmitted. It is permissible to not call this function for + * multicast frames but this can affect statistics. + * + * @hw: the hardware the frame was transmitted by + * @skb: the frame that was transmitted, owned by mac80211 after this call + * @status: status information for this frame; the status pointer need not + * be valid after this function returns and is not freed by mac80211, + * it is recommended that it points to a stack area + */ void ieee80211_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, struct ieee80211_tx_status *status); @@ -830,6 +1243,7 @@ struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw, /** * ieee80211_rts_get - RTS frame generation function * @hw: pointer obtained from ieee80211_alloc_hw(). + * @if_id: interface ID from &struct ieee80211_if_init_conf. * @frame: pointer to the frame that is going to be protected by the RTS. * @frame_len: the frame length (in octets). * @frame_txctl: &struct ieee80211_tx_control of the frame. @@ -840,7 +1254,7 @@ struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw, * the next RTS frame from the 802.11 code. The low-level is responsible * for calling this function before and RTS frame is needed. */ -void ieee80211_rts_get(struct ieee80211_hw *hw, +void ieee80211_rts_get(struct ieee80211_hw *hw, int if_id, const void *frame, size_t frame_len, const struct ieee80211_tx_control *frame_txctl, struct ieee80211_rts *rts); @@ -848,6 +1262,7 @@ void ieee80211_rts_get(struct ieee80211_hw *hw, /** * ieee80211_rts_duration - Get the duration field for an RTS frame * @hw: pointer obtained from ieee80211_alloc_hw(). + * @if_id: interface ID from &struct ieee80211_if_init_conf. * @frame_len: the length of the frame that is going to be protected by the RTS. * @frame_txctl: &struct ieee80211_tx_control of the frame. * @@ -855,13 +1270,14 @@ void ieee80211_rts_get(struct ieee80211_hw *hw, * the duration field, the low-level driver uses this function to receive * the duration field value in little-endian byteorder. */ -__le16 ieee80211_rts_duration(struct ieee80211_hw *hw, +__le16 ieee80211_rts_duration(struct ieee80211_hw *hw, int if_id, size_t frame_len, const struct ieee80211_tx_control *frame_txctl); /** * ieee80211_ctstoself_get - CTS-to-self frame generation function * @hw: pointer obtained from ieee80211_alloc_hw(). + * @if_id: interface ID from &struct ieee80211_if_init_conf. * @frame: pointer to the frame that is going to be protected by the CTS-to-self. * @frame_len: the frame length (in octets). * @frame_txctl: &struct ieee80211_tx_control of the frame. @@ -872,7 +1288,7 @@ __le16 ieee80211_rts_duration(struct ieee80211_hw *hw, * the next CTS-to-self frame from the 802.11 code. The low-level is responsible * for calling this function before and CTS-to-self frame is needed. */ -void ieee80211_ctstoself_get(struct ieee80211_hw *hw, +void ieee80211_ctstoself_get(struct ieee80211_hw *hw, int if_id, const void *frame, size_t frame_len, const struct ieee80211_tx_control *frame_txctl, struct ieee80211_cts *cts); @@ -880,6 +1296,7 @@ void ieee80211_ctstoself_get(struct ieee80211_hw *hw, /** * ieee80211_ctstoself_duration - Get the duration field for a CTS-to-self frame * @hw: pointer obtained from ieee80211_alloc_hw(). + * @if_id: interface ID from &struct ieee80211_if_init_conf. * @frame_len: the length of the frame that is going to be protected by the CTS-to-self. * @frame_txctl: &struct ieee80211_tx_control of the frame. * @@ -887,20 +1304,21 @@ void ieee80211_ctstoself_get(struct ieee80211_hw *hw, * the duration field, the low-level driver uses this function to receive * the duration field value in little-endian byteorder. */ -__le16 ieee80211_ctstoself_duration(struct ieee80211_hw *hw, +__le16 ieee80211_ctstoself_duration(struct ieee80211_hw *hw, int if_id, size_t frame_len, const struct ieee80211_tx_control *frame_txctl); /** * ieee80211_generic_frame_duration - Calculate the duration field for a frame * @hw: pointer obtained from ieee80211_alloc_hw(). + * @if_id: interface ID from &struct ieee80211_if_init_conf. * @frame_len: the length of the frame. * @rate: the rate (in 100kbps) at which the frame is going to be transmitted. * * Calculate the duration field of some generic frame, given its * length and transmission rate (in 100kbps). */ -__le16 ieee80211_generic_frame_duration(struct ieee80211_hw *hw, +__le16 ieee80211_generic_frame_duration(struct ieee80211_hw *hw, int if_id, size_t frame_len, int rate); @@ -929,14 +1347,26 @@ struct sk_buff * ieee80211_get_buffered_bc(struct ieee80211_hw *hw, int if_id, struct ieee80211_tx_control *control); -/* Given an sk_buff with a raw 802.11 header at the data pointer this function +/** + * ieee80211_get_hdrlen_from_skb - get header length from data + * + * Given an skb with a raw 802.11 header at the data pointer this function * returns the 802.11 header length in bytes (not including encryption * headers). If the data in the sk_buff is too short to contain a valid 802.11 * header the function returns 0. + * + * @skb: the frame */ int ieee80211_get_hdrlen_from_skb(const struct sk_buff *skb); -/* Like ieee80211_get_hdrlen_from_skb() but takes a FC in CPU order. */ +/** + * ieee80211_get_hdrlen - get header length from frame control + * + * This function returns the 802.11 header length in bytes (not including + * encryption headers.) + * + * @fc: the frame control field (in CPU endianness) + */ int ieee80211_get_hdrlen(u16 fc); /** @@ -982,66 +1412,14 @@ void ieee80211_stop_queues(struct ieee80211_hw *hw); void ieee80211_wake_queues(struct ieee80211_hw *hw); /** - * ieee80211_get_mc_list_item - iteration over items in multicast list - * @hw: pointer as obtained from ieee80211_alloc_hw(). - * @prev: value returned by previous call to ieee80211_get_mc_list_item() or - * NULL to start a new iteration. - * @ptr: pointer to buffer of void * type for internal usage of - * ieee80211_get_mc_list_item(). - * - * Iterates over items in multicast list of given device. To get the first - * item, pass NULL in @prev and in *@ptr. In subsequent calls, pass the - * value returned by previous call in @prev. Don't alter *@ptr during - * iteration. When there are no more items, NULL is returned. + * ieee80211_scan_completed - completed hardware scan + * + * When hardware scan offload is used (i.e. the hw_scan() callback is + * assigned) this function needs to be called by the driver to notify + * mac80211 that the scan finished. + * + * @hw: the hardware that finished the scan */ -struct dev_mc_list * -ieee80211_get_mc_list_item(struct ieee80211_hw *hw, - struct dev_mc_list *prev, - void **ptr); - -/* called by driver to notify scan status completed */ void ieee80211_scan_completed(struct ieee80211_hw *hw); -/* Function to indicate Radar Detection. The low level driver must call this - * function to indicate the presence of radar in the current channel. - * Additionally the radar type also could be sent */ -int ieee80211_radar_status(struct ieee80211_hw *hw, int channel, - int radar, int radar_type); - -/* return a pointer to the source address (SA) */ -static inline u8 *ieee80211_get_SA(struct ieee80211_hdr *hdr) -{ - u8 *raw = (u8 *) hdr; - u8 tofrom = (*(raw+1)) & 3; /* get the TODS and FROMDS bits */ - - switch (tofrom) { - case 2: - return hdr->addr3; - case 3: - return hdr->addr4; - } - return hdr->addr2; -} - -/* return a pointer to the destination address (DA) */ -static inline u8 *ieee80211_get_DA(struct ieee80211_hdr *hdr) -{ - u8 *raw = (u8 *) hdr; - u8 to_ds = (*(raw+1)) & 1; /* get the TODS bit */ - - if (to_ds) - return hdr->addr3; - return hdr->addr1; -} - -static inline int ieee80211_get_morefrag(struct ieee80211_hdr *hdr) -{ - return (le16_to_cpu(hdr->frame_control) & - IEEE80211_FCTL_MOREFRAGS) != 0; -} - -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0], ((u8*)(x))[1], ((u8*)(x))[2], \ - ((u8*)(x))[3], ((u8*)(x))[4], ((u8*)(x))[5] - #endif /* MAC80211_H */ diff --git a/include/net/ndisc.h b/include/net/ndisc.h index 475b10c575b3..6684f7efbeeb 100644 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h @@ -24,6 +24,7 @@ enum { ND_OPT_MTU = 5, /* RFC2461 */ __ND_OPT_ARRAY_MAX, ND_OPT_ROUTE_INFO = 24, /* RFC4191 */ + ND_OPT_RDNSS = 25, /* RFC5006 */ __ND_OPT_MAX }; diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h new file mode 100644 index 000000000000..93aa87d32804 --- /dev/null +++ b/include/net/net_namespace.h @@ -0,0 +1,123 @@ +/* + * Operations on the network namespace + */ +#ifndef __NET_NET_NAMESPACE_H +#define __NET_NET_NAMESPACE_H + +#include <asm/atomic.h> +#include <linux/workqueue.h> +#include <linux/list.h> + +struct proc_dir_entry; +struct net_device; +struct net { + atomic_t count; /* To decided when the network + * namespace should be freed. + */ + atomic_t use_count; /* To track references we + * destroy on demand + */ + struct list_head list; /* list of network namespaces */ + struct work_struct work; /* work struct for freeing */ + + struct proc_dir_entry *proc_net; + struct proc_dir_entry *proc_net_stat; + struct proc_dir_entry *proc_net_root; + + struct net_device *loopback_dev; /* The loopback */ + + struct list_head dev_base_head; + struct hlist_head *dev_name_head; + struct hlist_head *dev_index_head; +}; + +#ifdef CONFIG_NET +/* Init's network namespace */ +extern struct net init_net; +#define INIT_NET_NS(net_ns) .net_ns = &init_net, +#else +#define INIT_NET_NS(net_ns) +#endif + +extern struct list_head net_namespace_list; + +#ifdef CONFIG_NET +extern struct net *copy_net_ns(unsigned long flags, struct net *net_ns); +#else +static inline struct net *copy_net_ns(unsigned long flags, struct net *net_ns) +{ + /* There is nothing to copy so this is a noop */ + return net_ns; +} +#endif + +extern void __put_net(struct net *net); + +static inline struct net *get_net(struct net *net) +{ +#ifdef CONFIG_NET + atomic_inc(&net->count); +#endif + return net; +} + +static inline struct net *maybe_get_net(struct net *net) +{ + /* Used when we know struct net exists but we + * aren't guaranteed a previous reference count + * exists. If the reference count is zero this + * function fails and returns NULL. + */ + if (!atomic_inc_not_zero(&net->count)) + net = NULL; + return net; +} + +static inline void put_net(struct net *net) +{ +#ifdef CONFIG_NET + if (atomic_dec_and_test(&net->count)) + __put_net(net); +#endif +} + +static inline struct net *hold_net(struct net *net) +{ +#ifdef CONFIG_NET + atomic_inc(&net->use_count); +#endif + return net; +} + +static inline void release_net(struct net *net) +{ +#ifdef CONFIG_NET + atomic_dec(&net->use_count); +#endif +} + +#define for_each_net(VAR) \ + list_for_each_entry(VAR, &net_namespace_list, list) + +#ifdef CONFIG_NET_NS +#define __net_init +#define __net_exit +#define __net_initdata +#else +#define __net_init __init +#define __net_exit __exit_refok +#define __net_initdata __initdata +#endif + +struct pernet_operations { + struct list_head list; + int (*init)(struct net *net); + void (*exit)(struct net *net); +}; + +extern int register_pernet_subsys(struct pernet_operations *); +extern void unregister_pernet_subsys(struct pernet_operations *); +extern int register_pernet_device(struct pernet_operations *); +extern void unregister_pernet_device(struct pernet_operations *); + +#endif /* __NET_NET_NAMESPACE_H */ diff --git a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h index 7a671603fca6..9bf059817aec 100644 --- a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h +++ b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h @@ -21,4 +21,6 @@ extern struct nf_conntrack_l4proto nf_conntrack_l4proto_icmp; extern int nf_conntrack_ipv4_compat_init(void); extern void nf_conntrack_ipv4_compat_fini(void); +extern void need_ipv4_conntrack(void); + #endif /*_NF_CONNTRACK_IPV4_H*/ diff --git a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h index 5a8965904377..070d12cb4634 100644 --- a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h +++ b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h @@ -7,9 +7,6 @@ extern struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_udp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_icmpv6; -extern int nf_ct_ipv6_skip_exthdr(const struct sk_buff *skb, int start, - u8 *nexthdrp, int len); - extern int nf_ct_frag6_init(void); extern void nf_ct_frag6_cleanup(void); extern struct sk_buff *nf_ct_frag6_gather(struct sk_buff *skb); diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h index 810020ec345d..90fb66d99d0c 100644 --- a/include/net/netfilter/nf_conntrack.h +++ b/include/net/netfilter/nf_conntrack.h @@ -116,9 +116,6 @@ struct nf_conn struct ip_conntrack_counter counters[IP_CT_DIR_MAX]; #endif - /* Unique ID that identifies this conntrack*/ - unsigned int id; - #if defined(CONFIG_NF_CONNTRACK_MARK) u_int32_t mark; #endif diff --git a/include/net/netfilter/nf_conntrack_expect.h b/include/net/netfilter/nf_conntrack_expect.h index cae1a0dce365..b47c04f12dbe 100644 --- a/include/net/netfilter/nf_conntrack_expect.h +++ b/include/net/netfilter/nf_conntrack_expect.h @@ -38,9 +38,6 @@ struct nf_conntrack_expect /* Usage count. */ atomic_t use; - /* Unique ID */ - unsigned int id; - /* Flags */ unsigned int flags; diff --git a/include/net/netfilter/nf_conntrack_helper.h b/include/net/netfilter/nf_conntrack_helper.h index d04f99964d94..0dcc4c828ce9 100644 --- a/include/net/netfilter/nf_conntrack_helper.h +++ b/include/net/netfilter/nf_conntrack_helper.h @@ -36,7 +36,7 @@ struct nf_conntrack_helper void (*destroy)(struct nf_conn *ct); - int (*to_nfattr)(struct sk_buff *skb, const struct nf_conn *ct); + int (*to_nlattr)(struct sk_buff *skb, const struct nf_conn *ct); }; extern struct nf_conntrack_helper * diff --git a/include/net/netfilter/nf_conntrack_l3proto.h b/include/net/netfilter/nf_conntrack_l3proto.h index 3c58a2c4df28..15888fc7b72d 100644 --- a/include/net/netfilter/nf_conntrack_l3proto.h +++ b/include/net/netfilter/nf_conntrack_l3proto.h @@ -11,11 +11,11 @@ #ifndef _NF_CONNTRACK_L3PROTO_H #define _NF_CONNTRACK_L3PROTO_H +#include <linux/netlink.h> +#include <net/netlink.h> #include <linux/seq_file.h> #include <net/netfilter/nf_conntrack.h> -struct nfattr; - struct nf_conntrack_l3proto { /* L3 Protocol Family number. ex) PF_INET */ @@ -64,11 +64,12 @@ struct nf_conntrack_l3proto int (*get_l4proto)(const struct sk_buff *skb, unsigned int nhoff, unsigned int *dataoff, u_int8_t *protonum); - int (*tuple_to_nfattr)(struct sk_buff *skb, + int (*tuple_to_nlattr)(struct sk_buff *skb, const struct nf_conntrack_tuple *t); - int (*nfattr_to_tuple)(struct nfattr *tb[], + int (*nlattr_to_tuple)(struct nlattr *tb[], struct nf_conntrack_tuple *t); + const struct nla_policy *nla_policy; #ifdef CONFIG_SYSCTL struct ctl_table_header *ctl_table_header; diff --git a/include/net/netfilter/nf_conntrack_l4proto.h b/include/net/netfilter/nf_conntrack_l4proto.h index f46cb930414c..fb50c217ba0a 100644 --- a/include/net/netfilter/nf_conntrack_l4proto.h +++ b/include/net/netfilter/nf_conntrack_l4proto.h @@ -9,10 +9,11 @@ #ifndef _NF_CONNTRACK_L4PROTO_H #define _NF_CONNTRACK_L4PROTO_H +#include <linux/netlink.h> +#include <net/netlink.h> #include <net/netfilter/nf_conntrack.h> struct seq_file; -struct nfattr; struct nf_conntrack_l4proto { @@ -65,16 +66,17 @@ struct nf_conntrack_l4proto int pf, unsigned int hooknum); /* convert protoinfo to nfnetink attributes */ - int (*to_nfattr)(struct sk_buff *skb, struct nfattr *nfa, + int (*to_nlattr)(struct sk_buff *skb, struct nlattr *nla, const struct nf_conn *ct); /* convert nfnetlink attributes to protoinfo */ - int (*from_nfattr)(struct nfattr *tb[], struct nf_conn *ct); + int (*from_nlattr)(struct nlattr *tb[], struct nf_conn *ct); - int (*tuple_to_nfattr)(struct sk_buff *skb, + int (*tuple_to_nlattr)(struct sk_buff *skb, const struct nf_conntrack_tuple *t); - int (*nfattr_to_tuple)(struct nfattr *tb[], + int (*nlattr_to_tuple)(struct nlattr *tb[], struct nf_conntrack_tuple *t); + const struct nla_policy *nla_policy; #ifdef CONFIG_SYSCTL struct ctl_table_header **ctl_table_header; @@ -111,10 +113,11 @@ extern int nf_conntrack_l4proto_register(struct nf_conntrack_l4proto *proto); extern void nf_conntrack_l4proto_unregister(struct nf_conntrack_l4proto *proto); /* Generic netlink helpers */ -extern int nf_ct_port_tuple_to_nfattr(struct sk_buff *skb, +extern int nf_ct_port_tuple_to_nlattr(struct sk_buff *skb, const struct nf_conntrack_tuple *tuple); -extern int nf_ct_port_nfattr_to_tuple(struct nfattr *tb[], +extern int nf_ct_port_nlattr_to_tuple(struct nlattr *tb[], struct nf_conntrack_tuple *t); +extern const struct nla_policy nf_ct_port_nla_policy[]; /* Log invalid packets */ extern unsigned int nf_ct_log_invalid; diff --git a/include/net/netfilter/nf_conntrack_tuple.h b/include/net/netfilter/nf_conntrack_tuple.h index 040dae5f0c9e..c48e390f4b0f 100644 --- a/include/net/netfilter/nf_conntrack_tuple.h +++ b/include/net/netfilter/nf_conntrack_tuple.h @@ -35,7 +35,7 @@ union nf_conntrack_address { union nf_conntrack_man_proto { /* Add other protocols here. */ - u_int16_t all; + __be16 all; struct { __be16 port; @@ -73,7 +73,7 @@ struct nf_conntrack_tuple union nf_conntrack_address u3; union { /* Add other protocols here. */ - u_int16_t all; + __be16 all; struct { __be16 port; diff --git a/include/net/netfilter/nf_nat_protocol.h b/include/net/netfilter/nf_nat_protocol.h index a9ec5ef61468..14c7b2d7263c 100644 --- a/include/net/netfilter/nf_nat_protocol.h +++ b/include/net/netfilter/nf_nat_protocol.h @@ -38,10 +38,10 @@ struct nf_nat_protocol enum nf_nat_manip_type maniptype, const struct nf_conn *ct); - int (*range_to_nfattr)(struct sk_buff *skb, + int (*range_to_nlattr)(struct sk_buff *skb, const struct nf_nat_range *range); - int (*nfattr_to_range)(struct nfattr *tb[], + int (*nlattr_to_range)(struct nlattr *tb[], struct nf_nat_range *range); }; @@ -62,9 +62,9 @@ extern int init_protocols(void) __init; extern void cleanup_protocols(void); extern struct nf_nat_protocol *find_nat_proto(u_int16_t protonum); -extern int nf_nat_port_range_to_nfattr(struct sk_buff *skb, +extern int nf_nat_port_range_to_nlattr(struct sk_buff *skb, const struct nf_nat_range *range); -extern int nf_nat_port_nfattr_to_range(struct nfattr *tb[], +extern int nf_nat_port_nlattr_to_range(struct nlattr *tb[], struct nf_nat_range *range); #endif /*_NF_NAT_PROTO_H*/ diff --git a/include/net/netlabel.h b/include/net/netlabel.h index 9b7d6f2ac9a3..2e5b2f6f9fa0 100644 --- a/include/net/netlabel.h +++ b/include/net/netlabel.h @@ -132,6 +132,8 @@ struct netlbl_lsm_secattr_catmap { #define NETLBL_SECATTR_CACHE 0x00000002 #define NETLBL_SECATTR_MLS_LVL 0x00000004 #define NETLBL_SECATTR_MLS_CAT 0x00000008 +#define NETLBL_SECATTR_CACHEABLE (NETLBL_SECATTR_MLS_LVL | \ + NETLBL_SECATTR_MLS_CAT) struct netlbl_lsm_secattr { u32 flags; @@ -144,10 +146,9 @@ struct netlbl_lsm_secattr { }; /* - * LSM security attribute operations + * LSM security attribute operations (inline) */ - /** * netlbl_secattr_cache_alloc - Allocate and initialize a secattr cache * @flags: the memory allocation flags @@ -283,6 +284,9 @@ static inline void netlbl_secattr_free(struct netlbl_lsm_secattr *secattr) } #ifdef CONFIG_NETLABEL +/* + * LSM security attribute operations + */ int netlbl_secattr_catmap_walk(struct netlbl_lsm_secattr_catmap *catmap, u32 offset); int netlbl_secattr_catmap_walk_rng(struct netlbl_lsm_secattr_catmap *catmap, @@ -294,6 +298,25 @@ int netlbl_secattr_catmap_setrng(struct netlbl_lsm_secattr_catmap *catmap, u32 start, u32 end, gfp_t flags); + +/* + * LSM protocol operations + */ +int netlbl_enabled(void); +int netlbl_sock_setattr(struct sock *sk, + const struct netlbl_lsm_secattr *secattr); +int netlbl_sock_getattr(struct sock *sk, + struct netlbl_lsm_secattr *secattr); +int netlbl_skbuff_getattr(const struct sk_buff *skb, + struct netlbl_lsm_secattr *secattr); +void netlbl_skbuff_err(struct sk_buff *skb, int error); + +/* + * LSM label mapping cache operations + */ +void netlbl_cache_invalidate(void); +int netlbl_cache_add(const struct sk_buff *skb, + const struct netlbl_lsm_secattr *secattr); #else static inline int netlbl_secattr_catmap_walk( struct netlbl_lsm_secattr_catmap *catmap, @@ -301,14 +324,12 @@ static inline int netlbl_secattr_catmap_walk( { return -ENOENT; } - static inline int netlbl_secattr_catmap_walk_rng( struct netlbl_lsm_secattr_catmap *catmap, u32 offset) { return -ENOENT; } - static inline int netlbl_secattr_catmap_setbit( struct netlbl_lsm_secattr_catmap *catmap, u32 bit, @@ -316,7 +337,6 @@ static inline int netlbl_secattr_catmap_setbit( { return 0; } - static inline int netlbl_secattr_catmap_setrng( struct netlbl_lsm_secattr_catmap *catmap, u32 start, @@ -325,59 +345,33 @@ static inline int netlbl_secattr_catmap_setrng( { return 0; } -#endif - -/* - * LSM protocol operations - */ - -#ifdef CONFIG_NETLABEL -int netlbl_sock_setattr(struct sock *sk, - const struct netlbl_lsm_secattr *secattr); -int netlbl_sock_getattr(struct sock *sk, - struct netlbl_lsm_secattr *secattr); -int netlbl_skbuff_getattr(const struct sk_buff *skb, - struct netlbl_lsm_secattr *secattr); -void netlbl_skbuff_err(struct sk_buff *skb, int error); -#else +static inline int netlbl_enabled(void) +{ + return 0; +} static inline int netlbl_sock_setattr(struct sock *sk, const struct netlbl_lsm_secattr *secattr) { return -ENOSYS; } - static inline int netlbl_sock_getattr(struct sock *sk, struct netlbl_lsm_secattr *secattr) { return -ENOSYS; } - static inline int netlbl_skbuff_getattr(const struct sk_buff *skb, struct netlbl_lsm_secattr *secattr) { return -ENOSYS; } - static inline void netlbl_skbuff_err(struct sk_buff *skb, int error) { return; } -#endif /* CONFIG_NETLABEL */ - -/* - * LSM label mapping cache operations - */ - -#ifdef CONFIG_NETLABEL -void netlbl_cache_invalidate(void); -int netlbl_cache_add(const struct sk_buff *skb, - const struct netlbl_lsm_secattr *secattr); -#else static inline void netlbl_cache_invalidate(void) { return; } - static inline int netlbl_cache_add(const struct sk_buff *skb, const struct netlbl_lsm_secattr *secattr) { diff --git a/include/net/netlink.h b/include/net/netlink.h index d7b824be5422..9298218c07f9 100644 --- a/include/net/netlink.h +++ b/include/net/netlink.h @@ -84,7 +84,7 @@ * nla_next(nla)-----------------------------' * * Data Structures: - * struct nlattr netlink attribtue header + * struct nlattr netlink attribute header * * Attribute Construction: * nla_reserve(skb, type, len) reserve room for an attribute @@ -220,9 +220,9 @@ struct nl_info { u32 pid; }; -extern void netlink_run_queue(struct sock *sk, unsigned int *qlen, - int (*cb)(struct sk_buff *, - struct nlmsghdr *)); +extern int netlink_rcv_skb(struct sk_buff *skb, + int (*cb)(struct sk_buff *, + struct nlmsghdr *)); extern int nlmsg_notify(struct sock *sk, struct sk_buff *skb, u32 pid, unsigned int group, int report, gfp_t flags); @@ -667,6 +667,15 @@ static inline int nla_padlen(int payload) } /** + * nla_type - attribute type + * @nla: netlink attribute + */ +static inline int nla_type(const struct nlattr *nla) +{ + return nla->nla_type & NLA_TYPE_MASK; +} + +/** * nla_data - head of payload * @nla: netlink attribute */ @@ -697,7 +706,7 @@ static inline int nla_ok(const struct nlattr *nla, int remaining) } /** - * nla_next - next netlink attribte in attribute stream + * nla_next - next netlink attribute in attribute stream * @nla: netlink attribute * @remaining: number of bytes remaining in attribute stream * @@ -773,7 +782,7 @@ static inline int __nla_parse_nested_compat(struct nlattr *tb[], int maxtype, ({ data = nla_len(nla) >= len ? nla_data(nla) : NULL; \ __nla_parse_nested_compat(tb, maxtype, nla, policy, len); }) /** - * nla_put_u8 - Add a u16 netlink attribute to a socket buffer + * nla_put_u8 - Add a u8 netlink attribute to a socket buffer * @skb: socket buffer to add attribute to * @attrtype: attribute type * @value: numeric value @@ -989,7 +998,7 @@ static inline struct nlattr *nla_nest_start(struct sk_buff *skb, int attrtype) /** * nla_nest_end - Finalize nesting of attributes - * @skb: socket buffer the attribtues are stored in + * @skb: socket buffer the attributes are stored in * @start: container attribute * * Corrects the container attribute header to include the all @@ -1032,7 +1041,7 @@ static inline struct nlattr *nla_nest_compat_start(struct sk_buff *skb, /** * nla_nest_compat_end - Finalize nesting of compat attributes - * @skb: socket buffer the attribtues are stored in + * @skb: socket buffer the attributes are stored in * @start: container attribute * * Corrects the container attribute header to include the all diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h index 7968b1d66369..f285de69c615 100644 --- a/include/net/pkt_cls.h +++ b/include/net/pkt_cls.h @@ -2,6 +2,7 @@ #define __NET_PKT_CLS_H #include <linux/pkt_cls.h> +#include <net/net_namespace.h> #include <net/sch_generic.h> #include <net/act_api.h> @@ -351,7 +352,7 @@ tcf_match_indev(struct sk_buff *skb, char *indev) if (indev[0]) { if (!skb->iif) return 0; - dev = __dev_get_by_index(skb->iif); + dev = __dev_get_by_index(&init_net, skb->iif); if (!dev || strcmp(indev, dev->name)) return 0; } diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 9e22526e80e7..ab61809a9616 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -97,10 +97,9 @@ extern int tc_classify(struct sk_buff *skb, struct tcf_proto *tp, /* Calculate maximal size of packet seen by hard_start_xmit routine of this device. */ -static inline unsigned psched_mtu(struct net_device *dev) +static inline unsigned psched_mtu(const struct net_device *dev) { - unsigned mtu = dev->mtu; - return dev->hard_header ? mtu + dev->hard_header_len : mtu; + return dev->mtu + dev->hard_header_len; } #endif diff --git a/include/net/rose.h b/include/net/rose.h index a4047d3cf5dd..e5bb084d8754 100644 --- a/include/net/rose.h +++ b/include/net/rose.h @@ -188,7 +188,7 @@ extern void rose_kick(struct sock *); extern void rose_enquiry_response(struct sock *); /* rose_route.c */ -extern struct rose_neigh rose_loopback_neigh; +extern struct rose_neigh *rose_loopback_neigh; extern const struct file_operations rose_neigh_fops; extern const struct file_operations rose_nodes_fops; extern const struct file_operations rose_routes_fops; diff --git a/include/net/rtnetlink.h b/include/net/rtnetlink.h index 3861c05cdf0f..793863e09c69 100644 --- a/include/net/rtnetlink.h +++ b/include/net/rtnetlink.h @@ -78,6 +78,10 @@ extern void __rtnl_link_unregister(struct rtnl_link_ops *ops); extern int rtnl_link_register(struct rtnl_link_ops *ops); extern void rtnl_link_unregister(struct rtnl_link_ops *ops); +extern struct net_device *rtnl_create_link(struct net *net, char *ifname, + const struct rtnl_link_ops *ops, struct nlattr *tb[]); +extern const struct nla_policy ifla_policy[IFLA_MAX+1]; + #define MODULE_ALIAS_RTNL_LINK(kind) MODULE_ALIAS("rtnl-link-" kind) #endif diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 8a67f24cbe02..a02ec9e5fea5 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -302,4 +302,18 @@ drop: return NET_XMIT_DROP; } +/* Length to Time (L2T) lookup in a qdisc_rate_table, to determine how + long it will take to send a packet given its size. + */ +static inline u32 qdisc_l2t(struct qdisc_rate_table* rtab, unsigned int pktlen) +{ + int slot = pktlen + rtab->rate.cell_align + rtab->rate.overhead; + if (slot < 0) + slot = 0; + slot >>= rtab->rate.cell_log; + if (slot > 255) + return (rtab->data[255]*(slot >> 8) + rtab->data[slot & 0xFF]); + return rtab->data[slot]; +} + #endif diff --git a/include/net/sctp/auth.h b/include/net/sctp/auth.h new file mode 100644 index 000000000000..4945954a16af --- /dev/null +++ b/include/net/sctp/auth.h @@ -0,0 +1,128 @@ +/* SCTP kernel reference Implementation + * (C) Copyright 2007 Hewlett-Packard Development Company, L.P. + * + * This file is part of the SCTP kernel reference Implementation + * + * The SCTP reference implementation is free software; + * you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * The SCTP reference implementation is distributed in the hope that it + * will be useful, but WITHOUT ANY WARRANTY; without even the implied + * ************************ + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU CC; see the file COPYING. If not, write to + * the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + * Please send any bug reports or fixes you make to the + * email address(es): + * lksctp developers <lksctp-developers@lists.sourceforge.net> + * + * Or submit a bug report through the following website: + * http://www.sf.net/projects/lksctp + * + * Written or modified by: + * Vlad Yasevich <vladislav.yasevich@hp.com> + * + * Any bugs reported given to us we will try to fix... any fixes shared will + * be incorporated into the next SCTP release. + */ + +#ifndef __sctp_auth_h__ +#define __sctp_auth_h__ + +#include <linux/list.h> +#include <linux/crypto.h> + +struct sctp_endpoint; +struct sctp_association; +struct sctp_authkey; +struct sctp_hmacalgo; + +/* + * Define a generic struct that will hold all the info + * necessary for an HMAC transform + */ +struct sctp_hmac { + __u16 hmac_id; /* one of the above ids */ + char *hmac_name; /* name for loading */ + __u16 hmac_len; /* length of the signature */ +}; + +/* This is generic structure that containst authentication bytes used + * as keying material. It's a what is referred to as byte-vector all + * over SCTP-AUTH + */ +struct sctp_auth_bytes { + atomic_t refcnt; + __u32 len; + __u8 data[]; +}; + +/* Definition for a shared key, weather endpoint or association */ +struct sctp_shared_key { + struct list_head key_list; + __u16 key_id; + struct sctp_auth_bytes *key; +}; + +#define key_for_each(__key, __list_head) \ + list_for_each_entry(__key, __list_head, key_list) + +#define key_for_each_safe(__key, __tmp, __list_head) \ + list_for_each_entry_safe(__key, __tmp, __list_head, key_list) + +static inline void sctp_auth_key_hold(struct sctp_auth_bytes *key) +{ + if (!key) + return; + + atomic_inc(&key->refcnt); +} + +void sctp_auth_key_put(struct sctp_auth_bytes *key); +struct sctp_shared_key *sctp_auth_shkey_create(__u16 key_id, gfp_t gfp); +void sctp_auth_shkey_free(struct sctp_shared_key *sh_key); +void sctp_auth_destroy_keys(struct list_head *keys); +int sctp_auth_asoc_init_active_key(struct sctp_association *asoc, gfp_t gfp); +struct sctp_shared_key *sctp_auth_get_shkey( + const struct sctp_association *asoc, + __u16 key_id); +int sctp_auth_asoc_copy_shkeys(const struct sctp_endpoint *ep, + struct sctp_association *asoc, + gfp_t gfp); +int sctp_auth_init_hmacs(struct sctp_endpoint *ep, gfp_t gfp); +void sctp_auth_destroy_hmacs(struct crypto_hash *auth_hmacs[]); +struct sctp_hmac *sctp_auth_get_hmac(__u16 hmac_id); +struct sctp_hmac *sctp_auth_asoc_get_hmac(const struct sctp_association *asoc); +void sctp_auth_asoc_set_default_hmac(struct sctp_association *asoc, + struct sctp_hmac_algo_param *hmacs); +int sctp_auth_asoc_verify_hmac_id(const struct sctp_association *asoc, + __u16 hmac_id); +int sctp_auth_send_cid(sctp_cid_t chunk, const struct sctp_association *asoc); +int sctp_auth_recv_cid(sctp_cid_t chunk, const struct sctp_association *asoc); +void sctp_auth_calculate_hmac(const struct sctp_association *asoc, + struct sk_buff *skb, + struct sctp_auth_chunk *auth, gfp_t gfp); + +/* API Helpers */ +int sctp_auth_ep_add_chunkid(struct sctp_endpoint *ep, __u8 chunk_id); +int sctp_auth_ep_set_hmacs(struct sctp_endpoint *ep, + struct sctp_hmacalgo *hmacs); +int sctp_auth_set_key(struct sctp_endpoint *ep, + struct sctp_association *asoc, + struct sctp_authkey *auth_key); +int sctp_auth_set_active_key(struct sctp_endpoint *ep, + struct sctp_association *asoc, + __u16 key_id); +int sctp_auth_del_key_id(struct sctp_endpoint *ep, + struct sctp_association *asoc, + __u16 key_id); + +#endif diff --git a/include/net/sctp/command.h b/include/net/sctp/command.h index f56c8d695a82..b8733364557f 100644 --- a/include/net/sctp/command.h +++ b/include/net/sctp/command.h @@ -102,6 +102,7 @@ typedef enum { SCTP_CMD_SET_SK_ERR, /* Set sk_err */ SCTP_CMD_ASSOC_CHANGE, /* generate and send assoc_change event */ SCTP_CMD_ADAPTATION_IND, /* generate and send adaptation event */ + SCTP_CMD_ASSOC_SHKEY, /* generate the association shared keys */ SCTP_CMD_LAST } sctp_verb_t; diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h index bb37724495a5..da8354e8e33c 100644 --- a/include/net/sctp/constants.h +++ b/include/net/sctp/constants.h @@ -64,12 +64,18 @@ enum { SCTP_DEFAULT_INSTREAMS = SCTP_MAX_STREAM }; #define SCTP_CID_MAX SCTP_CID_ASCONF_ACK #define SCTP_NUM_BASE_CHUNK_TYPES (SCTP_CID_BASE_MAX + 1) -#define SCTP_NUM_CHUNK_TYPES (SCTP_NUM_BASE_CHUNKTYPES + 2) #define SCTP_NUM_ADDIP_CHUNK_TYPES 2 #define SCTP_NUM_PRSCTP_CHUNK_TYPES 1 +#define SCTP_NUM_AUTH_CHUNK_TYPES 1 + +#define SCTP_NUM_CHUNK_TYPES (SCTP_NUM_BASE_CHUNK_TYPES + \ + SCTP_NUM_ADDIP_CHUNK_TYPES +\ + SCTP_NUM_PRSCTP_CHUNK_TYPES +\ + SCTP_NUM_AUTH_CHUNK_TYPES) + /* These are the different flavours of event. */ typedef enum { @@ -177,7 +183,9 @@ typedef enum { SCTP_IERROR_NO_DATA, SCTP_IERROR_BAD_STREAM, SCTP_IERROR_BAD_PORTS, - + SCTP_IERROR_AUTH_BAD_HMAC, + SCTP_IERROR_AUTH_BAD_KEYID, + SCTP_IERROR_PROTO_VIOLATION, } sctp_ierror_t; @@ -409,4 +417,45 @@ typedef enum { SCTP_LOWER_CWND_INACTIVE, } sctp_lower_cwnd_t; + +/* SCTP-AUTH Necessary constants */ + +/* SCTP-AUTH, Section 3.3 + * + * The following Table 2 shows the currently defined values for HMAC + * identifiers. + * + * +-----------------+--------------------------+ + * | HMAC Identifier | Message Digest Algorithm | + * +-----------------+--------------------------+ + * | 0 | Reserved | + * | 1 | SHA-1 defined in [8] | + * | 2 | Reserved | + * | 3 | SHA-256 defined in [8] | + * +-----------------+--------------------------+ + */ +enum { + SCTP_AUTH_HMAC_ID_RESERVED_0, + SCTP_AUTH_HMAC_ID_SHA1, + SCTP_AUTH_HMAC_ID_RESERVED_2, + SCTP_AUTH_HMAC_ID_SHA256 +}; + +#define SCTP_AUTH_HMAC_ID_MAX SCTP_AUTH_HMAC_ID_SHA256 +#define SCTP_AUTH_NUM_HMACS (SCTP_AUTH_HMAC_ID_SHA256 + 1) +#define SCTP_SHA1_SIG_SIZE 20 +#define SCTP_SHA256_SIG_SIZE 32 + +/* SCTP-AUTH, Section 3.2 + * The chunk types for INIT, INIT-ACK, SHUTDOWN-COMPLETE and AUTH chunks + * MUST NOT be listed in the CHUNKS parameter + */ +#define SCTP_NUM_NOAUTH_CHUNKS 4 +#define SCTP_AUTH_MAX_CHUNKS (SCTP_NUM_CHUNK_TYPES - SCTP_NUM_NOAUTH_CHUNKS) + +/* SCTP-AUTH Section 6.1 + * The RANDOM parameter MUST contain a 32 byte random number. + */ +#define SCTP_AUTH_RANDOM_LENGTH 32 + #endif /* __sctp_constants_h__ */ diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index 16baef4dab7e..119f5a1ed499 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -123,6 +123,7 @@ * sctp/protocol.c */ extern struct sock *sctp_get_ctl_sock(void); +extern void sctp_local_addr_free(struct rcu_head *head); extern int sctp_copy_local_addr_list(struct sctp_bind_addr *, sctp_scope_t, gfp_t gfp, int flags); @@ -190,6 +191,16 @@ void sctp_assocs_proc_exit(void); /* + * Module global variables + */ + + /* + * sctp/protocol.c + */ +extern struct kmem_cache *sctp_chunk_cachep __read_mostly; +extern struct kmem_cache *sctp_bucket_cachep __read_mostly; + +/* * Section: Macros, externs, and inlines */ @@ -330,6 +341,7 @@ extern atomic_t sctp_dbg_objcnt_bind_bucket; extern atomic_t sctp_dbg_objcnt_addr; extern atomic_t sctp_dbg_objcnt_ssnmap; extern atomic_t sctp_dbg_objcnt_datamsg; +extern atomic_t sctp_dbg_objcnt_keys; /* Macros to atomically increment/decrement objcnt counters. */ #define SCTP_DBG_OBJCNT_INC(name) \ @@ -458,6 +470,11 @@ static inline void sctp_skb_set_owner_r(struct sk_buff *skb, struct sock *sk) skb->sk = sk; skb->destructor = sctp_sock_rfree; atomic_add(event->rmem_len, &sk->sk_rmem_alloc); + /* + * This mimics the behavior of + * sk_stream_set_owner_r + */ + sk->sk_forward_alloc -= event->rmem_len; } /* Tests if the list has one and only one entry. */ diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h index 73cb9943c8a8..bf2f5ed69c15 100644 --- a/include/net/sctp/sm.h +++ b/include/net/sctp/sm.h @@ -114,7 +114,6 @@ sctp_state_fn_t sctp_sf_do_4_C; sctp_state_fn_t sctp_sf_eat_data_6_2; sctp_state_fn_t sctp_sf_eat_data_fast_4_4; sctp_state_fn_t sctp_sf_eat_sack_6_2; -sctp_state_fn_t sctp_sf_tabort_8_4_8; sctp_state_fn_t sctp_sf_operr_notify; sctp_state_fn_t sctp_sf_t1_init_timer_expire; sctp_state_fn_t sctp_sf_t1_cookie_timer_expire; @@ -144,6 +143,7 @@ sctp_state_fn_t sctp_sf_do_asconf_ack; sctp_state_fn_t sctp_sf_do_9_2_reshutack; sctp_state_fn_t sctp_sf_eat_fwd_tsn; sctp_state_fn_t sctp_sf_eat_fwd_tsn_fast; +sctp_state_fn_t sctp_sf_eat_auth; /* Prototypes for primitive event state functions. */ sctp_state_fn_t sctp_sf_do_prm_asoc; @@ -214,7 +214,7 @@ struct sctp_chunk *sctp_make_shutdown_ack(const struct sctp_association *asoc, const struct sctp_chunk *); struct sctp_chunk *sctp_make_shutdown_complete(const struct sctp_association *, const struct sctp_chunk *); -void sctp_init_cause(struct sctp_chunk *, __be16 cause, const void *, size_t); +void sctp_init_cause(struct sctp_chunk *, __be16 cause, size_t); struct sctp_chunk *sctp_make_abort(const struct sctp_association *, const struct sctp_chunk *, const size_t hint); @@ -247,6 +247,9 @@ struct sctp_chunk *sctp_make_asconf_update_ip(struct sctp_association *, int, __be16); struct sctp_chunk *sctp_make_asconf_set_prim(struct sctp_association *asoc, union sctp_addr *addr); +int sctp_verify_asconf(const struct sctp_association *asoc, + struct sctp_paramhdr *param_hdr, void *chunk_end, + struct sctp_paramhdr **errp); struct sctp_chunk *sctp_process_asconf(struct sctp_association *asoc, struct sctp_chunk *asconf); int sctp_process_asconf_ack(struct sctp_association *asoc, @@ -254,6 +257,7 @@ int sctp_process_asconf_ack(struct sctp_association *asoc, struct sctp_chunk *sctp_make_fwdtsn(const struct sctp_association *asoc, __u32 new_cum_tsn, size_t nstreams, struct sctp_fwdtsn_skip *skiplist); +struct sctp_chunk *sctp_make_auth(const struct sctp_association *asoc); void sctp_chunk_assign_tsn(struct sctp_chunk *); void sctp_chunk_assign_ssn(struct sctp_chunk *); diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index ee4559b11302..ef892e00c833 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -64,6 +64,7 @@ #include <linux/skbuff.h> /* We need sk_buff_head. */ #include <linux/workqueue.h> /* We need tq_struct. */ #include <linux/sctp.h> /* We need sctp* header structs. */ +#include <net/sctp/auth.h> /* We need auth specific structs */ /* A convenience structure for handling sockaddr structures. * We should wean ourselves off this. @@ -196,8 +197,6 @@ extern struct sctp_globals { /* This is the sctp port control hash. */ int port_hashsize; - int port_rover; - spinlock_t port_alloc_lock; /* Protects port_rover. */ struct sctp_bind_hashbucket *port_hashtable; /* This is the global local address list. @@ -207,12 +206,18 @@ extern struct sctp_globals { * It is a list of sctp_sockaddr_entry. */ struct list_head local_addr_list; + + /* Lock that protects the local_addr_list writers */ + spinlock_t addr_list_lock; /* Flag to indicate if addip is enabled. */ int addip_enable; /* Flag to indicate if PR-SCTP is enabled. */ int prsctp_enable; + + /* Flag to idicate if SCTP-AUTH is enabled */ + int auth_enable; } sctp_globals; #define sctp_rto_initial (sctp_globals.rto_initial) @@ -242,8 +247,10 @@ extern struct sctp_globals { #define sctp_port_alloc_lock (sctp_globals.port_alloc_lock) #define sctp_port_hashtable (sctp_globals.port_hashtable) #define sctp_local_addr_list (sctp_globals.local_addr_list) +#define sctp_local_addr_lock (sctp_globals.addr_list_lock) #define sctp_addip_enable (sctp_globals.addip_enable) #define sctp_prsctp_enable (sctp_globals.prsctp_enable) +#define sctp_auth_enable (sctp_globals.auth_enable) /* SCTP Socket type: UDP or TCP style. */ typedef enum { @@ -393,6 +400,9 @@ struct sctp_cookie { __u32 adaptation_ind; + __u8 auth_random[sizeof(sctp_paramhdr_t) + SCTP_AUTH_RANDOM_LENGTH]; + __u8 auth_hmacs[SCTP_AUTH_NUM_HMACS + 2]; + __u8 auth_chunks[sizeof(sctp_paramhdr_t) + SCTP_AUTH_MAX_CHUNKS]; /* This is a shim for my peer's INIT packet, followed by * a copy of the raw address list of the association. @@ -417,6 +427,7 @@ struct sctp_signed_cookie { * internally. */ union sctp_addr_param { + struct sctp_paramhdr p; struct sctp_ipv4addr_param v4; struct sctp_ipv6addr_param v6; }; @@ -435,6 +446,10 @@ union sctp_params { struct sctp_ipv6addr_param *v6; union sctp_addr_param *addr; struct sctp_adaptation_ind_param *aind; + struct sctp_supported_ext_param *ext; + struct sctp_random_param *random; + struct sctp_chunks_param *chunks; + struct sctp_hmac_algo_param *hmac_algo; }; /* RFC 2960. Section 3.3.5 Heartbeat. @@ -673,6 +688,7 @@ struct sctp_chunk { struct sctp_errhdr *err_hdr; struct sctp_addiphdr *addip_hdr; struct sctp_fwdtsn_hdr *fwdtsn_hdr; + struct sctp_authhdr *auth_hdr; } subh; __u8 *chunk_end; @@ -706,6 +722,13 @@ struct sctp_chunk { */ struct sctp_transport *transport; + /* SCTP-AUTH: For the special case inbound processing of COOKIE-ECHO + * we need save a pointer to the AUTH chunk, since the SCTP-AUTH + * spec violates the principle premis that all chunks are processed + * in order. + */ + struct sk_buff *auth_chunk; + __u8 rtt_in_progress; /* Is this chunk used for RTT calculation? */ __u8 resent; /* Has this chunk ever been retransmitted. */ __u8 has_tsn; /* Does this chunk have a TSN yet? */ @@ -718,6 +741,7 @@ struct sctp_chunk { __s8 fast_retransmit; /* Is this chunk fast retransmitted? */ __u8 tsn_missing_report; /* Data chunk missing counter. */ __u8 data_accepted; /* At least 1 chunk in this packet accepted */ + __u8 auth; /* IN: was auth'ed | OUT: needs auth */ }; void sctp_chunk_hold(struct sctp_chunk *); @@ -736,8 +760,10 @@ const union sctp_addr *sctp_source(const struct sctp_chunk *chunk); /* This is a structure for holding either an IPv6 or an IPv4 address. */ struct sctp_sockaddr_entry { struct list_head list; + struct rcu_head rcu; union sctp_addr a; __u8 use_as_src; + __u8 valid; }; typedef struct sctp_chunk *(sctp_packet_phandler_t)(struct sctp_association *); @@ -765,16 +791,25 @@ struct sctp_packet { */ struct sctp_transport *transport; + /* pointer to the auth chunk for this packet */ + struct sctp_chunk *auth; + /* This packet contains a COOKIE-ECHO chunk. */ - char has_cookie_echo; + __u8 has_cookie_echo; + + /* This packet contains a SACK chunk. */ + __u8 has_sack; - /* This packet containsa SACK chunk. */ - char has_sack; + /* This packet contains an AUTH chunk */ + __u8 has_auth; + + /* This packet contains at least 1 DATA chunk */ + __u8 has_data; /* SCTP cannot fragment this packet. So let ip fragment it. */ - char ipfragok; + __u8 ipfragok; - int malloced; + __u8 malloced; }; struct sctp_packet *sctp_packet_init(struct sctp_packet *, @@ -1037,6 +1072,7 @@ void sctp_inq_init(struct sctp_inq *); void sctp_inq_free(struct sctp_inq *); void sctp_inq_push(struct sctp_inq *, struct sctp_chunk *packet); struct sctp_chunk *sctp_inq_pop(struct sctp_inq *); +struct sctp_chunkhdr *sctp_inq_peek(struct sctp_inq *); void sctp_inq_set_th_handler(struct sctp_inq *, work_func_t); /* This is the structure we use to hold outbound chunks. You push @@ -1148,7 +1184,9 @@ int sctp_bind_addr_copy(struct sctp_bind_addr *dest, int flags); int sctp_add_bind_addr(struct sctp_bind_addr *, union sctp_addr *, __u8 use_as_src, gfp_t gfp); -int sctp_del_bind_addr(struct sctp_bind_addr *, union sctp_addr *); +int sctp_del_bind_addr(struct sctp_bind_addr *, union sctp_addr *, + void fastcall (*rcu_call)(struct rcu_head *, + void (*func)(struct rcu_head *))); int sctp_bind_addr_match(struct sctp_bind_addr *, const union sctp_addr *, struct sctp_sock *); union sctp_addr *sctp_find_unmatch_addr(struct sctp_bind_addr *bp, @@ -1219,9 +1257,6 @@ struct sctp_ep_common { * bind_addr.address_list is our set of local IP addresses. */ struct sctp_bind_addr bind_addr; - - /* Protection during address list comparisons. */ - rwlock_t addr_lock; }; @@ -1284,6 +1319,21 @@ struct sctp_endpoint { /* rcvbuf acct. policy. */ __u32 rcvbuf_policy; + + /* SCTP AUTH: array of the HMACs that will be allocated + * we need this per association so that we don't serialize + */ + struct crypto_hash **auth_hmacs; + + /* SCTP-AUTH: hmacs for the endpoint encoded into parameter */ + struct sctp_hmac_algo_param *auth_hmacs_list; + + /* SCTP-AUTH: chunks to authenticate encoded into parameter */ + struct sctp_chunks_param *auth_chunk_list; + + /* SCTP-AUTH: endpoint shared keys */ + struct list_head endpoint_shared_keys; + __u16 active_key_id; }; /* Recover the outter endpoint structure. */ @@ -1490,6 +1540,8 @@ struct sctp_association { __u8 hostname_address;/* Peer understands DNS addresses? */ __u8 asconf_capable; /* Does peer support ADDIP? */ __u8 prsctp_capable; /* Can peer do PR-SCTP? */ + __u8 auth_capable; /* Is peer doing SCTP-AUTH? */ + __u8 addip_capable; /* Can peer do ADD-IP */ __u32 adaptation_ind; /* Adaptation Code point. */ @@ -1507,6 +1559,14 @@ struct sctp_association { * Initial TSN Value minus 1 */ __u32 addip_serial; + + /* SCTP-AUTH: We need to know pears random number, hmac list + * and authenticated chunk list. All that is part of the + * cookie and these are just pointers to those locations + */ + sctp_random_param_t *peer_random; + sctp_chunks_param_t *peer_chunks; + sctp_hmac_algo_param_t *peer_hmacs; } peer; /* State : A state variable indicating what state the @@ -1790,6 +1850,24 @@ struct sctp_association { */ __u32 addip_serial; + /* SCTP AUTH: list of the endpoint shared keys. These + * keys are provided out of band by the user applicaton + * and can't change during the lifetime of the association + */ + struct list_head endpoint_shared_keys; + + /* SCTP AUTH: + * The current generated assocaition shared key (secret) + */ + struct sctp_auth_bytes *asoc_shared_key; + + /* SCTP AUTH: hmac id of the first peer requested algorithm + * that we support. + */ + __u16 default_hmac_id; + + __u16 active_key_id; + /* Need to send an ECNE Chunk? */ char need_ecne; diff --git a/include/net/sctp/ulpevent.h b/include/net/sctp/ulpevent.h index de88ed5b0ba6..922a151eb93c 100644 --- a/include/net/sctp/ulpevent.h +++ b/include/net/sctp/ulpevent.h @@ -128,6 +128,10 @@ struct sctp_ulpevent *sctp_ulpevent_make_rcvmsg(struct sctp_association *asoc, struct sctp_chunk *chunk, gfp_t gfp); +struct sctp_ulpevent *sctp_ulpevent_make_authkey( + const struct sctp_association *asoc, __u16 key_id, + __u32 indication, gfp_t gfp); + void sctp_ulpevent_read_sndrcvinfo(const struct sctp_ulpevent *event, struct msghdr *); __u16 sctp_ulpevent_get_notification_type(const struct sctp_ulpevent *event); diff --git a/include/net/sctp/ulpqueue.h b/include/net/sctp/ulpqueue.h index 39ea3f442b47..cd33270e86dd 100644 --- a/include/net/sctp/ulpqueue.h +++ b/include/net/sctp/ulpqueue.h @@ -83,6 +83,7 @@ int sctp_clear_pd(struct sock *sk, struct sctp_association *asoc); /* Skip over an SSN. */ void sctp_ulpq_skip(struct sctp_ulpq *ulpq, __u16 sid, __u16 ssn); +void sctp_ulpq_reasm_flushtsn(struct sctp_ulpq *, __u32); #endif /* __sctp_ulpqueue_h__ */ diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h index 6d2b57758cca..00848b641f59 100644 --- a/include/net/sctp/user.h +++ b/include/net/sctp/user.h @@ -103,6 +103,21 @@ enum sctp_optname { #define SCTP_PARTIAL_DELIVERY_POINT SCTP_PARTIAL_DELIVERY_POINT SCTP_MAX_BURST, /* Set/Get max burst */ #define SCTP_MAX_BURST SCTP_MAX_BURST + SCTP_AUTH_CHUNK, /* Set only: add a chunk type to authenticat */ +#define SCTP_AUTH_CHUNK SCTP_AUTH_CHUNK + SCTP_HMAC_IDENT, +#define SCTP_HMAC_IDENT SCTP_HMAC_IDENT + SCTP_AUTH_KEY, +#define SCTP_AUTH_KEY SCTP_AUTH_KEY + SCTP_AUTH_ACTIVE_KEY, +#define SCTP_AUTH_ACTIVE_KEY SCTP_AUTH_ACTIVE_KEY + SCTP_AUTH_DELETE_KEY, +#define SCTP_AUTH_DELETE_KEY SCTP_AUTH_DELETE_KEY + SCTP_PEER_AUTH_CHUNKS, /* Read only */ +#define SCTP_PEER_AUTH_CHUNKS SCTP_PEER_AUTH_CHUNKS + SCTP_LOCAL_AUTH_CHUNKS, /* Read only */ +#define SCTP_LOCAL_AUTH_CHUNKS SCTP_LOCAL_AUTH_CHUNKS + /* Internal Socket Options. Some of the sctp library functions are * implemented using these socket options. @@ -370,6 +385,19 @@ struct sctp_pdapi_event { enum { SCTP_PARTIAL_DELIVERY_ABORTED=0, }; +struct sctp_authkey_event { + __u16 auth_type; + __u16 auth_flags; + __u32 auth_length; + __u16 auth_keynumber; + __u16 auth_altkeynumber; + __u32 auth_indication; + sctp_assoc_t auth_assoc_id; +}; + +enum { SCTP_AUTH_NEWKEY = 0, }; + + /* * Described in Section 7.3 * Ancillary Data and Notification Interest Options @@ -405,6 +433,7 @@ union sctp_notification { struct sctp_shutdown_event sn_shutdown_event; struct sctp_adaptation_event sn_adaptation_event; struct sctp_pdapi_event sn_pdapi_event; + struct sctp_authkey_event sn_authkey_event; }; /* Section 5.3.1 @@ -421,6 +450,7 @@ enum sctp_sn_type { SCTP_SHUTDOWN_EVENT, SCTP_PARTIAL_DELIVERY_EVENT, SCTP_ADAPTATION_INDICATION, + SCTP_AUTHENTICATION_EVENT, }; /* Notification error codes used to fill up the error fields in some @@ -539,6 +569,54 @@ struct sctp_paddrparams { __u32 spp_flags; } __attribute__((packed, aligned(4))); +/* + * 7.1.18. Add a chunk that must be authenticated (SCTP_AUTH_CHUNK) + * + * This set option adds a chunk type that the user is requesting to be + * received only in an authenticated way. Changes to the list of chunks + * will only effect future associations on the socket. + */ +struct sctp_authchunk { + __u8 sauth_chunk; +}; + +/* + * 7.1.19. Get or set the list of supported HMAC Identifiers (SCTP_HMAC_IDENT) + * + * This option gets or sets the list of HMAC algorithms that the local + * endpoint requires the peer to use. +*/ +struct sctp_hmacalgo { + __u16 shmac_num_idents; + __u16 shmac_idents[]; +}; + +/* + * 7.1.20. Set a shared key (SCTP_AUTH_KEY) + * + * This option will set a shared secret key which is used to build an + * association shared key. + */ +struct sctp_authkey { + sctp_assoc_t sca_assoc_id; + __u16 sca_keynumber; + __u16 sca_keylen; + __u8 sca_key[]; +}; + +/* + * 7.1.21. Get or set the active shared key (SCTP_AUTH_ACTIVE_KEY) + * + * This option will get or set the active shared key to be used to build + * the association shared key. + */ + +struct sctp_authkeyid { + sctp_assoc_t scact_assoc_id; + __u16 scact_keynumber; +}; + + /* 7.1.23. Delayed Ack Timer (SCTP_DELAYED_ACK_TIME) * * This options will get or set the delayed ack timer. The time is set @@ -608,6 +686,18 @@ struct sctp_status { }; /* + * 7.2.3. Get the list of chunks the peer requires to be authenticated + * (SCTP_PEER_AUTH_CHUNKS) + * + * This option gets a list of chunks for a specified association that + * the peer requires to be received authenticated only. + */ +struct sctp_authchunks { + sctp_assoc_t gauth_assoc_id; + uint8_t gauth_chunks[]; +}; + +/* * 8.3, 8.5 get all peer/local addresses in an association. * This parameter struct is used by SCTP_GET_PEER_ADDRS and * SCTP_GET_LOCAL_ADDRS socket options used internally to implement diff --git a/include/net/snmp.h b/include/net/snmp.h index 464970e39ec0..ea206bff0dc4 100644 --- a/include/net/snmp.h +++ b/include/net/snmp.h @@ -82,12 +82,23 @@ struct icmp_mib { unsigned long mibs[ICMP_MIB_MAX]; } __SNMP_MIB_ALIGN__; +#define ICMPMSG_MIB_MAX __ICMPMSG_MIB_MAX +struct icmpmsg_mib { + unsigned long mibs[ICMPMSG_MIB_MAX]; +} __SNMP_MIB_ALIGN__; + /* ICMP6 (IPv6-ICMP) */ #define ICMP6_MIB_MAX __ICMP6_MIB_MAX struct icmpv6_mib { unsigned long mibs[ICMP6_MIB_MAX]; } __SNMP_MIB_ALIGN__; +#define ICMP6MSG_MIB_MAX __ICMP6MSG_MIB_MAX +struct icmpv6msg_mib { + unsigned long mibs[ICMP6MSG_MIB_MAX]; +} __SNMP_MIB_ALIGN__; + + /* TCP */ #define TCP_MIB_MAX __TCP_MIB_MAX struct tcp_mib { diff --git a/include/net/sock.h b/include/net/sock.h index dfeb8b13024f..453c79d0915b 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -40,6 +40,7 @@ #ifndef _SOCK_H #define _SOCK_H +#include <linux/kernel.h> #include <linux/list.h> #include <linux/timer.h> #include <linux/cache.h> @@ -55,6 +56,7 @@ #include <asm/atomic.h> #include <net/dst.h> #include <net/checksum.h> +#include <net/net_namespace.h> /* * This structure really needs to be cleaned up. @@ -75,10 +77,9 @@ * between user contexts and software interrupt processing, whereas the * mini-semaphore synchronizes multiple users amongst themselves. */ -struct sock_iocb; typedef struct { spinlock_t slock; - struct sock_iocb *owner; + int owned; wait_queue_head_t wq; /* * We express the mutex-alike socket_lock semantics @@ -105,6 +106,7 @@ struct proto; * @skc_refcnt: reference count * @skc_hash: hash value used with various protocol lookup tables * @skc_prot: protocol handlers inside a network family + * @skc_net: reference to the network namespace of this socket * * This is the minimal network layer representation of sockets, the header * for struct sock and struct inet_timewait_sock. @@ -119,6 +121,7 @@ struct sock_common { atomic_t skc_refcnt; unsigned int skc_hash; struct proto *skc_prot; + struct net *skc_net; }; /** @@ -195,6 +198,7 @@ struct sock { #define sk_refcnt __sk_common.skc_refcnt #define sk_hash __sk_common.skc_hash #define sk_prot __sk_common.skc_prot +#define sk_net __sk_common.skc_net unsigned char sk_shutdown : 2, sk_no_check : 2, sk_userlocks : 4; @@ -481,17 +485,17 @@ static inline void sk_add_backlog(struct sock *sk, struct sk_buff *skb) skb->next = NULL; } -#define sk_wait_event(__sk, __timeo, __condition) \ -({ int rc; \ - release_sock(__sk); \ - rc = __condition; \ - if (!rc) { \ - *(__timeo) = schedule_timeout(*(__timeo)); \ - } \ - lock_sock(__sk); \ - rc = __condition; \ - rc; \ -}) +#define sk_wait_event(__sk, __timeo, __condition) \ + ({ int __rc; \ + release_sock(__sk); \ + __rc = __condition; \ + if (!__rc) { \ + *(__timeo) = schedule_timeout(*(__timeo)); \ + } \ + lock_sock(__sk); \ + __rc = __condition; \ + __rc; \ + }) extern int sk_stream_wait_connect(struct sock *sk, long *timeo_p); extern int sk_stream_wait_memory(struct sock *sk, long *timeo_p); @@ -702,7 +706,7 @@ extern int sk_stream_mem_schedule(struct sock *sk, int size, int kind); static inline int sk_stream_pages(int amt) { - return (amt + SK_STREAM_MEM_QUANTUM - 1) / SK_STREAM_MEM_QUANTUM; + return DIV_ROUND_UP(amt, SK_STREAM_MEM_QUANTUM); } static inline void sk_stream_mem_reclaim(struct sock *sk) @@ -736,7 +740,7 @@ static inline int sk_stream_wmem_schedule(struct sock *sk, int size) * Since ~2.3.5 it is also exclusive sleep lock serializing * accesses from user process context. */ -#define sock_owned_by_user(sk) ((sk)->sk_lock.owner) +#define sock_owned_by_user(sk) ((sk)->sk_lock.owned) /* * Macro so as to not evaluate some arguments when @@ -747,7 +751,7 @@ static inline int sk_stream_wmem_schedule(struct sock *sk, int size) */ #define sock_lock_init_class_and_name(sk, sname, skey, name, key) \ do { \ - sk->sk_lock.owner = NULL; \ + sk->sk_lock.owned = 0; \ init_waitqueue_head(&sk->sk_lock.wq); \ spin_lock_init(&(sk)->sk_lock.slock); \ debug_check_no_locks_freed((void *)&(sk)->sk_lock, \ @@ -773,7 +777,7 @@ extern void FASTCALL(release_sock(struct sock *sk)); SINGLE_DEPTH_NESTING) #define bh_unlock_sock(__sk) spin_unlock(&((__sk)->sk_lock.slock)) -extern struct sock *sk_alloc(int family, +extern struct sock *sk_alloc(struct net *net, int family, gfp_t priority, struct proto *prot, int zero_it); extern void sk_free(struct sock *sk); @@ -1002,6 +1006,7 @@ static inline void sock_copy(struct sock *nsk, const struct sock *osk) #endif memcpy(nsk, osk, osk->sk_prot->obj_size); + get_net(nsk->sk_net); #ifdef CONFIG_SECURITY_NETWORK nsk->sk_security = sptr; security_sk_clone(osk, nsk); diff --git a/include/net/tc_act/tc_nat.h b/include/net/tc_act/tc_nat.h new file mode 100644 index 000000000000..4a691f34d703 --- /dev/null +++ b/include/net/tc_act/tc_nat.h @@ -0,0 +1,21 @@ +#ifndef __NET_TC_NAT_H +#define __NET_TC_NAT_H + +#include <linux/types.h> +#include <net/act_api.h> + +struct tcf_nat { + struct tcf_common common; + + __be32 old_addr; + __be32 new_addr; + __be32 mask; + u32 flags; +}; + +static inline struct tcf_nat *to_tcf_nat(struct tcf_common *pc) +{ + return container_of(pc, struct tcf_nat, common); +} + +#endif /* __NET_TC_NAT_H */ diff --git a/include/net/tcp.h b/include/net/tcp.h index a8af9ae00177..92049e681258 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -39,6 +39,7 @@ #include <net/snmp.h> #include <net/ip.h> #include <net/tcp_states.h> +#include <net/inet_ecn.h> #include <linux/seq_file.h> @@ -281,7 +282,7 @@ extern int tcp_v4_remember_stamp(struct sock *sk); extern int tcp_v4_tw_remember_stamp(struct inet_timewait_sock *tw); -extern int tcp_sendmsg(struct kiocb *iocb, struct sock *sk, +extern int tcp_sendmsg(struct kiocb *iocb, struct socket *sock, struct msghdr *msg, size_t size); extern ssize_t tcp_sendpage(struct socket *sock, struct page *page, int offset, size_t size, int flags); @@ -330,6 +331,17 @@ static inline void tcp_clear_options(struct tcp_options_received *rx_opt) rx_opt->tstamp_ok = rx_opt->sack_ok = rx_opt->wscale_ok = rx_opt->snd_wscale = 0; } +#define TCP_ECN_OK 1 +#define TCP_ECN_QUEUE_CWR 2 +#define TCP_ECN_DEMAND_CWR 4 + +static __inline__ void +TCP_ECN_create_request(struct request_sock *req, struct tcphdr *th) +{ + if (sysctl_tcp_ecn && th->ece && th->cwr) + inet_rsk(req)->ecn_ok = 1; +} + enum tcp_tw_status { TCP_TW_SUCCESS = 0, @@ -573,8 +585,6 @@ struct tcp_skb_cb { #define TCP_SKB_CB(__skb) ((struct tcp_skb_cb *)&((__skb)->cb[0])) -#include <net/tcp_ecn.h> - /* Due to TSO, an SKB can be composed of multiple actual * packets. To keep these tracked properly, we use this. */ @@ -589,32 +599,19 @@ static inline int tcp_skb_mss(const struct sk_buff *skb) return skb_shinfo(skb)->gso_size; } -static inline void tcp_dec_pcount_approx(__u32 *count, - const struct sk_buff *skb) +static inline void tcp_dec_pcount_approx_int(__u32 *count, const int decr) { if (*count) { - *count -= tcp_skb_pcount(skb); + *count -= decr; if ((int)*count < 0) *count = 0; } } -static inline void tcp_packets_out_inc(struct sock *sk, - const struct sk_buff *skb) -{ - struct tcp_sock *tp = tcp_sk(sk); - int orig = tp->packets_out; - - tp->packets_out += tcp_skb_pcount(skb); - if (!orig) - inet_csk_reset_xmit_timer(sk, ICSK_TIME_RETRANS, - inet_csk(sk)->icsk_rto, TCP_RTO_MAX); -} - -static inline void tcp_packets_out_dec(struct tcp_sock *tp, - const struct sk_buff *skb) +static inline void tcp_dec_pcount_approx(__u32 *count, + const struct sk_buff *skb) { - tp->packets_out -= tcp_skb_pcount(skb); + tcp_dec_pcount_approx_int(count, tcp_skb_pcount(skb)); } /* Events passed to congestion control interface */ @@ -652,8 +649,7 @@ struct tcp_congestion_ops { /* lower bound for congestion window (optional) */ u32 (*min_cwnd)(const struct sock *sk); /* do new cwnd calculation (required) */ - void (*cong_avoid)(struct sock *sk, u32 ack, - u32 rtt, u32 in_flight, int good_ack); + void (*cong_avoid)(struct sock *sk, u32 ack, u32 in_flight, int good_ack); /* call before changing ca_state (optional) */ void (*set_state)(struct sock *sk, u8 new_state); /* call when cwnd event occurs (optional) */ @@ -661,7 +657,7 @@ struct tcp_congestion_ops { /* new value of cwnd after loss (optional) */ u32 (*undo_cwnd)(struct sock *sk); /* hook for packet ack accounting (optional) */ - void (*pkts_acked)(struct sock *sk, u32 num_acked, ktime_t last); + void (*pkts_acked)(struct sock *sk, u32 num_acked, s32 rtt_us); /* get info for inet_diag (optional) */ void (*get_info)(struct sock *sk, u32 ext, struct sk_buff *skb); @@ -684,8 +680,7 @@ extern void tcp_slow_start(struct tcp_sock *tp); extern struct tcp_congestion_ops tcp_init_congestion_ops; extern u32 tcp_reno_ssthresh(struct sock *sk); -extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, - u32 rtt, u32 in_flight, int flag); +extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 in_flight, int flag); extern u32 tcp_reno_min_cwnd(const struct sock *sk); extern struct tcp_congestion_ops tcp_reno; @@ -706,6 +701,39 @@ static inline void tcp_ca_event(struct sock *sk, const enum tcp_ca_event event) icsk->icsk_ca_ops->cwnd_event(sk, event); } +/* These functions determine how the current flow behaves in respect of SACK + * handling. SACK is negotiated with the peer, and therefore it can vary + * between different flows. + * + * tcp_is_sack - SACK enabled + * tcp_is_reno - No SACK + * tcp_is_fack - FACK enabled, implies SACK enabled + */ +static inline int tcp_is_sack(const struct tcp_sock *tp) +{ + return tp->rx_opt.sack_ok; +} + +static inline int tcp_is_reno(const struct tcp_sock *tp) +{ + return !tcp_is_sack(tp); +} + +static inline int tcp_is_fack(const struct tcp_sock *tp) +{ + return tp->rx_opt.sack_ok & 2; +} + +static inline void tcp_enable_fack(struct tcp_sock *tp) +{ + tp->rx_opt.sack_ok |= 2; +} + +static inline unsigned int tcp_left_out(const struct tcp_sock *tp) +{ + return tp->sacked_out + tp->lost_out; +} + /* This determines how many packets are "in the network" to the best * of our knowledge. In many cases it is conservative, but where * detailed information is available from the receiver (via SACK @@ -722,7 +750,7 @@ static inline void tcp_ca_event(struct sock *sk, const enum tcp_ca_event event) */ static inline unsigned int tcp_packets_in_flight(const struct tcp_sock *tp) { - return (tp->packets_out - tp->left_out + tp->retrans_out); + return tp->packets_out - tcp_left_out(tp) + tp->retrans_out; } /* If cwnd > ssthresh, we may raise ssthresh to be half-way to cwnd. @@ -740,12 +768,8 @@ static inline __u32 tcp_current_ssthresh(const struct sock *sk) (tp->snd_cwnd >> 2))); } -static inline void tcp_sync_left_out(struct tcp_sock *tp) -{ - BUG_ON(tp->rx_opt.sack_ok && - (tp->sacked_out + tp->lost_out > tp->packets_out)); - tp->left_out = tp->sacked_out + tp->lost_out; -} +/* Use define here intentionally to get WARN_ON location shown at the caller */ +#define tcp_verify_left_out(tp) WARN_ON(tcp_left_out(tp) > tp->packets_out) extern void tcp_enter_cwr(struct sock *sk, const int set_ssthresh); extern __u32 tcp_init_cwnd(struct tcp_sock *tp, struct dst_entry *dst); @@ -1042,12 +1066,18 @@ static inline void tcp_mib_init(void) TCP_ADD_STATS_USER(TCP_MIB_MAXCONN, -1); } -/*from STCP */ -static inline void clear_all_retrans_hints(struct tcp_sock *tp){ +/* from STCP */ +static inline void tcp_clear_retrans_hints_partial(struct tcp_sock *tp) +{ tp->lost_skb_hint = NULL; tp->scoreboard_skb_hint = NULL; tp->retransmit_skb_hint = NULL; tp->forward_skb_hint = NULL; +} + +static inline void tcp_clear_all_retrans_hints(struct tcp_sock *tp) +{ + tcp_clear_retrans_hints_partial(tp); tp->fastpath_skb_hint = NULL; } @@ -1061,14 +1091,12 @@ struct tcp_md5sig_key { }; struct tcp4_md5sig_key { - u8 *key; - u16 keylen; + struct tcp_md5sig_key base; __be32 addr; }; struct tcp6_md5sig_key { - u8 *key; - u16 keylen; + struct tcp_md5sig_key base; #if 0 u32 scope_id; /* XXX */ #endif diff --git a/include/net/tcp_ecn.h b/include/net/tcp_ecn.h deleted file mode 100644 index 89eb3e05116d..000000000000 --- a/include/net/tcp_ecn.h +++ /dev/null @@ -1,130 +0,0 @@ -#ifndef _NET_TCP_ECN_H_ -#define _NET_TCP_ECN_H_ 1 - -#include <net/inet_ecn.h> -#include <net/request_sock.h> - -#define TCP_HP_BITS (~(TCP_RESERVED_BITS|TCP_FLAG_PSH)) - -#define TCP_ECN_OK 1 -#define TCP_ECN_QUEUE_CWR 2 -#define TCP_ECN_DEMAND_CWR 4 - -static inline void TCP_ECN_queue_cwr(struct tcp_sock *tp) -{ - if (tp->ecn_flags&TCP_ECN_OK) - tp->ecn_flags |= TCP_ECN_QUEUE_CWR; -} - - -/* Output functions */ - -static inline void TCP_ECN_send_synack(struct tcp_sock *tp, - struct sk_buff *skb) -{ - TCP_SKB_CB(skb)->flags &= ~TCPCB_FLAG_CWR; - if (!(tp->ecn_flags&TCP_ECN_OK)) - TCP_SKB_CB(skb)->flags &= ~TCPCB_FLAG_ECE; -} - -static inline void TCP_ECN_send_syn(struct sock *sk, struct sk_buff *skb) -{ - struct tcp_sock *tp = tcp_sk(sk); - - tp->ecn_flags = 0; - if (sysctl_tcp_ecn) { - TCP_SKB_CB(skb)->flags |= TCPCB_FLAG_ECE|TCPCB_FLAG_CWR; - tp->ecn_flags = TCP_ECN_OK; - } -} - -static __inline__ void -TCP_ECN_make_synack(struct request_sock *req, struct tcphdr *th) -{ - if (inet_rsk(req)->ecn_ok) - th->ece = 1; -} - -static inline void TCP_ECN_send(struct sock *sk, struct sk_buff *skb, - int tcp_header_len) -{ - struct tcp_sock *tp = tcp_sk(sk); - - if (tp->ecn_flags & TCP_ECN_OK) { - /* Not-retransmitted data segment: set ECT and inject CWR. */ - if (skb->len != tcp_header_len && - !before(TCP_SKB_CB(skb)->seq, tp->snd_nxt)) { - INET_ECN_xmit(sk); - if (tp->ecn_flags&TCP_ECN_QUEUE_CWR) { - tp->ecn_flags &= ~TCP_ECN_QUEUE_CWR; - tcp_hdr(skb)->cwr = 1; - skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; - } - } else { - /* ACK or retransmitted segment: clear ECT|CE */ - INET_ECN_dontxmit(sk); - } - if (tp->ecn_flags & TCP_ECN_DEMAND_CWR) - tcp_hdr(skb)->ece = 1; - } -} - -/* Input functions */ - -static inline void TCP_ECN_accept_cwr(struct tcp_sock *tp, struct sk_buff *skb) -{ - if (tcp_hdr(skb)->cwr) - tp->ecn_flags &= ~TCP_ECN_DEMAND_CWR; -} - -static inline void TCP_ECN_withdraw_cwr(struct tcp_sock *tp) -{ - tp->ecn_flags &= ~TCP_ECN_DEMAND_CWR; -} - -static inline void TCP_ECN_check_ce(struct tcp_sock *tp, struct sk_buff *skb) -{ - if (tp->ecn_flags&TCP_ECN_OK) { - if (INET_ECN_is_ce(TCP_SKB_CB(skb)->flags)) - tp->ecn_flags |= TCP_ECN_DEMAND_CWR; - /* Funny extension: if ECT is not set on a segment, - * it is surely retransmit. It is not in ECN RFC, - * but Linux follows this rule. */ - else if (INET_ECN_is_not_ect((TCP_SKB_CB(skb)->flags))) - tcp_enter_quickack_mode((struct sock *)tp); - } -} - -static inline void TCP_ECN_rcv_synack(struct tcp_sock *tp, struct tcphdr *th) -{ - if ((tp->ecn_flags&TCP_ECN_OK) && (!th->ece || th->cwr)) - tp->ecn_flags &= ~TCP_ECN_OK; -} - -static inline void TCP_ECN_rcv_syn(struct tcp_sock *tp, struct tcphdr *th) -{ - if ((tp->ecn_flags&TCP_ECN_OK) && (!th->ece || !th->cwr)) - tp->ecn_flags &= ~TCP_ECN_OK; -} - -static inline int TCP_ECN_rcv_ecn_echo(struct tcp_sock *tp, struct tcphdr *th) -{ - if (th->ece && !th->syn && (tp->ecn_flags&TCP_ECN_OK)) - return 1; - return 0; -} - -static inline void TCP_ECN_openreq_child(struct tcp_sock *tp, - struct request_sock *req) -{ - tp->ecn_flags = inet_rsk(req)->ecn_ok ? TCP_ECN_OK : 0; -} - -static __inline__ void -TCP_ECN_create_request(struct request_sock *req, struct tcphdr *th) -{ - if (sysctl_tcp_ecn && th->ece && th->cwr) - inet_rsk(req)->ecn_ok = 1; -} - -#endif diff --git a/include/net/veth.h b/include/net/veth.h new file mode 100644 index 000000000000..3354c1eb424e --- /dev/null +++ b/include/net/veth.h @@ -0,0 +1,12 @@ +#ifndef __NET_VETH_H_ +#define __NET_VETH_H_ + +enum { + VETH_INFO_UNSPEC, + VETH_INFO_PEER, + + __VETH_INFO_MAX +#define VETH_INFO_MAX (__VETH_INFO_MAX - 1) +}; + +#endif diff --git a/include/net/wext.h b/include/net/wext.h index c02b8decf3af..80b31d826b7a 100644 --- a/include/net/wext.h +++ b/include/net/wext.h @@ -5,16 +5,23 @@ * wireless extensions interface to the core code */ +struct net; + #ifdef CONFIG_WIRELESS_EXT -extern int wext_proc_init(void); -extern int wext_handle_ioctl(struct ifreq *ifr, unsigned int cmd, +extern int wext_proc_init(struct net *net); +extern void wext_proc_exit(struct net *net); +extern int wext_handle_ioctl(struct net *net, struct ifreq *ifr, unsigned int cmd, void __user *arg); #else -static inline int wext_proc_init(void) +static inline int wext_proc_init(struct net *net) { return 0; } -static inline int wext_handle_ioctl(struct ifreq *ifr, unsigned int cmd, +static inline void wext_proc_exit(struct net *net) +{ + return; +} +static inline int wext_handle_ioctl(struct net *net, struct ifreq *ifr, unsigned int cmd, void __user *arg) { return -EINVAL; diff --git a/include/net/xfrm.h b/include/net/xfrm.h index ae959e950174..77be396ca633 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -2,7 +2,6 @@ #define _NET_XFRM_H #include <linux/compiler.h> -#include <linux/in.h> #include <linux/xfrm.h> #include <linux/spinlock.h> #include <linux/list.h> @@ -12,9 +11,11 @@ #include <linux/ipsec.h> #include <linux/in6.h> #include <linux/mutex.h> +#include <linux/audit.h> #include <net/sock.h> #include <net/dst.h> +#include <net/ip.h> #include <net/route.h> #include <net/ipv6.h> #include <net/ip6_fib.h> @@ -278,6 +279,7 @@ struct xfrm_type __u8 proto; __u8 flags; #define XFRM_TYPE_NON_FRAGMENT 1 +#define XFRM_TYPE_REPLAY_PROT 2 int (*init_state)(struct xfrm_state *x); void (*destructor)(struct xfrm_state *); @@ -298,6 +300,18 @@ extern void xfrm_put_type(struct xfrm_type *type); struct xfrm_mode { int (*input)(struct xfrm_state *x, struct sk_buff *skb); + + /* + * Add encapsulation header. + * + * On exit, the transport header will be set to the start of the + * encapsulation header to be filled in by x->type->output and + * the mac header will be set to the nextheader (protocol for + * IPv4) field of the extension header directly preceding the + * encapsulation header, or in its absence, that of the top IP + * header. The value of the network header will always point + * to the top IP header while skb->data will point to the payload. + */ int (*output)(struct xfrm_state *x,struct sk_buff *skb); struct module *owner; @@ -418,18 +432,66 @@ extern int xfrm_unregister_km(struct xfrm_mgr *km); extern unsigned int xfrm_policy_count[XFRM_POLICY_MAX*2]; +/* + * This structure is used for the duration where packets are being + * transformed by IPsec. As soon as the packet leaves IPsec the + * area beyond the generic IP part may be overwritten. + */ +struct xfrm_skb_cb { + union { + struct inet_skb_parm h4; + struct inet6_skb_parm h6; + } header; + + /* Sequence number for replay protection. */ + u64 seq; +}; + +#define XFRM_SKB_CB(__skb) ((struct xfrm_skb_cb *)&((__skb)->cb[0])) + /* Audit Information */ struct xfrm_audit { - uid_t loginuid; + u32 loginuid; u32 secid; }; #ifdef CONFIG_AUDITSYSCALL -extern void xfrm_audit_log(uid_t auid, u32 secid, int type, int result, - struct xfrm_policy *xp, struct xfrm_state *x); +static inline struct audit_buffer *xfrm_audit_start(u32 auid, u32 sid) +{ + struct audit_buffer *audit_buf = NULL; + char *secctx; + u32 secctx_len; + + audit_buf = audit_log_start(current->audit_context, GFP_ATOMIC, + AUDIT_MAC_IPSEC_EVENT); + if (audit_buf == NULL) + return NULL; + + audit_log_format(audit_buf, "auid=%u", auid); + + if (sid != 0 && + security_secid_to_secctx(sid, &secctx, &secctx_len) == 0) { + audit_log_format(audit_buf, " subj=%s", secctx); + security_release_secctx(secctx, secctx_len); + } else + audit_log_task_context(audit_buf); + return audit_buf; +} + +extern void xfrm_audit_policy_add(struct xfrm_policy *xp, int result, + u32 auid, u32 sid); +extern void xfrm_audit_policy_delete(struct xfrm_policy *xp, int result, + u32 auid, u32 sid); +extern void xfrm_audit_state_add(struct xfrm_state *x, int result, + u32 auid, u32 sid); +extern void xfrm_audit_state_delete(struct xfrm_state *x, int result, + u32 auid, u32 sid); #else -#define xfrm_audit_log(a,s,t,r,p,x) do { ; } while (0) +#define xfrm_audit_policy_add(x, r, a, s) do { ; } while (0) +#define xfrm_audit_policy_delete(x, r, a, s) do { ; } while (0) +#define xfrm_audit_state_add(x, r, a, s) do { ; } while (0) +#define xfrm_audit_state_delete(x, r, a, s) do { ; } while (0) #endif /* CONFIG_AUDITSYSCALL */ static inline void xfrm_pol_hold(struct xfrm_policy *policy) @@ -585,7 +647,6 @@ static inline int xfrm_sec_ctx_match(struct xfrm_sec_ctx *s1, struct xfrm_sec_ct struct xfrm_dst { union { - struct xfrm_dst *next; struct dst_entry dst; struct rtable rt; struct rt6_info rt6; @@ -982,9 +1043,9 @@ extern void xfrm_spd_getinfo(struct xfrmk_spdinfo *si); extern int xfrm_replay_check(struct xfrm_state *x, __be32 seq); extern void xfrm_replay_advance(struct xfrm_state *x, __be32 seq); extern void xfrm_replay_notify(struct xfrm_state *x, int event); -extern int xfrm_state_check(struct xfrm_state *x, struct sk_buff *skb); extern int xfrm_state_mtu(struct xfrm_state *x, int mtu); extern int xfrm_init_state(struct xfrm_state *x); +extern int xfrm_output(struct sk_buff *skb); extern int xfrm4_rcv(struct sk_buff *skb); extern int xfrm4_output(struct sk_buff *skb); extern int xfrm4_tunnel_register(struct xfrm_tunnel *handler, unsigned short family); @@ -1035,7 +1096,7 @@ struct xfrm_policy *xfrm_policy_bysel_ctx(u8 type, int dir, struct xfrm_policy *xfrm_policy_byid(u8, int dir, u32 id, int delete, int *err); int xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info); u32 xfrm_get_acqseq(void); -void xfrm_alloc_spi(struct xfrm_state *x, __be32 minspi, __be32 maxspi); +extern int xfrm_alloc_spi(struct xfrm_state *x, u32 minspi, u32 maxspi); struct xfrm_state * xfrm_find_acq(u8 mode, u32 reqid, u8 proto, xfrm_address_t *daddr, xfrm_address_t *saddr, int create, unsigned short family); @@ -1114,12 +1175,6 @@ static inline int xfrm_aevent_is_on(void) return ret; } -static inline void xfrm_aevent_doreplay(struct xfrm_state *x) -{ - if (xfrm_aevent_is_on()) - xfrm_replay_notify(x, XFRM_REPLAY_UPDATE); -} - #ifdef CONFIG_XFRM_MIGRATE static inline struct xfrm_algo *xfrm_algo_clone(struct xfrm_algo *orig) { diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h index 12243e80c706..a627c8682d2f 100644 --- a/include/rdma/ib_cm.h +++ b/include/rdma/ib_cm.h @@ -477,12 +477,15 @@ int ib_send_cm_rej(struct ib_cm_id *cm_id, const void *private_data, u8 private_data_len); +#define IB_CM_MRA_FLAG_DELAY 0x80 /* Send MRA only after a duplicate msg */ + /** * ib_send_cm_mra - Sends a message receipt acknowledgement to a connection * message. * @cm_id: Connection identifier associated with the connection message. - * @service_timeout: The maximum time required for the sender to reply to - * to the connection message. + * @service_timeout: The lower 5-bits specify the maximum time required for + * the sender to reply to to the connection message. The upper 3-bits + * specify additional control flags. * @private_data: Optional user-defined private data sent with the * message receipt acknowledgement. * @private_data_len: Size of the private data buffer, in bytes. diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h index 30712ddd8a5e..8ec3799e42e1 100644 --- a/include/rdma/ib_mad.h +++ b/include/rdma/ib_mad.h @@ -39,6 +39,8 @@ #if !defined( IB_MAD_H ) #define IB_MAD_H +#include <linux/list.h> + #include <rdma/ib_verbs.h> /* Management base version */ diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h index 5e26b2f53f86..942692b0b92e 100644 --- a/include/rdma/ib_sa.h +++ b/include/rdma/ib_sa.h @@ -109,8 +109,8 @@ enum ib_sa_selector { * Reserved rows are indicated with comments to help maintainability. */ -/* reserved: 0 */ -/* reserved: 1 */ +#define IB_SA_PATH_REC_SERVICE_ID (IB_SA_COMP_MASK( 0) |\ + IB_SA_COMP_MASK( 1)) #define IB_SA_PATH_REC_DGID IB_SA_COMP_MASK( 2) #define IB_SA_PATH_REC_SGID IB_SA_COMP_MASK( 3) #define IB_SA_PATH_REC_DLID IB_SA_COMP_MASK( 4) @@ -123,7 +123,7 @@ enum ib_sa_selector { #define IB_SA_PATH_REC_REVERSIBLE IB_SA_COMP_MASK(11) #define IB_SA_PATH_REC_NUMB_PATH IB_SA_COMP_MASK(12) #define IB_SA_PATH_REC_PKEY IB_SA_COMP_MASK(13) -/* reserved: 14 */ +#define IB_SA_PATH_REC_QOS_CLASS IB_SA_COMP_MASK(14) #define IB_SA_PATH_REC_SL IB_SA_COMP_MASK(15) #define IB_SA_PATH_REC_MTU_SELECTOR IB_SA_COMP_MASK(16) #define IB_SA_PATH_REC_MTU IB_SA_COMP_MASK(17) @@ -134,8 +134,7 @@ enum ib_sa_selector { #define IB_SA_PATH_REC_PREFERENCE IB_SA_COMP_MASK(22) struct ib_sa_path_rec { - /* reserved */ - /* reserved */ + __be64 service_id; union ib_gid dgid; union ib_gid sgid; __be16 dlid; @@ -148,7 +147,7 @@ struct ib_sa_path_rec { int reversible; u8 numb_path; __be16 pkey; - /* reserved */ + __be16 qos_class; u8 sl; u8 mtu_selector; u8 mtu; diff --git a/include/rdma/ib_umem.h b/include/rdma/ib_umem.h index c533d6c7903f..22298423cf0b 100644 --- a/include/rdma/ib_umem.h +++ b/include/rdma/ib_umem.h @@ -45,6 +45,7 @@ struct ib_umem { int offset; int page_size; int writable; + int hugetlb; struct list_head chunk_list; struct work_struct work; struct mm_struct *mm; diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h index d66b15ea82c4..29d2c7205a90 100644 --- a/include/rdma/ib_user_mad.h +++ b/include/rdma/ib_user_mad.h @@ -52,7 +52,50 @@ */ /** + * ib_user_mad_hdr_old - Old version of MAD packet header without pkey_index + * @id - ID of agent MAD received with/to be sent with + * @status - 0 on successful receive, ETIMEDOUT if no response + * received (transaction ID in data[] will be set to TID of original + * request) (ignored on send) + * @timeout_ms - Milliseconds to wait for response (unset on receive) + * @retries - Number of automatic retries to attempt + * @qpn - Remote QP number received from/to be sent to + * @qkey - Remote Q_Key to be sent with (unset on receive) + * @lid - Remote lid received from/to be sent to + * @sl - Service level received with/to be sent with + * @path_bits - Local path bits received with/to be sent with + * @grh_present - If set, GRH was received/should be sent + * @gid_index - Local GID index to send with (unset on receive) + * @hop_limit - Hop limit in GRH + * @traffic_class - Traffic class in GRH + * @gid - Remote GID in GRH + * @flow_label - Flow label in GRH + */ +struct ib_user_mad_hdr_old { + __u32 id; + __u32 status; + __u32 timeout_ms; + __u32 retries; + __u32 length; + __be32 qpn; + __be32 qkey; + __be16 lid; + __u8 sl; + __u8 path_bits; + __u8 grh_present; + __u8 gid_index; + __u8 hop_limit; + __u8 traffic_class; + __u8 gid[16]; + __be32 flow_label; +}; + +/** * ib_user_mad_hdr - MAD packet header + * This layout allows specifying/receiving the P_Key index. To use + * this capability, an application must call the + * IB_USER_MAD_ENABLE_PKEY ioctl on the user MAD file handle before + * any other actions with the file handle. * @id - ID of agent MAD received with/to be sent with * @status - 0 on successful receive, ETIMEDOUT if no response * received (transaction ID in data[] will be set to TID of original @@ -70,6 +113,7 @@ * @traffic_class - Traffic class in GRH * @gid - Remote GID in GRH * @flow_label - Flow label in GRH + * @pkey_index - P_Key index */ struct ib_user_mad_hdr { __u32 id; @@ -88,6 +132,8 @@ struct ib_user_mad_hdr { __u8 traffic_class; __u8 gid[16]; __be32 flow_label; + __u16 pkey_index; + __u8 reserved[6]; }; /** @@ -101,6 +147,26 @@ struct ib_user_mad { __u64 data[0]; }; +/* + * Earlier versions of this interface definition declared the + * method_mask[] member as an array of __u32 but treated it as a + * bitmap made up of longs in the kernel. This ambiguity meant that + * 32-bit big-endian applications that can run on both 32-bit and + * 64-bit kernels had no consistent ABI to rely on, and 64-bit + * big-endian applications that treated method_mask as being made up + * of 32-bit words would have their bitmap misinterpreted. + * + * To clear up this confusion, we change the declaration of + * method_mask[] to use unsigned long and handle the conversion from + * 32-bit userspace to 64-bit kernel for big-endian systems in the + * compat_ioctl method. Unfortunately, to keep the structure layout + * the same, we need the method_mask[] array to be aligned only to 4 + * bytes even when long is 64 bits, which forces us into this ugly + * typedef. + */ +typedef unsigned long __attribute__((aligned(4))) packed_ulong; +#define IB_USER_MAD_LONGS_PER_METHOD_MASK (128 / (8 * sizeof (long))) + /** * ib_user_mad_reg_req - MAD registration request * @id - Set by the kernel; used to identify agent in future requests. @@ -119,7 +185,7 @@ struct ib_user_mad { */ struct ib_user_mad_reg_req { __u32 id; - __u32 method_mask[4]; + packed_ulong method_mask[IB_USER_MAD_LONGS_PER_METHOD_MASK]; __u8 qpn; __u8 mgmt_class; __u8 mgmt_class_version; @@ -134,4 +200,6 @@ struct ib_user_mad_reg_req { #define IB_USER_MAD_UNREGISTER_AGENT _IOW(IB_IOCTL_MAGIC, 2, __u32) +#define IB_USER_MAD_ENABLE_PKEY _IO(IB_IOCTL_MAGIC, 3) + #endif /* IB_USER_MAD_H */ diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index 0627a6aa282a..4bea182d7116 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -46,6 +46,8 @@ #include <linux/mm.h> #include <linux/dma-mapping.h> #include <linux/kref.h> +#include <linux/list.h> +#include <linux/rwsem.h> #include <asm/atomic.h> #include <asm/scatterlist.h> @@ -731,11 +733,6 @@ struct ib_udata { size_t outlen; }; -#define IB_UMEM_MAX_PAGE_CHUNK \ - ((PAGE_SIZE - offsetof(struct ib_umem_chunk, page_list)) / \ - ((void *) &((struct ib_umem_chunk *) 0)->page_list[1] - \ - (void *) &((struct ib_umem_chunk *) 0)->page_list[0])) - struct ib_pd { struct ib_device *device; struct ib_uobject *uobject; diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h index 2d6a7705eae7..010f876f41d8 100644 --- a/include/rdma/rdma_cm.h +++ b/include/rdma/rdma_cm.h @@ -314,4 +314,18 @@ int rdma_join_multicast(struct rdma_cm_id *id, struct sockaddr *addr, */ void rdma_leave_multicast(struct rdma_cm_id *id, struct sockaddr *addr); +/** + * rdma_set_service_type - Set the type of service associated with a + * connection identifier. + * @id: Communication identifier to associated with service type. + * @tos: Type of service. + * + * The type of service is interpretted as a differentiated service + * field (RFC 2474). The service type should be specified before + * performing route resolution, as existing communication on the + * connection identifier may be unaffected. The type of service + * requested may not be supported by the network to all destinations. + */ +void rdma_set_service_type(struct rdma_cm_id *id, int tos); + #endif /* RDMA_CM_H */ diff --git a/include/rdma/rdma_user_cm.h b/include/rdma/rdma_user_cm.h index f632b0c007c9..9749c1b34d00 100644 --- a/include/rdma/rdma_user_cm.h +++ b/include/rdma/rdma_user_cm.h @@ -212,4 +212,22 @@ struct rdma_ucm_event_resp { } param; }; +/* Option levels */ +enum { + RDMA_OPTION_ID = 0 +}; + +/* Option details */ +enum { + RDMA_OPTION_ID_TOS = 0 +}; + +struct rdma_ucm_set_option { + __u64 optval; + __u32 id; + __u32 level; + __u32 optname; + __u32 optlen; +}; + #endif /* RDMA_USER_CM_H */ diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index 3f631b08a1ab..b4b31132618b 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -205,11 +205,21 @@ struct iscsi_queue { }; struct iscsi_session { + /* + * Syncs up the scsi eh thread with the iscsi eh thread when sending + * task management functions. This must be taken before the session + * and recv lock. + */ + struct mutex eh_mutex; + /* iSCSI session-wide sequencing */ uint32_t cmdsn; uint32_t exp_cmdsn; uint32_t max_cmdsn; + /* This tracks the reqs queued into the initiator */ + uint32_t queued_cmdsn; + /* configuration */ int initial_r2t_en; unsigned max_r2t; diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h index 2e6bdc4e7a0a..8dda2d66b5b9 100644 --- a/include/scsi/libsas.h +++ b/include/scsi/libsas.h @@ -30,6 +30,7 @@ #include <linux/timer.h> #include <linux/pci.h> #include <scsi/sas.h> +#include <linux/libata.h> #include <linux/list.h> #include <asm/semaphore.h> #include <scsi/scsi_device.h> @@ -165,6 +166,13 @@ struct sata_device { u8 port_no; /* port number, if this is a PM (Port) */ struct list_head children; /* PM Ports if this is a PM */ + + struct ata_port *ap; + struct ata_host ata_host; + struct ata_taskfile tf; + u32 sstatus; + u32 serror; + u32 scontrol; }; /* ---------- Domain device ---------- */ @@ -340,7 +348,7 @@ struct sas_ha_struct { /* public: */ char *sas_ha_name; - struct pci_dev *pcidev; /* should be set */ + struct device *dev; /* should be set */ struct module *lldd_module; /* should be set */ u8 *sas_addr; /* must be set */ @@ -624,6 +632,7 @@ int sas_set_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates); int sas_phy_enable(struct sas_phy *phy, int enabled); int sas_phy_reset(struct sas_phy *phy, int hard_reset); +int sas_queue_up(struct sas_task *task); extern int sas_queuecommand(struct scsi_cmnd *, void (*scsi_done)(struct scsi_cmnd *)); extern int sas_target_alloc(struct scsi_target *); @@ -661,4 +670,10 @@ int __sas_task_abort(struct sas_task *); int sas_eh_device_reset_handler(struct scsi_cmnd *cmd); int sas_eh_bus_reset_handler(struct scsi_cmnd *cmd); +extern void sas_target_destroy(struct scsi_target *); +extern int sas_slave_alloc(struct scsi_device *); +extern int sas_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); + +extern int sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, + struct request *req); #endif /* _SASLIB_H_ */ diff --git a/include/scsi/sas_ata.h b/include/scsi/sas_ata.h new file mode 100644 index 000000000000..dd5edc915417 --- /dev/null +++ b/include/scsi/sas_ata.h @@ -0,0 +1,60 @@ +/* + * Support for SATA devices on Serial Attached SCSI (SAS) controllers + * + * Copyright (C) 2006 IBM Corporation + * + * Written by: Darrick J. Wong <djwong@us.ibm.com>, IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + * + */ + +#ifndef _SAS_ATA_H_ +#define _SAS_ATA_H_ + +#include <linux/libata.h> +#include <scsi/libsas.h> + +#ifdef CONFIG_SCSI_SAS_ATA + +static inline int dev_is_sata(struct domain_device *dev) +{ + return (dev->rphy->identify.target_port_protocols & SAS_PROTOCOL_SATA); +} + +int sas_ata_init_host_and_port(struct domain_device *found_dev, + struct scsi_target *starget); + +void sas_ata_task_abort(struct sas_task *task); + +#else + + +static inline int dev_is_sata(struct domain_device *dev) +{ + return 0; +} +int sas_ata_init_host_and_port(struct domain_device *found_dev, + struct scsi_target *starget) +{ + return 0; +} +void sas_ata_task_abort(struct sas_task *task) +{ +} +#endif + +#endif /* _SAS_ATA_H_ */ diff --git a/include/scsi/scsi_driver.h b/include/scsi/scsi_driver.h index 02e26c1672bf..3465f31a21c4 100644 --- a/include/scsi/scsi_driver.h +++ b/include/scsi/scsi_driver.h @@ -13,8 +13,6 @@ struct scsi_driver { int (*init_command)(struct scsi_cmnd *); void (*rescan)(struct device *); - int (*issue_flush)(struct device *, sector_t *); - int (*prepare_flush)(struct request_queue *, struct request *); }; #define to_scsi_driver(drv) \ container_of((drv), struct scsi_driver, gendrv) diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index ba07cf7c04ba..3b8a6a85c2f8 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -341,7 +341,7 @@ struct scsi_host_template { /* * Name of proc directory */ - char *proc_name; + const char *proc_name; /* * Used to store the procfs directory if a driver implements the diff --git a/include/scsi/scsi_transport_sas.h b/include/scsi/scsi_transport_sas.h index 9aedc19820b0..abdfd2e27dd7 100644 --- a/include/scsi/scsi_transport_sas.h +++ b/include/scsi/scsi_transport_sas.h @@ -7,7 +7,7 @@ struct scsi_transport_template; struct sas_rphy; - +struct request; enum sas_device_type { SAS_PHY_UNUSED, @@ -23,6 +23,12 @@ enum sas_protocol { SAS_PROTOCOL_SSP = 0x08, }; +static inline int sas_protocol_ata(enum sas_protocol proto) +{ + return ((proto & SAS_PROTOCOL_SATA) || + (proto & SAS_PROTOCOL_STP))? 1 : 0; +} + enum sas_linkrate { /* These Values are defined in the SAS standard */ SAS_LINK_RATE_UNKNOWN = 0, @@ -85,10 +91,12 @@ struct sas_phy { #define phy_to_shost(phy) \ dev_to_shost((phy)->dev.parent) +struct request_queue; struct sas_rphy { struct device dev; struct sas_identify identify; struct list_head list; + struct request_queue *q; u32 scsi_target_id; }; @@ -166,6 +174,7 @@ struct sas_function_template { int (*phy_reset)(struct sas_phy *, int); int (*phy_enable)(struct sas_phy *, int); int (*set_phy_speed)(struct sas_phy *, struct sas_phy_linkrates *); + int (*smp_handler)(struct Scsi_Host *, struct sas_rphy *, struct request *); }; diff --git a/include/scsi/sd.h b/include/scsi/sd.h index 5261488e1108..ce02ad1f5185 100644 --- a/include/scsi/sd.h +++ b/include/scsi/sd.h @@ -56,8 +56,6 @@ static int sd_suspend(struct device *dev, pm_message_t state); static int sd_resume(struct device *dev); static void sd_rescan(struct device *); static int sd_init_command(struct scsi_cmnd *); -static int sd_issue_flush(struct device *, sector_t *); -static void sd_prepare_flush(request_queue_t *, struct request *); static void sd_read_capacity(struct scsi_disk *sdkp, unsigned char *buffer); static void scsi_disk_release(struct class_device *cdev); static void sd_print_sense_hdr(struct scsi_disk *, struct scsi_sense_hdr *); diff --git a/include/sound/ak4xxx-adda.h b/include/sound/ak4xxx-adda.h index aa49dda4f410..fd0a6c46f497 100644 --- a/include/sound/ak4xxx-adda.h +++ b/include/sound/ak4xxx-adda.h @@ -43,6 +43,7 @@ struct snd_ak4xxx_ops { struct snd_akm4xxx_dac_channel { char *name; /* mixer volume name */ unsigned int num_channels; + char *switch_name; /* mixer switch*/ }; /* ADC labels and channels */ diff --git a/include/sound/cs46xx.h b/include/sound/cs46xx.h index 685928e6f65a..353910ce9755 100644 --- a/include/sound/cs46xx.h +++ b/include/sound/cs46xx.h @@ -1723,6 +1723,10 @@ struct snd_cs46xx { struct snd_cs46xx_pcm *playback_pcm; unsigned int play_ctl; #endif + +#ifdef CONFIG_PM + u32 *saved_regs; +#endif }; int snd_cs46xx_create(struct snd_card *card, diff --git a/include/sound/cs46xx_dsp_spos.h b/include/sound/cs46xx_dsp_spos.h index da934def31e9..d9da9e59cf37 100644 --- a/include/sound/cs46xx_dsp_spos.h +++ b/include/sound/cs46xx_dsp_spos.h @@ -107,6 +107,7 @@ struct dsp_scb_descriptor { char scb_name[DSP_MAX_SCB_NAME]; u32 address; int index; + u32 *data; struct dsp_scb_descriptor * sub_list_ptr; struct dsp_scb_descriptor * next_scb_ptr; @@ -127,6 +128,7 @@ struct dsp_task_descriptor { int size; u32 address; int index; + u32 *data; }; struct dsp_pcm_channel_descriptor { diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 23e45a4cf0e4..529d0a564367 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -1120,6 +1120,16 @@ /************************************************************************************************/ /* EMU1010m HANA Destinations */ /************************************************************************************************/ +/* 32-bit destinations of signal in the Hana FPGA. Destinations are either + * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture + * - 16 x EMU_DST_ALICE2_EMU32_X. + */ +/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */ +/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture. + * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on + * setup of mixer control for each destination - see emumixer.c - + * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[] + */ #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ @@ -1199,6 +1209,12 @@ /************************************************************************************************/ /* EMU1010m HANA Sources */ /************************************************************************************************/ +/* 32-bit sources of signal in the Hana FPGA. The sources are routed to + * destinations using mixer control for each destination - see emumixer.c + * Sources are either physical inputs of FPGA, + * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A + + * 16 x EMU_SRC_ALICE_EMU32B + */ #define EMU_SRC_SILENCE 0x0000 /* Silence */ #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ diff --git a/include/sound/sb.h b/include/sound/sb.h index 2dd5c8e5b4fe..3ad854b397d2 100644 --- a/include/sound/sb.h +++ b/include/sound/sb.h @@ -38,6 +38,7 @@ enum sb_hw_type { SB_HW_ALS100, /* Avance Logic ALS100 chip */ SB_HW_ALS4000, /* Avance Logic ALS4000 chip */ SB_HW_DT019X, /* Diamond Tech. DT-019X / Avance Logic ALS-007 */ + SB_HW_CS5530, /* Cyrix/NatSemi 5530 VSA1 */ }; #define SB_OPEN_PCM 0x01 diff --git a/include/sound/version.h b/include/sound/version.h index 8e5b2f0f5946..6bbcfefd2c38 100644 --- a/include/sound/version.h +++ b/include/sound/version.h @@ -1,3 +1,3 @@ /* include/version.h. Generated by alsa/ksync script. */ #define CONFIG_SND_VERSION "1.0.14" -#define CONFIG_SND_DATE " (Thu May 31 09:03:25 2007 UTC)" +#define CONFIG_SND_DATE " (Fri Jul 20 09:12:58 2007 UTC)" diff --git a/include/sound/wavefront_fx.h b/include/sound/wavefront_fx.h deleted file mode 100644 index cec92b141796..000000000000 --- a/include/sound/wavefront_fx.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __SOUND_WAVEFRONT_FX_H -#define __SOUND_WAVEFRONT_FX_H - -extern int snd_wavefront_fx_detect (snd_wavefront_t *); -extern void snd_wavefront_fx_ioctl (snd_synth_t *sdev, - unsigned int cmd, - unsigned long arg); - -#endif __SOUND_WAVEFRONT_FX_H diff --git a/include/video/tx3912.h b/include/video/tx3912.h deleted file mode 100644 index 6b6d006038c2..000000000000 --- a/include/video/tx3912.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * linux/include/video/tx3912.h - * - * Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - * Includes for TMPR3912/05 and PR31700 LCD controller registers - */ -#include <asm/tx3912.h> - -#define VidCtrl1 REG_AT(0x028) -#define VidCtrl2 REG_AT(0x02C) -#define VidCtrl3 REG_AT(0x030) -#define VidCtrl4 REG_AT(0x034) -#define VidCtrl5 REG_AT(0x038) -#define VidCtrl6 REG_AT(0x03C) -#define VidCtrl7 REG_AT(0x040) -#define VidCtrl8 REG_AT(0x044) -#define VidCtrl9 REG_AT(0x048) -#define VidCtrl10 REG_AT(0x04C) -#define VidCtrl11 REG_AT(0x050) -#define VidCtrl12 REG_AT(0x054) -#define VidCtrl13 REG_AT(0x058) -#define VidCtrl14 REG_AT(0x05C) - -/* Video Control 1 Register */ -#define LINECNT 0xffc00000 -#define LINECNT_SHIFT 22 -#define LOADDLY BIT(21) -#define BAUDVAL (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) -#define BAUDVAL_SHIFT 16 -#define VIDDONEVAL (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)) -#define VIDDONEVAL_SHIFT 9 -#define ENFREEZEFRAME BIT(8) -#define TX3912_VIDCTRL1_BITSEL_MASK 0x000000c0 -#define TX3912_VIDCTRL1_2BIT_GRAY 0x00000040 -#define TX3912_VIDCTRL1_4BIT_GRAY 0x00000080 -#define TX3912_VIDCTRL1_8BIT_COLOR 0x000000c0 -#define BITSEL_SHIFT 6 -#define DISPSPLIT BIT(5) -#define DISP8 BIT(4) -#define DFMODE BIT(3) -#define INVVID BIT(2) -#define DISPON BIT(1) -#define ENVID BIT(0) - -/* Video Control 2 Register */ -#define VIDRATE_MASK 0xffc00000 -#define VIDRATE_SHIFT 22 -#define HORZVAL_MASK 0x001ff000 -#define HORZVAL_SHIFT 12 -#define LINEVAL_MASK 0x000001ff - -/* Video Control 3 Register */ -#define TX3912_VIDCTRL3_VIDBANK_MASK 0xfff00000 -#define TX3912_VIDCTRL3_VIDBASEHI_MASK 0x000ffff0 - -/* Video Control 4 Register */ -#define TX3912_VIDCTRL4_VIDBASELO_MASK 0x000ffff0 diff --git a/include/xen/events.h b/include/xen/events.h new file mode 100644 index 000000000000..2bde54d29be5 --- /dev/null +++ b/include/xen/events.h @@ -0,0 +1,48 @@ +#ifndef _XEN_EVENTS_H +#define _XEN_EVENTS_H + +#include <linux/interrupt.h> + +#include <xen/interface/event_channel.h> +#include <asm/xen/hypercall.h> + +enum ipi_vector { + XEN_RESCHEDULE_VECTOR, + XEN_CALL_FUNCTION_VECTOR, + + XEN_NR_IPIS, +}; + +int bind_evtchn_to_irq(unsigned int evtchn); +int bind_evtchn_to_irqhandler(unsigned int evtchn, + irq_handler_t handler, + unsigned long irqflags, const char *devname, + void *dev_id); +int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, + irq_handler_t handler, + unsigned long irqflags, const char *devname, + void *dev_id); +int bind_ipi_to_irqhandler(enum ipi_vector ipi, + unsigned int cpu, + irq_handler_t handler, + unsigned long irqflags, + const char *devname, + void *dev_id); + +/* + * Common unbind function for all event sources. Takes IRQ to unbind from. + * Automatically closes the underlying event channel (even for bindings + * made with bind_evtchn_to_irqhandler()). + */ +void unbind_from_irqhandler(unsigned int irq, void *dev_id); + +void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector); + +static inline void notify_remote_via_evtchn(int port) +{ + struct evtchn_send send = { .port = port }; + (void)HYPERVISOR_event_channel_op(EVTCHNOP_send, &send); +} + +extern void notify_remote_via_irq(int irq); +#endif /* _XEN_EVENTS_H */ diff --git a/include/xen/features.h b/include/xen/features.h new file mode 100644 index 000000000000..27292d4d2a6a --- /dev/null +++ b/include/xen/features.h @@ -0,0 +1,23 @@ +/****************************************************************************** + * features.h + * + * Query the features reported by Xen. + * + * Copyright (c) 2006, Ian Campbell + */ + +#ifndef __XEN_FEATURES_H__ +#define __XEN_FEATURES_H__ + +#include <xen/interface/features.h> + +void xen_setup_features(void); + +extern u8 xen_features[XENFEAT_NR_SUBMAPS * 32]; + +static inline int xen_feature(int flag) +{ + return xen_features[flag]; +} + +#endif /* __ASM_XEN_FEATURES_H__ */ diff --git a/include/xen/grant_table.h b/include/xen/grant_table.h new file mode 100644 index 000000000000..761c83498e03 --- /dev/null +++ b/include/xen/grant_table.h @@ -0,0 +1,107 @@ +/****************************************************************************** + * grant_table.h + * + * Two sets of functionality: + * 1. Granting foreign access to our memory reservation. + * 2. Accessing others' memory reservations via grant references. + * (i.e., mechanisms for both sender and recipient of grant references) + * + * Copyright (c) 2004-2005, K A Fraser + * Copyright (c) 2005, Christopher Clark + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef __ASM_GNTTAB_H__ +#define __ASM_GNTTAB_H__ + +#include <asm/xen/hypervisor.h> +#include <xen/interface/grant_table.h> + +/* NR_GRANT_FRAMES must be less than or equal to that configured in Xen */ +#define NR_GRANT_FRAMES 4 + +struct gnttab_free_callback { + struct gnttab_free_callback *next; + void (*fn)(void *); + void *arg; + u16 count; +}; + +int gnttab_grant_foreign_access(domid_t domid, unsigned long frame, + int readonly); + +/* + * End access through the given grant reference, iff the grant entry is no + * longer in use. Return 1 if the grant entry was freed, 0 if it is still in + * use. + */ +int gnttab_end_foreign_access_ref(grant_ref_t ref, int readonly); + +/* + * Eventually end access through the given grant reference, and once that + * access has been ended, free the given page too. Access will be ended + * immediately iff the grant entry is not in use, otherwise it will happen + * some time later. page may be 0, in which case no freeing will occur. + */ +void gnttab_end_foreign_access(grant_ref_t ref, int readonly, + unsigned long page); + +int gnttab_grant_foreign_transfer(domid_t domid, unsigned long pfn); + +unsigned long gnttab_end_foreign_transfer_ref(grant_ref_t ref); +unsigned long gnttab_end_foreign_transfer(grant_ref_t ref); + +int gnttab_query_foreign_access(grant_ref_t ref); + +/* + * operations on reserved batches of grant references + */ +int gnttab_alloc_grant_references(u16 count, grant_ref_t *pprivate_head); + +void gnttab_free_grant_reference(grant_ref_t ref); + +void gnttab_free_grant_references(grant_ref_t head); + +int gnttab_empty_grant_references(const grant_ref_t *pprivate_head); + +int gnttab_claim_grant_reference(grant_ref_t *pprivate_head); + +void gnttab_release_grant_reference(grant_ref_t *private_head, + grant_ref_t release); + +void gnttab_request_free_callback(struct gnttab_free_callback *callback, + void (*fn)(void *), void *arg, u16 count); +void gnttab_cancel_free_callback(struct gnttab_free_callback *callback); + +void gnttab_grant_foreign_access_ref(grant_ref_t ref, domid_t domid, + unsigned long frame, int readonly); + +void gnttab_grant_foreign_transfer_ref(grant_ref_t, domid_t domid, + unsigned long pfn); + +#define gnttab_map_vaddr(map) ((void *)(map.host_virt_addr)) + +#endif /* __ASM_GNTTAB_H__ */ diff --git a/include/xen/hvc-console.h b/include/xen/hvc-console.h new file mode 100644 index 000000000000..21c0ecfd786d --- /dev/null +++ b/include/xen/hvc-console.h @@ -0,0 +1,6 @@ +#ifndef XEN_HVC_CONSOLE_H +#define XEN_HVC_CONSOLE_H + +extern struct console xenboot_console; + +#endif /* XEN_HVC_CONSOLE_H */ diff --git a/include/xen/interface/elfnote.h b/include/xen/interface/elfnote.h new file mode 100644 index 000000000000..a64d3df5bd95 --- /dev/null +++ b/include/xen/interface/elfnote.h @@ -0,0 +1,133 @@ +/****************************************************************************** + * elfnote.h + * + * Definitions used for the Xen ELF notes. + * + * Copyright (c) 2006, Ian Campbell, XenSource Ltd. + */ + +#ifndef __XEN_PUBLIC_ELFNOTE_H__ +#define __XEN_PUBLIC_ELFNOTE_H__ + +/* + * The notes should live in a SHT_NOTE segment and have "Xen" in the + * name field. + * + * Numeric types are either 4 or 8 bytes depending on the content of + * the desc field. + * + * LEGACY indicated the fields in the legacy __xen_guest string which + * this a note type replaces. + */ + +/* + * NAME=VALUE pair (string). + * + * LEGACY: FEATURES and PAE + */ +#define XEN_ELFNOTE_INFO 0 + +/* + * The virtual address of the entry point (numeric). + * + * LEGACY: VIRT_ENTRY + */ +#define XEN_ELFNOTE_ENTRY 1 + +/* The virtual address of the hypercall transfer page (numeric). + * + * LEGACY: HYPERCALL_PAGE. (n.b. legacy value is a physical page + * number not a virtual address) + */ +#define XEN_ELFNOTE_HYPERCALL_PAGE 2 + +/* The virtual address where the kernel image should be mapped (numeric). + * + * Defaults to 0. + * + * LEGACY: VIRT_BASE + */ +#define XEN_ELFNOTE_VIRT_BASE 3 + +/* + * The offset of the ELF paddr field from the acutal required + * psuedo-physical address (numeric). + * + * This is used to maintain backwards compatibility with older kernels + * which wrote __PAGE_OFFSET into that field. This field defaults to 0 + * if not present. + * + * LEGACY: ELF_PADDR_OFFSET. (n.b. legacy default is VIRT_BASE) + */ +#define XEN_ELFNOTE_PADDR_OFFSET 4 + +/* + * The version of Xen that we work with (string). + * + * LEGACY: XEN_VER + */ +#define XEN_ELFNOTE_XEN_VERSION 5 + +/* + * The name of the guest operating system (string). + * + * LEGACY: GUEST_OS + */ +#define XEN_ELFNOTE_GUEST_OS 6 + +/* + * The version of the guest operating system (string). + * + * LEGACY: GUEST_VER + */ +#define XEN_ELFNOTE_GUEST_VERSION 7 + +/* + * The loader type (string). + * + * LEGACY: LOADER + */ +#define XEN_ELFNOTE_LOADER 8 + +/* + * The kernel supports PAE (x86/32 only, string = "yes" or "no"). + * + * LEGACY: PAE (n.b. The legacy interface included a provision to + * indicate 'extended-cr3' support allowing L3 page tables to be + * placed above 4G. It is assumed that any kernel new enough to use + * these ELF notes will include this and therefore "yes" here is + * equivalent to "yes[entended-cr3]" in the __xen_guest interface. + */ +#define XEN_ELFNOTE_PAE_MODE 9 + +/* + * The features supported/required by this kernel (string). + * + * The string must consist of a list of feature names (as given in + * features.h, without the "XENFEAT_" prefix) separated by '|' + * characters. If a feature is required for the kernel to function + * then the feature name must be preceded by a '!' character. + * + * LEGACY: FEATURES + */ +#define XEN_ELFNOTE_FEATURES 10 + +/* + * The kernel requires the symbol table to be loaded (string = "yes" or "no") + * LEGACY: BSD_SYMTAB (n.b. The legacy treated the presence or absence + * of this string as a boolean flag rather than requiring "yes" or + * "no". + */ +#define XEN_ELFNOTE_BSD_SYMTAB 11 + +#endif /* __XEN_PUBLIC_ELFNOTE_H__ */ + +/* + * Local variables: + * mode: C + * c-set-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/include/xen/interface/event_channel.h b/include/xen/interface/event_channel.h new file mode 100644 index 000000000000..919b5bdcb2bd --- /dev/null +++ b/include/xen/interface/event_channel.h @@ -0,0 +1,195 @@ +/****************************************************************************** + * event_channel.h + * + * Event channels between domains. + * + * Copyright (c) 2003-2004, K A Fraser. + */ + +#ifndef __XEN_PUBLIC_EVENT_CHANNEL_H__ +#define __XEN_PUBLIC_EVENT_CHANNEL_H__ + +typedef uint32_t evtchn_port_t; +DEFINE_GUEST_HANDLE(evtchn_port_t); + +/* + * EVTCHNOP_alloc_unbound: Allocate a port in domain <dom> and mark as + * accepting interdomain bindings from domain <remote_dom>. A fresh port + * is allocated in <dom> and returned as <port>. + * NOTES: + * 1. If the caller is unprivileged then <dom> must be DOMID_SELF. + * 2. <rdom> may be DOMID_SELF, allowing loopback connections. + */ +#define EVTCHNOP_alloc_unbound 6 +struct evtchn_alloc_unbound { + /* IN parameters */ + domid_t dom, remote_dom; + /* OUT parameters */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_interdomain: Construct an interdomain event channel between + * the calling domain and <remote_dom>. <remote_dom,remote_port> must identify + * a port that is unbound and marked as accepting bindings from the calling + * domain. A fresh port is allocated in the calling domain and returned as + * <local_port>. + * NOTES: + * 2. <remote_dom> may be DOMID_SELF, allowing loopback connections. + */ +#define EVTCHNOP_bind_interdomain 0 +struct evtchn_bind_interdomain { + /* IN parameters. */ + domid_t remote_dom; + evtchn_port_t remote_port; + /* OUT parameters. */ + evtchn_port_t local_port; +}; + +/* + * EVTCHNOP_bind_virq: Bind a local event channel to VIRQ <irq> on specified + * vcpu. + * NOTES: + * 1. A virtual IRQ may be bound to at most one event channel per vcpu. + * 2. The allocated event channel is bound to the specified vcpu. The binding + * may not be changed. + */ +#define EVTCHNOP_bind_virq 1 +struct evtchn_bind_virq { + /* IN parameters. */ + uint32_t virq; + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_pirq: Bind a local event channel to PIRQ <irq>. + * NOTES: + * 1. A physical IRQ may be bound to at most one event channel per domain. + * 2. Only a sufficiently-privileged domain may bind to a physical IRQ. + */ +#define EVTCHNOP_bind_pirq 2 +struct evtchn_bind_pirq { + /* IN parameters. */ + uint32_t pirq; +#define BIND_PIRQ__WILL_SHARE 1 + uint32_t flags; /* BIND_PIRQ__* */ + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_bind_ipi: Bind a local event channel to receive events. + * NOTES: + * 1. The allocated event channel is bound to the specified vcpu. The binding + * may not be changed. + */ +#define EVTCHNOP_bind_ipi 7 +struct evtchn_bind_ipi { + uint32_t vcpu; + /* OUT parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_close: Close a local event channel <port>. If the channel is + * interdomain then the remote end is placed in the unbound state + * (EVTCHNSTAT_unbound), awaiting a new connection. + */ +#define EVTCHNOP_close 3 +struct evtchn_close { + /* IN parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_send: Send an event to the remote end of the channel whose local + * endpoint is <port>. + */ +#define EVTCHNOP_send 4 +struct evtchn_send { + /* IN parameters. */ + evtchn_port_t port; +}; + +/* + * EVTCHNOP_status: Get the current status of the communication channel which + * has an endpoint at <dom, port>. + * NOTES: + * 1. <dom> may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may obtain the status of an event + * channel for which <dom> is not DOMID_SELF. + */ +#define EVTCHNOP_status 5 +struct evtchn_status { + /* IN parameters */ + domid_t dom; + evtchn_port_t port; + /* OUT parameters */ +#define EVTCHNSTAT_closed 0 /* Channel is not in use. */ +#define EVTCHNSTAT_unbound 1 /* Channel is waiting interdom connection.*/ +#define EVTCHNSTAT_interdomain 2 /* Channel is connected to remote domain. */ +#define EVTCHNSTAT_pirq 3 /* Channel is bound to a phys IRQ line. */ +#define EVTCHNSTAT_virq 4 /* Channel is bound to a virtual IRQ line */ +#define EVTCHNSTAT_ipi 5 /* Channel is bound to a virtual IPI line */ + uint32_t status; + uint32_t vcpu; /* VCPU to which this channel is bound. */ + union { + struct { + domid_t dom; + } unbound; /* EVTCHNSTAT_unbound */ + struct { + domid_t dom; + evtchn_port_t port; + } interdomain; /* EVTCHNSTAT_interdomain */ + uint32_t pirq; /* EVTCHNSTAT_pirq */ + uint32_t virq; /* EVTCHNSTAT_virq */ + } u; +}; + +/* + * EVTCHNOP_bind_vcpu: Specify which vcpu a channel should notify when an + * event is pending. + * NOTES: + * 1. IPI- and VIRQ-bound channels always notify the vcpu that initialised + * the binding. This binding cannot be changed. + * 2. All other channels notify vcpu0 by default. This default is set when + * the channel is allocated (a port that is freed and subsequently reused + * has its binding reset to vcpu0). + */ +#define EVTCHNOP_bind_vcpu 8 +struct evtchn_bind_vcpu { + /* IN parameters. */ + evtchn_port_t port; + uint32_t vcpu; +}; + +/* + * EVTCHNOP_unmask: Unmask the specified local event-channel port and deliver + * a notification to the appropriate VCPU if an event is pending. + */ +#define EVTCHNOP_unmask 9 +struct evtchn_unmask { + /* IN parameters. */ + evtchn_port_t port; +}; + +struct evtchn_op { + uint32_t cmd; /* EVTCHNOP_* */ + union { + struct evtchn_alloc_unbound alloc_unbound; + struct evtchn_bind_interdomain bind_interdomain; + struct evtchn_bind_virq bind_virq; + struct evtchn_bind_pirq bind_pirq; + struct evtchn_bind_ipi bind_ipi; + struct evtchn_close close; + struct evtchn_send send; + struct evtchn_status status; + struct evtchn_bind_vcpu bind_vcpu; + struct evtchn_unmask unmask; + } u; +}; +DEFINE_GUEST_HANDLE_STRUCT(evtchn_op); + +#endif /* __XEN_PUBLIC_EVENT_CHANNEL_H__ */ diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h new file mode 100644 index 000000000000..d73228d16488 --- /dev/null +++ b/include/xen/interface/features.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * features.h + * + * Feature flags, reported by XENVER_get_features. + * + * Copyright (c) 2006, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_FEATURES_H__ +#define __XEN_PUBLIC_FEATURES_H__ + +/* + * If set, the guest does not need to write-protect its pagetables, and can + * update them via direct writes. + */ +#define XENFEAT_writable_page_tables 0 + +/* + * If set, the guest does not need to write-protect its segment descriptor + * tables, and can update them via direct writes. + */ +#define XENFEAT_writable_descriptor_tables 1 + +/* + * If set, translation between the guest's 'pseudo-physical' address space + * and the host's machine address space are handled by the hypervisor. In this + * mode the guest does not need to perform phys-to/from-machine translations + * when performing page table operations. + */ +#define XENFEAT_auto_translated_physmap 2 + +/* If set, the guest is running in supervisor mode (e.g., x86 ring 0). */ +#define XENFEAT_supervisor_mode_kernel 3 + +/* + * If set, the guest does not need to allocate x86 PAE page directories + * below 4GB. This flag is usually implied by auto_translated_physmap. + */ +#define XENFEAT_pae_pgdir_above_4gb 4 + +#define XENFEAT_NR_SUBMAPS 1 + +#endif /* __XEN_PUBLIC_FEATURES_H__ */ diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h new file mode 100644 index 000000000000..219049802cf2 --- /dev/null +++ b/include/xen/interface/grant_table.h @@ -0,0 +1,375 @@ +/****************************************************************************** + * grant_table.h + * + * Interface for granting foreign access to page frames, and receiving + * page-ownership transfers. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_GRANT_TABLE_H__ +#define __XEN_PUBLIC_GRANT_TABLE_H__ + + +/*********************************** + * GRANT TABLE REPRESENTATION + */ + +/* Some rough guidelines on accessing and updating grant-table entries + * in a concurrency-safe manner. For more information, Linux contains a + * reference implementation for guest OSes (arch/xen/kernel/grant_table.c). + * + * NB. WMB is a no-op on current-generation x86 processors. However, a + * compiler barrier will still be required. + * + * Introducing a valid entry into the grant table: + * 1. Write ent->domid. + * 2. Write ent->frame: + * GTF_permit_access: Frame to which access is permitted. + * GTF_accept_transfer: Pseudo-phys frame slot being filled by new + * frame, or zero if none. + * 3. Write memory barrier (WMB). + * 4. Write ent->flags, inc. valid type. + * + * Invalidating an unused GTF_permit_access entry: + * 1. flags = ent->flags. + * 2. Observe that !(flags & (GTF_reading|GTF_writing)). + * 3. Check result of SMP-safe CMPXCHG(&ent->flags, flags, 0). + * NB. No need for WMB as reuse of entry is control-dependent on success of + * step 3, and all architectures guarantee ordering of ctrl-dep writes. + * + * Invalidating an in-use GTF_permit_access entry: + * This cannot be done directly. Request assistance from the domain controller + * which can set a timeout on the use of a grant entry and take necessary + * action. (NB. This is not yet implemented!). + * + * Invalidating an unused GTF_accept_transfer entry: + * 1. flags = ent->flags. + * 2. Observe that !(flags & GTF_transfer_committed). [*] + * 3. Check result of SMP-safe CMPXCHG(&ent->flags, flags, 0). + * NB. No need for WMB as reuse of entry is control-dependent on success of + * step 3, and all architectures guarantee ordering of ctrl-dep writes. + * [*] If GTF_transfer_committed is set then the grant entry is 'committed'. + * The guest must /not/ modify the grant entry until the address of the + * transferred frame is written. It is safe for the guest to spin waiting + * for this to occur (detect by observing GTF_transfer_completed in + * ent->flags). + * + * Invalidating a committed GTF_accept_transfer entry: + * 1. Wait for (ent->flags & GTF_transfer_completed). + * + * Changing a GTF_permit_access from writable to read-only: + * Use SMP-safe CMPXCHG to set GTF_readonly, while checking !GTF_writing. + * + * Changing a GTF_permit_access from read-only to writable: + * Use SMP-safe bit-setting instruction. + */ + +/* + * A grant table comprises a packed array of grant entries in one or more + * page frames shared between Xen and a guest. + * [XEN]: This field is written by Xen and read by the sharing guest. + * [GST]: This field is written by the guest and read by Xen. + */ +struct grant_entry { + /* GTF_xxx: various type and flag information. [XEN,GST] */ + uint16_t flags; + /* The domain being granted foreign privileges. [GST] */ + domid_t domid; + /* + * GTF_permit_access: Frame that @domid is allowed to map and access. [GST] + * GTF_accept_transfer: Frame whose ownership transferred by @domid. [XEN] + */ + uint32_t frame; +}; + +/* + * Type of grant entry. + * GTF_invalid: This grant entry grants no privileges. + * GTF_permit_access: Allow @domid to map/access @frame. + * GTF_accept_transfer: Allow @domid to transfer ownership of one page frame + * to this guest. Xen writes the page number to @frame. + */ +#define GTF_invalid (0U<<0) +#define GTF_permit_access (1U<<0) +#define GTF_accept_transfer (2U<<0) +#define GTF_type_mask (3U<<0) + +/* + * Subflags for GTF_permit_access. + * GTF_readonly: Restrict @domid to read-only mappings and accesses. [GST] + * GTF_reading: Grant entry is currently mapped for reading by @domid. [XEN] + * GTF_writing: Grant entry is currently mapped for writing by @domid. [XEN] + */ +#define _GTF_readonly (2) +#define GTF_readonly (1U<<_GTF_readonly) +#define _GTF_reading (3) +#define GTF_reading (1U<<_GTF_reading) +#define _GTF_writing (4) +#define GTF_writing (1U<<_GTF_writing) + +/* + * Subflags for GTF_accept_transfer: + * GTF_transfer_committed: Xen sets this flag to indicate that it is committed + * to transferring ownership of a page frame. When a guest sees this flag + * it must /not/ modify the grant entry until GTF_transfer_completed is + * set by Xen. + * GTF_transfer_completed: It is safe for the guest to spin-wait on this flag + * after reading GTF_transfer_committed. Xen will always write the frame + * address, followed by ORing this flag, in a timely manner. + */ +#define _GTF_transfer_committed (2) +#define GTF_transfer_committed (1U<<_GTF_transfer_committed) +#define _GTF_transfer_completed (3) +#define GTF_transfer_completed (1U<<_GTF_transfer_completed) + + +/*********************************** + * GRANT TABLE QUERIES AND USES + */ + +/* + * Reference to a grant entry in a specified domain's grant table. + */ +typedef uint32_t grant_ref_t; + +/* + * Handle to track a mapping created via a grant reference. + */ +typedef uint32_t grant_handle_t; + +/* + * GNTTABOP_map_grant_ref: Map the grant entry (<dom>,<ref>) for access + * by devices and/or host CPUs. If successful, <handle> is a tracking number + * that must be presented later to destroy the mapping(s). On error, <handle> + * is a negative status code. + * NOTES: + * 1. If GNTMAP_device_map is specified then <dev_bus_addr> is the address + * via which I/O devices may access the granted frame. + * 2. If GNTMAP_host_map is specified then a mapping will be added at + * either a host virtual address in the current address space, or at + * a PTE at the specified machine address. The type of mapping to + * perform is selected through the GNTMAP_contains_pte flag, and the + * address is specified in <host_addr>. + * 3. Mappings should only be destroyed via GNTTABOP_unmap_grant_ref. If a + * host mapping is destroyed by other means then it is *NOT* guaranteed + * to be accounted to the correct grant reference! + */ +#define GNTTABOP_map_grant_ref 0 +struct gnttab_map_grant_ref { + /* IN parameters. */ + uint64_t host_addr; + uint32_t flags; /* GNTMAP_* */ + grant_ref_t ref; + domid_t dom; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ + grant_handle_t handle; + uint64_t dev_bus_addr; +}; + +/* + * GNTTABOP_unmap_grant_ref: Destroy one or more grant-reference mappings + * tracked by <handle>. If <host_addr> or <dev_bus_addr> is zero, that + * field is ignored. If non-zero, they must refer to a device/host mapping + * that is tracked by <handle> + * NOTES: + * 1. The call may fail in an undefined manner if either mapping is not + * tracked by <handle>. + * 3. After executing a batch of unmaps, it is guaranteed that no stale + * mappings will remain in the device or host TLBs. + */ +#define GNTTABOP_unmap_grant_ref 1 +struct gnttab_unmap_grant_ref { + /* IN parameters. */ + uint64_t host_addr; + uint64_t dev_bus_addr; + grant_handle_t handle; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ +}; + +/* + * GNTTABOP_setup_table: Set up a grant table for <dom> comprising at least + * <nr_frames> pages. The frame addresses are written to the <frame_list>. + * Only <nr_frames> addresses are written, even if the table is larger. + * NOTES: + * 1. <dom> may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify <dom> != DOMID_SELF. + * 3. Xen may not support more than a single grant-table page per domain. + */ +#define GNTTABOP_setup_table 2 +struct gnttab_setup_table { + /* IN parameters. */ + domid_t dom; + uint32_t nr_frames; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ + ulong *frame_list; +}; + +/* + * GNTTABOP_dump_table: Dump the contents of the grant table to the + * xen console. Debugging use only. + */ +#define GNTTABOP_dump_table 3 +struct gnttab_dump_table { + /* IN parameters. */ + domid_t dom; + /* OUT parameters. */ + int16_t status; /* GNTST_* */ +}; + +/* + * GNTTABOP_transfer_grant_ref: Transfer <frame> to a foreign domain. The + * foreign domain has previously registered its interest in the transfer via + * <domid, ref>. + * + * Note that, even if the transfer fails, the specified page no longer belongs + * to the calling domain *unless* the error is GNTST_bad_page. + */ +#define GNTTABOP_transfer 4 +struct gnttab_transfer { + /* IN parameters. */ + unsigned long mfn; + domid_t domid; + grant_ref_t ref; + /* OUT parameters. */ + int16_t status; +}; + + +/* + * GNTTABOP_copy: Hypervisor based copy + * source and destinations can be eithers MFNs or, for foreign domains, + * grant references. the foreign domain has to grant read/write access + * in its grant table. + * + * The flags specify what type source and destinations are (either MFN + * or grant reference). + * + * Note that this can also be used to copy data between two domains + * via a third party if the source and destination domains had previously + * grant appropriate access to their pages to the third party. + * + * source_offset specifies an offset in the source frame, dest_offset + * the offset in the target frame and len specifies the number of + * bytes to be copied. + */ + +#define _GNTCOPY_source_gref (0) +#define GNTCOPY_source_gref (1<<_GNTCOPY_source_gref) +#define _GNTCOPY_dest_gref (1) +#define GNTCOPY_dest_gref (1<<_GNTCOPY_dest_gref) + +#define GNTTABOP_copy 5 +struct gnttab_copy { + /* IN parameters. */ + struct { + union { + grant_ref_t ref; + unsigned long gmfn; + } u; + domid_t domid; + uint16_t offset; + } source, dest; + uint16_t len; + uint16_t flags; /* GNTCOPY_* */ + /* OUT parameters. */ + int16_t status; +}; + +/* + * GNTTABOP_query_size: Query the current and maximum sizes of the shared + * grant table. + * NOTES: + * 1. <dom> may be specified as DOMID_SELF. + * 2. Only a sufficiently-privileged domain may specify <dom> != DOMID_SELF. + */ +#define GNTTABOP_query_size 6 +struct gnttab_query_size { + /* IN parameters. */ + domid_t dom; + /* OUT parameters. */ + uint32_t nr_frames; + uint32_t max_nr_frames; + int16_t status; /* GNTST_* */ +}; + + +/* + * Bitfield values for update_pin_status.flags. + */ + /* Map the grant entry for access by I/O devices. */ +#define _GNTMAP_device_map (0) +#define GNTMAP_device_map (1<<_GNTMAP_device_map) + /* Map the grant entry for access by host CPUs. */ +#define _GNTMAP_host_map (1) +#define GNTMAP_host_map (1<<_GNTMAP_host_map) + /* Accesses to the granted frame will be restricted to read-only access. */ +#define _GNTMAP_readonly (2) +#define GNTMAP_readonly (1<<_GNTMAP_readonly) + /* + * GNTMAP_host_map subflag: + * 0 => The host mapping is usable only by the guest OS. + * 1 => The host mapping is usable by guest OS + current application. + */ +#define _GNTMAP_application_map (3) +#define GNTMAP_application_map (1<<_GNTMAP_application_map) + + /* + * GNTMAP_contains_pte subflag: + * 0 => This map request contains a host virtual address. + * 1 => This map request contains the machine addess of the PTE to update. + */ +#define _GNTMAP_contains_pte (4) +#define GNTMAP_contains_pte (1<<_GNTMAP_contains_pte) + +/* + * Values for error status returns. All errors are -ve. + */ +#define GNTST_okay (0) /* Normal return. */ +#define GNTST_general_error (-1) /* General undefined error. */ +#define GNTST_bad_domain (-2) /* Unrecognsed domain id. */ +#define GNTST_bad_gntref (-3) /* Unrecognised or inappropriate gntref. */ +#define GNTST_bad_handle (-4) /* Unrecognised or inappropriate handle. */ +#define GNTST_bad_virt_addr (-5) /* Inappropriate virtual address to map. */ +#define GNTST_bad_dev_addr (-6) /* Inappropriate device address to unmap.*/ +#define GNTST_no_device_space (-7) /* Out of space in I/O MMU. */ +#define GNTST_permission_denied (-8) /* Not enough privilege for operation. */ +#define GNTST_bad_page (-9) /* Specified page was invalid for op. */ +#define GNTST_bad_copy_arg (-10) /* copy arguments cross page boundary */ + +#define GNTTABOP_error_msgs { \ + "okay", \ + "undefined error", \ + "unrecognised domain id", \ + "invalid grant reference", \ + "invalid mapping handle", \ + "invalid virtual address", \ + "invalid device address", \ + "no spare translation slot in the I/O MMU", \ + "permission denied", \ + "bad page", \ + "copy arguments cross page boundary" \ +} + +#endif /* __XEN_PUBLIC_GRANT_TABLE_H__ */ diff --git a/include/xen/interface/io/blkif.h b/include/xen/interface/io/blkif.h new file mode 100644 index 000000000000..c2d1fa4dc1ee --- /dev/null +++ b/include/xen/interface/io/blkif.h @@ -0,0 +1,94 @@ +/****************************************************************************** + * blkif.h + * + * Unified block-device I/O interface for Xen guest OSes. + * + * Copyright (c) 2003-2004, Keir Fraser + */ + +#ifndef __XEN_PUBLIC_IO_BLKIF_H__ +#define __XEN_PUBLIC_IO_BLKIF_H__ + +#include "ring.h" +#include "../grant_table.h" + +/* + * Front->back notifications: When enqueuing a new request, sending a + * notification can be made conditional on req_event (i.e., the generic + * hold-off mechanism provided by the ring macros). Backends must set + * req_event appropriately (e.g., using RING_FINAL_CHECK_FOR_REQUESTS()). + * + * Back->front notifications: When enqueuing a new response, sending a + * notification can be made conditional on rsp_event (i.e., the generic + * hold-off mechanism provided by the ring macros). Frontends must set + * rsp_event appropriately (e.g., using RING_FINAL_CHECK_FOR_RESPONSES()). + */ + +typedef uint16_t blkif_vdev_t; +typedef uint64_t blkif_sector_t; + +/* + * REQUEST CODES. + */ +#define BLKIF_OP_READ 0 +#define BLKIF_OP_WRITE 1 +/* + * Recognised only if "feature-barrier" is present in backend xenbus info. + * The "feature_barrier" node contains a boolean indicating whether barrier + * requests are likely to succeed or fail. Either way, a barrier request + * may fail at any time with BLKIF_RSP_EOPNOTSUPP if it is unsupported by + * the underlying block-device hardware. The boolean simply indicates whether + * or not it is worthwhile for the frontend to attempt barrier requests. + * If a backend does not recognise BLKIF_OP_WRITE_BARRIER, it should *not* + * create the "feature-barrier" node! + */ +#define BLKIF_OP_WRITE_BARRIER 2 + +/* + * Maximum scatter/gather segments per request. + * This is carefully chosen so that sizeof(struct blkif_ring) <= PAGE_SIZE. + * NB. This could be 12 if the ring indexes weren't stored in the same page. + */ +#define BLKIF_MAX_SEGMENTS_PER_REQUEST 11 + +struct blkif_request { + uint8_t operation; /* BLKIF_OP_??? */ + uint8_t nr_segments; /* number of segments */ + blkif_vdev_t handle; /* only for read/write requests */ + uint64_t id; /* private guest value, echoed in resp */ + blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */ + struct blkif_request_segment { + grant_ref_t gref; /* reference to I/O buffer frame */ + /* @first_sect: first sector in frame to transfer (inclusive). */ + /* @last_sect: last sector in frame to transfer (inclusive). */ + uint8_t first_sect, last_sect; + } seg[BLKIF_MAX_SEGMENTS_PER_REQUEST]; +}; + +struct blkif_response { + uint64_t id; /* copied from request */ + uint8_t operation; /* copied from request */ + int16_t status; /* BLKIF_RSP_??? */ +}; + +/* + * STATUS RETURN CODES. + */ + /* Operation not supported (only happens on barrier writes). */ +#define BLKIF_RSP_EOPNOTSUPP -2 + /* Operation failed for some unspecified reason (-EIO). */ +#define BLKIF_RSP_ERROR -1 + /* Operation completed successfully. */ +#define BLKIF_RSP_OKAY 0 + +/* + * Generate blkif ring structures and types. + */ + +DEFINE_RING_TYPES(blkif, struct blkif_request, struct blkif_response); + +#define VDISK_CDROM 0x1 +#define VDISK_REMOVABLE 0x2 +#define VDISK_READONLY 0x4 + +#endif /* __XEN_PUBLIC_IO_BLKIF_H__ */ diff --git a/include/xen/interface/io/console.h b/include/xen/interface/io/console.h new file mode 100644 index 000000000000..e563de70f784 --- /dev/null +++ b/include/xen/interface/io/console.h @@ -0,0 +1,23 @@ +/****************************************************************************** + * console.h + * + * Console I/O interface for Xen guest OSes. + * + * Copyright (c) 2005, Keir Fraser + */ + +#ifndef __XEN_PUBLIC_IO_CONSOLE_H__ +#define __XEN_PUBLIC_IO_CONSOLE_H__ + +typedef uint32_t XENCONS_RING_IDX; + +#define MASK_XENCONS_IDX(idx, ring) ((idx) & (sizeof(ring)-1)) + +struct xencons_interface { + char in[1024]; + char out[2048]; + XENCONS_RING_IDX in_cons, in_prod; + XENCONS_RING_IDX out_cons, out_prod; +}; + +#endif /* __XEN_PUBLIC_IO_CONSOLE_H__ */ diff --git a/include/xen/interface/io/netif.h b/include/xen/interface/io/netif.h new file mode 100644 index 000000000000..518481c95f18 --- /dev/null +++ b/include/xen/interface/io/netif.h @@ -0,0 +1,158 @@ +/****************************************************************************** + * netif.h + * + * Unified network-device I/O interface for Xen guest OSes. + * + * Copyright (c) 2003-2004, Keir Fraser + */ + +#ifndef __XEN_PUBLIC_IO_NETIF_H__ +#define __XEN_PUBLIC_IO_NETIF_H__ + +#include "ring.h" +#include "../grant_table.h" + +/* + * Notifications after enqueuing any type of message should be conditional on + * the appropriate req_event or rsp_event field in the shared ring. + * If the client sends notification for rx requests then it should specify + * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume + * that it cannot safely queue packets (as it may not be kicked to send them). + */ + +/* + * This is the 'wire' format for packets: + * Request 1: netif_tx_request -- NETTXF_* (any flags) + * [Request 2: netif_tx_extra] (only if request 1 has NETTXF_extra_info) + * [Request 3: netif_tx_extra] (only if request 2 has XEN_NETIF_EXTRA_MORE) + * Request 4: netif_tx_request -- NETTXF_more_data + * Request 5: netif_tx_request -- NETTXF_more_data + * ... + * Request N: netif_tx_request -- 0 + */ + +/* Protocol checksum field is blank in the packet (hardware offload)? */ +#define _NETTXF_csum_blank (0) +#define NETTXF_csum_blank (1U<<_NETTXF_csum_blank) + +/* Packet data has been validated against protocol checksum. */ +#define _NETTXF_data_validated (1) +#define NETTXF_data_validated (1U<<_NETTXF_data_validated) + +/* Packet continues in the next request descriptor. */ +#define _NETTXF_more_data (2) +#define NETTXF_more_data (1U<<_NETTXF_more_data) + +/* Packet to be followed by extra descriptor(s). */ +#define _NETTXF_extra_info (3) +#define NETTXF_extra_info (1U<<_NETTXF_extra_info) + +struct xen_netif_tx_request { + grant_ref_t gref; /* Reference to buffer page */ + uint16_t offset; /* Offset within buffer page */ + uint16_t flags; /* NETTXF_* */ + uint16_t id; /* Echoed in response message. */ + uint16_t size; /* Packet size in bytes. */ +}; + +/* Types of netif_extra_info descriptors. */ +#define XEN_NETIF_EXTRA_TYPE_NONE (0) /* Never used - invalid */ +#define XEN_NETIF_EXTRA_TYPE_GSO (1) /* u.gso */ +#define XEN_NETIF_EXTRA_TYPE_MAX (2) + +/* netif_extra_info flags. */ +#define _XEN_NETIF_EXTRA_FLAG_MORE (0) +#define XEN_NETIF_EXTRA_FLAG_MORE (1U<<_XEN_NETIF_EXTRA_FLAG_MORE) + +/* GSO types - only TCPv4 currently supported. */ +#define XEN_NETIF_GSO_TYPE_TCPV4 (1) + +/* + * This structure needs to fit within both netif_tx_request and + * netif_rx_response for compatibility. + */ +struct xen_netif_extra_info { + uint8_t type; /* XEN_NETIF_EXTRA_TYPE_* */ + uint8_t flags; /* XEN_NETIF_EXTRA_FLAG_* */ + + union { + struct { + /* + * Maximum payload size of each segment. For + * example, for TCP this is just the path MSS. + */ + uint16_t size; + + /* + * GSO type. This determines the protocol of + * the packet and any extra features required + * to segment the packet properly. + */ + uint8_t type; /* XEN_NETIF_GSO_TYPE_* */ + + /* Future expansion. */ + uint8_t pad; + + /* + * GSO features. This specifies any extra GSO + * features required to process this packet, + * such as ECN support for TCPv4. + */ + uint16_t features; /* XEN_NETIF_GSO_FEAT_* */ + } gso; + + uint16_t pad[3]; + } u; +}; + +struct xen_netif_tx_response { + uint16_t id; + int16_t status; /* NETIF_RSP_* */ +}; + +struct xen_netif_rx_request { + uint16_t id; /* Echoed in response message. */ + grant_ref_t gref; /* Reference to incoming granted frame */ +}; + +/* Packet data has been validated against protocol checksum. */ +#define _NETRXF_data_validated (0) +#define NETRXF_data_validated (1U<<_NETRXF_data_validated) + +/* Protocol checksum field is blank in the packet (hardware offload)? */ +#define _NETRXF_csum_blank (1) +#define NETRXF_csum_blank (1U<<_NETRXF_csum_blank) + +/* Packet continues in the next request descriptor. */ +#define _NETRXF_more_data (2) +#define NETRXF_more_data (1U<<_NETRXF_more_data) + +/* Packet to be followed by extra descriptor(s). */ +#define _NETRXF_extra_info (3) +#define NETRXF_extra_info (1U<<_NETRXF_extra_info) + +struct xen_netif_rx_response { + uint16_t id; + uint16_t offset; /* Offset in page of start of received packet */ + uint16_t flags; /* NETRXF_* */ + int16_t status; /* -ve: BLKIF_RSP_* ; +ve: Rx'ed pkt size. */ +}; + +/* + * Generate netif ring structures and types. + */ + +DEFINE_RING_TYPES(xen_netif_tx, + struct xen_netif_tx_request, + struct xen_netif_tx_response); +DEFINE_RING_TYPES(xen_netif_rx, + struct xen_netif_rx_request, + struct xen_netif_rx_response); + +#define NETIF_RSP_DROPPED -2 +#define NETIF_RSP_ERROR -1 +#define NETIF_RSP_OKAY 0 +/* No response: used for auxiliary requests (e.g., netif_tx_extra). */ +#define NETIF_RSP_NULL 1 + +#endif diff --git a/include/xen/interface/io/ring.h b/include/xen/interface/io/ring.h new file mode 100644 index 000000000000..e8cbf431c8cc --- /dev/null +++ b/include/xen/interface/io/ring.h @@ -0,0 +1,260 @@ +/****************************************************************************** + * ring.h + * + * Shared producer-consumer ring macros. + * + * Tim Deegan and Andrew Warfield November 2004. + */ + +#ifndef __XEN_PUBLIC_IO_RING_H__ +#define __XEN_PUBLIC_IO_RING_H__ + +typedef unsigned int RING_IDX; + +/* Round a 32-bit unsigned constant down to the nearest power of two. */ +#define __RD2(_x) (((_x) & 0x00000002) ? 0x2 : ((_x) & 0x1)) +#define __RD4(_x) (((_x) & 0x0000000c) ? __RD2((_x)>>2)<<2 : __RD2(_x)) +#define __RD8(_x) (((_x) & 0x000000f0) ? __RD4((_x)>>4)<<4 : __RD4(_x)) +#define __RD16(_x) (((_x) & 0x0000ff00) ? __RD8((_x)>>8)<<8 : __RD8(_x)) +#define __RD32(_x) (((_x) & 0xffff0000) ? __RD16((_x)>>16)<<16 : __RD16(_x)) + +/* + * Calculate size of a shared ring, given the total available space for the + * ring and indexes (_sz), and the name tag of the request/response structure. + * A ring contains as many entries as will fit, rounded down to the nearest + * power of two (so we can mask with (size-1) to loop around). + */ +#define __RING_SIZE(_s, _sz) \ + (__RD32(((_sz) - (long)&(_s)->ring + (long)(_s)) / sizeof((_s)->ring[0]))) + +/* + * Macros to make the correct C datatypes for a new kind of ring. + * + * To make a new ring datatype, you need to have two message structures, + * let's say struct request, and struct response already defined. + * + * In a header where you want the ring datatype declared, you then do: + * + * DEFINE_RING_TYPES(mytag, struct request, struct response); + * + * These expand out to give you a set of types, as you can see below. + * The most important of these are: + * + * struct mytag_sring - The shared ring. + * struct mytag_front_ring - The 'front' half of the ring. + * struct mytag_back_ring - The 'back' half of the ring. + * + * To initialize a ring in your code you need to know the location and size + * of the shared memory area (PAGE_SIZE, for instance). To initialise + * the front half: + * + * struct mytag_front_ring front_ring; + * SHARED_RING_INIT((struct mytag_sring *)shared_page); + * FRONT_RING_INIT(&front_ring, (struct mytag_sring *)shared_page, + * PAGE_SIZE); + * + * Initializing the back follows similarly (note that only the front + * initializes the shared ring): + * + * struct mytag_back_ring back_ring; + * BACK_RING_INIT(&back_ring, (struct mytag_sring *)shared_page, + * PAGE_SIZE); + */ + +#define DEFINE_RING_TYPES(__name, __req_t, __rsp_t) \ + \ +/* Shared ring entry */ \ +union __name##_sring_entry { \ + __req_t req; \ + __rsp_t rsp; \ +}; \ + \ +/* Shared ring page */ \ +struct __name##_sring { \ + RING_IDX req_prod, req_event; \ + RING_IDX rsp_prod, rsp_event; \ + uint8_t pad[48]; \ + union __name##_sring_entry ring[1]; /* variable-length */ \ +}; \ + \ +/* "Front" end's private variables */ \ +struct __name##_front_ring { \ + RING_IDX req_prod_pvt; \ + RING_IDX rsp_cons; \ + unsigned int nr_ents; \ + struct __name##_sring *sring; \ +}; \ + \ +/* "Back" end's private variables */ \ +struct __name##_back_ring { \ + RING_IDX rsp_prod_pvt; \ + RING_IDX req_cons; \ + unsigned int nr_ents; \ + struct __name##_sring *sring; \ +}; + +/* + * Macros for manipulating rings. + * + * FRONT_RING_whatever works on the "front end" of a ring: here + * requests are pushed on to the ring and responses taken off it. + * + * BACK_RING_whatever works on the "back end" of a ring: here + * requests are taken off the ring and responses put on. + * + * N.B. these macros do NO INTERLOCKS OR FLOW CONTROL. + * This is OK in 1-for-1 request-response situations where the + * requestor (front end) never has more than RING_SIZE()-1 + * outstanding requests. + */ + +/* Initialising empty rings */ +#define SHARED_RING_INIT(_s) do { \ + (_s)->req_prod = (_s)->rsp_prod = 0; \ + (_s)->req_event = (_s)->rsp_event = 1; \ + memset((_s)->pad, 0, sizeof((_s)->pad)); \ +} while(0) + +#define FRONT_RING_INIT(_r, _s, __size) do { \ + (_r)->req_prod_pvt = 0; \ + (_r)->rsp_cons = 0; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ + (_r)->sring = (_s); \ +} while (0) + +#define BACK_RING_INIT(_r, _s, __size) do { \ + (_r)->rsp_prod_pvt = 0; \ + (_r)->req_cons = 0; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ + (_r)->sring = (_s); \ +} while (0) + +/* Initialize to existing shared indexes -- for recovery */ +#define FRONT_RING_ATTACH(_r, _s, __size) do { \ + (_r)->sring = (_s); \ + (_r)->req_prod_pvt = (_s)->req_prod; \ + (_r)->rsp_cons = (_s)->rsp_prod; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ +} while (0) + +#define BACK_RING_ATTACH(_r, _s, __size) do { \ + (_r)->sring = (_s); \ + (_r)->rsp_prod_pvt = (_s)->rsp_prod; \ + (_r)->req_cons = (_s)->req_prod; \ + (_r)->nr_ents = __RING_SIZE(_s, __size); \ +} while (0) + +/* How big is this ring? */ +#define RING_SIZE(_r) \ + ((_r)->nr_ents) + +/* Number of free requests (for use on front side only). */ +#define RING_FREE_REQUESTS(_r) \ + (RING_SIZE(_r) - ((_r)->req_prod_pvt - (_r)->rsp_cons)) + +/* Test if there is an empty slot available on the front ring. + * (This is only meaningful from the front. ) + */ +#define RING_FULL(_r) \ + (RING_FREE_REQUESTS(_r) == 0) + +/* Test if there are outstanding messages to be processed on a ring. */ +#define RING_HAS_UNCONSUMED_RESPONSES(_r) \ + ((_r)->sring->rsp_prod - (_r)->rsp_cons) + +#define RING_HAS_UNCONSUMED_REQUESTS(_r) \ + ({ \ + unsigned int req = (_r)->sring->req_prod - (_r)->req_cons; \ + unsigned int rsp = RING_SIZE(_r) - \ + ((_r)->req_cons - (_r)->rsp_prod_pvt); \ + req < rsp ? req : rsp; \ + }) + +/* Direct access to individual ring elements, by index. */ +#define RING_GET_REQUEST(_r, _idx) \ + (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].req)) + +#define RING_GET_RESPONSE(_r, _idx) \ + (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].rsp)) + +/* Loop termination condition: Would the specified index overflow the ring? */ +#define RING_REQUEST_CONS_OVERFLOW(_r, _cons) \ + (((_cons) - (_r)->rsp_prod_pvt) >= RING_SIZE(_r)) + +#define RING_PUSH_REQUESTS(_r) do { \ + wmb(); /* back sees requests /before/ updated producer index */ \ + (_r)->sring->req_prod = (_r)->req_prod_pvt; \ +} while (0) + +#define RING_PUSH_RESPONSES(_r) do { \ + wmb(); /* front sees responses /before/ updated producer index */ \ + (_r)->sring->rsp_prod = (_r)->rsp_prod_pvt; \ +} while (0) + +/* + * Notification hold-off (req_event and rsp_event): + * + * When queueing requests or responses on a shared ring, it may not always be + * necessary to notify the remote end. For example, if requests are in flight + * in a backend, the front may be able to queue further requests without + * notifying the back (if the back checks for new requests when it queues + * responses). + * + * When enqueuing requests or responses: + * + * Use RING_PUSH_{REQUESTS,RESPONSES}_AND_CHECK_NOTIFY(). The second argument + * is a boolean return value. True indicates that the receiver requires an + * asynchronous notification. + * + * After dequeuing requests or responses (before sleeping the connection): + * + * Use RING_FINAL_CHECK_FOR_REQUESTS() or RING_FINAL_CHECK_FOR_RESPONSES(). + * The second argument is a boolean return value. True indicates that there + * are pending messages on the ring (i.e., the connection should not be put + * to sleep). + * + * These macros will set the req_event/rsp_event field to trigger a + * notification on the very next message that is enqueued. If you want to + * create batches of work (i.e., only receive a notification after several + * messages have been enqueued) then you will need to create a customised + * version of the FINAL_CHECK macro in your own code, which sets the event + * field appropriately. + */ + +#define RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(_r, _notify) do { \ + RING_IDX __old = (_r)->sring->req_prod; \ + RING_IDX __new = (_r)->req_prod_pvt; \ + wmb(); /* back sees requests /before/ updated producer index */ \ + (_r)->sring->req_prod = __new; \ + mb(); /* back sees new requests /before/ we check req_event */ \ + (_notify) = ((RING_IDX)(__new - (_r)->sring->req_event) < \ + (RING_IDX)(__new - __old)); \ +} while (0) + +#define RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(_r, _notify) do { \ + RING_IDX __old = (_r)->sring->rsp_prod; \ + RING_IDX __new = (_r)->rsp_prod_pvt; \ + wmb(); /* front sees responses /before/ updated producer index */ \ + (_r)->sring->rsp_prod = __new; \ + mb(); /* front sees new responses /before/ we check rsp_event */ \ + (_notify) = ((RING_IDX)(__new - (_r)->sring->rsp_event) < \ + (RING_IDX)(__new - __old)); \ +} while (0) + +#define RING_FINAL_CHECK_FOR_REQUESTS(_r, _work_to_do) do { \ + (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \ + if (_work_to_do) break; \ + (_r)->sring->req_event = (_r)->req_cons + 1; \ + mb(); \ + (_work_to_do) = RING_HAS_UNCONSUMED_REQUESTS(_r); \ +} while (0) + +#define RING_FINAL_CHECK_FOR_RESPONSES(_r, _work_to_do) do { \ + (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \ + if (_work_to_do) break; \ + (_r)->sring->rsp_event = (_r)->rsp_cons + 1; \ + mb(); \ + (_work_to_do) = RING_HAS_UNCONSUMED_RESPONSES(_r); \ +} while (0) + +#endif /* __XEN_PUBLIC_IO_RING_H__ */ diff --git a/include/xen/interface/io/xenbus.h b/include/xen/interface/io/xenbus.h new file mode 100644 index 000000000000..46508c7fa399 --- /dev/null +++ b/include/xen/interface/io/xenbus.h @@ -0,0 +1,44 @@ +/***************************************************************************** + * xenbus.h + * + * Xenbus protocol details. + * + * Copyright (C) 2005 XenSource Ltd. + */ + +#ifndef _XEN_PUBLIC_IO_XENBUS_H +#define _XEN_PUBLIC_IO_XENBUS_H + +/* The state of either end of the Xenbus, i.e. the current communication + status of initialisation across the bus. States here imply nothing about + the state of the connection between the driver and the kernel's device + layers. */ +enum xenbus_state +{ + XenbusStateUnknown = 0, + XenbusStateInitialising = 1, + XenbusStateInitWait = 2, /* Finished early + initialisation, but waiting + for information from the peer + or hotplug scripts. */ + XenbusStateInitialised = 3, /* Initialised and waiting for a + connection from the peer. */ + XenbusStateConnected = 4, + XenbusStateClosing = 5, /* The device is being closed + due to an error or an unplug + event. */ + XenbusStateClosed = 6 + +}; + +#endif /* _XEN_PUBLIC_IO_XENBUS_H */ + +/* + * Local variables: + * c-file-style: "linux" + * indent-tabs-mode: t + * c-indent-level: 8 + * c-basic-offset: 8 + * tab-width: 8 + * End: + */ diff --git a/include/xen/interface/io/xs_wire.h b/include/xen/interface/io/xs_wire.h new file mode 100644 index 000000000000..99fcffb372d1 --- /dev/null +++ b/include/xen/interface/io/xs_wire.h @@ -0,0 +1,87 @@ +/* + * Details of the "wire" protocol between Xen Store Daemon and client + * library or guest kernel. + * Copyright (C) 2005 Rusty Russell IBM Corporation + */ + +#ifndef _XS_WIRE_H +#define _XS_WIRE_H + +enum xsd_sockmsg_type +{ + XS_DEBUG, + XS_DIRECTORY, + XS_READ, + XS_GET_PERMS, + XS_WATCH, + XS_UNWATCH, + XS_TRANSACTION_START, + XS_TRANSACTION_END, + XS_INTRODUCE, + XS_RELEASE, + XS_GET_DOMAIN_PATH, + XS_WRITE, + XS_MKDIR, + XS_RM, + XS_SET_PERMS, + XS_WATCH_EVENT, + XS_ERROR, + XS_IS_DOMAIN_INTRODUCED +}; + +#define XS_WRITE_NONE "NONE" +#define XS_WRITE_CREATE "CREATE" +#define XS_WRITE_CREATE_EXCL "CREATE|EXCL" + +/* We hand errors as strings, for portability. */ +struct xsd_errors +{ + int errnum; + const char *errstring; +}; +#define XSD_ERROR(x) { x, #x } +static struct xsd_errors xsd_errors[] __attribute__((unused)) = { + XSD_ERROR(EINVAL), + XSD_ERROR(EACCES), + XSD_ERROR(EEXIST), + XSD_ERROR(EISDIR), + XSD_ERROR(ENOENT), + XSD_ERROR(ENOMEM), + XSD_ERROR(ENOSPC), + XSD_ERROR(EIO), + XSD_ERROR(ENOTEMPTY), + XSD_ERROR(ENOSYS), + XSD_ERROR(EROFS), + XSD_ERROR(EBUSY), + XSD_ERROR(EAGAIN), + XSD_ERROR(EISCONN) +}; + +struct xsd_sockmsg +{ + uint32_t type; /* XS_??? */ + uint32_t req_id;/* Request identifier, echoed in daemon's response. */ + uint32_t tx_id; /* Transaction id (0 if not related to a transaction). */ + uint32_t len; /* Length of data following this. */ + + /* Generally followed by nul-terminated string(s). */ +}; + +enum xs_watch_type +{ + XS_WATCH_PATH = 0, + XS_WATCH_TOKEN +}; + +/* Inter-domain shared memory communications. */ +#define XENSTORE_RING_SIZE 1024 +typedef uint32_t XENSTORE_RING_IDX; +#define MASK_XENSTORE_IDX(idx) ((idx) & (XENSTORE_RING_SIZE-1)) +struct xenstore_domain_interface { + char req[XENSTORE_RING_SIZE]; /* Requests to xenstore daemon. */ + char rsp[XENSTORE_RING_SIZE]; /* Replies and async watch events. */ + XENSTORE_RING_IDX req_cons, req_prod; + XENSTORE_RING_IDX rsp_cons, rsp_prod; +}; + +#endif /* _XS_WIRE_H */ diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h new file mode 100644 index 000000000000..af36ead16817 --- /dev/null +++ b/include/xen/interface/memory.h @@ -0,0 +1,145 @@ +/****************************************************************************** + * memory.h + * + * Memory reservation and information. + * + * Copyright (c) 2005, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_MEMORY_H__ +#define __XEN_PUBLIC_MEMORY_H__ + +/* + * Increase or decrease the specified domain's memory reservation. Returns a + * -ve errcode on failure, or the # extents successfully allocated or freed. + * arg == addr of struct xen_memory_reservation. + */ +#define XENMEM_increase_reservation 0 +#define XENMEM_decrease_reservation 1 +#define XENMEM_populate_physmap 6 +struct xen_memory_reservation { + + /* + * XENMEM_increase_reservation: + * OUT: MFN (*not* GMFN) bases of extents that were allocated + * XENMEM_decrease_reservation: + * IN: GMFN bases of extents to free + * XENMEM_populate_physmap: + * IN: GPFN bases of extents to populate with memory + * OUT: GMFN bases of extents that were allocated + * (NB. This command also updates the mach_to_phys translation table) + */ + GUEST_HANDLE(ulong) extent_start; + + /* Number of extents, and size/alignment of each (2^extent_order pages). */ + unsigned long nr_extents; + unsigned int extent_order; + + /* + * Maximum # bits addressable by the user of the allocated region (e.g., + * I/O devices often have a 32-bit limitation even in 64-bit systems). If + * zero then the user has no addressing restriction. + * This field is not used by XENMEM_decrease_reservation. + */ + unsigned int address_bits; + + /* + * Domain whose reservation is being changed. + * Unprivileged domains can specify only DOMID_SELF. + */ + domid_t domid; + +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_memory_reservation); + +/* + * Returns the maximum machine frame number of mapped RAM in this system. + * This command always succeeds (it never returns an error code). + * arg == NULL. + */ +#define XENMEM_maximum_ram_page 2 + +/* + * Returns the current or maximum memory reservation, in pages, of the + * specified domain (may be DOMID_SELF). Returns -ve errcode on failure. + * arg == addr of domid_t. + */ +#define XENMEM_current_reservation 3 +#define XENMEM_maximum_reservation 4 + +/* + * Returns a list of MFN bases of 2MB extents comprising the machine_to_phys + * mapping table. Architectures which do not have a m2p table do not implement + * this command. + * arg == addr of xen_machphys_mfn_list_t. + */ +#define XENMEM_machphys_mfn_list 5 +struct xen_machphys_mfn_list { + /* + * Size of the 'extent_start' array. Fewer entries will be filled if the + * machphys table is smaller than max_extents * 2MB. + */ + unsigned int max_extents; + + /* + * Pointer to buffer to fill with list of extent starts. If there are + * any large discontiguities in the machine address space, 2MB gaps in + * the machphys table will be represented by an MFN base of zero. + */ + GUEST_HANDLE(ulong) extent_start; + + /* + * Number of extents written to the above array. This will be smaller + * than 'max_extents' if the machphys table is smaller than max_e * 2MB. + */ + unsigned int nr_extents; +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list); + +/* + * Sets the GPFN at which a particular page appears in the specified guest's + * pseudophysical address space. + * arg == addr of xen_add_to_physmap_t. + */ +#define XENMEM_add_to_physmap 7 +struct xen_add_to_physmap { + /* Which domain to change the mapping for. */ + domid_t domid; + + /* Source mapping space. */ +#define XENMAPSPACE_shared_info 0 /* shared info page */ +#define XENMAPSPACE_grant_table 1 /* grant table page */ + unsigned int space; + + /* Index into source mapping space. */ + unsigned long idx; + + /* GPFN where the source mapping page should appear. */ + unsigned long gpfn; +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap); + +/* + * Translates a list of domain-specific GPFNs into MFNs. Returns a -ve error + * code on failure. This call only works for auto-translated guests. + */ +#define XENMEM_translate_gpfn_list 8 +struct xen_translate_gpfn_list { + /* Which domain to translate for? */ + domid_t domid; + + /* Length of list. */ + unsigned long nr_gpfns; + + /* List of GPFNs to translate. */ + GUEST_HANDLE(ulong) gpfn_list; + + /* + * Output list to contain MFN translations. May be the same as the input + * list (in which case each input GPFN is overwritten with the output MFN). + */ + GUEST_HANDLE(ulong) mfn_list; +}; +DEFINE_GUEST_HANDLE_STRUCT(xen_translate_gpfn_list); + +#endif /* __XEN_PUBLIC_MEMORY_H__ */ diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h new file mode 100644 index 000000000000..cd6939147cb6 --- /dev/null +++ b/include/xen/interface/physdev.h @@ -0,0 +1,145 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __XEN_PUBLIC_PHYSDEV_H__ +#define __XEN_PUBLIC_PHYSDEV_H__ + +/* + * Prototype for this hypercall is: + * int physdev_op(int cmd, void *args) + * @cmd == PHYSDEVOP_??? (physdev operation). + * @args == Operation-specific extra arguments (NULL if none). + */ + +/* + * Notify end-of-interrupt (EOI) for the specified IRQ. + * @arg == pointer to physdev_eoi structure. + */ +#define PHYSDEVOP_eoi 12 +struct physdev_eoi { + /* IN */ + uint32_t irq; +}; + +/* + * Query the status of an IRQ line. + * @arg == pointer to physdev_irq_status_query structure. + */ +#define PHYSDEVOP_irq_status_query 5 +struct physdev_irq_status_query { + /* IN */ + uint32_t irq; + /* OUT */ + uint32_t flags; /* XENIRQSTAT_* */ +}; + +/* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */ +#define _XENIRQSTAT_needs_eoi (0) +#define XENIRQSTAT_needs_eoi (1U<<_XENIRQSTAT_needs_eoi) + +/* IRQ shared by multiple guests? */ +#define _XENIRQSTAT_shared (1) +#define XENIRQSTAT_shared (1U<<_XENIRQSTAT_shared) + +/* + * Set the current VCPU's I/O privilege level. + * @arg == pointer to physdev_set_iopl structure. + */ +#define PHYSDEVOP_set_iopl 6 +struct physdev_set_iopl { + /* IN */ + uint32_t iopl; +}; + +/* + * Set the current VCPU's I/O-port permissions bitmap. + * @arg == pointer to physdev_set_iobitmap structure. + */ +#define PHYSDEVOP_set_iobitmap 7 +struct physdev_set_iobitmap { + /* IN */ + uint8_t * bitmap; + uint32_t nr_ports; +}; + +/* + * Read or write an IO-APIC register. + * @arg == pointer to physdev_apic structure. + */ +#define PHYSDEVOP_apic_read 8 +#define PHYSDEVOP_apic_write 9 +struct physdev_apic { + /* IN */ + unsigned long apic_physbase; + uint32_t reg; + /* IN or OUT */ + uint32_t value; +}; + +/* + * Allocate or free a physical upcall vector for the specified IRQ line. + * @arg == pointer to physdev_irq structure. + */ +#define PHYSDEVOP_alloc_irq_vector 10 +#define PHYSDEVOP_free_irq_vector 11 +struct physdev_irq { + /* IN */ + uint32_t irq; + /* IN or OUT */ + uint32_t vector; +}; + +/* + * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op() + * hypercall since 0x00030202. + */ +struct physdev_op { + uint32_t cmd; + union { + struct physdev_irq_status_query irq_status_query; + struct physdev_set_iopl set_iopl; + struct physdev_set_iobitmap set_iobitmap; + struct physdev_apic apic_op; + struct physdev_irq irq_op; + } u; +}; + +/* + * Notify that some PIRQ-bound event channels have been unmasked. + * ** This command is obsolete since interface version 0x00030202 and is ** + * ** unsupported by newer versions of Xen. ** + */ +#define PHYSDEVOP_IRQ_UNMASK_NOTIFY 4 + +/* + * These all-capitals physdev operation names are superceded by the new names + * (defined above) since interface version 0x00030202. + */ +#define PHYSDEVOP_IRQ_STATUS_QUERY PHYSDEVOP_irq_status_query +#define PHYSDEVOP_SET_IOPL PHYSDEVOP_set_iopl +#define PHYSDEVOP_SET_IOBITMAP PHYSDEVOP_set_iobitmap +#define PHYSDEVOP_APIC_READ PHYSDEVOP_apic_read +#define PHYSDEVOP_APIC_WRITE PHYSDEVOP_apic_write +#define PHYSDEVOP_ASSIGN_VECTOR PHYSDEVOP_alloc_irq_vector +#define PHYSDEVOP_FREE_VECTOR PHYSDEVOP_free_irq_vector +#define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi +#define PHYSDEVOP_IRQ_SHARED XENIRQSTAT_shared + +#endif /* __XEN_PUBLIC_PHYSDEV_H__ */ diff --git a/include/xen/interface/sched.h b/include/xen/interface/sched.h new file mode 100644 index 000000000000..5fec575a800a --- /dev/null +++ b/include/xen/interface/sched.h @@ -0,0 +1,77 @@ +/****************************************************************************** + * sched.h + * + * Scheduler state interactions + * + * Copyright (c) 2005, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_SCHED_H__ +#define __XEN_PUBLIC_SCHED_H__ + +#include "event_channel.h" + +/* + * The prototype for this hypercall is: + * long sched_op_new(int cmd, void *arg) + * @cmd == SCHEDOP_??? (scheduler operation). + * @arg == Operation-specific extra argument(s), as described below. + * + * **NOTE**: + * Versions of Xen prior to 3.0.2 provide only the following legacy version + * of this hypercall, supporting only the commands yield, block and shutdown: + * long sched_op(int cmd, unsigned long arg) + * @cmd == SCHEDOP_??? (scheduler operation). + * @arg == 0 (SCHEDOP_yield and SCHEDOP_block) + * == SHUTDOWN_* code (SCHEDOP_shutdown) + */ + +/* + * Voluntarily yield the CPU. + * @arg == NULL. + */ +#define SCHEDOP_yield 0 + +/* + * Block execution of this VCPU until an event is received for processing. + * If called with event upcalls masked, this operation will atomically + * reenable event delivery and check for pending events before blocking the + * VCPU. This avoids a "wakeup waiting" race. + * @arg == NULL. + */ +#define SCHEDOP_block 1 + +/* + * Halt execution of this domain (all VCPUs) and notify the system controller. + * @arg == pointer to sched_shutdown structure. + */ +#define SCHEDOP_shutdown 2 +struct sched_shutdown { + unsigned int reason; /* SHUTDOWN_* */ +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_shutdown); + +/* + * Poll a set of event-channel ports. Return when one or more are pending. An + * optional timeout may be specified. + * @arg == pointer to sched_poll structure. + */ +#define SCHEDOP_poll 3 +struct sched_poll { + GUEST_HANDLE(evtchn_port_t) ports; + unsigned int nr_ports; + uint64_t timeout; +}; +DEFINE_GUEST_HANDLE_STRUCT(sched_poll); + +/* + * Reason codes for SCHEDOP_shutdown. These may be interpreted by control + * software to determine the appropriate action. For the most part, Xen does + * not care about the shutdown code. + */ +#define SHUTDOWN_poweroff 0 /* Domain exited normally. Clean up and kill. */ +#define SHUTDOWN_reboot 1 /* Clean up, kill, and then restart. */ +#define SHUTDOWN_suspend 2 /* Clean up, save suspend info, kill. */ +#define SHUTDOWN_crash 3 /* Tell controller we've crashed. */ + +#endif /* __XEN_PUBLIC_SCHED_H__ */ diff --git a/include/xen/interface/vcpu.h b/include/xen/interface/vcpu.h new file mode 100644 index 000000000000..ff61ea365997 --- /dev/null +++ b/include/xen/interface/vcpu.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * vcpu.h + * + * VCPU initialisation, query, and hotplug. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright (c) 2005, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_VCPU_H__ +#define __XEN_PUBLIC_VCPU_H__ + +/* + * Prototype for this hypercall is: + * int vcpu_op(int cmd, int vcpuid, void *extra_args) + * @cmd == VCPUOP_??? (VCPU operation). + * @vcpuid == VCPU to operate on. + * @extra_args == Operation-specific extra arguments (NULL if none). + */ + +/* + * Initialise a VCPU. Each VCPU can be initialised only once. A + * newly-initialised VCPU will not run until it is brought up by VCPUOP_up. + * + * @extra_arg == pointer to vcpu_guest_context structure containing initial + * state for the VCPU. + */ +#define VCPUOP_initialise 0 + +/* + * Bring up a VCPU. This makes the VCPU runnable. This operation will fail + * if the VCPU has not been initialised (VCPUOP_initialise). + */ +#define VCPUOP_up 1 + +/* + * Bring down a VCPU (i.e., make it non-runnable). + * There are a few caveats that callers should observe: + * 1. This operation may return, and VCPU_is_up may return false, before the + * VCPU stops running (i.e., the command is asynchronous). It is a good + * idea to ensure that the VCPU has entered a non-critical loop before + * bringing it down. Alternatively, this operation is guaranteed + * synchronous if invoked by the VCPU itself. + * 2. After a VCPU is initialised, there is currently no way to drop all its + * references to domain memory. Even a VCPU that is down still holds + * memory references via its pagetable base pointer and GDT. It is good + * practise to move a VCPU onto an 'idle' or default page table, LDT and + * GDT before bringing it down. + */ +#define VCPUOP_down 2 + +/* Returns 1 if the given VCPU is up. */ +#define VCPUOP_is_up 3 + +/* + * Return information about the state and running time of a VCPU. + * @extra_arg == pointer to vcpu_runstate_info structure. + */ +#define VCPUOP_get_runstate_info 4 +struct vcpu_runstate_info { + /* VCPU's current state (RUNSTATE_*). */ + int state; + /* When was current state entered (system time, ns)? */ + uint64_t state_entry_time; + /* + * Time spent in each RUNSTATE_* (ns). The sum of these times is + * guaranteed not to drift from system time. + */ + uint64_t time[4]; +}; + +/* VCPU is currently running on a physical CPU. */ +#define RUNSTATE_running 0 + +/* VCPU is runnable, but not currently scheduled on any physical CPU. */ +#define RUNSTATE_runnable 1 + +/* VCPU is blocked (a.k.a. idle). It is therefore not runnable. */ +#define RUNSTATE_blocked 2 + +/* + * VCPU is not runnable, but it is not blocked. + * This is a 'catch all' state for things like hotplug and pauses by the + * system administrator (or for critical sections in the hypervisor). + * RUNSTATE_blocked dominates this state (it is the preferred state). + */ +#define RUNSTATE_offline 3 + +/* + * Register a shared memory area from which the guest may obtain its own + * runstate information without needing to execute a hypercall. + * Notes: + * 1. The registered address may be virtual or physical, depending on the + * platform. The virtual address should be registered on x86 systems. + * 2. Only one shared area may be registered per VCPU. The shared area is + * updated by the hypervisor each time the VCPU is scheduled. Thus + * runstate.state will always be RUNSTATE_running and + * runstate.state_entry_time will indicate the system time at which the + * VCPU was last scheduled to run. + * @extra_arg == pointer to vcpu_register_runstate_memory_area structure. + */ +#define VCPUOP_register_runstate_memory_area 5 +struct vcpu_register_runstate_memory_area { + union { + struct vcpu_runstate_info *v; + uint64_t p; + } addr; +}; + +/* + * Set or stop a VCPU's periodic timer. Every VCPU has one periodic timer + * which can be set via these commands. Periods smaller than one millisecond + * may not be supported. + */ +#define VCPUOP_set_periodic_timer 6 /* arg == vcpu_set_periodic_timer_t */ +#define VCPUOP_stop_periodic_timer 7 /* arg == NULL */ +struct vcpu_set_periodic_timer { + uint64_t period_ns; +}; + +/* + * Set or stop a VCPU's single-shot timer. Every VCPU has one single-shot + * timer which can be set via these commands. + */ +#define VCPUOP_set_singleshot_timer 8 /* arg == vcpu_set_singleshot_timer_t */ +#define VCPUOP_stop_singleshot_timer 9 /* arg == NULL */ +struct vcpu_set_singleshot_timer { + uint64_t timeout_abs_ns; + uint32_t flags; /* VCPU_SSHOTTMR_??? */ +}; + +/* Flags to VCPUOP_set_singleshot_timer. */ + /* Require the timeout to be in the future (return -ETIME if it's passed). */ +#define _VCPU_SSHOTTMR_future (0) +#define VCPU_SSHOTTMR_future (1U << _VCPU_SSHOTTMR_future) + +/* + * Register a memory location in the guest address space for the + * vcpu_info structure. This allows the guest to place the vcpu_info + * structure in a convenient place, such as in a per-cpu data area. + * The pointer need not be page aligned, but the structure must not + * cross a page boundary. + */ +#define VCPUOP_register_vcpu_info 10 /* arg == struct vcpu_info */ +struct vcpu_register_vcpu_info { + uint32_t mfn; /* mfn of page to place vcpu_info */ + uint32_t offset; /* offset within page */ +}; + +#endif /* __XEN_PUBLIC_VCPU_H__ */ diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h new file mode 100644 index 000000000000..453235e923f0 --- /dev/null +++ b/include/xen/interface/version.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * version.h + * + * Xen version, type, and compile information. + * + * Copyright (c) 2005, Nguyen Anh Quynh <aquynh@gmail.com> + * Copyright (c) 2005, Keir Fraser <keir@xensource.com> + */ + +#ifndef __XEN_PUBLIC_VERSION_H__ +#define __XEN_PUBLIC_VERSION_H__ + +/* NB. All ops return zero on success, except XENVER_version. */ + +/* arg == NULL; returns major:minor (16:16). */ +#define XENVER_version 0 + +/* arg == xen_extraversion_t. */ +#define XENVER_extraversion 1 +struct xen_extraversion { + char extraversion[16]; +}; +#define XEN_EXTRAVERSION_LEN (sizeof(struct xen_extraversion)) + +/* arg == xen_compile_info_t. */ +#define XENVER_compile_info 2 +struct xen_compile_info { + char compiler[64]; + char compile_by[16]; + char compile_domain[32]; + char compile_date[32]; +}; + +#define XENVER_capabilities 3 +struct xen_capabilities_info { + char info[1024]; +}; +#define XEN_CAPABILITIES_INFO_LEN (sizeof(struct xen_capabilities_info)) + +#define XENVER_changeset 4 +struct xen_changeset_info { + char info[64]; +}; +#define XEN_CHANGESET_INFO_LEN (sizeof(struct xen_changeset_info)) + +#define XENVER_platform_parameters 5 +struct xen_platform_parameters { + unsigned long virt_start; +}; + +#define XENVER_get_features 6 +struct xen_feature_info { + unsigned int submap_idx; /* IN: which 32-bit submap to return */ + uint32_t submap; /* OUT: 32-bit submap */ +}; + +/* Declares the features reported by XENVER_get_features. */ +#include "features.h" + +#endif /* __XEN_PUBLIC_VERSION_H__ */ diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h new file mode 100644 index 000000000000..518a5bf79ed3 --- /dev/null +++ b/include/xen/interface/xen.h @@ -0,0 +1,447 @@ +/****************************************************************************** + * xen.h + * + * Guest OS interface to Xen. + * + * Copyright (c) 2004, K A Fraser + */ + +#ifndef __XEN_PUBLIC_XEN_H__ +#define __XEN_PUBLIC_XEN_H__ + +#include <asm/xen/interface.h> + +/* + * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). + */ + +/* + * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. + * EAX = return value + * (argument registers may be clobbered on return) + * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. + * RAX = return value + * (argument registers not clobbered on return; RCX, R11 are) + */ +#define __HYPERVISOR_set_trap_table 0 +#define __HYPERVISOR_mmu_update 1 +#define __HYPERVISOR_set_gdt 2 +#define __HYPERVISOR_stack_switch 3 +#define __HYPERVISOR_set_callbacks 4 +#define __HYPERVISOR_fpu_taskswitch 5 +#define __HYPERVISOR_sched_op 6 +#define __HYPERVISOR_dom0_op 7 +#define __HYPERVISOR_set_debugreg 8 +#define __HYPERVISOR_get_debugreg 9 +#define __HYPERVISOR_update_descriptor 10 +#define __HYPERVISOR_memory_op 12 +#define __HYPERVISOR_multicall 13 +#define __HYPERVISOR_update_va_mapping 14 +#define __HYPERVISOR_set_timer_op 15 +#define __HYPERVISOR_event_channel_op_compat 16 +#define __HYPERVISOR_xen_version 17 +#define __HYPERVISOR_console_io 18 +#define __HYPERVISOR_physdev_op_compat 19 +#define __HYPERVISOR_grant_table_op 20 +#define __HYPERVISOR_vm_assist 21 +#define __HYPERVISOR_update_va_mapping_otherdomain 22 +#define __HYPERVISOR_iret 23 /* x86 only */ +#define __HYPERVISOR_vcpu_op 24 +#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ +#define __HYPERVISOR_mmuext_op 26 +#define __HYPERVISOR_acm_op 27 +#define __HYPERVISOR_nmi_op 28 +#define __HYPERVISOR_sched_op_new 29 +#define __HYPERVISOR_callback_op 30 +#define __HYPERVISOR_xenoprof_op 31 +#define __HYPERVISOR_event_channel_op 32 +#define __HYPERVISOR_physdev_op 33 +#define __HYPERVISOR_hvm_op 34 + +/* + * VIRTUAL INTERRUPTS + * + * Virtual interrupts that a guest OS may receive from Xen. + */ +#define VIRQ_TIMER 0 /* Timebase update, and/or requested timeout. */ +#define VIRQ_DEBUG 1 /* Request guest to dump debug info. */ +#define VIRQ_CONSOLE 2 /* (DOM0) Bytes received on emergency console. */ +#define VIRQ_DOM_EXC 3 /* (DOM0) Exceptional event for some domain. */ +#define VIRQ_DEBUGGER 6 /* (DOM0) A domain has paused for debugging. */ +#define NR_VIRQS 8 + +/* + * MMU-UPDATE REQUESTS + * + * HYPERVISOR_mmu_update() accepts a list of (ptr, val) pairs. + * A foreigndom (FD) can be specified (or DOMID_SELF for none). + * Where the FD has some effect, it is described below. + * ptr[1:0] specifies the appropriate MMU_* command. + * + * ptr[1:0] == MMU_NORMAL_PT_UPDATE: + * Updates an entry in a page table. If updating an L1 table, and the new + * table entry is valid/present, the mapped frame must belong to the FD, if + * an FD has been specified. If attempting to map an I/O page then the + * caller assumes the privilege of the FD. + * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. + * FD == DOMID_XEN: Map restricted areas of Xen's heap space. + * ptr[:2] -- Machine address of the page-table entry to modify. + * val -- Value to write. + * + * ptr[1:0] == MMU_MACHPHYS_UPDATE: + * Updates an entry in the machine->pseudo-physical mapping table. + * ptr[:2] -- Machine address within the frame whose mapping to modify. + * The frame must belong to the FD, if one is specified. + * val -- Value to write into the mapping entry. + */ +#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ +#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ + +/* + * MMU EXTENDED OPERATIONS + * + * HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. + * A foreigndom (FD) can be specified (or DOMID_SELF for none). + * Where the FD has some effect, it is described below. + * + * cmd: MMUEXT_(UN)PIN_*_TABLE + * mfn: Machine frame number to be (un)pinned as a p.t. page. + * The frame must belong to the FD, if one is specified. + * + * cmd: MMUEXT_NEW_BASEPTR + * mfn: Machine frame number of new page-table base to install in MMU. + * + * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] + * mfn: Machine frame number of new page-table base to install in MMU + * when in user space. + * + * cmd: MMUEXT_TLB_FLUSH_LOCAL + * No additional arguments. Flushes local TLB. + * + * cmd: MMUEXT_INVLPG_LOCAL + * linear_addr: Linear address to be flushed from the local TLB. + * + * cmd: MMUEXT_TLB_FLUSH_MULTI + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_INVLPG_MULTI + * linear_addr: Linear address to be flushed. + * vcpumask: Pointer to bitmap of VCPUs to be flushed. + * + * cmd: MMUEXT_TLB_FLUSH_ALL + * No additional arguments. Flushes all VCPUs' TLBs. + * + * cmd: MMUEXT_INVLPG_ALL + * linear_addr: Linear address to be flushed from all VCPUs' TLBs. + * + * cmd: MMUEXT_FLUSH_CACHE + * No additional arguments. Writes back and flushes cache contents. + * + * cmd: MMUEXT_SET_LDT + * linear_addr: Linear address of LDT base (NB. must be page-aligned). + * nr_ents: Number of entries in LDT. + */ +#define MMUEXT_PIN_L1_TABLE 0 +#define MMUEXT_PIN_L2_TABLE 1 +#define MMUEXT_PIN_L3_TABLE 2 +#define MMUEXT_PIN_L4_TABLE 3 +#define MMUEXT_UNPIN_TABLE 4 +#define MMUEXT_NEW_BASEPTR 5 +#define MMUEXT_TLB_FLUSH_LOCAL 6 +#define MMUEXT_INVLPG_LOCAL 7 +#define MMUEXT_TLB_FLUSH_MULTI 8 +#define MMUEXT_INVLPG_MULTI 9 +#define MMUEXT_TLB_FLUSH_ALL 10 +#define MMUEXT_INVLPG_ALL 11 +#define MMUEXT_FLUSH_CACHE 12 +#define MMUEXT_SET_LDT 13 +#define MMUEXT_NEW_USER_BASEPTR 15 + +#ifndef __ASSEMBLY__ +struct mmuext_op { + unsigned int cmd; + union { + /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR */ + unsigned long mfn; + /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ + unsigned long linear_addr; + } arg1; + union { + /* SET_LDT */ + unsigned int nr_ents; + /* TLB_FLUSH_MULTI, INVLPG_MULTI */ + void *vcpumask; + } arg2; +}; +DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); +#endif + +/* These are passed as 'flags' to update_va_mapping. They can be ORed. */ +/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ +/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ +#define UVMF_NONE (0UL<<0) /* No flushing at all. */ +#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ +#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ +#define UVMF_FLUSHTYPE_MASK (3UL<<0) +#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ +#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ +#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ + +/* + * Commands to HYPERVISOR_console_io(). + */ +#define CONSOLEIO_write 0 +#define CONSOLEIO_read 1 + +/* + * Commands to HYPERVISOR_vm_assist(). + */ +#define VMASST_CMD_enable 0 +#define VMASST_CMD_disable 1 +#define VMASST_TYPE_4gb_segments 0 +#define VMASST_TYPE_4gb_segments_notify 1 +#define VMASST_TYPE_writable_pagetables 2 +#define VMASST_TYPE_pae_extended_cr3 3 +#define MAX_VMASST_TYPE 3 + +#ifndef __ASSEMBLY__ + +typedef uint16_t domid_t; + +/* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ +#define DOMID_FIRST_RESERVED (0x7FF0U) + +/* DOMID_SELF is used in certain contexts to refer to oneself. */ +#define DOMID_SELF (0x7FF0U) + +/* + * DOMID_IO is used to restrict page-table updates to mapping I/O memory. + * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO + * is useful to ensure that no mappings to the OS's own heap are accidentally + * installed. (e.g., in Linux this could cause havoc as reference counts + * aren't adjusted on the I/O-mapping code path). + * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can + * be specified by any calling domain. + */ +#define DOMID_IO (0x7FF1U) + +/* + * DOMID_XEN is used to allow privileged domains to map restricted parts of + * Xen's heap space (e.g., the machine_to_phys table). + * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if + * the caller is privileged. + */ +#define DOMID_XEN (0x7FF2U) + +/* + * Send an array of these to HYPERVISOR_mmu_update(). + * NB. The fields are natural pointer/address size for this architecture. + */ +struct mmu_update { + uint64_t ptr; /* Machine address of PTE. */ + uint64_t val; /* New contents of PTE. */ +}; +DEFINE_GUEST_HANDLE_STRUCT(mmu_update); + +/* + * Send an array of these to HYPERVISOR_multicall(). + * NB. The fields are natural register size for this architecture. + */ +struct multicall_entry { + unsigned long op; + long result; + unsigned long args[6]; +}; +DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); + +/* + * Event channel endpoints per domain: + * 1024 if a long is 32 bits; 4096 if a long is 64 bits. + */ +#define NR_EVENT_CHANNELS (sizeof(unsigned long) * sizeof(unsigned long) * 64) + +struct vcpu_time_info { + /* + * Updates to the following values are preceded and followed + * by an increment of 'version'. The guest can therefore + * detect updates by looking for changes to 'version'. If the + * least-significant bit of the version number is set then an + * update is in progress and the guest must wait to read a + * consistent set of values. The correct way to interact with + * the version number is similar to Linux's seqlock: see the + * implementations of read_seqbegin/read_seqretry. + */ + uint32_t version; + uint32_t pad0; + uint64_t tsc_timestamp; /* TSC at last update of time vals. */ + uint64_t system_time; /* Time, in nanosecs, since boot. */ + /* + * Current system time: + * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul + * CPU frequency (Hz): + * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift + */ + uint32_t tsc_to_system_mul; + int8_t tsc_shift; + int8_t pad1[3]; +}; /* 32 bytes */ + +struct vcpu_info { + /* + * 'evtchn_upcall_pending' is written non-zero by Xen to indicate + * a pending notification for a particular VCPU. It is then cleared + * by the guest OS /before/ checking for pending work, thus avoiding + * a set-and-check race. Note that the mask is only accessed by Xen + * on the CPU that is currently hosting the VCPU. This means that the + * pending and mask flags can be updated by the guest without special + * synchronisation (i.e., no need for the x86 LOCK prefix). + * This may seem suboptimal because if the pending flag is set by + * a different CPU then an IPI may be scheduled even when the mask + * is set. However, note: + * 1. The task of 'interrupt holdoff' is covered by the per-event- + * channel mask bits. A 'noisy' event that is continually being + * triggered can be masked at source at this very precise + * granularity. + * 2. The main purpose of the per-VCPU mask is therefore to restrict + * reentrant execution: whether for concurrency control, or to + * prevent unbounded stack usage. Whatever the purpose, we expect + * that the mask will be asserted only for short periods at a time, + * and so the likelihood of a 'spurious' IPI is suitably small. + * The mask is read before making an event upcall to the guest: a + * non-zero mask therefore guarantees that the VCPU will not receive + * an upcall activation. The mask is cleared when the VCPU requests + * to block: this avoids wakeup-waiting races. + */ + uint8_t evtchn_upcall_pending; + uint8_t evtchn_upcall_mask; + unsigned long evtchn_pending_sel; + struct arch_vcpu_info arch; + struct vcpu_time_info time; +}; /* 64 bytes (x86) */ + +/* + * Xen/kernel shared data -- pointer provided in start_info. + * NB. We expect that this struct is smaller than a page. + */ +struct shared_info { + struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; + + /* + * A domain can create "event channels" on which it can send and receive + * asynchronous event notifications. There are three classes of event that + * are delivered by this mechanism: + * 1. Bi-directional inter- and intra-domain connections. Domains must + * arrange out-of-band to set up a connection (usually by allocating + * an unbound 'listener' port and avertising that via a storage service + * such as xenstore). + * 2. Physical interrupts. A domain with suitable hardware-access + * privileges can bind an event-channel port to a physical interrupt + * source. + * 3. Virtual interrupts ('events'). A domain can bind an event-channel + * port to a virtual interrupt source, such as the virtual-timer + * device or the emergency console. + * + * Event channels are addressed by a "port index". Each channel is + * associated with two bits of information: + * 1. PENDING -- notifies the domain that there is a pending notification + * to be processed. This bit is cleared by the guest. + * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING + * will cause an asynchronous upcall to be scheduled. This bit is only + * updated by the guest. It is read-only within Xen. If a channel + * becomes pending while the channel is masked then the 'edge' is lost + * (i.e., when the channel is unmasked, the guest must manually handle + * pending notifications as no upcall will be scheduled by Xen). + * + * To expedite scanning of pending notifications, any 0->1 pending + * transition on an unmasked channel causes a corresponding bit in a + * per-vcpu selector word to be set. Each bit in the selector covers a + * 'C long' in the PENDING bitfield array. + */ + unsigned long evtchn_pending[sizeof(unsigned long) * 8]; + unsigned long evtchn_mask[sizeof(unsigned long) * 8]; + + /* + * Wallclock time: updated only by control software. Guests should base + * their gettimeofday() syscall on this wallclock-base value. + */ + uint32_t wc_version; /* Version counter: see vcpu_time_info_t. */ + uint32_t wc_sec; /* Secs 00:00:00 UTC, Jan 1, 1970. */ + uint32_t wc_nsec; /* Nsecs 00:00:00 UTC, Jan 1, 1970. */ + + struct arch_shared_info arch; + +}; + +/* + * Start-of-day memory layout for the initial domain (DOM0): + * 1. The domain is started within contiguous virtual-memory region. + * 2. The contiguous region begins and ends on an aligned 4MB boundary. + * 3. The region start corresponds to the load address of the OS image. + * If the load address is not 4MB aligned then the address is rounded down. + * 4. This the order of bootstrap elements in the initial virtual region: + * a. relocated kernel image + * b. initial ram disk [mod_start, mod_len] + * c. list of allocated page frames [mfn_list, nr_pages] + * d. start_info_t structure [register ESI (x86)] + * e. bootstrap page tables [pt_base, CR3 (x86)] + * f. bootstrap stack [register ESP (x86)] + * 5. Bootstrap elements are packed together, but each is 4kB-aligned. + * 6. The initial ram disk may be omitted. + * 7. The list of page frames forms a contiguous 'pseudo-physical' memory + * layout for the domain. In particular, the bootstrap virtual-memory + * region is a 1:1 mapping to the first section of the pseudo-physical map. + * 8. All bootstrap elements are mapped read-writable for the guest OS. The + * only exception is the bootstrap page table, which is mapped read-only. + * 9. There is guaranteed to be at least 512kB padding after the final + * bootstrap element. If necessary, the bootstrap virtual region is + * extended by an extra 4MB to ensure this. + */ + +#define MAX_GUEST_CMDLINE 1024 +struct start_info { + /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ + char magic[32]; /* "xen-<version>-<platform>". */ + unsigned long nr_pages; /* Total pages allocated to this domain. */ + unsigned long shared_info; /* MACHINE address of shared info struct. */ + uint32_t flags; /* SIF_xxx flags. */ + unsigned long store_mfn; /* MACHINE page number of shared page. */ + uint32_t store_evtchn; /* Event channel for store communication. */ + union { + struct { + unsigned long mfn; /* MACHINE page number of console page. */ + uint32_t evtchn; /* Event channel for console page. */ + } domU; + struct { + uint32_t info_off; /* Offset of console_info struct. */ + uint32_t info_size; /* Size of console_info struct from start.*/ + } dom0; + } console; + /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ + unsigned long pt_base; /* VIRTUAL address of page directory. */ + unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ + unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ + unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ + unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ + int8_t cmd_line[MAX_GUEST_CMDLINE]; +}; + +/* These flags are passed in the 'flags' field of start_info_t. */ +#define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ +#define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ + +typedef uint64_t cpumap_t; + +typedef uint8_t xen_domain_handle_t[16]; + +/* Turn a plain number into a C unsigned long constant. */ +#define __mk_unsigned_long(x) x ## UL +#define mk_unsigned_long(x) __mk_unsigned_long(x) + +#else /* __ASSEMBLY__ */ + +/* In assembly code we cannot use C numeric constant suffixes. */ +#define mk_unsigned_long(x) x + +#endif /* !__ASSEMBLY__ */ + +#endif /* __XEN_PUBLIC_XEN_H__ */ diff --git a/include/xen/page.h b/include/xen/page.h new file mode 100644 index 000000000000..c0c8fcb27899 --- /dev/null +++ b/include/xen/page.h @@ -0,0 +1,180 @@ +#ifndef __XEN_PAGE_H +#define __XEN_PAGE_H + +#include <linux/pfn.h> + +#include <asm/uaccess.h> +#include <asm/pgtable.h> + +#include <xen/features.h> + +#ifdef CONFIG_X86_PAE +/* Xen machine address */ +typedef struct xmaddr { + unsigned long long maddr; +} xmaddr_t; + +/* Xen pseudo-physical address */ +typedef struct xpaddr { + unsigned long long paddr; +} xpaddr_t; +#else +/* Xen machine address */ +typedef struct xmaddr { + unsigned long maddr; +} xmaddr_t; + +/* Xen pseudo-physical address */ +typedef struct xpaddr { + unsigned long paddr; +} xpaddr_t; +#endif + +#define XMADDR(x) ((xmaddr_t) { .maddr = (x) }) +#define XPADDR(x) ((xpaddr_t) { .paddr = (x) }) + +/**** MACHINE <-> PHYSICAL CONVERSION MACROS ****/ +#define INVALID_P2M_ENTRY (~0UL) +#define FOREIGN_FRAME_BIT (1UL<<31) +#define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT) + +extern unsigned long *phys_to_machine_mapping; + +static inline unsigned long pfn_to_mfn(unsigned long pfn) +{ + if (xen_feature(XENFEAT_auto_translated_physmap)) + return pfn; + + return phys_to_machine_mapping[(unsigned int)(pfn)] & + ~FOREIGN_FRAME_BIT; +} + +static inline int phys_to_machine_mapping_valid(unsigned long pfn) +{ + if (xen_feature(XENFEAT_auto_translated_physmap)) + return 1; + + return (phys_to_machine_mapping[pfn] != INVALID_P2M_ENTRY); +} + +static inline unsigned long mfn_to_pfn(unsigned long mfn) +{ + unsigned long pfn; + + if (xen_feature(XENFEAT_auto_translated_physmap)) + return mfn; + +#if 0 + if (unlikely((mfn >> machine_to_phys_order) != 0)) + return max_mapnr; +#endif + + pfn = 0; + /* + * The array access can fail (e.g., device space beyond end of RAM). + * In such cases it doesn't matter what we return (we return garbage), + * but we must handle the fault without crashing! + */ + __get_user(pfn, &machine_to_phys_mapping[mfn]); + + return pfn; +} + +static inline xmaddr_t phys_to_machine(xpaddr_t phys) +{ + unsigned offset = phys.paddr & ~PAGE_MASK; + return XMADDR(PFN_PHYS((u64)pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset); +} + +static inline xpaddr_t machine_to_phys(xmaddr_t machine) +{ + unsigned offset = machine.maddr & ~PAGE_MASK; + return XPADDR(PFN_PHYS((u64)mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset); +} + +/* + * We detect special mappings in one of two ways: + * 1. If the MFN is an I/O page then Xen will set the m2p entry + * to be outside our maximum possible pseudophys range. + * 2. If the MFN belongs to a different domain then we will certainly + * not have MFN in our p2m table. Conversely, if the page is ours, + * then we'll have p2m(m2p(MFN))==MFN. + * If we detect a special mapping then it doesn't have a 'struct page'. + * We force !pfn_valid() by returning an out-of-range pointer. + * + * NB. These checks require that, for any MFN that is not in our reservation, + * there is no PFN such that p2m(PFN) == MFN. Otherwise we can get confused if + * we are foreign-mapping the MFN, and the other domain as m2p(MFN) == PFN. + * Yikes! Various places must poke in INVALID_P2M_ENTRY for safety. + * + * NB2. When deliberately mapping foreign pages into the p2m table, you *must* + * use FOREIGN_FRAME(). This will cause pte_pfn() to choke on it, as we + * require. In all the cases we care about, the FOREIGN_FRAME bit is + * masked (e.g., pfn_to_mfn()) so behaviour there is correct. + */ +static inline unsigned long mfn_to_local_pfn(unsigned long mfn) +{ + extern unsigned long max_mapnr; + unsigned long pfn = mfn_to_pfn(mfn); + if ((pfn < max_mapnr) + && !xen_feature(XENFEAT_auto_translated_physmap) + && (phys_to_machine_mapping[pfn] != mfn)) + return max_mapnr; /* force !pfn_valid() */ + return pfn; +} + +static inline void set_phys_to_machine(unsigned long pfn, unsigned long mfn) +{ + if (xen_feature(XENFEAT_auto_translated_physmap)) { + BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY); + return; + } + phys_to_machine_mapping[pfn] = mfn; +} + +/* VIRT <-> MACHINE conversion */ +#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) +#define virt_to_mfn(v) (pfn_to_mfn(PFN_DOWN(__pa(v)))) +#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) + +#ifdef CONFIG_X86_PAE +#define pte_mfn(_pte) (((_pte).pte_low >> PAGE_SHIFT) | \ + (((_pte).pte_high & 0xfff) << (32-PAGE_SHIFT))) + +static inline pte_t mfn_pte(unsigned long page_nr, pgprot_t pgprot) +{ + pte_t pte; + + pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | + (pgprot_val(pgprot) >> 32); + pte.pte_high &= (__supported_pte_mask >> 32); + pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)); + pte.pte_low &= __supported_pte_mask; + + return pte; +} + +static inline unsigned long long pte_val_ma(pte_t x) +{ + return ((unsigned long long)x.pte_high << 32) | x.pte_low; +} +#define pmd_val_ma(v) ((v).pmd) +#define pud_val_ma(v) ((v).pgd.pgd) +#define __pte_ma(x) ((pte_t) { .pte_low = (x), .pte_high = (x)>>32 } ) +#define __pmd_ma(x) ((pmd_t) { (x) } ) +#else /* !X86_PAE */ +#define pte_mfn(_pte) ((_pte).pte_low >> PAGE_SHIFT) +#define mfn_pte(pfn, prot) __pte_ma(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_val_ma(x) ((x).pte_low) +#define pmd_val_ma(v) ((v).pud.pgd.pgd) +#define __pte_ma(x) ((pte_t) { (x) } ) +#endif /* CONFIG_X86_PAE */ + +#define pgd_val_ma(x) ((x).pgd) + + +xmaddr_t arbitrary_virt_to_machine(unsigned long address); +void make_lowmem_page_readonly(void *vaddr); +void make_lowmem_page_readwrite(void *vaddr); + +#endif /* __XEN_PAGE_H */ diff --git a/include/xen/xenbus.h b/include/xen/xenbus.h new file mode 100644 index 000000000000..6f7c290651ae --- /dev/null +++ b/include/xen/xenbus.h @@ -0,0 +1,234 @@ +/****************************************************************************** + * xenbus.h + * + * Talks to Xen Store to figure out what devices we have. + * + * Copyright (C) 2005 Rusty Russell, IBM Corporation + * Copyright (C) 2005 XenSource Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation; or, when distributed + * separately from the Linux kernel or incorporated into other + * software packages, subject to the following license: + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this source file (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, + * merge, publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _XEN_XENBUS_H +#define _XEN_XENBUS_H + +#include <linux/device.h> +#include <linux/notifier.h> +#include <linux/mutex.h> +#include <linux/completion.h> +#include <linux/init.h> +#include <xen/interface/xen.h> +#include <xen/interface/grant_table.h> +#include <xen/interface/io/xenbus.h> +#include <xen/interface/io/xs_wire.h> + +/* Register callback to watch this node. */ +struct xenbus_watch +{ + struct list_head list; + + /* Path being watched. */ + const char *node; + + /* Callback (executed in a process context with no locks held). */ + void (*callback)(struct xenbus_watch *, + const char **vec, unsigned int len); +}; + + +/* A xenbus device. */ +struct xenbus_device { + const char *devicetype; + const char *nodename; + const char *otherend; + int otherend_id; + struct xenbus_watch otherend_watch; + struct device dev; + enum xenbus_state state; + struct completion down; +}; + +static inline struct xenbus_device *to_xenbus_device(struct device *dev) +{ + return container_of(dev, struct xenbus_device, dev); +} + +struct xenbus_device_id +{ + /* .../device/<device_type>/<identifier> */ + char devicetype[32]; /* General class of device. */ +}; + +/* A xenbus driver. */ +struct xenbus_driver { + char *name; + struct module *owner; + const struct xenbus_device_id *ids; + int (*probe)(struct xenbus_device *dev, + const struct xenbus_device_id *id); + void (*otherend_changed)(struct xenbus_device *dev, + enum xenbus_state backend_state); + int (*remove)(struct xenbus_device *dev); + int (*suspend)(struct xenbus_device *dev); + int (*suspend_cancel)(struct xenbus_device *dev); + int (*resume)(struct xenbus_device *dev); + int (*uevent)(struct xenbus_device *, char **, int, char *, int); + struct device_driver driver; + int (*read_otherend_details)(struct xenbus_device *dev); +}; + +static inline struct xenbus_driver *to_xenbus_driver(struct device_driver *drv) +{ + return container_of(drv, struct xenbus_driver, driver); +} + +int __must_check __xenbus_register_frontend(struct xenbus_driver *drv, + struct module *owner, + const char *mod_name); + +static inline int __must_check +xenbus_register_frontend(struct xenbus_driver *drv) +{ + WARN_ON(drv->owner != THIS_MODULE); + return __xenbus_register_frontend(drv, THIS_MODULE, KBUILD_MODNAME); +} + +int __must_check __xenbus_register_backend(struct xenbus_driver *drv, + struct module *owner, + const char *mod_name); +static inline int __must_check +xenbus_register_backend(struct xenbus_driver *drv) +{ + WARN_ON(drv->owner != THIS_MODULE); + return __xenbus_register_backend(drv, THIS_MODULE, KBUILD_MODNAME); +} + +void xenbus_unregister_driver(struct xenbus_driver *drv); + +struct xenbus_transaction +{ + u32 id; +}; + +/* Nil transaction ID. */ +#define XBT_NIL ((struct xenbus_transaction) { 0 }) + +int __init xenbus_dev_init(void); + +char **xenbus_directory(struct xenbus_transaction t, + const char *dir, const char *node, unsigned int *num); +void *xenbus_read(struct xenbus_transaction t, + const char *dir, const char *node, unsigned int *len); +int xenbus_write(struct xenbus_transaction t, + const char *dir, const char *node, const char *string); +int xenbus_mkdir(struct xenbus_transaction t, + const char *dir, const char *node); +int xenbus_exists(struct xenbus_transaction t, + const char *dir, const char *node); +int xenbus_rm(struct xenbus_transaction t, const char *dir, const char *node); +int xenbus_transaction_start(struct xenbus_transaction *t); +int xenbus_transaction_end(struct xenbus_transaction t, int abort); + +/* Single read and scanf: returns -errno or num scanned if > 0. */ +int xenbus_scanf(struct xenbus_transaction t, + const char *dir, const char *node, const char *fmt, ...) + __attribute__((format(scanf, 4, 5))); + +/* Single printf and write: returns -errno or 0. */ +int xenbus_printf(struct xenbus_transaction t, + const char *dir, const char *node, const char *fmt, ...) + __attribute__((format(printf, 4, 5))); + +/* Generic read function: NULL-terminated triples of name, + * sprintf-style type string, and pointer. Returns 0 or errno.*/ +int xenbus_gather(struct xenbus_transaction t, const char *dir, ...); + +/* notifer routines for when the xenstore comes up */ +extern int xenstored_ready; +int register_xenstore_notifier(struct notifier_block *nb); +void unregister_xenstore_notifier(struct notifier_block *nb); + +int register_xenbus_watch(struct xenbus_watch *watch); +void unregister_xenbus_watch(struct xenbus_watch *watch); +void xs_suspend(void); +void xs_resume(void); +void xs_suspend_cancel(void); + +/* Used by xenbus_dev to borrow kernel's store connection. */ +void *xenbus_dev_request_and_reply(struct xsd_sockmsg *msg); + +struct work_struct; + +/* Prepare for domain suspend: then resume or cancel the suspend. */ +void xenbus_suspend(void); +void xenbus_resume(void); +void xenbus_probe(struct work_struct *); +void xenbus_suspend_cancel(void); + +#define XENBUS_IS_ERR_READ(str) ({ \ + if (!IS_ERR(str) && strlen(str) == 0) { \ + kfree(str); \ + str = ERR_PTR(-ERANGE); \ + } \ + IS_ERR(str); \ +}) + +#define XENBUS_EXIST_ERR(err) ((err) == -ENOENT || (err) == -ERANGE) + +int xenbus_watch_path(struct xenbus_device *dev, const char *path, + struct xenbus_watch *watch, + void (*callback)(struct xenbus_watch *, + const char **, unsigned int)); +int xenbus_watch_pathfmt(struct xenbus_device *dev, struct xenbus_watch *watch, + void (*callback)(struct xenbus_watch *, + const char **, unsigned int), + const char *pathfmt, ...) + __attribute__ ((format (printf, 4, 5))); + +int xenbus_switch_state(struct xenbus_device *dev, enum xenbus_state new_state); +int xenbus_grant_ring(struct xenbus_device *dev, unsigned long ring_mfn); +int xenbus_map_ring_valloc(struct xenbus_device *dev, + int gnt_ref, void **vaddr); +int xenbus_map_ring(struct xenbus_device *dev, int gnt_ref, + grant_handle_t *handle, void *vaddr); + +int xenbus_unmap_ring_vfree(struct xenbus_device *dev, void *vaddr); +int xenbus_unmap_ring(struct xenbus_device *dev, + grant_handle_t handle, void *vaddr); + +int xenbus_alloc_evtchn(struct xenbus_device *dev, int *port); +int xenbus_bind_evtchn(struct xenbus_device *dev, int remote_port, int *port); +int xenbus_free_evtchn(struct xenbus_device *dev, int port); + +enum xenbus_state xenbus_read_driver_state(const char *path); + +void xenbus_dev_error(struct xenbus_device *dev, int err, const char *fmt, ...); +void xenbus_dev_fatal(struct xenbus_device *dev, int err, const char *fmt, ...); + +const char *xenbus_strstate(enum xenbus_state state); +int xenbus_dev_is_online(struct xenbus_device *dev); +int xenbus_frontend_closed(struct xenbus_device *dev); + +#endif /* _XEN_XENBUS_H */ |