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authorSwapnil Jakhade <sjakhade@cadence.com>2021-12-23 07:01:37 +0100
committerVinod Koul <vkoul@kernel.org>2021-12-27 16:35:09 +0530
commit09d976b3e8e257ff44405b6506bbaae6be1a6b3c (patch)
tree34f9875107746463a38062026196774cfe08663a /include/dt-bindings
parent637feefb8ac53fbe1147edb707b03dc09839fdf5 (diff)
phy: cadence: Sierra: Add support for derived reference clock output
Sierra has derived differential reference clock output which is sourced after the spread spectrum generation has been added. Add support to drive derived reference clock out of serdes. Model this derived clock as a "clock" so that platforms using this can enable it. Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz clock output. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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