diff options
| author | Jacob Keller <jacob.e.keller@intel.com> | 2022-11-09 15:09:40 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-11-11 10:58:39 +0000 |
| commit | 974557020a5917f73fb7d7218402ef744b109c41 (patch) | |
| tree | e3d02fc9fcff61e751f151057781abc8e98c2497 /drivers | |
| parent | e3f18e9d353aa8bd9e4db10acab21df380e212f5 (diff) | |
ptp: hclge: convert .adjfreq to .adjfine
The hclge implementation of .adjfreq is implemented in terms of a
straight forward "base * ppb / 1 billion" calculation.
Convert this to the newer .adjfine, using the recently added
adjust_by_scaled_ppm helper function.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Cc: Salil Mehta <salil.mehta@huawei.com>
Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c index a40b1583f114..80a2a0073d97 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c @@ -22,28 +22,16 @@ static int hclge_ptp_get_cycle(struct hclge_dev *hdev) return 0; } -static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) +static int hclge_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; - u64 adj_val, adj_base, diff; + u64 adj_val, adj_base; unsigned long flags; - bool is_neg = false; u32 quo, numerator; - if (ppb < 0) { - ppb = -ppb; - is_neg = true; - } - adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; - adj_val = adj_base * ppb; - diff = div_u64(adj_val, 1000000000ULL); - - if (is_neg) - adj_val = adj_base - diff; - else - adj_val = adj_base + diff; + adj_val = adjust_by_scaled_ppm(adj_base, scaled_ppm); /* This clock cycle is defined by three part: quotient, numerator * and denominator. For example, 2.5ns, the quotient is 2, @@ -446,7 +434,7 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev) ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX; ptp->info.n_ext_ts = 0; ptp->info.pps = 0; - ptp->info.adjfreq = hclge_ptp_adjfreq; + ptp->info.adjfine = hclge_ptp_adjfine; ptp->info.adjtime = hclge_ptp_adjtime; ptp->info.gettimex64 = hclge_ptp_gettimex; ptp->info.settime64 = hclge_ptp_settime; @@ -504,7 +492,7 @@ int hclge_ptp_init(struct hclge_dev *hdev) goto out; set_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags); - ret = hclge_ptp_adjfreq(&hdev->ptp->info, 0); + ret = hclge_ptp_adjfine(&hdev->ptp->info, 0); if (ret) { dev_err(&hdev->pdev->dev, "failed to init freq, ret = %d\n", ret); |