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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2015-03-09 16:48:47 +0200
committerMark Brown <broonie@kernel.org>2015-03-09 18:11:13 +0000
commitf051fc8f117d95baaa3654d40e779c56c2c6d180 (patch)
tree2a498e6522720261b2bce4adbbd045e23ca8cd8c /drivers
parent9f14538ecd1a210eff244a0a2281f6744fe4a59d (diff)
spi: dw-mid: take care of FIFO overrun/underrun when do DMA
In according to documentation SPI in DMA mode may encounter underrun/overrun failures in rare cases. When such failure occurs, an error recovery protocol is expected to be implemented in the device driver so that the failed transaction can be restarted. This patch enables FIFO overrun / underrun interrupts in DMA case and adds a handler for that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/spi-dw-mid.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 4b4d266aff9f..3729cdd84e94 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -100,6 +100,22 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
dma_release_channel(dws->rxchan);
}
+static irqreturn_t dma_transfer(struct dw_spi *dws)
+{
+ u16 irq_status = dw_readw(dws, DW_SPI_ISR);
+
+ if (!irq_status)
+ return IRQ_NONE;
+
+ dw_readw(dws, DW_SPI_ICR);
+ spi_reset_chip(dws);
+
+ dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
+ dws->master->cur_msg->status = -EIO;
+ spi_finalize_current_transfer(dws->master);
+ return IRQ_HANDLED;
+}
+
static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
if (dma_width == 1)
return DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -220,6 +236,11 @@ static int mid_spi_dma_setup(struct dw_spi *dws)
dma_ctrl |= SPI_DMA_RDMAE;
dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
+ /* Set the interrupt mask */
+ spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
+
+ dws->transfer_handler = dma_transfer;
+
return 0;
}