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authorSteven Lee <steven_lee@aspeedtech.com>2021-09-07 17:55:25 +0800
committerBartosz Golaszewski <brgl@bgdev.pl>2021-09-22 11:23:10 +0200
commitf6c35df22708438c94605b8896d2b4e4d5f342a3 (patch)
treee3703eaa07df5ef7795fb33682d36abff542cc65 /drivers
parent2dd824cca3407bc9a2bd11b00f6e117b66fcfcf1 (diff)
gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.
The current hwirq is calculated based on the old GPIO pin order(input GPIO range is from 0 to ngpios - 1). It should be calculated based on the current GPIO input pin order(input GPIOs are 0, 2, 4, ..., (ngpios - 1) * 2). Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpio/gpio-aspeed-sgpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 10f303d15225..3d6ef37a7702 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, &reg, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
+ generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
}
chained_irq_exit(ic, desc);