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authorMichal Simek <michal.simek@xilinx.com>2014-05-06 06:46:15 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-05-28 12:24:31 -0700
commitd3352154041e28cf8c1c260cca41d8e83d5377d8 (patch)
treed7ff0426499201491c308564ee592877e9b064e8 /drivers/tty
parentac62391496cf1ace051c4daebb00f7435320f11f (diff)
tty: serial: uartlite: Specify time for sending chars
Xilinx MDM (Microblaze Debug Module) also contains uart interface via JTAG which is compatible with uartlite driver. This interface is really slow that's why timeout is setup to 1s. Make this time delay not to be cpu speed dependent. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/uartlite.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
index 5f90ef24d475..dce27f34937e 100644
--- a/drivers/tty/serial/uartlite.c
+++ b/drivers/tty/serial/uartlite.c
@@ -418,14 +418,23 @@ static struct uart_ops ulite_ops = {
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
- int i;
u8 val;
-
- /* Spin waiting for TX fifo to have space available */
- for (i = 0; i < 100000; i++) {
+ unsigned long timeout;
+
+ /*
+ * Spin waiting for TX fifo to have space available.
+ * When using the Microblaze Debug Module this can take up to 1s
+ */
+ timeout = jiffies + msecs_to_jiffies(1000);
+ while (1) {
val = uart_in32(ULITE_STATUS, port);
if ((val & ULITE_STATUS_TXFULL) == 0)
break;
+ if (time_after(jiffies, timeout)) {
+ dev_warn(port->dev,
+ "timeout waiting for TX buffer empty\n");
+ break;
+ }
cpu_relax();
}
}