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author | Thomas Gleixner <tglx@linutronix.de> | 2019-02-23 17:21:53 +0100 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2019-02-23 17:21:53 +0100 |
commit | 8dd2eee2f444a7a570599bffc9da330157cca5b5 (patch) | |
tree | 400b9a2fb19e7ac5bac27750bdac77615eded541 /drivers/soc | |
parent | 75b710af7139768fd4ba2d4e05335d2344796279 (diff) | |
parent | f40f4fc9506d6b2b786920059b320aac3a831574 (diff) |
Merge branch 'clockevents/5.1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevents updates from Daniel Lezcano:
- Update the binding documentation for the gpt timer (Anson Huang)
- Improve checking and error handling at init time on risc timer (Atish
Patra)
- Update the binding documentation for r8a774c0 cmt and tmu (Biju Das)
- Fail gracefully when clock rate is unavailable on sun5i (Chen-Yu Tsai)
- Rename the tango-xtal, pxa and cs5535 to timer-*.c for consistency
(Daniel Lezcano)
- Add the support for the tegra210 timer and add the platform's Kconfig
selection (Joseph Lo)
- Do a cleanup in the header inclusions and remove the unused ones for the
exynos_mct timer driver (Krzysztof Kozlowski)
- Remove some non-of dead code and fix the error path when initializing
the resources in the exynos_mct timer driver (Marek Szyprowski)
- Update the DT bindings for the MT7629 (Ryder Lee)
- Provide a workaround for the arm arch timer for Allwinner A64 timers
(Samuel Holland)
- Clear the timer interrupt at shutdown time on the exynos_mct timer
driver (Stuart Menefy)
Diffstat (limited to 'drivers/soc')
-rw-r--r-- | drivers/soc/tegra/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index fe4481676da6..a0b03443d8c1 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC select PINCTRL_TEGRA210 select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select TEGRA_TIMER help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 |