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authorYifan Zha <Yifan.Zha@amd.com>2022-09-07 14:13:02 +0800
committerAlex Deucher <alexander.deucher@amd.com>2022-10-18 22:13:24 -0400
commit97a3d6090f5c2a165dc88bda05c1dcf9f08bf886 (patch)
treec2cbf6f3dd80c28263d8faa8fdfddb9c094ff8cf /drivers/sh
parente688ba3e276422aa88eae7a54186a95320836081 (diff)
drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11
[Why] L1 blocks most of GC registers accessing by MMIO. [How] Use RLCG interface to program GC registers under SRIOV VF in full access time. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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