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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2022-09-27 19:24:21 +0300
committerThierry Reding <thierry.reding@gmail.com>2022-09-28 16:21:46 +0200
commitd632e864351ac3df3ab4bb224ba27b0634ce93be (patch)
treecc61605b578e26acc3c8a67999e386fe2b240bd9 /drivers/pwm
parent4fdb3281bb8479ea0c41e6be0af5dcab669f9eb9 (diff)
pwm: lpss: Add a comment to the bypass field
Add a comment to the bypass field based on the commit b997e3edca4f ("pwm: lpss: Set enable-bit before waiting for update-bit to go low"). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
-rw-r--r--drivers/pwm/pwm-lpss.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
index c344921b2cab..8e82eb5a7e00 100644
--- a/drivers/pwm/pwm-lpss.h
+++ b/drivers/pwm/pwm-lpss.h
@@ -25,6 +25,11 @@ struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
+ /*
+ * Some versions of the IP may stuck in the state machine if enable
+ * bit is not set, and hence update bit will show busy status till
+ * the reset. For the rest it may be otherwise.
+ */
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device