diff options
| author | Manu Gautam <mgautam@codeaurora.org> | 2018-01-16 16:27:01 +0530 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2018-03-08 13:56:09 +0530 |
| commit | 76ddd300892a7e7c957c3ce0db5958c1c4866139 (patch) | |
| tree | 478d3b7b4710b9fd5272fb70a5993d57b49775ef /drivers/phy | |
| parent | c6549f0eefc4d492954af11421d359265c155a91 (diff) | |
phy: qcom-qmp: Move SERDES/PCS START after PHY reset
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index ecff2616dc84..edb6bbe95558 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -896,12 +896,12 @@ static int qcom_qmp_phy_init(struct phy *phy) if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; mask = cfg->mask_pcs_ready; |