diff options
| author | Chintan Vankar <c-vankar@ti.com> | 2023-12-21 15:59:55 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-12-22 21:20:08 +0530 |
| commit | d719915ad9706a16adde231789a1d46fc12fb9c7 (patch) | |
| tree | ed1450886998b262830abc6bdb848c2747a45caa /drivers/phy/ti | |
| parent | 2daa9555ba9858c29b9734b3a104c338b718feab (diff) | |
phy: ti: gmii-sel: Enable SGMII mode for J784S4
TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20231221102956.754617-1-c-vankar@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/ti')
| -rw-r--r-- | drivers/phy/ti/phy-gmii-sel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 555b323f45da..05004c8a758f 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -247,7 +247,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, |