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authorNiklas Cassel <niklas.cassel@axis.com>2018-03-28 13:50:16 +0200
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-04-03 12:38:06 +0100
commit96a3be43261b919a1785d080b501fae26ce97bc2 (patch)
tree41dde07313b0688007852ffdad58f1110bb76c7a /drivers/pci
parent6474a4e5546e1e3fbba5081dd201ebed62939278 (diff)
PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly
Since a 64-bit BAR consists of a BAR pair, we need to write to both BARs in the BAR pair to clear the BAR properly. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/dwc/pcie-designware-ep.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index c9bdb5f139b4..9164c9084b4e 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -28,6 +28,10 @@ static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
dw_pcie_dbi_ro_wr_en(pci);
dw_pcie_writel_dbi2(pci, reg, 0x0);
dw_pcie_writel_dbi(pci, reg, 0x0);
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
+ dw_pcie_writel_dbi(pci, reg + 4, 0x0);
+ }
dw_pcie_dbi_ro_wr_dis(pci);
}